Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.06 98.27 93.71 96.79 80.35 96.87 99.77 92.65


Total test records in report: 971
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T791 /workspace/coverage/default/129.edn_genbits.3142443182 Apr 18 02:26:29 PM PDT 24 Apr 18 02:26:31 PM PDT 24 48663026 ps
T792 /workspace/coverage/default/88.edn_err.4018581814 Apr 18 02:26:11 PM PDT 24 Apr 18 02:26:13 PM PDT 24 55421887 ps
T793 /workspace/coverage/default/20.edn_disable.1093718138 Apr 18 02:25:13 PM PDT 24 Apr 18 02:25:14 PM PDT 24 22749718 ps
T794 /workspace/coverage/default/2.edn_stress_all_with_rand_reset.779136801 Apr 18 02:24:35 PM PDT 24 Apr 18 02:53:18 PM PDT 24 152289576307 ps
T795 /workspace/coverage/default/76.edn_err.3848652216 Apr 18 02:26:10 PM PDT 24 Apr 18 02:26:11 PM PDT 24 57406736 ps
T33 /workspace/coverage/default/56.edn_err.3816403546 Apr 18 02:26:02 PM PDT 24 Apr 18 02:26:05 PM PDT 24 21450325 ps
T796 /workspace/coverage/default/223.edn_genbits.3174262713 Apr 18 02:26:40 PM PDT 24 Apr 18 02:26:42 PM PDT 24 53934459 ps
T797 /workspace/coverage/default/19.edn_genbits.4017162 Apr 18 02:25:13 PM PDT 24 Apr 18 02:25:15 PM PDT 24 42167516 ps
T798 /workspace/coverage/default/35.edn_disable_auto_req_mode.742345510 Apr 18 02:25:35 PM PDT 24 Apr 18 02:25:36 PM PDT 24 32504617 ps
T265 /workspace/coverage/default/59.edn_genbits.536876940 Apr 18 02:26:02 PM PDT 24 Apr 18 02:26:05 PM PDT 24 308709542 ps
T799 /workspace/coverage/default/93.edn_genbits.1771549869 Apr 18 02:26:20 PM PDT 24 Apr 18 02:26:21 PM PDT 24 180109276 ps
T800 /workspace/coverage/default/173.edn_genbits.2054965910 Apr 18 02:26:29 PM PDT 24 Apr 18 02:26:31 PM PDT 24 40987787 ps
T801 /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3627895793 Apr 18 02:24:44 PM PDT 24 Apr 18 02:40:56 PM PDT 24 171705640673 ps
T802 /workspace/coverage/default/86.edn_genbits.882429794 Apr 18 02:26:13 PM PDT 24 Apr 18 02:26:17 PM PDT 24 235465454 ps
T803 /workspace/coverage/default/199.edn_genbits.2622909844 Apr 18 02:26:34 PM PDT 24 Apr 18 02:26:36 PM PDT 24 33797234 ps
T804 /workspace/coverage/default/89.edn_err.205716523 Apr 18 02:26:12 PM PDT 24 Apr 18 02:26:14 PM PDT 24 25678401 ps
T805 /workspace/coverage/default/45.edn_smoke.2846085632 Apr 18 02:25:54 PM PDT 24 Apr 18 02:25:55 PM PDT 24 55689754 ps
T806 /workspace/coverage/default/29.edn_stress_all.498732374 Apr 18 02:25:22 PM PDT 24 Apr 18 02:25:25 PM PDT 24 462365392 ps
T807 /workspace/coverage/default/15.edn_stress_all.531983772 Apr 18 02:24:57 PM PDT 24 Apr 18 02:25:02 PM PDT 24 215322949 ps
T808 /workspace/coverage/default/184.edn_genbits.3389060218 Apr 18 02:26:34 PM PDT 24 Apr 18 02:26:36 PM PDT 24 57263365 ps
T809 /workspace/coverage/default/56.edn_genbits.2423442476 Apr 18 02:26:04 PM PDT 24 Apr 18 02:26:06 PM PDT 24 55878146 ps
T249 /workspace/coverage/default/42.edn_alert.1388696300 Apr 18 02:25:51 PM PDT 24 Apr 18 02:25:53 PM PDT 24 55318798 ps
T810 /workspace/coverage/default/283.edn_genbits.1685613586 Apr 18 02:26:43 PM PDT 24 Apr 18 02:26:45 PM PDT 24 186012966 ps
T811 /workspace/coverage/default/46.edn_disable_auto_req_mode.1441275382 Apr 18 02:25:52 PM PDT 24 Apr 18 02:25:54 PM PDT 24 50697011 ps
T812 /workspace/coverage/default/7.edn_err.640956248 Apr 18 02:24:39 PM PDT 24 Apr 18 02:24:41 PM PDT 24 20291430 ps
T813 /workspace/coverage/default/68.edn_err.3667546812 Apr 18 02:26:03 PM PDT 24 Apr 18 02:26:05 PM PDT 24 44740053 ps
T814 /workspace/coverage/default/37.edn_stress_all.1117538679 Apr 18 02:25:36 PM PDT 24 Apr 18 02:25:43 PM PDT 24 305676888 ps
T815 /workspace/coverage/default/81.edn_genbits.3194838965 Apr 18 02:26:07 PM PDT 24 Apr 18 02:26:11 PM PDT 24 226974249 ps
T816 /workspace/coverage/default/12.edn_smoke.1854536982 Apr 18 02:24:48 PM PDT 24 Apr 18 02:24:50 PM PDT 24 24077135 ps
T817 /workspace/coverage/default/219.edn_genbits.2732470052 Apr 18 02:26:41 PM PDT 24 Apr 18 02:26:43 PM PDT 24 33735278 ps
T818 /workspace/coverage/default/42.edn_err.3484576869 Apr 18 02:25:48 PM PDT 24 Apr 18 02:25:49 PM PDT 24 96407868 ps
T819 /workspace/coverage/default/6.edn_stress_all.2594831309 Apr 18 02:24:38 PM PDT 24 Apr 18 02:24:43 PM PDT 24 169679581 ps
T147 /workspace/coverage/default/23.edn_intr.3599366720 Apr 18 02:25:18 PM PDT 24 Apr 18 02:25:20 PM PDT 24 20219938 ps
T820 /workspace/coverage/default/47.edn_genbits.3858759749 Apr 18 02:25:56 PM PDT 24 Apr 18 02:25:59 PM PDT 24 38651647 ps
T821 /workspace/coverage/default/234.edn_genbits.573594181 Apr 18 02:26:39 PM PDT 24 Apr 18 02:26:41 PM PDT 24 47861451 ps
T822 /workspace/coverage/default/230.edn_genbits.1740083062 Apr 18 02:26:38 PM PDT 24 Apr 18 02:26:40 PM PDT 24 54046022 ps
T823 /workspace/coverage/default/35.edn_disable.2003967834 Apr 18 02:25:34 PM PDT 24 Apr 18 02:25:36 PM PDT 24 12256012 ps
T824 /workspace/coverage/default/22.edn_err.2718860051 Apr 18 02:25:20 PM PDT 24 Apr 18 02:25:22 PM PDT 24 18229791 ps
T825 /workspace/coverage/default/31.edn_disable.35722011 Apr 18 02:25:26 PM PDT 24 Apr 18 02:25:28 PM PDT 24 11106906 ps
T826 /workspace/coverage/default/49.edn_genbits.3950099469 Apr 18 02:25:59 PM PDT 24 Apr 18 02:26:01 PM PDT 24 92343271 ps
T827 /workspace/coverage/default/188.edn_genbits.2311005351 Apr 18 02:26:33 PM PDT 24 Apr 18 02:26:36 PM PDT 24 61977691 ps
T828 /workspace/coverage/default/53.edn_genbits.855011607 Apr 18 02:25:58 PM PDT 24 Apr 18 02:26:01 PM PDT 24 46856246 ps
T829 /workspace/coverage/default/29.edn_genbits.1563392915 Apr 18 02:25:20 PM PDT 24 Apr 18 02:25:22 PM PDT 24 21963762 ps
T830 /workspace/coverage/default/7.edn_intr.244213393 Apr 18 02:24:37 PM PDT 24 Apr 18 02:24:39 PM PDT 24 22563132 ps
T831 /workspace/coverage/default/9.edn_stress_all.2242837725 Apr 18 02:24:50 PM PDT 24 Apr 18 02:24:53 PM PDT 24 129875987 ps
T145 /workspace/coverage/default/26.edn_intr.3601073847 Apr 18 02:25:17 PM PDT 24 Apr 18 02:25:19 PM PDT 24 27146403 ps
T832 /workspace/coverage/default/42.edn_genbits.1732806608 Apr 18 02:25:45 PM PDT 24 Apr 18 02:25:47 PM PDT 24 155724917 ps
T833 /workspace/coverage/default/271.edn_genbits.117569909 Apr 18 02:26:45 PM PDT 24 Apr 18 02:26:47 PM PDT 24 73360853 ps
T834 /workspace/coverage/default/216.edn_genbits.2351024968 Apr 18 02:26:39 PM PDT 24 Apr 18 02:26:41 PM PDT 24 37186975 ps
T835 /workspace/coverage/default/49.edn_stress_all.1406616752 Apr 18 02:25:57 PM PDT 24 Apr 18 02:26:03 PM PDT 24 1312625929 ps
T836 /workspace/coverage/default/49.edn_alert_test.3723417310 Apr 18 02:26:08 PM PDT 24 Apr 18 02:26:09 PM PDT 24 14471826 ps
T837 /workspace/coverage/default/24.edn_disable.3873966287 Apr 18 02:25:14 PM PDT 24 Apr 18 02:25:15 PM PDT 24 38691354 ps
T34 /workspace/coverage/default/85.edn_err.2375321297 Apr 18 02:26:13 PM PDT 24 Apr 18 02:26:15 PM PDT 24 43365072 ps
T838 /workspace/coverage/default/14.edn_intr.3579913283 Apr 18 02:24:54 PM PDT 24 Apr 18 02:24:56 PM PDT 24 19774089 ps
T159 /workspace/coverage/default/36.edn_disable.3524485194 Apr 18 02:25:35 PM PDT 24 Apr 18 02:25:37 PM PDT 24 19453531 ps
T839 /workspace/coverage/default/44.edn_disable.2344284668 Apr 18 02:26:00 PM PDT 24 Apr 18 02:26:02 PM PDT 24 10957319 ps
T840 /workspace/coverage/cover_reg_top/12.edn_intr_test.2721032553 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:54 PM PDT 24 53528374 ps
T841 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3160501435 Apr 18 12:40:34 PM PDT 24 Apr 18 12:40:36 PM PDT 24 26811809 ps
T842 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2954874477 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:58 PM PDT 24 234513914 ps
T843 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1817054452 Apr 18 12:40:49 PM PDT 24 Apr 18 12:40:55 PM PDT 24 452912681 ps
T201 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3277636748 Apr 18 12:40:43 PM PDT 24 Apr 18 12:40:45 PM PDT 24 14310777 ps
T223 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.152417796 Apr 18 12:40:43 PM PDT 24 Apr 18 12:40:46 PM PDT 24 151138685 ps
T844 /workspace/coverage/cover_reg_top/23.edn_intr_test.129849602 Apr 18 12:41:10 PM PDT 24 Apr 18 12:41:13 PM PDT 24 50059647 ps
T202 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1100374810 Apr 18 12:40:38 PM PDT 24 Apr 18 12:40:40 PM PDT 24 13685195 ps
T845 /workspace/coverage/cover_reg_top/11.edn_intr_test.3343816412 Apr 18 12:40:45 PM PDT 24 Apr 18 12:40:46 PM PDT 24 138425700 ps
T219 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1805520971 Apr 18 12:40:44 PM PDT 24 Apr 18 12:40:46 PM PDT 24 78360880 ps
T846 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1559448740 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:54 PM PDT 24 24613789 ps
T847 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2525304807 Apr 18 12:40:49 PM PDT 24 Apr 18 12:40:51 PM PDT 24 47739257 ps
T220 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1389109242 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:54 PM PDT 24 13238415 ps
T203 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1100050858 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:53 PM PDT 24 19284222 ps
T204 /workspace/coverage/cover_reg_top/5.edn_csr_rw.485836013 Apr 18 12:41:57 PM PDT 24 Apr 18 12:41:59 PM PDT 24 44546550 ps
T848 /workspace/coverage/cover_reg_top/10.edn_tl_errors.4129906749 Apr 18 12:40:48 PM PDT 24 Apr 18 12:40:51 PM PDT 24 95966096 ps
T221 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3352368073 Apr 18 12:40:46 PM PDT 24 Apr 18 12:40:48 PM PDT 24 13401822 ps
T205 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3715443492 Apr 18 12:40:54 PM PDT 24 Apr 18 12:40:57 PM PDT 24 27182241 ps
T849 /workspace/coverage/cover_reg_top/40.edn_intr_test.2978554220 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:55 PM PDT 24 63476518 ps
T850 /workspace/coverage/cover_reg_top/2.edn_tl_errors.2151666405 Apr 18 12:40:35 PM PDT 24 Apr 18 12:40:41 PM PDT 24 120839800 ps
T206 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2083512887 Apr 18 12:40:35 PM PDT 24 Apr 18 12:40:39 PM PDT 24 114123961 ps
T224 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.421055410 Apr 18 12:40:42 PM PDT 24 Apr 18 12:40:45 PM PDT 24 304622250 ps
T851 /workspace/coverage/cover_reg_top/16.edn_tl_errors.150147716 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:55 PM PDT 24 30130653 ps
T852 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2748084407 Apr 18 12:40:49 PM PDT 24 Apr 18 12:40:52 PM PDT 24 20258273 ps
T853 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1025206571 Apr 18 12:41:07 PM PDT 24 Apr 18 12:41:09 PM PDT 24 64179251 ps
T854 /workspace/coverage/cover_reg_top/2.edn_intr_test.937521972 Apr 18 12:40:42 PM PDT 24 Apr 18 12:40:44 PM PDT 24 17397779 ps
T855 /workspace/coverage/cover_reg_top/8.edn_intr_test.3945921198 Apr 18 12:40:41 PM PDT 24 Apr 18 12:40:42 PM PDT 24 24555659 ps
T225 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.663321477 Apr 18 12:40:49 PM PDT 24 Apr 18 12:40:53 PM PDT 24 65065616 ps
T207 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2519489431 Apr 18 12:40:45 PM PDT 24 Apr 18 12:40:47 PM PDT 24 17013431 ps
T208 /workspace/coverage/cover_reg_top/9.edn_csr_rw.4145941954 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:53 PM PDT 24 40882577 ps
T856 /workspace/coverage/cover_reg_top/15.edn_tl_errors.782097380 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:56 PM PDT 24 350904534 ps
T209 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1219525251 Apr 18 12:41:15 PM PDT 24 Apr 18 12:41:17 PM PDT 24 27566486 ps
T226 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1771579660 Apr 18 12:40:37 PM PDT 24 Apr 18 12:40:39 PM PDT 24 222908642 ps
T857 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3051908142 Apr 18 12:40:30 PM PDT 24 Apr 18 12:40:34 PM PDT 24 227521020 ps
T858 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1537091877 Apr 18 12:40:55 PM PDT 24 Apr 18 12:40:58 PM PDT 24 449123585 ps
T859 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1265717092 Apr 18 12:40:45 PM PDT 24 Apr 18 12:40:46 PM PDT 24 36010983 ps
T860 /workspace/coverage/cover_reg_top/8.edn_tl_errors.2594956727 Apr 18 12:40:42 PM PDT 24 Apr 18 12:40:47 PM PDT 24 528681707 ps
T861 /workspace/coverage/cover_reg_top/17.edn_intr_test.309642847 Apr 18 12:40:46 PM PDT 24 Apr 18 12:40:48 PM PDT 24 14135712 ps
T862 /workspace/coverage/cover_reg_top/13.edn_intr_test.2463256351 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:55 PM PDT 24 80531873 ps
T863 /workspace/coverage/cover_reg_top/42.edn_intr_test.76246981 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:55 PM PDT 24 12880384 ps
T864 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1403657000 Apr 18 12:40:33 PM PDT 24 Apr 18 12:40:38 PM PDT 24 449606862 ps
T238 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3527692906 Apr 18 12:40:41 PM PDT 24 Apr 18 12:40:44 PM PDT 24 366482252 ps
T234 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2550112504 Apr 18 12:40:52 PM PDT 24 Apr 18 12:40:57 PM PDT 24 317047626 ps
T210 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3701437587 Apr 18 12:40:39 PM PDT 24 Apr 18 12:40:41 PM PDT 24 28666734 ps
T865 /workspace/coverage/cover_reg_top/18.edn_intr_test.2928223384 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:54 PM PDT 24 21121566 ps
T222 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.134947840 Apr 18 12:41:06 PM PDT 24 Apr 18 12:41:09 PM PDT 24 19488828 ps
T211 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3982024708 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:54 PM PDT 24 52168417 ps
T866 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3801289298 Apr 18 12:40:23 PM PDT 24 Apr 18 12:40:24 PM PDT 24 87022768 ps
T867 /workspace/coverage/cover_reg_top/3.edn_csr_rw.3913105224 Apr 18 12:40:39 PM PDT 24 Apr 18 12:40:41 PM PDT 24 15673365 ps
T868 /workspace/coverage/cover_reg_top/5.edn_intr_test.1832871963 Apr 18 12:40:43 PM PDT 24 Apr 18 12:40:45 PM PDT 24 18557591 ps
T869 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1962243934 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:54 PM PDT 24 20260953 ps
T870 /workspace/coverage/cover_reg_top/24.edn_intr_test.3686949168 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:52 PM PDT 24 118546938 ps
T239 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.790972548 Apr 18 12:40:52 PM PDT 24 Apr 18 12:40:56 PM PDT 24 151736199 ps
T871 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3048843795 Apr 18 12:40:36 PM PDT 24 Apr 18 12:40:42 PM PDT 24 175770410 ps
T872 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.965007475 Apr 18 12:40:31 PM PDT 24 Apr 18 12:40:32 PM PDT 24 30444128 ps
T873 /workspace/coverage/cover_reg_top/36.edn_intr_test.982130324 Apr 18 12:40:54 PM PDT 24 Apr 18 12:40:56 PM PDT 24 34023467 ps
T212 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2298208677 Apr 18 12:40:38 PM PDT 24 Apr 18 12:40:40 PM PDT 24 67799325 ps
T874 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3188792692 Apr 18 12:40:46 PM PDT 24 Apr 18 12:40:55 PM PDT 24 23052582 ps
T875 /workspace/coverage/cover_reg_top/10.edn_intr_test.4290245629 Apr 18 12:40:48 PM PDT 24 Apr 18 12:40:50 PM PDT 24 22522199 ps
T876 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.503619098 Apr 18 12:40:47 PM PDT 24 Apr 18 12:40:50 PM PDT 24 24871126 ps
T877 /workspace/coverage/cover_reg_top/2.edn_csr_rw.865559534 Apr 18 12:40:39 PM PDT 24 Apr 18 12:40:41 PM PDT 24 26370028 ps
T235 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3565599407 Apr 18 12:40:56 PM PDT 24 Apr 18 12:40:59 PM PDT 24 49610414 ps
T878 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3684860563 Apr 18 12:40:47 PM PDT 24 Apr 18 12:40:50 PM PDT 24 159958507 ps
T879 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1098492372 Apr 18 12:40:48 PM PDT 24 Apr 18 12:40:52 PM PDT 24 81522404 ps
T880 /workspace/coverage/cover_reg_top/0.edn_csr_rw.3909058492 Apr 18 12:40:42 PM PDT 24 Apr 18 12:40:44 PM PDT 24 16439533 ps
T213 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3639143270 Apr 18 12:40:43 PM PDT 24 Apr 18 12:40:45 PM PDT 24 64369122 ps
T881 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.676616096 Apr 18 12:40:45 PM PDT 24 Apr 18 12:40:46 PM PDT 24 18781422 ps
T882 /workspace/coverage/cover_reg_top/45.edn_intr_test.1433396943 Apr 18 12:40:58 PM PDT 24 Apr 18 12:41:00 PM PDT 24 14471853 ps
T883 /workspace/coverage/cover_reg_top/4.edn_intr_test.3736047025 Apr 18 12:40:45 PM PDT 24 Apr 18 12:40:48 PM PDT 24 25440570 ps
T884 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.282302770 Apr 18 12:40:37 PM PDT 24 Apr 18 12:40:39 PM PDT 24 40026740 ps
T885 /workspace/coverage/cover_reg_top/16.edn_intr_test.3266759392 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:54 PM PDT 24 31311557 ps
T886 /workspace/coverage/cover_reg_top/25.edn_intr_test.619188474 Apr 18 12:41:06 PM PDT 24 Apr 18 12:41:08 PM PDT 24 15749221 ps
T887 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.978995486 Apr 18 12:40:32 PM PDT 24 Apr 18 12:40:34 PM PDT 24 165388211 ps
T888 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3700728290 Apr 18 12:40:56 PM PDT 24 Apr 18 12:41:01 PM PDT 24 93962557 ps
T889 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4158343219 Apr 18 12:40:41 PM PDT 24 Apr 18 12:40:42 PM PDT 24 30435349 ps
T890 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1358054762 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:54 PM PDT 24 49314169 ps
T891 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.215498986 Apr 18 12:40:47 PM PDT 24 Apr 18 12:40:49 PM PDT 24 105868383 ps
T892 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3266663909 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:53 PM PDT 24 18528474 ps
T893 /workspace/coverage/cover_reg_top/31.edn_intr_test.855509081 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:54 PM PDT 24 30801718 ps
T894 /workspace/coverage/cover_reg_top/9.edn_intr_test.2400088639 Apr 18 12:40:47 PM PDT 24 Apr 18 12:40:49 PM PDT 24 19884513 ps
T895 /workspace/coverage/cover_reg_top/37.edn_intr_test.2698145850 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:53 PM PDT 24 10982511 ps
T896 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3919536364 Apr 18 12:40:46 PM PDT 24 Apr 18 12:40:49 PM PDT 24 202561715 ps
T897 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1861762292 Apr 18 12:40:41 PM PDT 24 Apr 18 12:40:42 PM PDT 24 58712328 ps
T898 /workspace/coverage/cover_reg_top/27.edn_intr_test.4060064984 Apr 18 12:40:52 PM PDT 24 Apr 18 12:40:55 PM PDT 24 22009201 ps
T899 /workspace/coverage/cover_reg_top/19.edn_intr_test.2916162229 Apr 18 12:41:01 PM PDT 24 Apr 18 12:41:02 PM PDT 24 19286850 ps
T900 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.42539800 Apr 18 12:40:43 PM PDT 24 Apr 18 12:40:45 PM PDT 24 32977714 ps
T901 /workspace/coverage/cover_reg_top/46.edn_intr_test.3374472031 Apr 18 12:40:57 PM PDT 24 Apr 18 12:40:59 PM PDT 24 14004343 ps
T902 /workspace/coverage/cover_reg_top/16.edn_csr_rw.2512574036 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:54 PM PDT 24 39644169 ps
T903 /workspace/coverage/cover_reg_top/43.edn_intr_test.657212160 Apr 18 12:41:03 PM PDT 24 Apr 18 12:41:05 PM PDT 24 18679669 ps
T904 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.525303740 Apr 18 12:40:52 PM PDT 24 Apr 18 12:40:56 PM PDT 24 40600959 ps
T905 /workspace/coverage/cover_reg_top/47.edn_intr_test.1665418690 Apr 18 12:41:07 PM PDT 24 Apr 18 12:41:09 PM PDT 24 200243585 ps
T906 /workspace/coverage/cover_reg_top/0.edn_intr_test.1969517551 Apr 18 12:40:35 PM PDT 24 Apr 18 12:40:37 PM PDT 24 13107329 ps
T907 /workspace/coverage/cover_reg_top/38.edn_intr_test.2642599366 Apr 18 12:40:49 PM PDT 24 Apr 18 12:40:52 PM PDT 24 14609201 ps
T908 /workspace/coverage/cover_reg_top/28.edn_intr_test.3440709378 Apr 18 12:40:52 PM PDT 24 Apr 18 12:40:56 PM PDT 24 13113496 ps
T909 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.791048752 Apr 18 12:40:43 PM PDT 24 Apr 18 12:40:45 PM PDT 24 75580720 ps
T910 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2023909934 Apr 18 12:40:38 PM PDT 24 Apr 18 12:40:42 PM PDT 24 94153767 ps
T911 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3428046832 Apr 18 12:40:49 PM PDT 24 Apr 18 12:40:52 PM PDT 24 19547547 ps
T912 /workspace/coverage/cover_reg_top/49.edn_intr_test.2968230837 Apr 18 12:41:05 PM PDT 24 Apr 18 12:41:07 PM PDT 24 44272199 ps
T913 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1373993685 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:54 PM PDT 24 17775978 ps
T914 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.4213908008 Apr 18 12:40:46 PM PDT 24 Apr 18 12:40:50 PM PDT 24 397274079 ps
T236 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3687582509 Apr 18 12:40:39 PM PDT 24 Apr 18 12:40:42 PM PDT 24 659640539 ps
T214 /workspace/coverage/cover_reg_top/7.edn_csr_rw.4112024301 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:55 PM PDT 24 11235838 ps
T215 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.344817809 Apr 18 12:40:33 PM PDT 24 Apr 18 12:40:35 PM PDT 24 22814329 ps
T915 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4263467995 Apr 18 12:40:45 PM PDT 24 Apr 18 12:40:49 PM PDT 24 193321333 ps
T916 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1030211027 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:55 PM PDT 24 151331135 ps
T917 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.4108869364 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:55 PM PDT 24 46037429 ps
T216 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.235708734 Apr 18 12:40:52 PM PDT 24 Apr 18 12:40:56 PM PDT 24 80415876 ps
T918 /workspace/coverage/cover_reg_top/20.edn_intr_test.2571253055 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:53 PM PDT 24 18600946 ps
T919 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1721345991 Apr 18 12:41:01 PM PDT 24 Apr 18 12:41:03 PM PDT 24 80805637 ps
T920 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.4120914955 Apr 18 12:40:46 PM PDT 24 Apr 18 12:40:48 PM PDT 24 33681546 ps
T921 /workspace/coverage/cover_reg_top/1.edn_intr_test.4180134709 Apr 18 12:40:27 PM PDT 24 Apr 18 12:40:29 PM PDT 24 14835506 ps
T922 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3386135804 Apr 18 12:40:40 PM PDT 24 Apr 18 12:40:41 PM PDT 24 35997100 ps
T923 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1083397640 Apr 18 12:40:45 PM PDT 24 Apr 18 12:40:47 PM PDT 24 15997930 ps
T924 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3793883117 Apr 18 12:40:48 PM PDT 24 Apr 18 12:40:51 PM PDT 24 51644028 ps
T925 /workspace/coverage/cover_reg_top/39.edn_intr_test.3675290793 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:55 PM PDT 24 27480045 ps
T926 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1030858610 Apr 18 12:40:48 PM PDT 24 Apr 18 12:40:50 PM PDT 24 543712127 ps
T927 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1629078242 Apr 18 12:40:53 PM PDT 24 Apr 18 12:40:57 PM PDT 24 47460766 ps
T928 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.330995433 Apr 18 12:40:37 PM PDT 24 Apr 18 12:40:40 PM PDT 24 20373045 ps
T929 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.280257109 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:54 PM PDT 24 359574442 ps
T217 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.81659239 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:53 PM PDT 24 82630746 ps
T930 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4117152838 Apr 18 12:40:47 PM PDT 24 Apr 18 12:40:51 PM PDT 24 223887911 ps
T931 /workspace/coverage/cover_reg_top/3.edn_intr_test.1888036667 Apr 18 12:40:45 PM PDT 24 Apr 18 12:40:46 PM PDT 24 35820513 ps
T932 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.215367803 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:52 PM PDT 24 36955482 ps
T933 /workspace/coverage/cover_reg_top/1.edn_csr_rw.4251950161 Apr 18 12:40:33 PM PDT 24 Apr 18 12:40:35 PM PDT 24 26180040 ps
T934 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3381362906 Apr 18 12:40:47 PM PDT 24 Apr 18 12:40:49 PM PDT 24 149604294 ps
T935 /workspace/coverage/cover_reg_top/44.edn_intr_test.3684058559 Apr 18 12:40:49 PM PDT 24 Apr 18 12:40:52 PM PDT 24 20996507 ps
T936 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3647069300 Apr 18 12:40:45 PM PDT 24 Apr 18 12:40:48 PM PDT 24 295493360 ps
T937 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1619171163 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:54 PM PDT 24 17659210 ps
T938 /workspace/coverage/cover_reg_top/32.edn_intr_test.1306226853 Apr 18 12:40:52 PM PDT 24 Apr 18 12:40:56 PM PDT 24 10704237 ps
T939 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3932708090 Apr 18 12:40:29 PM PDT 24 Apr 18 12:40:37 PM PDT 24 122670991 ps
T940 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2713692766 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:54 PM PDT 24 59194315 ps
T941 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3252676264 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:52 PM PDT 24 25493113 ps
T942 /workspace/coverage/cover_reg_top/22.edn_intr_test.3400000543 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:54 PM PDT 24 96312848 ps
T943 /workspace/coverage/cover_reg_top/26.edn_intr_test.1906742602 Apr 18 12:40:57 PM PDT 24 Apr 18 12:40:59 PM PDT 24 11380916 ps
T944 /workspace/coverage/cover_reg_top/35.edn_intr_test.4280601818 Apr 18 12:41:02 PM PDT 24 Apr 18 12:41:04 PM PDT 24 69219704 ps
T945 /workspace/coverage/cover_reg_top/15.edn_intr_test.393510593 Apr 18 12:40:48 PM PDT 24 Apr 18 12:40:50 PM PDT 24 11158439 ps
T946 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.574261468 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:55 PM PDT 24 20799224 ps
T947 /workspace/coverage/cover_reg_top/21.edn_intr_test.4165581139 Apr 18 12:40:49 PM PDT 24 Apr 18 12:40:52 PM PDT 24 51201263 ps
T218 /workspace/coverage/cover_reg_top/15.edn_csr_rw.4171382394 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:54 PM PDT 24 20650343 ps
T240 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3603030694 Apr 18 12:40:54 PM PDT 24 Apr 18 12:40:58 PM PDT 24 445409126 ps
T948 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1038421703 Apr 18 12:40:36 PM PDT 24 Apr 18 12:40:40 PM PDT 24 379831745 ps
T949 /workspace/coverage/cover_reg_top/7.edn_intr_test.527356645 Apr 18 12:40:41 PM PDT 24 Apr 18 12:40:43 PM PDT 24 24574213 ps
T950 /workspace/coverage/cover_reg_top/12.edn_tl_errors.984737692 Apr 18 12:40:43 PM PDT 24 Apr 18 12:40:48 PM PDT 24 278009643 ps
T951 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2729885631 Apr 18 12:40:51 PM PDT 24 Apr 18 12:41:01 PM PDT 24 1912084081 ps
T952 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3243414253 Apr 18 12:40:39 PM PDT 24 Apr 18 12:40:41 PM PDT 24 102305369 ps
T953 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3477878854 Apr 18 12:40:47 PM PDT 24 Apr 18 12:40:50 PM PDT 24 193314259 ps
T954 /workspace/coverage/cover_reg_top/14.edn_intr_test.4056734364 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:55 PM PDT 24 66610944 ps
T955 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3951023871 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:53 PM PDT 24 18969896 ps
T956 /workspace/coverage/cover_reg_top/41.edn_intr_test.3364527926 Apr 18 12:40:55 PM PDT 24 Apr 18 12:40:57 PM PDT 24 14655399 ps
T957 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1154633148 Apr 18 12:40:47 PM PDT 24 Apr 18 12:40:50 PM PDT 24 31862920 ps
T237 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1869319798 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:56 PM PDT 24 110453490 ps
T958 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1447072583 Apr 18 12:40:43 PM PDT 24 Apr 18 12:40:47 PM PDT 24 240222708 ps
T959 /workspace/coverage/cover_reg_top/30.edn_intr_test.2688686302 Apr 18 12:40:54 PM PDT 24 Apr 18 12:40:57 PM PDT 24 19153508 ps
T960 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3523905949 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:56 PM PDT 24 790633241 ps
T961 /workspace/coverage/cover_reg_top/33.edn_intr_test.3287060601 Apr 18 12:41:05 PM PDT 24 Apr 18 12:41:07 PM PDT 24 43166696 ps
T962 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2571811674 Apr 18 12:40:48 PM PDT 24 Apr 18 12:40:51 PM PDT 24 175639706 ps
T963 /workspace/coverage/cover_reg_top/29.edn_intr_test.3023883460 Apr 18 12:40:51 PM PDT 24 Apr 18 12:40:54 PM PDT 24 52116377 ps
T964 /workspace/coverage/cover_reg_top/14.edn_tl_errors.387089656 Apr 18 12:40:48 PM PDT 24 Apr 18 12:40:51 PM PDT 24 71439471 ps
T965 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3933665455 Apr 18 12:40:50 PM PDT 24 Apr 18 12:40:53 PM PDT 24 64917698 ps
T966 /workspace/coverage/cover_reg_top/6.edn_intr_test.3206690476 Apr 18 12:40:44 PM PDT 24 Apr 18 12:40:46 PM PDT 24 37950730 ps
T967 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3447612499 Apr 18 12:40:33 PM PDT 24 Apr 18 12:40:37 PM PDT 24 325854814 ps
T968 /workspace/coverage/cover_reg_top/34.edn_intr_test.850438217 Apr 18 12:40:53 PM PDT 24 Apr 18 12:40:56 PM PDT 24 17047154 ps
T969 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1177772838 Apr 18 12:40:42 PM PDT 24 Apr 18 12:40:44 PM PDT 24 280453388 ps
T970 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2727410935 Apr 18 12:40:49 PM PDT 24 Apr 18 12:40:52 PM PDT 24 131278030 ps
T971 /workspace/coverage/cover_reg_top/48.edn_intr_test.3732680392 Apr 18 12:40:52 PM PDT 24 Apr 18 12:40:56 PM PDT 24 52026581 ps

Test location /workspace/coverage/default/112.edn_genbits.2153167101
Short name T3
Test name
Test status
Simulation time 101963029 ps
CPU time 1.53 seconds
Started Apr 18 02:26:20 PM PDT 24
Finished Apr 18 02:26:22 PM PDT 24
Peak memory 217888 kb
Host smart-3f67cbba-d42e-4987-8b95-a1eafdbc6868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153167101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2153167101
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1573376544
Short name T109
Test name
Test status
Simulation time 66815257817 ps
CPU time 390.11 seconds
Started Apr 18 02:25:21 PM PDT 24
Finished Apr 18 02:31:52 PM PDT 24
Peak memory 218284 kb
Host smart-854313cb-aad2-4f76-b50c-62e0d5c7965f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573376544 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1573376544
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2058373478
Short name T1
Test name
Test status
Simulation time 45355388 ps
CPU time 1.43 seconds
Started Apr 18 02:25:14 PM PDT 24
Finished Apr 18 02:25:16 PM PDT 24
Peak memory 216236 kb
Host smart-c236154a-3ebd-4d7a-a23d-d2f992712bfd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058373478 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2058373478
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1650634102
Short name T94
Test name
Test status
Simulation time 376542217 ps
CPU time 6.09 seconds
Started Apr 18 02:24:27 PM PDT 24
Finished Apr 18 02:24:33 PM PDT 24
Peak memory 234276 kb
Host smart-cb95a391-8c4e-4531-8b27-78b2e09d16b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650634102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1650634102
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/32.edn_err.2519144107
Short name T4
Test name
Test status
Simulation time 35542151 ps
CPU time 0.87 seconds
Started Apr 18 02:25:32 PM PDT 24
Finished Apr 18 02:25:34 PM PDT 24
Peak memory 217348 kb
Host smart-9fb7c708-fd2c-450c-a454-dbf55b206c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519144107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2519144107
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/40.edn_alert.357600345
Short name T22
Test name
Test status
Simulation time 213688917 ps
CPU time 1.4 seconds
Started Apr 18 02:25:51 PM PDT 24
Finished Apr 18 02:25:53 PM PDT 24
Peak memory 215400 kb
Host smart-5ec3f09f-e5f7-4935-8454-66dbf26ef997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357600345 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.357600345
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/255.edn_genbits.4215311713
Short name T11
Test name
Test status
Simulation time 141527810 ps
CPU time 1.47 seconds
Started Apr 18 02:26:46 PM PDT 24
Finished Apr 18 02:26:48 PM PDT 24
Peak memory 217924 kb
Host smart-def2919b-bd3d-4921-b365-1a83ada395a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215311713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.4215311713
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_stress_all.1889560071
Short name T122
Test name
Test status
Simulation time 3226406423 ps
CPU time 4.74 seconds
Started Apr 18 02:25:21 PM PDT 24
Finished Apr 18 02:25:26 PM PDT 24
Peak memory 215148 kb
Host smart-57fc9804-633d-44c9-b62c-9f822437325c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889560071 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1889560071
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_alert.2938695397
Short name T21
Test name
Test status
Simulation time 30262372 ps
CPU time 1.29 seconds
Started Apr 18 02:25:18 PM PDT 24
Finished Apr 18 02:25:20 PM PDT 24
Peak memory 215400 kb
Host smart-8f825eb2-c567-4696-9f24-d9861afff8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938695397 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2938695397
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/43.edn_intr.908111888
Short name T19
Test name
Test status
Simulation time 21456312 ps
CPU time 1.06 seconds
Started Apr 18 02:25:54 PM PDT 24
Finished Apr 18 02:25:55 PM PDT 24
Peak memory 215456 kb
Host smart-d498bbd3-f32d-4645-9182-f99c08ccc48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908111888 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.908111888
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.2812545766
Short name T251
Test name
Test status
Simulation time 16928421 ps
CPU time 0.99 seconds
Started Apr 18 02:24:22 PM PDT 24
Finished Apr 18 02:24:24 PM PDT 24
Peak memory 206756 kb
Host smart-aba91dd2-b8f8-4f58-9e7e-ffe7a68bcd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812545766 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2812545766
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_err.2553199430
Short name T71
Test name
Test status
Simulation time 24312594 ps
CPU time 1.02 seconds
Started Apr 18 02:24:31 PM PDT 24
Finished Apr 18 02:24:32 PM PDT 24
Peak memory 217832 kb
Host smart-d310db2e-0001-4db4-ad94-52f25cb021fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553199430 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2553199430
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/11.edn_alert.3846991931
Short name T174
Test name
Test status
Simulation time 88363839 ps
CPU time 1.22 seconds
Started Apr 18 02:24:49 PM PDT 24
Finished Apr 18 02:24:51 PM PDT 24
Peak memory 215420 kb
Host smart-e5fdba09-73fd-40d6-9205-45612dee5844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846991931 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3846991931
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3687582509
Short name T236
Test name
Test status
Simulation time 659640539 ps
CPU time 2.18 seconds
Started Apr 18 12:40:39 PM PDT 24
Finished Apr 18 12:40:42 PM PDT 24
Peak memory 206076 kb
Host smart-bb9b4ecf-bc79-4f6d-893c-7f506b652e67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687582509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3687582509
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.240882664
Short name T184
Test name
Test status
Simulation time 275991365553 ps
CPU time 1705.79 seconds
Started Apr 18 02:24:25 PM PDT 24
Finished Apr 18 02:52:52 PM PDT 24
Peak memory 227228 kb
Host smart-d4ff9247-c798-413c-baad-186d5590afdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240882664 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.240882664
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1100374810
Short name T202
Test name
Test status
Simulation time 13685195 ps
CPU time 1.02 seconds
Started Apr 18 12:40:38 PM PDT 24
Finished Apr 18 12:40:40 PM PDT 24
Peak memory 206104 kb
Host smart-6ad82146-065e-405b-8b9c-fd7a82d191d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100374810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1100374810
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/default/14.edn_alert.4197222794
Short name T72
Test name
Test status
Simulation time 40402786 ps
CPU time 1.09 seconds
Started Apr 18 02:24:52 PM PDT 24
Finished Apr 18 02:24:54 PM PDT 24
Peak memory 215388 kb
Host smart-ce9ecdd5-943b-42c8-9fee-5b25d1728eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197222794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.4197222794
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/21.edn_disable.3258907148
Short name T20
Test name
Test status
Simulation time 32776377 ps
CPU time 0.89 seconds
Started Apr 18 02:25:27 PM PDT 24
Finished Apr 18 02:25:28 PM PDT 24
Peak memory 215672 kb
Host smart-30661764-f9c8-430e-aa1f-45e3646d0501
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258907148 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3258907148
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable.3665280537
Short name T88
Test name
Test status
Simulation time 14047452 ps
CPU time 0.98 seconds
Started Apr 18 02:24:51 PM PDT 24
Finished Apr 18 02:24:53 PM PDT 24
Peak memory 215828 kb
Host smart-c822fb05-d4bc-47f2-830b-510956d0643a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665280537 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3665280537
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.4224899133
Short name T50
Test name
Test status
Simulation time 167030431 ps
CPU time 1.1 seconds
Started Apr 18 02:25:19 PM PDT 24
Finished Apr 18 02:25:20 PM PDT 24
Peak memory 216332 kb
Host smart-aa5b1d95-aa12-4b99-a08f-5383f24bc61f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224899133 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.4224899133
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_intr.4216966687
Short name T146
Test name
Test status
Simulation time 26625333 ps
CPU time 0.81 seconds
Started Apr 18 02:25:21 PM PDT 24
Finished Apr 18 02:25:22 PM PDT 24
Peak memory 215304 kb
Host smart-6562731b-7c44-4dd7-9307-b8cf43edbb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216966687 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.4216966687
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/70.edn_genbits.621377447
Short name T137
Test name
Test status
Simulation time 29487753 ps
CPU time 1.33 seconds
Started Apr 18 02:26:03 PM PDT 24
Finished Apr 18 02:26:05 PM PDT 24
Peak memory 217644 kb
Host smart-68a345e1-5daa-4a89-b3d4-178e375550d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621377447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.621377447
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1497261742
Short name T43
Test name
Test status
Simulation time 44734794 ps
CPU time 0.98 seconds
Started Apr 18 02:25:35 PM PDT 24
Finished Apr 18 02:25:37 PM PDT 24
Peak memory 216224 kb
Host smart-fa7ffd54-3729-46dd-a8be-92a07693d61f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497261742 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1497261742
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/164.edn_genbits.678690121
Short name T358
Test name
Test status
Simulation time 141218539 ps
CPU time 3 seconds
Started Apr 18 02:26:29 PM PDT 24
Finished Apr 18 02:26:33 PM PDT 24
Peak memory 219324 kb
Host smart-ed2d0e20-d762-4ab4-bfe9-027ef42137b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678690121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.678690121
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_err.917356801
Short name T606
Test name
Test status
Simulation time 32593453 ps
CPU time 0.85 seconds
Started Apr 18 02:25:27 PM PDT 24
Finished Apr 18 02:25:29 PM PDT 24
Peak memory 214912 kb
Host smart-74201b7a-e64d-435b-9628-dccb26700c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917356801 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.917356801
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/116.edn_genbits.385473627
Short name T130
Test name
Test status
Simulation time 25277874 ps
CPU time 1.18 seconds
Started Apr 18 02:26:18 PM PDT 24
Finished Apr 18 02:26:20 PM PDT 24
Peak memory 216220 kb
Host smart-08eb0e44-47ff-48b5-ac00-f398e0219258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385473627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.385473627
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.1243803753
Short name T275
Test name
Test status
Simulation time 56347796 ps
CPU time 1.31 seconds
Started Apr 18 02:26:37 PM PDT 24
Finished Apr 18 02:26:38 PM PDT 24
Peak memory 217908 kb
Host smart-92201851-6032-4756-b741-d3570652c05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243803753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1243803753
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2436225038
Short name T227
Test name
Test status
Simulation time 25445826 ps
CPU time 1.26 seconds
Started Apr 18 02:25:27 PM PDT 24
Finished Apr 18 02:25:29 PM PDT 24
Peak memory 215468 kb
Host smart-6c5878fa-c2b5-4dd6-b800-6aa33e4b6c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436225038 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2436225038
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/36.edn_disable.3524485194
Short name T159
Test name
Test status
Simulation time 19453531 ps
CPU time 0.91 seconds
Started Apr 18 02:25:35 PM PDT 24
Finished Apr 18 02:25:37 PM PDT 24
Peak memory 215612 kb
Host smart-5d4fd373-83ea-470d-972b-2a016b9ba025
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524485194 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3524485194
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable.3871939031
Short name T164
Test name
Test status
Simulation time 14535287 ps
CPU time 0.93 seconds
Started Apr 18 02:24:30 PM PDT 24
Finished Apr 18 02:24:32 PM PDT 24
Peak memory 215716 kb
Host smart-fe7872ee-daa4-4a58-9132-b898a7622f75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871939031 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3871939031
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable.749254593
Short name T84
Test name
Test status
Simulation time 14321175 ps
CPU time 0.92 seconds
Started Apr 18 02:24:53 PM PDT 24
Finished Apr 18 02:24:54 PM PDT 24
Peak memory 215840 kb
Host smart-b1d7a152-c48d-4f08-b117-59c6303c0a47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749254593 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.749254593
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable.898705755
Short name T589
Test name
Test status
Simulation time 16112067 ps
CPU time 0.89 seconds
Started Apr 18 02:25:07 PM PDT 24
Finished Apr 18 02:25:08 PM PDT 24
Peak memory 215804 kb
Host smart-d056ca33-1c2c-4f59-a436-4f8b7b0be26c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898705755 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.898705755
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.389290422
Short name T31
Test name
Test status
Simulation time 51475176 ps
CPU time 1.14 seconds
Started Apr 18 02:25:05 PM PDT 24
Finished Apr 18 02:25:07 PM PDT 24
Peak memory 216388 kb
Host smart-b127f7c6-41b5-4ef5-863d-dd05038ed526
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389290422 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.389290422
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2699247057
Short name T30
Test name
Test status
Simulation time 67976255 ps
CPU time 1.37 seconds
Started Apr 18 02:25:19 PM PDT 24
Finished Apr 18 02:25:21 PM PDT 24
Peak memory 216088 kb
Host smart-e103c770-a687-44d1-8ae6-3d9d48dff1ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699247057 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2699247057
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3933550040
Short name T58
Test name
Test status
Simulation time 85346994 ps
CPU time 1.1 seconds
Started Apr 18 02:25:38 PM PDT 24
Finished Apr 18 02:25:39 PM PDT 24
Peak memory 216304 kb
Host smart-2c8571c0-af5a-4f1b-af36-756368a77081
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933550040 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3933550040
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/172.edn_genbits.3391928680
Short name T270
Test name
Test status
Simulation time 147161485 ps
CPU time 1.3 seconds
Started Apr 18 02:26:29 PM PDT 24
Finished Apr 18 02:26:31 PM PDT 24
Peak memory 216624 kb
Host smart-46924576-9624-492c-bae0-ce726e9b5f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391928680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3391928680
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_regwen.1456297610
Short name T100
Test name
Test status
Simulation time 45410483 ps
CPU time 0.92 seconds
Started Apr 18 02:24:33 PM PDT 24
Finished Apr 18 02:24:35 PM PDT 24
Peak memory 206820 kb
Host smart-5cc38146-e05a-47d1-8fd1-4696aefb73e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456297610 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1456297610
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_alert_test.2468196969
Short name T155
Test name
Test status
Simulation time 32527134 ps
CPU time 0.96 seconds
Started Apr 18 02:24:34 PM PDT 24
Finished Apr 18 02:24:36 PM PDT 24
Peak memory 206668 kb
Host smart-0591479d-8a37-406c-9aab-2ddd5d6ad778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468196969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2468196969
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_stress_all.1180210911
Short name T199
Test name
Test status
Simulation time 709147773 ps
CPU time 3.58 seconds
Started Apr 18 02:24:25 PM PDT 24
Finished Apr 18 02:24:29 PM PDT 24
Peak memory 215000 kb
Host smart-987e1e8c-c1e4-411d-87ef-c6be6c881284
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180210911 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1180210911
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_alert.1730407475
Short name T243
Test name
Test status
Simulation time 65761868 ps
CPU time 1.14 seconds
Started Apr 18 02:25:03 PM PDT 24
Finished Apr 18 02:25:05 PM PDT 24
Peak memory 215396 kb
Host smart-34b34648-5a2b-4668-b8b8-a84074f02857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730407475 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1730407475
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert.3583399127
Short name T229
Test name
Test status
Simulation time 86408778 ps
CPU time 1.06 seconds
Started Apr 18 02:25:22 PM PDT 24
Finished Apr 18 02:25:24 PM PDT 24
Peak memory 215404 kb
Host smart-bf195ee9-da80-41dd-ba35-bb047cf64709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583399127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3583399127
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/18.edn_intr.3566179189
Short name T105
Test name
Test status
Simulation time 75389880 ps
CPU time 0.86 seconds
Started Apr 18 02:25:03 PM PDT 24
Finished Apr 18 02:25:04 PM PDT 24
Peak memory 215316 kb
Host smart-8a2e3bdb-c7e1-48cf-9f43-b723dd6a9d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566179189 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3566179189
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/196.edn_genbits.2617854061
Short name T260
Test name
Test status
Simulation time 44770074 ps
CPU time 1.49 seconds
Started Apr 18 02:26:35 PM PDT 24
Finished Apr 18 02:26:37 PM PDT 24
Peak memory 217484 kb
Host smart-4acfd9c4-389c-4f0c-9b3c-75292547bf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617854061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2617854061
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3411564991
Short name T180
Test name
Test status
Simulation time 93363617 ps
CPU time 1.17 seconds
Started Apr 18 02:25:12 PM PDT 24
Finished Apr 18 02:25:14 PM PDT 24
Peak memory 215420 kb
Host smart-51b95810-41ac-4bdc-9faa-5e7f921ad995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411564991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3411564991
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/48.edn_err.1507078186
Short name T45
Test name
Test status
Simulation time 35667204 ps
CPU time 1.37 seconds
Started Apr 18 02:25:59 PM PDT 24
Finished Apr 18 02:26:02 PM PDT 24
Peak memory 233276 kb
Host smart-5e70cb3f-7446-4bf6-99a5-656b0f9efebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507078186 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1507078186
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3982024708
Short name T211
Test name
Test status
Simulation time 52168417 ps
CPU time 0.86 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:54 PM PDT 24
Peak memory 205984 kb
Host smart-3d799d56-15c9-4353-a4c1-3f0b8827615f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982024708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3982024708
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.4171382394
Short name T218
Test name
Test status
Simulation time 20650343 ps
CPU time 0.83 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:54 PM PDT 24
Peak memory 205956 kb
Host smart-2b0f94b9-c28b-439b-b5c5-6164f984d937
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171382394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.4171382394
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/default/1.edn_genbits.1563696527
Short name T284
Test name
Test status
Simulation time 242185064 ps
CPU time 2 seconds
Started Apr 18 02:24:38 PM PDT 24
Finished Apr 18 02:24:42 PM PDT 24
Peak memory 217772 kb
Host smart-eb90b599-148b-4a4c-8956-9b0c7c72bf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563696527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1563696527
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1976506278
Short name T269
Test name
Test status
Simulation time 69303727 ps
CPU time 1.51 seconds
Started Apr 18 02:26:16 PM PDT 24
Finished Apr 18 02:26:19 PM PDT 24
Peak memory 217924 kb
Host smart-9c552e4d-45ed-45e1-b399-051dbeb1cec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976506278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1976506278
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.252567370
Short name T282
Test name
Test status
Simulation time 42666886 ps
CPU time 1.07 seconds
Started Apr 18 02:26:16 PM PDT 24
Finished Apr 18 02:26:18 PM PDT 24
Peak memory 214868 kb
Host smart-030104ea-f133-4eac-938d-220fd800a28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252567370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.252567370
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.3326034775
Short name T532
Test name
Test status
Simulation time 28658295 ps
CPU time 1.28 seconds
Started Apr 18 02:26:18 PM PDT 24
Finished Apr 18 02:26:19 PM PDT 24
Peak memory 218744 kb
Host smart-00262dcf-ca01-4380-b773-4624f4f05a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326034775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3326034775
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.3702485343
Short name T276
Test name
Test status
Simulation time 81003990 ps
CPU time 1.13 seconds
Started Apr 18 02:26:20 PM PDT 24
Finished Apr 18 02:26:22 PM PDT 24
Peak memory 217620 kb
Host smart-2a5940e7-57a7-466a-876a-151920c3a7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702485343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3702485343
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.790364530
Short name T649
Test name
Test status
Simulation time 65685717 ps
CPU time 1.3 seconds
Started Apr 18 02:26:32 PM PDT 24
Finished Apr 18 02:26:33 PM PDT 24
Peak memory 216520 kb
Host smart-7bb4c728-70f7-4656-acbe-50548944b72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790364530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.790364530
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.397966122
Short name T263
Test name
Test status
Simulation time 93180798 ps
CPU time 1.37 seconds
Started Apr 18 02:26:42 PM PDT 24
Finished Apr 18 02:26:45 PM PDT 24
Peak memory 218900 kb
Host smart-e6a0d3e8-2102-48bd-95d8-e62a0dbe7848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397966122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.397966122
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_genbits.2651802145
Short name T266
Test name
Test status
Simulation time 251431608 ps
CPU time 1.35 seconds
Started Apr 18 02:25:26 PM PDT 24
Finished Apr 18 02:25:29 PM PDT 24
Peak memory 216548 kb
Host smart-ddd0f0af-ac9e-4445-9116-4a9adb387ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651802145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2651802145
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/280.edn_genbits.237162949
Short name T288
Test name
Test status
Simulation time 60522654 ps
CPU time 2.16 seconds
Started Apr 18 02:26:51 PM PDT 24
Finished Apr 18 02:26:55 PM PDT 24
Peak memory 217728 kb
Host smart-188f9bb2-88e7-4ce6-b238-1d685c76febb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237162949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.237162949
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1576065772
Short name T757
Test name
Test status
Simulation time 42399666 ps
CPU time 1.26 seconds
Started Apr 18 02:24:38 PM PDT 24
Finished Apr 18 02:24:41 PM PDT 24
Peak memory 215332 kb
Host smart-2efa510a-ae3d-4b4d-90c0-bdc1806274f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576065772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1576065772
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/59.edn_genbits.536876940
Short name T265
Test name
Test status
Simulation time 308709542 ps
CPU time 1.9 seconds
Started Apr 18 02:26:02 PM PDT 24
Finished Apr 18 02:26:05 PM PDT 24
Peak memory 217804 kb
Host smart-5184052f-9d0b-44f6-bf8e-aa8d4f0fe9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536876940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.536876940
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.4043141640
Short name T107
Test name
Test status
Simulation time 31164191 ps
CPU time 0.89 seconds
Started Apr 18 02:25:10 PM PDT 24
Finished Apr 18 02:25:11 PM PDT 24
Peak memory 215292 kb
Host smart-93ba89de-5373-424c-8e5d-77d7e262a1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043141640 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.4043141640
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/0.edn_alert.96363329
Short name T177
Test name
Test status
Simulation time 26434297 ps
CPU time 1.29 seconds
Started Apr 18 02:24:30 PM PDT 24
Finished Apr 18 02:24:32 PM PDT 24
Peak memory 215424 kb
Host smart-f19007bc-8d82-4f6d-a6ae-2f7ad6b38e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96363329 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.96363329
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable.431844444
Short name T2
Test name
Test status
Simulation time 14289176 ps
CPU time 0.84 seconds
Started Apr 18 02:24:28 PM PDT 24
Finished Apr 18 02:24:29 PM PDT 24
Peak memory 215076 kb
Host smart-4fd027e5-7bfb-4eb9-a16e-2b57929a4a0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431844444 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.431844444
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.330995433
Short name T928
Test name
Test status
Simulation time 20373045 ps
CPU time 1.32 seconds
Started Apr 18 12:40:37 PM PDT 24
Finished Apr 18 12:40:40 PM PDT 24
Peak memory 206048 kb
Host smart-e5ae9864-a982-42d7-9845-a0c5e49bdfce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330995433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.330995433
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3048843795
Short name T871
Test name
Test status
Simulation time 175770410 ps
CPU time 5.16 seconds
Started Apr 18 12:40:36 PM PDT 24
Finished Apr 18 12:40:42 PM PDT 24
Peak memory 206136 kb
Host smart-d4389092-fc04-418c-8210-06e85c47ef90
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048843795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3048843795
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3701437587
Short name T210
Test name
Test status
Simulation time 28666734 ps
CPU time 0.88 seconds
Started Apr 18 12:40:39 PM PDT 24
Finished Apr 18 12:40:41 PM PDT 24
Peak memory 205916 kb
Host smart-0c1ffd66-3485-4c93-b5d3-0a9c0fc85dbc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701437587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3701437587
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3243414253
Short name T952
Test name
Test status
Simulation time 102305369 ps
CPU time 1.27 seconds
Started Apr 18 12:40:39 PM PDT 24
Finished Apr 18 12:40:41 PM PDT 24
Peak memory 214332 kb
Host smart-ffc7443f-9d10-4570-9208-3ffcba8c7365
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243414253 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3243414253
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3909058492
Short name T880
Test name
Test status
Simulation time 16439533 ps
CPU time 0.88 seconds
Started Apr 18 12:40:42 PM PDT 24
Finished Apr 18 12:40:44 PM PDT 24
Peak memory 205908 kb
Host smart-c361a02c-7dae-4406-8a71-9c1e6b9662c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909058492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3909058492
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1969517551
Short name T906
Test name
Test status
Simulation time 13107329 ps
CPU time 0.86 seconds
Started Apr 18 12:40:35 PM PDT 24
Finished Apr 18 12:40:37 PM PDT 24
Peak memory 205936 kb
Host smart-1a05d0a0-095b-4d5e-b3a8-77d3bee99037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969517551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1969517551
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.965007475
Short name T872
Test name
Test status
Simulation time 30444128 ps
CPU time 1.13 seconds
Started Apr 18 12:40:31 PM PDT 24
Finished Apr 18 12:40:32 PM PDT 24
Peak memory 206048 kb
Host smart-0706cf35-6506-4aa0-9dad-b7a1cac50938
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965007475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.965007475
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3477878854
Short name T953
Test name
Test status
Simulation time 193314259 ps
CPU time 1.95 seconds
Started Apr 18 12:40:47 PM PDT 24
Finished Apr 18 12:40:50 PM PDT 24
Peak memory 214392 kb
Host smart-9dca725a-a2d9-4c3d-8dfd-6a6fa9ec701f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477878854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3477878854
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3932708090
Short name T939
Test name
Test status
Simulation time 122670991 ps
CPU time 1.69 seconds
Started Apr 18 12:40:29 PM PDT 24
Finished Apr 18 12:40:37 PM PDT 24
Peak memory 206048 kb
Host smart-971fb249-f8c9-42f5-8946-b3f1bb4f09f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932708090 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3932708090
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.81659239
Short name T217
Test name
Test status
Simulation time 82630746 ps
CPU time 1.61 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:53 PM PDT 24
Peak memory 206060 kb
Host smart-3596d702-6324-4d73-ba48-a69737c1a73f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81659239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.81659239
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2023909934
Short name T910
Test name
Test status
Simulation time 94153767 ps
CPU time 2.98 seconds
Started Apr 18 12:40:38 PM PDT 24
Finished Apr 18 12:40:42 PM PDT 24
Peak memory 206088 kb
Host smart-8b967b06-6531-4b48-b109-0062ff3fd610
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023909934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2023909934
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3801289298
Short name T866
Test name
Test status
Simulation time 87022768 ps
CPU time 0.85 seconds
Started Apr 18 12:40:23 PM PDT 24
Finished Apr 18 12:40:24 PM PDT 24
Peak memory 205908 kb
Host smart-f8ac5169-b91a-4f46-88db-a2fff3ee4e91
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801289298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3801289298
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4158343219
Short name T889
Test name
Test status
Simulation time 30435349 ps
CPU time 1.04 seconds
Started Apr 18 12:40:41 PM PDT 24
Finished Apr 18 12:40:42 PM PDT 24
Peak memory 214256 kb
Host smart-6d3ba971-c025-4a3a-ac76-519be8a15570
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158343219 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.4158343219
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.4251950161
Short name T933
Test name
Test status
Simulation time 26180040 ps
CPU time 0.92 seconds
Started Apr 18 12:40:33 PM PDT 24
Finished Apr 18 12:40:35 PM PDT 24
Peak memory 206008 kb
Host smart-fc1b792c-ea97-441c-b615-6cd5e2992ea8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251950161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.4251950161
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.4180134709
Short name T921
Test name
Test status
Simulation time 14835506 ps
CPU time 0.92 seconds
Started Apr 18 12:40:27 PM PDT 24
Finished Apr 18 12:40:29 PM PDT 24
Peak memory 205948 kb
Host smart-07f6aca9-eaf7-43d9-9622-c318a46dc096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180134709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.4180134709
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.282302770
Short name T884
Test name
Test status
Simulation time 40026740 ps
CPU time 1.13 seconds
Started Apr 18 12:40:37 PM PDT 24
Finished Apr 18 12:40:39 PM PDT 24
Peak memory 206080 kb
Host smart-3838e25c-6e57-495a-907a-7e8e3231814e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282302770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.282302770
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3051908142
Short name T857
Test name
Test status
Simulation time 227521020 ps
CPU time 4.08 seconds
Started Apr 18 12:40:30 PM PDT 24
Finished Apr 18 12:40:34 PM PDT 24
Peak memory 214284 kb
Host smart-f0ef126a-b87e-4eb3-adaf-d645ddc9e840
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051908142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3051908142
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3447612499
Short name T967
Test name
Test status
Simulation time 325854814 ps
CPU time 2.32 seconds
Started Apr 18 12:40:33 PM PDT 24
Finished Apr 18 12:40:37 PM PDT 24
Peak memory 214288 kb
Host smart-78b0631a-2cdd-412f-9f99-9705cf1d61ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447612499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3447612499
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1559448740
Short name T846
Test name
Test status
Simulation time 24613789 ps
CPU time 1.21 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:54 PM PDT 24
Peak memory 214392 kb
Host smart-97cae8d4-0f3d-4584-9466-874ba5b4bf17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559448740 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1559448740
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.4290245629
Short name T875
Test name
Test status
Simulation time 22522199 ps
CPU time 0.85 seconds
Started Apr 18 12:40:48 PM PDT 24
Finished Apr 18 12:40:50 PM PDT 24
Peak memory 205960 kb
Host smart-1f9eac72-d317-4d75-b092-64b4e4633d33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290245629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.4290245629
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1100050858
Short name T203
Test name
Test status
Simulation time 19284222 ps
CPU time 1.12 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:53 PM PDT 24
Peak memory 206040 kb
Host smart-0d408a19-a4ba-4ed3-bc03-e914f8b15202
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100050858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1100050858
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.4129906749
Short name T848
Test name
Test status
Simulation time 95966096 ps
CPU time 1.76 seconds
Started Apr 18 12:40:48 PM PDT 24
Finished Apr 18 12:40:51 PM PDT 24
Peak memory 214368 kb
Host smart-eb3a7c3c-5782-4d65-b8b4-279f28b0a05e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129906749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.4129906749
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.421055410
Short name T224
Test name
Test status
Simulation time 304622250 ps
CPU time 1.65 seconds
Started Apr 18 12:40:42 PM PDT 24
Finished Apr 18 12:40:45 PM PDT 24
Peak memory 214376 kb
Host smart-c9d923f4-b35a-4a73-ae54-afcd565f8002
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421055410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.421055410
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3428046832
Short name T911
Test name
Test status
Simulation time 19547547 ps
CPU time 1.26 seconds
Started Apr 18 12:40:49 PM PDT 24
Finished Apr 18 12:40:52 PM PDT 24
Peak memory 214356 kb
Host smart-1a9afb71-be69-4e18-b20c-ce4136786f3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428046832 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3428046832
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3639143270
Short name T213
Test name
Test status
Simulation time 64369122 ps
CPU time 0.85 seconds
Started Apr 18 12:40:43 PM PDT 24
Finished Apr 18 12:40:45 PM PDT 24
Peak memory 205648 kb
Host smart-8106b113-8511-4075-bca8-a6adad03130e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639143270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3639143270
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3343816412
Short name T845
Test name
Test status
Simulation time 138425700 ps
CPU time 0.82 seconds
Started Apr 18 12:40:45 PM PDT 24
Finished Apr 18 12:40:46 PM PDT 24
Peak memory 206024 kb
Host smart-a89fe77e-83de-4b6f-8e7b-e91bd90cf3b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343816412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3343816412
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.215367803
Short name T932
Test name
Test status
Simulation time 36955482 ps
CPU time 0.98 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:52 PM PDT 24
Peak memory 206156 kb
Host smart-63bcb7d4-036e-49f5-8de0-0537d9cf461b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215367803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.215367803
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3647069300
Short name T936
Test name
Test status
Simulation time 295493360 ps
CPU time 2.68 seconds
Started Apr 18 12:40:45 PM PDT 24
Finished Apr 18 12:40:48 PM PDT 24
Peak memory 214364 kb
Host smart-8324be0f-85c6-4cfc-8844-cd81b7feb975
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647069300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3647069300
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3793883117
Short name T924
Test name
Test status
Simulation time 51644028 ps
CPU time 1.61 seconds
Started Apr 18 12:40:48 PM PDT 24
Finished Apr 18 12:40:51 PM PDT 24
Peak memory 206012 kb
Host smart-10d05a73-daab-4a25-9917-40c00e3c67f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793883117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3793883117
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1629078242
Short name T927
Test name
Test status
Simulation time 47460766 ps
CPU time 1.63 seconds
Started Apr 18 12:40:53 PM PDT 24
Finished Apr 18 12:40:57 PM PDT 24
Peak memory 214368 kb
Host smart-3738114b-5f1a-4abb-bd06-3217741c27e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629078242 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1629078242
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1373993685
Short name T913
Test name
Test status
Simulation time 17775978 ps
CPU time 0.78 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:54 PM PDT 24
Peak memory 205972 kb
Host smart-f1da2a45-9e9e-4d7c-9389-8669be4c9f8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373993685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1373993685
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2721032553
Short name T840
Test name
Test status
Simulation time 53528374 ps
CPU time 0.89 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:54 PM PDT 24
Peak memory 205920 kb
Host smart-5546682f-9eea-4047-acda-de804d9cd13c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721032553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2721032553
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.280257109
Short name T929
Test name
Test status
Simulation time 359574442 ps
CPU time 1.29 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:54 PM PDT 24
Peak memory 206132 kb
Host smart-bc4c0274-5028-4e4c-9f39-fc5d52ebb965
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280257109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.280257109
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.984737692
Short name T950
Test name
Test status
Simulation time 278009643 ps
CPU time 4.62 seconds
Started Apr 18 12:40:43 PM PDT 24
Finished Apr 18 12:40:48 PM PDT 24
Peak memory 214324 kb
Host smart-3c25042d-9fa4-4b61-86b7-347a4a044e82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984737692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.984737692
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.663321477
Short name T225
Test name
Test status
Simulation time 65065616 ps
CPU time 1.71 seconds
Started Apr 18 12:40:49 PM PDT 24
Finished Apr 18 12:40:53 PM PDT 24
Peak memory 206264 kb
Host smart-8be0149c-fde3-4763-89ce-275dfc530308
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663321477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.663321477
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.525303740
Short name T904
Test name
Test status
Simulation time 40600959 ps
CPU time 1.14 seconds
Started Apr 18 12:40:52 PM PDT 24
Finished Apr 18 12:40:56 PM PDT 24
Peak memory 213984 kb
Host smart-fc9eb9ae-2819-447d-b27b-4de00fb97de5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525303740 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.525303740
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1389109242
Short name T220
Test name
Test status
Simulation time 13238415 ps
CPU time 0.88 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:54 PM PDT 24
Peak memory 206052 kb
Host smart-7ddba573-273e-49e8-b475-9f86d84125b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389109242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1389109242
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2463256351
Short name T862
Test name
Test status
Simulation time 80531873 ps
CPU time 0.84 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:55 PM PDT 24
Peak memory 205976 kb
Host smart-d96bc7ea-0dca-446a-804e-a81eecc12fc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463256351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2463256351
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3933665455
Short name T965
Test name
Test status
Simulation time 64917698 ps
CPU time 1.38 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:53 PM PDT 24
Peak memory 206112 kb
Host smart-8bf304bc-b041-4832-8088-219bf4731f85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933665455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3933665455
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1098492372
Short name T879
Test name
Test status
Simulation time 81522404 ps
CPU time 3.15 seconds
Started Apr 18 12:40:48 PM PDT 24
Finished Apr 18 12:40:52 PM PDT 24
Peak memory 214632 kb
Host smart-846d2af1-11ae-4dba-b6e1-0bb88ef649dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098492372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1098492372
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.4213908008
Short name T914
Test name
Test status
Simulation time 397274079 ps
CPU time 2.61 seconds
Started Apr 18 12:40:46 PM PDT 24
Finished Apr 18 12:40:50 PM PDT 24
Peak memory 214264 kb
Host smart-e97e9667-818a-454f-a796-f30e7492dd70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213908008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.4213908008
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2525304807
Short name T847
Test name
Test status
Simulation time 47739257 ps
CPU time 0.93 seconds
Started Apr 18 12:40:49 PM PDT 24
Finished Apr 18 12:40:51 PM PDT 24
Peak memory 206088 kb
Host smart-ad41e026-61ba-4fbe-ba5a-669c27bf2aa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525304807 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2525304807
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1265717092
Short name T859
Test name
Test status
Simulation time 36010983 ps
CPU time 0.81 seconds
Started Apr 18 12:40:45 PM PDT 24
Finished Apr 18 12:40:46 PM PDT 24
Peak memory 205908 kb
Host smart-dbc40dcc-1b36-4a37-a896-d310af15ede3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265717092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1265717092
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.4056734364
Short name T954
Test name
Test status
Simulation time 66610944 ps
CPU time 0.79 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:55 PM PDT 24
Peak memory 205932 kb
Host smart-eacab8a5-d5cb-4045-a843-7b6dc1470255
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056734364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.4056734364
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1219525251
Short name T209
Test name
Test status
Simulation time 27566486 ps
CPU time 0.96 seconds
Started Apr 18 12:41:15 PM PDT 24
Finished Apr 18 12:41:17 PM PDT 24
Peak memory 206080 kb
Host smart-f00e603c-885b-4884-bf0c-0cd96bd879ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219525251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1219525251
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.387089656
Short name T964
Test name
Test status
Simulation time 71439471 ps
CPU time 1.52 seconds
Started Apr 18 12:40:48 PM PDT 24
Finished Apr 18 12:40:51 PM PDT 24
Peak memory 214320 kb
Host smart-90508c99-c40a-4603-af11-487ca39f6489
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387089656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.387089656
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2550112504
Short name T234
Test name
Test status
Simulation time 317047626 ps
CPU time 2.31 seconds
Started Apr 18 12:40:52 PM PDT 24
Finished Apr 18 12:40:57 PM PDT 24
Peak memory 206124 kb
Host smart-5fe3dde6-897b-4c77-aacc-c4b25f8082d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550112504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2550112504
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2713692766
Short name T940
Test name
Test status
Simulation time 59194315 ps
CPU time 1.37 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:54 PM PDT 24
Peak memory 214532 kb
Host smart-51fc570c-2379-4b0b-832f-8280fdd4ec6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713692766 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2713692766
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.393510593
Short name T945
Test name
Test status
Simulation time 11158439 ps
CPU time 0.84 seconds
Started Apr 18 12:40:48 PM PDT 24
Finished Apr 18 12:40:50 PM PDT 24
Peak memory 205880 kb
Host smart-9c47fd9f-ca79-4677-9507-b2f0109e690c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393510593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.393510593
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1030858610
Short name T926
Test name
Test status
Simulation time 543712127 ps
CPU time 1.63 seconds
Started Apr 18 12:40:48 PM PDT 24
Finished Apr 18 12:40:50 PM PDT 24
Peak memory 206060 kb
Host smart-faf873d6-3007-4285-956c-d08b3730f8e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030858610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1030858610
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.782097380
Short name T856
Test name
Test status
Simulation time 350904534 ps
CPU time 3.37 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:56 PM PDT 24
Peak memory 214528 kb
Host smart-f0dbc35a-590b-4cc6-9264-2c71eed74c3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782097380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.782097380
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4263467995
Short name T915
Test name
Test status
Simulation time 193321333 ps
CPU time 3.65 seconds
Started Apr 18 12:40:45 PM PDT 24
Finished Apr 18 12:40:49 PM PDT 24
Peak memory 206416 kb
Host smart-4ef519d5-cc33-4061-8349-9c5bc66c5ee9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263467995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.4263467995
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3188792692
Short name T874
Test name
Test status
Simulation time 23052582 ps
CPU time 1.4 seconds
Started Apr 18 12:40:46 PM PDT 24
Finished Apr 18 12:40:55 PM PDT 24
Peak memory 214348 kb
Host smart-4d020fb9-8a2d-4433-b87f-4cad66bf2fba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188792692 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3188792692
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2512574036
Short name T902
Test name
Test status
Simulation time 39644169 ps
CPU time 0.85 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:54 PM PDT 24
Peak memory 205992 kb
Host smart-015fe61d-d6c9-4bd3-854d-3d17bb563156
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512574036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2512574036
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3266759392
Short name T885
Test name
Test status
Simulation time 31311557 ps
CPU time 0.85 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:54 PM PDT 24
Peak memory 205988 kb
Host smart-68c47bfc-ab6d-493c-96ac-21e956032f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266759392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3266759392
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3951023871
Short name T955
Test name
Test status
Simulation time 18969896 ps
CPU time 1.15 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:53 PM PDT 24
Peak memory 206188 kb
Host smart-4cf5c769-d676-4ef9-ad1a-ab6b529d787c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951023871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3951023871
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.150147716
Short name T851
Test name
Test status
Simulation time 30130653 ps
CPU time 1.92 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:55 PM PDT 24
Peak memory 214412 kb
Host smart-c3fe82e9-bc53-4e47-8115-33718775f4b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150147716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.150147716
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3919536364
Short name T896
Test name
Test status
Simulation time 202561715 ps
CPU time 1.67 seconds
Started Apr 18 12:40:46 PM PDT 24
Finished Apr 18 12:40:49 PM PDT 24
Peak memory 206128 kb
Host smart-a4c6ac95-7bc5-49fa-a7d2-2f689bd322b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919536364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3919536364
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.574261468
Short name T946
Test name
Test status
Simulation time 20799224 ps
CPU time 1.27 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:55 PM PDT 24
Peak memory 214476 kb
Host smart-80c6245d-8879-4c6b-9f10-47cc6a420946
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574261468 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.574261468
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3252676264
Short name T941
Test name
Test status
Simulation time 25493113 ps
CPU time 0.87 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:52 PM PDT 24
Peak memory 206072 kb
Host smart-208828aa-b609-4d21-b3c8-879e9d64df5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252676264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3252676264
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.309642847
Short name T861
Test name
Test status
Simulation time 14135712 ps
CPU time 0.82 seconds
Started Apr 18 12:40:46 PM PDT 24
Finished Apr 18 12:40:48 PM PDT 24
Peak memory 205904 kb
Host smart-4dca11cf-3cef-4f00-bbd2-edd03230b672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309642847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.309642847
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1962243934
Short name T869
Test name
Test status
Simulation time 20260953 ps
CPU time 0.9 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:54 PM PDT 24
Peak memory 206212 kb
Host smart-62f1172a-8b1e-475d-889c-adcfbaab6b60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962243934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1962243934
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1030211027
Short name T916
Test name
Test status
Simulation time 151331135 ps
CPU time 2.75 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:55 PM PDT 24
Peak memory 214400 kb
Host smart-c9ef47ed-8985-4bc1-94fb-f5f8406ca29c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030211027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1030211027
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.790972548
Short name T239
Test name
Test status
Simulation time 151736199 ps
CPU time 1.48 seconds
Started Apr 18 12:40:52 PM PDT 24
Finished Apr 18 12:40:56 PM PDT 24
Peak memory 206116 kb
Host smart-22a747e8-f7f3-4651-bc0b-b454ab7e1d5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790972548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.790972548
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.4108869364
Short name T917
Test name
Test status
Simulation time 46037429 ps
CPU time 1.36 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:55 PM PDT 24
Peak memory 216572 kb
Host smart-ac456a20-0f8a-4b45-bd1f-e24da156ceff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108869364 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.4108869364
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1721345991
Short name T919
Test name
Test status
Simulation time 80805637 ps
CPU time 0.85 seconds
Started Apr 18 12:41:01 PM PDT 24
Finished Apr 18 12:41:03 PM PDT 24
Peak memory 206044 kb
Host smart-c76bbd32-715f-42f1-ab5b-526d06a29aa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721345991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1721345991
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2928223384
Short name T865
Test name
Test status
Simulation time 21121566 ps
CPU time 0.85 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:54 PM PDT 24
Peak memory 205996 kb
Host smart-a612d5ee-7caf-4376-9dad-826a2cfb69de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928223384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2928223384
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.134947840
Short name T222
Test name
Test status
Simulation time 19488828 ps
CPU time 1.21 seconds
Started Apr 18 12:41:06 PM PDT 24
Finished Apr 18 12:41:09 PM PDT 24
Peak memory 206064 kb
Host smart-5a2d570b-a269-4bf4-8167-7e8ae59e4a4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134947840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.134947840
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3700728290
Short name T888
Test name
Test status
Simulation time 93962557 ps
CPU time 3.61 seconds
Started Apr 18 12:40:56 PM PDT 24
Finished Apr 18 12:41:01 PM PDT 24
Peak memory 214424 kb
Host smart-56941fd9-1617-4187-87e8-2ce3e8ad8103
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700728290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3700728290
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3565599407
Short name T235
Test name
Test status
Simulation time 49610414 ps
CPU time 1.69 seconds
Started Apr 18 12:40:56 PM PDT 24
Finished Apr 18 12:40:59 PM PDT 24
Peak memory 206200 kb
Host smart-5426ef46-26b4-4f26-8ac7-b6a2381c2dfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565599407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3565599407
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1025206571
Short name T853
Test name
Test status
Simulation time 64179251 ps
CPU time 1.06 seconds
Started Apr 18 12:41:07 PM PDT 24
Finished Apr 18 12:41:09 PM PDT 24
Peak memory 214304 kb
Host smart-8dfb8511-04a3-4e91-b358-638787342c09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025206571 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1025206571
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1619171163
Short name T937
Test name
Test status
Simulation time 17659210 ps
CPU time 0.79 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:54 PM PDT 24
Peak memory 205972 kb
Host smart-7c65af45-198f-430f-b5c9-23f936c13cd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619171163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1619171163
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2916162229
Short name T899
Test name
Test status
Simulation time 19286850 ps
CPU time 0.85 seconds
Started Apr 18 12:41:01 PM PDT 24
Finished Apr 18 12:41:02 PM PDT 24
Peak memory 205864 kb
Host smart-a3d80952-6168-41ba-9e2b-e8ceff880c6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916162229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2916162229
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3266663909
Short name T892
Test name
Test status
Simulation time 18528474 ps
CPU time 1.13 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:53 PM PDT 24
Peak memory 206136 kb
Host smart-7dd62c42-1819-4bc5-ae31-ad2174c14de6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266663909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3266663909
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1537091877
Short name T858
Test name
Test status
Simulation time 449123585 ps
CPU time 1.93 seconds
Started Apr 18 12:40:55 PM PDT 24
Finished Apr 18 12:40:58 PM PDT 24
Peak memory 214424 kb
Host smart-74de7ff4-61a6-4b75-b497-d85ba52dae77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537091877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1537091877
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3603030694
Short name T240
Test name
Test status
Simulation time 445409126 ps
CPU time 2.65 seconds
Started Apr 18 12:40:54 PM PDT 24
Finished Apr 18 12:40:58 PM PDT 24
Peak memory 206104 kb
Host smart-0acb9bbb-cbdf-4b7a-87ce-0fc612ff6589
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603030694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3603030694
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4117152838
Short name T930
Test name
Test status
Simulation time 223887911 ps
CPU time 3.06 seconds
Started Apr 18 12:40:47 PM PDT 24
Finished Apr 18 12:40:51 PM PDT 24
Peak memory 205984 kb
Host smart-f7298906-a7d0-444e-857f-64b8c0e5b9ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117152838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.4117152838
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.344817809
Short name T215
Test name
Test status
Simulation time 22814329 ps
CPU time 0.85 seconds
Started Apr 18 12:40:33 PM PDT 24
Finished Apr 18 12:40:35 PM PDT 24
Peak memory 206004 kb
Host smart-0a8beadd-8011-4632-9822-df3eff164ea6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344817809 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.344817809
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3160501435
Short name T841
Test name
Test status
Simulation time 26811809 ps
CPU time 1.32 seconds
Started Apr 18 12:40:34 PM PDT 24
Finished Apr 18 12:40:36 PM PDT 24
Peak memory 214468 kb
Host smart-400302df-07b9-4746-bea9-2b22a46008d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160501435 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3160501435
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.865559534
Short name T877
Test name
Test status
Simulation time 26370028 ps
CPU time 0.91 seconds
Started Apr 18 12:40:39 PM PDT 24
Finished Apr 18 12:40:41 PM PDT 24
Peak memory 206044 kb
Host smart-1032d18e-f5bc-44bf-955e-2177d2086d6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865559534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.865559534
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.937521972
Short name T854
Test name
Test status
Simulation time 17397779 ps
CPU time 0.97 seconds
Started Apr 18 12:40:42 PM PDT 24
Finished Apr 18 12:40:44 PM PDT 24
Peak memory 206008 kb
Host smart-4cc7651a-2085-42ae-8263-bac969d97bff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937521972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.937521972
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.503619098
Short name T876
Test name
Test status
Simulation time 24871126 ps
CPU time 1.03 seconds
Started Apr 18 12:40:47 PM PDT 24
Finished Apr 18 12:40:50 PM PDT 24
Peak memory 206064 kb
Host smart-b7b076dd-98af-4f70-9fc4-06c2a6dde081
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503619098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out
standing.503619098
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2151666405
Short name T850
Test name
Test status
Simulation time 120839800 ps
CPU time 4.64 seconds
Started Apr 18 12:40:35 PM PDT 24
Finished Apr 18 12:40:41 PM PDT 24
Peak memory 214328 kb
Host smart-12767397-ef09-4e79-ac27-3e313c76b5eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151666405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2151666405
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2571253055
Short name T918
Test name
Test status
Simulation time 18600946 ps
CPU time 0.87 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:53 PM PDT 24
Peak memory 205952 kb
Host smart-277da2c5-ec63-416f-94f9-a7068b98e55c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571253055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2571253055
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.4165581139
Short name T947
Test name
Test status
Simulation time 51201263 ps
CPU time 0.83 seconds
Started Apr 18 12:40:49 PM PDT 24
Finished Apr 18 12:40:52 PM PDT 24
Peak memory 205892 kb
Host smart-973031a1-56db-4f08-813e-f308aee57e26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165581139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.4165581139
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3400000543
Short name T942
Test name
Test status
Simulation time 96312848 ps
CPU time 0.84 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:54 PM PDT 24
Peak memory 205832 kb
Host smart-f5209e20-7de5-42d6-a639-d437aae20454
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400000543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3400000543
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.129849602
Short name T844
Test name
Test status
Simulation time 50059647 ps
CPU time 0.87 seconds
Started Apr 18 12:41:10 PM PDT 24
Finished Apr 18 12:41:13 PM PDT 24
Peak memory 205984 kb
Host smart-0586ae0a-85b9-44ea-aebe-bf630ad50bb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129849602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.129849602
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3686949168
Short name T870
Test name
Test status
Simulation time 118546938 ps
CPU time 0.81 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:52 PM PDT 24
Peak memory 205892 kb
Host smart-c2559803-0181-4801-b593-d7b057136b23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686949168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3686949168
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.619188474
Short name T886
Test name
Test status
Simulation time 15749221 ps
CPU time 0.89 seconds
Started Apr 18 12:41:06 PM PDT 24
Finished Apr 18 12:41:08 PM PDT 24
Peak memory 205920 kb
Host smart-eedb3554-d004-46c6-837a-a38f15ff57ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619188474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.619188474
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1906742602
Short name T943
Test name
Test status
Simulation time 11380916 ps
CPU time 0.85 seconds
Started Apr 18 12:40:57 PM PDT 24
Finished Apr 18 12:40:59 PM PDT 24
Peak memory 205920 kb
Host smart-3539b28e-85b7-4d56-8512-2be188dcd5c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906742602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1906742602
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.4060064984
Short name T898
Test name
Test status
Simulation time 22009201 ps
CPU time 0.81 seconds
Started Apr 18 12:40:52 PM PDT 24
Finished Apr 18 12:40:55 PM PDT 24
Peak memory 205852 kb
Host smart-14c5493f-a35e-4811-9cd8-2820e0090d8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060064984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.4060064984
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3440709378
Short name T908
Test name
Test status
Simulation time 13113496 ps
CPU time 0.9 seconds
Started Apr 18 12:40:52 PM PDT 24
Finished Apr 18 12:40:56 PM PDT 24
Peak memory 205920 kb
Host smart-b6a03f05-a987-4a45-85bc-b4ea48295e94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440709378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3440709378
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3023883460
Short name T963
Test name
Test status
Simulation time 52116377 ps
CPU time 0.83 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:54 PM PDT 24
Peak memory 205952 kb
Host smart-89e14db0-df7a-4e78-ae7b-494130ae8013
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023883460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3023883460
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2298208677
Short name T212
Test name
Test status
Simulation time 67799325 ps
CPU time 1.57 seconds
Started Apr 18 12:40:38 PM PDT 24
Finished Apr 18 12:40:40 PM PDT 24
Peak memory 206024 kb
Host smart-6c77bef8-6a85-4dd2-a3b9-9f76f1a0306a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298208677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2298208677
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2083512887
Short name T206
Test name
Test status
Simulation time 114123961 ps
CPU time 3.24 seconds
Started Apr 18 12:40:35 PM PDT 24
Finished Apr 18 12:40:39 PM PDT 24
Peak memory 205976 kb
Host smart-90deb7e3-4d5f-404a-82b4-b0a5efd6873e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083512887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2083512887
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3277636748
Short name T201
Test name
Test status
Simulation time 14310777 ps
CPU time 0.92 seconds
Started Apr 18 12:40:43 PM PDT 24
Finished Apr 18 12:40:45 PM PDT 24
Peak memory 205996 kb
Host smart-5db3ae2d-93fa-48ff-8bcf-b9cd4fd3abde
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277636748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3277636748
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1177772838
Short name T969
Test name
Test status
Simulation time 280453388 ps
CPU time 1.49 seconds
Started Apr 18 12:40:42 PM PDT 24
Finished Apr 18 12:40:44 PM PDT 24
Peak memory 218128 kb
Host smart-0f93b458-1999-4421-9a9b-c72996c87b10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177772838 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1177772838
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3913105224
Short name T867
Test name
Test status
Simulation time 15673365 ps
CPU time 0.95 seconds
Started Apr 18 12:40:39 PM PDT 24
Finished Apr 18 12:40:41 PM PDT 24
Peak memory 205936 kb
Host smart-43313f2a-0a5a-41db-959a-2c79085754ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913105224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3913105224
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1888036667
Short name T931
Test name
Test status
Simulation time 35820513 ps
CPU time 0.82 seconds
Started Apr 18 12:40:45 PM PDT 24
Finished Apr 18 12:40:46 PM PDT 24
Peak memory 205880 kb
Host smart-32c6a279-95d9-4f42-999b-f16efbbce412
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888036667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1888036667
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.978995486
Short name T887
Test name
Test status
Simulation time 165388211 ps
CPU time 1.27 seconds
Started Apr 18 12:40:32 PM PDT 24
Finished Apr 18 12:40:34 PM PDT 24
Peak memory 206152 kb
Host smart-1456c254-5d65-449e-8fea-f40345efd950
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978995486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.978995486
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1403657000
Short name T864
Test name
Test status
Simulation time 449606862 ps
CPU time 4 seconds
Started Apr 18 12:40:33 PM PDT 24
Finished Apr 18 12:40:38 PM PDT 24
Peak memory 214412 kb
Host smart-1af6bacd-feef-444c-af3c-32b85b7b45ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403657000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1403657000
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1771579660
Short name T226
Test name
Test status
Simulation time 222908642 ps
CPU time 1.42 seconds
Started Apr 18 12:40:37 PM PDT 24
Finished Apr 18 12:40:39 PM PDT 24
Peak memory 214404 kb
Host smart-b2241824-7c4b-4f2c-95a1-89dfa7868ad5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771579660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1771579660
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2688686302
Short name T959
Test name
Test status
Simulation time 19153508 ps
CPU time 0.85 seconds
Started Apr 18 12:40:54 PM PDT 24
Finished Apr 18 12:40:57 PM PDT 24
Peak memory 205920 kb
Host smart-7dbff512-ba4b-40a0-8139-6139cdc91233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688686302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2688686302
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.855509081
Short name T893
Test name
Test status
Simulation time 30801718 ps
CPU time 0.9 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:54 PM PDT 24
Peak memory 206000 kb
Host smart-15b3ad71-b04c-4448-af1f-11eca7d9b881
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855509081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.855509081
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1306226853
Short name T938
Test name
Test status
Simulation time 10704237 ps
CPU time 0.82 seconds
Started Apr 18 12:40:52 PM PDT 24
Finished Apr 18 12:40:56 PM PDT 24
Peak memory 205856 kb
Host smart-66830ea5-97a9-4f0a-9635-d49397b7ecd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306226853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1306226853
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3287060601
Short name T961
Test name
Test status
Simulation time 43166696 ps
CPU time 0.83 seconds
Started Apr 18 12:41:05 PM PDT 24
Finished Apr 18 12:41:07 PM PDT 24
Peak memory 205988 kb
Host smart-396f7f2c-595f-4a04-a834-62603e8082dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287060601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3287060601
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.850438217
Short name T968
Test name
Test status
Simulation time 17047154 ps
CPU time 0.87 seconds
Started Apr 18 12:40:53 PM PDT 24
Finished Apr 18 12:40:56 PM PDT 24
Peak memory 205976 kb
Host smart-4601b953-959c-4787-9f3b-c4eb1e5cdfa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850438217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.850438217
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.4280601818
Short name T944
Test name
Test status
Simulation time 69219704 ps
CPU time 0.9 seconds
Started Apr 18 12:41:02 PM PDT 24
Finished Apr 18 12:41:04 PM PDT 24
Peak memory 205920 kb
Host smart-022d5d1e-5269-4a2d-bb68-f6751f7c8d89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280601818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.4280601818
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.982130324
Short name T873
Test name
Test status
Simulation time 34023467 ps
CPU time 0.8 seconds
Started Apr 18 12:40:54 PM PDT 24
Finished Apr 18 12:40:56 PM PDT 24
Peak memory 205952 kb
Host smart-54692ea6-fd74-4164-899a-fe0c25c90cce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982130324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.982130324
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2698145850
Short name T895
Test name
Test status
Simulation time 10982511 ps
CPU time 0.83 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:53 PM PDT 24
Peak memory 205936 kb
Host smart-4982460e-6665-4179-94e9-e2a15b1ae991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698145850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2698145850
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2642599366
Short name T907
Test name
Test status
Simulation time 14609201 ps
CPU time 0.88 seconds
Started Apr 18 12:40:49 PM PDT 24
Finished Apr 18 12:40:52 PM PDT 24
Peak memory 205924 kb
Host smart-25c1d877-97ec-4349-829b-6ed847ad9141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642599366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2642599366
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3675290793
Short name T925
Test name
Test status
Simulation time 27480045 ps
CPU time 0.78 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:55 PM PDT 24
Peak memory 205892 kb
Host smart-fc554841-0202-481d-9611-3b77f9358b41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675290793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3675290793
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.235708734
Short name T216
Test name
Test status
Simulation time 80415876 ps
CPU time 1.01 seconds
Started Apr 18 12:40:52 PM PDT 24
Finished Apr 18 12:40:56 PM PDT 24
Peak memory 206148 kb
Host smart-7b8ef6d3-4b9d-4f57-a94d-f759545869e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235708734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.235708734
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.152417796
Short name T223
Test name
Test status
Simulation time 151138685 ps
CPU time 2.04 seconds
Started Apr 18 12:40:43 PM PDT 24
Finished Apr 18 12:40:46 PM PDT 24
Peak memory 205956 kb
Host smart-252dbdd0-e1d9-41c9-9d9f-413e6df9a194
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152417796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.152417796
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1861762292
Short name T897
Test name
Test status
Simulation time 58712328 ps
CPU time 0.97 seconds
Started Apr 18 12:40:41 PM PDT 24
Finished Apr 18 12:40:42 PM PDT 24
Peak memory 206000 kb
Host smart-9dbaddc8-8480-4856-9784-8b9f450101f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861762292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1861762292
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.676616096
Short name T881
Test name
Test status
Simulation time 18781422 ps
CPU time 1.02 seconds
Started Apr 18 12:40:45 PM PDT 24
Finished Apr 18 12:40:46 PM PDT 24
Peak memory 214424 kb
Host smart-94ac3df3-7232-4b1d-97db-7856799501f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676616096 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.676616096
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1805520971
Short name T219
Test name
Test status
Simulation time 78360880 ps
CPU time 0.81 seconds
Started Apr 18 12:40:44 PM PDT 24
Finished Apr 18 12:40:46 PM PDT 24
Peak memory 205992 kb
Host smart-41006a30-dba2-42a3-b416-26cd30063c59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805520971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1805520971
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3736047025
Short name T883
Test name
Test status
Simulation time 25440570 ps
CPU time 0.81 seconds
Started Apr 18 12:40:45 PM PDT 24
Finished Apr 18 12:40:48 PM PDT 24
Peak memory 205844 kb
Host smart-367d3246-7856-4c38-9e37-6c5062ed5f01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736047025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3736047025
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.215498986
Short name T891
Test name
Test status
Simulation time 105868383 ps
CPU time 1.09 seconds
Started Apr 18 12:40:47 PM PDT 24
Finished Apr 18 12:40:49 PM PDT 24
Peak memory 206192 kb
Host smart-cd72871f-98fc-483a-b3eb-ab3affea5dc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215498986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.215498986
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1038421703
Short name T948
Test name
Test status
Simulation time 379831745 ps
CPU time 3 seconds
Started Apr 18 12:40:36 PM PDT 24
Finished Apr 18 12:40:40 PM PDT 24
Peak memory 214352 kb
Host smart-b494084b-473d-45d9-9b70-f231f2d7cc02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038421703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1038421703
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2571811674
Short name T962
Test name
Test status
Simulation time 175639706 ps
CPU time 1.52 seconds
Started Apr 18 12:40:48 PM PDT 24
Finished Apr 18 12:40:51 PM PDT 24
Peak memory 206120 kb
Host smart-3668e9ba-414f-446b-b8fe-dfb6719fb924
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571811674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2571811674
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2978554220
Short name T849
Test name
Test status
Simulation time 63476518 ps
CPU time 0.81 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:55 PM PDT 24
Peak memory 205912 kb
Host smart-e39e093b-f974-436c-adac-0f94acd1dff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978554220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2978554220
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3364527926
Short name T956
Test name
Test status
Simulation time 14655399 ps
CPU time 0.89 seconds
Started Apr 18 12:40:55 PM PDT 24
Finished Apr 18 12:40:57 PM PDT 24
Peak memory 205996 kb
Host smart-0650e0c9-0c57-4b95-b1f6-5848e9702921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364527926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3364527926
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.76246981
Short name T863
Test name
Test status
Simulation time 12880384 ps
CPU time 0.85 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:55 PM PDT 24
Peak memory 206004 kb
Host smart-8b0359ff-c548-479c-9db8-c8d198572337
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76246981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.76246981
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.657212160
Short name T903
Test name
Test status
Simulation time 18679669 ps
CPU time 0.93 seconds
Started Apr 18 12:41:03 PM PDT 24
Finished Apr 18 12:41:05 PM PDT 24
Peak memory 205936 kb
Host smart-07bc2733-1bdf-4627-bb64-ef89ca66d81d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657212160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.657212160
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3684058559
Short name T935
Test name
Test status
Simulation time 20996507 ps
CPU time 0.83 seconds
Started Apr 18 12:40:49 PM PDT 24
Finished Apr 18 12:40:52 PM PDT 24
Peak memory 205892 kb
Host smart-1254759d-322f-4304-9362-d6c6c8e1005f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684058559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3684058559
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1433396943
Short name T882
Test name
Test status
Simulation time 14471853 ps
CPU time 0.89 seconds
Started Apr 18 12:40:58 PM PDT 24
Finished Apr 18 12:41:00 PM PDT 24
Peak memory 205936 kb
Host smart-f453e226-9056-427d-9719-deb12d392059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433396943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1433396943
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3374472031
Short name T901
Test name
Test status
Simulation time 14004343 ps
CPU time 0.92 seconds
Started Apr 18 12:40:57 PM PDT 24
Finished Apr 18 12:40:59 PM PDT 24
Peak memory 206044 kb
Host smart-3b128b4e-2bed-4b05-a100-5407f88a1a37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374472031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3374472031
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1665418690
Short name T905
Test name
Test status
Simulation time 200243585 ps
CPU time 0.89 seconds
Started Apr 18 12:41:07 PM PDT 24
Finished Apr 18 12:41:09 PM PDT 24
Peak memory 205836 kb
Host smart-a32a2ebc-201d-4d6a-b8db-d467ca1899c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665418690 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1665418690
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3732680392
Short name T971
Test name
Test status
Simulation time 52026581 ps
CPU time 0.77 seconds
Started Apr 18 12:40:52 PM PDT 24
Finished Apr 18 12:40:56 PM PDT 24
Peak memory 205908 kb
Host smart-9450677d-03fe-4d29-b7b3-a25baa3f4855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732680392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3732680392
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2968230837
Short name T912
Test name
Test status
Simulation time 44272199 ps
CPU time 0.84 seconds
Started Apr 18 12:41:05 PM PDT 24
Finished Apr 18 12:41:07 PM PDT 24
Peak memory 205924 kb
Host smart-cf574065-e1ee-47ad-88b3-d1a04bcdad9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968230837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2968230837
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.791048752
Short name T909
Test name
Test status
Simulation time 75580720 ps
CPU time 1.69 seconds
Started Apr 18 12:40:43 PM PDT 24
Finished Apr 18 12:40:45 PM PDT 24
Peak memory 214332 kb
Host smart-961b4ae9-2eb8-4aa1-937a-a84da0aa369b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791048752 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.791048752
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.485836013
Short name T204
Test name
Test status
Simulation time 44546550 ps
CPU time 0.89 seconds
Started Apr 18 12:41:57 PM PDT 24
Finished Apr 18 12:41:59 PM PDT 24
Peak memory 205976 kb
Host smart-2b47eb67-9948-46c8-b2c0-dbd4f627ada7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485836013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.485836013
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1832871963
Short name T868
Test name
Test status
Simulation time 18557591 ps
CPU time 0.77 seconds
Started Apr 18 12:40:43 PM PDT 24
Finished Apr 18 12:40:45 PM PDT 24
Peak memory 205852 kb
Host smart-4645b433-b3d3-41d1-b92d-f3db94478fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832871963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1832871963
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2519489431
Short name T207
Test name
Test status
Simulation time 17013431 ps
CPU time 0.98 seconds
Started Apr 18 12:40:45 PM PDT 24
Finished Apr 18 12:40:47 PM PDT 24
Peak memory 206072 kb
Host smart-9c035eb7-b9c8-464f-af78-eb449028255d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519489431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2519489431
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3523905949
Short name T960
Test name
Test status
Simulation time 790633241 ps
CPU time 2.61 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:56 PM PDT 24
Peak memory 214372 kb
Host smart-f65f7ee3-4fec-4b1f-a3ac-63448c2344b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523905949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3523905949
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2729885631
Short name T951
Test name
Test status
Simulation time 1912084081 ps
CPU time 7.78 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:41:01 PM PDT 24
Peak memory 206040 kb
Host smart-36ce5fae-13d4-4b9d-85e1-f6ceb30f514b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729885631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2729885631
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3381362906
Short name T934
Test name
Test status
Simulation time 149604294 ps
CPU time 1.01 seconds
Started Apr 18 12:40:47 PM PDT 24
Finished Apr 18 12:40:49 PM PDT 24
Peak memory 206196 kb
Host smart-9c122ba1-6563-4ef8-ae01-d7de8f77f3f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381362906 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3381362906
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1083397640
Short name T923
Test name
Test status
Simulation time 15997930 ps
CPU time 0.96 seconds
Started Apr 18 12:40:45 PM PDT 24
Finished Apr 18 12:40:47 PM PDT 24
Peak memory 205976 kb
Host smart-af8c71ff-c9d7-4e59-b09c-e437de846d79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083397640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1083397640
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3206690476
Short name T966
Test name
Test status
Simulation time 37950730 ps
CPU time 0.82 seconds
Started Apr 18 12:40:44 PM PDT 24
Finished Apr 18 12:40:46 PM PDT 24
Peak memory 205896 kb
Host smart-f6a52227-4c8f-4a5a-a28b-4cda1d1c64c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206690476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3206690476
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3352368073
Short name T221
Test name
Test status
Simulation time 13401822 ps
CPU time 0.93 seconds
Started Apr 18 12:40:46 PM PDT 24
Finished Apr 18 12:40:48 PM PDT 24
Peak memory 206184 kb
Host smart-8626613a-b38c-4667-8bbf-2309c8991025
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352368073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3352368073
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1817054452
Short name T843
Test name
Test status
Simulation time 452912681 ps
CPU time 3.86 seconds
Started Apr 18 12:40:49 PM PDT 24
Finished Apr 18 12:40:55 PM PDT 24
Peak memory 214500 kb
Host smart-95145734-0210-40bd-8cd4-870d38da4be6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817054452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1817054452
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1447072583
Short name T958
Test name
Test status
Simulation time 240222708 ps
CPU time 2.72 seconds
Started Apr 18 12:40:43 PM PDT 24
Finished Apr 18 12:40:47 PM PDT 24
Peak memory 206128 kb
Host smart-ed150cb9-c136-4c4f-a0fb-762058b8a332
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447072583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1447072583
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3684860563
Short name T878
Test name
Test status
Simulation time 159958507 ps
CPU time 1.61 seconds
Started Apr 18 12:40:47 PM PDT 24
Finished Apr 18 12:40:50 PM PDT 24
Peak memory 214344 kb
Host smart-3dd75a3a-5712-458a-b477-f9326ade2f6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684860563 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3684860563
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.4112024301
Short name T214
Test name
Test status
Simulation time 11235838 ps
CPU time 0.82 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:55 PM PDT 24
Peak memory 206040 kb
Host smart-0fe1d30d-6458-45ae-ab7d-8c996a2a7eaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112024301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.4112024301
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.527356645
Short name T949
Test name
Test status
Simulation time 24574213 ps
CPU time 0.85 seconds
Started Apr 18 12:40:41 PM PDT 24
Finished Apr 18 12:40:43 PM PDT 24
Peak memory 205968 kb
Host smart-3e3767e7-c60f-4ff3-b3fa-5e71f5d4d0df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527356645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.527356645
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3715443492
Short name T205
Test name
Test status
Simulation time 27182241 ps
CPU time 0.96 seconds
Started Apr 18 12:40:54 PM PDT 24
Finished Apr 18 12:40:57 PM PDT 24
Peak memory 206208 kb
Host smart-9c071ae5-03f8-4abf-895d-f6ba8cb3de12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715443492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3715443492
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2748084407
Short name T852
Test name
Test status
Simulation time 20258273 ps
CPU time 1.46 seconds
Started Apr 18 12:40:49 PM PDT 24
Finished Apr 18 12:40:52 PM PDT 24
Peak memory 214424 kb
Host smart-8b4ca816-8def-4af2-98e7-064cb327f2cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748084407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2748084407
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2727410935
Short name T970
Test name
Test status
Simulation time 131278030 ps
CPU time 2.13 seconds
Started Apr 18 12:40:49 PM PDT 24
Finished Apr 18 12:40:52 PM PDT 24
Peak memory 206184 kb
Host smart-1fe3758b-dbdd-4744-8b10-6bb43a74ebdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727410935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2727410935
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.4120914955
Short name T920
Test name
Test status
Simulation time 33681546 ps
CPU time 1.02 seconds
Started Apr 18 12:40:46 PM PDT 24
Finished Apr 18 12:40:48 PM PDT 24
Peak memory 206152 kb
Host smart-ae664b0b-0cbd-4398-9470-a3c645c02693
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120914955 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.4120914955
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1358054762
Short name T890
Test name
Test status
Simulation time 49314169 ps
CPU time 0.85 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:54 PM PDT 24
Peak memory 205956 kb
Host smart-ba1f5a2d-cdb6-42c9-9369-a8399e1e05aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358054762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1358054762
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3945921198
Short name T855
Test name
Test status
Simulation time 24555659 ps
CPU time 0.85 seconds
Started Apr 18 12:40:41 PM PDT 24
Finished Apr 18 12:40:42 PM PDT 24
Peak memory 205992 kb
Host smart-55549e9c-b1e7-489c-b450-fe422b3148b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945921198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3945921198
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.42539800
Short name T900
Test name
Test status
Simulation time 32977714 ps
CPU time 1.32 seconds
Started Apr 18 12:40:43 PM PDT 24
Finished Apr 18 12:40:45 PM PDT 24
Peak memory 206020 kb
Host smart-76be3ebd-31c1-4881-83a5-79274f547f6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42539800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outs
tanding.42539800
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2594956727
Short name T860
Test name
Test status
Simulation time 528681707 ps
CPU time 3.89 seconds
Started Apr 18 12:40:42 PM PDT 24
Finished Apr 18 12:40:47 PM PDT 24
Peak memory 214320 kb
Host smart-c1f21411-4509-468b-862d-9915ca5d2c09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594956727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2594956727
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3527692906
Short name T238
Test name
Test status
Simulation time 366482252 ps
CPU time 2.48 seconds
Started Apr 18 12:40:41 PM PDT 24
Finished Apr 18 12:40:44 PM PDT 24
Peak memory 206188 kb
Host smart-94866e41-4b90-4790-80b2-5b9ec413b8f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527692906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3527692906
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1154633148
Short name T957
Test name
Test status
Simulation time 31862920 ps
CPU time 1.81 seconds
Started Apr 18 12:40:47 PM PDT 24
Finished Apr 18 12:40:50 PM PDT 24
Peak memory 214464 kb
Host smart-cab11a46-d11b-445c-8667-e8f8d70030b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154633148 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1154633148
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.4145941954
Short name T208
Test name
Test status
Simulation time 40882577 ps
CPU time 0.9 seconds
Started Apr 18 12:40:50 PM PDT 24
Finished Apr 18 12:40:53 PM PDT 24
Peak memory 206068 kb
Host smart-727f5fd1-20a2-423c-93d2-0cfdd719a9c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145941954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.4145941954
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2400088639
Short name T894
Test name
Test status
Simulation time 19884513 ps
CPU time 0.85 seconds
Started Apr 18 12:40:47 PM PDT 24
Finished Apr 18 12:40:49 PM PDT 24
Peak memory 205928 kb
Host smart-5f7f7958-aca8-44d8-b986-fc083bc55212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400088639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2400088639
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3386135804
Short name T922
Test name
Test status
Simulation time 35997100 ps
CPU time 1.02 seconds
Started Apr 18 12:40:40 PM PDT 24
Finished Apr 18 12:40:41 PM PDT 24
Peak memory 206060 kb
Host smart-47d8519b-3f90-4463-94e5-8a1073c36f73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386135804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3386135804
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2954874477
Short name T842
Test name
Test status
Simulation time 234513914 ps
CPU time 4.24 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:58 PM PDT 24
Peak memory 214396 kb
Host smart-0ca5d256-bc3f-47c3-8934-00157c19163b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954874477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2954874477
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1869319798
Short name T237
Test name
Test status
Simulation time 110453490 ps
CPU time 2.36 seconds
Started Apr 18 12:40:51 PM PDT 24
Finished Apr 18 12:40:56 PM PDT 24
Peak memory 206032 kb
Host smart-7dde6825-5acd-409a-82e5-70ced2ecb836
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869319798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1869319798
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1654152110
Short name T169
Test name
Test status
Simulation time 70456584 ps
CPU time 1.28 seconds
Started Apr 18 02:24:38 PM PDT 24
Finished Apr 18 02:24:41 PM PDT 24
Peak memory 216120 kb
Host smart-e2367f00-a376-449d-8a1f-c496f7f6b58d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654152110 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1654152110
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.488647208
Short name T720
Test name
Test status
Simulation time 85000529 ps
CPU time 1.01 seconds
Started Apr 18 02:24:29 PM PDT 24
Finished Apr 18 02:24:30 PM PDT 24
Peak memory 219140 kb
Host smart-15b79aa0-8669-441a-af4a-dd119996f386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488647208 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.488647208
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.3318304712
Short name T340
Test name
Test status
Simulation time 56817413 ps
CPU time 1.72 seconds
Started Apr 18 02:24:25 PM PDT 24
Finished Apr 18 02:24:28 PM PDT 24
Peak memory 217672 kb
Host smart-3dc8ab93-0b3e-40e0-abc4-86b00a74c380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318304712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3318304712
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.2943856509
Short name T471
Test name
Test status
Simulation time 22604592 ps
CPU time 1.09 seconds
Started Apr 18 02:24:34 PM PDT 24
Finished Apr 18 02:24:36 PM PDT 24
Peak memory 215256 kb
Host smart-0852ea0d-5e40-4fa4-8d01-0d124cf81ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943856509 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2943856509
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1902344428
Short name T95
Test name
Test status
Simulation time 1285285818 ps
CPU time 5.58 seconds
Started Apr 18 02:24:28 PM PDT 24
Finished Apr 18 02:24:34 PM PDT 24
Peak memory 234400 kb
Host smart-99a8d76b-63e4-473d-a7dd-bcfb620ac459
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902344428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1902344428
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.511726100
Short name T301
Test name
Test status
Simulation time 24112170 ps
CPU time 0.98 seconds
Started Apr 18 02:24:32 PM PDT 24
Finished Apr 18 02:24:33 PM PDT 24
Peak memory 215024 kb
Host smart-ad3a0142-9bd4-4f98-b263-0217d7310e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511726100 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.511726100
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_alert.4203167332
Short name T766
Test name
Test status
Simulation time 22780228 ps
CPU time 1.16 seconds
Started Apr 18 02:24:37 PM PDT 24
Finished Apr 18 02:24:39 PM PDT 24
Peak memory 215408 kb
Host smart-01837519-d2d5-4615-8173-346b2dabc09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203167332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.4203167332
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.5915612
Short name T428
Test name
Test status
Simulation time 27544035 ps
CPU time 0.92 seconds
Started Apr 18 02:24:31 PM PDT 24
Finished Apr 18 02:24:33 PM PDT 24
Peak memory 206716 kb
Host smart-50832933-3508-4dc1-babc-7e165c9227f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5915612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.5915612
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2613514124
Short name T455
Test name
Test status
Simulation time 53021003 ps
CPU time 1.07 seconds
Started Apr 18 02:24:34 PM PDT 24
Finished Apr 18 02:24:36 PM PDT 24
Peak memory 217256 kb
Host smart-269a2029-3881-4912-8303-00676cf437eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613514124 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2613514124
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.3215948023
Short name T76
Test name
Test status
Simulation time 19920162 ps
CPU time 1.13 seconds
Started Apr 18 02:24:33 PM PDT 24
Finished Apr 18 02:24:35 PM PDT 24
Peak memory 232352 kb
Host smart-b6827807-83a7-4afa-a2bb-62ce10f7a15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215948023 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3215948023
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_intr.2516377058
Short name T566
Test name
Test status
Simulation time 20575010 ps
CPU time 1.06 seconds
Started Apr 18 02:24:27 PM PDT 24
Finished Apr 18 02:24:29 PM PDT 24
Peak memory 215276 kb
Host smart-abc5ec8e-ec54-4634-9503-ee0dc911f91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516377058 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2516377058
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.3533199827
Short name T254
Test name
Test status
Simulation time 51821506 ps
CPU time 0.9 seconds
Started Apr 18 02:24:27 PM PDT 24
Finished Apr 18 02:24:29 PM PDT 24
Peak memory 206808 kb
Host smart-4b2bffb6-1142-42f3-8849-7cbb91a5241c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533199827 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3533199827
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1094850751
Short name T93
Test name
Test status
Simulation time 184054217 ps
CPU time 3.67 seconds
Started Apr 18 02:24:27 PM PDT 24
Finished Apr 18 02:24:31 PM PDT 24
Peak memory 233056 kb
Host smart-2055da63-7d9a-4928-939b-b731a214547c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094850751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1094850751
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.115103017
Short name T313
Test name
Test status
Simulation time 18403518 ps
CPU time 1.02 seconds
Started Apr 18 02:24:35 PM PDT 24
Finished Apr 18 02:24:37 PM PDT 24
Peak memory 215008 kb
Host smart-26096a68-4ca1-4ad7-bfdd-6c3decda3596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115103017 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.115103017
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.640055485
Short name T127
Test name
Test status
Simulation time 277501028 ps
CPU time 5.85 seconds
Started Apr 18 02:24:34 PM PDT 24
Finished Apr 18 02:24:41 PM PDT 24
Peak memory 216276 kb
Host smart-0467033e-e93e-4ad9-8dc5-4522e709e18d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640055485 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.640055485
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2252232127
Short name T725
Test name
Test status
Simulation time 59391757247 ps
CPU time 1393.08 seconds
Started Apr 18 02:24:28 PM PDT 24
Finished Apr 18 02:47:42 PM PDT 24
Peak memory 221888 kb
Host smart-b813cc5f-053d-4596-b4dd-794b5dcab0c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252232127 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2252232127
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1178504957
Short name T256
Test name
Test status
Simulation time 41983417 ps
CPU time 1.23 seconds
Started Apr 18 02:24:43 PM PDT 24
Finished Apr 18 02:24:44 PM PDT 24
Peak memory 215404 kb
Host smart-20bb1e12-39b0-41a2-b159-f8831c56fb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178504957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1178504957
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.432759049
Short name T660
Test name
Test status
Simulation time 35130920 ps
CPU time 1.23 seconds
Started Apr 18 02:24:45 PM PDT 24
Finished Apr 18 02:24:46 PM PDT 24
Peak memory 205964 kb
Host smart-3b247504-4334-440a-959e-ca7f050e1c23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432759049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.432759049
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.2437260198
Short name T616
Test name
Test status
Simulation time 13175850 ps
CPU time 0.92 seconds
Started Apr 18 02:24:48 PM PDT 24
Finished Apr 18 02:24:49 PM PDT 24
Peak memory 215592 kb
Host smart-9aee28ad-b648-4492-9834-b0b4b6859730
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437260198 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2437260198
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.103127145
Short name T9
Test name
Test status
Simulation time 61593194 ps
CPU time 1.1 seconds
Started Apr 18 02:24:43 PM PDT 24
Finished Apr 18 02:24:45 PM PDT 24
Peak memory 216328 kb
Host smart-3b8c32f1-9b47-483d-a64a-66214f24bf04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103127145 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.103127145
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.3792268315
Short name T168
Test name
Test status
Simulation time 18192421 ps
CPU time 1.05 seconds
Started Apr 18 02:24:43 PM PDT 24
Finished Apr 18 02:24:44 PM PDT 24
Peak memory 217728 kb
Host smart-12cd6cfa-c92d-4bd6-89f5-428e0a67971c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792268315 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3792268315
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3117937788
Short name T601
Test name
Test status
Simulation time 104789615 ps
CPU time 1.6 seconds
Started Apr 18 02:24:48 PM PDT 24
Finished Apr 18 02:24:50 PM PDT 24
Peak memory 218128 kb
Host smart-a144fbd4-4f36-43d4-83c8-05489b4f77a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117937788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3117937788
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3203840538
Short name T474
Test name
Test status
Simulation time 37797666 ps
CPU time 0.87 seconds
Started Apr 18 02:24:43 PM PDT 24
Finished Apr 18 02:24:44 PM PDT 24
Peak memory 215144 kb
Host smart-1fea08f1-ff7d-46c8-ab24-3bfee97df47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203840538 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3203840538
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2596559368
Short name T506
Test name
Test status
Simulation time 44104202 ps
CPU time 0.89 seconds
Started Apr 18 02:24:43 PM PDT 24
Finished Apr 18 02:24:44 PM PDT 24
Peak memory 215016 kb
Host smart-b49c115c-4cb0-48ab-8279-350cc7363255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596559368 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2596559368
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1607281633
Short name T318
Test name
Test status
Simulation time 201939316 ps
CPU time 3.25 seconds
Started Apr 18 02:24:42 PM PDT 24
Finished Apr 18 02:24:46 PM PDT 24
Peak memory 219556 kb
Host smart-58e999ff-0c94-469f-836e-f97e39480f73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607281633 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1607281633
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3170144164
Short name T128
Test name
Test status
Simulation time 167233747001 ps
CPU time 1909.32 seconds
Started Apr 18 02:24:43 PM PDT 24
Finished Apr 18 02:56:33 PM PDT 24
Peak memory 228272 kb
Host smart-a3ca4e56-4615-433e-a252-9c4ba1b9bcfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170144164 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3170144164
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.1074113402
Short name T768
Test name
Test status
Simulation time 84893164 ps
CPU time 1.21 seconds
Started Apr 18 02:26:14 PM PDT 24
Finished Apr 18 02:26:16 PM PDT 24
Peak memory 216472 kb
Host smart-c7ed6da5-22af-443c-bfa4-0951882b24f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074113402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1074113402
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.4287393312
Short name T404
Test name
Test status
Simulation time 93904537 ps
CPU time 1.51 seconds
Started Apr 18 02:26:11 PM PDT 24
Finished Apr 18 02:26:13 PM PDT 24
Peak memory 218092 kb
Host smart-ca9fae0e-8207-48e2-a174-0e8c75a07aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287393312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.4287393312
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.1543433665
Short name T407
Test name
Test status
Simulation time 71593577 ps
CPU time 1.37 seconds
Started Apr 18 02:26:12 PM PDT 24
Finished Apr 18 02:26:15 PM PDT 24
Peak memory 217644 kb
Host smart-ccd7eca1-6c10-40a3-b1e3-4e206df33a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543433665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1543433665
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.4028016458
Short name T394
Test name
Test status
Simulation time 112839828 ps
CPU time 1.32 seconds
Started Apr 18 02:26:13 PM PDT 24
Finished Apr 18 02:26:15 PM PDT 24
Peak memory 217724 kb
Host smart-3d869eca-7d7f-46f2-9f4d-110b3a285295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028016458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.4028016458
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1426311205
Short name T345
Test name
Test status
Simulation time 212326510 ps
CPU time 1.62 seconds
Started Apr 18 02:26:15 PM PDT 24
Finished Apr 18 02:26:17 PM PDT 24
Peak memory 216568 kb
Host smart-d6222067-0a26-4ff3-8b42-4a7b26676954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426311205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1426311205
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1604810255
Short name T636
Test name
Test status
Simulation time 150782073 ps
CPU time 1.19 seconds
Started Apr 18 02:26:15 PM PDT 24
Finished Apr 18 02:26:17 PM PDT 24
Peak memory 216384 kb
Host smart-b75755fb-2725-473e-9d1a-2d7f7c3e3786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604810255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1604810255
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.1372547980
Short name T371
Test name
Test status
Simulation time 117886588 ps
CPU time 1.25 seconds
Started Apr 18 02:26:17 PM PDT 24
Finished Apr 18 02:26:19 PM PDT 24
Peak memory 216304 kb
Host smart-44def85d-ec88-4b5e-a1c4-bbc9be473a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372547980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1372547980
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.1203730758
Short name T754
Test name
Test status
Simulation time 105677554 ps
CPU time 2.13 seconds
Started Apr 18 02:24:49 PM PDT 24
Finished Apr 18 02:24:52 PM PDT 24
Peak memory 206164 kb
Host smart-ed8bf6fe-7666-4373-8eb4-aa6c9e4708fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203730758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1203730758
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3303560509
Short name T379
Test name
Test status
Simulation time 43065734 ps
CPU time 1.11 seconds
Started Apr 18 02:24:50 PM PDT 24
Finished Apr 18 02:24:52 PM PDT 24
Peak memory 217456 kb
Host smart-76547606-3e77-4155-8465-01db32521ad7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303560509 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3303560509
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.392067
Short name T510
Test name
Test status
Simulation time 19454560 ps
CPU time 1.14 seconds
Started Apr 18 02:24:52 PM PDT 24
Finished Apr 18 02:24:54 PM PDT 24
Peak memory 232124 kb
Host smart-577053f7-d18f-4ee9-886c-5c1369c40189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.392067
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2431156776
Short name T666
Test name
Test status
Simulation time 288395675 ps
CPU time 1.74 seconds
Started Apr 18 02:24:42 PM PDT 24
Finished Apr 18 02:24:44 PM PDT 24
Peak memory 217836 kb
Host smart-66ae533f-7257-4c4b-9415-05d9573a5363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431156776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2431156776
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1184996649
Short name T367
Test name
Test status
Simulation time 22157908 ps
CPU time 1.07 seconds
Started Apr 18 02:24:51 PM PDT 24
Finished Apr 18 02:24:53 PM PDT 24
Peak memory 215316 kb
Host smart-dcb7ac11-647a-4f07-b201-8970fb497256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184996649 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1184996649
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.119326332
Short name T701
Test name
Test status
Simulation time 17084179 ps
CPU time 0.98 seconds
Started Apr 18 02:24:43 PM PDT 24
Finished Apr 18 02:24:45 PM PDT 24
Peak memory 215000 kb
Host smart-90ac9ae1-c54b-47a5-bd7c-e805bbb25093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119326332 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.119326332
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2465092846
Short name T408
Test name
Test status
Simulation time 791146643 ps
CPU time 5.65 seconds
Started Apr 18 02:24:48 PM PDT 24
Finished Apr 18 02:24:54 PM PDT 24
Peak memory 216428 kb
Host smart-3787663c-9850-42e3-9347-75b87ff39ade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465092846 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2465092846
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3627895793
Short name T801
Test name
Test status
Simulation time 171705640673 ps
CPU time 970.64 seconds
Started Apr 18 02:24:44 PM PDT 24
Finished Apr 18 02:40:56 PM PDT 24
Peak memory 220588 kb
Host smart-ee6dd85c-0c2a-462a-8aea-f652c2694a4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627895793 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3627895793
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.2003682943
Short name T470
Test name
Test status
Simulation time 93418756 ps
CPU time 1.23 seconds
Started Apr 18 02:26:23 PM PDT 24
Finished Apr 18 02:26:25 PM PDT 24
Peak memory 216328 kb
Host smart-382511a3-f5b8-4444-a95e-d6df16704ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003682943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2003682943
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.764879972
Short name T373
Test name
Test status
Simulation time 67552453 ps
CPU time 1.19 seconds
Started Apr 18 02:26:19 PM PDT 24
Finished Apr 18 02:26:21 PM PDT 24
Peak memory 217992 kb
Host smart-3bf9becb-64a8-464d-ba2a-342d7959089d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764879972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.764879972
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.1145030523
Short name T544
Test name
Test status
Simulation time 172697903 ps
CPU time 2.42 seconds
Started Apr 18 02:26:19 PM PDT 24
Finished Apr 18 02:26:21 PM PDT 24
Peak memory 216608 kb
Host smart-18ff7ded-089f-452f-99b5-5fbf4f197566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145030523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1145030523
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.216306309
Short name T674
Test name
Test status
Simulation time 91053116 ps
CPU time 1.35 seconds
Started Apr 18 02:26:17 PM PDT 24
Finished Apr 18 02:26:19 PM PDT 24
Peak memory 217836 kb
Host smart-0ffa4755-2c9a-4262-9f36-d3dc30aea486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216306309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.216306309
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.1586425036
Short name T675
Test name
Test status
Simulation time 41157948 ps
CPU time 1.02 seconds
Started Apr 18 02:26:20 PM PDT 24
Finished Apr 18 02:26:22 PM PDT 24
Peak memory 216392 kb
Host smart-bf87979c-f174-4fa6-82e9-0c6e349a6224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586425036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1586425036
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.134672737
Short name T448
Test name
Test status
Simulation time 92203967 ps
CPU time 2.25 seconds
Started Apr 18 02:26:20 PM PDT 24
Finished Apr 18 02:26:23 PM PDT 24
Peak memory 217816 kb
Host smart-8d70e122-8427-4df4-abff-5210b85edd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134672737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.134672737
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3146265041
Short name T584
Test name
Test status
Simulation time 42734897 ps
CPU time 1.58 seconds
Started Apr 18 02:26:19 PM PDT 24
Finished Apr 18 02:26:21 PM PDT 24
Peak memory 219276 kb
Host smart-de1a34b6-2d96-46a0-afd2-12d537e06775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146265041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3146265041
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.338524440
Short name T622
Test name
Test status
Simulation time 95311470 ps
CPU time 2.3 seconds
Started Apr 18 02:26:16 PM PDT 24
Finished Apr 18 02:26:19 PM PDT 24
Peak memory 216604 kb
Host smart-b08d9e5b-5087-4a6a-8be4-49c6d3917e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338524440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.338524440
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1082024427
Short name T67
Test name
Test status
Simulation time 160095501 ps
CPU time 1.11 seconds
Started Apr 18 02:24:50 PM PDT 24
Finished Apr 18 02:24:52 PM PDT 24
Peak memory 215396 kb
Host smart-9f488443-a967-43e7-8372-f5cbacd2b349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082024427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1082024427
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2577751400
Short name T436
Test name
Test status
Simulation time 37822610 ps
CPU time 0.83 seconds
Started Apr 18 02:24:54 PM PDT 24
Finished Apr 18 02:24:55 PM PDT 24
Peak memory 205592 kb
Host smart-01c2042c-a28a-4f4a-93fb-dec8ced5293e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577751400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2577751400
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2056834245
Short name T729
Test name
Test status
Simulation time 12275409 ps
CPU time 0.85 seconds
Started Apr 18 02:24:51 PM PDT 24
Finished Apr 18 02:24:52 PM PDT 24
Peak memory 215308 kb
Host smart-3185ce1c-4fe6-44b8-b963-95dcfe31f119
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056834245 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2056834245
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3848404890
Short name T376
Test name
Test status
Simulation time 25171747 ps
CPU time 1.07 seconds
Started Apr 18 02:24:54 PM PDT 24
Finished Apr 18 02:24:55 PM PDT 24
Peak memory 216296 kb
Host smart-6852b80a-66d4-4528-85e0-f0e3afcc1609
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848404890 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3848404890
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.106655863
Short name T599
Test name
Test status
Simulation time 19337855 ps
CPU time 1.05 seconds
Started Apr 18 02:24:49 PM PDT 24
Finished Apr 18 02:24:51 PM PDT 24
Peak memory 217784 kb
Host smart-0045d9ef-c78a-4cb3-85f2-25374ae1d1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106655863 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.106655863
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2411255406
Short name T751
Test name
Test status
Simulation time 32763916 ps
CPU time 1.38 seconds
Started Apr 18 02:24:49 PM PDT 24
Finished Apr 18 02:24:51 PM PDT 24
Peak memory 217672 kb
Host smart-cb56e636-1be2-4331-a22d-3ecbf58061cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411255406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2411255406
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3658779882
Short name T569
Test name
Test status
Simulation time 34907452 ps
CPU time 0.97 seconds
Started Apr 18 02:24:50 PM PDT 24
Finished Apr 18 02:24:51 PM PDT 24
Peak memory 223640 kb
Host smart-028883cb-e498-4af3-8df2-a5b090706647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658779882 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3658779882
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1854536982
Short name T816
Test name
Test status
Simulation time 24077135 ps
CPU time 0.95 seconds
Started Apr 18 02:24:48 PM PDT 24
Finished Apr 18 02:24:50 PM PDT 24
Peak memory 215036 kb
Host smart-7f19f189-c867-4439-a187-d77a8bbefbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854536982 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1854536982
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1272635372
Short name T409
Test name
Test status
Simulation time 1406264694 ps
CPU time 3.52 seconds
Started Apr 18 02:24:50 PM PDT 24
Finished Apr 18 02:24:54 PM PDT 24
Peak memory 215000 kb
Host smart-2bf799e5-37ad-4f25-9d24-570550ccc23e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272635372 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1272635372
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1294913406
Short name T531
Test name
Test status
Simulation time 34486653075 ps
CPU time 768.1 seconds
Started Apr 18 02:24:51 PM PDT 24
Finished Apr 18 02:37:40 PM PDT 24
Peak memory 217544 kb
Host smart-0a67ead8-9a14-46f8-9d90-3a55c60ad906
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294913406 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1294913406
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.3316171929
Short name T733
Test name
Test status
Simulation time 61285243 ps
CPU time 1.33 seconds
Started Apr 18 02:26:20 PM PDT 24
Finished Apr 18 02:26:22 PM PDT 24
Peak memory 217888 kb
Host smart-236dd095-4c52-444a-a009-773c2cfa51eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316171929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3316171929
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.645908931
Short name T731
Test name
Test status
Simulation time 120789379 ps
CPU time 1.18 seconds
Started Apr 18 02:26:20 PM PDT 24
Finished Apr 18 02:26:21 PM PDT 24
Peak memory 216476 kb
Host smart-52b28e8b-b370-4e3a-abb6-9b4e52f67419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645908931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.645908931
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.3055016117
Short name T553
Test name
Test status
Simulation time 79567976 ps
CPU time 2.78 seconds
Started Apr 18 02:26:18 PM PDT 24
Finished Apr 18 02:26:21 PM PDT 24
Peak memory 217700 kb
Host smart-4b8a3b4c-9675-4c55-91db-f61d03cc5dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055016117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3055016117
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2454310727
Short name T386
Test name
Test status
Simulation time 193589444 ps
CPU time 1.88 seconds
Started Apr 18 02:26:18 PM PDT 24
Finished Apr 18 02:26:21 PM PDT 24
Peak memory 217976 kb
Host smart-c4f335c3-af60-4fc8-ba2c-7ec05ccd39a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454310727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2454310727
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.3372515499
Short name T292
Test name
Test status
Simulation time 87771684 ps
CPU time 1.31 seconds
Started Apr 18 02:26:17 PM PDT 24
Finished Apr 18 02:26:19 PM PDT 24
Peak memory 216648 kb
Host smart-06021bca-5f49-468d-856b-1a3730c37535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372515499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3372515499
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.113333917
Short name T629
Test name
Test status
Simulation time 32625106 ps
CPU time 1 seconds
Started Apr 18 02:26:16 PM PDT 24
Finished Apr 18 02:26:18 PM PDT 24
Peak memory 216372 kb
Host smart-19d947f2-ccc1-43e5-886f-a7a735e19483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113333917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.113333917
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.3697600053
Short name T143
Test name
Test status
Simulation time 97776573 ps
CPU time 1.37 seconds
Started Apr 18 02:26:22 PM PDT 24
Finished Apr 18 02:26:24 PM PDT 24
Peak memory 217704 kb
Host smart-20536fc4-4277-429a-b0dc-cb1725c653a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697600053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3697600053
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.715669778
Short name T611
Test name
Test status
Simulation time 118353902 ps
CPU time 1.49 seconds
Started Apr 18 02:26:23 PM PDT 24
Finished Apr 18 02:26:25 PM PDT 24
Peak memory 217788 kb
Host smart-ce7e6659-3a28-495f-8101-99516c9823fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715669778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.715669778
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3142443182
Short name T791
Test name
Test status
Simulation time 48663026 ps
CPU time 1.79 seconds
Started Apr 18 02:26:29 PM PDT 24
Finished Apr 18 02:26:31 PM PDT 24
Peak memory 217580 kb
Host smart-cfdd4b43-3a55-4bab-a559-d1c12398ddd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142443182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3142443182
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3530946000
Short name T765
Test name
Test status
Simulation time 49396480 ps
CPU time 1.23 seconds
Started Apr 18 02:24:56 PM PDT 24
Finished Apr 18 02:24:58 PM PDT 24
Peak memory 215444 kb
Host smart-d755d33f-b071-4258-aca6-2c20f8ebbb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530946000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3530946000
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3450466741
Short name T443
Test name
Test status
Simulation time 48763200 ps
CPU time 0.84 seconds
Started Apr 18 02:24:51 PM PDT 24
Finished Apr 18 02:24:52 PM PDT 24
Peak memory 206428 kb
Host smart-314d3a0b-1220-4ebf-8c5d-a189a27963f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450466741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3450466741
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.847559973
Short name T157
Test name
Test status
Simulation time 110349417 ps
CPU time 1.12 seconds
Started Apr 18 02:24:54 PM PDT 24
Finished Apr 18 02:24:56 PM PDT 24
Peak memory 216272 kb
Host smart-e5232540-a6cb-4976-a983-432f1f33439e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847559973 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.847559973
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.851542600
Short name T332
Test name
Test status
Simulation time 25673422 ps
CPU time 0.9 seconds
Started Apr 18 02:24:55 PM PDT 24
Finished Apr 18 02:24:56 PM PDT 24
Peak memory 217668 kb
Host smart-f3d91187-023f-43d1-908e-7256b9d4ea49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851542600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.851542600
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.4103527667
Short name T736
Test name
Test status
Simulation time 69084873 ps
CPU time 1.66 seconds
Started Apr 18 02:24:54 PM PDT 24
Finished Apr 18 02:24:57 PM PDT 24
Peak memory 217872 kb
Host smart-69cb7421-f88d-49e0-9de9-60ba8e0ba131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103527667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.4103527667
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.239721829
Short name T708
Test name
Test status
Simulation time 22037366 ps
CPU time 1.14 seconds
Started Apr 18 02:24:54 PM PDT 24
Finished Apr 18 02:24:55 PM PDT 24
Peak memory 215296 kb
Host smart-ce93824c-49f1-4a54-a89c-fc214dd5198e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239721829 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.239721829
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.484675817
Short name T390
Test name
Test status
Simulation time 14905049 ps
CPU time 0.99 seconds
Started Apr 18 02:24:56 PM PDT 24
Finished Apr 18 02:24:57 PM PDT 24
Peak memory 215000 kb
Host smart-b8112a3c-1fda-4eee-931d-7e1aebd8aff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484675817 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.484675817
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1311908360
Short name T714
Test name
Test status
Simulation time 312830221 ps
CPU time 2.56 seconds
Started Apr 18 02:24:55 PM PDT 24
Finished Apr 18 02:24:58 PM PDT 24
Peak memory 216444 kb
Host smart-a1f44ba9-fda3-4624-b77e-b682c8582b2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311908360 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1311908360
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.887427574
Short name T190
Test name
Test status
Simulation time 68186960529 ps
CPU time 730.67 seconds
Started Apr 18 02:24:52 PM PDT 24
Finished Apr 18 02:37:04 PM PDT 24
Peak memory 219128 kb
Host smart-3fa87eca-51ae-4c0e-8ccd-26e56fbc0132
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887427574 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.887427574
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.3871092318
Short name T197
Test name
Test status
Simulation time 49072312 ps
CPU time 1.19 seconds
Started Apr 18 02:26:22 PM PDT 24
Finished Apr 18 02:26:24 PM PDT 24
Peak memory 215060 kb
Host smart-99202449-9465-4d18-861f-afeb9bb665af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871092318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3871092318
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.4253041532
Short name T10
Test name
Test status
Simulation time 58160869 ps
CPU time 1.47 seconds
Started Apr 18 02:26:25 PM PDT 24
Finished Apr 18 02:26:27 PM PDT 24
Peak memory 217804 kb
Host smart-44863bfb-3e86-4c0f-b5f1-0c155858463f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253041532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.4253041532
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.2113471507
Short name T374
Test name
Test status
Simulation time 37236271 ps
CPU time 1.59 seconds
Started Apr 18 02:26:24 PM PDT 24
Finished Apr 18 02:26:26 PM PDT 24
Peak memory 216540 kb
Host smart-9417455e-679d-4260-b701-3e4e21703ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113471507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2113471507
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1856838429
Short name T770
Test name
Test status
Simulation time 28105725 ps
CPU time 1.2 seconds
Started Apr 18 02:26:25 PM PDT 24
Finished Apr 18 02:26:27 PM PDT 24
Peak memory 216308 kb
Host smart-1cb85ca9-043b-46b0-9719-d81f465fc724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856838429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1856838429
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3179681837
Short name T705
Test name
Test status
Simulation time 75099415 ps
CPU time 1.36 seconds
Started Apr 18 02:26:24 PM PDT 24
Finished Apr 18 02:26:25 PM PDT 24
Peak memory 217784 kb
Host smart-f3eafdb4-2c5b-4a05-84d4-8c482d01aaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179681837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3179681837
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.3288573591
Short name T283
Test name
Test status
Simulation time 112257984 ps
CPU time 1.22 seconds
Started Apr 18 02:26:22 PM PDT 24
Finished Apr 18 02:26:24 PM PDT 24
Peak memory 216548 kb
Host smart-757880fa-9a77-482a-bff8-e2f0db2bccd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288573591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3288573591
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.771698069
Short name T450
Test name
Test status
Simulation time 37837009 ps
CPU time 1.45 seconds
Started Apr 18 02:26:25 PM PDT 24
Finished Apr 18 02:26:27 PM PDT 24
Peak memory 217532 kb
Host smart-b471dcfe-d439-4811-8e4e-bc268eff5ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771698069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.771698069
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.4205470081
Short name T232
Test name
Test status
Simulation time 117898978 ps
CPU time 1.13 seconds
Started Apr 18 02:26:25 PM PDT 24
Finished Apr 18 02:26:27 PM PDT 24
Peak memory 216544 kb
Host smart-9e6f723e-b0b2-47ae-a085-3268efbd3d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205470081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.4205470081
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.3705679813
Short name T452
Test name
Test status
Simulation time 58110901 ps
CPU time 1.64 seconds
Started Apr 18 02:26:22 PM PDT 24
Finished Apr 18 02:26:24 PM PDT 24
Peak memory 217560 kb
Host smart-466624ac-9e8a-4349-aacf-c9df67843d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705679813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3705679813
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1016210668
Short name T577
Test name
Test status
Simulation time 75872416 ps
CPU time 1.63 seconds
Started Apr 18 02:26:25 PM PDT 24
Finished Apr 18 02:26:27 PM PDT 24
Peak memory 217804 kb
Host smart-1b29a8f1-2fd6-4e50-9964-9980deabde6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016210668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1016210668
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert_test.1483521573
Short name T753
Test name
Test status
Simulation time 18315831 ps
CPU time 0.83 seconds
Started Apr 18 02:25:00 PM PDT 24
Finished Apr 18 02:25:02 PM PDT 24
Peak memory 205552 kb
Host smart-5b90aa24-cfe0-4c70-9df7-1f5413311ce9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483521573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1483521573
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_err.3467378782
Short name T80
Test name
Test status
Simulation time 22997597 ps
CPU time 0.95 seconds
Started Apr 18 02:24:55 PM PDT 24
Finished Apr 18 02:24:57 PM PDT 24
Peak memory 217704 kb
Host smart-7e120e69-8bd5-42a6-b95c-f41868030f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467378782 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3467378782
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2002105497
Short name T573
Test name
Test status
Simulation time 120390522 ps
CPU time 1.47 seconds
Started Apr 18 02:24:55 PM PDT 24
Finished Apr 18 02:24:57 PM PDT 24
Peak memory 218184 kb
Host smart-905b9ec2-0112-4c3b-aec3-bcac8f046692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002105497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2002105497
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3579913283
Short name T838
Test name
Test status
Simulation time 19774089 ps
CPU time 1.07 seconds
Started Apr 18 02:24:54 PM PDT 24
Finished Apr 18 02:24:56 PM PDT 24
Peak memory 215468 kb
Host smart-718155ef-b0d7-4650-945b-3c3b5d23b9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579913283 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3579913283
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2678524685
Short name T479
Test name
Test status
Simulation time 47766437 ps
CPU time 0.92 seconds
Started Apr 18 02:24:53 PM PDT 24
Finished Apr 18 02:24:54 PM PDT 24
Peak memory 215024 kb
Host smart-436aabb6-2a99-46ea-8d8e-3d1fe28636a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678524685 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2678524685
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3506719837
Short name T476
Test name
Test status
Simulation time 157608781 ps
CPU time 3.61 seconds
Started Apr 18 02:24:52 PM PDT 24
Finished Apr 18 02:24:56 PM PDT 24
Peak memory 216228 kb
Host smart-1e6c71b2-801b-46e4-852e-63da6d73b86c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506719837 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3506719837
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.4173281497
Short name T619
Test name
Test status
Simulation time 201296535890 ps
CPU time 1894.65 seconds
Started Apr 18 02:24:56 PM PDT 24
Finished Apr 18 02:56:31 PM PDT 24
Peak memory 225040 kb
Host smart-8ead6ee1-eee6-453f-aaee-7deaa1691f41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173281497 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.4173281497
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.2624064747
Short name T328
Test name
Test status
Simulation time 41105987 ps
CPU time 1.16 seconds
Started Apr 18 02:26:21 PM PDT 24
Finished Apr 18 02:26:23 PM PDT 24
Peak memory 217872 kb
Host smart-aa77835c-375a-4dab-a8da-ad3c2007a691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624064747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2624064747
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.1946117504
Short name T671
Test name
Test status
Simulation time 80750444 ps
CPU time 1.04 seconds
Started Apr 18 02:26:38 PM PDT 24
Finished Apr 18 02:26:39 PM PDT 24
Peak memory 216436 kb
Host smart-9d3d6166-144a-4d28-90e1-7606f36ebecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946117504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1946117504
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.1500241541
Short name T463
Test name
Test status
Simulation time 174329837 ps
CPU time 3.64 seconds
Started Apr 18 02:26:23 PM PDT 24
Finished Apr 18 02:26:27 PM PDT 24
Peak memory 216576 kb
Host smart-e61f4d5e-c1d5-41df-a94d-bbc0f52a89a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500241541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1500241541
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.3568920773
Short name T442
Test name
Test status
Simulation time 53293777 ps
CPU time 1.83 seconds
Started Apr 18 02:26:25 PM PDT 24
Finished Apr 18 02:26:27 PM PDT 24
Peak memory 219164 kb
Host smart-bf41caa9-e40c-414e-a1c6-73bab6331b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568920773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3568920773
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1785601752
Short name T548
Test name
Test status
Simulation time 53598343 ps
CPU time 1.56 seconds
Started Apr 18 02:26:25 PM PDT 24
Finished Apr 18 02:26:27 PM PDT 24
Peak memory 217628 kb
Host smart-6b9680be-0738-46b7-ab70-df248067bbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785601752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1785601752
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.3823770443
Short name T272
Test name
Test status
Simulation time 85766135 ps
CPU time 2.01 seconds
Started Apr 18 02:26:23 PM PDT 24
Finished Apr 18 02:26:25 PM PDT 24
Peak memory 217892 kb
Host smart-61733bf6-fd2e-410c-9c8d-5128319321a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823770443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3823770443
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.2506544740
Short name T561
Test name
Test status
Simulation time 24866275 ps
CPU time 1.26 seconds
Started Apr 18 02:26:24 PM PDT 24
Finished Apr 18 02:26:26 PM PDT 24
Peak memory 216372 kb
Host smart-e94b9489-1484-4190-9f3a-a71790da31a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506544740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2506544740
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.4207302551
Short name T484
Test name
Test status
Simulation time 39739922 ps
CPU time 1.14 seconds
Started Apr 18 02:26:24 PM PDT 24
Finished Apr 18 02:26:26 PM PDT 24
Peak memory 216492 kb
Host smart-f2bbefa9-2f42-483f-9628-e3d6fe4ff1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207302551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.4207302551
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.1594585895
Short name T779
Test name
Test status
Simulation time 79776833 ps
CPU time 2 seconds
Started Apr 18 02:26:23 PM PDT 24
Finished Apr 18 02:26:26 PM PDT 24
Peak memory 216588 kb
Host smart-74fcb504-633a-4862-a6e5-6a85bf32fd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594585895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1594585895
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.2430824965
Short name T233
Test name
Test status
Simulation time 203142252 ps
CPU time 1.28 seconds
Started Apr 18 02:26:28 PM PDT 24
Finished Apr 18 02:26:29 PM PDT 24
Peak memory 217972 kb
Host smart-b2b73c74-57f8-4232-b053-5389ecb687a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430824965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2430824965
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3086813342
Short name T241
Test name
Test status
Simulation time 87973231 ps
CPU time 1.24 seconds
Started Apr 18 02:24:58 PM PDT 24
Finished Apr 18 02:25:00 PM PDT 24
Peak memory 215636 kb
Host smart-9851e879-da38-489c-8bed-a7098d49c978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086813342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3086813342
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3867375424
Short name T576
Test name
Test status
Simulation time 27767845 ps
CPU time 0.91 seconds
Started Apr 18 02:24:59 PM PDT 24
Finished Apr 18 02:25:00 PM PDT 24
Peak memory 206392 kb
Host smart-1418bb79-43b6-4531-910e-8a24d24fccad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867375424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3867375424
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1601971696
Short name T563
Test name
Test status
Simulation time 14017041 ps
CPU time 0.91 seconds
Started Apr 18 02:24:58 PM PDT 24
Finished Apr 18 02:24:59 PM PDT 24
Peak memory 215536 kb
Host smart-ad95fc4f-70d6-4cd1-bfaa-ddfd887afbe9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601971696 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1601971696
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2323541616
Short name T139
Test name
Test status
Simulation time 75766727 ps
CPU time 1 seconds
Started Apr 18 02:25:06 PM PDT 24
Finished Apr 18 02:25:07 PM PDT 24
Peak memory 217336 kb
Host smart-8ad74b6b-7055-4e52-9027-e8a7b7799d83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323541616 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2323541616
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.3152573559
Short name T68
Test name
Test status
Simulation time 70605650 ps
CPU time 0.81 seconds
Started Apr 18 02:24:59 PM PDT 24
Finished Apr 18 02:25:00 PM PDT 24
Peak memory 217844 kb
Host smart-8ba8ba77-04f4-4850-ad88-bb6029d1fa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152573559 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3152573559
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2439475616
Short name T400
Test name
Test status
Simulation time 68175169 ps
CPU time 2.63 seconds
Started Apr 18 02:24:58 PM PDT 24
Finished Apr 18 02:25:01 PM PDT 24
Peak memory 219180 kb
Host smart-01f90cc8-c5da-416d-9036-089d32b6a8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439475616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2439475616
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.234722282
Short name T97
Test name
Test status
Simulation time 22200999 ps
CPU time 1.11 seconds
Started Apr 18 02:25:02 PM PDT 24
Finished Apr 18 02:25:03 PM PDT 24
Peak memory 215272 kb
Host smart-09473e28-760c-45a8-aa40-6e0a3ea1b0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234722282 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.234722282
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2449420931
Short name T120
Test name
Test status
Simulation time 19205335 ps
CPU time 0.97 seconds
Started Apr 18 02:24:57 PM PDT 24
Finished Apr 18 02:24:59 PM PDT 24
Peak memory 215016 kb
Host smart-7dc53771-de06-48c9-9ae7-9e62b4121925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449420931 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2449420931
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.531983772
Short name T807
Test name
Test status
Simulation time 215322949 ps
CPU time 4.33 seconds
Started Apr 18 02:24:57 PM PDT 24
Finished Apr 18 02:25:02 PM PDT 24
Peak memory 215004 kb
Host smart-9f1969b4-7b63-487c-8e0c-2f849563d58c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531983772 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.531983772
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1610599998
Short name T423
Test name
Test status
Simulation time 160383051692 ps
CPU time 905.89 seconds
Started Apr 18 02:25:06 PM PDT 24
Finished Apr 18 02:40:12 PM PDT 24
Peak memory 221088 kb
Host smart-965bf055-41be-4491-b8ac-fd61165ad22d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610599998 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1610599998
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.817411231
Short name T309
Test name
Test status
Simulation time 182074075 ps
CPU time 1.47 seconds
Started Apr 18 02:26:26 PM PDT 24
Finished Apr 18 02:26:29 PM PDT 24
Peak memory 218100 kb
Host smart-d7ea2dba-8737-496c-9bc2-c1707031cc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817411231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.817411231
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.3023765709
Short name T126
Test name
Test status
Simulation time 43478330 ps
CPU time 1.05 seconds
Started Apr 18 02:26:34 PM PDT 24
Finished Apr 18 02:26:36 PM PDT 24
Peak memory 216408 kb
Host smart-caa90013-505c-4fa4-af15-a42d36dcd605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023765709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3023765709
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.56198181
Short name T658
Test name
Test status
Simulation time 87264462 ps
CPU time 1.45 seconds
Started Apr 18 02:26:30 PM PDT 24
Finished Apr 18 02:26:32 PM PDT 24
Peak memory 216436 kb
Host smart-926428d4-5f18-44d6-a5a8-ee959d2fbf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56198181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.56198181
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.183469638
Short name T411
Test name
Test status
Simulation time 47933582 ps
CPU time 1 seconds
Started Apr 18 02:26:33 PM PDT 24
Finished Apr 18 02:26:35 PM PDT 24
Peak memory 216364 kb
Host smart-2262e89b-d016-4c65-8fb7-76203c40a230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183469638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.183469638
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.3366309645
Short name T598
Test name
Test status
Simulation time 57672436 ps
CPU time 1.07 seconds
Started Apr 18 02:26:29 PM PDT 24
Finished Apr 18 02:26:30 PM PDT 24
Peak memory 216720 kb
Host smart-8893b6f7-9e3a-4d6a-b217-f45bca796f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366309645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3366309645
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.4145445045
Short name T538
Test name
Test status
Simulation time 82384019 ps
CPU time 2 seconds
Started Apr 18 02:26:29 PM PDT 24
Finished Apr 18 02:26:31 PM PDT 24
Peak memory 218008 kb
Host smart-c98d0620-ddbb-4560-a6b3-0f638d65bc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145445045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.4145445045
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.2271777057
Short name T635
Test name
Test status
Simulation time 65906525 ps
CPU time 1.07 seconds
Started Apr 18 02:26:27 PM PDT 24
Finished Apr 18 02:26:29 PM PDT 24
Peak memory 216524 kb
Host smart-7ef6c7fd-1c8b-4972-8cea-eb4aa213cf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271777057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2271777057
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.633293424
Short name T231
Test name
Test status
Simulation time 47894708 ps
CPU time 1.28 seconds
Started Apr 18 02:26:32 PM PDT 24
Finished Apr 18 02:26:34 PM PDT 24
Peak memory 216492 kb
Host smart-e7ce5860-6b4e-497a-98ac-d7e3d8f269ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633293424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.633293424
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2085937849
Short name T537
Test name
Test status
Simulation time 121623016 ps
CPU time 1.39 seconds
Started Apr 18 02:26:27 PM PDT 24
Finished Apr 18 02:26:30 PM PDT 24
Peak memory 217796 kb
Host smart-1ef13544-25b3-47aa-ac8c-2be0786b51b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085937849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2085937849
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.1502678000
Short name T361
Test name
Test status
Simulation time 38694928 ps
CPU time 1.79 seconds
Started Apr 18 02:26:29 PM PDT 24
Finished Apr 18 02:26:31 PM PDT 24
Peak memory 217712 kb
Host smart-18e78b5a-9bcb-42a0-bdd8-7f00e817efbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502678000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1502678000
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.197221275
Short name T500
Test name
Test status
Simulation time 51448827 ps
CPU time 1.25 seconds
Started Apr 18 02:25:00 PM PDT 24
Finished Apr 18 02:25:02 PM PDT 24
Peak memory 215392 kb
Host smart-75b803ab-cd96-4ad8-832b-cf9658d71c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197221275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.197221275
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1348307197
Short name T460
Test name
Test status
Simulation time 14435619 ps
CPU time 0.95 seconds
Started Apr 18 02:25:05 PM PDT 24
Finished Apr 18 02:25:06 PM PDT 24
Peak memory 205892 kb
Host smart-a0620b51-874b-429d-9bcc-3edd2f9c6ee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348307197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1348307197
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.4171224068
Short name T179
Test name
Test status
Simulation time 17451014 ps
CPU time 0.87 seconds
Started Apr 18 02:25:04 PM PDT 24
Finished Apr 18 02:25:06 PM PDT 24
Peak memory 215720 kb
Host smart-aaf12e8f-6898-479f-b916-9ff08c79e87e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171224068 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.4171224068
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.777224094
Short name T312
Test name
Test status
Simulation time 50958171 ps
CPU time 1.03 seconds
Started Apr 18 02:25:04 PM PDT 24
Finished Apr 18 02:25:06 PM PDT 24
Peak memory 216304 kb
Host smart-513f8420-00a0-4ba8-abd8-804ae1fb06c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777224094 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.777224094
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1844889458
Short name T162
Test name
Test status
Simulation time 19440615 ps
CPU time 1.13 seconds
Started Apr 18 02:25:00 PM PDT 24
Finished Apr 18 02:25:01 PM PDT 24
Peak memory 217872 kb
Host smart-34787e36-f6c3-47f2-957a-e4953c6f82b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844889458 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1844889458
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2796581035
Short name T784
Test name
Test status
Simulation time 35515370 ps
CPU time 1.9 seconds
Started Apr 18 02:25:07 PM PDT 24
Finished Apr 18 02:25:09 PM PDT 24
Peak memory 217656 kb
Host smart-11948524-7922-4804-bfab-2f8c0754f9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796581035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2796581035
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2883230998
Short name T451
Test name
Test status
Simulation time 37650711 ps
CPU time 0.93 seconds
Started Apr 18 02:24:58 PM PDT 24
Finished Apr 18 02:25:00 PM PDT 24
Peak memory 215060 kb
Host smart-5d8c4fc6-c26f-4a8c-a589-56be18dc2b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883230998 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2883230998
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3327591983
Short name T522
Test name
Test status
Simulation time 15985605 ps
CPU time 0.99 seconds
Started Apr 18 02:24:58 PM PDT 24
Finished Apr 18 02:24:59 PM PDT 24
Peak memory 215060 kb
Host smart-5ab917c1-8ebe-49e0-ab09-60f4a01417d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327591983 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3327591983
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2240600073
Short name T490
Test name
Test status
Simulation time 171943151 ps
CPU time 1.58 seconds
Started Apr 18 02:24:59 PM PDT 24
Finished Apr 18 02:25:01 PM PDT 24
Peak memory 216316 kb
Host smart-7625c6c2-fd82-4c34-856f-7d615da6f71d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240600073 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2240600073
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.863930748
Short name T466
Test name
Test status
Simulation time 100748404009 ps
CPU time 1377.43 seconds
Started Apr 18 02:24:59 PM PDT 24
Finished Apr 18 02:47:57 PM PDT 24
Peak memory 224804 kb
Host smart-531fdd90-23d6-46de-9a2b-3da2d15bac21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863930748 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.863930748
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.4043088988
Short name T273
Test name
Test status
Simulation time 40589016 ps
CPU time 1.11 seconds
Started Apr 18 02:26:26 PM PDT 24
Finished Apr 18 02:26:27 PM PDT 24
Peak memory 216392 kb
Host smart-576281f1-2885-4a9f-9663-79661b0b7846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043088988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.4043088988
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.2162265178
Short name T24
Test name
Test status
Simulation time 43288621 ps
CPU time 1.78 seconds
Started Apr 18 02:26:32 PM PDT 24
Finished Apr 18 02:26:34 PM PDT 24
Peak memory 217616 kb
Host smart-8a710e9a-653c-4260-a282-9dbd09edb6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162265178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2162265178
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.1339438435
Short name T540
Test name
Test status
Simulation time 70186069 ps
CPU time 1.13 seconds
Started Apr 18 02:26:33 PM PDT 24
Finished Apr 18 02:26:35 PM PDT 24
Peak memory 217800 kb
Host smart-1e509cc8-7752-4e9c-b56b-bcc1bf08cc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339438435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1339438435
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2987734703
Short name T507
Test name
Test status
Simulation time 53811998 ps
CPU time 1.5 seconds
Started Apr 18 02:26:27 PM PDT 24
Finished Apr 18 02:26:29 PM PDT 24
Peak memory 217872 kb
Host smart-2c01a40a-2dd7-41e5-803c-9a23c5b7ac23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987734703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2987734703
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3638196948
Short name T633
Test name
Test status
Simulation time 59143073 ps
CPU time 1.26 seconds
Started Apr 18 02:26:29 PM PDT 24
Finished Apr 18 02:26:31 PM PDT 24
Peak memory 216308 kb
Host smart-e12a0d01-8ebd-4749-b06b-5364770df2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638196948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3638196948
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.2647108481
Short name T525
Test name
Test status
Simulation time 226709597 ps
CPU time 2.98 seconds
Started Apr 18 02:26:32 PM PDT 24
Finished Apr 18 02:26:36 PM PDT 24
Peak memory 219020 kb
Host smart-15aa2f3b-7a17-48dc-a802-81aade6df0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647108481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2647108481
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.831086288
Short name T462
Test name
Test status
Simulation time 36230135 ps
CPU time 1.38 seconds
Started Apr 18 02:26:27 PM PDT 24
Finished Apr 18 02:26:29 PM PDT 24
Peak memory 217548 kb
Host smart-a52a865f-233b-49e7-b9e1-1df89b411f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831086288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.831086288
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.698910471
Short name T628
Test name
Test status
Simulation time 142666049 ps
CPU time 1.81 seconds
Started Apr 18 02:26:30 PM PDT 24
Finished Apr 18 02:26:32 PM PDT 24
Peak memory 217916 kb
Host smart-4b41fe3a-9c04-4c75-b6c1-b28ebe4a3818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698910471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.698910471
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.3382423156
Short name T696
Test name
Test status
Simulation time 75338226 ps
CPU time 2.72 seconds
Started Apr 18 02:26:28 PM PDT 24
Finished Apr 18 02:26:31 PM PDT 24
Peak memory 217600 kb
Host smart-00a4932b-b3e9-4eaf-93df-cf0a5becf0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382423156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3382423156
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2895584903
Short name T248
Test name
Test status
Simulation time 23713111 ps
CPU time 1.19 seconds
Started Apr 18 02:25:03 PM PDT 24
Finished Apr 18 02:25:05 PM PDT 24
Peak memory 215368 kb
Host smart-f333b107-0407-463f-90c9-a028ef029b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895584903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2895584903
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.734654151
Short name T330
Test name
Test status
Simulation time 17231735 ps
CPU time 0.93 seconds
Started Apr 18 02:25:08 PM PDT 24
Finished Apr 18 02:25:09 PM PDT 24
Peak memory 205820 kb
Host smart-b17470f0-162f-4af4-b6fc-d904f3c7e13a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734654151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.734654151
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.1915886315
Short name T77
Test name
Test status
Simulation time 10907662 ps
CPU time 0.9 seconds
Started Apr 18 02:25:04 PM PDT 24
Finished Apr 18 02:25:05 PM PDT 24
Peak memory 215604 kb
Host smart-84a9bbe0-c71f-483a-9140-1e98a289be02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915886315 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1915886315
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.121103774
Short name T335
Test name
Test status
Simulation time 40233109 ps
CPU time 1.07 seconds
Started Apr 18 02:25:04 PM PDT 24
Finished Apr 18 02:25:06 PM PDT 24
Peak memory 216032 kb
Host smart-3d1a6ec9-3dcd-439a-bb36-cb01095be76f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121103774 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.121103774
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.499505595
Short name T661
Test name
Test status
Simulation time 20915388 ps
CPU time 0.95 seconds
Started Apr 18 02:25:03 PM PDT 24
Finished Apr 18 02:25:05 PM PDT 24
Peak memory 217720 kb
Host smart-8e5a6389-93e8-4550-9343-3f64608841b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499505595 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.499505595
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3096700730
Short name T723
Test name
Test status
Simulation time 70257503 ps
CPU time 1.48 seconds
Started Apr 18 02:25:04 PM PDT 24
Finished Apr 18 02:25:06 PM PDT 24
Peak memory 217612 kb
Host smart-c4a3551b-6f98-445e-b9b9-dfbf8c7a1555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096700730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3096700730
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.4158627091
Short name T558
Test name
Test status
Simulation time 21737591 ps
CPU time 1.09 seconds
Started Apr 18 02:25:04 PM PDT 24
Finished Apr 18 02:25:05 PM PDT 24
Peak memory 215148 kb
Host smart-bd128e8f-6ee1-49e3-808c-9dc2ec355abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158627091 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.4158627091
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1177755397
Short name T638
Test name
Test status
Simulation time 19693855 ps
CPU time 0.92 seconds
Started Apr 18 02:25:03 PM PDT 24
Finished Apr 18 02:25:05 PM PDT 24
Peak memory 215020 kb
Host smart-efed86f0-2a0c-4fb7-9496-88d59754c74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177755397 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1177755397
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1359775017
Short name T343
Test name
Test status
Simulation time 427771161 ps
CPU time 2.61 seconds
Started Apr 18 02:25:05 PM PDT 24
Finished Apr 18 02:25:08 PM PDT 24
Peak memory 215004 kb
Host smart-b849bba2-24ee-485a-8366-c6a3ae8c1c8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359775017 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1359775017
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1213737989
Short name T110
Test name
Test status
Simulation time 104213695668 ps
CPU time 1348.32 seconds
Started Apr 18 02:25:03 PM PDT 24
Finished Apr 18 02:47:32 PM PDT 24
Peak memory 225008 kb
Host smart-546f8f15-056d-408e-b1b1-7a723ffbc42d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213737989 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1213737989
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.3190963416
Short name T665
Test name
Test status
Simulation time 36537384 ps
CPU time 1.36 seconds
Started Apr 18 02:26:27 PM PDT 24
Finished Apr 18 02:26:29 PM PDT 24
Peak memory 217364 kb
Host smart-2f4c3bb0-f956-4ea7-ac66-3702b7238c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190963416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3190963416
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.3204702571
Short name T735
Test name
Test status
Simulation time 190838538 ps
CPU time 2.06 seconds
Started Apr 18 02:26:30 PM PDT 24
Finished Apr 18 02:26:33 PM PDT 24
Peak memory 217720 kb
Host smart-94882454-9a44-4af9-ad9b-dc8c49fd5b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204702571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3204702571
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.2054965910
Short name T800
Test name
Test status
Simulation time 40987787 ps
CPU time 1.63 seconds
Started Apr 18 02:26:29 PM PDT 24
Finished Apr 18 02:26:31 PM PDT 24
Peak memory 218892 kb
Host smart-09df165b-e3f3-4325-97f1-f7b5c693eb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054965910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2054965910
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.2515449396
Short name T709
Test name
Test status
Simulation time 51773659 ps
CPU time 1.39 seconds
Started Apr 18 02:26:38 PM PDT 24
Finished Apr 18 02:26:40 PM PDT 24
Peak memory 216488 kb
Host smart-fdc8cc8e-3223-4db2-9637-bee167e405a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515449396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2515449396
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2663464518
Short name T520
Test name
Test status
Simulation time 88039624 ps
CPU time 1.15 seconds
Started Apr 18 02:26:33 PM PDT 24
Finished Apr 18 02:26:35 PM PDT 24
Peak memory 216484 kb
Host smart-1584b672-9fcb-4667-a75c-293b3ffab01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663464518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2663464518
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.4210876091
Short name T364
Test name
Test status
Simulation time 43806955 ps
CPU time 1.37 seconds
Started Apr 18 02:26:33 PM PDT 24
Finished Apr 18 02:26:36 PM PDT 24
Peak memory 216456 kb
Host smart-ef78e03c-3379-4a37-ac7d-18f003fd9086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210876091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.4210876091
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1909477898
Short name T704
Test name
Test status
Simulation time 120618112 ps
CPU time 2.7 seconds
Started Apr 18 02:26:32 PM PDT 24
Finished Apr 18 02:26:35 PM PDT 24
Peak memory 216436 kb
Host smart-56519e35-eb06-45ae-a9ea-ff149026cf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909477898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1909477898
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.1767990223
Short name T348
Test name
Test status
Simulation time 45402043 ps
CPU time 1.44 seconds
Started Apr 18 02:26:34 PM PDT 24
Finished Apr 18 02:26:36 PM PDT 24
Peak memory 217688 kb
Host smart-b0463dc3-710a-42c3-a793-7ec569a5ffd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767990223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1767990223
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.2433390871
Short name T632
Test name
Test status
Simulation time 14971361 ps
CPU time 0.91 seconds
Started Apr 18 02:25:09 PM PDT 24
Finished Apr 18 02:25:10 PM PDT 24
Peak memory 206452 kb
Host smart-3a2d4195-cecd-4465-92cf-02a3543202a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433390871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2433390871
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.89899885
Short name T65
Test name
Test status
Simulation time 32567961 ps
CPU time 0.84 seconds
Started Apr 18 02:25:07 PM PDT 24
Finished Apr 18 02:25:08 PM PDT 24
Peak memory 215584 kb
Host smart-a7ff85de-125c-4821-a0fc-edb6d7fb6608
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89899885 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.89899885
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2125399032
Short name T667
Test name
Test status
Simulation time 144263463 ps
CPU time 1.09 seconds
Started Apr 18 02:25:11 PM PDT 24
Finished Apr 18 02:25:13 PM PDT 24
Peak memory 215424 kb
Host smart-97bf15db-07c6-4dc6-8598-cac042147fb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125399032 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2125399032
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1540552629
Short name T300
Test name
Test status
Simulation time 23424815 ps
CPU time 0.87 seconds
Started Apr 18 02:25:05 PM PDT 24
Finished Apr 18 02:25:07 PM PDT 24
Peak memory 217508 kb
Host smart-41978207-b4f2-468f-b90e-39449bee64d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540552629 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1540552629
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2775110062
Short name T410
Test name
Test status
Simulation time 66028970 ps
CPU time 1.25 seconds
Started Apr 18 02:25:07 PM PDT 24
Finished Apr 18 02:25:09 PM PDT 24
Peak memory 217776 kb
Host smart-1ae819f9-f7d9-47b1-b13d-1360056bab28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775110062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2775110062
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.2539090123
Short name T554
Test name
Test status
Simulation time 26350964 ps
CPU time 0.93 seconds
Started Apr 18 02:25:05 PM PDT 24
Finished Apr 18 02:25:06 PM PDT 24
Peak memory 215008 kb
Host smart-f8b72ee9-d103-4a44-a8e4-5f6c918ebde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539090123 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2539090123
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.962781337
Short name T761
Test name
Test status
Simulation time 414379123 ps
CPU time 1.36 seconds
Started Apr 18 02:25:05 PM PDT 24
Finished Apr 18 02:25:07 PM PDT 24
Peak memory 216216 kb
Host smart-1bcaa271-0ab3-407b-a056-cae32076a16b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962781337 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.962781337
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.4288413516
Short name T398
Test name
Test status
Simulation time 72289766552 ps
CPU time 438.55 seconds
Started Apr 18 02:25:04 PM PDT 24
Finished Apr 18 02:32:23 PM PDT 24
Peak memory 217468 kb
Host smart-274bc181-eb0d-49ce-871d-4451c5f1a70a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288413516 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.4288413516
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.454820277
Short name T337
Test name
Test status
Simulation time 99206162 ps
CPU time 1.47 seconds
Started Apr 18 02:26:34 PM PDT 24
Finished Apr 18 02:26:36 PM PDT 24
Peak memory 218028 kb
Host smart-28111414-74a1-4f74-a181-b76e23ace526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454820277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.454820277
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.976882269
Short name T625
Test name
Test status
Simulation time 56061282 ps
CPU time 1.94 seconds
Started Apr 18 02:26:33 PM PDT 24
Finished Apr 18 02:26:36 PM PDT 24
Peak memory 217628 kb
Host smart-d4754b1f-fcb9-480c-960e-bcf986cf5b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976882269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.976882269
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.194200550
Short name T712
Test name
Test status
Simulation time 304261116 ps
CPU time 2.21 seconds
Started Apr 18 02:26:36 PM PDT 24
Finished Apr 18 02:26:39 PM PDT 24
Peak memory 217696 kb
Host smart-14734c8e-4a12-4bb9-a3be-623c48a04dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194200550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.194200550
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.3200142058
Short name T512
Test name
Test status
Simulation time 44556434 ps
CPU time 1.67 seconds
Started Apr 18 02:26:32 PM PDT 24
Finished Apr 18 02:26:34 PM PDT 24
Peak memory 216548 kb
Host smart-b0138b71-1463-4d7e-9cc5-62d7a7d91529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200142058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3200142058
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.3389060218
Short name T808
Test name
Test status
Simulation time 57263365 ps
CPU time 1.65 seconds
Started Apr 18 02:26:34 PM PDT 24
Finished Apr 18 02:26:36 PM PDT 24
Peak memory 218500 kb
Host smart-f50e3b6d-2671-4bfc-9c58-d627c86e9253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389060218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3389060218
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.2143982347
Short name T315
Test name
Test status
Simulation time 75647579 ps
CPU time 1.12 seconds
Started Apr 18 02:26:36 PM PDT 24
Finished Apr 18 02:26:37 PM PDT 24
Peak memory 216432 kb
Host smart-02ad7a64-e441-478e-91fb-9b9b105e1df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143982347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2143982347
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.3971577904
Short name T653
Test name
Test status
Simulation time 345637112 ps
CPU time 1.39 seconds
Started Apr 18 02:26:36 PM PDT 24
Finished Apr 18 02:26:38 PM PDT 24
Peak memory 216456 kb
Host smart-007ee324-5e8a-452b-bbdd-28b5337fd6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971577904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3971577904
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.405831395
Short name T657
Test name
Test status
Simulation time 84748290 ps
CPU time 1.13 seconds
Started Apr 18 02:26:34 PM PDT 24
Finished Apr 18 02:26:36 PM PDT 24
Peak memory 216400 kb
Host smart-246fc7eb-2cae-4532-b217-2a056dc2e467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405831395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.405831395
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.2311005351
Short name T827
Test name
Test status
Simulation time 61977691 ps
CPU time 1.25 seconds
Started Apr 18 02:26:33 PM PDT 24
Finished Apr 18 02:26:36 PM PDT 24
Peak memory 217556 kb
Host smart-2e0c03b0-1585-4818-8482-b5273188da47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311005351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2311005351
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.2045436103
Short name T299
Test name
Test status
Simulation time 97900701 ps
CPU time 1.06 seconds
Started Apr 18 02:26:33 PM PDT 24
Finished Apr 18 02:26:35 PM PDT 24
Peak memory 216184 kb
Host smart-6ad16588-9cc0-40d8-b695-b879814fc537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045436103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2045436103
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1141828363
Short name T259
Test name
Test status
Simulation time 31502297 ps
CPU time 1.35 seconds
Started Apr 18 02:25:12 PM PDT 24
Finished Apr 18 02:25:14 PM PDT 24
Peak memory 215380 kb
Host smart-4fe8b8f9-578c-4459-a8b9-36d912d6dc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141828363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1141828363
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2821484143
Short name T322
Test name
Test status
Simulation time 22716188 ps
CPU time 0.86 seconds
Started Apr 18 02:25:19 PM PDT 24
Finished Apr 18 02:25:20 PM PDT 24
Peak memory 205868 kb
Host smart-6fc9a2ed-6a80-4e1a-b5e4-891c8f6f965c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821484143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2821484143
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.753301241
Short name T550
Test name
Test status
Simulation time 31425574 ps
CPU time 0.85 seconds
Started Apr 18 02:25:12 PM PDT 24
Finished Apr 18 02:25:14 PM PDT 24
Peak memory 215600 kb
Host smart-d9dcd0ad-d60b-4299-915a-a8ce4334f909
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753301241 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.753301241
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.203770816
Short name T600
Test name
Test status
Simulation time 61366421 ps
CPU time 1.18 seconds
Started Apr 18 02:25:10 PM PDT 24
Finished Apr 18 02:25:12 PM PDT 24
Peak memory 217528 kb
Host smart-c314f50c-935e-4e40-a449-03993bd1445e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203770816 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.203770816
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2189772180
Short name T55
Test name
Test status
Simulation time 47548011 ps
CPU time 0.99 seconds
Started Apr 18 02:25:20 PM PDT 24
Finished Apr 18 02:25:21 PM PDT 24
Peak memory 219148 kb
Host smart-f4f1b568-97f8-4783-bc9f-eb1e54673ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189772180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2189772180
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.4017162
Short name T797
Test name
Test status
Simulation time 42167516 ps
CPU time 1.3 seconds
Started Apr 18 02:25:13 PM PDT 24
Finished Apr 18 02:25:15 PM PDT 24
Peak memory 217552 kb
Host smart-fb8ddb5c-eb0d-4cdd-9b97-66e316dba953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.4017162
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2417980019
Short name T491
Test name
Test status
Simulation time 22405118 ps
CPU time 1.1 seconds
Started Apr 18 02:25:27 PM PDT 24
Finished Apr 18 02:25:29 PM PDT 24
Peak memory 215664 kb
Host smart-cea59db9-cd38-4787-9ad6-a72d2e2e8f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417980019 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2417980019
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.787253572
Short name T641
Test name
Test status
Simulation time 26459796 ps
CPU time 0.95 seconds
Started Apr 18 02:25:10 PM PDT 24
Finished Apr 18 02:25:11 PM PDT 24
Peak memory 214976 kb
Host smart-2de0a7c6-be17-4e3f-99bf-ca7fd019d2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787253572 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.787253572
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1116298851
Short name T152
Test name
Test status
Simulation time 515331205 ps
CPU time 4.86 seconds
Started Apr 18 02:25:27 PM PDT 24
Finished Apr 18 02:25:33 PM PDT 24
Peak memory 215080 kb
Host smart-4e7ddbb7-812f-49b5-b7b1-dd7cbf1e4b58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116298851 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1116298851
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1380219428
Short name T397
Test name
Test status
Simulation time 83152255888 ps
CPU time 956.02 seconds
Started Apr 18 02:25:10 PM PDT 24
Finished Apr 18 02:41:06 PM PDT 24
Peak memory 221188 kb
Host smart-5fa4aac5-69d9-44e0-bf82-af4105a2dc9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380219428 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1380219428
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.1326409449
Short name T728
Test name
Test status
Simulation time 52296232 ps
CPU time 1.48 seconds
Started Apr 18 02:26:33 PM PDT 24
Finished Apr 18 02:26:36 PM PDT 24
Peak memory 216220 kb
Host smart-7fb48066-d41e-4672-b90b-9bdf1836c8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326409449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1326409449
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.1699061009
Short name T504
Test name
Test status
Simulation time 300050467 ps
CPU time 1.68 seconds
Started Apr 18 02:26:33 PM PDT 24
Finished Apr 18 02:26:35 PM PDT 24
Peak memory 219336 kb
Host smart-c3083429-c43c-404c-9900-c846216ecb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699061009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1699061009
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.2354715757
Short name T331
Test name
Test status
Simulation time 80246464 ps
CPU time 1.31 seconds
Started Apr 18 02:26:34 PM PDT 24
Finished Apr 18 02:26:36 PM PDT 24
Peak memory 218080 kb
Host smart-704844fa-36e7-4922-98f3-f5d1ea5f2ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354715757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2354715757
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.2946522052
Short name T437
Test name
Test status
Simulation time 51324317 ps
CPU time 1.35 seconds
Started Apr 18 02:26:33 PM PDT 24
Finished Apr 18 02:26:36 PM PDT 24
Peak memory 217736 kb
Host smart-4b14f4ee-b7cb-4791-97dc-c865438a8415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946522052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2946522052
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.620576550
Short name T586
Test name
Test status
Simulation time 162003084 ps
CPU time 1.74 seconds
Started Apr 18 02:26:33 PM PDT 24
Finished Apr 18 02:26:35 PM PDT 24
Peak memory 218072 kb
Host smart-3db8e4a9-5fdd-4b1d-9ea9-64d0d916a091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620576550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.620576550
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.1915397593
Short name T618
Test name
Test status
Simulation time 54372740 ps
CPU time 1.06 seconds
Started Apr 18 02:26:34 PM PDT 24
Finished Apr 18 02:26:36 PM PDT 24
Peak memory 216236 kb
Host smart-f18a67d0-e379-44cd-b816-e7ffac1a44c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915397593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1915397593
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.180969338
Short name T739
Test name
Test status
Simulation time 82398687 ps
CPU time 1.25 seconds
Started Apr 18 02:26:33 PM PDT 24
Finished Apr 18 02:26:35 PM PDT 24
Peak memory 217624 kb
Host smart-89267329-9e5a-4ce1-930c-224bac481258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180969338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.180969338
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.2622909844
Short name T803
Test name
Test status
Simulation time 33797234 ps
CPU time 1.26 seconds
Started Apr 18 02:26:34 PM PDT 24
Finished Apr 18 02:26:36 PM PDT 24
Peak memory 217652 kb
Host smart-f5185594-f287-4258-929e-fd18b4313d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622909844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2622909844
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3832060052
Short name T91
Test name
Test status
Simulation time 31744076 ps
CPU time 1.22 seconds
Started Apr 18 02:24:35 PM PDT 24
Finished Apr 18 02:24:37 PM PDT 24
Peak memory 215404 kb
Host smart-3378e298-05fc-43df-8145-19c0c4617110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832060052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3832060052
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2629965068
Short name T759
Test name
Test status
Simulation time 39489588 ps
CPU time 0.83 seconds
Started Apr 18 02:24:31 PM PDT 24
Finished Apr 18 02:24:32 PM PDT 24
Peak memory 205540 kb
Host smart-1587a45a-8434-492a-9fe1-9cf44c1dbec5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629965068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2629965068
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1370720007
Short name T646
Test name
Test status
Simulation time 19145324 ps
CPU time 0.84 seconds
Started Apr 18 02:24:35 PM PDT 24
Finished Apr 18 02:24:37 PM PDT 24
Peak memory 215308 kb
Host smart-408848dc-82d2-4468-a751-6e00385b4acb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370720007 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1370720007
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3360603141
Short name T392
Test name
Test status
Simulation time 27975026 ps
CPU time 1.08 seconds
Started Apr 18 02:24:28 PM PDT 24
Finished Apr 18 02:24:30 PM PDT 24
Peak memory 217408 kb
Host smart-f8497d31-4321-49d1-996e-28ebf9a01d06
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360603141 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3360603141
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_genbits.1097393039
Short name T640
Test name
Test status
Simulation time 44610608 ps
CPU time 1.43 seconds
Started Apr 18 02:24:35 PM PDT 24
Finished Apr 18 02:24:37 PM PDT 24
Peak memory 217456 kb
Host smart-77e8a529-7d29-432d-88c3-7ef480b688cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097393039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1097393039
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1481669753
Short name T578
Test name
Test status
Simulation time 30295095 ps
CPU time 0.93 seconds
Started Apr 18 02:24:27 PM PDT 24
Finished Apr 18 02:24:28 PM PDT 24
Peak memory 215284 kb
Host smart-229f8570-784d-40c2-9627-976fb4ed6962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481669753 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1481669753
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.1227813400
Short name T246
Test name
Test status
Simulation time 31839926 ps
CPU time 0.9 seconds
Started Apr 18 02:24:35 PM PDT 24
Finished Apr 18 02:24:37 PM PDT 24
Peak memory 206856 kb
Host smart-dd06a1a5-fb4e-4065-adf4-a1652e220f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227813400 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1227813400
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.6134384
Short name T298
Test name
Test status
Simulation time 39727870 ps
CPU time 0.9 seconds
Started Apr 18 02:24:35 PM PDT 24
Finished Apr 18 02:24:37 PM PDT 24
Peak memory 215056 kb
Host smart-d7cb7cc4-0683-431e-ad87-f24a5265a2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6134384 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.6134384
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.762310974
Short name T402
Test name
Test status
Simulation time 53984839 ps
CPU time 1.61 seconds
Started Apr 18 02:24:36 PM PDT 24
Finished Apr 18 02:24:38 PM PDT 24
Peak memory 206828 kb
Host smart-3d2ef44d-6927-4a5f-96cf-89087eb003e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762310974 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.762310974
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.779136801
Short name T794
Test name
Test status
Simulation time 152289576307 ps
CPU time 1722.08 seconds
Started Apr 18 02:24:35 PM PDT 24
Finished Apr 18 02:53:18 PM PDT 24
Peak memory 225276 kb
Host smart-09f32a6d-811c-4229-802b-98a5e02aed85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779136801 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.779136801
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2259867974
Short name T250
Test name
Test status
Simulation time 27250510 ps
CPU time 1.29 seconds
Started Apr 18 02:25:16 PM PDT 24
Finished Apr 18 02:25:18 PM PDT 24
Peak memory 215392 kb
Host smart-bd46bf3c-fb33-4924-aad0-3dbf156b11c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259867974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2259867974
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2977811166
Short name T503
Test name
Test status
Simulation time 21508626 ps
CPU time 1.09 seconds
Started Apr 18 02:25:09 PM PDT 24
Finished Apr 18 02:25:10 PM PDT 24
Peak memory 206664 kb
Host smart-36ced6fe-85f6-45d2-bcb0-112e5b228727
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977811166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2977811166
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1093718138
Short name T793
Test name
Test status
Simulation time 22749718 ps
CPU time 0.84 seconds
Started Apr 18 02:25:13 PM PDT 24
Finished Apr 18 02:25:14 PM PDT 24
Peak memory 215672 kb
Host smart-2008ee5c-c030-4894-aba3-916fa546212e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093718138 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1093718138
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.1463406128
Short name T710
Test name
Test status
Simulation time 24979763 ps
CPU time 0.95 seconds
Started Apr 18 02:25:10 PM PDT 24
Finished Apr 18 02:25:11 PM PDT 24
Peak memory 217392 kb
Host smart-cdb0686b-043d-4743-a1ce-e42fbf87d33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463406128 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1463406128
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3264951959
Short name T612
Test name
Test status
Simulation time 28071207 ps
CPU time 1.21 seconds
Started Apr 18 02:25:26 PM PDT 24
Finished Apr 18 02:25:28 PM PDT 24
Peak memory 217504 kb
Host smart-365a62d0-0d48-426e-b076-56e1784c4eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264951959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3264951959
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_smoke.4110461880
Short name T631
Test name
Test status
Simulation time 32647110 ps
CPU time 0.95 seconds
Started Apr 18 02:25:10 PM PDT 24
Finished Apr 18 02:25:11 PM PDT 24
Peak memory 215032 kb
Host smart-f172ea90-82a0-4f0a-92ad-16e05ee0858a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110461880 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.4110461880
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3264607408
Short name T682
Test name
Test status
Simulation time 340494208 ps
CPU time 2.4 seconds
Started Apr 18 02:25:11 PM PDT 24
Finished Apr 18 02:25:14 PM PDT 24
Peak memory 216344 kb
Host smart-593bedd8-e679-4785-8aa1-868ff30c0c17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264607408 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3264607408
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2637340533
Short name T111
Test name
Test status
Simulation time 260369436506 ps
CPU time 807.04 seconds
Started Apr 18 02:25:12 PM PDT 24
Finished Apr 18 02:38:40 PM PDT 24
Peak memory 220284 kb
Host smart-5954dafb-f258-413e-b1b0-9d04542632ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637340533 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2637340533
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3610720082
Short name T514
Test name
Test status
Simulation time 122199245 ps
CPU time 1.42 seconds
Started Apr 18 02:26:33 PM PDT 24
Finished Apr 18 02:26:36 PM PDT 24
Peak memory 214572 kb
Host smart-8f92d7ce-ed86-4912-9764-c4ee78d2dfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610720082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3610720082
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1595665614
Short name T365
Test name
Test status
Simulation time 71266766 ps
CPU time 1.18 seconds
Started Apr 18 02:26:36 PM PDT 24
Finished Apr 18 02:26:38 PM PDT 24
Peak memory 218024 kb
Host smart-55c9db14-8038-4727-8db8-d8c56cc2ea70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595665614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1595665614
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.4082251250
Short name T562
Test name
Test status
Simulation time 47691677 ps
CPU time 1.64 seconds
Started Apr 18 02:26:33 PM PDT 24
Finished Apr 18 02:26:36 PM PDT 24
Peak memory 219108 kb
Host smart-4bd3f61b-a142-4a1b-879f-a76d8c2fd036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082251250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.4082251250
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.67102211
Short name T639
Test name
Test status
Simulation time 52891700 ps
CPU time 1.77 seconds
Started Apr 18 02:26:33 PM PDT 24
Finished Apr 18 02:26:36 PM PDT 24
Peak memory 217644 kb
Host smart-ffc355a2-c014-4629-b9e6-7ab74c226b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67102211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.67102211
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1016914044
Short name T294
Test name
Test status
Simulation time 270897217 ps
CPU time 3.27 seconds
Started Apr 18 02:26:37 PM PDT 24
Finished Apr 18 02:26:41 PM PDT 24
Peak memory 217628 kb
Host smart-4266a4ec-1942-4fd7-b01c-10452f7f27b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016914044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1016914044
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1794872128
Short name T747
Test name
Test status
Simulation time 25174983 ps
CPU time 1.06 seconds
Started Apr 18 02:26:41 PM PDT 24
Finished Apr 18 02:26:43 PM PDT 24
Peak memory 216692 kb
Host smart-24c5b917-92da-45e4-87e2-952c4e71769c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794872128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1794872128
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.150614960
Short name T524
Test name
Test status
Simulation time 53720292 ps
CPU time 0.98 seconds
Started Apr 18 02:26:41 PM PDT 24
Finished Apr 18 02:26:42 PM PDT 24
Peak memory 216388 kb
Host smart-d34cd58e-0925-411f-bfcd-f1bad4f68601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150614960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.150614960
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1660574714
Short name T758
Test name
Test status
Simulation time 34308008 ps
CPU time 1.07 seconds
Started Apr 18 02:26:51 PM PDT 24
Finished Apr 18 02:26:54 PM PDT 24
Peak memory 217584 kb
Host smart-6a5f8bea-3572-4bd7-8297-dab1c42cb132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660574714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1660574714
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1967235643
Short name T711
Test name
Test status
Simulation time 90702014 ps
CPU time 2.64 seconds
Started Apr 18 02:26:42 PM PDT 24
Finished Apr 18 02:26:46 PM PDT 24
Peak memory 218024 kb
Host smart-d1da515a-c963-4314-8680-befb64d3b1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967235643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1967235643
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert_test.2678360618
Short name T449
Test name
Test status
Simulation time 85678318 ps
CPU time 0.81 seconds
Started Apr 18 02:25:12 PM PDT 24
Finished Apr 18 02:25:13 PM PDT 24
Peak memory 205648 kb
Host smart-13da1a5d-f5da-49c8-ab95-09214c04c168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678360618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2678360618
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_genbits.3002272595
Short name T624
Test name
Test status
Simulation time 53908330 ps
CPU time 2.27 seconds
Started Apr 18 02:25:16 PM PDT 24
Finished Apr 18 02:25:19 PM PDT 24
Peak memory 219508 kb
Host smart-76d2fcad-b512-45c0-b49f-325059d3e170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002272595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3002272595
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.302250127
Short name T380
Test name
Test status
Simulation time 33752589 ps
CPU time 1.02 seconds
Started Apr 18 02:25:14 PM PDT 24
Finished Apr 18 02:25:15 PM PDT 24
Peak memory 223740 kb
Host smart-cd8bd493-52cc-429f-972a-f699ba1257da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302250127 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.302250127
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2663645800
Short name T742
Test name
Test status
Simulation time 18667892 ps
CPU time 1.02 seconds
Started Apr 18 02:25:27 PM PDT 24
Finished Apr 18 02:25:29 PM PDT 24
Peak memory 215072 kb
Host smart-6620cfc6-c40c-4ade-9623-a013ddfbdbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663645800 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2663645800
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.326357615
Short name T461
Test name
Test status
Simulation time 156064045 ps
CPU time 3.01 seconds
Started Apr 18 02:25:27 PM PDT 24
Finished Apr 18 02:25:31 PM PDT 24
Peak memory 216304 kb
Host smart-2629f5d7-9f4c-4d2f-8c3d-f1ddd55369c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326357615 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.326357615
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1120146010
Short name T703
Test name
Test status
Simulation time 52250758322 ps
CPU time 1170.95 seconds
Started Apr 18 02:25:14 PM PDT 24
Finished Apr 18 02:44:46 PM PDT 24
Peak memory 223332 kb
Host smart-f1b234a6-477e-4412-a3eb-e2068f2210ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120146010 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1120146010
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3196807473
Short name T115
Test name
Test status
Simulation time 81832973 ps
CPU time 1.14 seconds
Started Apr 18 02:26:38 PM PDT 24
Finished Apr 18 02:26:39 PM PDT 24
Peak memory 216492 kb
Host smart-51dabbdd-fb6d-451f-92f7-6afae4a78407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196807473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3196807473
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1626063161
Short name T396
Test name
Test status
Simulation time 175387481 ps
CPU time 1.81 seconds
Started Apr 18 02:26:38 PM PDT 24
Finished Apr 18 02:26:40 PM PDT 24
Peak memory 218000 kb
Host smart-30813b64-233a-4e15-a8e7-6305e7f70a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626063161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1626063161
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2866475398
Short name T459
Test name
Test status
Simulation time 130664251 ps
CPU time 2.91 seconds
Started Apr 18 02:26:39 PM PDT 24
Finished Apr 18 02:26:43 PM PDT 24
Peak memory 219216 kb
Host smart-58c0bef3-ea27-49eb-b15e-d3ffbdb97e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866475398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2866475398
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3380935483
Short name T338
Test name
Test status
Simulation time 31789008 ps
CPU time 1.35 seconds
Started Apr 18 02:26:39 PM PDT 24
Finished Apr 18 02:26:41 PM PDT 24
Peak memory 217788 kb
Host smart-7a652d7a-5ea5-48f8-babe-240e759ae8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380935483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3380935483
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1085575320
Short name T549
Test name
Test status
Simulation time 274886999 ps
CPU time 4.01 seconds
Started Apr 18 02:26:40 PM PDT 24
Finished Apr 18 02:26:45 PM PDT 24
Peak memory 216672 kb
Host smart-e375d3e3-e7d5-4054-b7f3-2bfa4ff654e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085575320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1085575320
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.451419611
Short name T378
Test name
Test status
Simulation time 119501761 ps
CPU time 1.67 seconds
Started Apr 18 02:26:40 PM PDT 24
Finished Apr 18 02:26:42 PM PDT 24
Peak memory 218048 kb
Host smart-4ef9bd69-32fe-4473-aafe-f241b516bc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451419611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.451419611
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2351024968
Short name T834
Test name
Test status
Simulation time 37186975 ps
CPU time 1.79 seconds
Started Apr 18 02:26:39 PM PDT 24
Finished Apr 18 02:26:41 PM PDT 24
Peak memory 217556 kb
Host smart-ec203f5a-fe90-4aba-bc23-0caf5b09f2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351024968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2351024968
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.282269723
Short name T475
Test name
Test status
Simulation time 49505455 ps
CPU time 1.14 seconds
Started Apr 18 02:26:39 PM PDT 24
Finished Apr 18 02:26:41 PM PDT 24
Peak memory 216348 kb
Host smart-824db5d5-f758-42f7-882d-8b8b164e17d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282269723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.282269723
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.712452335
Short name T355
Test name
Test status
Simulation time 45375520 ps
CPU time 1.05 seconds
Started Apr 18 02:26:41 PM PDT 24
Finished Apr 18 02:26:43 PM PDT 24
Peak memory 216532 kb
Host smart-519da0f1-ab55-4efc-b433-ca9e29cbfbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712452335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.712452335
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2732470052
Short name T817
Test name
Test status
Simulation time 33735278 ps
CPU time 1.26 seconds
Started Apr 18 02:26:41 PM PDT 24
Finished Apr 18 02:26:43 PM PDT 24
Peak memory 215036 kb
Host smart-2a4f1eb3-26b4-46df-9e0a-fd9b3fedf067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732470052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2732470052
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert_test.3791871024
Short name T429
Test name
Test status
Simulation time 27014339 ps
CPU time 0.86 seconds
Started Apr 18 02:25:27 PM PDT 24
Finished Apr 18 02:25:29 PM PDT 24
Peak memory 205524 kb
Host smart-55bb1839-ac8c-4d69-9c33-18a5ed16942f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791871024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3791871024
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1285257648
Short name T66
Test name
Test status
Simulation time 16412570 ps
CPU time 0.94 seconds
Started Apr 18 02:25:11 PM PDT 24
Finished Apr 18 02:25:12 PM PDT 24
Peak memory 215588 kb
Host smart-9120578b-870e-4c2c-9eef-5ade094b0f77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285257648 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1285257648
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.4156135437
Short name T42
Test name
Test status
Simulation time 46102096 ps
CPU time 0.98 seconds
Started Apr 18 02:25:10 PM PDT 24
Finished Apr 18 02:25:11 PM PDT 24
Peak memory 217692 kb
Host smart-6f17274a-7301-4222-bed1-939695a42538
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156135437 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.4156135437
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2718860051
Short name T824
Test name
Test status
Simulation time 18229791 ps
CPU time 1.05 seconds
Started Apr 18 02:25:20 PM PDT 24
Finished Apr 18 02:25:22 PM PDT 24
Peak memory 218056 kb
Host smart-08816982-b189-417c-afe0-37c98a7b3df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718860051 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2718860051
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1077502792
Short name T694
Test name
Test status
Simulation time 52800640 ps
CPU time 1.32 seconds
Started Apr 18 02:25:14 PM PDT 24
Finished Apr 18 02:25:16 PM PDT 24
Peak memory 215008 kb
Host smart-3a2e8aa1-0f95-47af-816f-329e8e5ef617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077502792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1077502792
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2827660490
Short name T594
Test name
Test status
Simulation time 24177788 ps
CPU time 1.17 seconds
Started Apr 18 02:25:27 PM PDT 24
Finished Apr 18 02:25:29 PM PDT 24
Peak memory 223696 kb
Host smart-78967bbd-d358-4a08-b94f-b23f9c99b24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827660490 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2827660490
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1271073775
Short name T419
Test name
Test status
Simulation time 84728297 ps
CPU time 0.99 seconds
Started Apr 18 02:25:12 PM PDT 24
Finished Apr 18 02:25:14 PM PDT 24
Peak memory 214924 kb
Host smart-68b3ee28-5816-448b-9970-344ef4249dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271073775 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1271073775
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1607444257
Short name T150
Test name
Test status
Simulation time 317152886 ps
CPU time 2.25 seconds
Started Apr 18 02:25:09 PM PDT 24
Finished Apr 18 02:25:12 PM PDT 24
Peak memory 216212 kb
Host smart-9120b32b-42c2-429c-ad66-2ce3e886f8cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607444257 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1607444257
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3129490961
Short name T734
Test name
Test status
Simulation time 74353984195 ps
CPU time 469.84 seconds
Started Apr 18 02:25:14 PM PDT 24
Finished Apr 18 02:33:04 PM PDT 24
Peak memory 223452 kb
Host smart-dbe3f029-9ac1-4336-a418-a41284f1b82d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129490961 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3129490961
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2509025738
Short name T790
Test name
Test status
Simulation time 20861415 ps
CPU time 1.08 seconds
Started Apr 18 02:26:42 PM PDT 24
Finished Apr 18 02:26:43 PM PDT 24
Peak memory 216792 kb
Host smart-0e722ba0-e20e-436f-b21f-53062a5c8a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509025738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2509025738
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3451049248
Short name T417
Test name
Test status
Simulation time 76180044 ps
CPU time 1.53 seconds
Started Apr 18 02:26:38 PM PDT 24
Finished Apr 18 02:26:40 PM PDT 24
Peak memory 217700 kb
Host smart-9c4e4134-f7f0-40d3-a835-c382efda29d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451049248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3451049248
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.147282228
Short name T291
Test name
Test status
Simulation time 53708667 ps
CPU time 1.4 seconds
Started Apr 18 02:26:38 PM PDT 24
Finished Apr 18 02:26:40 PM PDT 24
Peak memory 218972 kb
Host smart-e838fc0a-cae1-40c3-ad5a-545eaa0da851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147282228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.147282228
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3174262713
Short name T796
Test name
Test status
Simulation time 53934459 ps
CPU time 1.17 seconds
Started Apr 18 02:26:40 PM PDT 24
Finished Apr 18 02:26:42 PM PDT 24
Peak memory 216276 kb
Host smart-09696c8f-5063-45ed-b1a3-9747ccd7a3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174262713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3174262713
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.33518454
Short name T113
Test name
Test status
Simulation time 53569605 ps
CPU time 1.39 seconds
Started Apr 18 02:26:42 PM PDT 24
Finished Apr 18 02:26:45 PM PDT 24
Peak memory 217100 kb
Host smart-4436e256-3465-43d9-97cb-b1be8e433d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33518454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.33518454
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.543677194
Short name T515
Test name
Test status
Simulation time 40462943 ps
CPU time 1.1 seconds
Started Apr 18 02:26:43 PM PDT 24
Finished Apr 18 02:26:45 PM PDT 24
Peak memory 216288 kb
Host smart-08762b0e-654b-4d55-8fb6-a6f6f1f46e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543677194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.543677194
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.481382993
Short name T158
Test name
Test status
Simulation time 50543013 ps
CPU time 1.36 seconds
Started Apr 18 02:26:38 PM PDT 24
Finished Apr 18 02:26:40 PM PDT 24
Peak memory 217692 kb
Host smart-c38acd16-e275-4051-8350-739298507821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481382993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.481382993
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.667290572
Short name T304
Test name
Test status
Simulation time 254452365 ps
CPU time 1.48 seconds
Started Apr 18 02:26:40 PM PDT 24
Finished Apr 18 02:26:42 PM PDT 24
Peak memory 217768 kb
Host smart-07ed99cf-8a99-4dd0-8d22-ad7fd32ae21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667290572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.667290572
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2650322480
Short name T290
Test name
Test status
Simulation time 57771086 ps
CPU time 1.44 seconds
Started Apr 18 02:26:39 PM PDT 24
Finished Apr 18 02:26:41 PM PDT 24
Peak memory 217792 kb
Host smart-01a5c6d0-a5a4-41af-878e-b0e07b1277ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650322480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2650322480
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3266963033
Short name T293
Test name
Test status
Simulation time 105625413 ps
CPU time 2.14 seconds
Started Apr 18 02:26:41 PM PDT 24
Finished Apr 18 02:26:44 PM PDT 24
Peak memory 217852 kb
Host smart-40a45ee7-35cc-4f06-a76e-a6f61189ed24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266963033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3266963033
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.4270654841
Short name T92
Test name
Test status
Simulation time 27406477 ps
CPU time 1.27 seconds
Started Apr 18 02:25:14 PM PDT 24
Finished Apr 18 02:25:16 PM PDT 24
Peak memory 215372 kb
Host smart-adc91399-e26a-4a6b-86a0-760adce57ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270654841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.4270654841
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2848964551
Short name T346
Test name
Test status
Simulation time 47936366 ps
CPU time 0.88 seconds
Started Apr 18 02:25:18 PM PDT 24
Finished Apr 18 02:25:19 PM PDT 24
Peak memory 205832 kb
Host smart-f581e65d-d9dd-422a-83eb-2b9622639705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848964551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2848964551
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3648267853
Short name T161
Test name
Test status
Simulation time 32382055 ps
CPU time 0.83 seconds
Started Apr 18 02:25:15 PM PDT 24
Finished Apr 18 02:25:16 PM PDT 24
Peak memory 215772 kb
Host smart-8f364a31-b0ce-4e9c-a5ae-d80e4b604586
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648267853 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3648267853
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.2954900941
Short name T198
Test name
Test status
Simulation time 35143300 ps
CPU time 1.33 seconds
Started Apr 18 02:25:16 PM PDT 24
Finished Apr 18 02:25:18 PM PDT 24
Peak memory 215284 kb
Host smart-d267c5c6-a128-427e-8cfd-fe569d1f6ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954900941 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2954900941
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2718179963
Short name T412
Test name
Test status
Simulation time 29084365 ps
CPU time 1.25 seconds
Started Apr 18 02:25:11 PM PDT 24
Finished Apr 18 02:25:13 PM PDT 24
Peak memory 217732 kb
Host smart-6edbd018-6ee6-4979-9572-e5997a190d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718179963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2718179963
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3599366720
Short name T147
Test name
Test status
Simulation time 20219938 ps
CPU time 1.07 seconds
Started Apr 18 02:25:18 PM PDT 24
Finished Apr 18 02:25:20 PM PDT 24
Peak memory 215100 kb
Host smart-c67c61ad-c7c4-494d-b1d0-08278ff6bc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599366720 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3599366720
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1509128526
Short name T432
Test name
Test status
Simulation time 14947203 ps
CPU time 0.94 seconds
Started Apr 18 02:25:14 PM PDT 24
Finished Apr 18 02:25:15 PM PDT 24
Peak memory 214952 kb
Host smart-4d871d00-0e5b-442d-a2f5-60fd152d6773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509128526 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1509128526
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3373413640
Short name T724
Test name
Test status
Simulation time 225744130 ps
CPU time 2.71 seconds
Started Apr 18 02:25:13 PM PDT 24
Finished Apr 18 02:25:16 PM PDT 24
Peak memory 214980 kb
Host smart-2f41f505-7520-42fe-a72c-5beef4bf607f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373413640 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3373413640
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2048988088
Short name T341
Test name
Test status
Simulation time 87924408318 ps
CPU time 741.53 seconds
Started Apr 18 02:25:16 PM PDT 24
Finished Apr 18 02:37:38 PM PDT 24
Peak memory 223340 kb
Host smart-f783a84a-4249-4b94-8703-aaa34b00ecdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048988088 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2048988088
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1740083062
Short name T822
Test name
Test status
Simulation time 54046022 ps
CPU time 1.5 seconds
Started Apr 18 02:26:38 PM PDT 24
Finished Apr 18 02:26:40 PM PDT 24
Peak memory 217900 kb
Host smart-5a6118bb-bbda-4e81-95fd-cc47902a5325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740083062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1740083062
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3237517803
Short name T787
Test name
Test status
Simulation time 87006911 ps
CPU time 1.3 seconds
Started Apr 18 02:26:42 PM PDT 24
Finished Apr 18 02:26:43 PM PDT 24
Peak memory 219332 kb
Host smart-8b7556b7-456b-42f6-93bf-ead0bde2a458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237517803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3237517803
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.637707093
Short name T663
Test name
Test status
Simulation time 62636699 ps
CPU time 1.21 seconds
Started Apr 18 02:26:40 PM PDT 24
Finished Apr 18 02:26:42 PM PDT 24
Peak memory 216412 kb
Host smart-899127e7-1dda-46e0-b51a-9ebdb9854723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637707093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.637707093
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.792171320
Short name T596
Test name
Test status
Simulation time 272094918 ps
CPU time 1.28 seconds
Started Apr 18 02:26:40 PM PDT 24
Finished Apr 18 02:26:42 PM PDT 24
Peak memory 216432 kb
Host smart-30dfcb64-7d8a-4b54-b277-60d92b7ac6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792171320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.792171320
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.573594181
Short name T821
Test name
Test status
Simulation time 47861451 ps
CPU time 1.19 seconds
Started Apr 18 02:26:39 PM PDT 24
Finished Apr 18 02:26:41 PM PDT 24
Peak memory 218060 kb
Host smart-f3570b63-9785-4de1-98c7-2f3dfd23b088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573594181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.573594181
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3766682398
Short name T344
Test name
Test status
Simulation time 46703431 ps
CPU time 1.58 seconds
Started Apr 18 02:26:37 PM PDT 24
Finished Apr 18 02:26:39 PM PDT 24
Peak memory 218572 kb
Host smart-1ecb2997-7f5d-4f41-a9f2-2e9bc39428b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766682398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3766682398
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1783886870
Short name T12
Test name
Test status
Simulation time 132198140 ps
CPU time 1.21 seconds
Started Apr 18 02:26:39 PM PDT 24
Finished Apr 18 02:26:40 PM PDT 24
Peak memory 217684 kb
Host smart-7252c939-f346-4b40-8203-efbda88a29a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783886870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1783886870
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1579042051
Short name T320
Test name
Test status
Simulation time 42927870 ps
CPU time 1.09 seconds
Started Apr 18 02:26:43 PM PDT 24
Finished Apr 18 02:26:45 PM PDT 24
Peak memory 216684 kb
Host smart-1f210e05-dcaa-4d20-9f15-4e42773a1f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579042051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1579042051
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1752489597
Short name T319
Test name
Test status
Simulation time 294442098 ps
CPU time 1.15 seconds
Started Apr 18 02:26:41 PM PDT 24
Finished Apr 18 02:26:43 PM PDT 24
Peak memory 216432 kb
Host smart-cf92a740-3cd5-4526-9685-24d38aac7d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752489597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1752489597
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3594152243
Short name T727
Test name
Test status
Simulation time 41985889 ps
CPU time 1.4 seconds
Started Apr 18 02:26:39 PM PDT 24
Finished Apr 18 02:26:41 PM PDT 24
Peak memory 217808 kb
Host smart-145e16f6-aec6-4370-b234-cd42ded96241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594152243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3594152243
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1617369712
Short name T678
Test name
Test status
Simulation time 30984752 ps
CPU time 1.21 seconds
Started Apr 18 02:25:17 PM PDT 24
Finished Apr 18 02:25:19 PM PDT 24
Peak memory 215388 kb
Host smart-fcdaeaa0-7e2f-4879-a737-60f68802bb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617369712 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1617369712
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.77198564
Short name T528
Test name
Test status
Simulation time 15221067 ps
CPU time 0.91 seconds
Started Apr 18 02:25:16 PM PDT 24
Finished Apr 18 02:25:18 PM PDT 24
Peak memory 206364 kb
Host smart-a490dad4-ad34-428a-8f8e-70c818761319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77198564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.77198564
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3873966287
Short name T837
Test name
Test status
Simulation time 38691354 ps
CPU time 0.85 seconds
Started Apr 18 02:25:14 PM PDT 24
Finished Apr 18 02:25:15 PM PDT 24
Peak memory 215120 kb
Host smart-00e5e3da-eb86-4e4a-b491-7876328726d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873966287 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3873966287
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.950557157
Short name T75
Test name
Test status
Simulation time 24090621 ps
CPU time 0.96 seconds
Started Apr 18 02:25:18 PM PDT 24
Finished Apr 18 02:25:20 PM PDT 24
Peak memory 217660 kb
Host smart-d6b2575c-d82e-4f83-9f03-3c309f46617a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950557157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.950557157
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_intr.4024789288
Short name T647
Test name
Test status
Simulation time 22032239 ps
CPU time 1.04 seconds
Started Apr 18 02:25:17 PM PDT 24
Finished Apr 18 02:25:18 PM PDT 24
Peak memory 215112 kb
Host smart-a6d41424-6b1c-41af-a40e-2b48c573f054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024789288 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.4024789288
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.4215701110
Short name T687
Test name
Test status
Simulation time 96276193 ps
CPU time 0.93 seconds
Started Apr 18 02:25:16 PM PDT 24
Finished Apr 18 02:25:18 PM PDT 24
Peak memory 215016 kb
Host smart-8fe91ea7-b209-4fdd-9d11-8d25652f2b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215701110 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.4215701110
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.278554369
Short name T310
Test name
Test status
Simulation time 368956017 ps
CPU time 2.7 seconds
Started Apr 18 02:25:15 PM PDT 24
Finished Apr 18 02:25:18 PM PDT 24
Peak memory 216592 kb
Host smart-4684d680-4496-4833-bae7-a5ef3200d762
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278554369 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.278554369
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2855883936
Short name T193
Test name
Test status
Simulation time 28242099273 ps
CPU time 266.45 seconds
Started Apr 18 02:25:17 PM PDT 24
Finished Apr 18 02:29:44 PM PDT 24
Peak memory 219852 kb
Host smart-591da821-93d6-4225-acd7-62251cedd436
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855883936 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2855883936
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3063806096
Short name T387
Test name
Test status
Simulation time 64786695 ps
CPU time 2.22 seconds
Started Apr 18 02:26:39 PM PDT 24
Finished Apr 18 02:26:42 PM PDT 24
Peak memory 215120 kb
Host smart-850223c6-5af9-440a-81a7-8adfce6b53c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063806096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3063806096
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2955062727
Short name T431
Test name
Test status
Simulation time 62557051 ps
CPU time 1.71 seconds
Started Apr 18 02:26:42 PM PDT 24
Finished Apr 18 02:26:45 PM PDT 24
Peak memory 217240 kb
Host smart-e7cfddcd-8be1-4ea7-853b-a90f4db5882d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955062727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2955062727
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1703300501
Short name T480
Test name
Test status
Simulation time 175744360 ps
CPU time 0.98 seconds
Started Apr 18 02:26:42 PM PDT 24
Finished Apr 18 02:26:44 PM PDT 24
Peak memory 216436 kb
Host smart-332614c3-22d6-4f10-ac84-72e3d22569eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703300501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1703300501
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3894950714
Short name T634
Test name
Test status
Simulation time 188330672 ps
CPU time 0.9 seconds
Started Apr 18 02:26:40 PM PDT 24
Finished Apr 18 02:26:42 PM PDT 24
Peak memory 216256 kb
Host smart-9ea769f0-dc49-481e-ae85-2431349bde9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894950714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3894950714
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1305750359
Short name T722
Test name
Test status
Simulation time 216910059 ps
CPU time 2.81 seconds
Started Apr 18 02:26:50 PM PDT 24
Finished Apr 18 02:26:55 PM PDT 24
Peak memory 219236 kb
Host smart-c4eac1a0-3e49-4712-a29a-76d03498ab05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305750359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1305750359
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.203414731
Short name T112
Test name
Test status
Simulation time 38761369 ps
CPU time 1.15 seconds
Started Apr 18 02:26:40 PM PDT 24
Finished Apr 18 02:26:42 PM PDT 24
Peak memory 217592 kb
Host smart-c9f2322d-48c2-4d7b-b748-0b64bbd2624b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203414731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.203414731
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.4230851245
Short name T643
Test name
Test status
Simulation time 41922568 ps
CPU time 1.62 seconds
Started Apr 18 02:26:36 PM PDT 24
Finished Apr 18 02:26:38 PM PDT 24
Peak memory 217444 kb
Host smart-7f009ab5-cd04-45d0-8978-65257e60d644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230851245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.4230851245
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.514735803
Short name T381
Test name
Test status
Simulation time 95244641 ps
CPU time 1.36 seconds
Started Apr 18 02:26:40 PM PDT 24
Finished Apr 18 02:26:42 PM PDT 24
Peak memory 218780 kb
Host smart-05bf52f6-6bb9-4403-bed4-8391a2b10d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514735803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.514735803
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3486845711
Short name T603
Test name
Test status
Simulation time 42921868 ps
CPU time 1.19 seconds
Started Apr 18 02:26:37 PM PDT 24
Finished Apr 18 02:26:39 PM PDT 24
Peak memory 216184 kb
Host smart-9d322939-7ad2-41be-979f-5018ea0fd9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486845711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3486845711
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1818877624
Short name T662
Test name
Test status
Simulation time 88836707 ps
CPU time 1.21 seconds
Started Apr 18 02:26:41 PM PDT 24
Finished Apr 18 02:26:43 PM PDT 24
Peak memory 216452 kb
Host smart-e932da34-ddde-4dde-99b7-c92e659ddaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818877624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1818877624
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.281361405
Short name T764
Test name
Test status
Simulation time 24608072 ps
CPU time 1.14 seconds
Started Apr 18 02:25:16 PM PDT 24
Finished Apr 18 02:25:18 PM PDT 24
Peak memory 215328 kb
Host smart-e8bf7327-cb05-46a6-8178-b1ea6bb3eddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281361405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.281361405
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.448224993
Short name T416
Test name
Test status
Simulation time 16445932 ps
CPU time 0.92 seconds
Started Apr 18 02:25:17 PM PDT 24
Finished Apr 18 02:25:19 PM PDT 24
Peak memory 205868 kb
Host smart-f28451b6-3096-41b1-98a8-d42b4cb1011c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448224993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.448224993
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.1275977337
Short name T383
Test name
Test status
Simulation time 17171212 ps
CPU time 0.87 seconds
Started Apr 18 02:25:26 PM PDT 24
Finished Apr 18 02:25:28 PM PDT 24
Peak memory 215608 kb
Host smart-f1396088-076f-4910-8d6e-9ea08b814647
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275977337 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1275977337
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3583249179
Short name T178
Test name
Test status
Simulation time 277484192 ps
CPU time 1.1 seconds
Started Apr 18 02:25:27 PM PDT 24
Finished Apr 18 02:25:29 PM PDT 24
Peak memory 216492 kb
Host smart-a301ced4-a91b-4ed5-8662-faafaa8c5cae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583249179 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3583249179
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2463308999
Short name T59
Test name
Test status
Simulation time 18616770 ps
CPU time 1.1 seconds
Started Apr 18 02:25:15 PM PDT 24
Finished Apr 18 02:25:17 PM PDT 24
Peak memory 217680 kb
Host smart-a20def55-57fd-49fa-ae7e-3ccbb14c3dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463308999 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2463308999
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3785406005
Short name T498
Test name
Test status
Simulation time 64445077 ps
CPU time 1.12 seconds
Started Apr 18 02:25:18 PM PDT 24
Finished Apr 18 02:25:19 PM PDT 24
Peak memory 216524 kb
Host smart-718e799d-feec-439e-bf71-4fad518eb14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785406005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3785406005
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3196418628
Short name T775
Test name
Test status
Simulation time 34914270 ps
CPU time 1.03 seconds
Started Apr 18 02:25:17 PM PDT 24
Finished Apr 18 02:25:19 PM PDT 24
Peak memory 223724 kb
Host smart-23ff03f8-92d5-4546-a448-08784584c839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196418628 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3196418628
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.4057955408
Short name T608
Test name
Test status
Simulation time 19968865 ps
CPU time 1.02 seconds
Started Apr 18 02:25:16 PM PDT 24
Finished Apr 18 02:25:17 PM PDT 24
Peak memory 215008 kb
Host smart-8e4894f6-70df-4420-93c3-eff019dfb465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057955408 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.4057955408
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.4274931277
Short name T651
Test name
Test status
Simulation time 936074860 ps
CPU time 3.83 seconds
Started Apr 18 02:25:15 PM PDT 24
Finished Apr 18 02:25:19 PM PDT 24
Peak memory 216560 kb
Host smart-63e715f9-7444-49a4-bd2d-e8049865afdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274931277 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.4274931277
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1142312218
Short name T316
Test name
Test status
Simulation time 17278153305 ps
CPU time 219.29 seconds
Started Apr 18 02:25:16 PM PDT 24
Finished Apr 18 02:28:56 PM PDT 24
Peak memory 218560 kb
Host smart-e514c620-28dc-490d-8c48-d55a1e204e39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142312218 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1142312218
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3050595080
Short name T738
Test name
Test status
Simulation time 239419826 ps
CPU time 1.3 seconds
Started Apr 18 02:26:51 PM PDT 24
Finished Apr 18 02:26:54 PM PDT 24
Peak memory 219388 kb
Host smart-7df844ca-c334-43e1-986b-1c8b49aab6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050595080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3050595080
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.216655375
Short name T420
Test name
Test status
Simulation time 57789652 ps
CPU time 2.11 seconds
Started Apr 18 02:26:41 PM PDT 24
Finished Apr 18 02:26:44 PM PDT 24
Peak memory 219248 kb
Host smart-64e5d5ae-a2b3-4162-bbd2-663eeef79a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216655375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.216655375
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2160656527
Short name T487
Test name
Test status
Simulation time 94537492 ps
CPU time 1.45 seconds
Started Apr 18 02:26:42 PM PDT 24
Finished Apr 18 02:26:44 PM PDT 24
Peak memory 218208 kb
Host smart-8c740c3d-8337-4bd9-a5d1-88d13749a55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160656527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2160656527
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1309221842
Short name T281
Test name
Test status
Simulation time 540391918 ps
CPU time 3.57 seconds
Started Apr 18 02:26:40 PM PDT 24
Finished Apr 18 02:26:44 PM PDT 24
Peak memory 219160 kb
Host smart-a0c07238-222f-4ec5-9dc3-f50cae6635aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309221842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1309221842
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3988431350
Short name T740
Test name
Test status
Simulation time 138051670 ps
CPU time 1.27 seconds
Started Apr 18 02:26:51 PM PDT 24
Finished Apr 18 02:26:53 PM PDT 24
Peak memory 216572 kb
Host smart-41ad9803-6640-490f-8e1e-5dfc79f366d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988431350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3988431350
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.793676265
Short name T746
Test name
Test status
Simulation time 94596505 ps
CPU time 1.24 seconds
Started Apr 18 02:26:45 PM PDT 24
Finished Apr 18 02:26:47 PM PDT 24
Peak memory 217424 kb
Host smart-7fb9325b-7e85-4918-8162-e35a8f47844b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793676265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.793676265
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2779087054
Short name T140
Test name
Test status
Simulation time 145556825 ps
CPU time 0.98 seconds
Started Apr 18 02:26:44 PM PDT 24
Finished Apr 18 02:26:46 PM PDT 24
Peak memory 216492 kb
Host smart-e4c68d9f-cc97-4277-a2e6-a0334a6e00c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779087054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2779087054
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1382735368
Short name T434
Test name
Test status
Simulation time 78737585 ps
CPU time 1.42 seconds
Started Apr 18 02:26:44 PM PDT 24
Finished Apr 18 02:26:46 PM PDT 24
Peak memory 217468 kb
Host smart-8cf2a652-ba0a-4a5f-80cb-08b16b0e4181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382735368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1382735368
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.713595109
Short name T142
Test name
Test status
Simulation time 87829181 ps
CPU time 1.34 seconds
Started Apr 18 02:26:44 PM PDT 24
Finished Apr 18 02:26:47 PM PDT 24
Peak memory 217772 kb
Host smart-43c1243c-ca6a-46a5-9830-02e0e9ccce57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713595109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.713595109
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1368624240
Short name T688
Test name
Test status
Simulation time 36109721 ps
CPU time 1.07 seconds
Started Apr 18 02:25:18 PM PDT 24
Finished Apr 18 02:25:20 PM PDT 24
Peak memory 214960 kb
Host smart-27e0effe-174d-4dc7-b6a1-89ca1ef475cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368624240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1368624240
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.5810843
Short name T502
Test name
Test status
Simulation time 24656978 ps
CPU time 0.89 seconds
Started Apr 18 02:25:17 PM PDT 24
Finished Apr 18 02:25:19 PM PDT 24
Peak memory 206472 kb
Host smart-1a916bd7-c6c9-46ee-af75-6fac3b5d2f9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5810843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.5810843
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2770924343
Short name T627
Test name
Test status
Simulation time 20000724 ps
CPU time 0.89 seconds
Started Apr 18 02:25:17 PM PDT 24
Finished Apr 18 02:25:18 PM PDT 24
Peak memory 215720 kb
Host smart-12ae4889-2e1d-4ff2-a919-8a59aaf5f8de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770924343 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2770924343
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3098957585
Short name T499
Test name
Test status
Simulation time 68165163 ps
CPU time 1.06 seconds
Started Apr 18 02:25:17 PM PDT 24
Finished Apr 18 02:25:19 PM PDT 24
Peak memory 217376 kb
Host smart-5f39d400-eb53-4c10-83b8-3bdd131ff09c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098957585 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3098957585
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2089911375
Short name T557
Test name
Test status
Simulation time 18766936 ps
CPU time 1.03 seconds
Started Apr 18 02:25:15 PM PDT 24
Finished Apr 18 02:25:17 PM PDT 24
Peak memory 217752 kb
Host smart-f14333f9-b410-404a-9ba8-8c1ecf22364a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089911375 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2089911375
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.963671980
Short name T279
Test name
Test status
Simulation time 63211701 ps
CPU time 1.28 seconds
Started Apr 18 02:25:26 PM PDT 24
Finished Apr 18 02:25:29 PM PDT 24
Peak memory 217940 kb
Host smart-ae2c0040-def5-441e-8469-89ffcd99788a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963671980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.963671980
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3601073847
Short name T145
Test name
Test status
Simulation time 27146403 ps
CPU time 0.98 seconds
Started Apr 18 02:25:17 PM PDT 24
Finished Apr 18 02:25:19 PM PDT 24
Peak memory 215512 kb
Host smart-a5a62a41-7635-4cb5-816e-cfa35fc2fc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601073847 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3601073847
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3493813667
Short name T630
Test name
Test status
Simulation time 23168771 ps
CPU time 0.95 seconds
Started Apr 18 02:25:18 PM PDT 24
Finished Apr 18 02:25:20 PM PDT 24
Peak memory 214924 kb
Host smart-911a3505-f48a-4649-aaf1-6fee34326d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493813667 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3493813667
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3647353671
Short name T99
Test name
Test status
Simulation time 757766187 ps
CPU time 3.24 seconds
Started Apr 18 02:25:20 PM PDT 24
Finished Apr 18 02:25:24 PM PDT 24
Peak memory 214920 kb
Host smart-af7a1b40-1d02-4c3c-8779-b62535e26250
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647353671 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3647353671
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1079473613
Short name T623
Test name
Test status
Simulation time 773560162417 ps
CPU time 1490.48 seconds
Started Apr 18 02:25:18 PM PDT 24
Finished Apr 18 02:50:09 PM PDT 24
Peak memory 223364 kb
Host smart-0116b477-c7d1-40cc-8f1a-b548779d3e30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079473613 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1079473613
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.625509119
Short name T135
Test name
Test status
Simulation time 165619657 ps
CPU time 1.37 seconds
Started Apr 18 02:26:44 PM PDT 24
Finished Apr 18 02:26:46 PM PDT 24
Peak memory 217672 kb
Host smart-16cf60c9-1d1b-4e78-b098-e559388e78c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625509119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.625509119
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1082068908
Short name T141
Test name
Test status
Simulation time 79187981 ps
CPU time 1.96 seconds
Started Apr 18 02:26:51 PM PDT 24
Finished Apr 18 02:26:54 PM PDT 24
Peak memory 217684 kb
Host smart-004ab753-69a0-4b82-8d46-e371b196a100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082068908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1082068908
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3272736820
Short name T472
Test name
Test status
Simulation time 66390515 ps
CPU time 1.14 seconds
Started Apr 18 02:26:45 PM PDT 24
Finished Apr 18 02:26:47 PM PDT 24
Peak memory 216392 kb
Host smart-8542a32a-ea45-4fae-bb94-cf4662351c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272736820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3272736820
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2985119704
Short name T325
Test name
Test status
Simulation time 128453027 ps
CPU time 1.19 seconds
Started Apr 18 02:26:50 PM PDT 24
Finished Apr 18 02:26:53 PM PDT 24
Peak memory 216500 kb
Host smart-3c3b0ffe-341c-4634-8a31-67e7c3a30eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985119704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2985119704
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3097358271
Short name T483
Test name
Test status
Simulation time 42798228 ps
CPU time 1.25 seconds
Started Apr 18 02:26:48 PM PDT 24
Finished Apr 18 02:26:50 PM PDT 24
Peak memory 216364 kb
Host smart-42b897ce-03b1-4482-b8cc-46c9cfa2fc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097358271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3097358271
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2709603818
Short name T334
Test name
Test status
Simulation time 58253516 ps
CPU time 1.24 seconds
Started Apr 18 02:26:56 PM PDT 24
Finished Apr 18 02:26:59 PM PDT 24
Peak memory 216468 kb
Host smart-43e621b6-8463-4de8-ad5c-f00aeef8e9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709603818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2709603818
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3589991133
Short name T114
Test name
Test status
Simulation time 84313637 ps
CPU time 1.37 seconds
Started Apr 18 02:26:45 PM PDT 24
Finished Apr 18 02:26:47 PM PDT 24
Peak memory 217716 kb
Host smart-b986c25a-7b16-4f09-99a6-aee32dc250ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589991133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3589991133
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3655579448
Short name T592
Test name
Test status
Simulation time 243128524 ps
CPU time 3.38 seconds
Started Apr 18 02:26:44 PM PDT 24
Finished Apr 18 02:26:48 PM PDT 24
Peak memory 216764 kb
Host smart-c98e70c5-5eb1-4c3f-9f9d-6ca251132b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655579448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3655579448
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1662918009
Short name T482
Test name
Test status
Simulation time 256993469 ps
CPU time 3.35 seconds
Started Apr 18 02:26:56 PM PDT 24
Finished Apr 18 02:27:00 PM PDT 24
Peak memory 219020 kb
Host smart-29f9a294-48ab-4387-8aed-f7690a3fa4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662918009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1662918009
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.905206358
Short name T16
Test name
Test status
Simulation time 52434277 ps
CPU time 1.22 seconds
Started Apr 18 02:26:44 PM PDT 24
Finished Apr 18 02:26:46 PM PDT 24
Peak memory 216460 kb
Host smart-f002507b-c890-499a-b5e4-1829eff2c601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905206358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.905206358
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert_test.788124230
Short name T488
Test name
Test status
Simulation time 16199564 ps
CPU time 1.01 seconds
Started Apr 18 02:25:15 PM PDT 24
Finished Apr 18 02:25:17 PM PDT 24
Peak memory 206676 kb
Host smart-18556660-37ca-4dcf-a241-1a467290bcfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788124230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.788124230
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3361244017
Short name T684
Test name
Test status
Simulation time 22303676 ps
CPU time 0.87 seconds
Started Apr 18 02:25:16 PM PDT 24
Finished Apr 18 02:25:18 PM PDT 24
Peak memory 215336 kb
Host smart-b143d0f8-e79e-4141-ae1a-c5f45a3bbd25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361244017 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3361244017
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.2889018832
Short name T321
Test name
Test status
Simulation time 18256540 ps
CPU time 1.04 seconds
Started Apr 18 02:25:21 PM PDT 24
Finished Apr 18 02:25:22 PM PDT 24
Peak memory 217788 kb
Host smart-23b335e3-5394-46f3-b27a-38a0e614825c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889018832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2889018832
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2261664159
Short name T302
Test name
Test status
Simulation time 72895976 ps
CPU time 1.24 seconds
Started Apr 18 02:25:16 PM PDT 24
Finished Apr 18 02:25:17 PM PDT 24
Peak memory 217884 kb
Host smart-f4d57224-421d-43f4-be06-136e8c3f273c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261664159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2261664159
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1781935013
Short name T96
Test name
Test status
Simulation time 23912501 ps
CPU time 1 seconds
Started Apr 18 02:25:16 PM PDT 24
Finished Apr 18 02:25:18 PM PDT 24
Peak memory 215172 kb
Host smart-c7de3b58-68f0-48da-894c-1ea91dd13e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781935013 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1781935013
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.4290398850
Short name T151
Test name
Test status
Simulation time 36359513 ps
CPU time 0.91 seconds
Started Apr 18 02:25:15 PM PDT 24
Finished Apr 18 02:25:16 PM PDT 24
Peak memory 214976 kb
Host smart-acbfd9ff-b5b9-493a-a1ab-8b6da01c667e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290398850 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.4290398850
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.4023466140
Short name T289
Test name
Test status
Simulation time 313933239778 ps
CPU time 1835.48 seconds
Started Apr 18 02:25:16 PM PDT 24
Finished Apr 18 02:55:53 PM PDT 24
Peak memory 225256 kb
Host smart-e62b840f-3d3e-4ead-ac75-51c74481221d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023466140 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.4023466140
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.93609520
Short name T689
Test name
Test status
Simulation time 144448280 ps
CPU time 2.77 seconds
Started Apr 18 02:26:49 PM PDT 24
Finished Apr 18 02:26:53 PM PDT 24
Peak memory 218980 kb
Host smart-899f0096-342e-4d9d-912c-478b9d0301b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93609520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.93609520
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.117569909
Short name T833
Test name
Test status
Simulation time 73360853 ps
CPU time 1.1 seconds
Started Apr 18 02:26:45 PM PDT 24
Finished Apr 18 02:26:47 PM PDT 24
Peak memory 216400 kb
Host smart-a82bd8c7-666b-4b01-ad69-1874444410de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117569909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.117569909
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1534167357
Short name T780
Test name
Test status
Simulation time 92278397 ps
CPU time 1.12 seconds
Started Apr 18 02:26:46 PM PDT 24
Finished Apr 18 02:26:48 PM PDT 24
Peak memory 216396 kb
Host smart-a149b8cd-a523-4e52-81fa-fcbd5bbe3a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534167357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1534167357
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2507548512
Short name T308
Test name
Test status
Simulation time 78562799 ps
CPU time 1.09 seconds
Started Apr 18 02:26:44 PM PDT 24
Finished Apr 18 02:26:46 PM PDT 24
Peak memory 216212 kb
Host smart-beadab9c-9598-45da-9555-1448fb2ac967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507548512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2507548512
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1473703135
Short name T527
Test name
Test status
Simulation time 89883160 ps
CPU time 1.27 seconds
Started Apr 18 02:26:46 PM PDT 24
Finished Apr 18 02:26:49 PM PDT 24
Peak memory 217700 kb
Host smart-d3177415-6a26-44c7-8d02-feefc2875080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473703135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1473703135
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3120313101
Short name T440
Test name
Test status
Simulation time 39318044 ps
CPU time 1.37 seconds
Started Apr 18 02:26:44 PM PDT 24
Finished Apr 18 02:26:46 PM PDT 24
Peak memory 217428 kb
Host smart-566cdd71-7dab-4cba-9460-1c6fc297385b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120313101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3120313101
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2909169802
Short name T732
Test name
Test status
Simulation time 76066076 ps
CPU time 1.35 seconds
Started Apr 18 02:26:46 PM PDT 24
Finished Apr 18 02:26:48 PM PDT 24
Peak memory 217692 kb
Host smart-bdeb6eea-5987-430d-827d-fde402371264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909169802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2909169802
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3876262878
Short name T700
Test name
Test status
Simulation time 40908648 ps
CPU time 1.28 seconds
Started Apr 18 02:26:56 PM PDT 24
Finished Apr 18 02:26:58 PM PDT 24
Peak memory 216316 kb
Host smart-45d80032-af9e-4760-abd1-aec3f1b6b9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876262878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3876262878
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.511552489
Short name T38
Test name
Test status
Simulation time 227984814 ps
CPU time 3.12 seconds
Started Apr 18 02:26:46 PM PDT 24
Finished Apr 18 02:26:50 PM PDT 24
Peak memory 218908 kb
Host smart-f521b560-eeeb-48c0-8691-a2047886c68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511552489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.511552489
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2056993627
Short name T715
Test name
Test status
Simulation time 87216811 ps
CPU time 1.33 seconds
Started Apr 18 02:26:43 PM PDT 24
Finished Apr 18 02:26:46 PM PDT 24
Peak memory 216672 kb
Host smart-e2719df8-cee9-466e-a651-adb08580764f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056993627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2056993627
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.3256111985
Short name T670
Test name
Test status
Simulation time 50872944 ps
CPU time 0.89 seconds
Started Apr 18 02:25:20 PM PDT 24
Finished Apr 18 02:25:22 PM PDT 24
Peak memory 205852 kb
Host smart-3760de25-e521-4531-8f92-b71ab805c803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256111985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3256111985
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.4275850965
Short name T446
Test name
Test status
Simulation time 27398716 ps
CPU time 0.82 seconds
Started Apr 18 02:25:20 PM PDT 24
Finished Apr 18 02:25:21 PM PDT 24
Peak memory 215584 kb
Host smart-12baf5dc-6039-4135-9998-69e3a80fd843
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275850965 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.4275850965
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.397775665
Short name T477
Test name
Test status
Simulation time 120461217 ps
CPU time 1.14 seconds
Started Apr 18 02:25:22 PM PDT 24
Finished Apr 18 02:25:24 PM PDT 24
Peak memory 217740 kb
Host smart-df125b5f-a3a3-4c8b-ab6e-1393fb711dd2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397775665 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.397775665
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1413160392
Short name T626
Test name
Test status
Simulation time 18715724 ps
CPU time 1.09 seconds
Started Apr 18 02:25:25 PM PDT 24
Finished Apr 18 02:25:27 PM PDT 24
Peak memory 217880 kb
Host smart-56cc0b77-8463-4fb6-9e18-b0a4a10a5f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413160392 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1413160392
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3260858088
Short name T595
Test name
Test status
Simulation time 107191090 ps
CPU time 1.08 seconds
Started Apr 18 02:25:26 PM PDT 24
Finished Apr 18 02:25:28 PM PDT 24
Peak memory 216488 kb
Host smart-cb9c27b9-0663-4101-b8e9-281ef3b166ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260858088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3260858088
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.4159911159
Short name T382
Test name
Test status
Simulation time 37343043 ps
CPU time 0.96 seconds
Started Apr 18 02:25:17 PM PDT 24
Finished Apr 18 02:25:19 PM PDT 24
Peak memory 223552 kb
Host smart-46f91b97-9368-40b2-a92c-19a1f3d8942a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159911159 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.4159911159
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1915130142
Short name T303
Test name
Test status
Simulation time 16344232 ps
CPU time 1.01 seconds
Started Apr 18 02:25:17 PM PDT 24
Finished Apr 18 02:25:19 PM PDT 24
Peak memory 215012 kb
Host smart-b3128ee8-3d02-4000-acf7-e38087e178be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915130142 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1915130142
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3279154258
Short name T496
Test name
Test status
Simulation time 582094414 ps
CPU time 5.06 seconds
Started Apr 18 02:25:19 PM PDT 24
Finished Apr 18 02:25:24 PM PDT 24
Peak memory 217456 kb
Host smart-21a267aa-5ae2-4588-9688-91d71e4c8e03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279154258 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3279154258
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1367520556
Short name T664
Test name
Test status
Simulation time 83546836257 ps
CPU time 917.66 seconds
Started Apr 18 02:25:18 PM PDT 24
Finished Apr 18 02:40:37 PM PDT 24
Peak memory 219776 kb
Host smart-90a837fb-113d-4903-b2dc-f162df49401d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367520556 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1367520556
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/281.edn_genbits.66159337
Short name T698
Test name
Test status
Simulation time 38037606 ps
CPU time 1.39 seconds
Started Apr 18 02:26:45 PM PDT 24
Finished Apr 18 02:26:48 PM PDT 24
Peak memory 217496 kb
Host smart-4b7dcad6-3066-4fd5-a939-d32ec21a146e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66159337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.66159337
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2924680492
Short name T741
Test name
Test status
Simulation time 66372658 ps
CPU time 1.15 seconds
Started Apr 18 02:26:56 PM PDT 24
Finished Apr 18 02:26:58 PM PDT 24
Peak memory 216676 kb
Host smart-fbef7b07-5726-4a76-8d4b-dc62dd5b3c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924680492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2924680492
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1685613586
Short name T810
Test name
Test status
Simulation time 186012966 ps
CPU time 1.31 seconds
Started Apr 18 02:26:43 PM PDT 24
Finished Apr 18 02:26:45 PM PDT 24
Peak memory 216360 kb
Host smart-fa026742-093d-42f2-91cb-50800f3ea4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685613586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1685613586
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.469995279
Short name T534
Test name
Test status
Simulation time 46665068 ps
CPU time 1.49 seconds
Started Apr 18 02:26:51 PM PDT 24
Finished Apr 18 02:26:54 PM PDT 24
Peak memory 216412 kb
Host smart-60d7f26b-9fe1-40b3-884b-ab4736c0b5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469995279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.469995279
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.975112692
Short name T138
Test name
Test status
Simulation time 43278036 ps
CPU time 1.43 seconds
Started Apr 18 02:26:43 PM PDT 24
Finished Apr 18 02:26:45 PM PDT 24
Peak memory 217328 kb
Host smart-0fe1c6c2-be40-4ed0-99e0-e8e77fa45832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975112692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.975112692
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.326761387
Short name T230
Test name
Test status
Simulation time 169565508 ps
CPU time 1.08 seconds
Started Apr 18 02:26:45 PM PDT 24
Finished Apr 18 02:26:47 PM PDT 24
Peak memory 216400 kb
Host smart-728e79f3-d0db-4688-a2a8-346640eeb80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326761387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.326761387
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1358101285
Short name T571
Test name
Test status
Simulation time 136540668 ps
CPU time 2.91 seconds
Started Apr 18 02:26:46 PM PDT 24
Finished Apr 18 02:26:50 PM PDT 24
Peak memory 218472 kb
Host smart-f57a5c56-3009-4e33-b4e8-946ff42e08b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358101285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1358101285
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.599941475
Short name T750
Test name
Test status
Simulation time 52118105 ps
CPU time 1.25 seconds
Started Apr 18 02:26:49 PM PDT 24
Finished Apr 18 02:26:51 PM PDT 24
Peak memory 216576 kb
Host smart-d55d018f-5028-4fcb-820f-b71d3433eef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599941475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.599941475
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.891671982
Short name T526
Test name
Test status
Simulation time 154201115 ps
CPU time 1.17 seconds
Started Apr 18 02:26:53 PM PDT 24
Finished Apr 18 02:26:55 PM PDT 24
Peak memory 216432 kb
Host smart-2ec64cb2-08d7-4017-a49a-cb043bbd473e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891671982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.891671982
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1552097337
Short name T28
Test name
Test status
Simulation time 42373471 ps
CPU time 1.24 seconds
Started Apr 18 02:25:25 PM PDT 24
Finished Apr 18 02:25:27 PM PDT 24
Peak memory 215396 kb
Host smart-c68a5ae7-0fda-469b-a392-18582a1b3ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552097337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1552097337
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3196623847
Short name T129
Test name
Test status
Simulation time 57632001 ps
CPU time 0.93 seconds
Started Apr 18 02:25:23 PM PDT 24
Finished Apr 18 02:25:24 PM PDT 24
Peak memory 206600 kb
Host smart-0e85d68a-426b-4f6b-a8e2-4c6be17d4e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196623847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3196623847
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.626649354
Short name T83
Test name
Test status
Simulation time 10739794 ps
CPU time 0.88 seconds
Started Apr 18 02:25:21 PM PDT 24
Finished Apr 18 02:25:23 PM PDT 24
Peak memory 215716 kb
Host smart-255a32f0-9e89-4291-aac8-ffe0c9d80f87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626649354 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.626649354
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1494992789
Short name T26
Test name
Test status
Simulation time 71151809 ps
CPU time 1.08 seconds
Started Apr 18 02:25:20 PM PDT 24
Finished Apr 18 02:25:22 PM PDT 24
Peak memory 216328 kb
Host smart-021a8ca2-ff49-433f-8796-64279c62ec2a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494992789 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1494992789
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2772213830
Short name T63
Test name
Test status
Simulation time 30762912 ps
CPU time 0.86 seconds
Started Apr 18 02:25:25 PM PDT 24
Finished Apr 18 02:25:27 PM PDT 24
Peak memory 217720 kb
Host smart-fff24f9d-396f-4e2f-96dd-340913f5b557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772213830 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2772213830
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1563392915
Short name T829
Test name
Test status
Simulation time 21963762 ps
CPU time 1.12 seconds
Started Apr 18 02:25:20 PM PDT 24
Finished Apr 18 02:25:22 PM PDT 24
Peak memory 217512 kb
Host smart-5f90e662-e88e-455e-834d-30d296acd3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563392915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1563392915
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_smoke.2020315518
Short name T406
Test name
Test status
Simulation time 47624882 ps
CPU time 0.91 seconds
Started Apr 18 02:25:22 PM PDT 24
Finished Apr 18 02:25:24 PM PDT 24
Peak memory 214988 kb
Host smart-d9cf968a-ffaf-4fe7-89a3-3ce74bf3bf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020315518 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2020315518
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.498732374
Short name T806
Test name
Test status
Simulation time 462365392 ps
CPU time 2.82 seconds
Started Apr 18 02:25:22 PM PDT 24
Finished Apr 18 02:25:25 PM PDT 24
Peak memory 214872 kb
Host smart-98408cd8-b878-4942-9ef4-d23574ddeaea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498732374 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.498732374
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/290.edn_genbits.900726878
Short name T588
Test name
Test status
Simulation time 199134211 ps
CPU time 1.09 seconds
Started Apr 18 02:26:52 PM PDT 24
Finished Apr 18 02:26:54 PM PDT 24
Peak memory 216552 kb
Host smart-facad7f2-6e94-4fbc-972c-bf0990e420b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900726878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.900726878
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1922075177
Short name T413
Test name
Test status
Simulation time 42372029 ps
CPU time 1.35 seconds
Started Apr 18 02:26:51 PM PDT 24
Finished Apr 18 02:26:54 PM PDT 24
Peak memory 216232 kb
Host smart-8bf3f43c-06ca-478b-bc63-7443ec5f4dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922075177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1922075177
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.4269426235
Short name T306
Test name
Test status
Simulation time 28682865 ps
CPU time 1.2 seconds
Started Apr 18 02:26:49 PM PDT 24
Finished Apr 18 02:26:51 PM PDT 24
Peak memory 216632 kb
Host smart-6bafcbff-ba94-4b1c-9356-8fb12c08a27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269426235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.4269426235
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.273277681
Short name T718
Test name
Test status
Simulation time 39207657 ps
CPU time 1.21 seconds
Started Apr 18 02:26:54 PM PDT 24
Finished Apr 18 02:26:56 PM PDT 24
Peak memory 216380 kb
Host smart-f14697b7-7ce3-46ba-86f3-d690b4007fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273277681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.273277681
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3453746904
Short name T362
Test name
Test status
Simulation time 48847716 ps
CPU time 1.14 seconds
Started Apr 18 02:26:49 PM PDT 24
Finished Apr 18 02:26:51 PM PDT 24
Peak memory 216208 kb
Host smart-c2c3e1f2-6eb2-435f-a060-d289b3f3fbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453746904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3453746904
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1355321144
Short name T530
Test name
Test status
Simulation time 41426555 ps
CPU time 1.41 seconds
Started Apr 18 02:26:50 PM PDT 24
Finished Apr 18 02:26:52 PM PDT 24
Peak memory 216260 kb
Host smart-05047bc4-76fe-476a-adc2-62a33cf3418d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355321144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1355321144
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1106214687
Short name T523
Test name
Test status
Simulation time 46095930 ps
CPU time 1.74 seconds
Started Apr 18 02:26:49 PM PDT 24
Finished Apr 18 02:26:51 PM PDT 24
Peak memory 217756 kb
Host smart-4641728e-6be4-446b-a0b4-04c5343527d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106214687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1106214687
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.476460533
Short name T366
Test name
Test status
Simulation time 23260659 ps
CPU time 1.06 seconds
Started Apr 18 02:26:49 PM PDT 24
Finished Apr 18 02:26:51 PM PDT 24
Peak memory 216360 kb
Host smart-d26e62f8-b5d0-4a25-8baf-7551fce194bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476460533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.476460533
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2973642908
Short name T481
Test name
Test status
Simulation time 65211684 ps
CPU time 1.35 seconds
Started Apr 18 02:26:49 PM PDT 24
Finished Apr 18 02:26:51 PM PDT 24
Peak memory 216228 kb
Host smart-37892fa7-b485-4bb9-98d1-1af9d86f02f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973642908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2973642908
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2392629152
Short name T511
Test name
Test status
Simulation time 139589591 ps
CPU time 1.24 seconds
Started Apr 18 02:26:48 PM PDT 24
Finished Apr 18 02:26:50 PM PDT 24
Peak memory 216336 kb
Host smart-c4c8318c-8ae8-445e-b4d2-fcf2c9146797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392629152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2392629152
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert_test.3160145756
Short name T582
Test name
Test status
Simulation time 13847973 ps
CPU time 0.89 seconds
Started Apr 18 02:24:37 PM PDT 24
Finished Apr 18 02:24:38 PM PDT 24
Peak memory 206388 kb
Host smart-00f7c685-3478-4a9b-87e2-1bfd9f27eb63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160145756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3160145756
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.726483361
Short name T617
Test name
Test status
Simulation time 50419171 ps
CPU time 0.83 seconds
Started Apr 18 02:24:39 PM PDT 24
Finished Apr 18 02:24:41 PM PDT 24
Peak memory 215340 kb
Host smart-426f5af8-b04c-445e-b7f8-e23a464d2a14
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726483361 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.726483361
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.391174196
Short name T52
Test name
Test status
Simulation time 49581029 ps
CPU time 1.11 seconds
Started Apr 18 02:24:32 PM PDT 24
Finished Apr 18 02:24:34 PM PDT 24
Peak memory 216284 kb
Host smart-b2bebd15-e62e-4f59-a160-5af106c11f02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391174196 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.391174196
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.214147352
Short name T53
Test name
Test status
Simulation time 62515203 ps
CPU time 1.02 seconds
Started Apr 18 02:24:41 PM PDT 24
Finished Apr 18 02:24:43 PM PDT 24
Peak memory 219068 kb
Host smart-11bbc08a-877c-413c-9d91-14aa3fcbbd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214147352 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.214147352
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3220793528
Short name T17
Test name
Test status
Simulation time 38022386 ps
CPU time 1.42 seconds
Started Apr 18 02:24:39 PM PDT 24
Finished Apr 18 02:24:41 PM PDT 24
Peak memory 217656 kb
Host smart-f21eb459-1196-478c-8384-91b37fa34d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220793528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3220793528
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.661375233
Short name T119
Test name
Test status
Simulation time 22720398 ps
CPU time 1.17 seconds
Started Apr 18 02:24:30 PM PDT 24
Finished Apr 18 02:24:31 PM PDT 24
Peak memory 223668 kb
Host smart-0f5e3303-bc27-4d9f-a1d4-cc328ce5f1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661375233 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.661375233
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.664316200
Short name T255
Test name
Test status
Simulation time 17993984 ps
CPU time 1.01 seconds
Started Apr 18 02:24:39 PM PDT 24
Finished Apr 18 02:24:41 PM PDT 24
Peak memory 206748 kb
Host smart-c1db2fa6-d3bd-4050-b68f-75a275857c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664316200 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.664316200
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.605911053
Short name T124
Test name
Test status
Simulation time 3144447746 ps
CPU time 6.55 seconds
Started Apr 18 02:24:35 PM PDT 24
Finished Apr 18 02:24:42 PM PDT 24
Peak memory 235820 kb
Host smart-a8ed259a-dc5e-4dd8-8730-620e86edc119
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605911053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.605911053
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3270508713
Short name T781
Test name
Test status
Simulation time 16475646 ps
CPU time 0.93 seconds
Started Apr 18 02:24:30 PM PDT 24
Finished Apr 18 02:24:32 PM PDT 24
Peak memory 215000 kb
Host smart-d15728ff-2063-4e6f-9007-a61880292bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270508713 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3270508713
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3180040673
Short name T264
Test name
Test status
Simulation time 109507955 ps
CPU time 2.62 seconds
Started Apr 18 02:24:29 PM PDT 24
Finished Apr 18 02:24:32 PM PDT 24
Peak memory 215056 kb
Host smart-818bf300-c772-452b-8609-0f940a84aa90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180040673 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3180040673
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2596831605
Short name T183
Test name
Test status
Simulation time 205675199770 ps
CPU time 1339.44 seconds
Started Apr 18 02:24:27 PM PDT 24
Finished Apr 18 02:46:47 PM PDT 24
Peak memory 224452 kb
Host smart-57e141cb-c495-452c-abee-bd5fbc7f9395
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596831605 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2596831605
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1043668464
Short name T74
Test name
Test status
Simulation time 100328690 ps
CPU time 1.33 seconds
Started Apr 18 02:25:22 PM PDT 24
Finished Apr 18 02:25:23 PM PDT 24
Peak memory 215412 kb
Host smart-8f39fc0c-049d-4027-90ac-24d4c14acad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043668464 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1043668464
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2963995848
Short name T426
Test name
Test status
Simulation time 63168578 ps
CPU time 0.94 seconds
Started Apr 18 02:25:21 PM PDT 24
Finished Apr 18 02:25:22 PM PDT 24
Peak memory 205832 kb
Host smart-fce6a4c3-a89c-4445-8820-49699697a938
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963995848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2963995848
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2794118983
Short name T160
Test name
Test status
Simulation time 25589380 ps
CPU time 0.83 seconds
Started Apr 18 02:25:20 PM PDT 24
Finished Apr 18 02:25:22 PM PDT 24
Peak memory 215620 kb
Host smart-5ddd7ce3-69e5-4380-8645-55de86428f12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794118983 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2794118983
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3627537576
Short name T485
Test name
Test status
Simulation time 22626288 ps
CPU time 1.02 seconds
Started Apr 18 02:25:23 PM PDT 24
Finished Apr 18 02:25:24 PM PDT 24
Peak memory 217500 kb
Host smart-d3986503-6722-4e65-976b-f5c5c2807f45
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627537576 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3627537576
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.64058637
Short name T64
Test name
Test status
Simulation time 175449558 ps
CPU time 1.09 seconds
Started Apr 18 02:25:21 PM PDT 24
Finished Apr 18 02:25:23 PM PDT 24
Peak memory 219124 kb
Host smart-6f657626-ea3d-424a-9e5d-f71280767d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64058637 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.64058637
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2609290514
Short name T287
Test name
Test status
Simulation time 165204187 ps
CPU time 3.39 seconds
Started Apr 18 02:25:20 PM PDT 24
Finished Apr 18 02:25:24 PM PDT 24
Peak memory 217628 kb
Host smart-eebad4e2-067f-4b9b-b0e1-d9d26c343456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609290514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2609290514
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2035268024
Short name T518
Test name
Test status
Simulation time 31853282 ps
CPU time 1.06 seconds
Started Apr 18 02:25:20 PM PDT 24
Finished Apr 18 02:25:21 PM PDT 24
Peak memory 223776 kb
Host smart-ba7eef30-aab1-4787-9837-6ebba6c3eb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035268024 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2035268024
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2537170701
Short name T685
Test name
Test status
Simulation time 29012222 ps
CPU time 0.93 seconds
Started Apr 18 02:25:23 PM PDT 24
Finished Apr 18 02:25:24 PM PDT 24
Peak memory 215020 kb
Host smart-202353f9-0eea-4c53-bdb4-34aeed8a6221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537170701 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2537170701
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2730655037
Short name T529
Test name
Test status
Simulation time 1750449874 ps
CPU time 4.12 seconds
Started Apr 18 02:25:20 PM PDT 24
Finished Apr 18 02:25:25 PM PDT 24
Peak memory 216040 kb
Host smart-ef8f4de1-f58a-4112-a69d-d94bc74a4c6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730655037 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2730655037
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1007557355
Short name T181
Test name
Test status
Simulation time 203510465068 ps
CPU time 1119.13 seconds
Started Apr 18 02:25:21 PM PDT 24
Finished Apr 18 02:44:00 PM PDT 24
Peak memory 222188 kb
Host smart-5607ddda-1ad8-4522-bf19-d54b3003c1e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007557355 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1007557355
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1969745887
Short name T228
Test name
Test status
Simulation time 41819554 ps
CPU time 1.14 seconds
Started Apr 18 02:25:25 PM PDT 24
Finished Apr 18 02:25:26 PM PDT 24
Peak memory 215432 kb
Host smart-9b406951-2fcc-426e-82ec-694fcb402ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969745887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1969745887
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.4099887027
Short name T307
Test name
Test status
Simulation time 68326786 ps
CPU time 0.86 seconds
Started Apr 18 02:25:25 PM PDT 24
Finished Apr 18 02:25:27 PM PDT 24
Peak memory 205656 kb
Host smart-e823156d-2167-43df-a886-fec3038cc1c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099887027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.4099887027
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.35722011
Short name T825
Test name
Test status
Simulation time 11106906 ps
CPU time 0.84 seconds
Started Apr 18 02:25:26 PM PDT 24
Finished Apr 18 02:25:28 PM PDT 24
Peak memory 215440 kb
Host smart-2b80a933-7b75-47ba-ab8d-3a5cdbba0a65
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35722011 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.35722011
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.1978469908
Short name T464
Test name
Test status
Simulation time 25061865 ps
CPU time 1.07 seconds
Started Apr 18 02:25:32 PM PDT 24
Finished Apr 18 02:25:34 PM PDT 24
Peak memory 219084 kb
Host smart-4705ce06-e493-4bcc-bc3f-59e1d429855a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978469908 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1978469908
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.4178451379
Short name T267
Test name
Test status
Simulation time 152205559 ps
CPU time 3.36 seconds
Started Apr 18 02:25:22 PM PDT 24
Finished Apr 18 02:25:26 PM PDT 24
Peak memory 217836 kb
Host smart-9edad836-2cd6-4dfe-b546-9bfb20f5fc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178451379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.4178451379
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.769087075
Short name T13
Test name
Test status
Simulation time 39855596 ps
CPU time 1.02 seconds
Started Apr 18 02:25:22 PM PDT 24
Finished Apr 18 02:25:23 PM PDT 24
Peak memory 223740 kb
Host smart-4fe06468-e9f4-4a82-b3f9-cf17d337b23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769087075 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.769087075
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.834759927
Short name T517
Test name
Test status
Simulation time 18919243 ps
CPU time 1.06 seconds
Started Apr 18 02:25:25 PM PDT 24
Finished Apr 18 02:25:27 PM PDT 24
Peak memory 214992 kb
Host smart-b6909d62-920d-4d52-8219-8d836b589268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834759927 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.834759927
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1925788100
Short name T737
Test name
Test status
Simulation time 161905826 ps
CPU time 3.14 seconds
Started Apr 18 02:25:25 PM PDT 24
Finished Apr 18 02:25:28 PM PDT 24
Peak memory 214948 kb
Host smart-56ef5281-69cd-4fca-9764-37523cb834c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925788100 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1925788100
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1467073838
Short name T401
Test name
Test status
Simulation time 294958883314 ps
CPU time 817.9 seconds
Started Apr 18 02:25:21 PM PDT 24
Finished Apr 18 02:38:59 PM PDT 24
Peak memory 220584 kb
Host smart-3a6ff97c-d2c2-46e5-9e95-f82de40d996c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467073838 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1467073838
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1989338544
Short name T659
Test name
Test status
Simulation time 43954587 ps
CPU time 1.2 seconds
Started Apr 18 02:25:26 PM PDT 24
Finished Apr 18 02:25:28 PM PDT 24
Peak memory 215412 kb
Host smart-d6e65435-f7b5-43a0-80c5-f421e325c71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989338544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1989338544
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1798784746
Short name T493
Test name
Test status
Simulation time 70043014 ps
CPU time 0.98 seconds
Started Apr 18 02:25:30 PM PDT 24
Finished Apr 18 02:25:32 PM PDT 24
Peak memory 205856 kb
Host smart-01baa4f8-1b87-4d22-87bf-521c4edbc291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798784746 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1798784746
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3642126791
Short name T167
Test name
Test status
Simulation time 35215088 ps
CPU time 0.84 seconds
Started Apr 18 02:25:32 PM PDT 24
Finished Apr 18 02:25:34 PM PDT 24
Peak memory 215724 kb
Host smart-5d1e2908-d961-479f-8b46-afacf073eca2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642126791 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3642126791
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_genbits.3386899156
Short name T774
Test name
Test status
Simulation time 48959255 ps
CPU time 1.18 seconds
Started Apr 18 02:25:24 PM PDT 24
Finished Apr 18 02:25:26 PM PDT 24
Peak memory 216312 kb
Host smart-9be5f704-149c-42f3-aa77-e3794f3e8968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386899156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3386899156
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.699986886
Short name T615
Test name
Test status
Simulation time 37568366 ps
CPU time 0.97 seconds
Started Apr 18 02:25:25 PM PDT 24
Finished Apr 18 02:25:27 PM PDT 24
Peak memory 223700 kb
Host smart-ef2fabfe-df33-4081-98c7-835fc3476de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699986886 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.699986886
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.358821181
Short name T336
Test name
Test status
Simulation time 16645814 ps
CPU time 0.94 seconds
Started Apr 18 02:25:25 PM PDT 24
Finished Apr 18 02:25:27 PM PDT 24
Peak memory 214948 kb
Host smart-9d9f00d7-f11e-4f7b-ad2b-809fc02756b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358821181 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.358821181
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2851411472
Short name T454
Test name
Test status
Simulation time 568882056 ps
CPU time 3.78 seconds
Started Apr 18 02:25:25 PM PDT 24
Finished Apr 18 02:25:30 PM PDT 24
Peak memory 218620 kb
Host smart-2aeed218-cb78-4d5f-8615-5ca036957a22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851411472 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2851411472
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2220565429
Short name T509
Test name
Test status
Simulation time 22548851113 ps
CPU time 517.52 seconds
Started Apr 18 02:25:32 PM PDT 24
Finished Apr 18 02:34:11 PM PDT 24
Peak memory 217516 kb
Host smart-c6527923-1a2e-49d8-88d6-1cd0716eaa3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220565429 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2220565429
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1986972103
Short name T673
Test name
Test status
Simulation time 89486075 ps
CPU time 1.12 seconds
Started Apr 18 02:25:32 PM PDT 24
Finished Apr 18 02:25:34 PM PDT 24
Peak memory 215340 kb
Host smart-76adc73b-a930-4b2a-9dbb-7e99e92ae115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986972103 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1986972103
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2870915969
Short name T786
Test name
Test status
Simulation time 62123890 ps
CPU time 0.86 seconds
Started Apr 18 02:25:31 PM PDT 24
Finished Apr 18 02:25:32 PM PDT 24
Peak memory 205680 kb
Host smart-2fce2240-2360-4e78-bcb1-e86ec3bdd802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870915969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2870915969
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3980085648
Short name T131
Test name
Test status
Simulation time 13045834 ps
CPU time 0.93 seconds
Started Apr 18 02:25:30 PM PDT 24
Finished Apr 18 02:25:31 PM PDT 24
Peak memory 215540 kb
Host smart-8afdafef-9398-486d-877d-1ae42d4c1296
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980085648 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3980085648
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3198637560
Short name T51
Test name
Test status
Simulation time 59740625 ps
CPU time 1.19 seconds
Started Apr 18 02:25:35 PM PDT 24
Finished Apr 18 02:25:37 PM PDT 24
Peak memory 216296 kb
Host smart-19f988ac-3951-49cb-ae1f-4c4fb96e43fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198637560 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3198637560
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2855207991
Short name T743
Test name
Test status
Simulation time 38514479 ps
CPU time 1.08 seconds
Started Apr 18 02:25:34 PM PDT 24
Finished Apr 18 02:25:36 PM PDT 24
Peak memory 216448 kb
Host smart-da29f039-45eb-4c91-8eb6-c2b4ef7b1517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855207991 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2855207991
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.4042433790
Short name T580
Test name
Test status
Simulation time 67269618 ps
CPU time 1.15 seconds
Started Apr 18 02:25:24 PM PDT 24
Finished Apr 18 02:25:26 PM PDT 24
Peak memory 216372 kb
Host smart-75eb67c2-d8e4-48dd-84a0-60b44d6c6dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042433790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.4042433790
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1164305669
Short name T648
Test name
Test status
Simulation time 22309400 ps
CPU time 0.91 seconds
Started Apr 18 02:25:30 PM PDT 24
Finished Apr 18 02:25:31 PM PDT 24
Peak memory 215536 kb
Host smart-bfd9a2b6-608f-4fd8-bbb7-1daa8f9eab9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164305669 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1164305669
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.158880124
Short name T444
Test name
Test status
Simulation time 49588968 ps
CPU time 0.9 seconds
Started Apr 18 02:25:32 PM PDT 24
Finished Apr 18 02:25:34 PM PDT 24
Peak memory 214572 kb
Host smart-28c203fc-38dd-4605-8443-bb5cb76e88f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158880124 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.158880124
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3361608098
Short name T121
Test name
Test status
Simulation time 609667184 ps
CPU time 4.37 seconds
Started Apr 18 02:25:25 PM PDT 24
Finished Apr 18 02:25:30 PM PDT 24
Peak memory 216264 kb
Host smart-d18122d9-f08a-4653-bff6-d737244c26ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361608098 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3361608098
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.4106193121
Short name T579
Test name
Test status
Simulation time 109069873060 ps
CPU time 531.27 seconds
Started Apr 18 02:25:31 PM PDT 24
Finished Apr 18 02:34:23 PM PDT 24
Peak memory 218556 kb
Host smart-ee6491f0-8ece-4768-987a-5f23f623b852
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106193121 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.4106193121
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2888337529
Short name T252
Test name
Test status
Simulation time 30771986 ps
CPU time 1.3 seconds
Started Apr 18 02:25:34 PM PDT 24
Finished Apr 18 02:25:36 PM PDT 24
Peak memory 215396 kb
Host smart-1bd5e4d4-47e5-4e6c-800d-1e63f9b0ca17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888337529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2888337529
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1516802502
Short name T352
Test name
Test status
Simulation time 17556280 ps
CPU time 0.91 seconds
Started Apr 18 02:25:32 PM PDT 24
Finished Apr 18 02:25:33 PM PDT 24
Peak memory 205956 kb
Host smart-28588164-c362-4f77-9a8e-7bec87436576
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516802502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1516802502
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.761536035
Short name T642
Test name
Test status
Simulation time 13351069 ps
CPU time 0.89 seconds
Started Apr 18 02:25:30 PM PDT 24
Finished Apr 18 02:25:31 PM PDT 24
Peak memory 215468 kb
Host smart-250b5126-b504-4bd0-99a2-db22b0176afc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761536035 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.761536035
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.2597656745
Short name T453
Test name
Test status
Simulation time 19435694 ps
CPU time 1.18 seconds
Started Apr 18 02:25:33 PM PDT 24
Finished Apr 18 02:25:34 PM PDT 24
Peak memory 232136 kb
Host smart-31eb5840-d6e4-4277-bd0e-c516664299aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597656745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2597656745
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1865399865
Short name T353
Test name
Test status
Simulation time 43205885 ps
CPU time 1.57 seconds
Started Apr 18 02:25:33 PM PDT 24
Finished Apr 18 02:25:35 PM PDT 24
Peak memory 217380 kb
Host smart-86329322-a868-43ed-b785-1bd0f0b9ebd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865399865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1865399865
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.959043231
Short name T118
Test name
Test status
Simulation time 21295905 ps
CPU time 1.22 seconds
Started Apr 18 02:25:33 PM PDT 24
Finished Apr 18 02:25:35 PM PDT 24
Peak memory 223704 kb
Host smart-f46868d6-a48e-490d-a604-162071a75de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959043231 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.959043231
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3066043926
Short name T195
Test name
Test status
Simulation time 104841153 ps
CPU time 0.89 seconds
Started Apr 18 02:25:32 PM PDT 24
Finished Apr 18 02:25:33 PM PDT 24
Peak memory 206788 kb
Host smart-ea982f82-5d54-4b95-ab27-36d107c8fda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066043926 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3066043926
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.4049625263
Short name T707
Test name
Test status
Simulation time 1328610083 ps
CPU time 3.95 seconds
Started Apr 18 02:25:36 PM PDT 24
Finished Apr 18 02:25:40 PM PDT 24
Peak memory 218576 kb
Host smart-e5ff701e-f833-47d4-a353-f8cadd73a5d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049625263 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.4049625263
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3894719656
Short name T489
Test name
Test status
Simulation time 734755469889 ps
CPU time 3167.23 seconds
Started Apr 18 02:25:33 PM PDT 24
Finished Apr 18 03:18:21 PM PDT 24
Peak memory 229480 kb
Host smart-8fcc29e6-ee30-4eda-af3e-58d94e7b94a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894719656 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3894719656
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3423944589
Short name T551
Test name
Test status
Simulation time 61313983 ps
CPU time 1.28 seconds
Started Apr 18 02:25:31 PM PDT 24
Finished Apr 18 02:25:33 PM PDT 24
Peak memory 215392 kb
Host smart-c79e729a-86e6-40e2-8bc5-b0cec82052b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423944589 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3423944589
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.927979116
Short name T117
Test name
Test status
Simulation time 38227208 ps
CPU time 0.87 seconds
Started Apr 18 02:25:40 PM PDT 24
Finished Apr 18 02:25:41 PM PDT 24
Peak memory 205544 kb
Host smart-87bea002-d00a-4aed-85e2-2cd9ad9c5739
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927979116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.927979116
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2003967834
Short name T823
Test name
Test status
Simulation time 12256012 ps
CPU time 0.94 seconds
Started Apr 18 02:25:34 PM PDT 24
Finished Apr 18 02:25:36 PM PDT 24
Peak memory 215772 kb
Host smart-2b82f25f-3f51-43cc-b690-51e916fc7b5b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003967834 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2003967834
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.742345510
Short name T798
Test name
Test status
Simulation time 32504617 ps
CPU time 1.23 seconds
Started Apr 18 02:25:35 PM PDT 24
Finished Apr 18 02:25:36 PM PDT 24
Peak memory 216252 kb
Host smart-be719830-b488-40d2-bbc1-87ebeab208b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742345510 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.742345510
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2596213735
Short name T690
Test name
Test status
Simulation time 47340791 ps
CPU time 0.92 seconds
Started Apr 18 02:25:31 PM PDT 24
Finished Apr 18 02:25:33 PM PDT 24
Peak memory 217716 kb
Host smart-dc837e79-7982-4a20-8f4d-46a75384dd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596213735 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2596213735
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3380398039
Short name T125
Test name
Test status
Simulation time 45458218 ps
CPU time 1.52 seconds
Started Apr 18 02:25:32 PM PDT 24
Finished Apr 18 02:25:34 PM PDT 24
Peak memory 217672 kb
Host smart-1d56f89a-2061-400c-9a43-81dd0235926e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380398039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3380398039
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2311905041
Short name T98
Test name
Test status
Simulation time 54939437 ps
CPU time 0.84 seconds
Started Apr 18 02:25:37 PM PDT 24
Finished Apr 18 02:25:39 PM PDT 24
Peak memory 214996 kb
Host smart-2ca82fdd-aed1-407f-9b51-834b3544f3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311905041 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2311905041
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3626291670
Short name T568
Test name
Test status
Simulation time 137344757 ps
CPU time 0.88 seconds
Started Apr 18 02:25:31 PM PDT 24
Finished Apr 18 02:25:33 PM PDT 24
Peak memory 214988 kb
Host smart-87a929f9-15eb-4342-8af9-efb29e86c917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626291670 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3626291670
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.697258916
Short name T495
Test name
Test status
Simulation time 834834650 ps
CPU time 5.29 seconds
Started Apr 18 02:25:33 PM PDT 24
Finished Apr 18 02:25:38 PM PDT 24
Peak memory 216248 kb
Host smart-b2e64bfd-c642-423b-9c09-c193a036a9b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697258916 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.697258916
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2844209940
Short name T668
Test name
Test status
Simulation time 348353548011 ps
CPU time 687.89 seconds
Started Apr 18 02:25:34 PM PDT 24
Finished Apr 18 02:37:03 PM PDT 24
Peak memory 218404 kb
Host smart-45b9173f-0ff2-4997-95cb-3f0dc109bb01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844209940 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2844209940
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3616854415
Short name T258
Test name
Test status
Simulation time 103965440 ps
CPU time 1.22 seconds
Started Apr 18 02:25:35 PM PDT 24
Finished Apr 18 02:25:37 PM PDT 24
Peak memory 215412 kb
Host smart-0f6ea719-0041-4f6e-93b4-c66df88c2856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616854415 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3616854415
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2802080522
Short name T360
Test name
Test status
Simulation time 84949226 ps
CPU time 1.03 seconds
Started Apr 18 02:25:35 PM PDT 24
Finished Apr 18 02:25:37 PM PDT 24
Peak memory 205820 kb
Host smart-de01122f-e1a5-4529-ba2a-1c66acb11f73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802080522 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2802080522
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_err.2929872489
Short name T87
Test name
Test status
Simulation time 20524169 ps
CPU time 1.08 seconds
Started Apr 18 02:25:37 PM PDT 24
Finished Apr 18 02:25:38 PM PDT 24
Peak memory 217940 kb
Host smart-b36cb141-883e-4d1a-8f10-137ab21b771b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929872489 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2929872489
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3844739072
Short name T655
Test name
Test status
Simulation time 151315517 ps
CPU time 3 seconds
Started Apr 18 02:25:32 PM PDT 24
Finished Apr 18 02:25:36 PM PDT 24
Peak memory 218036 kb
Host smart-17d1fb1b-08aa-485f-b3ed-7c9447d065b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844739072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3844739072
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.769742436
Short name T350
Test name
Test status
Simulation time 21675181 ps
CPU time 1.11 seconds
Started Apr 18 02:25:37 PM PDT 24
Finished Apr 18 02:25:38 PM PDT 24
Peak memory 215416 kb
Host smart-b0547d94-6ecb-4e2e-b472-a2b7d9a0f083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769742436 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.769742436
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.4287789146
Short name T782
Test name
Test status
Simulation time 47217020 ps
CPU time 0.9 seconds
Started Apr 18 02:25:30 PM PDT 24
Finished Apr 18 02:25:32 PM PDT 24
Peak memory 214972 kb
Host smart-5d2184f3-c7d3-46cd-b291-16170a1655e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287789146 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.4287789146
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2497677875
Short name T677
Test name
Test status
Simulation time 263091684 ps
CPU time 2.99 seconds
Started Apr 18 02:25:35 PM PDT 24
Finished Apr 18 02:25:39 PM PDT 24
Peak memory 215008 kb
Host smart-8066b32b-8cb1-4191-b756-e73c52bb23d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497677875 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2497677875
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.651183723
Short name T342
Test name
Test status
Simulation time 61968169386 ps
CPU time 401.04 seconds
Started Apr 18 02:25:37 PM PDT 24
Finished Apr 18 02:32:19 PM PDT 24
Peak memory 217536 kb
Host smart-380e3eb3-feeb-46e1-bb9f-97e933dc1b1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651183723 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.651183723
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2045353362
Short name T257
Test name
Test status
Simulation time 48284632 ps
CPU time 1.24 seconds
Started Apr 18 02:25:37 PM PDT 24
Finished Apr 18 02:25:39 PM PDT 24
Peak memory 215404 kb
Host smart-33359ec8-63fd-47fb-831a-480a6d7851c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045353362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2045353362
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1176675074
Short name T717
Test name
Test status
Simulation time 17062270 ps
CPU time 0.96 seconds
Started Apr 18 02:25:38 PM PDT 24
Finished Apr 18 02:25:40 PM PDT 24
Peak memory 205868 kb
Host smart-20b89811-1676-4651-9a90-46cb9502db54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176675074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1176675074
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1057027374
Short name T163
Test name
Test status
Simulation time 37634609 ps
CPU time 0.91 seconds
Started Apr 18 02:25:35 PM PDT 24
Finished Apr 18 02:25:36 PM PDT 24
Peak memory 215696 kb
Host smart-b363c5b9-916f-49e0-8abc-5e83340ae55d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057027374 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1057027374
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_err.876972206
Short name T372
Test name
Test status
Simulation time 29981188 ps
CPU time 1.19 seconds
Started Apr 18 02:25:37 PM PDT 24
Finished Apr 18 02:25:39 PM PDT 24
Peak memory 218840 kb
Host smart-2fb10fde-923e-4893-b550-649a4ece6688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876972206 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.876972206
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2256130077
Short name T681
Test name
Test status
Simulation time 135216552 ps
CPU time 1.91 seconds
Started Apr 18 02:25:35 PM PDT 24
Finished Apr 18 02:25:38 PM PDT 24
Peak memory 216584 kb
Host smart-274be53c-6d31-40d3-8306-3ffe0e4dcc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256130077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2256130077
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2999738082
Short name T108
Test name
Test status
Simulation time 29695232 ps
CPU time 0.93 seconds
Started Apr 18 02:25:38 PM PDT 24
Finished Apr 18 02:25:40 PM PDT 24
Peak memory 215580 kb
Host smart-49cba48b-02de-4c21-9cc2-16eaccb201af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999738082 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2999738082
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1128261264
Short name T604
Test name
Test status
Simulation time 26507667 ps
CPU time 1.03 seconds
Started Apr 18 02:25:36 PM PDT 24
Finished Apr 18 02:25:38 PM PDT 24
Peak memory 214924 kb
Host smart-4f72e173-29a8-4277-92d1-1c568c4a1ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128261264 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1128261264
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1117538679
Short name T814
Test name
Test status
Simulation time 305676888 ps
CPU time 6.04 seconds
Started Apr 18 02:25:36 PM PDT 24
Finished Apr 18 02:25:43 PM PDT 24
Peak memory 216424 kb
Host smart-b56233f9-11b2-4a80-a6fc-1a3a2ecf825f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117538679 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1117538679
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1600945965
Short name T501
Test name
Test status
Simulation time 1154674228528 ps
CPU time 2268.22 seconds
Started Apr 18 02:25:36 PM PDT 24
Finished Apr 18 03:03:25 PM PDT 24
Peak memory 229752 kb
Host smart-ae933702-24d3-44f9-8909-e5051d6618fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600945965 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1600945965
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.4152099444
Short name T90
Test name
Test status
Simulation time 26769937 ps
CPU time 1.15 seconds
Started Apr 18 02:25:38 PM PDT 24
Finished Apr 18 02:25:40 PM PDT 24
Peak memory 215448 kb
Host smart-8bff4d81-1039-451c-8f8f-5666cd564fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152099444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.4152099444
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3890285516
Short name T422
Test name
Test status
Simulation time 70630896 ps
CPU time 1.61 seconds
Started Apr 18 02:25:41 PM PDT 24
Finished Apr 18 02:25:43 PM PDT 24
Peak memory 205972 kb
Host smart-7626fba7-2cbe-4cd1-b555-be826b8423d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890285516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3890285516
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3646977156
Short name T702
Test name
Test status
Simulation time 38177961 ps
CPU time 0.87 seconds
Started Apr 18 02:25:42 PM PDT 24
Finished Apr 18 02:25:44 PM PDT 24
Peak memory 215588 kb
Host smart-824d83fd-261b-498d-9fd4-c6b694826bc7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646977156 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3646977156
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2893306600
Short name T776
Test name
Test status
Simulation time 56934937 ps
CPU time 1.12 seconds
Started Apr 18 02:25:42 PM PDT 24
Finished Apr 18 02:25:43 PM PDT 24
Peak memory 216204 kb
Host smart-17e993f5-261e-4ca9-bd2d-961adabf9f7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893306600 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2893306600
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.218971205
Short name T637
Test name
Test status
Simulation time 32938710 ps
CPU time 1.02 seconds
Started Apr 18 02:25:40 PM PDT 24
Finished Apr 18 02:25:41 PM PDT 24
Peak memory 230788 kb
Host smart-12a43c5c-876b-465d-8a85-830571fe473c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218971205 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.218971205
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1549534681
Short name T521
Test name
Test status
Simulation time 64922811 ps
CPU time 1.69 seconds
Started Apr 18 02:25:36 PM PDT 24
Finished Apr 18 02:25:38 PM PDT 24
Peak memory 217836 kb
Host smart-c500d0e0-24c0-4a42-8e8c-fbac7b3d4568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549534681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1549534681
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2878781641
Short name T354
Test name
Test status
Simulation time 28430227 ps
CPU time 0.88 seconds
Started Apr 18 02:25:37 PM PDT 24
Finished Apr 18 02:25:39 PM PDT 24
Peak memory 215228 kb
Host smart-f80d688d-64ed-4ac4-b1d9-73008f9f9a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878781641 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2878781641
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3384904609
Short name T645
Test name
Test status
Simulation time 20765183 ps
CPU time 0.98 seconds
Started Apr 18 02:25:36 PM PDT 24
Finished Apr 18 02:25:38 PM PDT 24
Peak memory 206772 kb
Host smart-07dd08a5-8748-4733-bb75-6f3d59bba4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384904609 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3384904609
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.1847788117
Short name T699
Test name
Test status
Simulation time 352756767 ps
CPU time 4.24 seconds
Started Apr 18 02:25:38 PM PDT 24
Finished Apr 18 02:25:43 PM PDT 24
Peak memory 217524 kb
Host smart-8c195082-ffe4-44ac-babd-d4ea2d41f8e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847788117 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1847788117
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3035631640
Short name T194
Test name
Test status
Simulation time 114525873291 ps
CPU time 384.58 seconds
Started Apr 18 02:25:36 PM PDT 24
Finished Apr 18 02:32:01 PM PDT 24
Peak memory 218312 kb
Host smart-37bc2652-179e-48ca-9952-d05118720657
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035631640 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3035631640
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1796451797
Short name T771
Test name
Test status
Simulation time 26968317 ps
CPU time 1.22 seconds
Started Apr 18 02:25:42 PM PDT 24
Finished Apr 18 02:25:44 PM PDT 24
Peak memory 215344 kb
Host smart-7ddbcdb6-7187-44e3-9977-5d022dec9b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796451797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1796451797
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3833418481
Short name T552
Test name
Test status
Simulation time 20050011 ps
CPU time 1.04 seconds
Started Apr 18 02:25:46 PM PDT 24
Finished Apr 18 02:25:47 PM PDT 24
Peak memory 206696 kb
Host smart-a6c08e4e-74de-44e2-8bf2-29282659ed1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833418481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3833418481
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1872044159
Short name T317
Test name
Test status
Simulation time 37631500 ps
CPU time 0.86 seconds
Started Apr 18 02:25:41 PM PDT 24
Finished Apr 18 02:25:42 PM PDT 24
Peak memory 215400 kb
Host smart-fea0c62f-2e38-4f35-9f5e-0b0de4c93063
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872044159 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1872044159
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3454090193
Short name T695
Test name
Test status
Simulation time 197687578 ps
CPU time 1.06 seconds
Started Apr 18 02:25:45 PM PDT 24
Finished Apr 18 02:25:47 PM PDT 24
Peak memory 216336 kb
Host smart-9b5aedbe-a873-4f46-8fc1-627eb8d55393
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454090193 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3454090193
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.257412984
Short name T40
Test name
Test status
Simulation time 34407287 ps
CPU time 0.93 seconds
Started Apr 18 02:25:41 PM PDT 24
Finished Apr 18 02:25:42 PM PDT 24
Peak memory 219208 kb
Host smart-831b7579-b46e-4778-806e-295bee5b528e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257412984 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.257412984
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.4228085104
Short name T541
Test name
Test status
Simulation time 106843698 ps
CPU time 1.21 seconds
Started Apr 18 02:25:43 PM PDT 24
Finished Apr 18 02:25:44 PM PDT 24
Peak memory 216464 kb
Host smart-87c1a249-7942-44c8-ad6d-152ef1d9e2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228085104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.4228085104
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2400482563
Short name T683
Test name
Test status
Simulation time 22298574 ps
CPU time 1.08 seconds
Started Apr 18 02:25:41 PM PDT 24
Finished Apr 18 02:25:43 PM PDT 24
Peak memory 215328 kb
Host smart-b8c100c2-0e4c-44d2-8feb-016f14b14b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400482563 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2400482563
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2711995570
Short name T721
Test name
Test status
Simulation time 57434329 ps
CPU time 0.94 seconds
Started Apr 18 02:25:40 PM PDT 24
Finished Apr 18 02:25:42 PM PDT 24
Peak memory 215016 kb
Host smart-1a44f715-e9e2-47b6-8b4b-1adb84b1ca1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711995570 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2711995570
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.125889436
Short name T200
Test name
Test status
Simulation time 878578626 ps
CPU time 1.75 seconds
Started Apr 18 02:25:44 PM PDT 24
Finished Apr 18 02:25:47 PM PDT 24
Peak memory 214984 kb
Host smart-30fc6f09-1dc1-405f-ba9a-c60d5cd3fbff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125889436 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.125889436
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3442428690
Short name T609
Test name
Test status
Simulation time 19687674507 ps
CPU time 342.06 seconds
Started Apr 18 02:25:45 PM PDT 24
Finished Apr 18 02:31:27 PM PDT 24
Peak memory 218060 kb
Host smart-e4c8c56d-f742-4c1e-a5b9-e53db1cbe937
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442428690 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3442428690
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.472018564
Short name T27
Test name
Test status
Simulation time 93175076 ps
CPU time 1.34 seconds
Started Apr 18 02:24:38 PM PDT 24
Finished Apr 18 02:24:40 PM PDT 24
Peak memory 215384 kb
Host smart-4d76ad41-3621-4ef6-a426-7cae4e754bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472018564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.472018564
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.641863439
Short name T593
Test name
Test status
Simulation time 20388750 ps
CPU time 0.95 seconds
Started Apr 18 02:24:41 PM PDT 24
Finished Apr 18 02:24:42 PM PDT 24
Peak memory 205964 kb
Host smart-545f6233-e602-4fe7-a715-8f8f8043d796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641863439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.641863439
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1734574943
Short name T473
Test name
Test status
Simulation time 12844231 ps
CPU time 0.9 seconds
Started Apr 18 02:24:38 PM PDT 24
Finished Apr 18 02:24:40 PM PDT 24
Peak memory 215732 kb
Host smart-fc9e546f-e9d7-4d5e-89a4-03b01d5cf3a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734574943 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1734574943
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1627823628
Short name T57
Test name
Test status
Simulation time 27754745 ps
CPU time 1.08 seconds
Started Apr 18 02:24:31 PM PDT 24
Finished Apr 18 02:24:32 PM PDT 24
Peak memory 218732 kb
Host smart-27a24bae-3a65-42c6-b775-02e4d2bbb96d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627823628 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1627823628
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2800916596
Short name T311
Test name
Test status
Simulation time 20151489 ps
CPU time 1.03 seconds
Started Apr 18 02:24:37 PM PDT 24
Finished Apr 18 02:24:39 PM PDT 24
Peak memory 217388 kb
Host smart-3c5b3be0-b2ac-4f5e-8d6d-ac63906f6f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800916596 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2800916596
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1387278589
Short name T277
Test name
Test status
Simulation time 54837464 ps
CPU time 1.36 seconds
Started Apr 18 02:24:41 PM PDT 24
Finished Apr 18 02:24:43 PM PDT 24
Peak memory 217528 kb
Host smart-315d42e5-3eae-44db-bc8d-e20954d7e191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387278589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1387278589
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2840750724
Short name T393
Test name
Test status
Simulation time 25771496 ps
CPU time 1.11 seconds
Started Apr 18 02:24:39 PM PDT 24
Finished Apr 18 02:24:41 PM PDT 24
Peak memory 223804 kb
Host smart-21d7dd52-76cf-4f64-b675-15b7a6a553bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840750724 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2840750724
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1770559549
Short name T101
Test name
Test status
Simulation time 17555954 ps
CPU time 0.95 seconds
Started Apr 18 02:24:36 PM PDT 24
Finished Apr 18 02:24:38 PM PDT 24
Peak memory 206840 kb
Host smart-04a72250-d210-4ebf-8438-f10926ef3853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770559549 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1770559549
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.794364200
Short name T123
Test name
Test status
Simulation time 188059241 ps
CPU time 3.34 seconds
Started Apr 18 02:24:41 PM PDT 24
Finished Apr 18 02:24:45 PM PDT 24
Peak memory 234056 kb
Host smart-772271a4-dbd8-4d92-95d2-c704592bd819
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794364200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.794364200
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3460164411
Short name T745
Test name
Test status
Simulation time 33494149 ps
CPU time 0.9 seconds
Started Apr 18 02:24:36 PM PDT 24
Finished Apr 18 02:24:38 PM PDT 24
Peak memory 215032 kb
Host smart-2c311ecf-3f2c-4a25-8438-53d875a7614e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460164411 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3460164411
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.464024319
Short name T359
Test name
Test status
Simulation time 77996110 ps
CPU time 1.96 seconds
Started Apr 18 02:24:37 PM PDT 24
Finished Apr 18 02:24:40 PM PDT 24
Peak memory 216260 kb
Host smart-dee340bf-4cba-4ab4-8c85-b7612ccff1db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464024319 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.464024319
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.375663020
Short name T607
Test name
Test status
Simulation time 91568481057 ps
CPU time 1009.69 seconds
Started Apr 18 02:24:38 PM PDT 24
Finished Apr 18 02:41:28 PM PDT 24
Peak memory 220800 kb
Host smart-381d748b-5a5b-4f94-b029-b4f1593540a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375663020 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.375663020
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert_test.1255334708
Short name T716
Test name
Test status
Simulation time 14282604 ps
CPU time 0.9 seconds
Started Apr 18 02:25:48 PM PDT 24
Finished Apr 18 02:25:49 PM PDT 24
Peak memory 206700 kb
Host smart-6f4843c8-dc6f-4fa9-ae7f-f581e5d42fdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255334708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1255334708
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2241029011
Short name T585
Test name
Test status
Simulation time 18033209 ps
CPU time 0.87 seconds
Started Apr 18 02:25:45 PM PDT 24
Finished Apr 18 02:25:47 PM PDT 24
Peak memory 215236 kb
Host smart-e3dcf56e-aa3b-4689-8dc5-ffa0659a96dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241029011 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2241029011
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1829629249
Short name T329
Test name
Test status
Simulation time 35594226 ps
CPU time 0.91 seconds
Started Apr 18 02:25:44 PM PDT 24
Finished Apr 18 02:25:45 PM PDT 24
Peak memory 217496 kb
Host smart-13488b25-8f46-409b-a769-1ea6b5e256ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829629249 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1829629249
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.4085649974
Short name T156
Test name
Test status
Simulation time 18279489 ps
CPU time 1.06 seconds
Started Apr 18 02:25:48 PM PDT 24
Finished Apr 18 02:25:49 PM PDT 24
Peak memory 217952 kb
Host smart-ab3343e0-8d75-4faf-bb24-793789acb895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085649974 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.4085649974
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1510194594
Short name T349
Test name
Test status
Simulation time 43501249 ps
CPU time 1.41 seconds
Started Apr 18 02:25:45 PM PDT 24
Finished Apr 18 02:25:47 PM PDT 24
Peak memory 217580 kb
Host smart-e10c74c2-9482-4f57-a2ba-126b7244dd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510194594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1510194594
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2461208566
Short name T763
Test name
Test status
Simulation time 22648733 ps
CPU time 1.11 seconds
Started Apr 18 02:25:45 PM PDT 24
Finished Apr 18 02:25:46 PM PDT 24
Peak memory 215328 kb
Host smart-c008c4ab-fbce-41f1-8016-03d4e141a704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461208566 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2461208566
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2397179374
Short name T357
Test name
Test status
Simulation time 43403840 ps
CPU time 0.92 seconds
Started Apr 18 02:25:39 PM PDT 24
Finished Apr 18 02:25:40 PM PDT 24
Peak memory 215000 kb
Host smart-6ed6efed-54cc-4a49-a736-016c33c955a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397179374 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2397179374
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1134125506
Short name T196
Test name
Test status
Simulation time 835978003 ps
CPU time 4.63 seconds
Started Apr 18 02:25:40 PM PDT 24
Finished Apr 18 02:25:45 PM PDT 24
Peak memory 218972 kb
Host smart-bced5dc7-a005-4487-b039-47a69865ec7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134125506 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1134125506
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1192516703
Short name T185
Test name
Test status
Simulation time 143956637339 ps
CPU time 1705.1 seconds
Started Apr 18 02:25:42 PM PDT 24
Finished Apr 18 02:54:08 PM PDT 24
Peak memory 225276 kb
Host smart-06717170-fc9e-4437-bf2e-af874e70fbd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192516703 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1192516703
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.965756227
Short name T749
Test name
Test status
Simulation time 364194005 ps
CPU time 1.49 seconds
Started Apr 18 02:25:49 PM PDT 24
Finished Apr 18 02:25:51 PM PDT 24
Peak memory 215392 kb
Host smart-a57941ab-34b4-43b7-82f0-1918c35bdde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965756227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.965756227
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3078511225
Short name T788
Test name
Test status
Simulation time 26681750 ps
CPU time 1.21 seconds
Started Apr 18 02:25:45 PM PDT 24
Finished Apr 18 02:25:47 PM PDT 24
Peak memory 206536 kb
Host smart-a6ad4e30-7b02-4934-93b0-fe5fa485daf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078511225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3078511225
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2377335867
Short name T132
Test name
Test status
Simulation time 11813697 ps
CPU time 0.88 seconds
Started Apr 18 02:25:50 PM PDT 24
Finished Apr 18 02:25:52 PM PDT 24
Peak memory 215296 kb
Host smart-f9959421-43c1-4afa-9225-7c0c4431e453
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377335867 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2377335867
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.230919085
Short name T556
Test name
Test status
Simulation time 90517485 ps
CPU time 1.04 seconds
Started Apr 18 02:25:45 PM PDT 24
Finished Apr 18 02:25:46 PM PDT 24
Peak memory 217360 kb
Host smart-7b0e9b9c-0fc9-476a-84ed-9d191eb7b992
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230919085 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.230919085
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.297369944
Short name T37
Test name
Test status
Simulation time 21417967 ps
CPU time 1.11 seconds
Started Apr 18 02:25:46 PM PDT 24
Finished Apr 18 02:25:48 PM PDT 24
Peak memory 219112 kb
Host smart-132b6d24-aaba-4817-a41e-bebc90d55b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297369944 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.297369944
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2128991823
Short name T133
Test name
Test status
Simulation time 57934737 ps
CPU time 1.85 seconds
Started Apr 18 02:25:45 PM PDT 24
Finished Apr 18 02:25:47 PM PDT 24
Peak memory 217844 kb
Host smart-857ac375-753e-4c65-b41c-c2b72bccf024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128991823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2128991823
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.4119824528
Short name T106
Test name
Test status
Simulation time 22921346 ps
CPU time 0.97 seconds
Started Apr 18 02:25:47 PM PDT 24
Finished Apr 18 02:25:48 PM PDT 24
Peak memory 215496 kb
Host smart-453f463c-ece1-4662-a9cb-580983b27595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119824528 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.4119824528
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1541625512
Short name T597
Test name
Test status
Simulation time 24443850 ps
CPU time 0.96 seconds
Started Apr 18 02:25:49 PM PDT 24
Finished Apr 18 02:25:50 PM PDT 24
Peak memory 214952 kb
Host smart-8b6324f5-ec70-4a6e-badb-ac6da218b6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541625512 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1541625512
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.290319670
Short name T6
Test name
Test status
Simulation time 548975690 ps
CPU time 3.32 seconds
Started Apr 18 02:25:56 PM PDT 24
Finished Apr 18 02:26:00 PM PDT 24
Peak memory 216212 kb
Host smart-aec4df06-e520-4da2-82bf-1282f02d0746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290319670 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.290319670
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.4163264956
Short name T425
Test name
Test status
Simulation time 16674763339 ps
CPU time 371.4 seconds
Started Apr 18 02:25:56 PM PDT 24
Finished Apr 18 02:32:08 PM PDT 24
Peak memory 222572 kb
Host smart-1cddb668-bbb1-4bdf-b5bf-142be00d3be8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163264956 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.4163264956
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1388696300
Short name T249
Test name
Test status
Simulation time 55318798 ps
CPU time 1.17 seconds
Started Apr 18 02:25:51 PM PDT 24
Finished Apr 18 02:25:53 PM PDT 24
Peak memory 215392 kb
Host smart-d561be18-113b-4f82-82bb-2b4fbc0a2f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388696300 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1388696300
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3453634020
Short name T430
Test name
Test status
Simulation time 55279102 ps
CPU time 0.97 seconds
Started Apr 18 02:25:54 PM PDT 24
Finished Apr 18 02:25:56 PM PDT 24
Peak memory 205836 kb
Host smart-fd2abb53-6903-4cc3-a621-4415dd391365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453634020 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3453634020
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3946295027
Short name T171
Test name
Test status
Simulation time 10677208 ps
CPU time 0.89 seconds
Started Apr 18 02:25:47 PM PDT 24
Finished Apr 18 02:25:49 PM PDT 24
Peak memory 215560 kb
Host smart-ba14a569-9d35-4059-adc4-72c280d070bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946295027 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3946295027
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.4073285133
Short name T756
Test name
Test status
Simulation time 30902137 ps
CPU time 1.23 seconds
Started Apr 18 02:25:51 PM PDT 24
Finished Apr 18 02:25:53 PM PDT 24
Peak memory 216308 kb
Host smart-8137c1ec-eb13-43d0-b945-c2948004a856
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073285133 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.4073285133
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3484576869
Short name T818
Test name
Test status
Simulation time 96407868 ps
CPU time 1.04 seconds
Started Apr 18 02:25:48 PM PDT 24
Finished Apr 18 02:25:49 PM PDT 24
Peak memory 219112 kb
Host smart-b4491b61-27f8-4d30-8541-0d78a4a33352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484576869 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3484576869
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1732806608
Short name T832
Test name
Test status
Simulation time 155724917 ps
CPU time 1.21 seconds
Started Apr 18 02:25:45 PM PDT 24
Finished Apr 18 02:25:47 PM PDT 24
Peak memory 216484 kb
Host smart-be77e14d-b2ba-4fbb-8287-75c231fe2abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732806608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1732806608
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.475532432
Short name T18
Test name
Test status
Simulation time 46369264 ps
CPU time 0.85 seconds
Started Apr 18 02:25:47 PM PDT 24
Finished Apr 18 02:25:49 PM PDT 24
Peak memory 215244 kb
Host smart-b3108e26-0ab3-4870-869c-81ebc3ce954d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475532432 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.475532432
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.1715484589
Short name T591
Test name
Test status
Simulation time 54041944 ps
CPU time 0.9 seconds
Started Apr 18 02:25:46 PM PDT 24
Finished Apr 18 02:25:48 PM PDT 24
Peak memory 214968 kb
Host smart-793e1cfd-a168-48c2-852a-740ed378450c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715484589 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1715484589
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.670531713
Short name T435
Test name
Test status
Simulation time 234171996 ps
CPU time 4.95 seconds
Started Apr 18 02:25:47 PM PDT 24
Finished Apr 18 02:25:53 PM PDT 24
Peak memory 219084 kb
Host smart-f1df6428-4585-408f-9063-20506530dbdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670531713 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.670531713
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3014224089
Short name T182
Test name
Test status
Simulation time 74237626424 ps
CPU time 1152.85 seconds
Started Apr 18 02:25:48 PM PDT 24
Finished Apr 18 02:45:01 PM PDT 24
Peak memory 222828 kb
Host smart-41291813-a477-40d8-a301-37f83b389113
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014224089 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3014224089
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1310184753
Short name T427
Test name
Test status
Simulation time 72675562 ps
CPU time 1.05 seconds
Started Apr 18 02:25:51 PM PDT 24
Finished Apr 18 02:25:52 PM PDT 24
Peak memory 215504 kb
Host smart-70334d6c-09cb-4adc-a3f2-84b5aa855e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310184753 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1310184753
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1787039917
Short name T760
Test name
Test status
Simulation time 85327902 ps
CPU time 0.77 seconds
Started Apr 18 02:25:54 PM PDT 24
Finished Apr 18 02:25:56 PM PDT 24
Peak memory 205012 kb
Host smart-bf41fce4-2145-4b65-98d1-2078f0e1ae07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787039917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1787039917
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1264055634
Short name T62
Test name
Test status
Simulation time 19721135 ps
CPU time 0.87 seconds
Started Apr 18 02:25:51 PM PDT 24
Finished Apr 18 02:25:52 PM PDT 24
Peak memory 214692 kb
Host smart-be42d6a2-ebae-4d7b-b556-d2c57012e454
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264055634 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1264055634
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2570306784
Short name T175
Test name
Test status
Simulation time 66399364 ps
CPU time 1.01 seconds
Started Apr 18 02:25:55 PM PDT 24
Finished Apr 18 02:25:57 PM PDT 24
Peak memory 216544 kb
Host smart-35cd641b-7aeb-42ec-a207-f825982de5e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570306784 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2570306784
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2845261522
Short name T445
Test name
Test status
Simulation time 132089719 ps
CPU time 1.11 seconds
Started Apr 18 02:25:51 PM PDT 24
Finished Apr 18 02:25:52 PM PDT 24
Peak memory 232992 kb
Host smart-c07c0ab9-8e3e-4a3d-90c3-3ab9f71ef3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845261522 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2845261522
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2966151491
Short name T134
Test name
Test status
Simulation time 93967630 ps
CPU time 1.46 seconds
Started Apr 18 02:25:55 PM PDT 24
Finished Apr 18 02:25:57 PM PDT 24
Peak memory 217428 kb
Host smart-813849a7-4b3c-4404-b184-2292813ce5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966151491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2966151491
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_smoke.2009506228
Short name T652
Test name
Test status
Simulation time 19333762 ps
CPU time 1.02 seconds
Started Apr 18 02:25:50 PM PDT 24
Finished Apr 18 02:25:52 PM PDT 24
Peak memory 215020 kb
Host smart-b2e53be9-2aa6-4243-8d8d-57bfc390d269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009506228 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2009506228
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3337500219
Short name T297
Test name
Test status
Simulation time 321355630 ps
CPU time 3.77 seconds
Started Apr 18 02:25:54 PM PDT 24
Finished Apr 18 02:25:58 PM PDT 24
Peak memory 215036 kb
Host smart-c5edb7d6-9bc7-4ebb-818f-3bc2f4732df7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337500219 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3337500219
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3419916395
Short name T389
Test name
Test status
Simulation time 88491745982 ps
CPU time 1096.96 seconds
Started Apr 18 02:25:59 PM PDT 24
Finished Apr 18 02:44:17 PM PDT 24
Peak memory 222560 kb
Host smart-508f0e45-ea60-4dcb-b885-2dd71a3d446e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419916395 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3419916395
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1247719106
Short name T73
Test name
Test status
Simulation time 74083830 ps
CPU time 1.12 seconds
Started Apr 18 02:25:55 PM PDT 24
Finished Apr 18 02:25:57 PM PDT 24
Peak memory 215288 kb
Host smart-7adb7b70-25d8-49f6-995e-748a1d5cf9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247719106 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1247719106
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3501790034
Short name T399
Test name
Test status
Simulation time 55369076 ps
CPU time 0.92 seconds
Started Apr 18 02:25:51 PM PDT 24
Finished Apr 18 02:25:52 PM PDT 24
Peak memory 205848 kb
Host smart-5b02226e-64f7-49ed-b46d-9d58729669e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501790034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3501790034
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2344284668
Short name T839
Test name
Test status
Simulation time 10957319 ps
CPU time 0.88 seconds
Started Apr 18 02:26:00 PM PDT 24
Finished Apr 18 02:26:02 PM PDT 24
Peak memory 215556 kb
Host smart-607c29c1-6738-4c9c-bc55-6558ad9e9081
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344284668 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2344284668
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_err.1143517567
Short name T49
Test name
Test status
Simulation time 32682066 ps
CPU time 0.91 seconds
Started Apr 18 02:25:53 PM PDT 24
Finished Apr 18 02:25:54 PM PDT 24
Peak memory 218880 kb
Host smart-e8483ee0-56ac-4658-827e-819514c1762a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143517567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1143517567
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2558613953
Short name T513
Test name
Test status
Simulation time 85374163 ps
CPU time 1.66 seconds
Started Apr 18 02:25:51 PM PDT 24
Finished Apr 18 02:25:53 PM PDT 24
Peak memory 217680 kb
Host smart-9aedb8e5-64c7-4fc9-8411-aa7eec53948d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558613953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2558613953
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2396847344
Short name T539
Test name
Test status
Simulation time 41287559 ps
CPU time 0.88 seconds
Started Apr 18 02:25:55 PM PDT 24
Finished Apr 18 02:25:57 PM PDT 24
Peak memory 214960 kb
Host smart-ca6ce3f2-715c-420e-b7b2-0d83329f7a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396847344 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2396847344
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1032673600
Short name T296
Test name
Test status
Simulation time 18201622 ps
CPU time 1 seconds
Started Apr 18 02:25:51 PM PDT 24
Finished Apr 18 02:25:52 PM PDT 24
Peak memory 214984 kb
Host smart-601fd97e-586e-447f-ab86-cbbd21d92c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032673600 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1032673600
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3629962895
Short name T385
Test name
Test status
Simulation time 110683416 ps
CPU time 1.49 seconds
Started Apr 18 02:25:51 PM PDT 24
Finished Apr 18 02:25:53 PM PDT 24
Peak memory 216436 kb
Host smart-665d8450-258d-4a75-948c-ffda0ed55398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629962895 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3629962895
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.891167002
Short name T654
Test name
Test status
Simulation time 634342085202 ps
CPU time 2418.04 seconds
Started Apr 18 02:25:54 PM PDT 24
Finished Apr 18 03:06:12 PM PDT 24
Peak memory 231332 kb
Host smart-3eacc482-0e64-4bec-8660-338a9a3e931c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891167002 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.891167002
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3298951507
Short name T505
Test name
Test status
Simulation time 114238452 ps
CPU time 1.16 seconds
Started Apr 18 02:25:55 PM PDT 24
Finished Apr 18 02:25:57 PM PDT 24
Peak memory 215276 kb
Host smart-c8edfce1-7cc3-42b1-ab6b-7185f4c39d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298951507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3298951507
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3665648378
Short name T572
Test name
Test status
Simulation time 16327601 ps
CPU time 0.91 seconds
Started Apr 18 02:25:52 PM PDT 24
Finished Apr 18 02:25:54 PM PDT 24
Peak memory 206892 kb
Host smart-34fbf37e-08a2-4ebf-9f53-0e68e234451b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665648378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3665648378
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2893389760
Short name T676
Test name
Test status
Simulation time 14303139 ps
CPU time 0.93 seconds
Started Apr 18 02:25:56 PM PDT 24
Finished Apr 18 02:25:58 PM PDT 24
Peak memory 215284 kb
Host smart-dd6994de-a565-4052-8494-f718c9bc837b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893389760 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2893389760
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_err.3917135026
Short name T172
Test name
Test status
Simulation time 69705124 ps
CPU time 1.07 seconds
Started Apr 18 02:25:57 PM PDT 24
Finished Apr 18 02:25:59 PM PDT 24
Peak memory 218844 kb
Host smart-ea56e992-19a0-4e6f-a98e-9826cbe6dcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917135026 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3917135026
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.416568066
Short name T388
Test name
Test status
Simulation time 68173596 ps
CPU time 0.97 seconds
Started Apr 18 02:25:53 PM PDT 24
Finished Apr 18 02:25:55 PM PDT 24
Peak memory 216388 kb
Host smart-e34e7b76-7b59-4ca9-be30-66c9077b371a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416568066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.416568066
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.4224660169
Short name T785
Test name
Test status
Simulation time 22434630 ps
CPU time 1.18 seconds
Started Apr 18 02:25:52 PM PDT 24
Finished Apr 18 02:25:54 PM PDT 24
Peak memory 223744 kb
Host smart-12b0dfcf-00d3-4e53-be53-39f7029ec490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224660169 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.4224660169
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2846085632
Short name T805
Test name
Test status
Simulation time 55689754 ps
CPU time 0.9 seconds
Started Apr 18 02:25:54 PM PDT 24
Finished Apr 18 02:25:55 PM PDT 24
Peak memory 214940 kb
Host smart-b4b15a4e-cccd-4926-83c2-61a4e4548f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846085632 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2846085632
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.677646889
Short name T368
Test name
Test status
Simulation time 75837791 ps
CPU time 1.31 seconds
Started Apr 18 02:25:52 PM PDT 24
Finished Apr 18 02:25:54 PM PDT 24
Peak memory 215012 kb
Host smart-4b8f2369-7160-4fe6-a3f1-8bbccad481c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677646889 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.677646889
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.909217201
Short name T679
Test name
Test status
Simulation time 536035646856 ps
CPU time 915.7 seconds
Started Apr 18 02:25:53 PM PDT 24
Finished Apr 18 02:41:09 PM PDT 24
Peak memory 220624 kb
Host smart-d84b3cbd-1ecf-4282-9624-c70994866992
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909217201 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.909217201
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2242418847
Short name T253
Test name
Test status
Simulation time 26424661 ps
CPU time 1.29 seconds
Started Apr 18 02:26:00 PM PDT 24
Finished Apr 18 02:26:02 PM PDT 24
Peak memory 215368 kb
Host smart-8fcd6d7f-5ac5-45e6-81b7-5dab4ca82bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242418847 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2242418847
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1580859432
Short name T486
Test name
Test status
Simulation time 14420549 ps
CPU time 0.93 seconds
Started Apr 18 02:25:55 PM PDT 24
Finished Apr 18 02:25:57 PM PDT 24
Peak memory 206420 kb
Host smart-46491905-663e-4a49-813e-a0cf2b6132ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580859432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1580859432
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.710923166
Short name T176
Test name
Test status
Simulation time 18748413 ps
CPU time 0.85 seconds
Started Apr 18 02:25:54 PM PDT 24
Finished Apr 18 02:25:56 PM PDT 24
Peak memory 206940 kb
Host smart-d7bc3ebc-8fe8-4be1-9f40-873243dd08ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710923166 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.710923166
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1441275382
Short name T811
Test name
Test status
Simulation time 50697011 ps
CPU time 1.19 seconds
Started Apr 18 02:25:52 PM PDT 24
Finished Apr 18 02:25:54 PM PDT 24
Peak memory 216268 kb
Host smart-6b1ef1be-f739-4148-8cf2-a1d0a050a074
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441275382 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1441275382
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2038717625
Short name T69
Test name
Test status
Simulation time 75381052 ps
CPU time 1.07 seconds
Started Apr 18 02:25:54 PM PDT 24
Finished Apr 18 02:25:56 PM PDT 24
Peak memory 218956 kb
Host smart-82ee85de-5c14-4230-abf3-62db0e7d4758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038717625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2038717625
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2513716134
Short name T620
Test name
Test status
Simulation time 57333842 ps
CPU time 1.07 seconds
Started Apr 18 02:25:57 PM PDT 24
Finished Apr 18 02:25:59 PM PDT 24
Peak memory 216264 kb
Host smart-2ff5c103-458a-4431-8e5f-073957eb4c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513716134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2513716134
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3565890537
Short name T377
Test name
Test status
Simulation time 26160667 ps
CPU time 0.97 seconds
Started Apr 18 02:25:50 PM PDT 24
Finished Apr 18 02:25:51 PM PDT 24
Peak memory 215156 kb
Host smart-498c0a48-79ca-4197-bd71-e012cd9c3240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565890537 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3565890537
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3941179680
Short name T693
Test name
Test status
Simulation time 106993604 ps
CPU time 0.91 seconds
Started Apr 18 02:25:52 PM PDT 24
Finished Apr 18 02:25:54 PM PDT 24
Peak memory 215004 kb
Host smart-9306ffb1-bbe4-453a-8d39-84c5ffce2b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941179680 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3941179680
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1304753392
Short name T564
Test name
Test status
Simulation time 607280787 ps
CPU time 5.94 seconds
Started Apr 18 02:25:54 PM PDT 24
Finished Apr 18 02:26:00 PM PDT 24
Peak memory 216460 kb
Host smart-da125e1e-15dd-43c5-ae89-96029e6f7f66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304753392 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1304753392
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3021138618
Short name T650
Test name
Test status
Simulation time 286124984645 ps
CPU time 2038.16 seconds
Started Apr 18 02:25:52 PM PDT 24
Finished Apr 18 02:59:51 PM PDT 24
Peak memory 227864 kb
Host smart-406fcf68-74bc-48ac-8fd6-d4a5c2d3de43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021138618 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3021138618
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.4274506015
Short name T154
Test name
Test status
Simulation time 42430874 ps
CPU time 1.12 seconds
Started Apr 18 02:25:59 PM PDT 24
Finished Apr 18 02:26:01 PM PDT 24
Peak memory 215408 kb
Host smart-fd265779-39c5-495b-b11b-3189c4900f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274506015 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.4274506015
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3194355074
Short name T691
Test name
Test status
Simulation time 23026623 ps
CPU time 0.8 seconds
Started Apr 18 02:25:56 PM PDT 24
Finished Apr 18 02:25:58 PM PDT 24
Peak memory 205560 kb
Host smart-e89b062a-c14b-438f-81f6-ab9ae932edc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194355074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3194355074
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2224047928
Short name T546
Test name
Test status
Simulation time 14250410 ps
CPU time 0.92 seconds
Started Apr 18 02:25:58 PM PDT 24
Finished Apr 18 02:26:00 PM PDT 24
Peak memory 215636 kb
Host smart-0713c57b-8d0b-48f7-a186-2b651f90226a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224047928 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2224047928
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1701267969
Short name T726
Test name
Test status
Simulation time 81042603 ps
CPU time 1.06 seconds
Started Apr 18 02:25:59 PM PDT 24
Finished Apr 18 02:26:01 PM PDT 24
Peak memory 216152 kb
Host smart-bd373472-5351-4229-abdc-df4293fdbb11
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701267969 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1701267969
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3467048111
Short name T60
Test name
Test status
Simulation time 18939096 ps
CPU time 1.09 seconds
Started Apr 18 02:25:59 PM PDT 24
Finished Apr 18 02:26:01 PM PDT 24
Peak memory 217804 kb
Host smart-26e570eb-4e07-460d-a275-9497f1ca2dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467048111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3467048111
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3858759749
Short name T820
Test name
Test status
Simulation time 38651647 ps
CPU time 1.39 seconds
Started Apr 18 02:25:56 PM PDT 24
Finished Apr 18 02:25:59 PM PDT 24
Peak memory 219104 kb
Host smart-60f38c32-0aac-4b39-9029-113b60d0b405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858759749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3858759749
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2209041017
Short name T144
Test name
Test status
Simulation time 21247976 ps
CPU time 1.08 seconds
Started Apr 18 02:25:59 PM PDT 24
Finished Apr 18 02:26:01 PM PDT 24
Peak memory 215548 kb
Host smart-e836d837-40b2-40d1-9efa-de4cc978834e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209041017 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2209041017
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.11013821
Short name T456
Test name
Test status
Simulation time 19216303 ps
CPU time 1.06 seconds
Started Apr 18 02:25:58 PM PDT 24
Finished Apr 18 02:26:00 PM PDT 24
Peak memory 214940 kb
Host smart-cc0b0c69-ffa4-47c7-959a-58a75ef7aeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11013821 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.11013821
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.4186266191
Short name T268
Test name
Test status
Simulation time 357190120 ps
CPU time 4.13 seconds
Started Apr 18 02:25:57 PM PDT 24
Finished Apr 18 02:26:02 PM PDT 24
Peak memory 216436 kb
Host smart-3f98af9c-91b1-4ef9-a4e6-58c14fa061e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186266191 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.4186266191
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2630106594
Short name T438
Test name
Test status
Simulation time 35485757572 ps
CPU time 679.94 seconds
Started Apr 18 02:25:58 PM PDT 24
Finished Apr 18 02:37:19 PM PDT 24
Peak memory 220852 kb
Host smart-5028547a-0677-44c6-abfd-c4f251ce8b7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630106594 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2630106594
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.879055900
Short name T153
Test name
Test status
Simulation time 159204739 ps
CPU time 1.12 seconds
Started Apr 18 02:25:57 PM PDT 24
Finished Apr 18 02:25:59 PM PDT 24
Peak memory 215364 kb
Host smart-abb43a8e-b441-4fd9-99c0-b45ebd96ce24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879055900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.879055900
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1522568773
Short name T370
Test name
Test status
Simulation time 39066137 ps
CPU time 0.91 seconds
Started Apr 18 02:25:58 PM PDT 24
Finished Apr 18 02:26:00 PM PDT 24
Peak memory 206452 kb
Host smart-0935f5f6-673f-490d-99d1-f379c916cd74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522568773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1522568773
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2309898434
Short name T173
Test name
Test status
Simulation time 11513484 ps
CPU time 0.89 seconds
Started Apr 18 02:25:57 PM PDT 24
Finished Apr 18 02:25:59 PM PDT 24
Peak memory 215260 kb
Host smart-e58f1b51-c3b1-4ff3-89ce-a04f1a0df0de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309898434 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2309898434
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3531423807
Short name T545
Test name
Test status
Simulation time 55752481 ps
CPU time 1.09 seconds
Started Apr 18 02:25:58 PM PDT 24
Finished Apr 18 02:26:00 PM PDT 24
Peak memory 216072 kb
Host smart-48c8c760-0aa4-494b-bb5c-7be424e67893
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531423807 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3531423807
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_genbits.1159627827
Short name T136
Test name
Test status
Simulation time 39908460 ps
CPU time 1.6 seconds
Started Apr 18 02:25:57 PM PDT 24
Finished Apr 18 02:26:00 PM PDT 24
Peak memory 217444 kb
Host smart-39d93490-951b-460e-b2d8-9a1c20d5d861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159627827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1159627827
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.4225324390
Short name T467
Test name
Test status
Simulation time 34309529 ps
CPU time 0.95 seconds
Started Apr 18 02:25:58 PM PDT 24
Finished Apr 18 02:26:00 PM PDT 24
Peak memory 215128 kb
Host smart-a4e58b04-b5bd-4017-87ca-06679801e0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225324390 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.4225324390
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1342262026
Short name T324
Test name
Test status
Simulation time 23547528 ps
CPU time 1.04 seconds
Started Apr 18 02:26:08 PM PDT 24
Finished Apr 18 02:26:09 PM PDT 24
Peak memory 214960 kb
Host smart-65bca088-5303-4997-b254-b60ec80950ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342262026 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1342262026
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3296421194
Short name T418
Test name
Test status
Simulation time 497674290 ps
CPU time 5.22 seconds
Started Apr 18 02:25:57 PM PDT 24
Finished Apr 18 02:26:03 PM PDT 24
Peak memory 216116 kb
Host smart-c05e451f-ea05-44f1-bebb-73fa5231706e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296421194 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3296421194
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3059901691
Short name T192
Test name
Test status
Simulation time 8756296538 ps
CPU time 154.72 seconds
Started Apr 18 02:25:59 PM PDT 24
Finished Apr 18 02:28:35 PM PDT 24
Peak memory 217896 kb
Host smart-82e39b76-e869-461d-8f09-1ed66b26e6c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059901691 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3059901691
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.3349395350
Short name T575
Test name
Test status
Simulation time 25705347 ps
CPU time 1.16 seconds
Started Apr 18 02:25:58 PM PDT 24
Finished Apr 18 02:26:00 PM PDT 24
Peak memory 215372 kb
Host smart-d19e4ce6-32db-4326-a04b-269719b9a837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349395350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3349395350
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3723417310
Short name T836
Test name
Test status
Simulation time 14471826 ps
CPU time 0.98 seconds
Started Apr 18 02:26:08 PM PDT 24
Finished Apr 18 02:26:09 PM PDT 24
Peak memory 205836 kb
Host smart-9a1a218e-372e-417e-9086-a93969fbe709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723417310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3723417310
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3474827435
Short name T680
Test name
Test status
Simulation time 39156013 ps
CPU time 0.87 seconds
Started Apr 18 02:25:58 PM PDT 24
Finished Apr 18 02:26:00 PM PDT 24
Peak memory 215412 kb
Host smart-5723876c-1ca8-4b4e-baa8-281dc2a92e85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474827435 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3474827435
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.407307622
Short name T56
Test name
Test status
Simulation time 35084265 ps
CPU time 1.25 seconds
Started Apr 18 02:26:00 PM PDT 24
Finished Apr 18 02:26:02 PM PDT 24
Peak memory 216156 kb
Host smart-3f968bd8-6a26-4e07-93d2-586ca22a038e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407307622 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.407307622
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2501383505
Short name T86
Test name
Test status
Simulation time 39193313 ps
CPU time 0.83 seconds
Started Apr 18 02:25:58 PM PDT 24
Finished Apr 18 02:26:00 PM PDT 24
Peak memory 217600 kb
Host smart-11b259ec-e331-4d8d-b242-75cdba7b0e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501383505 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2501383505
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3950099469
Short name T826
Test name
Test status
Simulation time 92343271 ps
CPU time 1.17 seconds
Started Apr 18 02:25:59 PM PDT 24
Finished Apr 18 02:26:01 PM PDT 24
Peak memory 216332 kb
Host smart-b7bf7564-0f6f-4a1a-8922-e74feba3f911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950099469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3950099469
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1238528308
Short name T148
Test name
Test status
Simulation time 29590847 ps
CPU time 0.88 seconds
Started Apr 18 02:25:58 PM PDT 24
Finished Apr 18 02:26:00 PM PDT 24
Peak memory 215336 kb
Host smart-40b0f1d2-9360-45cd-812f-a02c04b28fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238528308 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1238528308
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3167082068
Short name T469
Test name
Test status
Simulation time 26528500 ps
CPU time 0.96 seconds
Started Apr 18 02:25:58 PM PDT 24
Finished Apr 18 02:26:00 PM PDT 24
Peak memory 215000 kb
Host smart-4fc7ebfb-8f4d-40e4-bae5-b8e52cddcb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167082068 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3167082068
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1406616752
Short name T835
Test name
Test status
Simulation time 1312625929 ps
CPU time 4.96 seconds
Started Apr 18 02:25:57 PM PDT 24
Finished Apr 18 02:26:03 PM PDT 24
Peak memory 216364 kb
Host smart-0c2943cb-019a-43aa-b164-b3460e941086
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406616752 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1406616752
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1072916058
Short name T191
Test name
Test status
Simulation time 265250405272 ps
CPU time 1293.9 seconds
Started Apr 18 02:25:56 PM PDT 24
Finished Apr 18 02:47:32 PM PDT 24
Peak memory 223452 kb
Host smart-e1e7e111-f5cb-487c-9bd5-84d148e3021e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072916058 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1072916058
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3238460359
Short name T769
Test name
Test status
Simulation time 42374888 ps
CPU time 1.12 seconds
Started Apr 18 02:24:33 PM PDT 24
Finished Apr 18 02:24:35 PM PDT 24
Peak memory 215236 kb
Host smart-7d196e0e-6afa-4daa-b78d-b453e5d87dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238460359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3238460359
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2810333501
Short name T305
Test name
Test status
Simulation time 117069623 ps
CPU time 0.78 seconds
Started Apr 18 02:24:33 PM PDT 24
Finished Apr 18 02:24:35 PM PDT 24
Peak memory 205084 kb
Host smart-00b88fd7-1eaa-49fd-93b9-63c757d4718b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810333501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2810333501
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1735613182
Short name T78
Test name
Test status
Simulation time 42301826 ps
CPU time 0.88 seconds
Started Apr 18 02:24:35 PM PDT 24
Finished Apr 18 02:24:37 PM PDT 24
Peak memory 215636 kb
Host smart-0a3d7b9f-7bae-495e-8385-c0e28a6599db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735613182 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1735613182
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.846876065
Short name T166
Test name
Test status
Simulation time 22824227 ps
CPU time 1.08 seconds
Started Apr 18 02:24:37 PM PDT 24
Finished Apr 18 02:24:39 PM PDT 24
Peak memory 216236 kb
Host smart-df0844db-a56f-43cf-9131-ed82e0317a55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846876065 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.846876065
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3550986246
Short name T468
Test name
Test status
Simulation time 21258002 ps
CPU time 0.99 seconds
Started Apr 18 02:24:33 PM PDT 24
Finished Apr 18 02:24:35 PM PDT 24
Peak memory 217460 kb
Host smart-5eadf0fa-6019-405c-a376-713726cfa3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550986246 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3550986246
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3212391648
Short name T610
Test name
Test status
Simulation time 68666021 ps
CPU time 1.36 seconds
Started Apr 18 02:24:33 PM PDT 24
Finished Apr 18 02:24:35 PM PDT 24
Peak memory 217464 kb
Host smart-6a4a0c59-7482-4383-bc17-ea68c8efe8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212391648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3212391648
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2618820897
Short name T295
Test name
Test status
Simulation time 19926570 ps
CPU time 1.08 seconds
Started Apr 18 02:24:34 PM PDT 24
Finished Apr 18 02:24:36 PM PDT 24
Peak memory 215480 kb
Host smart-03697ebf-fd1f-4218-a56b-8115f3df986f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618820897 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2618820897
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3305426962
Short name T102
Test name
Test status
Simulation time 29020110 ps
CPU time 1.03 seconds
Started Apr 18 02:24:35 PM PDT 24
Finished Apr 18 02:24:37 PM PDT 24
Peak memory 206824 kb
Host smart-71435fe0-0ab9-468e-992d-39aabeefa5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305426962 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3305426962
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2054215014
Short name T602
Test name
Test status
Simulation time 18722042 ps
CPU time 0.98 seconds
Started Apr 18 02:24:35 PM PDT 24
Finished Apr 18 02:24:37 PM PDT 24
Peak memory 214928 kb
Host smart-1270b0f6-0f31-45b4-a33d-81217519862f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054215014 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2054215014
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.655255159
Short name T149
Test name
Test status
Simulation time 181066141 ps
CPU time 3.88 seconds
Started Apr 18 02:24:39 PM PDT 24
Finished Apr 18 02:24:44 PM PDT 24
Peak memory 217528 kb
Host smart-e8b75d67-9392-4eca-8b72-23870830fbf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655255159 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.655255159
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.113829146
Short name T384
Test name
Test status
Simulation time 72527305348 ps
CPU time 432.27 seconds
Started Apr 18 02:24:39 PM PDT 24
Finished Apr 18 02:31:52 PM PDT 24
Peak memory 217660 kb
Host smart-cd080623-b2d9-43e9-9ccb-c40ed4984f92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113829146 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.113829146
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.3965025451
Short name T14
Test name
Test status
Simulation time 71749955 ps
CPU time 1.2 seconds
Started Apr 18 02:25:58 PM PDT 24
Finished Apr 18 02:26:01 PM PDT 24
Peak memory 223816 kb
Host smart-2b4dc9ce-6955-4bff-afd2-9cd84948b2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965025451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3965025451
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1330280399
Short name T447
Test name
Test status
Simulation time 443243627 ps
CPU time 3.73 seconds
Started Apr 18 02:25:57 PM PDT 24
Finished Apr 18 02:26:02 PM PDT 24
Peak memory 216752 kb
Host smart-9d527191-a86f-4bb5-b2a9-b6acd068e158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330280399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1330280399
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.793833568
Short name T621
Test name
Test status
Simulation time 18712348 ps
CPU time 0.99 seconds
Started Apr 18 02:25:56 PM PDT 24
Finished Apr 18 02:25:58 PM PDT 24
Peak memory 218028 kb
Host smart-2b4aaa40-636f-42fa-a178-ad97dda83c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793833568 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.793833568
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3331639233
Short name T778
Test name
Test status
Simulation time 252957406 ps
CPU time 1.36 seconds
Started Apr 18 02:26:00 PM PDT 24
Finished Apr 18 02:26:02 PM PDT 24
Peak memory 218860 kb
Host smart-aa67e1dc-1e12-4866-8be3-7941a858fe39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331639233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3331639233
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.63168193
Short name T574
Test name
Test status
Simulation time 21136473 ps
CPU time 0.86 seconds
Started Apr 18 02:25:56 PM PDT 24
Finished Apr 18 02:25:57 PM PDT 24
Peak memory 217516 kb
Host smart-3d1e7a98-303a-4746-93c0-3353571a61f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63168193 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.63168193
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1766198630
Short name T730
Test name
Test status
Simulation time 48985667 ps
CPU time 1.22 seconds
Started Apr 18 02:25:59 PM PDT 24
Finished Apr 18 02:26:01 PM PDT 24
Peak memory 216452 kb
Host smart-ed205a77-ee47-43cb-a742-022a86dbd25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766198630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1766198630
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.2258171652
Short name T744
Test name
Test status
Simulation time 23748457 ps
CPU time 0.97 seconds
Started Apr 18 02:25:56 PM PDT 24
Finished Apr 18 02:25:58 PM PDT 24
Peak memory 217776 kb
Host smart-d4b02783-ad8f-48ca-817b-3c7661840895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258171652 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2258171652
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.855011607
Short name T828
Test name
Test status
Simulation time 46856246 ps
CPU time 1.46 seconds
Started Apr 18 02:25:58 PM PDT 24
Finished Apr 18 02:26:01 PM PDT 24
Peak memory 217780 kb
Host smart-b4c3a9b0-ff5b-430e-8ae2-97030be0baea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855011607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.855011607
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.1839890003
Short name T8
Test name
Test status
Simulation time 33026130 ps
CPU time 1.02 seconds
Started Apr 18 02:25:57 PM PDT 24
Finished Apr 18 02:25:59 PM PDT 24
Peak memory 219924 kb
Host smart-0e8316af-903b-4f51-8475-a51be67d7577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839890003 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1839890003
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1626696129
Short name T565
Test name
Test status
Simulation time 96594072 ps
CPU time 1.22 seconds
Started Apr 18 02:25:58 PM PDT 24
Finished Apr 18 02:26:00 PM PDT 24
Peak memory 217940 kb
Host smart-7b7f83af-c701-4f7d-8f59-2514a96be5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626696129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1626696129
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.4242091927
Short name T542
Test name
Test status
Simulation time 22557445 ps
CPU time 0.89 seconds
Started Apr 18 02:25:57 PM PDT 24
Finished Apr 18 02:25:59 PM PDT 24
Peak memory 217640 kb
Host smart-14231bd2-c6b7-470c-89e9-6829da2d3bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242091927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.4242091927
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3670430356
Short name T326
Test name
Test status
Simulation time 80322000 ps
CPU time 1.12 seconds
Started Apr 18 02:25:55 PM PDT 24
Finished Apr 18 02:25:57 PM PDT 24
Peak memory 217808 kb
Host smart-3fe3e9bc-3ccd-4ba2-9051-9885c463733c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670430356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3670430356
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.3816403546
Short name T33
Test name
Test status
Simulation time 21450325 ps
CPU time 1.25 seconds
Started Apr 18 02:26:02 PM PDT 24
Finished Apr 18 02:26:05 PM PDT 24
Peak memory 229460 kb
Host smart-7e2a66e7-2bc5-4c91-be3d-d8c40bae8057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816403546 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3816403546
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2423442476
Short name T809
Test name
Test status
Simulation time 55878146 ps
CPU time 1.51 seconds
Started Apr 18 02:26:04 PM PDT 24
Finished Apr 18 02:26:06 PM PDT 24
Peak memory 217604 kb
Host smart-65b4f55b-7507-4a57-846c-994252b966ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423442476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2423442476
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.771920743
Short name T41
Test name
Test status
Simulation time 21153147 ps
CPU time 1.09 seconds
Started Apr 18 02:26:10 PM PDT 24
Finished Apr 18 02:26:13 PM PDT 24
Peak memory 219292 kb
Host smart-3c0b018a-41a3-4719-beba-343fe86a6ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771920743 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.771920743
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2551063706
Short name T669
Test name
Test status
Simulation time 48504792 ps
CPU time 1.23 seconds
Started Apr 18 02:26:03 PM PDT 24
Finished Apr 18 02:26:05 PM PDT 24
Peak memory 216504 kb
Host smart-34db4e96-fabf-4199-a7dd-f7e04ee29356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551063706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2551063706
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2810611725
Short name T508
Test name
Test status
Simulation time 74218954 ps
CPU time 1.07 seconds
Started Apr 18 02:26:02 PM PDT 24
Finished Apr 18 02:26:05 PM PDT 24
Peak memory 230964 kb
Host smart-6f883463-1375-493e-827b-865ba2ac384a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810611725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2810611725
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2356915666
Short name T405
Test name
Test status
Simulation time 62768740 ps
CPU time 2.11 seconds
Started Apr 18 02:26:04 PM PDT 24
Finished Apr 18 02:26:07 PM PDT 24
Peak memory 217688 kb
Host smart-cd991c79-e4b7-42ef-9527-e8f26e0b14b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356915666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2356915666
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.3634567412
Short name T656
Test name
Test status
Simulation time 31565872 ps
CPU time 0.88 seconds
Started Apr 18 02:26:00 PM PDT 24
Finished Apr 18 02:26:02 PM PDT 24
Peak memory 217568 kb
Host smart-23179136-ad39-4e0d-b1ac-386f8aec6aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634567412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3634567412
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/6.edn_alert.1216094169
Short name T424
Test name
Test status
Simulation time 71473371 ps
CPU time 1.18 seconds
Started Apr 18 02:24:37 PM PDT 24
Finished Apr 18 02:24:39 PM PDT 24
Peak memory 214972 kb
Host smart-65708fa4-3e60-4b0d-815e-a6508beeebd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216094169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1216094169
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.372541611
Short name T403
Test name
Test status
Simulation time 69637303 ps
CPU time 0.87 seconds
Started Apr 18 02:24:37 PM PDT 24
Finished Apr 18 02:24:38 PM PDT 24
Peak memory 206764 kb
Host smart-5be5e168-5722-484a-9a82-08fefd3346ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372541611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.372541611
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3777605481
Short name T89
Test name
Test status
Simulation time 13337524 ps
CPU time 0.83 seconds
Started Apr 18 02:24:32 PM PDT 24
Finished Apr 18 02:24:33 PM PDT 24
Peak memory 215728 kb
Host smart-1a9a04be-b3a4-42b4-a060-ab6d4c877fac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777605481 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3777605481
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2232118731
Short name T244
Test name
Test status
Simulation time 63299978 ps
CPU time 1.15 seconds
Started Apr 18 02:24:33 PM PDT 24
Finished Apr 18 02:24:35 PM PDT 24
Peak memory 217604 kb
Host smart-36c6ee5b-30fe-4ce8-bdde-e581fead715d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232118731 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2232118731
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.525910387
Short name T789
Test name
Test status
Simulation time 22800965 ps
CPU time 0.92 seconds
Started Apr 18 02:24:35 PM PDT 24
Finished Apr 18 02:24:37 PM PDT 24
Peak memory 218008 kb
Host smart-a4762c83-4cb9-46a5-b295-2d41a97345be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525910387 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.525910387
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.782195738
Short name T278
Test name
Test status
Simulation time 86511223 ps
CPU time 3.22 seconds
Started Apr 18 02:24:38 PM PDT 24
Finished Apr 18 02:24:43 PM PDT 24
Peak memory 219208 kb
Host smart-41662789-de5a-4568-b496-ce2f330d8454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782195738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.782195738
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3774843907
Short name T697
Test name
Test status
Simulation time 22509464 ps
CPU time 1.08 seconds
Started Apr 18 02:24:33 PM PDT 24
Finished Apr 18 02:24:35 PM PDT 24
Peak memory 215296 kb
Host smart-20e6b26a-8d32-4db8-99f6-5027de446f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774843907 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3774843907
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1839343091
Short name T614
Test name
Test status
Simulation time 46419999 ps
CPU time 0.94 seconds
Started Apr 18 02:24:34 PM PDT 24
Finished Apr 18 02:24:36 PM PDT 24
Peak memory 206724 kb
Host smart-f791f883-5e0e-4d6a-bbba-1ff71cc00874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839343091 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1839343091
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.145626794
Short name T375
Test name
Test status
Simulation time 24732318 ps
CPU time 0.93 seconds
Started Apr 18 02:24:37 PM PDT 24
Finished Apr 18 02:24:38 PM PDT 24
Peak memory 214944 kb
Host smart-8091ed12-2bf0-4672-b96b-e1382c8f9767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145626794 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.145626794
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2594831309
Short name T819
Test name
Test status
Simulation time 169679581 ps
CPU time 3.98 seconds
Started Apr 18 02:24:38 PM PDT 24
Finished Apr 18 02:24:43 PM PDT 24
Peak memory 219216 kb
Host smart-c88ad29a-fd30-4f69-a10c-726b49cb04b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594831309 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2594831309
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.735620721
Short name T189
Test name
Test status
Simulation time 39149868873 ps
CPU time 222.44 seconds
Started Apr 18 02:24:39 PM PDT 24
Finished Apr 18 02:28:22 PM PDT 24
Peak memory 223124 kb
Host smart-19380686-040d-4a05-853b-d6ef6b2e7199
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735620721 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.735620721
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.1892944423
Short name T48
Test name
Test status
Simulation time 20944611 ps
CPU time 1.13 seconds
Started Apr 18 02:26:04 PM PDT 24
Finished Apr 18 02:26:06 PM PDT 24
Peak memory 219084 kb
Host smart-f61a7400-3792-4400-a562-2e9ec217f4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892944423 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1892944423
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3612745229
Short name T536
Test name
Test status
Simulation time 38058990 ps
CPU time 1.37 seconds
Started Apr 18 02:26:01 PM PDT 24
Finished Apr 18 02:26:03 PM PDT 24
Peak memory 217636 kb
Host smart-e49f226b-cc4d-44fc-bfb8-30e70812d020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612745229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3612745229
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.124834754
Short name T85
Test name
Test status
Simulation time 26196100 ps
CPU time 0.95 seconds
Started Apr 18 02:26:01 PM PDT 24
Finished Apr 18 02:26:02 PM PDT 24
Peak memory 217888 kb
Host smart-a220362b-70fd-442c-8975-e97f9e39a311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124834754 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.124834754
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2447790938
Short name T274
Test name
Test status
Simulation time 22716987 ps
CPU time 1.23 seconds
Started Apr 18 02:26:01 PM PDT 24
Finished Apr 18 02:26:03 PM PDT 24
Peak memory 217788 kb
Host smart-26fae072-a6a5-4aec-bed9-407e003b2cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447790938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2447790938
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.3769956889
Short name T29
Test name
Test status
Simulation time 20463056 ps
CPU time 1.08 seconds
Started Apr 18 02:26:09 PM PDT 24
Finished Apr 18 02:26:11 PM PDT 24
Peak memory 218852 kb
Host smart-6f7f6856-6562-4303-a3e1-d2ec43d730ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769956889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3769956889
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2924334431
Short name T497
Test name
Test status
Simulation time 74294359 ps
CPU time 1.14 seconds
Started Apr 18 02:26:00 PM PDT 24
Finished Apr 18 02:26:02 PM PDT 24
Peak memory 217904 kb
Host smart-e482393e-a7ba-4615-8d3c-7d46ba336686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924334431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2924334431
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.3971918778
Short name T79
Test name
Test status
Simulation time 29876780 ps
CPU time 0.85 seconds
Started Apr 18 02:26:00 PM PDT 24
Finished Apr 18 02:26:02 PM PDT 24
Peak memory 217612 kb
Host smart-e063b63d-bf71-47fc-9692-74b4187cacaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971918778 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3971918778
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2985208842
Short name T261
Test name
Test status
Simulation time 53093557 ps
CPU time 1.34 seconds
Started Apr 18 02:26:08 PM PDT 24
Finished Apr 18 02:26:10 PM PDT 24
Peak memory 217792 kb
Host smart-79d9d638-a778-4f62-884c-16990d3def04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985208842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2985208842
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.1554864609
Short name T762
Test name
Test status
Simulation time 30156156 ps
CPU time 0.88 seconds
Started Apr 18 02:26:01 PM PDT 24
Finished Apr 18 02:26:02 PM PDT 24
Peak memory 217712 kb
Host smart-4e1043c7-fb3e-471e-8e38-d983d506fd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554864609 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1554864609
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.98233063
Short name T262
Test name
Test status
Simulation time 32037487 ps
CPU time 1.46 seconds
Started Apr 18 02:26:07 PM PDT 24
Finished Apr 18 02:26:09 PM PDT 24
Peak memory 217504 kb
Host smart-40379253-cf6f-49d1-abbb-5f0321020efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98233063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.98233063
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.1127510080
Short name T15
Test name
Test status
Simulation time 31104369 ps
CPU time 0.95 seconds
Started Apr 18 02:26:10 PM PDT 24
Finished Apr 18 02:26:12 PM PDT 24
Peak memory 222536 kb
Host smart-04e3121d-1d70-4b55-873f-b1f16dc5bf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127510080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1127510080
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3352003484
Short name T363
Test name
Test status
Simulation time 19142836 ps
CPU time 1.01 seconds
Started Apr 18 02:26:01 PM PDT 24
Finished Apr 18 02:26:03 PM PDT 24
Peak memory 216524 kb
Host smart-5d1ff9c8-706a-49a3-9483-2c48df25e03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352003484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3352003484
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.1144798839
Short name T54
Test name
Test status
Simulation time 50797120 ps
CPU time 1 seconds
Started Apr 18 02:26:10 PM PDT 24
Finished Apr 18 02:26:11 PM PDT 24
Peak memory 229304 kb
Host smart-e274039c-f0db-4137-9c52-43c6ab3b49b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144798839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1144798839
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1715237827
Short name T752
Test name
Test status
Simulation time 51127798 ps
CPU time 1.22 seconds
Started Apr 18 02:26:07 PM PDT 24
Finished Apr 18 02:26:08 PM PDT 24
Peak memory 217516 kb
Host smart-2d88613e-00de-47b2-b526-44db97fd4fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715237827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1715237827
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.2142979256
Short name T32
Test name
Test status
Simulation time 34176851 ps
CPU time 1.12 seconds
Started Apr 18 02:26:02 PM PDT 24
Finished Apr 18 02:26:05 PM PDT 24
Peak memory 216396 kb
Host smart-cbd65d6e-221a-4a1f-a809-33cffe8801ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142979256 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2142979256
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2949615018
Short name T783
Test name
Test status
Simulation time 81903344 ps
CPU time 1.16 seconds
Started Apr 18 02:26:02 PM PDT 24
Finished Apr 18 02:26:04 PM PDT 24
Peak memory 216388 kb
Host smart-66bcb7ec-9f09-4c22-9015-b80a45e97f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949615018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2949615018
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.3667546812
Short name T813
Test name
Test status
Simulation time 44740053 ps
CPU time 1.05 seconds
Started Apr 18 02:26:03 PM PDT 24
Finished Apr 18 02:26:05 PM PDT 24
Peak memory 217676 kb
Host smart-b4c1da11-d99a-4da6-8851-6ddc0af96123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667546812 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3667546812
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1425962214
Short name T494
Test name
Test status
Simulation time 182638217 ps
CPU time 1.64 seconds
Started Apr 18 02:26:03 PM PDT 24
Finished Apr 18 02:26:06 PM PDT 24
Peak memory 218616 kb
Host smart-42ad45ce-6fec-474a-9a94-060a6c7f0922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425962214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1425962214
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.1581011865
Short name T35
Test name
Test status
Simulation time 154229851 ps
CPU time 1.2 seconds
Started Apr 18 02:26:07 PM PDT 24
Finished Apr 18 02:26:09 PM PDT 24
Peak memory 229372 kb
Host smart-fecb030a-0456-4c23-bff3-b4ad2ca99d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581011865 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1581011865
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2726427876
Short name T748
Test name
Test status
Simulation time 46911660 ps
CPU time 1.22 seconds
Started Apr 18 02:26:04 PM PDT 24
Finished Apr 18 02:26:05 PM PDT 24
Peak memory 218920 kb
Host smart-3c7d7c15-5899-4cf1-a603-a871af4c7cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726427876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2726427876
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3579196517
Short name T23
Test name
Test status
Simulation time 97235280 ps
CPU time 1.27 seconds
Started Apr 18 02:24:38 PM PDT 24
Finished Apr 18 02:24:41 PM PDT 24
Peak memory 215372 kb
Host smart-831fc0e5-408b-447a-91bc-71dc5e675e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579196517 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3579196517
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2605254124
Short name T519
Test name
Test status
Simulation time 29962550 ps
CPU time 0.85 seconds
Started Apr 18 02:24:36 PM PDT 24
Finished Apr 18 02:24:38 PM PDT 24
Peak memory 205868 kb
Host smart-4827203d-8cb7-44c0-89ea-8eae447b984d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605254124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2605254124
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.421747502
Short name T533
Test name
Test status
Simulation time 28658750 ps
CPU time 0.79 seconds
Started Apr 18 02:24:40 PM PDT 24
Finished Apr 18 02:24:41 PM PDT 24
Peak memory 215120 kb
Host smart-55c1a3ce-3cdb-4c74-927a-9ecf6f24b2a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421747502 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.421747502
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_err.640956248
Short name T812
Test name
Test status
Simulation time 20291430 ps
CPU time 0.99 seconds
Started Apr 18 02:24:39 PM PDT 24
Finished Apr 18 02:24:41 PM PDT 24
Peak memory 217844 kb
Host smart-f704b473-c5e9-43b9-ac88-513f8dfadac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640956248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.640956248
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.353147351
Short name T543
Test name
Test status
Simulation time 76200829 ps
CPU time 1.02 seconds
Started Apr 18 02:24:34 PM PDT 24
Finished Apr 18 02:24:36 PM PDT 24
Peak memory 216344 kb
Host smart-a4c0bd8d-ccc5-4eeb-bf54-043632ecac61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353147351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.353147351
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.244213393
Short name T830
Test name
Test status
Simulation time 22563132 ps
CPU time 1.17 seconds
Started Apr 18 02:24:37 PM PDT 24
Finished Apr 18 02:24:39 PM PDT 24
Peak memory 223776 kb
Host smart-752480e7-36c6-4c20-a944-c2dbd125a58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244213393 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.244213393
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_smoke.3764533442
Short name T613
Test name
Test status
Simulation time 101338879 ps
CPU time 0.84 seconds
Started Apr 18 02:24:38 PM PDT 24
Finished Apr 18 02:24:40 PM PDT 24
Peak memory 206800 kb
Host smart-7a000caf-99fb-4df7-9063-b32c7273d088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764533442 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3764533442
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3052900750
Short name T478
Test name
Test status
Simulation time 803123763 ps
CPU time 4.35 seconds
Started Apr 18 02:24:50 PM PDT 24
Finished Apr 18 02:24:54 PM PDT 24
Peak memory 216264 kb
Host smart-af1adc22-720e-4f09-be66-f6cb0f4c85bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052900750 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3052900750
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2948783836
Short name T186
Test name
Test status
Simulation time 4447123469 ps
CPU time 97.82 seconds
Started Apr 18 02:24:38 PM PDT 24
Finished Apr 18 02:26:17 PM PDT 24
Peak memory 217576 kb
Host smart-05e444be-61dc-4ed3-8439-6596c205a89d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948783836 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2948783836
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.238899547
Short name T351
Test name
Test status
Simulation time 19173384 ps
CPU time 1.03 seconds
Started Apr 18 02:26:10 PM PDT 24
Finished Apr 18 02:26:11 PM PDT 24
Peak memory 217392 kb
Host smart-16fc4b3c-66cd-4ead-88c8-d2bf27abba0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238899547 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.238899547
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/71.edn_err.2858182823
Short name T70
Test name
Test status
Simulation time 43388064 ps
CPU time 1.19 seconds
Started Apr 18 02:26:03 PM PDT 24
Finished Apr 18 02:26:05 PM PDT 24
Peak memory 233160 kb
Host smart-c20af5ed-e1d9-4965-98a0-d8a5b9b4e927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858182823 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2858182823
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3045162173
Short name T587
Test name
Test status
Simulation time 97987342 ps
CPU time 1.45 seconds
Started Apr 18 02:26:07 PM PDT 24
Finished Apr 18 02:26:09 PM PDT 24
Peak memory 217904 kb
Host smart-e62f895f-b2e2-438f-beb1-90ac74e6448b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045162173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3045162173
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.2934657568
Short name T165
Test name
Test status
Simulation time 19621145 ps
CPU time 1.23 seconds
Started Apr 18 02:26:03 PM PDT 24
Finished Apr 18 02:26:05 PM PDT 24
Peak memory 218084 kb
Host smart-794c4fb9-15b5-42cb-bd40-99c537b88183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934657568 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2934657568
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3267102189
Short name T356
Test name
Test status
Simulation time 81767628 ps
CPU time 1.16 seconds
Started Apr 18 02:26:03 PM PDT 24
Finished Apr 18 02:26:05 PM PDT 24
Peak memory 216336 kb
Host smart-a9f1edb7-1071-4675-9812-af87da6d53d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267102189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3267102189
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.3067077214
Short name T421
Test name
Test status
Simulation time 22235000 ps
CPU time 0.97 seconds
Started Apr 18 02:26:08 PM PDT 24
Finished Apr 18 02:26:09 PM PDT 24
Peak memory 217696 kb
Host smart-54a2105b-d68f-4d15-bcd4-4de7fef050ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067077214 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3067077214
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.457370181
Short name T570
Test name
Test status
Simulation time 65843104 ps
CPU time 1.05 seconds
Started Apr 18 02:26:05 PM PDT 24
Finished Apr 18 02:26:06 PM PDT 24
Peak memory 216288 kb
Host smart-d10b2705-7775-4d69-bb52-aa011632d065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457370181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.457370181
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.4062856152
Short name T773
Test name
Test status
Simulation time 24627029 ps
CPU time 1.03 seconds
Started Apr 18 02:26:11 PM PDT 24
Finished Apr 18 02:26:13 PM PDT 24
Peak memory 222536 kb
Host smart-7d00fa5c-0425-4f89-b6ab-8ac0c338c606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062856152 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.4062856152
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3544825721
Short name T271
Test name
Test status
Simulation time 245771739 ps
CPU time 3.04 seconds
Started Apr 18 02:26:09 PM PDT 24
Finished Apr 18 02:26:13 PM PDT 24
Peak memory 219360 kb
Host smart-9a8c5370-9e3b-45ce-96bf-f7a95a9bef21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544825721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3544825721
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.3142482954
Short name T414
Test name
Test status
Simulation time 20523541 ps
CPU time 1.08 seconds
Started Apr 18 02:26:03 PM PDT 24
Finished Apr 18 02:26:05 PM PDT 24
Peak memory 217816 kb
Host smart-d5efaf71-b2c8-4f18-8389-8f08eefd4d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142482954 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3142482954
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.4103695430
Short name T415
Test name
Test status
Simulation time 38047911 ps
CPU time 1.33 seconds
Started Apr 18 02:26:04 PM PDT 24
Finished Apr 18 02:26:06 PM PDT 24
Peak memory 217472 kb
Host smart-2d9bb88d-6ebe-43a7-9d15-eb4bd9c93e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103695430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.4103695430
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3848652216
Short name T795
Test name
Test status
Simulation time 57406736 ps
CPU time 0.98 seconds
Started Apr 18 02:26:10 PM PDT 24
Finished Apr 18 02:26:11 PM PDT 24
Peak memory 217808 kb
Host smart-34e1b4cc-6ed4-41e7-a2b3-f7cee684d70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848652216 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3848652216
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2886980186
Short name T285
Test name
Test status
Simulation time 57979157 ps
CPU time 1.47 seconds
Started Apr 18 02:26:10 PM PDT 24
Finished Apr 18 02:26:12 PM PDT 24
Peak memory 217852 kb
Host smart-da793f01-23ce-43b5-9d3f-6f2372179418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886980186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2886980186
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.2895671557
Short name T44
Test name
Test status
Simulation time 58257886 ps
CPU time 1.33 seconds
Started Apr 18 02:26:10 PM PDT 24
Finished Apr 18 02:26:12 PM PDT 24
Peak memory 233248 kb
Host smart-6b0a45ff-c976-413c-a802-ff81c8a87b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895671557 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2895671557
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.4270196160
Short name T767
Test name
Test status
Simulation time 45652912 ps
CPU time 1.39 seconds
Started Apr 18 02:26:08 PM PDT 24
Finished Apr 18 02:26:10 PM PDT 24
Peak memory 217388 kb
Host smart-5e4fac4f-48da-457e-95de-b807b10f98ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270196160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.4270196160
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.3891257077
Short name T46
Test name
Test status
Simulation time 46745600 ps
CPU time 1.29 seconds
Started Apr 18 02:26:11 PM PDT 24
Finished Apr 18 02:26:13 PM PDT 24
Peak memory 233044 kb
Host smart-60c4dae7-6b63-46f4-9d75-8010a6e9f19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891257077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3891257077
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.831761365
Short name T395
Test name
Test status
Simulation time 47681088 ps
CPU time 1.14 seconds
Started Apr 18 02:26:06 PM PDT 24
Finished Apr 18 02:26:08 PM PDT 24
Peak memory 216280 kb
Host smart-81109852-187f-4a6d-a34d-a8fbd12e8bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831761365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.831761365
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.3880541782
Short name T692
Test name
Test status
Simulation time 17980525 ps
CPU time 1.12 seconds
Started Apr 18 02:26:10 PM PDT 24
Finished Apr 18 02:26:12 PM PDT 24
Peak memory 222888 kb
Host smart-f95c0962-de86-44ee-bc24-7eed604cbb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880541782 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3880541782
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.4197031284
Short name T772
Test name
Test status
Simulation time 61900900 ps
CPU time 1.57 seconds
Started Apr 18 02:26:08 PM PDT 24
Finished Apr 18 02:26:10 PM PDT 24
Peak memory 216468 kb
Host smart-b890c485-30ac-4c02-9954-120bce75b83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197031284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.4197031284
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.492151547
Short name T242
Test name
Test status
Simulation time 93670551 ps
CPU time 1.22 seconds
Started Apr 18 02:24:50 PM PDT 24
Finished Apr 18 02:24:51 PM PDT 24
Peak memory 215368 kb
Host smart-94675632-f30b-44fc-be21-0fb7860ec639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492151547 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.492151547
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.563254343
Short name T535
Test name
Test status
Simulation time 74158785 ps
CPU time 0.91 seconds
Started Apr 18 02:25:25 PM PDT 24
Finished Apr 18 02:25:27 PM PDT 24
Peak memory 205652 kb
Host smart-64227bb6-58dd-4adb-bd4e-8744f07dd99d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563254343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.563254343
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1986195348
Short name T516
Test name
Test status
Simulation time 58328666 ps
CPU time 0.84 seconds
Started Apr 18 02:24:49 PM PDT 24
Finished Apr 18 02:24:51 PM PDT 24
Peak memory 215060 kb
Host smart-489cd2c5-e9a1-4bec-aaa2-36f1ee871629
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986195348 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1986195348
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1513494618
Short name T755
Test name
Test status
Simulation time 43930993 ps
CPU time 1.09 seconds
Started Apr 18 02:24:40 PM PDT 24
Finished Apr 18 02:24:41 PM PDT 24
Peak memory 217556 kb
Host smart-76528c05-da41-4b77-a294-10f8d3420d24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513494618 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1513494618
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2843050572
Short name T713
Test name
Test status
Simulation time 47864079 ps
CPU time 1.02 seconds
Started Apr 18 02:24:39 PM PDT 24
Finished Apr 18 02:24:41 PM PDT 24
Peak memory 219892 kb
Host smart-8aa2001f-9e77-4f26-a37f-13e880948e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843050572 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2843050572
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3324351675
Short name T492
Test name
Test status
Simulation time 46246777 ps
CPU time 1.71 seconds
Started Apr 18 02:24:38 PM PDT 24
Finished Apr 18 02:24:41 PM PDT 24
Peak memory 217656 kb
Host smart-64df01e1-9bd4-4532-8f01-a12f8530ac58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324351675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3324351675
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1314558110
Short name T103
Test name
Test status
Simulation time 27306953 ps
CPU time 0.81 seconds
Started Apr 18 02:24:39 PM PDT 24
Finished Apr 18 02:24:41 PM PDT 24
Peak memory 215292 kb
Host smart-86cf1a2e-bab9-40dc-b9ec-ac015400ad5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314558110 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1314558110
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.4289880182
Short name T245
Test name
Test status
Simulation time 30929535 ps
CPU time 0.93 seconds
Started Apr 18 02:24:39 PM PDT 24
Finished Apr 18 02:24:41 PM PDT 24
Peak memory 206816 kb
Host smart-2f60d78b-a951-4643-8bc7-4a28ecc929de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289880182 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.4289880182
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3162591579
Short name T777
Test name
Test status
Simulation time 16519683 ps
CPU time 0.99 seconds
Started Apr 18 02:24:38 PM PDT 24
Finished Apr 18 02:24:40 PM PDT 24
Peak memory 214976 kb
Host smart-fce87e5f-584d-4b1a-8fb7-1454fd230be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162591579 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3162591579
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1007211657
Short name T369
Test name
Test status
Simulation time 59676455 ps
CPU time 1.76 seconds
Started Apr 18 02:24:39 PM PDT 24
Finished Apr 18 02:24:42 PM PDT 24
Peak memory 215000 kb
Host smart-37c50a06-c386-4821-8916-d373aea6befd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007211657 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1007211657
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3691140087
Short name T187
Test name
Test status
Simulation time 153600276314 ps
CPU time 1800.37 seconds
Started Apr 18 02:24:38 PM PDT 24
Finished Apr 18 02:54:39 PM PDT 24
Peak memory 227508 kb
Host smart-96ca1deb-7d4a-4b16-9fc8-0d6c27874df2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691140087 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3691140087
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.3178383284
Short name T314
Test name
Test status
Simulation time 20010263 ps
CPU time 1.1 seconds
Started Apr 18 02:26:09 PM PDT 24
Finished Apr 18 02:26:11 PM PDT 24
Peak memory 217780 kb
Host smart-b076cb47-f186-4fc5-8fe4-19ddea888245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178383284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3178383284
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2954128428
Short name T547
Test name
Test status
Simulation time 93956980 ps
CPU time 1.11 seconds
Started Apr 18 02:26:06 PM PDT 24
Finished Apr 18 02:26:08 PM PDT 24
Peak memory 216180 kb
Host smart-2556c83d-9a19-48bf-bc31-49f4d3a967f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954128428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2954128428
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.3182637342
Short name T36
Test name
Test status
Simulation time 27736540 ps
CPU time 1.2 seconds
Started Apr 18 02:26:09 PM PDT 24
Finished Apr 18 02:26:10 PM PDT 24
Peak memory 219760 kb
Host smart-c90f1996-b690-47fc-8c30-6d71de3a22ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182637342 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3182637342
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3194838965
Short name T815
Test name
Test status
Simulation time 226974249 ps
CPU time 2.85 seconds
Started Apr 18 02:26:07 PM PDT 24
Finished Apr 18 02:26:11 PM PDT 24
Peak memory 217660 kb
Host smart-ca4fba04-143d-4066-8873-28dc88d8d119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194838965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3194838965
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.3760280329
Short name T465
Test name
Test status
Simulation time 22140704 ps
CPU time 1.08 seconds
Started Apr 18 02:26:10 PM PDT 24
Finished Apr 18 02:26:12 PM PDT 24
Peak memory 231812 kb
Host smart-de526ae3-046b-4e91-9abc-bf12ad2286b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760280329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3760280329
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3101198731
Short name T323
Test name
Test status
Simulation time 56951279 ps
CPU time 1.59 seconds
Started Apr 18 02:26:04 PM PDT 24
Finished Apr 18 02:26:07 PM PDT 24
Peak memory 217892 kb
Host smart-b20fb050-2b52-4f29-a007-8d68ed9cb1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101198731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3101198731
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.2008808865
Short name T170
Test name
Test status
Simulation time 24482599 ps
CPU time 1.13 seconds
Started Apr 18 02:26:10 PM PDT 24
Finished Apr 18 02:26:12 PM PDT 24
Peak memory 217588 kb
Host smart-d22f24b1-ef81-4577-99c1-9237d7616bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008808865 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2008808865
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.6443997
Short name T686
Test name
Test status
Simulation time 49481551 ps
CPU time 1.22 seconds
Started Apr 18 02:26:07 PM PDT 24
Finished Apr 18 02:26:09 PM PDT 24
Peak memory 216312 kb
Host smart-02569152-8d8d-439f-bb15-06451a4a676f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6443997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.6443997
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.3513463542
Short name T457
Test name
Test status
Simulation time 21535413 ps
CPU time 1.09 seconds
Started Apr 18 02:26:10 PM PDT 24
Finished Apr 18 02:26:12 PM PDT 24
Peak memory 217880 kb
Host smart-37898f69-8683-4f39-98d3-28ab7f608444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513463542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3513463542
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1123486139
Short name T560
Test name
Test status
Simulation time 51184004 ps
CPU time 1.42 seconds
Started Apr 18 02:26:08 PM PDT 24
Finished Apr 18 02:26:10 PM PDT 24
Peak memory 216184 kb
Host smart-1c4548b1-3fb7-41b2-b592-f5cd92a65bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123486139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1123486139
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.2375321297
Short name T34
Test name
Test status
Simulation time 43365072 ps
CPU time 1.13 seconds
Started Apr 18 02:26:13 PM PDT 24
Finished Apr 18 02:26:15 PM PDT 24
Peak memory 229484 kb
Host smart-60c7747f-22c1-4c3c-9090-711fb88885a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375321297 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2375321297
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3082095936
Short name T327
Test name
Test status
Simulation time 257547031 ps
CPU time 3.14 seconds
Started Apr 18 02:26:06 PM PDT 24
Finished Apr 18 02:26:09 PM PDT 24
Peak memory 217876 kb
Host smart-c342acbf-e6b5-4eb2-a599-124e99bc3e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082095936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3082095936
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.3659121286
Short name T347
Test name
Test status
Simulation time 24997156 ps
CPU time 0.85 seconds
Started Apr 18 02:26:08 PM PDT 24
Finished Apr 18 02:26:10 PM PDT 24
Peak memory 217612 kb
Host smart-26b1617d-921d-480b-ad44-63960aa31d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659121286 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3659121286
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.882429794
Short name T802
Test name
Test status
Simulation time 235465454 ps
CPU time 3.54 seconds
Started Apr 18 02:26:13 PM PDT 24
Finished Apr 18 02:26:17 PM PDT 24
Peak memory 217560 kb
Host smart-d7ffc79b-64b3-4d9e-82ab-56f270670c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882429794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.882429794
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1765490823
Short name T590
Test name
Test status
Simulation time 25735393 ps
CPU time 1.02 seconds
Started Apr 18 02:26:06 PM PDT 24
Finished Apr 18 02:26:08 PM PDT 24
Peak memory 232076 kb
Host smart-2d599488-76ac-414b-b15c-b91b0ed685e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765490823 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1765490823
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3097333429
Short name T333
Test name
Test status
Simulation time 192631865 ps
CPU time 1.13 seconds
Started Apr 18 02:26:07 PM PDT 24
Finished Apr 18 02:26:09 PM PDT 24
Peak memory 216516 kb
Host smart-55618a66-feeb-48c2-89ab-f9cfe469c812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097333429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3097333429
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.4018581814
Short name T792
Test name
Test status
Simulation time 55421887 ps
CPU time 1.06 seconds
Started Apr 18 02:26:11 PM PDT 24
Finished Apr 18 02:26:13 PM PDT 24
Peak memory 219920 kb
Host smart-69b2d844-16c8-498b-82ed-8bc7af61f721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018581814 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.4018581814
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3413317895
Short name T706
Test name
Test status
Simulation time 101707397 ps
CPU time 1.36 seconds
Started Apr 18 02:26:08 PM PDT 24
Finished Apr 18 02:26:10 PM PDT 24
Peak memory 217916 kb
Host smart-50c693a8-0ce4-4f0b-b88f-e44fd863a728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413317895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3413317895
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.205716523
Short name T804
Test name
Test status
Simulation time 25678401 ps
CPU time 0.97 seconds
Started Apr 18 02:26:12 PM PDT 24
Finished Apr 18 02:26:14 PM PDT 24
Peak memory 218904 kb
Host smart-2487e409-3a21-417b-ba62-95815a2af6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205716523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.205716523
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.259394108
Short name T391
Test name
Test status
Simulation time 45603153 ps
CPU time 1.69 seconds
Started Apr 18 02:26:12 PM PDT 24
Finished Apr 18 02:26:15 PM PDT 24
Peak memory 217648 kb
Host smart-2dd10666-eafb-46b0-8e2b-c7242d17a0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259394108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.259394108
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3134860020
Short name T583
Test name
Test status
Simulation time 374468873 ps
CPU time 1.59 seconds
Started Apr 18 02:24:44 PM PDT 24
Finished Apr 18 02:24:46 PM PDT 24
Peak memory 215412 kb
Host smart-20da6f2b-4da2-4ac6-a139-f30fd2204d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134860020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3134860020
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.183098772
Short name T116
Test name
Test status
Simulation time 36613458 ps
CPU time 0.81 seconds
Started Apr 18 02:24:43 PM PDT 24
Finished Apr 18 02:24:45 PM PDT 24
Peak memory 206304 kb
Host smart-324a4ca1-d209-45b8-8a95-5dc8f7d6040b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183098772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.183098772
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2198238423
Short name T82
Test name
Test status
Simulation time 21756022 ps
CPU time 0.85 seconds
Started Apr 18 02:24:45 PM PDT 24
Finished Apr 18 02:24:46 PM PDT 24
Peak memory 215612 kb
Host smart-5197fd4a-bf30-4e43-a038-a4bd3e231ab8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198238423 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2198238423
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_err.2545787619
Short name T605
Test name
Test status
Simulation time 24759437 ps
CPU time 0.91 seconds
Started Apr 18 02:24:44 PM PDT 24
Finished Apr 18 02:24:46 PM PDT 24
Peak memory 217504 kb
Host smart-02993b23-b9e8-45ae-9c93-d26640dd03f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545787619 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2545787619
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2883811199
Short name T672
Test name
Test status
Simulation time 33074817 ps
CPU time 1.18 seconds
Started Apr 18 02:24:37 PM PDT 24
Finished Apr 18 02:24:39 PM PDT 24
Peak memory 217596 kb
Host smart-8244762c-ffe8-43e6-841c-f172b502a2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883811199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2883811199
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.556365434
Short name T104
Test name
Test status
Simulation time 37724119 ps
CPU time 0.82 seconds
Started Apr 18 02:24:41 PM PDT 24
Finished Apr 18 02:24:43 PM PDT 24
Peak memory 215168 kb
Host smart-168ebdea-c6eb-4c2b-9099-78da815ec6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556365434 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.556365434
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.535526775
Short name T247
Test name
Test status
Simulation time 32151240 ps
CPU time 0.94 seconds
Started Apr 18 02:24:38 PM PDT 24
Finished Apr 18 02:24:40 PM PDT 24
Peak memory 206800 kb
Host smart-7bb2d03d-6150-430c-900b-ed36fd3a2699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535526775 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.535526775
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2590587776
Short name T559
Test name
Test status
Simulation time 64734449 ps
CPU time 0.96 seconds
Started Apr 18 02:24:49 PM PDT 24
Finished Apr 18 02:24:51 PM PDT 24
Peak memory 214972 kb
Host smart-e2f983ac-6127-495c-aa3b-791f8bef0c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590587776 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2590587776
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2242837725
Short name T831
Test name
Test status
Simulation time 129875987 ps
CPU time 3.22 seconds
Started Apr 18 02:24:50 PM PDT 24
Finished Apr 18 02:24:53 PM PDT 24
Peak memory 214948 kb
Host smart-a8ec8640-a40a-4cfd-acb9-783a308239eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242837725 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2242837725
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.294046549
Short name T188
Test name
Test status
Simulation time 190816803924 ps
CPU time 1024.58 seconds
Started Apr 18 02:24:40 PM PDT 24
Finished Apr 18 02:41:46 PM PDT 24
Peak memory 221396 kb
Host smart-5cb8d50e-ac16-4721-97ef-da6c1a7e537b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294046549 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.294046549
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.3553915906
Short name T61
Test name
Test status
Simulation time 28663297 ps
CPU time 1.32 seconds
Started Apr 18 02:26:11 PM PDT 24
Finished Apr 18 02:26:13 PM PDT 24
Peak memory 233352 kb
Host smart-2e3fd63e-ddd4-469d-b85c-8d00098df516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553915906 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3553915906
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2799938272
Short name T280
Test name
Test status
Simulation time 62446164 ps
CPU time 2.06 seconds
Started Apr 18 02:26:16 PM PDT 24
Finished Apr 18 02:26:19 PM PDT 24
Peak memory 217496 kb
Host smart-75c27ec8-4f49-4e4e-bbd9-1ffce0e13cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799938272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2799938272
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.3844520480
Short name T433
Test name
Test status
Simulation time 77606355 ps
CPU time 1.09 seconds
Started Apr 18 02:26:14 PM PDT 24
Finished Apr 18 02:26:16 PM PDT 24
Peak memory 218944 kb
Host smart-32547430-bb61-4832-a38b-519b44c66ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844520480 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3844520480
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2226841763
Short name T39
Test name
Test status
Simulation time 29027578 ps
CPU time 1.32 seconds
Started Apr 18 02:26:12 PM PDT 24
Finished Apr 18 02:26:14 PM PDT 24
Peak memory 218912 kb
Host smart-0ad1b031-080a-4337-ae7a-4356121b4edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226841763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2226841763
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.3120229436
Short name T81
Test name
Test status
Simulation time 37838072 ps
CPU time 0.9 seconds
Started Apr 18 02:26:11 PM PDT 24
Finished Apr 18 02:26:12 PM PDT 24
Peak memory 217464 kb
Host smart-282afc6a-96ae-434f-aaa9-ce5113b2e234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120229436 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3120229436
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1336825703
Short name T286
Test name
Test status
Simulation time 120490597 ps
CPU time 2.4 seconds
Started Apr 18 02:26:12 PM PDT 24
Finished Apr 18 02:26:15 PM PDT 24
Peak memory 217676 kb
Host smart-5f89e582-af9a-4e32-8f34-6f725549bc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336825703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1336825703
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.1947194115
Short name T719
Test name
Test status
Simulation time 36369574 ps
CPU time 1.12 seconds
Started Apr 18 02:26:16 PM PDT 24
Finished Apr 18 02:26:18 PM PDT 24
Peak memory 220160 kb
Host smart-74398566-4fe4-41b3-bcca-286298199738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947194115 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1947194115
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1771549869
Short name T799
Test name
Test status
Simulation time 180109276 ps
CPU time 1.36 seconds
Started Apr 18 02:26:20 PM PDT 24
Finished Apr 18 02:26:21 PM PDT 24
Peak memory 216492 kb
Host smart-1f7e541b-4558-4683-a65e-73d514163fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771549869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1771549869
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.541162623
Short name T555
Test name
Test status
Simulation time 26294736 ps
CPU time 0.98 seconds
Started Apr 18 02:26:12 PM PDT 24
Finished Apr 18 02:26:14 PM PDT 24
Peak memory 222592 kb
Host smart-d27df768-78b0-419c-a59c-e145625d924a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541162623 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.541162623
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1344741255
Short name T644
Test name
Test status
Simulation time 45848032 ps
CPU time 1.56 seconds
Started Apr 18 02:26:12 PM PDT 24
Finished Apr 18 02:26:14 PM PDT 24
Peak memory 216516 kb
Host smart-e20c98a6-497f-45ad-8876-1aa3e6cb50f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344741255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1344741255
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.14968213
Short name T567
Test name
Test status
Simulation time 22228018 ps
CPU time 1.16 seconds
Started Apr 18 02:26:16 PM PDT 24
Finished Apr 18 02:26:18 PM PDT 24
Peak memory 218256 kb
Host smart-0cfad846-8310-4457-9ca6-95101b38801b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14968213 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.14968213
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2828011816
Short name T439
Test name
Test status
Simulation time 37642813 ps
CPU time 1.55 seconds
Started Apr 18 02:26:14 PM PDT 24
Finished Apr 18 02:26:16 PM PDT 24
Peak memory 217284 kb
Host smart-b2ed20e8-b871-42ba-9b56-75ba3926b14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828011816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2828011816
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.1282603725
Short name T7
Test name
Test status
Simulation time 53535924 ps
CPU time 0.98 seconds
Started Apr 18 02:26:14 PM PDT 24
Finished Apr 18 02:26:16 PM PDT 24
Peak memory 218600 kb
Host smart-b73e5179-dd12-4833-9325-b841c5f346cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282603725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1282603725
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2191525861
Short name T25
Test name
Test status
Simulation time 47690326 ps
CPU time 1.7 seconds
Started Apr 18 02:26:16 PM PDT 24
Finished Apr 18 02:26:18 PM PDT 24
Peak memory 217404 kb
Host smart-6e10e6e6-5c32-4d96-b9af-1e1410529dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191525861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2191525861
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.163403473
Short name T458
Test name
Test status
Simulation time 71655341 ps
CPU time 1.25 seconds
Started Apr 18 02:26:14 PM PDT 24
Finished Apr 18 02:26:16 PM PDT 24
Peak memory 232964 kb
Host smart-ea7e246b-5f9c-43b4-b99e-11adc4abd356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163403473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.163403473
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.871406538
Short name T581
Test name
Test status
Simulation time 299130379 ps
CPU time 4 seconds
Started Apr 18 02:26:15 PM PDT 24
Finished Apr 18 02:26:20 PM PDT 24
Peak memory 219184 kb
Host smart-49995f10-2001-41e8-bcc7-9fe82fbbed0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871406538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.871406538
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1052828397
Short name T5
Test name
Test status
Simulation time 20067051 ps
CPU time 1.02 seconds
Started Apr 18 02:26:13 PM PDT 24
Finished Apr 18 02:26:15 PM PDT 24
Peak memory 217852 kb
Host smart-5c91570b-3d14-4be2-98a3-3f4d6deedb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052828397 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1052828397
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2166464219
Short name T441
Test name
Test status
Simulation time 73130815 ps
CPU time 1.24 seconds
Started Apr 18 02:26:12 PM PDT 24
Finished Apr 18 02:26:15 PM PDT 24
Peak memory 217992 kb
Host smart-f638ec8f-e040-4dfc-aec2-3ee401f3bc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166464219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2166464219
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.3180612864
Short name T47
Test name
Test status
Simulation time 86417312 ps
CPU time 0.99 seconds
Started Apr 18 02:26:12 PM PDT 24
Finished Apr 18 02:26:14 PM PDT 24
Peak memory 219716 kb
Host smart-4d46af20-d900-455e-88b0-0161689d93b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180612864 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3180612864
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1025293322
Short name T339
Test name
Test status
Simulation time 49096675 ps
CPU time 1.27 seconds
Started Apr 18 02:26:14 PM PDT 24
Finished Apr 18 02:26:16 PM PDT 24
Peak memory 217488 kb
Host smart-47209006-a540-4bdd-a50b-2247225f5aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025293322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1025293322
Directory /workspace/99.edn_genbits/latest
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