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 LINE       292
 EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)
             ------------1------------    ------2-----
-1--2-StatusTests
01CoveredT1,T3,T7
10CoveredT2,T7,T24
11CoveredT1,T3,T7

 LINE       297
 EXPRESSION (sfifo_rescmd_int_err || sfifo_gencmd_int_err || edn_cntr_err_sum || edn_main_sm_err_sum || edn_ack_sm_err_sum)
             ----------1---------    ----------2---------    --------3-------    ---------4---------    ---------5--------
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001CoveredT6,T39,T82
00010CoveredT79,T80,T81
00100CoveredT4,T15,T16
01000CoveredT17,T18,T19
10000CoveredT17,T18,T19

 LINE       304
 EXPRESSION ((edn_enable_fo[FatalErr] && (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum)) || fatal_loc_events)
             -------------------------------------1-------------------------------------    --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T6,T39
10CoveredT36,T34,T37

 LINE       304
 SUB-EXPRESSION (edn_enable_fo[FatalErr] && (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum))
                 -----------1-----------    -----------------------2----------------------
-1--2-StatusTests
01CoveredT36,T34,T37
10CoveredT1,T2,T3
11CoveredT36,T34,T37

 LINE       304
 SUB-EXPRESSION (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum)
                 ----------1---------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT36,T37,T38
10CoveredT34,T17,T35

 LINE       310
 EXPRESSION (((|sfifo_rescmd_err)) || err_code_test_bit[0])
             ----------1----------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT34,T17,T35

 LINE       312
 EXPRESSION (((|sfifo_gencmd_err)) || err_code_test_bit[1])
             ----------1----------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT36,T37,T38

 LINE       314
 EXPRESSION (((|edn_ack_sm_err)) || err_code_test_bit[20])
             ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T6,T39

 LINE       316
 EXPRESSION (edn_main_sm_err || err_code_test_bit[21])
             -------1-------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T6,T39

 LINE       318
 EXPRESSION (edn_cntr_err || err_code_test_bit[22])
             ------1-----    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T15,T16

 LINE       321
 EXPRESSION (sfifo_rescmd_err[2] || sfifo_gencmd_err[2] || err_code_test_bit[28])
             ---------1---------    ---------2---------    ----------3----------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT36,T40
100CoveredT41,T153

 LINE       325
 EXPRESSION (sfifo_rescmd_err[1] || sfifo_gencmd_err[1] || err_code_test_bit[29])
             ---------1---------    ---------2---------    ----------3----------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT38,T105,T106
100CoveredT34,T35,T104

 LINE       329
 EXPRESSION (sfifo_rescmd_err[0] || sfifo_gencmd_err[0] || err_code_test_bit[30])
             ---------1---------    ---------2---------    ----------3----------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT36,T37,T40
100CoveredT17,T41,T154

 LINE       337
 EXPRESSION (edn_enable_fo[ReseedCmdErr] && sfifo_rescmd_err_sum)
             -------------1-------------    ----------2---------
-1--2-StatusTests
01CoveredT34,T17,T35
10CoveredT1,T2,T3
11CoveredT34,T17,T35

 LINE       340
 EXPRESSION (edn_enable_fo[GenCmdErr] && sfifo_gencmd_err_sum)
             ------------1-----------    ----------2---------
-1--2-StatusTests
01CoveredT36,T37,T38
10CoveredT1,T2,T3
11CoveredT36,T37,T38

 LINE       357
 EXPRESSION (edn_enable_fo[FifoWrErr] && fifo_write_err_sum)
             ------------1-----------    ---------2--------
-1--2-StatusTests
01CoveredT36,T40,T41
10CoveredT1,T2,T3
11CoveredT36,T40,T41

 LINE       360
 EXPRESSION (edn_enable_fo[FifoRdErr] && fifo_read_err_sum)
             ------------1-----------    --------2--------
-1--2-StatusTests
01CoveredT34,T38,T35
10CoveredT1,T2,T3
11CoveredT34,T38,T35

 LINE       363
 EXPRESSION (edn_enable_fo[FifoStErr] && fifo_status_err_sum)
             ------------1-----------    ---------2---------
-1--2-StatusTests
01CoveredT36,T37,T40
10CoveredT1,T2,T3
11CoveredT36,T37,T40

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 0) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT1,T2,T3
11Not Covered

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 0)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 1) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10Not Covered
11Not Covered

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 1)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 2) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT5,T42,T44
11CoveredT5,T42,T44

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 2)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T42,T44

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 3) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT42,T43,T44
11CoveredT42,T43,T44

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 3)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT42,T43,T44

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 4) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT42,T49,T155
11CoveredT42,T49,T155

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 4)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT42,T49,T155

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 5) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT42,T79,T77
11CoveredT42,T79,T77

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 5)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT42,T79,T77

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 6) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT43,T77,T156
11CoveredT43,T77,T156

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 6)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT43,T77,T156

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 7) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT43,T44,T77
11CoveredT43,T44,T77

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 7)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT43,T44,T77

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 8) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT42,T77,T85
11CoveredT42,T77,T85

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 8)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT42,T77,T85

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 9) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT42,T43,T79
11CoveredT42,T43,T79

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 9)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT42,T43,T79

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 10) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT43,T44,T57
11CoveredT43,T44,T57

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 10)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT43,T44,T57

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 11) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT5,T28,T42
11CoveredT5,T28,T42

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 11)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T28,T42

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 12) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT43,T77,T32
11CoveredT43,T77,T32

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 12)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT43,T77,T32

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 13) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT42,T44,T77
11CoveredT42,T44,T77

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 13)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT42,T44,T77

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 14) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT42,T43,T77
11CoveredT42,T43,T77

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 14)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT42,T43,T77

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 15) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT42,T44,T77
11CoveredT42,T44,T77

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 15)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT42,T44,T77

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 16) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT42,T43,T44
11CoveredT42,T43,T44

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 16)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT42,T43,T44

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 17) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT7,T39,T42
11CoveredT7,T39,T42

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 17)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T39,T42

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 18) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT42,T43,T46
11CoveredT42,T43,T46

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 18)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT42,T43,T46

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 19) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT42,T43,T155
11CoveredT42,T43,T155

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 19)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT42,T43,T155

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 20) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10Not Covered
11Not Covered

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 20)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 21) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10Not Covered
11Not Covered

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 21)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 22) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10Not Covered
11Not Covered

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 22)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 23) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T7,T5
10CoveredT3,T6,T42
11CoveredT3,T6,T42

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 23)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T6,T42

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 24) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT3,T7,T5
10CoveredT2,T42,T43
11CoveredT2,T42,T43

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 24)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T42,T43

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 25) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT6,T43,T155
11CoveredT6,T43,T155

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 25)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T43,T155

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 26) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT43,T50,T157
11CoveredT43,T50,T157

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 26)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT43,T50,T157

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 27) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT42,T44,T77
11CoveredT42,T44,T77

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 27)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT42,T44,T77

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 28) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10Not Covered
11Not Covered

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 28)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 29) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10Not Covered
11Not Covered

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 29)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 30) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T7
10Not Covered
11Not Covered

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 30)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       372
 EXPRESSION (edn_enable_fo[CsrngAckErr] && csrng_cmd_i.csrng_rsp_sts && csrng_cmd_i.csrng_rsp_ack)
             -------------1------------    ------------2------------    ------------3------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT31,T32,T33

 LINE       378
 EXPRESSION (edn_bus_cmp_alert || cmd_fifo_rst_pfa || auto_req_mode_pfa || boot_req_mode_pfa || edn_enable_pfa || csrng_ack_err)
             --------1--------    --------2-------    --------3--------    --------4--------    -------5------    ------6------
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T3
000001CoveredT31,T32,T33
000010CoveredT158,T141,T159
000100CoveredT33,T142,T160
001000CoveredT31,T32,T140
010000CoveredT57,T56,T109
100000CoveredT31,T32,T33

 LINE       397
 EXPRESSION (event_edn_fatal_err || sfifo_rescmd_int_err || sfifo_gencmd_int_err)
             ---------1---------    ----------2---------    ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100CoveredT4,T6,T39

 LINE       400
 SUB-EXPRESSION (reg2hw.alert_test.recov_alert.q && reg2hw.alert_test.recov_alert.qe)
                 ---------------1---------------    ----------------2---------------
-1--2-StatusTests
01CoveredT26,T58,T59
10CoveredT1,T2,T3
11CoveredT26,T58,T59

 LINE       404
 SUB-EXPRESSION (reg2hw.alert_test.fatal_alert.q && reg2hw.alert_test.fatal_alert.qe)
                 ---------------1---------------    ----------------2---------------
-1--2-StatusTests
01CoveredT26,T58,T59
10CoveredT1,T2,T3
11CoveredT26,T58,T59

 LINE       480
 EXPRESSION (reg2hw.sw_cmd_req.qe && cmd_reg_rdy_q)
             ----------1---------    ------2------
-1--2-StatusTests
01CoveredT1,T3,T7
10CoveredT7,T100,T20
11CoveredT1,T3,T7

 LINE       492
 EXPRESSION (cs_cmd_req_vld_out_q && send_cs_cmd_gated)
             ----------1---------    --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       493
 EXPRESSION (cs_cmd_req_vld_out_q && send_gencmd_gated)
             ----------1---------    --------2--------
-1--2-StatusTests
01CoveredT7,T10,T14
10CoveredT1,T2,T3
11CoveredT7,T10,T14

 LINE       494
 EXPRESSION (cs_cmd_req_vld_out_q && send_rescmd_gated)
             ----------1---------    --------2--------
-1--2-StatusTests
01CoveredT7,T10,T14
10CoveredT1,T2,T3
11CoveredT7,T10,T14

 LINE       497
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReq])) ? '0 : (boot_wr_ins_cmd ? boot_ins_cmd : (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       497
 SUB-EXPRESSION 
 Number  Term
      1  boot_wr_ins_cmd ? boot_ins_cmd : (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T24,T6

 LINE       497
 SUB-EXPRESSION (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)))
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T24,T6

 LINE       497
 SUB-EXPRESSION (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q))
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T47,T46

 LINE       497
 SUB-EXPRESSION (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T7

 LINE       506
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqValid])) ? '0 : (cs_cmd_handshake ? '0 : ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q)))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       506
 SUB-EXPRESSION (cs_cmd_handshake ? '0 : ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q))
                 --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       506
 SUB-EXPRESSION ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q)
                 -------------------------------------1------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       506
 SUB-EXPRESSION (sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd)
                 -------1-------    -------2-------    -------3-------    -------4-------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT24,T47,T46
0010CoveredT2,T24,T6
0100CoveredT2,T24,T6
1000CoveredT1,T3,T7

 LINE       513
 EXPRESSION (cs_cmd_req_vld_q && csrng_cmd_i.csrng_req_ready)
             --------1-------    -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       517
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqOut])) ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q) : ((send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       517
 SUB-EXPRESSION 
 Number  Term
      1  (send_rescmd || capt_rescmd_fifo_cnt) ? (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q) : ((send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q)))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T10,T14

 LINE       517
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt)
                 -----1-----    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T10,T14
10CoveredT7,T10,T14

 LINE       517
 SUB-EXPRESSION (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q)
                 --------1-------
-1-StatusTests
0CoveredT7,T10,T14
1CoveredT7,T10,T14

 LINE       517
 SUB-EXPRESSION 
 Number  Term
      1  (send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T10,T14

 LINE       517
 SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T10,T14
10CoveredT7,T10,T14

 LINE       517
 SUB-EXPRESSION (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q)
                 --------1-------
-1-StatusTests
0CoveredT7,T10,T14
1CoveredT7,T10,T14

 LINE       517
 SUB-EXPRESSION ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q)
                 ---------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       517
 SUB-EXPRESSION (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))
                 --------1-------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       533
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqValidOut])) ? '0 : (cmd_sent ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       533
 SUB-EXPRESSION 
 Number  Term
      1  cmd_sent ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake))))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T10,T14

 LINE       533
 SUB-EXPRESSION ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))))
                 ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T10,T14

 LINE       533
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt)
                 -----1-----    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T10,T14
10CoveredT10,T14,T32

 LINE       533
 SUB-EXPRESSION ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake))))
                 ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T10,T14

 LINE       533
 SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T10,T14
10CoveredT7,T10,T14

 LINE       533
 SUB-EXPRESSION (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))
                 --------1-------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       548
 EXPRESSION (((!sw_cmd_req_load)) && cmd_rdy_d && cmd_reg_rdy_d)
             ----------1---------    ----2----    ------3------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T7
110Not Covered
111CoveredT1,T3,T7

 LINE       552
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (((!sw_cmd_valid)) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       552
 SUB-EXPRESSION (((!sw_cmd_valid)) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))))
                 --------1--------
-1-StatusTests
0CoveredT1,T3,T7
1CoveredT2,T7,T24

 LINE       552
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)))
                 -------1-------
-1-StatusTests
0CoveredT1,T3,T7
1CoveredT1,T3,T7

 LINE       552
 SUB-EXPRESSION (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))
                 ----------1---------
-1-StatusTests
0CoveredT1,T3,T7
1CoveredT1,T3,T7

 LINE       552
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T3,T7
1CoveredT1,T3,T7

 LINE       563
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (((!sw_cmd_valid)) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       563
 SUB-EXPRESSION (((!sw_cmd_valid)) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q))))
                 --------1--------
-1-StatusTests
0CoveredT1,T3,T7
1CoveredT2,T7,T24

 LINE       563
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)))
                 -------1-------
-1-StatusTests
0CoveredT1,T3,T7
1CoveredT1,T3,T7

 LINE       563
 SUB-EXPRESSION (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q))
                 ----------1---------
-1-StatusTests
0CoveredT1,T3,T7
1CoveredT1,T3,T7

 LINE       563
 SUB-EXPRESSION (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)
                 --------1-------
-1-StatusTests
0CoveredT1,T3,T7
1CoveredT1,T3,T7

 LINE       574
 EXPRESSION (((!edn_enable_fo[SwCmdSts])) ? CMD_STS_SUCCESS : ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? csrng_cmd_i.csrng_rsp_sts : csrng_cmd_sts_q))
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       574
 SUB-EXPRESSION ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? csrng_cmd_i.csrng_rsp_sts : csrng_cmd_sts_q)
                 ---------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T7

 LINE       574
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)
                 ------------1------------    ------2-----
-1--2-StatusTests
01CoveredT1,T3,T7
10CoveredT2,T7,T24
11CoveredT1,T3,T7

 LINE       582
 EXPRESSION (((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? 1'b1 : csrng_sw_cmd_ack_q)))
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       582
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? 1'b1 : csrng_sw_cmd_ack_q))
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T7

 LINE       582
 SUB-EXPRESSION ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? 1'b1 : csrng_sw_cmd_ack_q)
                 ---------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T7

 LINE       582
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)
                 ------------1------------    ------2-----
-1--2-StatusTests
01CoveredT1,T3,T7
10CoveredT2,T7,T24
11CoveredT1,T3,T7

 LINE       594
 EXPRESSION ((main_sm_done_pulse || ((!edn_enable_fo[HwCmdSts]))) ? 1'b0 : (boot_wr_ins_cmd ? 1'b1 : boot_mode_q))
             --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       594
 SUB-EXPRESSION (main_sm_done_pulse || ((!edn_enable_fo[HwCmdSts])))
                 ---------1--------    --------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T3,T7

 LINE       594
 SUB-EXPRESSION (boot_wr_ins_cmd ? 1'b1 : boot_mode_q)
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T24,T6

 LINE       600
 EXPRESSION ((main_sm_done_pulse || ((!edn_enable_fo[HwCmdSts]))) ? 1'b0 : (auto_req_mode_busy ? 1'b1 : auto_mode_q))
             --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       600
 SUB-EXPRESSION (main_sm_done_pulse || ((!edn_enable_fo[HwCmdSts])))
                 ---------1--------    --------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T3,T7

 LINE       600
 SUB-EXPRESSION (auto_req_mode_busy ? 1'b1 : auto_mode_q)
                 ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T10,T14

 LINE       607
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[HwCmdSts])) ? CMD_STS_SUCCESS : (sw_cmd_valid ? csrng_hw_cmd_sts_q : ((cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready) ? CMD_STS_SUCCESS : ((csrng_cmd_i.csrng_rsp_ack && csrng_cmd_i.csrng_rsp_sts) ? csrng_cmd_i.csrng_rsp_sts : csrng_hw_cmd_sts_q))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       607
 SUB-EXPRESSION 
 Number  Term
      1  sw_cmd_valid ? csrng_hw_cmd_sts_q : ((cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready) ? CMD_STS_SUCCESS : ((csrng_cmd_i.csrng_rsp_ack && csrng_cmd_i.csrng_rsp_sts) ? csrng_cmd_i.csrng_rsp_sts : csrng_hw_cmd_sts_q)))
-1-StatusTests
0CoveredT2,T7,T24
1CoveredT1,T3,T7

 LINE       607
 SUB-EXPRESSION 
 Number  Term
      1  (cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready) ? CMD_STS_SUCCESS : ((csrng_cmd_i.csrng_rsp_ack && csrng_cmd_i.csrng_rsp_sts) ? csrng_cmd_i.csrng_rsp_sts : csrng_hw_cmd_sts_q))
-1-StatusTests
0CoveredT2,T7,T24
1CoveredT2,T7,T24

 LINE       607
 SUB-EXPRESSION (cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready)
                 ----------1---------    -------------2-------------
-1--2-StatusTests
01CoveredT2,T7,T24
10CoveredT2,T7,T24
11CoveredT2,T7,T24

 LINE       607
 SUB-EXPRESSION ((csrng_cmd_i.csrng_rsp_ack && csrng_cmd_i.csrng_rsp_sts) ? csrng_cmd_i.csrng_rsp_sts : csrng_hw_cmd_sts_q)
                 ----------------------------1---------------------------
-1-StatusTests
0CoveredT2,T7,T24
1CoveredT31,T32,T33

 LINE       607
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack && csrng_cmd_i.csrng_rsp_sts)
                 ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T7,T24
11CoveredT31,T32,T33

 LINE       617
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[HwCmdSts])) ? 1'b0 : (sw_cmd_valid ? csrng_hw_cmd_ack_q : ((cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready) ? 1'b0 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : csrng_hw_cmd_ack_q))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       617
 SUB-EXPRESSION 
 Number  Term
      1  sw_cmd_valid ? csrng_hw_cmd_ack_q : ((cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready) ? 1'b0 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : csrng_hw_cmd_ack_q)))
-1-StatusTests
0CoveredT2,T7,T24
1CoveredT1,T3,T7

 LINE       617
 SUB-EXPRESSION ((cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready) ? 1'b0 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : csrng_hw_cmd_ack_q))
                 --------------------------1--------------------------
-1-StatusTests
0CoveredT2,T7,T24
1CoveredT2,T7,T24

 LINE       617
 SUB-EXPRESSION (cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready)
                 ----------1---------    -------------2-------------
-1--2-StatusTests
01CoveredT2,T7,T24
10CoveredT2,T7,T24
11CoveredT2,T7,T24

 LINE       617
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : csrng_hw_cmd_ack_q)
                 ------------1------------
-1-StatusTests
0CoveredT2,T7,T24
1CoveredT2,T7,T24

 LINE       627
 EXPRESSION ((edn_enable_fo[HwCmdSts] && ((!sw_cmd_valid)) && cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready) ? cs_cmd_req_out_q[3:0] : cmd_type_q)
             --------------------------------------------------1--------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T7,T24

 LINE       627
 SUB-EXPRESSION (edn_enable_fo[HwCmdSts] && ((!sw_cmd_valid)) && cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready)
                 -----------1-----------    --------2--------    ----------3---------    -------------4-------------
-1--2--3--4-StatusTests
0111CoveredT63,T64,T126
1011CoveredT1,T3,T7
1101CoveredT2,T7,T24
1110CoveredT2,T7,T24
1111CoveredT2,T7,T24

 LINE       654
 EXPRESSION ((send_rescmd || capt_rescmd_fifo_cnt) && csrng_cmd_i.csrng_req_ready)
             ------------------1------------------    -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T10,T14
11CoveredT7,T10,T14

 LINE       654
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt)
                 -----1-----    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T10,T14
10CoveredT7,T10,T14

 LINE       656
 EXPRESSION (rescmd_handshake ? 1'b1 : reseed_cmd_load)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T10,T14

 LINE       660
 EXPRESSION (auto_req_mode_busy ? cs_cmd_req_out_q : reseed_cmd_bus)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T10,T14

 LINE       664
 EXPRESSION ((rescmd_handshake && ((!cmd_sent))) || capt_rescmd_fifo_cnt)
             -----------------1-----------------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T10,T14
10CoveredT10,T14,T20

 LINE       664
 SUB-EXPRESSION (rescmd_handshake && ((!cmd_sent)))
                 --------1-------    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T10,T14
11CoveredT10,T14,T20

 LINE       666
 EXPRESSION (cmd_fifo_rst_fo[1] || main_sm_done_pulse)
             ---------1--------    ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T7
10CoveredT7,T4,T6

 LINE       668
 SUB-EXPRESSION (sfifo_rescmd_push && sfifo_rescmd_full)
                 --------1--------    --------2--------
-1--2-StatusTests
01CoveredT101,T102,T103
10CoveredT7,T4,T6
11CoveredT41,T153

 LINE       668
 SUB-EXPRESSION (sfifo_rescmd_pop && ((!sfifo_rescmd_not_empty)))
                 --------1-------    -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T10,T14
11CoveredT34,T35,T104

 LINE       668
 SUB-EXPRESSION ((sfifo_rescmd_full && ((!sfifo_rescmd_not_empty))) || sfifo_rescmd_int_err)
                 -------------------------1------------------------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T19
10CoveredT41,T154,T153

 LINE       668
 SUB-EXPRESSION (sfifo_rescmd_full && ((!sfifo_rescmd_not_empty)))
                 --------1--------    -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT101,T102,T103
11CoveredT41,T154,T153

 LINE       697
 EXPRESSION ((send_gencmd || capt_gencmd_fifo_cnt) && csrng_cmd_i.csrng_req_ready)
             ------------------1------------------    -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T10,T14
11CoveredT7,T10,T14

 LINE       697
 SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T10,T14
10CoveredT7,T10,T14

 LINE       699
 EXPRESSION (gencmd_handshake ? 1'b1 : generate_cmd_load)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T10,T14

 LINE       703
 EXPRESSION (auto_req_mode_busy ? cs_cmd_req_out_q : generate_cmd_bus)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T10,T14

 LINE       707
 EXPRESSION ((gencmd_handshake && ((!cmd_sent))) || capt_gencmd_fifo_cnt)
             -----------------1-----------------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T10,T14
10CoveredT10,T14,T100

 LINE       707
 SUB-EXPRESSION (gencmd_handshake && ((!cmd_sent)))
                 --------1-------    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T10,T14
11CoveredT10,T14,T100

 LINE       709
 EXPRESSION (cmd_fifo_rst_fo[2] || main_sm_done_pulse)
             ---------1--------    ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T7
10CoveredT7,T4,T6

 LINE       711
 SUB-EXPRESSION (sfifo_gencmd_push && sfifo_gencmd_full)
                 --------1--------    --------2--------
-1--2-StatusTests
01CoveredT7,T4,T10
10CoveredT7,T4,T6
11CoveredT36,T40
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%