Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.17 98.24 93.82 97.01 80.92 96.76 99.77 92.64


Total test records in report: 969
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T786 /workspace/coverage/default/21.edn_smoke.1257026750 Apr 21 01:35:54 PM PDT 24 Apr 21 01:35:55 PM PDT 24 20208327 ps
T787 /workspace/coverage/default/50.edn_genbits.2637799240 Apr 21 01:37:17 PM PDT 24 Apr 21 01:37:19 PM PDT 24 37938172 ps
T788 /workspace/coverage/default/30.edn_genbits.3972934098 Apr 21 01:36:25 PM PDT 24 Apr 21 01:36:27 PM PDT 24 153814402 ps
T259 /workspace/coverage/default/23.edn_alert.3027957861 Apr 21 01:36:03 PM PDT 24 Apr 21 01:36:05 PM PDT 24 38358880 ps
T789 /workspace/coverage/default/20.edn_stress_all.3381370734 Apr 21 01:35:57 PM PDT 24 Apr 21 01:36:01 PM PDT 24 632018490 ps
T790 /workspace/coverage/default/18.edn_smoke.388677955 Apr 21 01:35:45 PM PDT 24 Apr 21 01:35:46 PM PDT 24 55181294 ps
T791 /workspace/coverage/default/68.edn_genbits.971255745 Apr 21 01:37:29 PM PDT 24 Apr 21 01:37:31 PM PDT 24 126578539 ps
T792 /workspace/coverage/default/169.edn_genbits.1673149144 Apr 21 01:38:12 PM PDT 24 Apr 21 01:38:13 PM PDT 24 34700556 ps
T793 /workspace/coverage/default/18.edn_alert_test.1619344398 Apr 21 01:35:49 PM PDT 24 Apr 21 01:35:50 PM PDT 24 41219233 ps
T794 /workspace/coverage/default/245.edn_genbits.3784473390 Apr 21 01:38:36 PM PDT 24 Apr 21 01:38:38 PM PDT 24 57223921 ps
T795 /workspace/coverage/default/98.edn_err.3963313428 Apr 21 01:37:49 PM PDT 24 Apr 21 01:37:50 PM PDT 24 72834863 ps
T796 /workspace/coverage/default/198.edn_genbits.1891395245 Apr 21 01:38:18 PM PDT 24 Apr 21 01:38:20 PM PDT 24 45623046 ps
T797 /workspace/coverage/default/61.edn_err.2231254130 Apr 21 01:37:27 PM PDT 24 Apr 21 01:37:28 PM PDT 24 40718001 ps
T798 /workspace/coverage/default/178.edn_genbits.3521045152 Apr 21 01:38:14 PM PDT 24 Apr 21 01:38:15 PM PDT 24 46406906 ps
T115 /workspace/coverage/default/37.edn_disable_auto_req_mode.29432329 Apr 21 01:36:44 PM PDT 24 Apr 21 01:36:45 PM PDT 24 71539903 ps
T799 /workspace/coverage/default/38.edn_alert_test.321422887 Apr 21 01:36:47 PM PDT 24 Apr 21 01:36:48 PM PDT 24 17038885 ps
T800 /workspace/coverage/default/5.edn_alert_test.3934861255 Apr 21 01:35:10 PM PDT 24 Apr 21 01:35:11 PM PDT 24 15352702 ps
T801 /workspace/coverage/default/72.edn_err.255445642 Apr 21 01:37:34 PM PDT 24 Apr 21 01:37:35 PM PDT 24 28143029 ps
T802 /workspace/coverage/default/248.edn_genbits.2349910494 Apr 21 01:38:35 PM PDT 24 Apr 21 01:38:37 PM PDT 24 65581758 ps
T803 /workspace/coverage/default/4.edn_intr.4200677576 Apr 21 01:35:02 PM PDT 24 Apr 21 01:35:03 PM PDT 24 36948615 ps
T804 /workspace/coverage/default/7.edn_stress_all.1155561196 Apr 21 01:35:15 PM PDT 24 Apr 21 01:35:21 PM PDT 24 472850733 ps
T805 /workspace/coverage/default/46.edn_err.2065690919 Apr 21 01:37:11 PM PDT 24 Apr 21 01:37:12 PM PDT 24 29069936 ps
T806 /workspace/coverage/default/5.edn_alert.2702621235 Apr 21 01:35:07 PM PDT 24 Apr 21 01:35:08 PM PDT 24 84854746 ps
T807 /workspace/coverage/default/11.edn_stress_all.2170606167 Apr 21 01:35:26 PM PDT 24 Apr 21 01:35:29 PM PDT 24 1430690613 ps
T808 /workspace/coverage/default/13.edn_disable_auto_req_mode.1355480234 Apr 21 01:35:34 PM PDT 24 Apr 21 01:35:35 PM PDT 24 31204794 ps
T255 /workspace/coverage/default/2.edn_regwen.2024304494 Apr 21 01:34:54 PM PDT 24 Apr 21 01:34:56 PM PDT 24 18465092 ps
T809 /workspace/coverage/default/93.edn_err.129252274 Apr 21 01:37:48 PM PDT 24 Apr 21 01:37:49 PM PDT 24 32732224 ps
T810 /workspace/coverage/default/74.edn_err.1318003767 Apr 21 01:37:34 PM PDT 24 Apr 21 01:37:36 PM PDT 24 18420078 ps
T811 /workspace/coverage/default/5.edn_intr.3645240533 Apr 21 01:35:10 PM PDT 24 Apr 21 01:35:12 PM PDT 24 26769973 ps
T812 /workspace/coverage/default/25.edn_disable.4024387063 Apr 21 01:36:04 PM PDT 24 Apr 21 01:36:05 PM PDT 24 41115009 ps
T813 /workspace/coverage/default/75.edn_genbits.4119421980 Apr 21 01:37:35 PM PDT 24 Apr 21 01:37:36 PM PDT 24 74534432 ps
T814 /workspace/coverage/default/49.edn_stress_all.442839029 Apr 21 01:37:14 PM PDT 24 Apr 21 01:37:19 PM PDT 24 828250043 ps
T815 /workspace/coverage/default/151.edn_genbits.3214355166 Apr 21 01:38:03 PM PDT 24 Apr 21 01:38:05 PM PDT 24 250829900 ps
T816 /workspace/coverage/default/124.edn_genbits.2985443079 Apr 21 01:37:56 PM PDT 24 Apr 21 01:37:58 PM PDT 24 63816882 ps
T817 /workspace/coverage/default/25.edn_alert.3780638587 Apr 21 01:36:07 PM PDT 24 Apr 21 01:36:09 PM PDT 24 58721543 ps
T818 /workspace/coverage/default/20.edn_err.105568619 Apr 21 01:35:55 PM PDT 24 Apr 21 01:35:57 PM PDT 24 66926461 ps
T277 /workspace/coverage/default/85.edn_genbits.2290253385 Apr 21 01:37:41 PM PDT 24 Apr 21 01:37:43 PM PDT 24 40466386 ps
T819 /workspace/coverage/default/122.edn_genbits.2679129428 Apr 21 01:38:03 PM PDT 24 Apr 21 01:38:05 PM PDT 24 76500515 ps
T820 /workspace/coverage/default/214.edn_genbits.4125969059 Apr 21 01:38:25 PM PDT 24 Apr 21 01:38:27 PM PDT 24 71625222 ps
T821 /workspace/coverage/default/56.edn_err.274773146 Apr 21 01:37:25 PM PDT 24 Apr 21 01:37:26 PM PDT 24 29777831 ps
T822 /workspace/coverage/default/7.edn_genbits.2455752424 Apr 21 01:35:18 PM PDT 24 Apr 21 01:35:20 PM PDT 24 63363479 ps
T823 /workspace/coverage/default/8.edn_smoke.1031814333 Apr 21 01:35:20 PM PDT 24 Apr 21 01:35:21 PM PDT 24 26347208 ps
T824 /workspace/coverage/default/223.edn_genbits.1337049640 Apr 21 01:38:26 PM PDT 24 Apr 21 01:38:30 PM PDT 24 633571857 ps
T825 /workspace/coverage/default/84.edn_err.2463103516 Apr 21 01:37:39 PM PDT 24 Apr 21 01:37:41 PM PDT 24 23319307 ps
T826 /workspace/coverage/default/35.edn_intr.2032332540 Apr 21 01:36:34 PM PDT 24 Apr 21 01:36:35 PM PDT 24 19960566 ps
T827 /workspace/coverage/default/235.edn_genbits.2114728653 Apr 21 01:38:28 PM PDT 24 Apr 21 01:38:30 PM PDT 24 235443999 ps
T828 /workspace/coverage/default/17.edn_intr.3275412497 Apr 21 01:35:44 PM PDT 24 Apr 21 01:35:45 PM PDT 24 22692544 ps
T829 /workspace/coverage/default/280.edn_genbits.3538451535 Apr 21 01:38:42 PM PDT 24 Apr 21 01:38:44 PM PDT 24 115419450 ps
T830 /workspace/coverage/default/164.edn_genbits.2304298830 Apr 21 01:38:07 PM PDT 24 Apr 21 01:38:10 PM PDT 24 143702678 ps
T831 /workspace/coverage/default/6.edn_alert.966525874 Apr 21 01:35:15 PM PDT 24 Apr 21 01:35:16 PM PDT 24 95693604 ps
T832 /workspace/coverage/default/8.edn_disable_auto_req_mode.3769732530 Apr 21 01:35:19 PM PDT 24 Apr 21 01:35:20 PM PDT 24 51977275 ps
T833 /workspace/coverage/default/196.edn_genbits.3403889896 Apr 21 01:38:17 PM PDT 24 Apr 21 01:38:19 PM PDT 24 88180925 ps
T834 /workspace/coverage/default/33.edn_stress_all_with_rand_reset.4083424769 Apr 21 01:36:28 PM PDT 24 Apr 21 02:05:48 PM PDT 24 356578945582 ps
T835 /workspace/coverage/default/184.edn_genbits.3090861615 Apr 21 01:38:16 PM PDT 24 Apr 21 01:38:18 PM PDT 24 42865081 ps
T836 /workspace/coverage/cover_reg_top/28.edn_intr_test.2540693454 Apr 21 12:44:36 PM PDT 24 Apr 21 12:44:38 PM PDT 24 36874277 ps
T837 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1404528013 Apr 21 12:44:07 PM PDT 24 Apr 21 12:44:10 PM PDT 24 219462331 ps
T228 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2670887539 Apr 21 12:43:59 PM PDT 24 Apr 21 12:44:02 PM PDT 24 103286378 ps
T838 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4115489269 Apr 21 12:44:36 PM PDT 24 Apr 21 12:44:38 PM PDT 24 89444627 ps
T225 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3787724200 Apr 21 12:44:37 PM PDT 24 Apr 21 12:44:39 PM PDT 24 33618095 ps
T839 /workspace/coverage/cover_reg_top/11.edn_intr_test.3002759049 Apr 21 12:44:27 PM PDT 24 Apr 21 12:44:28 PM PDT 24 98483308 ps
T226 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1102207569 Apr 21 12:44:39 PM PDT 24 Apr 21 12:44:41 PM PDT 24 53426223 ps
T207 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1009525419 Apr 21 12:44:22 PM PDT 24 Apr 21 12:44:23 PM PDT 24 164004681 ps
T840 /workspace/coverage/cover_reg_top/34.edn_intr_test.3938646866 Apr 21 12:44:44 PM PDT 24 Apr 21 12:44:46 PM PDT 24 15832440 ps
T841 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3056772160 Apr 21 12:44:34 PM PDT 24 Apr 21 12:44:35 PM PDT 24 94089322 ps
T842 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3009637774 Apr 21 12:44:19 PM PDT 24 Apr 21 12:44:22 PM PDT 24 354450324 ps
T843 /workspace/coverage/cover_reg_top/1.edn_intr_test.624514559 Apr 21 12:44:10 PM PDT 24 Apr 21 12:44:12 PM PDT 24 11455540 ps
T844 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1105860401 Apr 21 12:44:33 PM PDT 24 Apr 21 12:44:34 PM PDT 24 19547394 ps
T845 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1572152986 Apr 21 12:44:41 PM PDT 24 Apr 21 12:44:42 PM PDT 24 49580310 ps
T846 /workspace/coverage/cover_reg_top/45.edn_intr_test.3659201072 Apr 21 12:44:23 PM PDT 24 Apr 21 12:44:24 PM PDT 24 21299633 ps
T847 /workspace/coverage/cover_reg_top/19.edn_tl_errors.142234956 Apr 21 12:44:34 PM PDT 24 Apr 21 12:44:37 PM PDT 24 51699033 ps
T208 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2636387407 Apr 21 12:44:15 PM PDT 24 Apr 21 12:44:17 PM PDT 24 68100037 ps
T848 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3148146623 Apr 21 12:44:25 PM PDT 24 Apr 21 12:44:27 PM PDT 24 141929207 ps
T849 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3848031437 Apr 21 12:44:11 PM PDT 24 Apr 21 12:44:13 PM PDT 24 16831244 ps
T227 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1640462946 Apr 21 12:44:22 PM PDT 24 Apr 21 12:44:24 PM PDT 24 35400995 ps
T229 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4268811427 Apr 21 12:44:05 PM PDT 24 Apr 21 12:44:08 PM PDT 24 453148994 ps
T850 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1992681634 Apr 21 12:44:08 PM PDT 24 Apr 21 12:44:15 PM PDT 24 944809874 ps
T851 /workspace/coverage/cover_reg_top/25.edn_intr_test.3118733481 Apr 21 12:44:43 PM PDT 24 Apr 21 12:44:45 PM PDT 24 36299143 ps
T852 /workspace/coverage/cover_reg_top/14.edn_tl_errors.4097002001 Apr 21 12:44:24 PM PDT 24 Apr 21 12:44:28 PM PDT 24 148573675 ps
T853 /workspace/coverage/cover_reg_top/30.edn_intr_test.3286850511 Apr 21 12:44:38 PM PDT 24 Apr 21 12:44:39 PM PDT 24 75473166 ps
T209 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1986933240 Apr 21 12:44:08 PM PDT 24 Apr 21 12:44:09 PM PDT 24 84012363 ps
T854 /workspace/coverage/cover_reg_top/13.edn_tl_errors.891859347 Apr 21 12:44:29 PM PDT 24 Apr 21 12:44:32 PM PDT 24 33794964 ps
T855 /workspace/coverage/cover_reg_top/20.edn_intr_test.820027860 Apr 21 12:44:29 PM PDT 24 Apr 21 12:44:30 PM PDT 24 38631721 ps
T856 /workspace/coverage/cover_reg_top/15.edn_intr_test.3788385886 Apr 21 12:44:26 PM PDT 24 Apr 21 12:44:27 PM PDT 24 12292677 ps
T857 /workspace/coverage/cover_reg_top/9.edn_intr_test.1669117333 Apr 21 12:44:25 PM PDT 24 Apr 21 12:44:26 PM PDT 24 12829625 ps
T210 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2480369180 Apr 21 12:44:14 PM PDT 24 Apr 21 12:44:15 PM PDT 24 132961418 ps
T230 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2312448976 Apr 21 12:44:14 PM PDT 24 Apr 21 12:44:16 PM PDT 24 147859182 ps
T858 /workspace/coverage/cover_reg_top/16.edn_intr_test.821044368 Apr 21 12:44:15 PM PDT 24 Apr 21 12:44:16 PM PDT 24 36174274 ps
T859 /workspace/coverage/cover_reg_top/6.edn_intr_test.1367928221 Apr 21 12:44:11 PM PDT 24 Apr 21 12:44:13 PM PDT 24 13509505 ps
T860 /workspace/coverage/cover_reg_top/44.edn_intr_test.3707273804 Apr 21 12:44:31 PM PDT 24 Apr 21 12:44:33 PM PDT 24 20742866 ps
T861 /workspace/coverage/cover_reg_top/19.edn_intr_test.2833547890 Apr 21 12:44:29 PM PDT 24 Apr 21 12:44:30 PM PDT 24 22945371 ps
T239 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3102708341 Apr 21 12:44:11 PM PDT 24 Apr 21 12:44:14 PM PDT 24 195727827 ps
T862 /workspace/coverage/cover_reg_top/37.edn_intr_test.3512301370 Apr 21 12:44:38 PM PDT 24 Apr 21 12:44:40 PM PDT 24 125208007 ps
T863 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1747168895 Apr 21 12:44:15 PM PDT 24 Apr 21 12:44:17 PM PDT 24 46658113 ps
T211 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3709837767 Apr 21 12:44:08 PM PDT 24 Apr 21 12:44:11 PM PDT 24 94739302 ps
T864 /workspace/coverage/cover_reg_top/24.edn_intr_test.170053840 Apr 21 12:44:14 PM PDT 24 Apr 21 12:44:16 PM PDT 24 40017185 ps
T212 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1133068976 Apr 21 12:44:54 PM PDT 24 Apr 21 12:44:56 PM PDT 24 57070386 ps
T865 /workspace/coverage/cover_reg_top/27.edn_intr_test.1481629718 Apr 21 12:44:38 PM PDT 24 Apr 21 12:44:40 PM PDT 24 31217498 ps
T866 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.4129459905 Apr 21 12:44:13 PM PDT 24 Apr 21 12:44:15 PM PDT 24 136538463 ps
T213 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3303328601 Apr 21 12:44:22 PM PDT 24 Apr 21 12:44:24 PM PDT 24 115277855 ps
T214 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2898761222 Apr 21 12:44:01 PM PDT 24 Apr 21 12:44:03 PM PDT 24 26067727 ps
T867 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3251780647 Apr 21 12:44:06 PM PDT 24 Apr 21 12:44:09 PM PDT 24 99747267 ps
T868 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2690257824 Apr 21 12:44:18 PM PDT 24 Apr 21 12:44:20 PM PDT 24 36690942 ps
T869 /workspace/coverage/cover_reg_top/31.edn_intr_test.3442058880 Apr 21 12:44:29 PM PDT 24 Apr 21 12:44:30 PM PDT 24 13133105 ps
T215 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2295242610 Apr 21 12:44:25 PM PDT 24 Apr 21 12:44:26 PM PDT 24 42825778 ps
T870 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1203261937 Apr 21 12:44:13 PM PDT 24 Apr 21 12:44:16 PM PDT 24 55073039 ps
T216 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1903868056 Apr 21 12:44:02 PM PDT 24 Apr 21 12:44:06 PM PDT 24 212815706 ps
T871 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.914063495 Apr 21 12:44:25 PM PDT 24 Apr 21 12:44:27 PM PDT 24 32909056 ps
T872 /workspace/coverage/cover_reg_top/29.edn_intr_test.487823717 Apr 21 12:44:44 PM PDT 24 Apr 21 12:44:46 PM PDT 24 158710731 ps
T873 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1056423110 Apr 21 12:44:51 PM PDT 24 Apr 21 12:44:52 PM PDT 24 65208960 ps
T240 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.646972326 Apr 21 12:44:13 PM PDT 24 Apr 21 12:44:17 PM PDT 24 104388063 ps
T874 /workspace/coverage/cover_reg_top/12.edn_csr_rw.3995772055 Apr 21 12:44:21 PM PDT 24 Apr 21 12:44:22 PM PDT 24 29583611 ps
T875 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2422478579 Apr 21 12:44:31 PM PDT 24 Apr 21 12:44:37 PM PDT 24 127111483 ps
T876 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3014145397 Apr 21 12:44:41 PM PDT 24 Apr 21 12:44:42 PM PDT 24 62096246 ps
T877 /workspace/coverage/cover_reg_top/40.edn_intr_test.2913321614 Apr 21 12:44:35 PM PDT 24 Apr 21 12:44:37 PM PDT 24 16985898 ps
T878 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3190318948 Apr 21 12:44:23 PM PDT 24 Apr 21 12:44:27 PM PDT 24 90674425 ps
T879 /workspace/coverage/cover_reg_top/5.edn_intr_test.2775833585 Apr 21 12:44:17 PM PDT 24 Apr 21 12:44:18 PM PDT 24 17950431 ps
T880 /workspace/coverage/cover_reg_top/16.edn_csr_rw.2113978595 Apr 21 12:44:37 PM PDT 24 Apr 21 12:44:38 PM PDT 24 89488912 ps
T217 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3871726737 Apr 21 12:44:10 PM PDT 24 Apr 21 12:44:12 PM PDT 24 81973174 ps
T881 /workspace/coverage/cover_reg_top/32.edn_intr_test.2114629733 Apr 21 12:44:32 PM PDT 24 Apr 21 12:44:33 PM PDT 24 18499008 ps
T882 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.147810568 Apr 21 12:44:09 PM PDT 24 Apr 21 12:44:11 PM PDT 24 28791606 ps
T883 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2204867940 Apr 21 12:44:05 PM PDT 24 Apr 21 12:44:07 PM PDT 24 48754233 ps
T884 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3872561269 Apr 21 12:44:00 PM PDT 24 Apr 21 12:44:02 PM PDT 24 170996786 ps
T885 /workspace/coverage/cover_reg_top/41.edn_intr_test.1923922306 Apr 21 12:44:38 PM PDT 24 Apr 21 12:44:40 PM PDT 24 23382319 ps
T886 /workspace/coverage/cover_reg_top/26.edn_intr_test.2211011004 Apr 21 12:44:29 PM PDT 24 Apr 21 12:44:30 PM PDT 24 27539645 ps
T887 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2489796315 Apr 21 12:44:03 PM PDT 24 Apr 21 12:44:05 PM PDT 24 63328527 ps
T888 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1075882054 Apr 21 12:44:20 PM PDT 24 Apr 21 12:44:23 PM PDT 24 106570175 ps
T218 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.306816942 Apr 21 12:44:19 PM PDT 24 Apr 21 12:44:20 PM PDT 24 49667476 ps
T889 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3834166164 Apr 21 12:44:12 PM PDT 24 Apr 21 12:44:14 PM PDT 24 135693773 ps
T890 /workspace/coverage/cover_reg_top/8.edn_csr_rw.4263656055 Apr 21 12:44:04 PM PDT 24 Apr 21 12:44:06 PM PDT 24 15069211 ps
T891 /workspace/coverage/cover_reg_top/3.edn_csr_rw.617163450 Apr 21 12:44:10 PM PDT 24 Apr 21 12:44:12 PM PDT 24 40644019 ps
T892 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3200372738 Apr 21 12:44:30 PM PDT 24 Apr 21 12:44:31 PM PDT 24 16279709 ps
T893 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2961258294 Apr 21 12:44:00 PM PDT 24 Apr 21 12:44:02 PM PDT 24 45670059 ps
T894 /workspace/coverage/cover_reg_top/1.edn_csr_rw.881748138 Apr 21 12:44:06 PM PDT 24 Apr 21 12:44:07 PM PDT 24 11120518 ps
T895 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2072167239 Apr 21 12:44:20 PM PDT 24 Apr 21 12:44:27 PM PDT 24 57855405 ps
T896 /workspace/coverage/cover_reg_top/14.edn_intr_test.3757669090 Apr 21 12:44:25 PM PDT 24 Apr 21 12:44:26 PM PDT 24 39670191 ps
T897 /workspace/coverage/cover_reg_top/36.edn_intr_test.1219821879 Apr 21 12:44:19 PM PDT 24 Apr 21 12:44:20 PM PDT 24 45144193 ps
T898 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2149354381 Apr 21 12:44:11 PM PDT 24 Apr 21 12:44:13 PM PDT 24 21637816 ps
T241 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2510057030 Apr 21 12:44:14 PM PDT 24 Apr 21 12:44:16 PM PDT 24 110832206 ps
T899 /workspace/coverage/cover_reg_top/21.edn_intr_test.1862838141 Apr 21 12:44:25 PM PDT 24 Apr 21 12:44:26 PM PDT 24 29488329 ps
T900 /workspace/coverage/cover_reg_top/17.edn_csr_rw.801716018 Apr 21 12:44:26 PM PDT 24 Apr 21 12:44:27 PM PDT 24 30916150 ps
T901 /workspace/coverage/cover_reg_top/33.edn_intr_test.953777391 Apr 21 12:44:38 PM PDT 24 Apr 21 12:44:40 PM PDT 24 21937992 ps
T902 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2794719899 Apr 21 12:44:03 PM PDT 24 Apr 21 12:44:05 PM PDT 24 78746828 ps
T903 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3507866313 Apr 21 12:44:05 PM PDT 24 Apr 21 12:44:09 PM PDT 24 229385094 ps
T904 /workspace/coverage/cover_reg_top/4.edn_intr_test.3731111951 Apr 21 12:44:02 PM PDT 24 Apr 21 12:44:04 PM PDT 24 15445244 ps
T905 /workspace/coverage/cover_reg_top/42.edn_intr_test.4266742018 Apr 21 12:44:53 PM PDT 24 Apr 21 12:44:54 PM PDT 24 113985327 ps
T906 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2881014540 Apr 21 12:44:22 PM PDT 24 Apr 21 12:44:24 PM PDT 24 72265615 ps
T907 /workspace/coverage/cover_reg_top/7.edn_intr_test.889273673 Apr 21 12:44:01 PM PDT 24 Apr 21 12:44:03 PM PDT 24 15651192 ps
T219 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3800433285 Apr 21 12:44:18 PM PDT 24 Apr 21 12:44:19 PM PDT 24 34339683 ps
T242 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1530585801 Apr 21 12:44:19 PM PDT 24 Apr 21 12:44:22 PM PDT 24 1356496446 ps
T908 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1479034075 Apr 21 12:44:23 PM PDT 24 Apr 21 12:44:25 PM PDT 24 45975096 ps
T909 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1468203301 Apr 21 12:44:08 PM PDT 24 Apr 21 12:44:13 PM PDT 24 940059038 ps
T220 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1332481578 Apr 21 12:44:24 PM PDT 24 Apr 21 12:44:25 PM PDT 24 32433930 ps
T221 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2666179340 Apr 21 12:44:02 PM PDT 24 Apr 21 12:44:04 PM PDT 24 80910068 ps
T910 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3076016286 Apr 21 12:44:18 PM PDT 24 Apr 21 12:44:20 PM PDT 24 121969621 ps
T911 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4192842086 Apr 21 12:44:08 PM PDT 24 Apr 21 12:44:09 PM PDT 24 93306498 ps
T912 /workspace/coverage/cover_reg_top/12.edn_intr_test.209381014 Apr 21 12:44:22 PM PDT 24 Apr 21 12:44:23 PM PDT 24 26080589 ps
T913 /workspace/coverage/cover_reg_top/18.edn_intr_test.3112942807 Apr 21 12:44:37 PM PDT 24 Apr 21 12:44:39 PM PDT 24 13765260 ps
T914 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1447470962 Apr 21 12:44:13 PM PDT 24 Apr 21 12:44:16 PM PDT 24 37473967 ps
T915 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2146466123 Apr 21 12:44:10 PM PDT 24 Apr 21 12:44:13 PM PDT 24 383416728 ps
T916 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3572971030 Apr 21 12:44:21 PM PDT 24 Apr 21 12:44:23 PM PDT 24 102906427 ps
T917 /workspace/coverage/cover_reg_top/43.edn_intr_test.606131981 Apr 21 12:44:35 PM PDT 24 Apr 21 12:44:37 PM PDT 24 50222169 ps
T918 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2641077022 Apr 21 12:44:15 PM PDT 24 Apr 21 12:44:17 PM PDT 24 63776770 ps
T919 /workspace/coverage/cover_reg_top/38.edn_intr_test.811896235 Apr 21 12:44:32 PM PDT 24 Apr 21 12:44:34 PM PDT 24 33286640 ps
T920 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1301716242 Apr 21 12:44:09 PM PDT 24 Apr 21 12:44:11 PM PDT 24 15931191 ps
T921 /workspace/coverage/cover_reg_top/22.edn_intr_test.1075808993 Apr 21 12:44:37 PM PDT 24 Apr 21 12:44:38 PM PDT 24 41101474 ps
T922 /workspace/coverage/cover_reg_top/0.edn_intr_test.2642144700 Apr 21 12:44:10 PM PDT 24 Apr 21 12:44:11 PM PDT 24 25545200 ps
T923 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1641103826 Apr 21 12:44:39 PM PDT 24 Apr 21 12:44:42 PM PDT 24 255878879 ps
T924 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1868385035 Apr 21 12:44:09 PM PDT 24 Apr 21 12:44:12 PM PDT 24 101283006 ps
T925 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2147635717 Apr 21 12:44:21 PM PDT 24 Apr 21 12:44:23 PM PDT 24 270942506 ps
T926 /workspace/coverage/cover_reg_top/8.edn_intr_test.142751658 Apr 21 12:44:09 PM PDT 24 Apr 21 12:44:10 PM PDT 24 20551826 ps
T927 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2104393840 Apr 21 12:44:28 PM PDT 24 Apr 21 12:44:30 PM PDT 24 57835608 ps
T928 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3739156700 Apr 21 12:43:59 PM PDT 24 Apr 21 12:44:00 PM PDT 24 28735517 ps
T929 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2591379735 Apr 21 12:44:25 PM PDT 24 Apr 21 12:44:26 PM PDT 24 19551284 ps
T930 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3020581194 Apr 21 12:44:27 PM PDT 24 Apr 21 12:44:30 PM PDT 24 334931137 ps
T931 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1790345431 Apr 21 12:44:22 PM PDT 24 Apr 21 12:44:24 PM PDT 24 29117435 ps
T932 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2382046182 Apr 21 12:44:39 PM PDT 24 Apr 21 12:44:41 PM PDT 24 105182391 ps
T933 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1479991030 Apr 21 12:44:07 PM PDT 24 Apr 21 12:44:08 PM PDT 24 37711081 ps
T236 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.304581781 Apr 21 12:44:06 PM PDT 24 Apr 21 12:44:09 PM PDT 24 101219270 ps
T934 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1500407116 Apr 21 12:44:07 PM PDT 24 Apr 21 12:44:12 PM PDT 24 248149559 ps
T935 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.655212456 Apr 21 12:44:00 PM PDT 24 Apr 21 12:44:04 PM PDT 24 180178671 ps
T936 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1704068369 Apr 21 12:44:22 PM PDT 24 Apr 21 12:44:24 PM PDT 24 82709099 ps
T937 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3200229337 Apr 21 12:43:58 PM PDT 24 Apr 21 12:44:00 PM PDT 24 106700291 ps
T938 /workspace/coverage/cover_reg_top/12.edn_tl_errors.2895245487 Apr 21 12:44:22 PM PDT 24 Apr 21 12:44:24 PM PDT 24 81518082 ps
T939 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.234117290 Apr 21 12:44:11 PM PDT 24 Apr 21 12:44:14 PM PDT 24 82266644 ps
T940 /workspace/coverage/cover_reg_top/10.edn_intr_test.3528839280 Apr 21 12:44:16 PM PDT 24 Apr 21 12:44:17 PM PDT 24 12950851 ps
T941 /workspace/coverage/cover_reg_top/23.edn_intr_test.111054667 Apr 21 12:44:41 PM PDT 24 Apr 21 12:44:42 PM PDT 24 26846008 ps
T942 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2734440546 Apr 21 12:44:12 PM PDT 24 Apr 21 12:44:14 PM PDT 24 31666284 ps
T943 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3690283888 Apr 21 12:44:09 PM PDT 24 Apr 21 12:44:12 PM PDT 24 88545634 ps
T944 /workspace/coverage/cover_reg_top/39.edn_intr_test.3101273037 Apr 21 12:44:42 PM PDT 24 Apr 21 12:44:44 PM PDT 24 138232756 ps
T945 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1655324725 Apr 21 12:44:32 PM PDT 24 Apr 21 12:44:34 PM PDT 24 11883799 ps
T946 /workspace/coverage/cover_reg_top/15.edn_tl_errors.3906206984 Apr 21 12:44:15 PM PDT 24 Apr 21 12:44:18 PM PDT 24 36103837 ps
T947 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1498618790 Apr 21 12:44:32 PM PDT 24 Apr 21 12:44:33 PM PDT 24 54309747 ps
T948 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3538094706 Apr 21 12:44:43 PM PDT 24 Apr 21 12:44:46 PM PDT 24 23749369 ps
T237 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.43462316 Apr 21 12:44:23 PM PDT 24 Apr 21 12:44:25 PM PDT 24 440627953 ps
T949 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1047908709 Apr 21 12:44:28 PM PDT 24 Apr 21 12:44:29 PM PDT 24 28203371 ps
T950 /workspace/coverage/cover_reg_top/49.edn_intr_test.921808283 Apr 21 12:44:32 PM PDT 24 Apr 21 12:44:34 PM PDT 24 26980045 ps
T951 /workspace/coverage/cover_reg_top/2.edn_intr_test.2014002603 Apr 21 12:43:59 PM PDT 24 Apr 21 12:44:01 PM PDT 24 22753725 ps
T952 /workspace/coverage/cover_reg_top/46.edn_intr_test.2138624225 Apr 21 12:44:42 PM PDT 24 Apr 21 12:44:43 PM PDT 24 15714163 ps
T953 /workspace/coverage/cover_reg_top/35.edn_intr_test.3718220247 Apr 21 12:44:48 PM PDT 24 Apr 21 12:44:49 PM PDT 24 14628189 ps
T954 /workspace/coverage/cover_reg_top/47.edn_intr_test.2423303949 Apr 21 12:44:29 PM PDT 24 Apr 21 12:44:31 PM PDT 24 25081583 ps
T955 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1580357078 Apr 21 12:44:31 PM PDT 24 Apr 21 12:44:34 PM PDT 24 298104399 ps
T956 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3559640361 Apr 21 12:44:05 PM PDT 24 Apr 21 12:44:07 PM PDT 24 60207990 ps
T957 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2282029745 Apr 21 12:44:25 PM PDT 24 Apr 21 12:44:29 PM PDT 24 187441107 ps
T958 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1888274986 Apr 21 12:44:18 PM PDT 24 Apr 21 12:44:21 PM PDT 24 173067739 ps
T222 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.341513472 Apr 21 12:44:09 PM PDT 24 Apr 21 12:44:10 PM PDT 24 21853451 ps
T959 /workspace/coverage/cover_reg_top/5.edn_tl_errors.934810613 Apr 21 12:44:14 PM PDT 24 Apr 21 12:44:17 PM PDT 24 83110088 ps
T960 /workspace/coverage/cover_reg_top/13.edn_intr_test.1751130063 Apr 21 12:44:27 PM PDT 24 Apr 21 12:44:28 PM PDT 24 33094873 ps
T238 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3076482887 Apr 21 12:44:24 PM PDT 24 Apr 21 12:44:26 PM PDT 24 54158601 ps
T961 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2843642520 Apr 21 12:44:11 PM PDT 24 Apr 21 12:44:14 PM PDT 24 135773017 ps
T223 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.603878720 Apr 21 12:44:13 PM PDT 24 Apr 21 12:44:14 PM PDT 24 17507102 ps
T962 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1050817612 Apr 21 12:44:16 PM PDT 24 Apr 21 12:44:20 PM PDT 24 89328364 ps
T963 /workspace/coverage/cover_reg_top/17.edn_intr_test.2914711518 Apr 21 12:44:13 PM PDT 24 Apr 21 12:44:15 PM PDT 24 14386073 ps
T964 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2057088448 Apr 21 12:44:22 PM PDT 24 Apr 21 12:44:23 PM PDT 24 20146793 ps
T965 /workspace/coverage/cover_reg_top/3.edn_intr_test.2848322727 Apr 21 12:44:08 PM PDT 24 Apr 21 12:44:10 PM PDT 24 20427549 ps
T966 /workspace/coverage/cover_reg_top/48.edn_intr_test.1802979483 Apr 21 12:44:45 PM PDT 24 Apr 21 12:44:46 PM PDT 24 41794296 ps
T967 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1320897323 Apr 21 12:44:19 PM PDT 24 Apr 21 12:44:20 PM PDT 24 33468699 ps
T968 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2746676829 Apr 21 12:44:31 PM PDT 24 Apr 21 12:44:33 PM PDT 24 18020157 ps
T969 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4058761265 Apr 21 12:44:15 PM PDT 24 Apr 21 12:44:17 PM PDT 24 38612546 ps
T224 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.235729419 Apr 21 12:44:12 PM PDT 24 Apr 21 12:44:13 PM PDT 24 26770793 ps

Test location /workspace/coverage/default/215.edn_genbits.1046505982
Short name T24
Test name
Test status
Simulation time 81953357 ps
CPU time 1.38 seconds
Started Apr 21 01:38:23 PM PDT 24
Finished Apr 21 01:38:25 PM PDT 24
Peak memory 218644 kb
Host smart-e6464f5e-bc76-4fb0-b3c1-b2ec7c72295e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046505982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1046505982
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1823915002
Short name T42
Test name
Test status
Simulation time 337395857049 ps
CPU time 1832.04 seconds
Started Apr 21 01:36:12 PM PDT 24
Finished Apr 21 02:06:44 PM PDT 24
Peak memory 225932 kb
Host smart-6d775f08-0c43-42db-a800-ad410125eba8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823915002 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1823915002
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2187503296
Short name T10
Test name
Test status
Simulation time 77665937 ps
CPU time 1.03 seconds
Started Apr 21 01:35:36 PM PDT 24
Finished Apr 21 01:35:38 PM PDT 24
Peak memory 217076 kb
Host smart-2caac942-bd49-4d5d-8625-6ee489ab032c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187503296 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2187503296
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_intr.1269203778
Short name T39
Test name
Test status
Simulation time 34617575 ps
CPU time 0.92 seconds
Started Apr 21 01:35:18 PM PDT 24
Finished Apr 21 01:35:19 PM PDT 24
Peak memory 215772 kb
Host smart-79fa36f0-387c-43e1-9227-d63b89ce4e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269203778 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1269203778
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3610442048
Short name T19
Test name
Test status
Simulation time 1843143495 ps
CPU time 7.96 seconds
Started Apr 21 01:34:55 PM PDT 24
Finished Apr 21 01:35:03 PM PDT 24
Peak memory 237100 kb
Host smart-4744ac1a-98e7-4cb3-9197-e3644277e58e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610442048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3610442048
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/19.edn_alert.977740666
Short name T56
Test name
Test status
Simulation time 30355746 ps
CPU time 1.3 seconds
Started Apr 21 01:35:50 PM PDT 24
Finished Apr 21 01:35:52 PM PDT 24
Peak memory 216064 kb
Host smart-6bcb5f0d-6b94-4a7c-bc68-1f67df2626d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977740666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.977740666
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.3216097148
Short name T93
Test name
Test status
Simulation time 67790109 ps
CPU time 2.21 seconds
Started Apr 21 01:38:05 PM PDT 24
Finished Apr 21 01:38:07 PM PDT 24
Peak memory 220032 kb
Host smart-7c8bbf95-bb63-486b-b128-fb5d3b018e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216097148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3216097148
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_disable.1006237170
Short name T84
Test name
Test status
Simulation time 20131150 ps
CPU time 0.89 seconds
Started Apr 21 01:36:09 PM PDT 24
Finished Apr 21 01:36:10 PM PDT 24
Peak memory 216768 kb
Host smart-58e4341a-4011-44ea-93d5-2c5f7ecb9bed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006237170 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1006237170
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/65.edn_err.4168361755
Short name T120
Test name
Test status
Simulation time 20528219 ps
CPU time 1.11 seconds
Started Apr 21 01:37:29 PM PDT 24
Finished Apr 21 01:37:30 PM PDT 24
Peak memory 224412 kb
Host smart-98037a5b-3c3d-467b-9d54-d5cef889ee31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168361755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.4168361755
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/18.edn_alert.1393075026
Short name T32
Test name
Test status
Simulation time 90018032 ps
CPU time 1.26 seconds
Started Apr 21 01:35:49 PM PDT 24
Finished Apr 21 01:35:50 PM PDT 24
Peak memory 216072 kb
Host smart-b9cfc9c7-b365-46f7-a09c-1edf3f1621e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393075026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1393075026
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/25.edn_err.145789598
Short name T16
Test name
Test status
Simulation time 24695677 ps
CPU time 1.03 seconds
Started Apr 21 01:36:09 PM PDT 24
Finished Apr 21 01:36:11 PM PDT 24
Peak memory 224356 kb
Host smart-375db2f9-d0c3-4482-9f14-1c5d58cd0cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145789598 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.145789598
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/49.edn_alert.1394812859
Short name T103
Test name
Test status
Simulation time 123370143 ps
CPU time 1.19 seconds
Started Apr 21 01:37:18 PM PDT 24
Finished Apr 21 01:37:20 PM PDT 24
Peak memory 216172 kb
Host smart-d8777ad1-1928-4448-a8f5-73aea457c6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394812859 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1394812859
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/0.edn_regwen.2953962687
Short name T28
Test name
Test status
Simulation time 21550620 ps
CPU time 0.89 seconds
Started Apr 21 01:34:46 PM PDT 24
Finished Apr 21 01:34:47 PM PDT 24
Peak memory 207424 kb
Host smart-57fc4a55-2f36-4962-8239-72a4f938a6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953962687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2953962687
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_alert.3693010299
Short name T142
Test name
Test status
Simulation time 22098527 ps
CPU time 1.13 seconds
Started Apr 21 01:35:15 PM PDT 24
Finished Apr 21 01:35:16 PM PDT 24
Peak memory 216136 kb
Host smart-96cd608a-d523-41d0-8ad5-cf6db81c6428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693010299 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3693010299
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.816788883
Short name T112
Test name
Test status
Simulation time 40450534 ps
CPU time 1.33 seconds
Started Apr 21 01:37:10 PM PDT 24
Finished Apr 21 01:37:12 PM PDT 24
Peak memory 217264 kb
Host smart-b4cf5d61-1922-4553-a684-9fd8245c227f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816788883 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.816788883
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1530585801
Short name T242
Test name
Test status
Simulation time 1356496446 ps
CPU time 2.67 seconds
Started Apr 21 12:44:19 PM PDT 24
Finished Apr 21 12:44:22 PM PDT 24
Peak memory 206420 kb
Host smart-11f0ddd3-8086-4aea-8232-06ed178b9624
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530585801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1530585801
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2636387407
Short name T208
Test name
Test status
Simulation time 68100037 ps
CPU time 0.81 seconds
Started Apr 21 12:44:15 PM PDT 24
Finished Apr 21 12:44:17 PM PDT 24
Peak memory 206032 kb
Host smart-b8eb43c0-a636-4fce-a84c-93290c5d9712
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636387407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2636387407
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.146579246
Short name T125
Test name
Test status
Simulation time 157695780 ps
CPU time 1.04 seconds
Started Apr 21 01:36:04 PM PDT 24
Finished Apr 21 01:36:05 PM PDT 24
Peak memory 217320 kb
Host smart-e4fb1435-f6cc-4b66-aa98-7372cdff2e4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146579246 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.146579246
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_disable.1459802818
Short name T193
Test name
Test status
Simulation time 118390886 ps
CPU time 0.77 seconds
Started Apr 21 01:36:34 PM PDT 24
Finished Apr 21 01:36:35 PM PDT 24
Peak memory 216592 kb
Host smart-3b1c0849-bd5a-4e80-ba2c-dfea26aa2970
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459802818 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1459802818
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable.283970446
Short name T151
Test name
Test status
Simulation time 13947906 ps
CPU time 0.92 seconds
Started Apr 21 01:37:17 PM PDT 24
Finished Apr 21 01:37:18 PM PDT 24
Peak memory 216828 kb
Host smart-85ab2eb7-65d9-40e7-a961-0965ec96a2a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283970446 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.283970446
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable.2374079090
Short name T169
Test name
Test status
Simulation time 14172306 ps
CPU time 0.9 seconds
Started Apr 21 01:36:25 PM PDT 24
Finished Apr 21 01:36:26 PM PDT 24
Peak memory 216820 kb
Host smart-7c849740-e0f3-40a0-9217-a8be8ef71500
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374079090 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2374079090
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2655116323
Short name T43
Test name
Test status
Simulation time 302006689238 ps
CPU time 1546.89 seconds
Started Apr 21 01:37:09 PM PDT 24
Finished Apr 21 02:02:56 PM PDT 24
Peak memory 224756 kb
Host smart-7d51fe04-21c4-4e6f-975f-6831dc98ee59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655116323 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2655116323
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.2982700684
Short name T127
Test name
Test status
Simulation time 31703954 ps
CPU time 1.08 seconds
Started Apr 21 01:35:33 PM PDT 24
Finished Apr 21 01:35:34 PM PDT 24
Peak memory 218440 kb
Host smart-f4b2aa1a-c408-461c-9657-8ebc6eebd297
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982700684 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.2982700684
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_intr.2831802416
Short name T36
Test name
Test status
Simulation time 34899222 ps
CPU time 0.81 seconds
Started Apr 21 01:36:36 PM PDT 24
Finished Apr 21 01:36:37 PM PDT 24
Peak memory 215956 kb
Host smart-2a12bd08-dfb0-4b8c-9192-2eaddd753067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831802416 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2831802416
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/57.edn_genbits.2740022795
Short name T289
Test name
Test status
Simulation time 67519191 ps
CPU time 1.33 seconds
Started Apr 21 01:37:25 PM PDT 24
Finished Apr 21 01:37:27 PM PDT 24
Peak memory 219776 kb
Host smart-03978760-0ba6-44ad-b3ac-74b88e597d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740022795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2740022795
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3027957861
Short name T259
Test name
Test status
Simulation time 38358880 ps
CPU time 1.16 seconds
Started Apr 21 01:36:03 PM PDT 24
Finished Apr 21 01:36:05 PM PDT 24
Peak memory 216052 kb
Host smart-52910f41-47ee-4b51-b972-a8754cd8c8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027957861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3027957861
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/0.edn_intr.1760057162
Short name T34
Test name
Test status
Simulation time 25165024 ps
CPU time 0.9 seconds
Started Apr 21 01:34:49 PM PDT 24
Finished Apr 21 01:34:50 PM PDT 24
Peak memory 216152 kb
Host smart-2a3b3661-f6cb-4779-8c60-5f57988889d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760057162 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1760057162
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/153.edn_genbits.2925182062
Short name T286
Test name
Test status
Simulation time 43832204 ps
CPU time 1.57 seconds
Started Apr 21 01:38:05 PM PDT 24
Finished Apr 21 01:38:07 PM PDT 24
Peak memory 220284 kb
Host smart-9042aeeb-52b6-45f2-abaa-acaaac43e787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925182062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2925182062
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3765748952
Short name T21
Test name
Test status
Simulation time 44062814 ps
CPU time 1.52 seconds
Started Apr 21 01:38:36 PM PDT 24
Finished Apr 21 01:38:38 PM PDT 24
Peak memory 218516 kb
Host smart-774642e3-2a25-4a31-8974-05871f6ee81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765748952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3765748952
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_regwen.2655776459
Short name T250
Test name
Test status
Simulation time 15007675 ps
CPU time 1.04 seconds
Started Apr 21 01:35:11 PM PDT 24
Finished Apr 21 01:35:12 PM PDT 24
Peak memory 207320 kb
Host smart-240f3133-003a-4980-aa95-4a8edff6b714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655776459 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2655776459
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/18.edn_disable.2235476636
Short name T690
Test name
Test status
Simulation time 42306753 ps
CPU time 0.86 seconds
Started Apr 21 01:35:51 PM PDT 24
Finished Apr 21 01:35:52 PM PDT 24
Peak memory 215840 kb
Host smart-9ea0d23f-c754-4cde-a330-29f037e11055
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235476636 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2235476636
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.895860205
Short name T14
Test name
Test status
Simulation time 40791088 ps
CPU time 1.24 seconds
Started Apr 21 01:35:55 PM PDT 24
Finished Apr 21 01:35:57 PM PDT 24
Peak memory 217148 kb
Host smart-2d64b773-78c2-48f5-81b7-96ccbc5dfff1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895860205 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.895860205
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1542190793
Short name T661
Test name
Test status
Simulation time 71524748 ps
CPU time 0.98 seconds
Started Apr 21 01:35:21 PM PDT 24
Finished Apr 21 01:35:22 PM PDT 24
Peak memory 217384 kb
Host smart-831ca373-ea57-400e-b84e-36dce13ffc36
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542190793 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1542190793
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.989924474
Short name T173
Test name
Test status
Simulation time 41103074 ps
CPU time 1.36 seconds
Started Apr 21 01:35:31 PM PDT 24
Finished Apr 21 01:35:33 PM PDT 24
Peak memory 217296 kb
Host smart-e025c4a4-3a67-4c4e-b80f-53961c51fbef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989924474 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.989924474
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.29432329
Short name T115
Test name
Test status
Simulation time 71539903 ps
CPU time 1.28 seconds
Started Apr 21 01:36:44 PM PDT 24
Finished Apr 21 01:36:45 PM PDT 24
Peak memory 217092 kb
Host smart-fdc8ade0-5381-4e11-83f4-f5f87206e384
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29432329 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_dis
able_auto_req_mode.29432329
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/158.edn_genbits.3557264852
Short name T12
Test name
Test status
Simulation time 22921695 ps
CPU time 1.18 seconds
Started Apr 21 01:38:06 PM PDT 24
Finished Apr 21 01:38:07 PM PDT 24
Peak memory 217592 kb
Host smart-2175031f-f9d0-4f1c-9793-5ca12ab4206b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557264852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3557264852
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.3269232086
Short name T299
Test name
Test status
Simulation time 27494714 ps
CPU time 0.91 seconds
Started Apr 21 01:35:29 PM PDT 24
Finished Apr 21 01:35:30 PM PDT 24
Peak memory 206884 kb
Host smart-776e8bfd-3148-4df7-add8-2f18ac415259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269232086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3269232086
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_alert.3231106376
Short name T33
Test name
Test status
Simulation time 26756309 ps
CPU time 1.19 seconds
Started Apr 21 01:36:45 PM PDT 24
Finished Apr 21 01:36:46 PM PDT 24
Peak memory 216076 kb
Host smart-f0e1a1b5-997a-44d3-8abe-c89772dce89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231106376 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3231106376
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/281.edn_genbits.799236135
Short name T89
Test name
Test status
Simulation time 42540644 ps
CPU time 1.16 seconds
Started Apr 21 01:38:41 PM PDT 24
Finished Apr 21 01:38:42 PM PDT 24
Peak memory 218668 kb
Host smart-016eb7f7-1a8f-44c1-8124-95575205fb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799236135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.799236135
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2666179340
Short name T221
Test name
Test status
Simulation time 80910068 ps
CPU time 1.59 seconds
Started Apr 21 12:44:02 PM PDT 24
Finished Apr 21 12:44:04 PM PDT 24
Peak memory 206468 kb
Host smart-fd7ca089-c793-428c-b0a6-73d5c489b708
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666179340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2666179340
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/default/42.edn_alert.26482744
Short name T189
Test name
Test status
Simulation time 24173795 ps
CPU time 1.15 seconds
Started Apr 21 01:36:59 PM PDT 24
Finished Apr 21 01:37:00 PM PDT 24
Peak memory 216068 kb
Host smart-f10c6f7d-f09b-44ae-a134-91dc392ae7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26482744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.26482744
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/46.edn_intr.2830414180
Short name T41
Test name
Test status
Simulation time 34365379 ps
CPU time 0.98 seconds
Started Apr 21 01:37:12 PM PDT 24
Finished Apr 21 01:37:13 PM PDT 24
Peak memory 216128 kb
Host smart-25f8bd14-c47b-44a3-8a1d-1ba11cdffd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830414180 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2830414180
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/187.edn_genbits.1266984535
Short name T54
Test name
Test status
Simulation time 44225657 ps
CPU time 1.23 seconds
Started Apr 21 01:38:17 PM PDT 24
Finished Apr 21 01:38:18 PM PDT 24
Peak memory 217216 kb
Host smart-3d7ae857-a3e6-4373-92ac-0c513a710b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266984535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1266984535
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_err.882694316
Short name T83
Test name
Test status
Simulation time 42951247 ps
CPU time 0.83 seconds
Started Apr 21 01:34:50 PM PDT 24
Finished Apr 21 01:34:51 PM PDT 24
Peak memory 218736 kb
Host smart-96f08e8a-aa1d-4e39-9fa8-a475f668be97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882694316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.882694316
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.304581781
Short name T236
Test name
Test status
Simulation time 101219270 ps
CPU time 2.42 seconds
Started Apr 21 12:44:06 PM PDT 24
Finished Apr 21 12:44:09 PM PDT 24
Peak memory 214428 kb
Host smart-707664a9-becd-4e4e-a81a-9efce6eee3ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304581781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.304581781
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2942265907
Short name T497
Test name
Test status
Simulation time 40581959 ps
CPU time 1.48 seconds
Started Apr 21 01:34:47 PM PDT 24
Finished Apr 21 01:34:48 PM PDT 24
Peak memory 218340 kb
Host smart-033c3e1d-5ee1-4f6f-aebb-ab29aa602ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942265907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2942265907
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_alert.1167733621
Short name T253
Test name
Test status
Simulation time 50834946 ps
CPU time 1.29 seconds
Started Apr 21 01:35:22 PM PDT 24
Finished Apr 21 01:35:24 PM PDT 24
Peak memory 216036 kb
Host smart-22f47543-6345-44a7-9b95-e4e3e6e2d4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167733621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1167733621
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_genbits.2004681196
Short name T47
Test name
Test status
Simulation time 42199347 ps
CPU time 1.61 seconds
Started Apr 21 01:35:23 PM PDT 24
Finished Apr 21 01:35:25 PM PDT 24
Peak memory 218592 kb
Host smart-6591eeaa-db68-4c77-9fc5-71fd2de0a163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004681196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2004681196
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_stress_all.95178676
Short name T341
Test name
Test status
Simulation time 508157954 ps
CPU time 3.76 seconds
Started Apr 21 01:35:21 PM PDT 24
Finished Apr 21 01:35:25 PM PDT 24
Peak memory 217288 kb
Host smart-e2280e81-89c4-4b14-ad45-f7394dab57a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95178676 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.95178676
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_alert.3376252794
Short name T392
Test name
Test status
Simulation time 25814878 ps
CPU time 1.19 seconds
Started Apr 21 01:35:25 PM PDT 24
Finished Apr 21 01:35:27 PM PDT 24
Peak memory 216064 kb
Host smart-1ba0d416-1f68-4f33-a90d-45b9d177152e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376252794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3376252794
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.2199085203
Short name T620
Test name
Test status
Simulation time 66591158 ps
CPU time 1 seconds
Started Apr 21 01:37:54 PM PDT 24
Finished Apr 21 01:37:55 PM PDT 24
Peak memory 217376 kb
Host smart-d30810fb-f81d-46cc-94b8-950fb5e7976d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199085203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2199085203
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_stress_all.3179844525
Short name T444
Test name
Test status
Simulation time 269607985 ps
CPU time 5.93 seconds
Started Apr 21 01:35:36 PM PDT 24
Finished Apr 21 01:35:42 PM PDT 24
Peak memory 217304 kb
Host smart-86719455-97dd-4804-964e-2b809e01f8f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179844525 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3179844525
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/147.edn_genbits.734877533
Short name T267
Test name
Test status
Simulation time 58930062 ps
CPU time 1.02 seconds
Started Apr 21 01:38:08 PM PDT 24
Finished Apr 21 01:38:09 PM PDT 24
Peak memory 218932 kb
Host smart-186d57a8-1eea-4afc-8e52-994a753b2168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734877533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.734877533
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3191945246
Short name T159
Test name
Test status
Simulation time 143952428 ps
CPU time 1.04 seconds
Started Apr 21 01:35:43 PM PDT 24
Finished Apr 21 01:35:44 PM PDT 24
Peak memory 215980 kb
Host smart-d59bed19-7103-4c61-8ba5-25f7eb9e4301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191945246 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3191945246
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.2660604644
Short name T271
Test name
Test status
Simulation time 30430111 ps
CPU time 1.32 seconds
Started Apr 21 01:38:13 PM PDT 24
Finished Apr 21 01:38:15 PM PDT 24
Peak memory 218784 kb
Host smart-364e7bfd-8e0c-4d16-a7f4-a92efc0c18ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660604644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2660604644
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_genbits.1304572351
Short name T283
Test name
Test status
Simulation time 54800356 ps
CPU time 1.54 seconds
Started Apr 21 01:36:41 PM PDT 24
Finished Apr 21 01:36:43 PM PDT 24
Peak memory 218572 kb
Host smart-383bb201-25da-410f-81ba-7999bcea1dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304572351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1304572351
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_genbits.3458310239
Short name T279
Test name
Test status
Simulation time 49312362 ps
CPU time 1.87 seconds
Started Apr 21 01:36:59 PM PDT 24
Finished Apr 21 01:37:02 PM PDT 24
Peak memory 220176 kb
Host smart-bd97a7d1-75e0-4c22-86ea-b53e51c5067f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458310239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3458310239
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_genbits.491421254
Short name T72
Test name
Test status
Simulation time 44929765 ps
CPU time 1.65 seconds
Started Apr 21 01:35:13 PM PDT 24
Finished Apr 21 01:35:15 PM PDT 24
Peak memory 219884 kb
Host smart-dff56c20-b7fd-45d3-8b49-b324b548df5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491421254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.491421254
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1486265829
Short name T38
Test name
Test status
Simulation time 20811680 ps
CPU time 1.07 seconds
Started Apr 21 01:35:57 PM PDT 24
Finished Apr 21 01:35:59 PM PDT 24
Peak memory 216132 kb
Host smart-f348d135-40e2-41b4-8fe6-b078fbf400e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486265829 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1486265829
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/12.edn_alert.981382952
Short name T246
Test name
Test status
Simulation time 77812408 ps
CPU time 1.14 seconds
Started Apr 21 01:35:32 PM PDT 24
Finished Apr 21 01:35:33 PM PDT 24
Peak memory 216076 kb
Host smart-1227fde9-9bcf-4c13-af26-80c9da94e8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981382952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.981382952
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/19.edn_disable.738951752
Short name T85
Test name
Test status
Simulation time 71371096 ps
CPU time 0.84 seconds
Started Apr 21 01:35:54 PM PDT 24
Finished Apr 21 01:35:55 PM PDT 24
Peak memory 216780 kb
Host smart-e68af54d-4355-4c38-8b5f-3f815b66e887
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738951752 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.738951752
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/111.edn_genbits.3540955813
Short name T766
Test name
Test status
Simulation time 55586810 ps
CPU time 1.25 seconds
Started Apr 21 01:37:56 PM PDT 24
Finished Apr 21 01:37:57 PM PDT 24
Peak memory 220192 kb
Host smart-39cffd0b-0688-42ad-8726-9e8b1c1fb8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540955813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3540955813
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.1526035629
Short name T680
Test name
Test status
Simulation time 56136784 ps
CPU time 1.55 seconds
Started Apr 21 01:38:14 PM PDT 24
Finished Apr 21 01:38:16 PM PDT 24
Peak memory 220272 kb
Host smart-26424b96-609f-4961-bd5b-dfaf5ca60ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526035629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1526035629
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.655212456
Short name T935
Test name
Test status
Simulation time 180178671 ps
CPU time 2.98 seconds
Started Apr 21 12:44:00 PM PDT 24
Finished Apr 21 12:44:04 PM PDT 24
Peak memory 206268 kb
Host smart-e5c7fb4a-13cb-4cd7-ac04-a75d0bc7d5d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655212456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.655212456
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4192842086
Short name T911
Test name
Test status
Simulation time 93306498 ps
CPU time 0.97 seconds
Started Apr 21 12:44:08 PM PDT 24
Finished Apr 21 12:44:09 PM PDT 24
Peak memory 206320 kb
Host smart-b51b709e-0b30-461b-b811-9fc6d1797a0f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192842086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.4192842086
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2104393840
Short name T927
Test name
Test status
Simulation time 57835608 ps
CPU time 1.44 seconds
Started Apr 21 12:44:28 PM PDT 24
Finished Apr 21 12:44:30 PM PDT 24
Peak memory 214544 kb
Host smart-2e0894a8-fb46-4b85-a1b3-7d7b22147e35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104393840 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2104393840
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2898761222
Short name T214
Test name
Test status
Simulation time 26067727 ps
CPU time 0.9 seconds
Started Apr 21 12:44:01 PM PDT 24
Finished Apr 21 12:44:03 PM PDT 24
Peak memory 206336 kb
Host smart-12653f8e-5222-4857-8f22-19ea2e4b8843
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898761222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2898761222
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2642144700
Short name T922
Test name
Test status
Simulation time 25545200 ps
CPU time 0.9 seconds
Started Apr 21 12:44:10 PM PDT 24
Finished Apr 21 12:44:11 PM PDT 24
Peak memory 206268 kb
Host smart-4b1bf65d-0df0-4e02-bc42-889dcbbade67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642144700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2642144700
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1986933240
Short name T209
Test name
Test status
Simulation time 84012363 ps
CPU time 1.09 seconds
Started Apr 21 12:44:08 PM PDT 24
Finished Apr 21 12:44:09 PM PDT 24
Peak memory 206244 kb
Host smart-69147c51-5caa-4d26-9d9e-5675bdf18ed1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986933240 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1986933240
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3009637774
Short name T842
Test name
Test status
Simulation time 354450324 ps
CPU time 3.5 seconds
Started Apr 21 12:44:19 PM PDT 24
Finished Apr 21 12:44:22 PM PDT 24
Peak memory 218440 kb
Host smart-fbd7e366-6a93-4b37-b8ff-21a587d2defb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009637774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3009637774
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.603878720
Short name T223
Test name
Test status
Simulation time 17507102 ps
CPU time 1.1 seconds
Started Apr 21 12:44:13 PM PDT 24
Finished Apr 21 12:44:14 PM PDT 24
Peak memory 206340 kb
Host smart-fa9c0d44-00b9-4eeb-b55f-bfced07997fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603878720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.603878720
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3507866313
Short name T903
Test name
Test status
Simulation time 229385094 ps
CPU time 3.1 seconds
Started Apr 21 12:44:05 PM PDT 24
Finished Apr 21 12:44:09 PM PDT 24
Peak memory 206348 kb
Host smart-add0319f-d75e-41ed-be99-21e32024bef4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507866313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3507866313
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.235729419
Short name T224
Test name
Test status
Simulation time 26770793 ps
CPU time 0.93 seconds
Started Apr 21 12:44:12 PM PDT 24
Finished Apr 21 12:44:13 PM PDT 24
Peak memory 206340 kb
Host smart-eb84a75b-a46b-49c3-8e24-c45c8c9859e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235729419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.235729419
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3572971030
Short name T916
Test name
Test status
Simulation time 102906427 ps
CPU time 1.34 seconds
Started Apr 21 12:44:21 PM PDT 24
Finished Apr 21 12:44:23 PM PDT 24
Peak memory 214604 kb
Host smart-a976b520-824b-44d8-99b2-b4e7648bf812
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572971030 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3572971030
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.881748138
Short name T894
Test name
Test status
Simulation time 11120518 ps
CPU time 0.87 seconds
Started Apr 21 12:44:06 PM PDT 24
Finished Apr 21 12:44:07 PM PDT 24
Peak memory 206256 kb
Host smart-65aff768-d4c3-4fcb-9da5-663df9ddc548
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881748138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.881748138
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.624514559
Short name T843
Test name
Test status
Simulation time 11455540 ps
CPU time 0.92 seconds
Started Apr 21 12:44:10 PM PDT 24
Finished Apr 21 12:44:12 PM PDT 24
Peak memory 206272 kb
Host smart-d191e3e6-3d71-4d1b-b4a2-24d8f6cd2b23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624514559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.624514559
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.914063495
Short name T871
Test name
Test status
Simulation time 32909056 ps
CPU time 1.14 seconds
Started Apr 21 12:44:25 PM PDT 24
Finished Apr 21 12:44:27 PM PDT 24
Peak memory 206392 kb
Host smart-f09d9c29-d17e-4ca0-aea1-1a0dbb799e45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914063495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.914063495
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1468203301
Short name T909
Test name
Test status
Simulation time 940059038 ps
CPU time 3.92 seconds
Started Apr 21 12:44:08 PM PDT 24
Finished Apr 21 12:44:13 PM PDT 24
Peak memory 214588 kb
Host smart-82577904-9bcc-4c69-956c-e785bf348894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468203301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1468203301
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1868385035
Short name T924
Test name
Test status
Simulation time 101283006 ps
CPU time 2.6 seconds
Started Apr 21 12:44:09 PM PDT 24
Finished Apr 21 12:44:12 PM PDT 24
Peak memory 206228 kb
Host smart-66c456a7-32ff-4bb1-a3db-266f7721ba8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868385035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1868385035
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4058761265
Short name T969
Test name
Test status
Simulation time 38612546 ps
CPU time 1.4 seconds
Started Apr 21 12:44:15 PM PDT 24
Finished Apr 21 12:44:17 PM PDT 24
Peak memory 214636 kb
Host smart-3dd0506a-85a7-472d-a41a-82cb6dfd8e80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058761265 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.4058761265
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3528839280
Short name T940
Test name
Test status
Simulation time 12950851 ps
CPU time 0.87 seconds
Started Apr 21 12:44:16 PM PDT 24
Finished Apr 21 12:44:17 PM PDT 24
Peak memory 206212 kb
Host smart-9ca8e6a1-da37-4579-8a4d-06b757bb7166
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528839280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3528839280
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3200372738
Short name T892
Test name
Test status
Simulation time 16279709 ps
CPU time 1.05 seconds
Started Apr 21 12:44:30 PM PDT 24
Finished Apr 21 12:44:31 PM PDT 24
Peak memory 206404 kb
Host smart-ded9a701-d8b7-4643-9b78-1fa9c9518ca1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200372738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3200372738
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1888274986
Short name T958
Test name
Test status
Simulation time 173067739 ps
CPU time 2.5 seconds
Started Apr 21 12:44:18 PM PDT 24
Finished Apr 21 12:44:21 PM PDT 24
Peak memory 214548 kb
Host smart-b08d087d-d8a7-418e-81fe-c5b7bd79d621
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888274986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1888274986
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2382046182
Short name T932
Test name
Test status
Simulation time 105182391 ps
CPU time 1.76 seconds
Started Apr 21 12:44:39 PM PDT 24
Finished Apr 21 12:44:41 PM PDT 24
Peak memory 206284 kb
Host smart-360195dd-e384-4189-ac04-239d194d7fa7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382046182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2382046182
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3148146623
Short name T848
Test name
Test status
Simulation time 141929207 ps
CPU time 1.02 seconds
Started Apr 21 12:44:25 PM PDT 24
Finished Apr 21 12:44:27 PM PDT 24
Peak memory 214580 kb
Host smart-0e702103-730b-4ad0-9727-1fc9b2b807d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148146623 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3148146623
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2057088448
Short name T964
Test name
Test status
Simulation time 20146793 ps
CPU time 0.88 seconds
Started Apr 21 12:44:22 PM PDT 24
Finished Apr 21 12:44:23 PM PDT 24
Peak memory 206280 kb
Host smart-ae8bc453-9e67-4282-9aeb-cec02c7a2e9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057088448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2057088448
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3002759049
Short name T839
Test name
Test status
Simulation time 98483308 ps
CPU time 0.95 seconds
Started Apr 21 12:44:27 PM PDT 24
Finished Apr 21 12:44:28 PM PDT 24
Peak memory 206212 kb
Host smart-5187ec74-27d1-41ad-901a-462f7e93accb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002759049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3002759049
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2746676829
Short name T968
Test name
Test status
Simulation time 18020157 ps
CPU time 1.16 seconds
Started Apr 21 12:44:31 PM PDT 24
Finished Apr 21 12:44:33 PM PDT 24
Peak memory 206272 kb
Host smart-2eeeda82-a590-4001-b60c-136d34019193
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746676829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2746676829
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1747168895
Short name T863
Test name
Test status
Simulation time 46658113 ps
CPU time 1.84 seconds
Started Apr 21 12:44:15 PM PDT 24
Finished Apr 21 12:44:17 PM PDT 24
Peak memory 214512 kb
Host smart-111a0f7e-acb9-4a6c-8bc8-2b3a0f6922a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747168895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1747168895
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2312448976
Short name T230
Test name
Test status
Simulation time 147859182 ps
CPU time 1.7 seconds
Started Apr 21 12:44:14 PM PDT 24
Finished Apr 21 12:44:16 PM PDT 24
Peak memory 214732 kb
Host smart-8d243f5c-7165-4c3b-a984-17484f84f329
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312448976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2312448976
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3014145397
Short name T876
Test name
Test status
Simulation time 62096246 ps
CPU time 1.15 seconds
Started Apr 21 12:44:41 PM PDT 24
Finished Apr 21 12:44:42 PM PDT 24
Peak memory 214588 kb
Host smart-a5cf6c62-0a71-4f45-ba16-99456357a68a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014145397 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3014145397
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3995772055
Short name T874
Test name
Test status
Simulation time 29583611 ps
CPU time 0.93 seconds
Started Apr 21 12:44:21 PM PDT 24
Finished Apr 21 12:44:22 PM PDT 24
Peak memory 206232 kb
Host smart-4daa603c-f5f5-4d5d-9e3b-48889567968a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995772055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3995772055
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.209381014
Short name T912
Test name
Test status
Simulation time 26080589 ps
CPU time 0.88 seconds
Started Apr 21 12:44:22 PM PDT 24
Finished Apr 21 12:44:23 PM PDT 24
Peak memory 206140 kb
Host smart-c71f278f-2f03-416c-841e-975d7883661f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209381014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.209381014
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1704068369
Short name T936
Test name
Test status
Simulation time 82709099 ps
CPU time 1.47 seconds
Started Apr 21 12:44:22 PM PDT 24
Finished Apr 21 12:44:24 PM PDT 24
Peak memory 206388 kb
Host smart-e786f49e-d83a-4d8e-8d03-d8d6bef27aa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704068369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1704068369
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2895245487
Short name T938
Test name
Test status
Simulation time 81518082 ps
CPU time 1.58 seconds
Started Apr 21 12:44:22 PM PDT 24
Finished Apr 21 12:44:24 PM PDT 24
Peak memory 214556 kb
Host smart-a8bff4ca-91d2-4934-9473-c54685cc01fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895245487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2895245487
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3834166164
Short name T889
Test name
Test status
Simulation time 135693773 ps
CPU time 1.64 seconds
Started Apr 21 12:44:12 PM PDT 24
Finished Apr 21 12:44:14 PM PDT 24
Peak memory 206336 kb
Host smart-f8ae1a0f-abd5-4e1f-9a3d-31936541eb77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834166164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3834166164
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3076016286
Short name T910
Test name
Test status
Simulation time 121969621 ps
CPU time 1.46 seconds
Started Apr 21 12:44:18 PM PDT 24
Finished Apr 21 12:44:20 PM PDT 24
Peak memory 214764 kb
Host smart-014e006d-5f8d-4543-8432-a2f9f63deaec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076016286 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3076016286
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1332481578
Short name T220
Test name
Test status
Simulation time 32433930 ps
CPU time 0.93 seconds
Started Apr 21 12:44:24 PM PDT 24
Finished Apr 21 12:44:25 PM PDT 24
Peak memory 206328 kb
Host smart-6ae0e586-c7fe-41da-8a1d-7420ca9d4e37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332481578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1332481578
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1751130063
Short name T960
Test name
Test status
Simulation time 33094873 ps
CPU time 0.81 seconds
Started Apr 21 12:44:27 PM PDT 24
Finished Apr 21 12:44:28 PM PDT 24
Peak memory 205976 kb
Host smart-12fbdf4b-4992-49b8-a55e-64faffce89da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751130063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1751130063
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2881014540
Short name T906
Test name
Test status
Simulation time 72265615 ps
CPU time 1.45 seconds
Started Apr 21 12:44:22 PM PDT 24
Finished Apr 21 12:44:24 PM PDT 24
Peak memory 206380 kb
Host smart-f8937d8f-871b-444a-8fb9-c5d23fc37b8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881014540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2881014540
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.891859347
Short name T854
Test name
Test status
Simulation time 33794964 ps
CPU time 2.4 seconds
Started Apr 21 12:44:29 PM PDT 24
Finished Apr 21 12:44:32 PM PDT 24
Peak memory 214644 kb
Host smart-b8217e59-bf42-4922-b662-86cccfc46bc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891859347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.891859347
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1641103826
Short name T923
Test name
Test status
Simulation time 255878879 ps
CPU time 2.11 seconds
Started Apr 21 12:44:39 PM PDT 24
Finished Apr 21 12:44:42 PM PDT 24
Peak memory 206572 kb
Host smart-36a52486-94f3-4a71-81e5-b474eb323b2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641103826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1641103826
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2147635717
Short name T925
Test name
Test status
Simulation time 270942506 ps
CPU time 1.64 seconds
Started Apr 21 12:44:21 PM PDT 24
Finished Apr 21 12:44:23 PM PDT 24
Peak memory 214512 kb
Host smart-86ff0710-5074-4a27-90ef-5a4b520d07e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147635717 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2147635717
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1047908709
Short name T949
Test name
Test status
Simulation time 28203371 ps
CPU time 0.86 seconds
Started Apr 21 12:44:28 PM PDT 24
Finished Apr 21 12:44:29 PM PDT 24
Peak memory 206252 kb
Host smart-bc2d11f2-2e28-4836-ad9f-41ac37d151e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047908709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1047908709
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3757669090
Short name T896
Test name
Test status
Simulation time 39670191 ps
CPU time 0.86 seconds
Started Apr 21 12:44:25 PM PDT 24
Finished Apr 21 12:44:26 PM PDT 24
Peak memory 206188 kb
Host smart-6e20b4a3-eaa8-4906-9653-f71587a000c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757669090 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3757669090
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3303328601
Short name T213
Test name
Test status
Simulation time 115277855 ps
CPU time 1.41 seconds
Started Apr 21 12:44:22 PM PDT 24
Finished Apr 21 12:44:24 PM PDT 24
Peak memory 206296 kb
Host smart-d51f42d7-dba5-4fc9-b8d1-2c53826f39b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303328601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3303328601
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.4097002001
Short name T852
Test name
Test status
Simulation time 148573675 ps
CPU time 3 seconds
Started Apr 21 12:44:24 PM PDT 24
Finished Apr 21 12:44:28 PM PDT 24
Peak memory 214548 kb
Host smart-e0dd8012-ec20-4e97-9305-6bfaa36ba443
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097002001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.4097002001
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.646972326
Short name T240
Test name
Test status
Simulation time 104388063 ps
CPU time 2.67 seconds
Started Apr 21 12:44:13 PM PDT 24
Finished Apr 21 12:44:17 PM PDT 24
Peak memory 206344 kb
Host smart-593fd1b3-c0a2-44a6-aadc-07b2e32831e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646972326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.646972326
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1572152986
Short name T845
Test name
Test status
Simulation time 49580310 ps
CPU time 0.98 seconds
Started Apr 21 12:44:41 PM PDT 24
Finished Apr 21 12:44:42 PM PDT 24
Peak memory 206320 kb
Host smart-d1df341b-86f4-4428-aaad-8692bf230939
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572152986 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1572152986
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2295242610
Short name T215
Test name
Test status
Simulation time 42825778 ps
CPU time 0.87 seconds
Started Apr 21 12:44:25 PM PDT 24
Finished Apr 21 12:44:26 PM PDT 24
Peak memory 206096 kb
Host smart-b3d936fd-229c-465c-88c1-4c9cd86ae7a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295242610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2295242610
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3788385886
Short name T856
Test name
Test status
Simulation time 12292677 ps
CPU time 0.84 seconds
Started Apr 21 12:44:26 PM PDT 24
Finished Apr 21 12:44:27 PM PDT 24
Peak memory 206160 kb
Host smart-83b786cd-9100-4611-b0d6-9f2d65763d55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788385886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3788385886
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1102207569
Short name T226
Test name
Test status
Simulation time 53426223 ps
CPU time 1.08 seconds
Started Apr 21 12:44:39 PM PDT 24
Finished Apr 21 12:44:41 PM PDT 24
Peak memory 206356 kb
Host smart-c09e5c13-5726-428c-8f17-6ffb6863e2fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102207569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1102207569
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3906206984
Short name T946
Test name
Test status
Simulation time 36103837 ps
CPU time 2.48 seconds
Started Apr 21 12:44:15 PM PDT 24
Finished Apr 21 12:44:18 PM PDT 24
Peak memory 218396 kb
Host smart-a3530eea-466b-4267-ae8f-5323e26ff44a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906206984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3906206984
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1498618790
Short name T947
Test name
Test status
Simulation time 54309747 ps
CPU time 1.14 seconds
Started Apr 21 12:44:32 PM PDT 24
Finished Apr 21 12:44:33 PM PDT 24
Peak memory 214604 kb
Host smart-52f8cbca-22ce-4b72-9567-a8f2cb892e1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498618790 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1498618790
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2113978595
Short name T880
Test name
Test status
Simulation time 89488912 ps
CPU time 0.9 seconds
Started Apr 21 12:44:37 PM PDT 24
Finished Apr 21 12:44:38 PM PDT 24
Peak memory 206032 kb
Host smart-19eb5390-32ca-453e-a64c-0eac720556d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113978595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2113978595
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.821044368
Short name T858
Test name
Test status
Simulation time 36174274 ps
CPU time 0.83 seconds
Started Apr 21 12:44:15 PM PDT 24
Finished Apr 21 12:44:16 PM PDT 24
Peak memory 206064 kb
Host smart-22592e21-3ad0-493a-b3d5-60284e8e9be7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821044368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.821044368
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2072167239
Short name T895
Test name
Test status
Simulation time 57855405 ps
CPU time 1.09 seconds
Started Apr 21 12:44:20 PM PDT 24
Finished Apr 21 12:44:27 PM PDT 24
Peak memory 206348 kb
Host smart-3368b192-92ef-4de6-8bd0-c17f1090a38f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072167239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2072167239
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1580357078
Short name T955
Test name
Test status
Simulation time 298104399 ps
CPU time 3.01 seconds
Started Apr 21 12:44:31 PM PDT 24
Finished Apr 21 12:44:34 PM PDT 24
Peak memory 214588 kb
Host smart-81cdf65f-8915-4054-83ed-19549aa5c3fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580357078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1580357078
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3020581194
Short name T930
Test name
Test status
Simulation time 334931137 ps
CPU time 2.34 seconds
Started Apr 21 12:44:27 PM PDT 24
Finished Apr 21 12:44:30 PM PDT 24
Peak memory 214520 kb
Host smart-f454bc8e-3231-47d7-beaf-a52270e75213
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020581194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3020581194
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3056772160
Short name T841
Test name
Test status
Simulation time 94089322 ps
CPU time 1.3 seconds
Started Apr 21 12:44:34 PM PDT 24
Finished Apr 21 12:44:35 PM PDT 24
Peak memory 217760 kb
Host smart-2105f6eb-5311-4d72-9d63-f447652035fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056772160 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3056772160
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.801716018
Short name T900
Test name
Test status
Simulation time 30916150 ps
CPU time 0.8 seconds
Started Apr 21 12:44:26 PM PDT 24
Finished Apr 21 12:44:27 PM PDT 24
Peak memory 206032 kb
Host smart-8ff61258-9ac5-4c40-97ff-4f5d27315ffa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801716018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.801716018
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2914711518
Short name T963
Test name
Test status
Simulation time 14386073 ps
CPU time 0.89 seconds
Started Apr 21 12:44:13 PM PDT 24
Finished Apr 21 12:44:15 PM PDT 24
Peak memory 206156 kb
Host smart-7aff6763-db27-4359-9162-c310e3285f9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914711518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2914711518
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3787724200
Short name T225
Test name
Test status
Simulation time 33618095 ps
CPU time 1.14 seconds
Started Apr 21 12:44:37 PM PDT 24
Finished Apr 21 12:44:39 PM PDT 24
Peak memory 206320 kb
Host smart-3c43b8f0-fdb9-4a69-9021-4cfd2e55ae7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787724200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3787724200
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2282029745
Short name T957
Test name
Test status
Simulation time 187441107 ps
CPU time 3.31 seconds
Started Apr 21 12:44:25 PM PDT 24
Finished Apr 21 12:44:29 PM PDT 24
Peak memory 214484 kb
Host smart-c04f681e-d9bd-4cdb-b1d9-f814c06d4988
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282029745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2282029745
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1479034075
Short name T908
Test name
Test status
Simulation time 45975096 ps
CPU time 1.56 seconds
Started Apr 21 12:44:23 PM PDT 24
Finished Apr 21 12:44:25 PM PDT 24
Peak memory 206352 kb
Host smart-9eaa59f6-1964-49e6-b7bb-5fa53de492ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479034075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1479034075
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2690257824
Short name T868
Test name
Test status
Simulation time 36690942 ps
CPU time 1.19 seconds
Started Apr 21 12:44:18 PM PDT 24
Finished Apr 21 12:44:20 PM PDT 24
Peak memory 214552 kb
Host smart-c4ef8055-58ae-4ebc-b61c-a4168eb2d7d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690257824 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2690257824
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1133068976
Short name T212
Test name
Test status
Simulation time 57070386 ps
CPU time 0.88 seconds
Started Apr 21 12:44:54 PM PDT 24
Finished Apr 21 12:44:56 PM PDT 24
Peak memory 206348 kb
Host smart-aa54a4ef-5d03-49bf-9fe2-aac9a8c02038
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133068976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1133068976
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3112942807
Short name T913
Test name
Test status
Simulation time 13765260 ps
CPU time 0.87 seconds
Started Apr 21 12:44:37 PM PDT 24
Finished Apr 21 12:44:39 PM PDT 24
Peak memory 206168 kb
Host smart-e1a1e297-fb99-4165-910d-ca633de252bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112942807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3112942807
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1640462946
Short name T227
Test name
Test status
Simulation time 35400995 ps
CPU time 1.36 seconds
Started Apr 21 12:44:22 PM PDT 24
Finished Apr 21 12:44:24 PM PDT 24
Peak memory 206288 kb
Host smart-612b304d-7dd8-41c4-b5c5-185016643dea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640462946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1640462946
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3190318948
Short name T878
Test name
Test status
Simulation time 90674425 ps
CPU time 3.26 seconds
Started Apr 21 12:44:23 PM PDT 24
Finished Apr 21 12:44:27 PM PDT 24
Peak memory 214392 kb
Host smart-a1694b81-e02a-4852-b771-e6fcef0e8b62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190318948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3190318948
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2510057030
Short name T241
Test name
Test status
Simulation time 110832206 ps
CPU time 1.82 seconds
Started Apr 21 12:44:14 PM PDT 24
Finished Apr 21 12:44:16 PM PDT 24
Peak memory 214448 kb
Host smart-6fe6726e-ba46-48fe-afb7-7580aa9576aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510057030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2510057030
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1105860401
Short name T844
Test name
Test status
Simulation time 19547394 ps
CPU time 1.12 seconds
Started Apr 21 12:44:33 PM PDT 24
Finished Apr 21 12:44:34 PM PDT 24
Peak memory 214600 kb
Host smart-b822ea9a-0a4a-43bb-8f24-5913fceca130
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105860401 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1105860401
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2591379735
Short name T929
Test name
Test status
Simulation time 19551284 ps
CPU time 0.85 seconds
Started Apr 21 12:44:25 PM PDT 24
Finished Apr 21 12:44:26 PM PDT 24
Peak memory 206108 kb
Host smart-7a58bdde-0877-4941-b1d4-043f8a51cf24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591379735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2591379735
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2833547890
Short name T861
Test name
Test status
Simulation time 22945371 ps
CPU time 0.87 seconds
Started Apr 21 12:44:29 PM PDT 24
Finished Apr 21 12:44:30 PM PDT 24
Peak memory 206180 kb
Host smart-c426bc5a-42e9-4f64-8281-5d173e903fa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833547890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2833547890
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3538094706
Short name T948
Test name
Test status
Simulation time 23749369 ps
CPU time 1.17 seconds
Started Apr 21 12:44:43 PM PDT 24
Finished Apr 21 12:44:46 PM PDT 24
Peak memory 206384 kb
Host smart-864aedce-788b-4f08-a0f3-d6ed15fb6725
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538094706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3538094706
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.142234956
Short name T847
Test name
Test status
Simulation time 51699033 ps
CPU time 2.1 seconds
Started Apr 21 12:44:34 PM PDT 24
Finished Apr 21 12:44:37 PM PDT 24
Peak memory 214544 kb
Host smart-9e46da6d-706b-4e4d-a6f2-b363bb2e3f8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142234956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.142234956
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3076482887
Short name T238
Test name
Test status
Simulation time 54158601 ps
CPU time 1.72 seconds
Started Apr 21 12:44:24 PM PDT 24
Finished Apr 21 12:44:26 PM PDT 24
Peak memory 206328 kb
Host smart-6d1dff06-9e1a-497b-a974-ac8ddc7a4158
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076482887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3076482887
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.147810568
Short name T882
Test name
Test status
Simulation time 28791606 ps
CPU time 1.05 seconds
Started Apr 21 12:44:09 PM PDT 24
Finished Apr 21 12:44:11 PM PDT 24
Peak memory 206292 kb
Host smart-36f71782-5456-4f0d-800c-0f6f012eaf67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147810568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.147810568
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3709837767
Short name T211
Test name
Test status
Simulation time 94739302 ps
CPU time 2.97 seconds
Started Apr 21 12:44:08 PM PDT 24
Finished Apr 21 12:44:11 PM PDT 24
Peak memory 206364 kb
Host smart-83fbf584-945c-47bf-bc95-c55dfa54a511
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709837767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3709837767
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.341513472
Short name T222
Test name
Test status
Simulation time 21853451 ps
CPU time 1.01 seconds
Started Apr 21 12:44:09 PM PDT 24
Finished Apr 21 12:44:10 PM PDT 24
Peak memory 206252 kb
Host smart-961dd4b9-899f-4514-ab5e-647c76a3b4cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341513472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.341513472
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3251780647
Short name T867
Test name
Test status
Simulation time 99747267 ps
CPU time 1.75 seconds
Started Apr 21 12:44:06 PM PDT 24
Finished Apr 21 12:44:09 PM PDT 24
Peak memory 214484 kb
Host smart-b1d48a6b-0f7d-4441-a1cc-bdec0e35c242
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251780647 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3251780647
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2961258294
Short name T893
Test name
Test status
Simulation time 45670059 ps
CPU time 0.85 seconds
Started Apr 21 12:44:00 PM PDT 24
Finished Apr 21 12:44:02 PM PDT 24
Peak memory 206252 kb
Host smart-ccf36fed-971a-45bb-b36b-d73b48cbe9b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961258294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2961258294
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2014002603
Short name T951
Test name
Test status
Simulation time 22753725 ps
CPU time 0.86 seconds
Started Apr 21 12:43:59 PM PDT 24
Finished Apr 21 12:44:01 PM PDT 24
Peak memory 206208 kb
Host smart-2dc8dcaa-ed87-4595-8b3f-377fc6673da2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014002603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2014002603
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2489796315
Short name T887
Test name
Test status
Simulation time 63328527 ps
CPU time 1.43 seconds
Started Apr 21 12:44:03 PM PDT 24
Finished Apr 21 12:44:05 PM PDT 24
Peak memory 206336 kb
Host smart-839f92c1-399c-45c5-8768-27146887bc55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489796315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2489796315
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1050817612
Short name T962
Test name
Test status
Simulation time 89328364 ps
CPU time 3.31 seconds
Started Apr 21 12:44:16 PM PDT 24
Finished Apr 21 12:44:20 PM PDT 24
Peak memory 214460 kb
Host smart-41c2bd3b-ac98-4f33-a990-d6e9ce5c8aba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050817612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1050817612
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3872561269
Short name T884
Test name
Test status
Simulation time 170996786 ps
CPU time 1.54 seconds
Started Apr 21 12:44:00 PM PDT 24
Finished Apr 21 12:44:02 PM PDT 24
Peak memory 214528 kb
Host smart-9e513126-269a-4baf-8c2f-f650c9c80293
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872561269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3872561269
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.820027860
Short name T855
Test name
Test status
Simulation time 38631721 ps
CPU time 0.95 seconds
Started Apr 21 12:44:29 PM PDT 24
Finished Apr 21 12:44:30 PM PDT 24
Peak memory 206164 kb
Host smart-6a79700f-d417-4e5a-9542-769b0924d9a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820027860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.820027860
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1862838141
Short name T899
Test name
Test status
Simulation time 29488329 ps
CPU time 0.85 seconds
Started Apr 21 12:44:25 PM PDT 24
Finished Apr 21 12:44:26 PM PDT 24
Peak memory 206280 kb
Host smart-efa3d4f1-190e-484b-b947-c5a067352ca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862838141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1862838141
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1075808993
Short name T921
Test name
Test status
Simulation time 41101474 ps
CPU time 0.81 seconds
Started Apr 21 12:44:37 PM PDT 24
Finished Apr 21 12:44:38 PM PDT 24
Peak memory 205976 kb
Host smart-afbf6873-f815-4daa-8c85-ba0e8c98814f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075808993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1075808993
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.111054667
Short name T941
Test name
Test status
Simulation time 26846008 ps
CPU time 0.86 seconds
Started Apr 21 12:44:41 PM PDT 24
Finished Apr 21 12:44:42 PM PDT 24
Peak memory 206152 kb
Host smart-121b50da-588c-406b-b150-a129edb80b41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111054667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.111054667
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.170053840
Short name T864
Test name
Test status
Simulation time 40017185 ps
CPU time 0.85 seconds
Started Apr 21 12:44:14 PM PDT 24
Finished Apr 21 12:44:16 PM PDT 24
Peak memory 206268 kb
Host smart-823ec527-0c02-4064-960e-1f4e8fbe6ea2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170053840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.170053840
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3118733481
Short name T851
Test name
Test status
Simulation time 36299143 ps
CPU time 0.85 seconds
Started Apr 21 12:44:43 PM PDT 24
Finished Apr 21 12:44:45 PM PDT 24
Peak memory 206144 kb
Host smart-f6c56934-8e68-4bd4-80bb-13867e72406c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118733481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3118733481
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2211011004
Short name T886
Test name
Test status
Simulation time 27539645 ps
CPU time 0.82 seconds
Started Apr 21 12:44:29 PM PDT 24
Finished Apr 21 12:44:30 PM PDT 24
Peak memory 205892 kb
Host smart-fffdbe03-e34b-45ec-a3d8-10dd4b42132b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211011004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2211011004
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1481629718
Short name T865
Test name
Test status
Simulation time 31217498 ps
CPU time 0.82 seconds
Started Apr 21 12:44:38 PM PDT 24
Finished Apr 21 12:44:40 PM PDT 24
Peak memory 206040 kb
Host smart-13579470-fe82-4759-9c09-8897792be47c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481629718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1481629718
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2540693454
Short name T836
Test name
Test status
Simulation time 36874277 ps
CPU time 0.83 seconds
Started Apr 21 12:44:36 PM PDT 24
Finished Apr 21 12:44:38 PM PDT 24
Peak memory 205972 kb
Host smart-7eacb00e-ba60-4699-b06d-cc1e85423a67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540693454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2540693454
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.487823717
Short name T872
Test name
Test status
Simulation time 158710731 ps
CPU time 0.93 seconds
Started Apr 21 12:44:44 PM PDT 24
Finished Apr 21 12:44:46 PM PDT 24
Peak memory 206184 kb
Host smart-0a462889-64ec-47fd-b917-7bfd0bf60865
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487823717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.487823717
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.234117290
Short name T939
Test name
Test status
Simulation time 82266644 ps
CPU time 1.71 seconds
Started Apr 21 12:44:11 PM PDT 24
Finished Apr 21 12:44:14 PM PDT 24
Peak memory 206240 kb
Host smart-f7840d3d-6980-4e84-b907-40751ca7cc1f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234117290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.234117290
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1903868056
Short name T216
Test name
Test status
Simulation time 212815706 ps
CPU time 3.19 seconds
Started Apr 21 12:44:02 PM PDT 24
Finished Apr 21 12:44:06 PM PDT 24
Peak memory 206340 kb
Host smart-6a7fe8fc-d250-423f-a6f1-53f29aa99451
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903868056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1903868056
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2149354381
Short name T898
Test name
Test status
Simulation time 21637816 ps
CPU time 0.9 seconds
Started Apr 21 12:44:11 PM PDT 24
Finished Apr 21 12:44:13 PM PDT 24
Peak memory 206256 kb
Host smart-5fbdd395-9308-4027-9f44-b253667ea351
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149354381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2149354381
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.4129459905
Short name T866
Test name
Test status
Simulation time 136538463 ps
CPU time 1.58 seconds
Started Apr 21 12:44:13 PM PDT 24
Finished Apr 21 12:44:15 PM PDT 24
Peak memory 214640 kb
Host smart-f7ff28e8-6e7d-4429-9894-a33e8437f3f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129459905 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.4129459905
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.617163450
Short name T891
Test name
Test status
Simulation time 40644019 ps
CPU time 0.91 seconds
Started Apr 21 12:44:10 PM PDT 24
Finished Apr 21 12:44:12 PM PDT 24
Peak memory 206244 kb
Host smart-4257a0f3-1326-4bc1-8d43-014a283deeaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617163450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.617163450
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2848322727
Short name T965
Test name
Test status
Simulation time 20427549 ps
CPU time 0.87 seconds
Started Apr 21 12:44:08 PM PDT 24
Finished Apr 21 12:44:10 PM PDT 24
Peak memory 206016 kb
Host smart-ec3dc12b-53b2-4616-adea-3673cea5cc00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848322727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2848322727
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3200229337
Short name T937
Test name
Test status
Simulation time 106700291 ps
CPU time 1.03 seconds
Started Apr 21 12:43:58 PM PDT 24
Finished Apr 21 12:44:00 PM PDT 24
Peak memory 206280 kb
Host smart-caea54a7-1d70-4a77-8c5a-0cd723432147
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200229337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3200229337
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1404528013
Short name T837
Test name
Test status
Simulation time 219462331 ps
CPU time 1.91 seconds
Started Apr 21 12:44:07 PM PDT 24
Finished Apr 21 12:44:10 PM PDT 24
Peak memory 214572 kb
Host smart-281b8043-9e84-4670-9dca-d9fbb6601dcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404528013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1404528013
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2843642520
Short name T961
Test name
Test status
Simulation time 135773017 ps
CPU time 2.11 seconds
Started Apr 21 12:44:11 PM PDT 24
Finished Apr 21 12:44:14 PM PDT 24
Peak memory 206236 kb
Host smart-d79e5dcf-1e7f-4c0a-8c94-6bddfc5429ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843642520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2843642520
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3286850511
Short name T853
Test name
Test status
Simulation time 75473166 ps
CPU time 0.88 seconds
Started Apr 21 12:44:38 PM PDT 24
Finished Apr 21 12:44:39 PM PDT 24
Peak memory 206308 kb
Host smart-43dc7172-680c-4f4a-8bec-7321b9349d06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286850511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3286850511
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3442058880
Short name T869
Test name
Test status
Simulation time 13133105 ps
CPU time 0.84 seconds
Started Apr 21 12:44:29 PM PDT 24
Finished Apr 21 12:44:30 PM PDT 24
Peak memory 206184 kb
Host smart-eb294321-d71e-4506-b6fd-ef17f1fbdfed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442058880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3442058880
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2114629733
Short name T881
Test name
Test status
Simulation time 18499008 ps
CPU time 0.83 seconds
Started Apr 21 12:44:32 PM PDT 24
Finished Apr 21 12:44:33 PM PDT 24
Peak memory 206168 kb
Host smart-8054a68f-7428-4930-88fe-188a1028ca9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114629733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2114629733
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.953777391
Short name T901
Test name
Test status
Simulation time 21937992 ps
CPU time 0.9 seconds
Started Apr 21 12:44:38 PM PDT 24
Finished Apr 21 12:44:40 PM PDT 24
Peak memory 206172 kb
Host smart-33d54baa-94bf-4d76-9fa4-2a9e6b0a7436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953777391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.953777391
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3938646866
Short name T840
Test name
Test status
Simulation time 15832440 ps
CPU time 0.94 seconds
Started Apr 21 12:44:44 PM PDT 24
Finished Apr 21 12:44:46 PM PDT 24
Peak memory 206308 kb
Host smart-3993509c-bf8e-420a-9662-ded9c928acb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938646866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3938646866
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3718220247
Short name T953
Test name
Test status
Simulation time 14628189 ps
CPU time 0.87 seconds
Started Apr 21 12:44:48 PM PDT 24
Finished Apr 21 12:44:49 PM PDT 24
Peak memory 206256 kb
Host smart-b74b4505-7912-433a-babe-79652ff26977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718220247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3718220247
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1219821879
Short name T897
Test name
Test status
Simulation time 45144193 ps
CPU time 0.84 seconds
Started Apr 21 12:44:19 PM PDT 24
Finished Apr 21 12:44:20 PM PDT 24
Peak memory 206432 kb
Host smart-f3446a57-b062-457d-bfbc-62e155288162
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219821879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1219821879
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3512301370
Short name T862
Test name
Test status
Simulation time 125208007 ps
CPU time 0.86 seconds
Started Apr 21 12:44:38 PM PDT 24
Finished Apr 21 12:44:40 PM PDT 24
Peak memory 206268 kb
Host smart-c16db0d7-a703-4bfd-a018-c96d5150578b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512301370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3512301370
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.811896235
Short name T919
Test name
Test status
Simulation time 33286640 ps
CPU time 0.88 seconds
Started Apr 21 12:44:32 PM PDT 24
Finished Apr 21 12:44:34 PM PDT 24
Peak memory 206180 kb
Host smart-90c80ae7-0a29-41bb-8f93-a283aee36802
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811896235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.811896235
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3101273037
Short name T944
Test name
Test status
Simulation time 138232756 ps
CPU time 0.82 seconds
Started Apr 21 12:44:42 PM PDT 24
Finished Apr 21 12:44:44 PM PDT 24
Peak memory 206192 kb
Host smart-7024b1a4-d526-488e-b190-b036f61cc423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101273037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3101273037
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3871726737
Short name T217
Test name
Test status
Simulation time 81973174 ps
CPU time 1.15 seconds
Started Apr 21 12:44:10 PM PDT 24
Finished Apr 21 12:44:12 PM PDT 24
Peak memory 206224 kb
Host smart-0198cfbe-aad7-4961-8277-c0fcd5a44e4c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871726737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3871726737
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1992681634
Short name T850
Test name
Test status
Simulation time 944809874 ps
CPU time 5.17 seconds
Started Apr 21 12:44:08 PM PDT 24
Finished Apr 21 12:44:15 PM PDT 24
Peak memory 206204 kb
Host smart-bd1f11d5-0b09-4559-9baa-7f21cfbdb351
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992681634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1992681634
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.306816942
Short name T218
Test name
Test status
Simulation time 49667476 ps
CPU time 0.9 seconds
Started Apr 21 12:44:19 PM PDT 24
Finished Apr 21 12:44:20 PM PDT 24
Peak memory 206236 kb
Host smart-bea8a7d1-a06a-4ca3-9880-934a6ea1f7f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306816942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.306816942
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3848031437
Short name T849
Test name
Test status
Simulation time 16831244 ps
CPU time 1.16 seconds
Started Apr 21 12:44:11 PM PDT 24
Finished Apr 21 12:44:13 PM PDT 24
Peak memory 214532 kb
Host smart-347f8903-3178-48db-bbad-53b916783798
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848031437 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3848031437
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3800433285
Short name T219
Test name
Test status
Simulation time 34339683 ps
CPU time 0.92 seconds
Started Apr 21 12:44:18 PM PDT 24
Finished Apr 21 12:44:19 PM PDT 24
Peak memory 206328 kb
Host smart-ad0c8ed3-a601-4a89-be03-3d3fbdbc0f9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800433285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3800433285
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3731111951
Short name T904
Test name
Test status
Simulation time 15445244 ps
CPU time 0.87 seconds
Started Apr 21 12:44:02 PM PDT 24
Finished Apr 21 12:44:04 PM PDT 24
Peak memory 206212 kb
Host smart-f42015e4-9263-4393-ae87-8cf7ddf6a947
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731111951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3731111951
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3559640361
Short name T956
Test name
Test status
Simulation time 60207990 ps
CPU time 1.31 seconds
Started Apr 21 12:44:05 PM PDT 24
Finished Apr 21 12:44:07 PM PDT 24
Peak memory 206316 kb
Host smart-14f71b6b-6bf1-43cd-a0e1-2396590366e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559640361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3559640361
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3690283888
Short name T943
Test name
Test status
Simulation time 88545634 ps
CPU time 2.06 seconds
Started Apr 21 12:44:09 PM PDT 24
Finished Apr 21 12:44:12 PM PDT 24
Peak memory 222776 kb
Host smart-bc715cb8-ab5c-4ec8-9021-6fe6767e0b98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690283888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3690283888
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2794719899
Short name T902
Test name
Test status
Simulation time 78746828 ps
CPU time 2.27 seconds
Started Apr 21 12:44:03 PM PDT 24
Finished Apr 21 12:44:05 PM PDT 24
Peak memory 206600 kb
Host smart-3c241e30-3d1d-4778-bb9e-5cdce4e57226
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794719899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2794719899
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2913321614
Short name T877
Test name
Test status
Simulation time 16985898 ps
CPU time 0.8 seconds
Started Apr 21 12:44:35 PM PDT 24
Finished Apr 21 12:44:37 PM PDT 24
Peak memory 205980 kb
Host smart-88892b02-bf7d-46f8-a808-82c851be5d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913321614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2913321614
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1923922306
Short name T885
Test name
Test status
Simulation time 23382319 ps
CPU time 0.87 seconds
Started Apr 21 12:44:38 PM PDT 24
Finished Apr 21 12:44:40 PM PDT 24
Peak memory 206216 kb
Host smart-72e95ff2-2f47-4c0a-8e90-82b2f860b7a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923922306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1923922306
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.4266742018
Short name T905
Test name
Test status
Simulation time 113985327 ps
CPU time 0.79 seconds
Started Apr 21 12:44:53 PM PDT 24
Finished Apr 21 12:44:54 PM PDT 24
Peak memory 206040 kb
Host smart-a2e31918-37aa-44ef-b84f-1e64a0f1a131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266742018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.4266742018
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.606131981
Short name T917
Test name
Test status
Simulation time 50222169 ps
CPU time 0.8 seconds
Started Apr 21 12:44:35 PM PDT 24
Finished Apr 21 12:44:37 PM PDT 24
Peak memory 206184 kb
Host smart-b65ad0e6-e9b9-4b4a-b024-bd63323389e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606131981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.606131981
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3707273804
Short name T860
Test name
Test status
Simulation time 20742866 ps
CPU time 0.99 seconds
Started Apr 21 12:44:31 PM PDT 24
Finished Apr 21 12:44:33 PM PDT 24
Peak memory 206268 kb
Host smart-3e18489d-cc8b-4105-ad12-e00e0a9538a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707273804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3707273804
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3659201072
Short name T846
Test name
Test status
Simulation time 21299633 ps
CPU time 0.78 seconds
Started Apr 21 12:44:23 PM PDT 24
Finished Apr 21 12:44:24 PM PDT 24
Peak memory 206044 kb
Host smart-0c460918-0496-4177-8b11-3d9c2cb37b1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659201072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3659201072
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2138624225
Short name T952
Test name
Test status
Simulation time 15714163 ps
CPU time 0.81 seconds
Started Apr 21 12:44:42 PM PDT 24
Finished Apr 21 12:44:43 PM PDT 24
Peak memory 206244 kb
Host smart-b0d38105-5b1b-45e8-804d-bb51108b152c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138624225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2138624225
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2423303949
Short name T954
Test name
Test status
Simulation time 25081583 ps
CPU time 0.84 seconds
Started Apr 21 12:44:29 PM PDT 24
Finished Apr 21 12:44:31 PM PDT 24
Peak memory 206176 kb
Host smart-1f75e120-2821-455d-bcc0-49fcb7863e4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423303949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2423303949
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1802979483
Short name T966
Test name
Test status
Simulation time 41794296 ps
CPU time 0.83 seconds
Started Apr 21 12:44:45 PM PDT 24
Finished Apr 21 12:44:46 PM PDT 24
Peak memory 206156 kb
Host smart-f2ea8f79-9072-41fe-83fd-0d13f5635644
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802979483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1802979483
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.921808283
Short name T950
Test name
Test status
Simulation time 26980045 ps
CPU time 0.79 seconds
Started Apr 21 12:44:32 PM PDT 24
Finished Apr 21 12:44:34 PM PDT 24
Peak memory 206060 kb
Host smart-db0cbc4d-fe95-4044-be76-36ff9cfd3fc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921808283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.921808283
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2422478579
Short name T875
Test name
Test status
Simulation time 127111483 ps
CPU time 1.05 seconds
Started Apr 21 12:44:31 PM PDT 24
Finished Apr 21 12:44:37 PM PDT 24
Peak memory 216188 kb
Host smart-47592790-52ab-41c8-9a04-90792d1dcfda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422478579 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2422478579
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3739156700
Short name T928
Test name
Test status
Simulation time 28735517 ps
CPU time 0.9 seconds
Started Apr 21 12:43:59 PM PDT 24
Finished Apr 21 12:44:00 PM PDT 24
Peak memory 206252 kb
Host smart-6a8bcdaa-8efa-4d3c-b710-5986dce0acf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739156700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3739156700
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2775833585
Short name T879
Test name
Test status
Simulation time 17950431 ps
CPU time 0.96 seconds
Started Apr 21 12:44:17 PM PDT 24
Finished Apr 21 12:44:18 PM PDT 24
Peak memory 206236 kb
Host smart-5bb44c83-cf85-40f0-af8c-5aa532e6396c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775833585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2775833585
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2734440546
Short name T942
Test name
Test status
Simulation time 31666284 ps
CPU time 1.3 seconds
Started Apr 21 12:44:12 PM PDT 24
Finished Apr 21 12:44:14 PM PDT 24
Peak memory 206312 kb
Host smart-ed58f2de-e880-411d-8f82-a607de0a8400
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734440546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2734440546
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.934810613
Short name T959
Test name
Test status
Simulation time 83110088 ps
CPU time 2.38 seconds
Started Apr 21 12:44:14 PM PDT 24
Finished Apr 21 12:44:17 PM PDT 24
Peak memory 214480 kb
Host smart-198aa3ad-5df4-42b2-9105-03a4ecccd297
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934810613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.934810613
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2670887539
Short name T228
Test name
Test status
Simulation time 103286378 ps
CPU time 1.61 seconds
Started Apr 21 12:43:59 PM PDT 24
Finished Apr 21 12:44:02 PM PDT 24
Peak memory 206316 kb
Host smart-e82a53ad-8c77-4c40-95a3-166ee4e1d7df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670887539 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2670887539
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1447470962
Short name T914
Test name
Test status
Simulation time 37473967 ps
CPU time 1.16 seconds
Started Apr 21 12:44:13 PM PDT 24
Finished Apr 21 12:44:16 PM PDT 24
Peak memory 217324 kb
Host smart-0ff11a99-101f-42b1-93d6-81e2680c0945
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447470962 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1447470962
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1479991030
Short name T933
Test name
Test status
Simulation time 37711081 ps
CPU time 0.88 seconds
Started Apr 21 12:44:07 PM PDT 24
Finished Apr 21 12:44:08 PM PDT 24
Peak memory 206284 kb
Host smart-bdd185be-a70c-47df-9bac-202322494794
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479991030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1479991030
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1367928221
Short name T859
Test name
Test status
Simulation time 13509505 ps
CPU time 0.9 seconds
Started Apr 21 12:44:11 PM PDT 24
Finished Apr 21 12:44:13 PM PDT 24
Peak memory 206180 kb
Host smart-367dc765-50ef-471c-bdf4-9453d7fa90b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367928221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1367928221
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1320897323
Short name T967
Test name
Test status
Simulation time 33468699 ps
CPU time 1.39 seconds
Started Apr 21 12:44:19 PM PDT 24
Finished Apr 21 12:44:20 PM PDT 24
Peak memory 206328 kb
Host smart-f68518f3-b75a-425e-a92c-8cdfdd0894c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320897323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1320897323
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1203261937
Short name T870
Test name
Test status
Simulation time 55073039 ps
CPU time 2.16 seconds
Started Apr 21 12:44:13 PM PDT 24
Finished Apr 21 12:44:16 PM PDT 24
Peak memory 214536 kb
Host smart-3423b654-e017-4451-824c-ebd09768a465
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203261937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1203261937
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3102708341
Short name T239
Test name
Test status
Simulation time 195727827 ps
CPU time 1.95 seconds
Started Apr 21 12:44:11 PM PDT 24
Finished Apr 21 12:44:14 PM PDT 24
Peak memory 214416 kb
Host smart-dab8f79e-e5e5-4c13-a835-47d41d1ad2b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102708341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3102708341
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1301716242
Short name T920
Test name
Test status
Simulation time 15931191 ps
CPU time 1.05 seconds
Started Apr 21 12:44:09 PM PDT 24
Finished Apr 21 12:44:11 PM PDT 24
Peak memory 214512 kb
Host smart-cb385c9c-04e7-4f00-93c6-e5d1d798b992
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301716242 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1301716242
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1655324725
Short name T945
Test name
Test status
Simulation time 11883799 ps
CPU time 0.92 seconds
Started Apr 21 12:44:32 PM PDT 24
Finished Apr 21 12:44:34 PM PDT 24
Peak memory 206320 kb
Host smart-841d9231-c47e-4998-ac0a-9efcbc989107
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655324725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1655324725
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.889273673
Short name T907
Test name
Test status
Simulation time 15651192 ps
CPU time 0.86 seconds
Started Apr 21 12:44:01 PM PDT 24
Finished Apr 21 12:44:03 PM PDT 24
Peak memory 206064 kb
Host smart-7958fe58-2f8d-480e-b0a5-b8b7f446b4eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889273673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.889273673
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1790345431
Short name T931
Test name
Test status
Simulation time 29117435 ps
CPU time 1.34 seconds
Started Apr 21 12:44:22 PM PDT 24
Finished Apr 21 12:44:24 PM PDT 24
Peak memory 206324 kb
Host smart-09edefe9-07ac-44c8-979b-3124516adbc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790345431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1790345431
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2641077022
Short name T918
Test name
Test status
Simulation time 63776770 ps
CPU time 1.3 seconds
Started Apr 21 12:44:15 PM PDT 24
Finished Apr 21 12:44:17 PM PDT 24
Peak memory 214600 kb
Host smart-b04aad22-16d4-44db-b6cf-06afe72bd0a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641077022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2641077022
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2146466123
Short name T915
Test name
Test status
Simulation time 383416728 ps
CPU time 2.5 seconds
Started Apr 21 12:44:10 PM PDT 24
Finished Apr 21 12:44:13 PM PDT 24
Peak memory 206308 kb
Host smart-e9f4c988-349f-4ecb-b265-d274fdb886db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146466123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2146466123
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1056423110
Short name T873
Test name
Test status
Simulation time 65208960 ps
CPU time 1.08 seconds
Started Apr 21 12:44:51 PM PDT 24
Finished Apr 21 12:44:52 PM PDT 24
Peak memory 214492 kb
Host smart-cf0713de-250e-498e-8c6d-5cf3e88534e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056423110 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1056423110
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.4263656055
Short name T890
Test name
Test status
Simulation time 15069211 ps
CPU time 1.02 seconds
Started Apr 21 12:44:04 PM PDT 24
Finished Apr 21 12:44:06 PM PDT 24
Peak memory 206320 kb
Host smart-c1e34bfd-af0d-460b-a9e8-b4c29479fff7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263656055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.4263656055
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.142751658
Short name T926
Test name
Test status
Simulation time 20551826 ps
CPU time 0.81 seconds
Started Apr 21 12:44:09 PM PDT 24
Finished Apr 21 12:44:10 PM PDT 24
Peak memory 205996 kb
Host smart-766bd346-68d5-449e-a747-9f24e40105a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142751658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.142751658
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2204867940
Short name T883
Test name
Test status
Simulation time 48754233 ps
CPU time 1.25 seconds
Started Apr 21 12:44:05 PM PDT 24
Finished Apr 21 12:44:07 PM PDT 24
Peak memory 206288 kb
Host smart-4b6c8a39-7158-49fc-b6d3-96579f62facb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204867940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2204867940
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1500407116
Short name T934
Test name
Test status
Simulation time 248149559 ps
CPU time 3.75 seconds
Started Apr 21 12:44:07 PM PDT 24
Finished Apr 21 12:44:12 PM PDT 24
Peak memory 214480 kb
Host smart-a109b52f-c350-42e5-afba-3db07826d007
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500407116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1500407116
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4268811427
Short name T229
Test name
Test status
Simulation time 453148994 ps
CPU time 1.73 seconds
Started Apr 21 12:44:05 PM PDT 24
Finished Apr 21 12:44:08 PM PDT 24
Peak memory 206328 kb
Host smart-f7b6691b-60b0-41f8-a191-da1da41ac4b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268811427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.4268811427
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4115489269
Short name T838
Test name
Test status
Simulation time 89444627 ps
CPU time 1.23 seconds
Started Apr 21 12:44:36 PM PDT 24
Finished Apr 21 12:44:38 PM PDT 24
Peak memory 214556 kb
Host smart-fd8ddba1-3df6-4c29-95ec-1901467454a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115489269 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.4115489269
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2480369180
Short name T210
Test name
Test status
Simulation time 132961418 ps
CPU time 0.82 seconds
Started Apr 21 12:44:14 PM PDT 24
Finished Apr 21 12:44:15 PM PDT 24
Peak memory 206124 kb
Host smart-7954e534-1897-4d8f-89f1-80bfef14f443
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480369180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2480369180
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1669117333
Short name T857
Test name
Test status
Simulation time 12829625 ps
CPU time 0.82 seconds
Started Apr 21 12:44:25 PM PDT 24
Finished Apr 21 12:44:26 PM PDT 24
Peak memory 205976 kb
Host smart-597e26b1-91b1-4c1e-b9ae-8e8cb1a550a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669117333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1669117333
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1009525419
Short name T207
Test name
Test status
Simulation time 164004681 ps
CPU time 1.15 seconds
Started Apr 21 12:44:22 PM PDT 24
Finished Apr 21 12:44:23 PM PDT 24
Peak memory 206264 kb
Host smart-77ecb2c4-2543-4672-827d-cba5c8c8e87f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009525419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1009525419
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1075882054
Short name T888
Test name
Test status
Simulation time 106570175 ps
CPU time 2.35 seconds
Started Apr 21 12:44:20 PM PDT 24
Finished Apr 21 12:44:23 PM PDT 24
Peak memory 214508 kb
Host smart-40a97211-83b4-4275-bfec-9d0b56921d33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075882054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1075882054
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.43462316
Short name T237
Test name
Test status
Simulation time 440627953 ps
CPU time 1.49 seconds
Started Apr 21 12:44:23 PM PDT 24
Finished Apr 21 12:44:25 PM PDT 24
Peak memory 206280 kb
Host smart-8fb26042-605c-448c-89ea-33e80911e89e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43462316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.43462316
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.2679002995
Short name T141
Test name
Test status
Simulation time 40601007 ps
CPU time 1.13 seconds
Started Apr 21 01:34:49 PM PDT 24
Finished Apr 21 01:34:50 PM PDT 24
Peak memory 216036 kb
Host smart-e1697c86-7922-4126-bddd-99b19bcefd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679002995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2679002995
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.1406470942
Short name T631
Test name
Test status
Simulation time 47872754 ps
CPU time 0.88 seconds
Started Apr 21 01:34:53 PM PDT 24
Finished Apr 21 01:34:54 PM PDT 24
Peak memory 206908 kb
Host smart-54681790-668f-4d20-9b1a-b17f529dab94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406470942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1406470942
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.2786162775
Short name T71
Test name
Test status
Simulation time 18569663 ps
CPU time 0.83 seconds
Started Apr 21 01:34:49 PM PDT 24
Finished Apr 21 01:34:50 PM PDT 24
Peak memory 216608 kb
Host smart-3d7d37f3-76a8-4778-8c87-a3f165057dc2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786162775 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2786162775
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2751400434
Short name T171
Test name
Test status
Simulation time 31873320 ps
CPU time 1.11 seconds
Started Apr 21 01:34:47 PM PDT 24
Finished Apr 21 01:34:48 PM PDT 24
Peak memory 219708 kb
Host smart-ef512109-33bb-40d0-82f1-75f508b44b69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751400434 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2751400434
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.2796574172
Short name T756
Test name
Test status
Simulation time 29993920 ps
CPU time 0.84 seconds
Started Apr 21 01:34:52 PM PDT 24
Finished Apr 21 01:34:54 PM PDT 24
Peak memory 218300 kb
Host smart-a2309760-016d-4816-9959-b38f79fce794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796574172 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2796574172
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1943344144
Short name T67
Test name
Test status
Simulation time 680513726 ps
CPU time 5.57 seconds
Started Apr 21 01:34:47 PM PDT 24
Finished Apr 21 01:34:53 PM PDT 24
Peak memory 235612 kb
Host smart-8577e1c6-d753-425f-9107-72994b361ee3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943344144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1943344144
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2298223104
Short name T301
Test name
Test status
Simulation time 42357066 ps
CPU time 0.86 seconds
Started Apr 21 01:34:44 PM PDT 24
Finished Apr 21 01:34:45 PM PDT 24
Peak memory 215808 kb
Host smart-39c2f8e2-0bf2-4980-9860-12cbb8b4fae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298223104 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2298223104
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1922469170
Short name T588
Test name
Test status
Simulation time 419538822 ps
CPU time 4.34 seconds
Started Apr 21 01:34:53 PM PDT 24
Finished Apr 21 01:34:57 PM PDT 24
Peak memory 217056 kb
Host smart-36edcc20-1192-4c6e-8032-302730b5f787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922469170 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1922469170
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3362012360
Short name T334
Test name
Test status
Simulation time 73125544770 ps
CPU time 926.77 seconds
Started Apr 21 01:34:51 PM PDT 24
Finished Apr 21 01:50:18 PM PDT 24
Peak memory 221476 kb
Host smart-010385a9-e768-4eb1-950e-67bd8daeb337
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362012360 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3362012360
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1339922795
Short name T188
Test name
Test status
Simulation time 81179500 ps
CPU time 1.28 seconds
Started Apr 21 01:34:50 PM PDT 24
Finished Apr 21 01:34:52 PM PDT 24
Peak memory 216072 kb
Host smart-625e93ef-cc46-4915-8dd7-7260736a0374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339922795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1339922795
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1927465862
Short name T336
Test name
Test status
Simulation time 12581757 ps
CPU time 0.89 seconds
Started Apr 21 01:34:50 PM PDT 24
Finished Apr 21 01:34:51 PM PDT 24
Peak memory 207432 kb
Host smart-43073fc0-a34d-478f-a5a6-43cae2a15bd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927465862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1927465862
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.3601127388
Short name T144
Test name
Test status
Simulation time 21354190 ps
CPU time 0.88 seconds
Started Apr 21 01:34:55 PM PDT 24
Finished Apr 21 01:34:56 PM PDT 24
Peak memory 216544 kb
Host smart-dc631843-d97c-4c81-8341-5fd59c689b00
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601127388 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3601127388
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2481375993
Short name T458
Test name
Test status
Simulation time 27286586 ps
CPU time 1.1 seconds
Started Apr 21 01:34:53 PM PDT 24
Finished Apr 21 01:34:55 PM PDT 24
Peak memory 218492 kb
Host smart-2c50208e-ff56-4a43-aedb-24c8994fa2fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481375993 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2481375993
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_genbits.1156381694
Short name T91
Test name
Test status
Simulation time 75789509 ps
CPU time 1.1 seconds
Started Apr 21 01:34:53 PM PDT 24
Finished Apr 21 01:34:54 PM PDT 24
Peak memory 215704 kb
Host smart-100795f9-30ee-4d26-a37d-f6e18b543186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156381694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1156381694
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1683498517
Short name T403
Test name
Test status
Simulation time 45366140 ps
CPU time 0.89 seconds
Started Apr 21 01:34:51 PM PDT 24
Finished Apr 21 01:34:52 PM PDT 24
Peak memory 215872 kb
Host smart-b1a52ac3-c6f5-4986-b6ee-aa5480044c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683498517 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1683498517
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.172199629
Short name T258
Test name
Test status
Simulation time 80772477 ps
CPU time 0.85 seconds
Started Apr 21 01:34:50 PM PDT 24
Finished Apr 21 01:34:51 PM PDT 24
Peak memory 207392 kb
Host smart-05948e2c-ece7-47c9-9007-2852bfc03f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172199629 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.172199629
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.3171051698
Short name T517
Test name
Test status
Simulation time 24074284 ps
CPU time 0.93 seconds
Started Apr 21 01:34:50 PM PDT 24
Finished Apr 21 01:34:51 PM PDT 24
Peak memory 215644 kb
Host smart-e866d077-24d4-4cd0-bcda-714bd6823ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171051698 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3171051698
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.410862796
Short name T379
Test name
Test status
Simulation time 263823119 ps
CPU time 5.29 seconds
Started Apr 21 01:34:54 PM PDT 24
Finished Apr 21 01:34:59 PM PDT 24
Peak memory 215736 kb
Host smart-deb3a9ea-e91b-4e3f-b1c7-f2510899f766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410862796 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.410862796
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.590529386
Short name T197
Test name
Test status
Simulation time 368757689901 ps
CPU time 1992.59 seconds
Started Apr 21 01:34:52 PM PDT 24
Finished Apr 21 02:08:05 PM PDT 24
Peak memory 226280 kb
Host smart-56860442-4914-4f0f-95c2-083240e77b19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590529386 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.590529386
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.2979756804
Short name T714
Test name
Test status
Simulation time 14578638 ps
CPU time 0.94 seconds
Started Apr 21 01:35:27 PM PDT 24
Finished Apr 21 01:35:28 PM PDT 24
Peak memory 215208 kb
Host smart-83d0bec2-fc18-4b2b-a586-6bcee734505a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979756804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2979756804
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.3686782396
Short name T751
Test name
Test status
Simulation time 37243580 ps
CPU time 0.86 seconds
Started Apr 21 01:35:22 PM PDT 24
Finished Apr 21 01:35:23 PM PDT 24
Peak memory 216796 kb
Host smart-7598ed0c-675a-4da9-b950-4e7f22737eb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686782396 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3686782396
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.304769902
Short name T385
Test name
Test status
Simulation time 24880907 ps
CPU time 0.93 seconds
Started Apr 21 01:35:25 PM PDT 24
Finished Apr 21 01:35:26 PM PDT 24
Peak memory 219168 kb
Host smart-30d4d370-9e07-4b32-bcab-eabc419cc2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304769902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.304769902
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_intr.1773598590
Short name T568
Test name
Test status
Simulation time 41066698 ps
CPU time 0.84 seconds
Started Apr 21 01:35:22 PM PDT 24
Finished Apr 21 01:35:23 PM PDT 24
Peak memory 215896 kb
Host smart-cf2780de-9a44-435c-8ff2-721d32a1753b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773598590 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1773598590
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1246751624
Short name T677
Test name
Test status
Simulation time 23171138 ps
CPU time 0.89 seconds
Started Apr 21 01:35:25 PM PDT 24
Finished Apr 21 01:35:26 PM PDT 24
Peak memory 215564 kb
Host smart-aa0368fa-89c0-46c2-bd44-09fb257baf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246751624 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1246751624
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.4244822545
Short name T763
Test name
Test status
Simulation time 31994532048 ps
CPU time 393.05 seconds
Started Apr 21 01:35:23 PM PDT 24
Finished Apr 21 01:41:56 PM PDT 24
Peak memory 218184 kb
Host smart-39f07051-ac35-44d1-b9db-8a2dff8370fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244822545 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.4244822545
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.1243363249
Short name T735
Test name
Test status
Simulation time 46307169 ps
CPU time 1.81 seconds
Started Apr 21 01:37:50 PM PDT 24
Finished Apr 21 01:37:52 PM PDT 24
Peak memory 219984 kb
Host smart-9215a4af-25df-4f03-b539-0ac0fde4a6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243363249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1243363249
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.277897095
Short name T601
Test name
Test status
Simulation time 189802811 ps
CPU time 2.67 seconds
Started Apr 21 01:37:49 PM PDT 24
Finished Apr 21 01:37:52 PM PDT 24
Peak memory 220196 kb
Host smart-a79ce981-50e7-4251-a6ff-4cebaff4b056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277897095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.277897095
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.3829489704
Short name T622
Test name
Test status
Simulation time 42066397 ps
CPU time 1.32 seconds
Started Apr 21 01:37:48 PM PDT 24
Finished Apr 21 01:37:50 PM PDT 24
Peak memory 218456 kb
Host smart-5cb58aa2-5926-4c58-91f0-622c6f3bc5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829489704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3829489704
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.35883119
Short name T542
Test name
Test status
Simulation time 63638531 ps
CPU time 1.47 seconds
Started Apr 21 01:37:48 PM PDT 24
Finished Apr 21 01:37:50 PM PDT 24
Peak memory 218456 kb
Host smart-66a5636a-edf2-4320-a3e8-12769be33093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35883119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.35883119
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.2972808334
Short name T682
Test name
Test status
Simulation time 73886694 ps
CPU time 1.07 seconds
Started Apr 21 01:37:49 PM PDT 24
Finished Apr 21 01:37:50 PM PDT 24
Peak memory 218904 kb
Host smart-390c571e-7567-4ac4-866d-f09b61ddadd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972808334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2972808334
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1111325623
Short name T626
Test name
Test status
Simulation time 211920210 ps
CPU time 1.07 seconds
Started Apr 21 01:37:50 PM PDT 24
Finished Apr 21 01:37:51 PM PDT 24
Peak memory 217340 kb
Host smart-1ed0e6d9-272a-41fa-96de-c49d5645ac34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111325623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1111325623
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.822764021
Short name T400
Test name
Test status
Simulation time 49610449 ps
CPU time 1.01 seconds
Started Apr 21 01:37:52 PM PDT 24
Finished Apr 21 01:37:53 PM PDT 24
Peak memory 217368 kb
Host smart-41406ccc-77f5-4b67-8c1a-55fadf5d8454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822764021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.822764021
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.75612970
Short name T653
Test name
Test status
Simulation time 32156967 ps
CPU time 1.49 seconds
Started Apr 21 01:37:53 PM PDT 24
Finished Apr 21 01:37:54 PM PDT 24
Peak memory 218436 kb
Host smart-05517b76-746d-46db-bfed-75278d73e6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75612970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.75612970
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.3782790982
Short name T694
Test name
Test status
Simulation time 59570920 ps
CPU time 1.42 seconds
Started Apr 21 01:37:52 PM PDT 24
Finished Apr 21 01:37:54 PM PDT 24
Peak memory 218684 kb
Host smart-297c7ee3-b5f9-4dee-aea0-84ddab9b2d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782790982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3782790982
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3976159151
Short name T535
Test name
Test status
Simulation time 32503050 ps
CPU time 1.41 seconds
Started Apr 21 01:37:55 PM PDT 24
Finished Apr 21 01:37:57 PM PDT 24
Peak memory 217536 kb
Host smart-95453293-422b-402f-8f2b-f71a3d05f343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976159151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3976159151
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.3754610075
Short name T592
Test name
Test status
Simulation time 90897223 ps
CPU time 0.95 seconds
Started Apr 21 01:35:26 PM PDT 24
Finished Apr 21 01:35:27 PM PDT 24
Peak memory 206984 kb
Host smart-a7483e9c-0028-4f5c-a6ae-3e64c845e619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754610075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3754610075
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.940118011
Short name T149
Test name
Test status
Simulation time 11277920 ps
CPU time 0.87 seconds
Started Apr 21 01:35:27 PM PDT 24
Finished Apr 21 01:35:28 PM PDT 24
Peak memory 216792 kb
Host smart-91005813-b456-443f-be53-7db380a82d79
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940118011 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.940118011
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.1440693626
Short name T693
Test name
Test status
Simulation time 30725302 ps
CPU time 0.95 seconds
Started Apr 21 01:35:25 PM PDT 24
Finished Apr 21 01:35:27 PM PDT 24
Peak memory 224196 kb
Host smart-0d72141a-e50e-44e6-bf73-f1bc9c979767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440693626 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1440693626
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.483836899
Short name T51
Test name
Test status
Simulation time 91256790 ps
CPU time 1.06 seconds
Started Apr 21 01:35:28 PM PDT 24
Finished Apr 21 01:35:29 PM PDT 24
Peak memory 217424 kb
Host smart-7d52c6a8-8d99-4f05-a248-8e3ee524d470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483836899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.483836899
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.2399088204
Short name T351
Test name
Test status
Simulation time 27499225 ps
CPU time 0.96 seconds
Started Apr 21 01:35:25 PM PDT 24
Finished Apr 21 01:35:26 PM PDT 24
Peak memory 215960 kb
Host smart-4ef1393c-0b60-4d49-b1e6-befcc2c47330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399088204 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2399088204
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1840783774
Short name T466
Test name
Test status
Simulation time 18304571 ps
CPU time 1.05 seconds
Started Apr 21 01:35:25 PM PDT 24
Finished Apr 21 01:35:27 PM PDT 24
Peak memory 215640 kb
Host smart-d1758924-2ed0-491b-be1a-53b765bd0293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840783774 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1840783774
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2170606167
Short name T807
Test name
Test status
Simulation time 1430690613 ps
CPU time 2.6 seconds
Started Apr 21 01:35:26 PM PDT 24
Finished Apr 21 01:35:29 PM PDT 24
Peak memory 217424 kb
Host smart-066558c6-e75a-4b14-91c7-48ccd2b9babc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170606167 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2170606167
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.4211309001
Short name T567
Test name
Test status
Simulation time 1331768602412 ps
CPU time 2101.36 seconds
Started Apr 21 01:35:27 PM PDT 24
Finished Apr 21 02:10:29 PM PDT 24
Peak memory 227884 kb
Host smart-41093c9b-a970-44dd-9a14-5798ec223115
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211309001 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.4211309001
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.2547656898
Short name T684
Test name
Test status
Simulation time 250830349 ps
CPU time 2.15 seconds
Started Apr 21 01:37:54 PM PDT 24
Finished Apr 21 01:37:57 PM PDT 24
Peak memory 218760 kb
Host smart-6cb7fcde-a995-4bff-a910-4fadfff3dc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547656898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2547656898
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.4169074823
Short name T544
Test name
Test status
Simulation time 306396281 ps
CPU time 1.56 seconds
Started Apr 21 01:37:50 PM PDT 24
Finished Apr 21 01:37:52 PM PDT 24
Peak memory 218856 kb
Host smart-69969a9a-baa2-4c1a-b477-993823aadfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169074823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.4169074823
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.313415674
Short name T759
Test name
Test status
Simulation time 54326040 ps
CPU time 1.19 seconds
Started Apr 21 01:37:53 PM PDT 24
Finished Apr 21 01:37:55 PM PDT 24
Peak memory 217436 kb
Host smart-27c2c3d8-9bd1-4697-9b4c-0becfe7528dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313415674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.313415674
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.1096102439
Short name T1
Test name
Test status
Simulation time 29142053 ps
CPU time 1.2 seconds
Started Apr 21 01:37:57 PM PDT 24
Finished Apr 21 01:37:58 PM PDT 24
Peak memory 218368 kb
Host smart-c2543fb8-ce39-4b1d-b756-1383c484f467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096102439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1096102439
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.557884489
Short name T739
Test name
Test status
Simulation time 121713756 ps
CPU time 1.35 seconds
Started Apr 21 01:37:54 PM PDT 24
Finished Apr 21 01:37:55 PM PDT 24
Peak memory 217464 kb
Host smart-d8c81943-c572-4d65-b445-dc5123518d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557884489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.557884489
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.2392503714
Short name T454
Test name
Test status
Simulation time 215048868 ps
CPU time 1.75 seconds
Started Apr 21 01:37:57 PM PDT 24
Finished Apr 21 01:37:59 PM PDT 24
Peak memory 219932 kb
Host smart-3bf6d339-a51e-41c1-80f2-f705daa5c7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392503714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2392503714
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.649436262
Short name T78
Test name
Test status
Simulation time 64103081 ps
CPU time 1.18 seconds
Started Apr 21 01:37:54 PM PDT 24
Finished Apr 21 01:37:56 PM PDT 24
Peak memory 217268 kb
Host smart-ca1d4755-48fc-4150-817f-99d92c5554ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649436262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.649436262
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.2773941104
Short name T427
Test name
Test status
Simulation time 88543993 ps
CPU time 1.03 seconds
Started Apr 21 01:37:56 PM PDT 24
Finished Apr 21 01:37:57 PM PDT 24
Peak memory 217324 kb
Host smart-307e6d8c-5631-4520-a532-41b97be507fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773941104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2773941104
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_disable.3557510605
Short name T143
Test name
Test status
Simulation time 16126850 ps
CPU time 0.82 seconds
Started Apr 21 01:35:28 PM PDT 24
Finished Apr 21 01:35:29 PM PDT 24
Peak memory 216772 kb
Host smart-484f72c0-2a78-433a-a406-77e4a23b466f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557510605 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3557510605
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.4136967077
Short name T576
Test name
Test status
Simulation time 30455973 ps
CPU time 1.31 seconds
Started Apr 21 01:35:32 PM PDT 24
Finished Apr 21 01:35:33 PM PDT 24
Peak memory 225932 kb
Host smart-6fe7ad6a-8422-4511-8213-d3889b6631f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136967077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.4136967077
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.533344432
Short name T673
Test name
Test status
Simulation time 75259702 ps
CPU time 1.59 seconds
Started Apr 21 01:35:31 PM PDT 24
Finished Apr 21 01:35:33 PM PDT 24
Peak memory 218716 kb
Host smart-071edc9a-9f19-4247-b5ad-e01b7af28729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533344432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.533344432
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1611359035
Short name T728
Test name
Test status
Simulation time 27087107 ps
CPU time 1.04 seconds
Started Apr 21 01:35:28 PM PDT 24
Finished Apr 21 01:35:30 PM PDT 24
Peak memory 224280 kb
Host smart-ac1b3b99-3023-4ffa-a692-4ca645df9f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611359035 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1611359035
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1665350457
Short name T484
Test name
Test status
Simulation time 33604365 ps
CPU time 0.88 seconds
Started Apr 21 01:35:28 PM PDT 24
Finished Apr 21 01:35:29 PM PDT 24
Peak memory 215608 kb
Host smart-c05dfdae-f907-478f-adb3-220418de811d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665350457 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1665350457
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2835082102
Short name T606
Test name
Test status
Simulation time 104352058 ps
CPU time 1.52 seconds
Started Apr 21 01:35:27 PM PDT 24
Finished Apr 21 01:35:29 PM PDT 24
Peak memory 217360 kb
Host smart-9de699e3-38d7-4432-b2ae-348f5da974bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835082102 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2835082102
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2683475776
Short name T530
Test name
Test status
Simulation time 69741334917 ps
CPU time 1277.91 seconds
Started Apr 21 01:35:33 PM PDT 24
Finished Apr 21 01:56:51 PM PDT 24
Peak memory 224496 kb
Host smart-298847c4-c692-40ee-8502-69db2315ca6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683475776 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2683475776
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.2743946251
Short name T95
Test name
Test status
Simulation time 55546353 ps
CPU time 1.68 seconds
Started Apr 21 01:37:57 PM PDT 24
Finished Apr 21 01:37:59 PM PDT 24
Peak memory 218416 kb
Host smart-c4276b78-0a98-4f0d-baae-5164783efc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743946251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2743946251
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.4156171454
Short name T485
Test name
Test status
Simulation time 56834631 ps
CPU time 1.07 seconds
Started Apr 21 01:38:09 PM PDT 24
Finished Apr 21 01:38:11 PM PDT 24
Peak memory 218976 kb
Host smart-9b248407-cac4-4449-a47b-d0cc5b7d1de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156171454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.4156171454
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.2679129428
Short name T819
Test name
Test status
Simulation time 76500515 ps
CPU time 1.66 seconds
Started Apr 21 01:38:03 PM PDT 24
Finished Apr 21 01:38:05 PM PDT 24
Peak memory 220052 kb
Host smart-1a844b6e-ba21-4058-99c4-e424c93421af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679129428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2679129428
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.815987502
Short name T101
Test name
Test status
Simulation time 137019544 ps
CPU time 3.21 seconds
Started Apr 21 01:37:58 PM PDT 24
Finished Apr 21 01:38:02 PM PDT 24
Peak memory 219916 kb
Host smart-021057f7-051e-4cd4-a504-2e32d0434bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815987502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.815987502
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.2985443079
Short name T816
Test name
Test status
Simulation time 63816882 ps
CPU time 1.37 seconds
Started Apr 21 01:37:56 PM PDT 24
Finished Apr 21 01:37:58 PM PDT 24
Peak memory 217212 kb
Host smart-da9eb94b-8a82-4b73-bc90-fa1ea564125e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985443079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2985443079
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.707158215
Short name T589
Test name
Test status
Simulation time 100488851 ps
CPU time 1.67 seconds
Started Apr 21 01:37:56 PM PDT 24
Finished Apr 21 01:37:58 PM PDT 24
Peak memory 218968 kb
Host smart-509601d1-98a4-4a26-82b1-cc13d00851fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707158215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.707158215
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1285196311
Short name T297
Test name
Test status
Simulation time 53095314 ps
CPU time 1.08 seconds
Started Apr 21 01:38:01 PM PDT 24
Finished Apr 21 01:38:03 PM PDT 24
Peak memory 219564 kb
Host smart-d70a5d2a-40ac-4d94-bef0-b475b72edb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285196311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1285196311
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.3794621103
Short name T644
Test name
Test status
Simulation time 209227729 ps
CPU time 2.86 seconds
Started Apr 21 01:37:56 PM PDT 24
Finished Apr 21 01:37:59 PM PDT 24
Peak memory 220160 kb
Host smart-4f75375e-f750-46f3-9f5b-788177fff615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794621103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3794621103
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.704019544
Short name T157
Test name
Test status
Simulation time 80575671 ps
CPU time 1.09 seconds
Started Apr 21 01:38:01 PM PDT 24
Finished Apr 21 01:38:02 PM PDT 24
Peak memory 217360 kb
Host smart-28042238-13fe-43cf-a58a-7cde93077647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704019544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.704019544
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2360627835
Short name T579
Test name
Test status
Simulation time 116248671 ps
CPU time 1.11 seconds
Started Apr 21 01:37:59 PM PDT 24
Finished Apr 21 01:38:00 PM PDT 24
Peak memory 219852 kb
Host smart-8cb2bfb1-b9b9-415d-8b0a-76d9cd7f53b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360627835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2360627835
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.34469033
Short name T110
Test name
Test status
Simulation time 29206717 ps
CPU time 1.28 seconds
Started Apr 21 01:35:32 PM PDT 24
Finished Apr 21 01:35:33 PM PDT 24
Peak memory 216144 kb
Host smart-0ed9fb67-67a4-4a59-bce3-18dfd86e618d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34469033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.34469033
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.1865914177
Short name T678
Test name
Test status
Simulation time 16691792 ps
CPU time 0.95 seconds
Started Apr 21 01:35:33 PM PDT 24
Finished Apr 21 01:35:35 PM PDT 24
Peak memory 206968 kb
Host smart-107ed931-23f1-42b1-91b5-e0146776d76d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865914177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1865914177
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.1267778614
Short name T405
Test name
Test status
Simulation time 13864108 ps
CPU time 0.92 seconds
Started Apr 21 01:35:32 PM PDT 24
Finished Apr 21 01:35:33 PM PDT 24
Peak memory 215996 kb
Host smart-eae315fb-112a-4845-8b5c-e6f595661572
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267778614 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1267778614
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1355480234
Short name T808
Test name
Test status
Simulation time 31204794 ps
CPU time 1.12 seconds
Started Apr 21 01:35:34 PM PDT 24
Finished Apr 21 01:35:35 PM PDT 24
Peak memory 219828 kb
Host smart-0102780a-82ff-48bc-a4b2-0fc83f6cbcf8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355480234 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1355480234
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2954649409
Short name T111
Test name
Test status
Simulation time 51151979 ps
CPU time 1.07 seconds
Started Apr 21 01:35:33 PM PDT 24
Finished Apr 21 01:35:34 PM PDT 24
Peak memory 229948 kb
Host smart-79f17094-972e-454a-a30d-0c1692afe39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954649409 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2954649409
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.981482156
Short name T3
Test name
Test status
Simulation time 59641311 ps
CPU time 1.72 seconds
Started Apr 21 01:35:29 PM PDT 24
Finished Apr 21 01:35:31 PM PDT 24
Peak memory 218456 kb
Host smart-406f6af6-a77b-4a70-a565-cdbc14117398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981482156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.981482156
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1233641856
Short name T536
Test name
Test status
Simulation time 24902133 ps
CPU time 1.06 seconds
Started Apr 21 01:35:32 PM PDT 24
Finished Apr 21 01:35:34 PM PDT 24
Peak memory 224404 kb
Host smart-6f977fa5-b6ec-4cdf-b7c4-ce71c6ac4edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233641856 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1233641856
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1930951464
Short name T343
Test name
Test status
Simulation time 26698808 ps
CPU time 0.93 seconds
Started Apr 21 01:35:31 PM PDT 24
Finished Apr 21 01:35:32 PM PDT 24
Peak memory 215624 kb
Host smart-ad0ab28a-ff34-4b05-aee2-8393a5c6e02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930951464 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1930951464
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3470250773
Short name T553
Test name
Test status
Simulation time 80637541 ps
CPU time 1.62 seconds
Started Apr 21 01:35:31 PM PDT 24
Finished Apr 21 01:35:33 PM PDT 24
Peak memory 217104 kb
Host smart-70df32e6-cb4a-4a88-b958-273d75538429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470250773 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3470250773
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1750330011
Short name T717
Test name
Test status
Simulation time 55117421569 ps
CPU time 1218.76 seconds
Started Apr 21 01:35:33 PM PDT 24
Finished Apr 21 01:55:52 PM PDT 24
Peak memory 220680 kb
Host smart-06d52465-4347-457c-bb53-332d54a2784b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750330011 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1750330011
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.4213858333
Short name T439
Test name
Test status
Simulation time 77785036 ps
CPU time 1.37 seconds
Started Apr 21 01:38:04 PM PDT 24
Finished Apr 21 01:38:06 PM PDT 24
Peak memory 219012 kb
Host smart-fe227249-efa9-4086-8c31-11e34139c635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213858333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.4213858333
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.1714991415
Short name T487
Test name
Test status
Simulation time 91060454 ps
CPU time 1.14 seconds
Started Apr 21 01:38:02 PM PDT 24
Finished Apr 21 01:38:03 PM PDT 24
Peak memory 217360 kb
Host smart-267ca161-312b-4491-8605-4a16e90b9581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714991415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1714991415
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1877071085
Short name T426
Test name
Test status
Simulation time 44643500 ps
CPU time 1.53 seconds
Started Apr 21 01:38:03 PM PDT 24
Finished Apr 21 01:38:05 PM PDT 24
Peak memory 218564 kb
Host smart-adcdaf35-1d09-48e2-96c7-194ec48310bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877071085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1877071085
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.2218409144
Short name T288
Test name
Test status
Simulation time 190817741 ps
CPU time 3.53 seconds
Started Apr 21 01:37:56 PM PDT 24
Finished Apr 21 01:38:00 PM PDT 24
Peak memory 220052 kb
Host smart-72aa5c9c-c938-4ae1-a8b4-df741b1ea70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218409144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2218409144
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.1621476934
Short name T774
Test name
Test status
Simulation time 193063536 ps
CPU time 1.03 seconds
Started Apr 21 01:37:58 PM PDT 24
Finished Apr 21 01:37:59 PM PDT 24
Peak memory 217260 kb
Host smart-850b27b2-b390-450e-9a36-330edec90376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621476934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1621476934
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.1940090207
Short name T373
Test name
Test status
Simulation time 32457598 ps
CPU time 1.26 seconds
Started Apr 21 01:38:01 PM PDT 24
Finished Apr 21 01:38:03 PM PDT 24
Peak memory 218724 kb
Host smart-a4d9f4b8-17cf-4d1a-ad4e-796e29548433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940090207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1940090207
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.3043209351
Short name T243
Test name
Test status
Simulation time 44246095 ps
CPU time 1.42 seconds
Started Apr 21 01:37:59 PM PDT 24
Finished Apr 21 01:38:00 PM PDT 24
Peak memory 218684 kb
Host smart-312ea804-5815-4dc3-883d-4170e44fd668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043209351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3043209351
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1108955921
Short name T672
Test name
Test status
Simulation time 98156267 ps
CPU time 1.2 seconds
Started Apr 21 01:38:02 PM PDT 24
Finished Apr 21 01:38:04 PM PDT 24
Peak memory 217196 kb
Host smart-ecfb49b2-44c0-46f8-8b63-98ae00eb9735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108955921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1108955921
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.852808945
Short name T417
Test name
Test status
Simulation time 55935840 ps
CPU time 1.94 seconds
Started Apr 21 01:37:59 PM PDT 24
Finished Apr 21 01:38:01 PM PDT 24
Peak memory 218520 kb
Host smart-773b35ab-264c-44c6-923e-4540bd8b44a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852808945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.852808945
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.3187978973
Short name T692
Test name
Test status
Simulation time 29811120 ps
CPU time 1.13 seconds
Started Apr 21 01:37:59 PM PDT 24
Finished Apr 21 01:38:00 PM PDT 24
Peak memory 219984 kb
Host smart-57539ae2-45ac-4a03-8bb4-aae3022af001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187978973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3187978973
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2039838336
Short name T252
Test name
Test status
Simulation time 121687695 ps
CPU time 1.26 seconds
Started Apr 21 01:35:34 PM PDT 24
Finished Apr 21 01:35:35 PM PDT 24
Peak memory 216072 kb
Host smart-00e10bd8-9dd3-4ab3-b35c-0d91fb3ff800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039838336 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2039838336
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3229329256
Short name T304
Test name
Test status
Simulation time 48588423 ps
CPU time 0.9 seconds
Started Apr 21 01:35:34 PM PDT 24
Finished Apr 21 01:35:35 PM PDT 24
Peak memory 206972 kb
Host smart-26b8ec10-7214-4871-8d2d-a436e6a028c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229329256 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3229329256
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1792397797
Short name T777
Test name
Test status
Simulation time 28896926 ps
CPU time 0.84 seconds
Started Apr 21 01:35:37 PM PDT 24
Finished Apr 21 01:35:38 PM PDT 24
Peak memory 216624 kb
Host smart-36b5b444-38c7-4a1d-b586-9763c8afaae3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792397797 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1792397797
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.615912645
Short name T60
Test name
Test status
Simulation time 36001458 ps
CPU time 1.17 seconds
Started Apr 21 01:35:34 PM PDT 24
Finished Apr 21 01:35:36 PM PDT 24
Peak memory 224368 kb
Host smart-04302fa4-d81d-4ba4-9723-30662aeea5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615912645 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.615912645
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3861127446
Short name T344
Test name
Test status
Simulation time 76438141 ps
CPU time 1.21 seconds
Started Apr 21 01:35:34 PM PDT 24
Finished Apr 21 01:35:36 PM PDT 24
Peak memory 215652 kb
Host smart-b471f192-7888-4e72-af23-6a3bda13e44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861127446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3861127446
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3794299794
Short name T321
Test name
Test status
Simulation time 29494975 ps
CPU time 0.95 seconds
Started Apr 21 01:35:39 PM PDT 24
Finished Apr 21 01:35:40 PM PDT 24
Peak memory 215920 kb
Host smart-ebdac1f5-df11-487b-b3c1-92d1d9390e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794299794 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3794299794
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.456604515
Short name T716
Test name
Test status
Simulation time 19341401 ps
CPU time 1.03 seconds
Started Apr 21 01:35:34 PM PDT 24
Finished Apr 21 01:35:35 PM PDT 24
Peak memory 215636 kb
Host smart-7b9e8609-dc39-405b-aea4-2d67b1342f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456604515 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.456604515
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.950777374
Short name T649
Test name
Test status
Simulation time 211105897071 ps
CPU time 1417.91 seconds
Started Apr 21 01:35:34 PM PDT 24
Finished Apr 21 01:59:13 PM PDT 24
Peak memory 226164 kb
Host smart-c5bac608-daad-4f04-b9f4-e7fd847b1116
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950777374 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.950777374
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.459529619
Short name T457
Test name
Test status
Simulation time 97785488 ps
CPU time 1.33 seconds
Started Apr 21 01:38:03 PM PDT 24
Finished Apr 21 01:38:04 PM PDT 24
Peak memory 218972 kb
Host smart-d888cb9c-d370-4fe2-871f-8109605b7839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459529619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.459529619
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.374945113
Short name T635
Test name
Test status
Simulation time 57531114 ps
CPU time 1.37 seconds
Started Apr 21 01:38:00 PM PDT 24
Finished Apr 21 01:38:02 PM PDT 24
Peak memory 218604 kb
Host smart-4a8c8978-fef2-43f4-9526-483f3b414ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374945113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.374945113
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.2285292064
Short name T706
Test name
Test status
Simulation time 34786717 ps
CPU time 1.27 seconds
Started Apr 21 01:38:01 PM PDT 24
Finished Apr 21 01:38:03 PM PDT 24
Peak memory 217228 kb
Host smart-98a92721-b384-4a48-afd1-3442b2a474d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285292064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2285292064
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.3234869319
Short name T531
Test name
Test status
Simulation time 42379933 ps
CPU time 1.24 seconds
Started Apr 21 01:38:03 PM PDT 24
Finished Apr 21 01:38:05 PM PDT 24
Peak memory 217280 kb
Host smart-bb28579d-e095-4b49-9b27-fc5aa1385f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234869319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3234869319
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1180962877
Short name T428
Test name
Test status
Simulation time 49503556 ps
CPU time 1.15 seconds
Started Apr 21 01:38:04 PM PDT 24
Finished Apr 21 01:38:06 PM PDT 24
Peak memory 218408 kb
Host smart-85ca6dad-a910-417e-b5f4-5f9735e5690f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180962877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1180962877
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.324854646
Short name T467
Test name
Test status
Simulation time 44530714 ps
CPU time 1.86 seconds
Started Apr 21 01:38:03 PM PDT 24
Finished Apr 21 01:38:05 PM PDT 24
Peak memory 218596 kb
Host smart-c7ea54dc-8143-468e-87c9-a721838c9d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324854646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.324854646
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.3665180524
Short name T371
Test name
Test status
Simulation time 108622041 ps
CPU time 1.3 seconds
Started Apr 21 01:38:04 PM PDT 24
Finished Apr 21 01:38:05 PM PDT 24
Peak memory 217256 kb
Host smart-e3663aad-684d-48f3-b767-254aca0c558f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665180524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3665180524
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.1953234021
Short name T551
Test name
Test status
Simulation time 46310461 ps
CPU time 1.08 seconds
Started Apr 21 01:38:02 PM PDT 24
Finished Apr 21 01:38:04 PM PDT 24
Peak memory 217348 kb
Host smart-0cff36cc-986b-482c-aadd-3c2f2e99c1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953234021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1953234021
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.3831221215
Short name T490
Test name
Test status
Simulation time 40368340 ps
CPU time 0.92 seconds
Started Apr 21 01:38:06 PM PDT 24
Finished Apr 21 01:38:07 PM PDT 24
Peak memory 217408 kb
Host smart-8d92c568-2be5-45e8-8235-70a0a2e9a38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831221215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3831221215
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3727089462
Short name T160
Test name
Test status
Simulation time 75543505 ps
CPU time 1.2 seconds
Started Apr 21 01:35:38 PM PDT 24
Finished Apr 21 01:35:39 PM PDT 24
Peak memory 216032 kb
Host smart-29063744-3faf-4102-9ff4-2eb5855ed63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727089462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3727089462
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3474649985
Short name T391
Test name
Test status
Simulation time 56773017 ps
CPU time 0.92 seconds
Started Apr 21 01:35:42 PM PDT 24
Finished Apr 21 01:35:43 PM PDT 24
Peak memory 215184 kb
Host smart-18d9ae2e-c40e-4b53-b5c8-5bb261589739
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474649985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3474649985
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.856399832
Short name T702
Test name
Test status
Simulation time 42226457 ps
CPU time 0.87 seconds
Started Apr 21 01:35:41 PM PDT 24
Finished Apr 21 01:35:42 PM PDT 24
Peak memory 216628 kb
Host smart-a170ef50-abdb-4938-9212-4346ca489e48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856399832 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.856399832
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2603166968
Short name T559
Test name
Test status
Simulation time 161323337 ps
CPU time 1.1 seconds
Started Apr 21 01:35:49 PM PDT 24
Finished Apr 21 01:35:51 PM PDT 24
Peak memory 217252 kb
Host smart-504a056c-4de0-43c1-afbb-4fd22b6f7148
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603166968 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2603166968
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.137600857
Short name T632
Test name
Test status
Simulation time 91324228 ps
CPU time 0.83 seconds
Started Apr 21 01:35:37 PM PDT 24
Finished Apr 21 01:35:38 PM PDT 24
Peak memory 218404 kb
Host smart-0f7044e7-1d3d-4d5c-9a2e-b0fe1d02b2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137600857 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.137600857
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2426832657
Short name T416
Test name
Test status
Simulation time 38639121 ps
CPU time 1.14 seconds
Started Apr 21 01:35:37 PM PDT 24
Finished Apr 21 01:35:39 PM PDT 24
Peak memory 219884 kb
Host smart-0a11551a-dcbe-4cd7-b086-8a6c1209f7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426832657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2426832657
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.398752454
Short name T480
Test name
Test status
Simulation time 35520087 ps
CPU time 0.81 seconds
Started Apr 21 01:35:38 PM PDT 24
Finished Apr 21 01:35:39 PM PDT 24
Peak memory 215752 kb
Host smart-55d4d9c1-759d-4a4f-9a27-df76063f664f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398752454 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.398752454
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2826994180
Short name T656
Test name
Test status
Simulation time 45051252 ps
CPU time 0.84 seconds
Started Apr 21 01:35:38 PM PDT 24
Finished Apr 21 01:35:39 PM PDT 24
Peak memory 215660 kb
Host smart-73ef8dbc-999e-4630-a219-9fb4c79130df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826994180 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2826994180
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.4032055246
Short name T164
Test name
Test status
Simulation time 119842413 ps
CPU time 1.33 seconds
Started Apr 21 01:35:40 PM PDT 24
Finished Apr 21 01:35:41 PM PDT 24
Peak memory 215708 kb
Host smart-1da5d4c0-0659-4ba4-9ba7-4db1b5e6b7c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032055246 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.4032055246
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2061333929
Short name T688
Test name
Test status
Simulation time 113781129013 ps
CPU time 1211.83 seconds
Started Apr 21 01:35:38 PM PDT 24
Finished Apr 21 01:55:50 PM PDT 24
Peak memory 223600 kb
Host smart-eca6f84b-8c7d-446f-824b-6bbe24d44421
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061333929 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2061333929
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.2497204763
Short name T577
Test name
Test status
Simulation time 38079005 ps
CPU time 1.37 seconds
Started Apr 21 01:38:02 PM PDT 24
Finished Apr 21 01:38:04 PM PDT 24
Peak memory 217448 kb
Host smart-8b5294cc-608b-4700-bdd2-347e12a1f5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497204763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2497204763
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.3214355166
Short name T815
Test name
Test status
Simulation time 250829900 ps
CPU time 1.62 seconds
Started Apr 21 01:38:03 PM PDT 24
Finished Apr 21 01:38:05 PM PDT 24
Peak memory 218696 kb
Host smart-1c0f764e-a43c-4d62-a21c-ac402060e62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214355166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3214355166
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.2911490697
Short name T364
Test name
Test status
Simulation time 62975637 ps
CPU time 1.06 seconds
Started Apr 21 01:38:03 PM PDT 24
Finished Apr 21 01:38:05 PM PDT 24
Peak memory 217228 kb
Host smart-55f3c291-339a-4049-a947-08f07e681ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911490697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2911490697
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.3112320669
Short name T97
Test name
Test status
Simulation time 59420281 ps
CPU time 1.4 seconds
Started Apr 21 01:38:05 PM PDT 24
Finished Apr 21 01:38:07 PM PDT 24
Peak memory 218552 kb
Host smart-83452c49-1b36-46c2-bbe0-4b5effc695d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112320669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3112320669
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.1207493409
Short name T328
Test name
Test status
Simulation time 66924531 ps
CPU time 1.33 seconds
Started Apr 21 01:38:08 PM PDT 24
Finished Apr 21 01:38:10 PM PDT 24
Peak memory 219100 kb
Host smart-f877e54d-c190-417e-830e-9b350e470297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207493409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1207493409
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.571462049
Short name T471
Test name
Test status
Simulation time 39341146 ps
CPU time 1.4 seconds
Started Apr 21 01:38:04 PM PDT 24
Finished Apr 21 01:38:06 PM PDT 24
Peak memory 217344 kb
Host smart-a2c461fa-da50-40ce-9c5e-d2cf39a574da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571462049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.571462049
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.2926280683
Short name T695
Test name
Test status
Simulation time 63892857 ps
CPU time 1.33 seconds
Started Apr 21 01:38:07 PM PDT 24
Finished Apr 21 01:38:08 PM PDT 24
Peak memory 218756 kb
Host smart-4e95bbc6-fc95-4483-a484-5580ff48ed53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926280683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2926280683
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.3124065048
Short name T474
Test name
Test status
Simulation time 75464614 ps
CPU time 1.49 seconds
Started Apr 21 01:38:08 PM PDT 24
Finished Apr 21 01:38:10 PM PDT 24
Peak memory 218492 kb
Host smart-a1a9404b-f667-4705-8f7e-ffbd784c2a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124065048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3124065048
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1173939976
Short name T709
Test name
Test status
Simulation time 108345403 ps
CPU time 1.24 seconds
Started Apr 21 01:35:40 PM PDT 24
Finished Apr 21 01:35:42 PM PDT 24
Peak memory 216052 kb
Host smart-87de0b03-09f3-4bc4-8812-e42bd7f04337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173939976 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1173939976
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2288260841
Short name T303
Test name
Test status
Simulation time 37488924 ps
CPU time 0.8 seconds
Started Apr 21 01:35:42 PM PDT 24
Finished Apr 21 01:35:43 PM PDT 24
Peak memory 215040 kb
Host smart-cae8d6e6-997b-426a-846a-fda419aed305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288260841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2288260841
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2796175839
Short name T782
Test name
Test status
Simulation time 34818794 ps
CPU time 0.84 seconds
Started Apr 21 01:35:44 PM PDT 24
Finished Apr 21 01:35:45 PM PDT 24
Peak memory 216784 kb
Host smart-46e5eab9-3ba4-40c6-a42d-41c5a2724fb0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796175839 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2796175839
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.428557648
Short name T510
Test name
Test status
Simulation time 48560294 ps
CPU time 0.98 seconds
Started Apr 21 01:35:42 PM PDT 24
Finished Apr 21 01:35:43 PM PDT 24
Peak memory 218576 kb
Host smart-47f36f24-0524-4222-a305-bab00776cf47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428557648 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.428557648
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.2484899287
Short name T114
Test name
Test status
Simulation time 65675319 ps
CPU time 0.91 seconds
Started Apr 21 01:35:43 PM PDT 24
Finished Apr 21 01:35:45 PM PDT 24
Peak memory 219964 kb
Host smart-3737558d-bcd3-4cb0-98c8-cd798f6a9b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484899287 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2484899287
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.833257251
Short name T742
Test name
Test status
Simulation time 70017440 ps
CPU time 1.75 seconds
Started Apr 21 01:35:46 PM PDT 24
Finished Apr 21 01:35:48 PM PDT 24
Peak memory 218772 kb
Host smart-f9d7d3cb-9621-456e-8c98-eb4ab25eb7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833257251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.833257251
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1725983933
Short name T747
Test name
Test status
Simulation time 27631997 ps
CPU time 1.04 seconds
Started Apr 21 01:35:45 PM PDT 24
Finished Apr 21 01:35:46 PM PDT 24
Peak memory 224296 kb
Host smart-f00c2772-16a7-484c-9713-13be94254ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725983933 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1725983933
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2626392789
Short name T500
Test name
Test status
Simulation time 43114407 ps
CPU time 0.88 seconds
Started Apr 21 01:35:41 PM PDT 24
Finished Apr 21 01:35:43 PM PDT 24
Peak memory 215668 kb
Host smart-086121c7-bc95-4859-8a62-9b85d48bba23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626392789 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2626392789
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.229773736
Short name T469
Test name
Test status
Simulation time 790285077 ps
CPU time 4.92 seconds
Started Apr 21 01:35:42 PM PDT 24
Finished Apr 21 01:35:47 PM PDT 24
Peak memory 217184 kb
Host smart-dfdb02ee-d948-4a88-83de-1f48b4fee6c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229773736 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.229773736
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2595276917
Short name T291
Test name
Test status
Simulation time 67122684858 ps
CPU time 854.84 seconds
Started Apr 21 01:35:40 PM PDT 24
Finished Apr 21 01:49:55 PM PDT 24
Peak memory 221416 kb
Host smart-64190fed-74ef-43db-b994-f88dad8b9ba8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595276917 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2595276917
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.edn_genbits.3502770608
Short name T640
Test name
Test status
Simulation time 140408789 ps
CPU time 2.9 seconds
Started Apr 21 01:38:06 PM PDT 24
Finished Apr 21 01:38:09 PM PDT 24
Peak memory 219992 kb
Host smart-449aca84-a49f-4b3f-aa0a-bbe5afd2e990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502770608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3502770608
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.571213934
Short name T550
Test name
Test status
Simulation time 34933755 ps
CPU time 1.28 seconds
Started Apr 21 01:38:04 PM PDT 24
Finished Apr 21 01:38:06 PM PDT 24
Peak memory 218508 kb
Host smart-38c694f2-cff6-43f2-9904-9931e0cccdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571213934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.571213934
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2254632294
Short name T659
Test name
Test status
Simulation time 33264847 ps
CPU time 1.35 seconds
Started Apr 21 01:38:04 PM PDT 24
Finished Apr 21 01:38:06 PM PDT 24
Peak memory 218632 kb
Host smart-b1f66a72-e79d-4cf9-9132-7e6a75caf09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254632294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2254632294
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.2304298830
Short name T830
Test name
Test status
Simulation time 143702678 ps
CPU time 3.19 seconds
Started Apr 21 01:38:07 PM PDT 24
Finished Apr 21 01:38:10 PM PDT 24
Peak memory 215684 kb
Host smart-590193e2-3b25-40b1-937e-e927727c004b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304298830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2304298830
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.1733720363
Short name T322
Test name
Test status
Simulation time 99772015 ps
CPU time 1.47 seconds
Started Apr 21 01:38:07 PM PDT 24
Finished Apr 21 01:38:09 PM PDT 24
Peak memory 218764 kb
Host smart-1e41ba3e-d53e-4f1e-b5d8-3dabe65fd215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733720363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1733720363
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.3331125090
Short name T607
Test name
Test status
Simulation time 45201023 ps
CPU time 1.1 seconds
Started Apr 21 01:38:09 PM PDT 24
Finished Apr 21 01:38:11 PM PDT 24
Peak memory 217332 kb
Host smart-7ab263ca-c2b6-44ca-a14d-c0a00190eb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331125090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3331125090
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.1879280810
Short name T363
Test name
Test status
Simulation time 32383291 ps
CPU time 1.22 seconds
Started Apr 21 01:38:07 PM PDT 24
Finished Apr 21 01:38:09 PM PDT 24
Peak memory 219416 kb
Host smart-c347d18b-4d59-4e0f-b01d-51e245676da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879280810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1879280810
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.890766973
Short name T492
Test name
Test status
Simulation time 164826455 ps
CPU time 3.33 seconds
Started Apr 21 01:38:10 PM PDT 24
Finished Apr 21 01:38:14 PM PDT 24
Peak memory 219272 kb
Host smart-2069f638-9278-4d4d-aef8-00bcbdd075ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890766973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.890766973
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.1673149144
Short name T792
Test name
Test status
Simulation time 34700556 ps
CPU time 1.32 seconds
Started Apr 21 01:38:12 PM PDT 24
Finished Apr 21 01:38:13 PM PDT 24
Peak memory 217400 kb
Host smart-90ac1b04-b995-45f3-92ce-a5bb95aacee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673149144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1673149144
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.808044302
Short name T701
Test name
Test status
Simulation time 117960794 ps
CPU time 0.87 seconds
Started Apr 21 01:35:45 PM PDT 24
Finished Apr 21 01:35:46 PM PDT 24
Peak memory 206976 kb
Host smart-3972d51d-da8a-41e8-8453-3d79ef47a841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808044302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.808044302
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3821553819
Short name T585
Test name
Test status
Simulation time 18110169 ps
CPU time 0.82 seconds
Started Apr 21 01:35:46 PM PDT 24
Finished Apr 21 01:35:48 PM PDT 24
Peak memory 216672 kb
Host smart-829c98aa-55fc-49d9-8149-7b4193e130a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821553819 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3821553819
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.855883047
Short name T779
Test name
Test status
Simulation time 42061230 ps
CPU time 1.27 seconds
Started Apr 21 01:35:45 PM PDT 24
Finished Apr 21 01:35:46 PM PDT 24
Peak memory 225280 kb
Host smart-e2c790ed-949a-4db2-b880-2ad89d331411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855883047 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.855883047
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.693944002
Short name T696
Test name
Test status
Simulation time 31326845 ps
CPU time 1.23 seconds
Started Apr 21 01:35:45 PM PDT 24
Finished Apr 21 01:35:46 PM PDT 24
Peak memory 217296 kb
Host smart-b7eba33e-5b7f-426b-ae33-fc0f863a529a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693944002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.693944002
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3275412497
Short name T828
Test name
Test status
Simulation time 22692544 ps
CPU time 1.16 seconds
Started Apr 21 01:35:44 PM PDT 24
Finished Apr 21 01:35:45 PM PDT 24
Peak memory 224404 kb
Host smart-60b99ff6-3a6d-4510-a74e-9db1fef7a3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275412497 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3275412497
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3900527744
Short name T494
Test name
Test status
Simulation time 16440335 ps
CPU time 1.05 seconds
Started Apr 21 01:35:47 PM PDT 24
Finished Apr 21 01:35:49 PM PDT 24
Peak memory 215656 kb
Host smart-73cec37e-37bf-456e-bb52-41412aaf0a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900527744 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3900527744
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2890565967
Short name T302
Test name
Test status
Simulation time 228617034 ps
CPU time 4.67 seconds
Started Apr 21 01:35:48 PM PDT 24
Finished Apr 21 01:35:53 PM PDT 24
Peak memory 215644 kb
Host smart-7d5c1e79-530a-4524-8c1f-17e9c3a6fc95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890565967 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2890565967
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2392558319
Short name T642
Test name
Test status
Simulation time 210961450176 ps
CPU time 2505.67 seconds
Started Apr 21 01:35:46 PM PDT 24
Finished Apr 21 02:17:32 PM PDT 24
Peak memory 229632 kb
Host smart-69438f56-a3b7-49f4-a4bc-db409739725b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392558319 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2392558319
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.2354125027
Short name T432
Test name
Test status
Simulation time 40489095 ps
CPU time 1.35 seconds
Started Apr 21 01:38:13 PM PDT 24
Finished Apr 21 01:38:14 PM PDT 24
Peak memory 217320 kb
Host smart-09896579-af84-44f5-af23-69db95f81dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354125027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2354125027
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2556766002
Short name T737
Test name
Test status
Simulation time 144167621 ps
CPU time 1.49 seconds
Started Apr 21 01:38:14 PM PDT 24
Finished Apr 21 01:38:15 PM PDT 24
Peak memory 219100 kb
Host smart-e2f4219b-7960-4b29-8ae8-7c0835a61e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556766002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2556766002
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.1822302139
Short name T743
Test name
Test status
Simulation time 51191687 ps
CPU time 1.63 seconds
Started Apr 21 01:38:11 PM PDT 24
Finished Apr 21 01:38:13 PM PDT 24
Peak memory 218648 kb
Host smart-e9fded06-4382-4b83-a8de-01c2e954aa32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822302139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1822302139
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.2973915212
Short name T234
Test name
Test status
Simulation time 37247040 ps
CPU time 1.3 seconds
Started Apr 21 01:38:11 PM PDT 24
Finished Apr 21 01:38:13 PM PDT 24
Peak memory 217364 kb
Host smart-235c056e-ed4d-496e-a94d-6e444e0adfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973915212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2973915212
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.1876501354
Short name T290
Test name
Test status
Simulation time 51252605 ps
CPU time 1.51 seconds
Started Apr 21 01:38:12 PM PDT 24
Finished Apr 21 01:38:14 PM PDT 24
Peak memory 218648 kb
Host smart-34bce130-35ab-4fb6-8e9d-c66337a7af20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876501354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1876501354
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.1879509747
Short name T270
Test name
Test status
Simulation time 49037834 ps
CPU time 1.88 seconds
Started Apr 21 01:38:17 PM PDT 24
Finished Apr 21 01:38:19 PM PDT 24
Peak memory 219040 kb
Host smart-eb475971-bd9a-41ac-874e-7101d80792fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879509747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1879509747
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.679100116
Short name T318
Test name
Test status
Simulation time 107028028 ps
CPU time 1.13 seconds
Started Apr 21 01:38:14 PM PDT 24
Finished Apr 21 01:38:15 PM PDT 24
Peak memory 217240 kb
Host smart-3e27d0bd-b1a6-4112-b5d3-7ce1567a278c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679100116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.679100116
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.3521045152
Short name T798
Test name
Test status
Simulation time 46406906 ps
CPU time 1.17 seconds
Started Apr 21 01:38:14 PM PDT 24
Finished Apr 21 01:38:15 PM PDT 24
Peak memory 219868 kb
Host smart-67efa82e-05d4-4115-b952-b713a1580732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521045152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3521045152
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.249098840
Short name T384
Test name
Test status
Simulation time 45565643 ps
CPU time 1.78 seconds
Started Apr 21 01:38:13 PM PDT 24
Finished Apr 21 01:38:15 PM PDT 24
Peak memory 217476 kb
Host smart-6fafecf9-53a0-419e-9f7c-05dbe28ae53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249098840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.249098840
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.1619344398
Short name T793
Test name
Test status
Simulation time 41219233 ps
CPU time 0.8 seconds
Started Apr 21 01:35:49 PM PDT 24
Finished Apr 21 01:35:50 PM PDT 24
Peak memory 207136 kb
Host smart-f12820bf-3b4d-4e93-9ec6-5ba8ee4aa855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619344398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1619344398
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_err.4283179784
Short name T69
Test name
Test status
Simulation time 26256754 ps
CPU time 0.88 seconds
Started Apr 21 01:35:51 PM PDT 24
Finished Apr 21 01:35:52 PM PDT 24
Peak memory 218636 kb
Host smart-f1de92f8-45d2-4243-940d-72da4729afbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283179784 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.4283179784
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3815237503
Short name T538
Test name
Test status
Simulation time 36141627 ps
CPU time 1.63 seconds
Started Apr 21 01:35:47 PM PDT 24
Finished Apr 21 01:35:49 PM PDT 24
Peak memory 218616 kb
Host smart-78db666d-564f-49b6-9a0d-38f5e08be4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815237503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3815237503
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1746319219
Short name T566
Test name
Test status
Simulation time 30807041 ps
CPU time 0.91 seconds
Started Apr 21 01:35:47 PM PDT 24
Finished Apr 21 01:35:48 PM PDT 24
Peak memory 215924 kb
Host smart-b5072673-1be0-4954-8400-1f8e9b26af61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746319219 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1746319219
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.388677955
Short name T790
Test name
Test status
Simulation time 55181294 ps
CPU time 0.89 seconds
Started Apr 21 01:35:45 PM PDT 24
Finished Apr 21 01:35:46 PM PDT 24
Peak memory 215640 kb
Host smart-227ed060-a7c1-4323-9ee8-7e8e38af8dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388677955 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.388677955
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1043112019
Short name T263
Test name
Test status
Simulation time 90172087 ps
CPU time 2.31 seconds
Started Apr 21 01:35:46 PM PDT 24
Finished Apr 21 01:35:49 PM PDT 24
Peak memory 215692 kb
Host smart-948894d0-98b0-48e3-9ddb-502dac35187a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043112019 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1043112019
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.4159203105
Short name T203
Test name
Test status
Simulation time 36618542223 ps
CPU time 410.76 seconds
Started Apr 21 01:35:46 PM PDT 24
Finished Apr 21 01:42:37 PM PDT 24
Peak memory 218344 kb
Host smart-7bbaf918-ab06-4e55-96b1-760dc9e4c5fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159203105 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.4159203105
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.2550562797
Short name T362
Test name
Test status
Simulation time 43886578 ps
CPU time 1.14 seconds
Started Apr 21 01:38:13 PM PDT 24
Finished Apr 21 01:38:14 PM PDT 24
Peak memory 218572 kb
Host smart-14898ecc-86cf-4b20-b309-89ac50e6b37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550562797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2550562797
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.2408585746
Short name T295
Test name
Test status
Simulation time 52017787 ps
CPU time 2.03 seconds
Started Apr 21 01:38:14 PM PDT 24
Finished Apr 21 01:38:16 PM PDT 24
Peak memory 217500 kb
Host smart-f377d6bb-db1e-49c3-b66d-6752518ff32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408585746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2408585746
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.392989430
Short name T27
Test name
Test status
Simulation time 47919824 ps
CPU time 1.41 seconds
Started Apr 21 01:38:13 PM PDT 24
Finished Apr 21 01:38:15 PM PDT 24
Peak memory 218504 kb
Host smart-b38f28f7-b5f3-4cc3-8e5d-f55cdecf00b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392989430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.392989430
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.3090861615
Short name T835
Test name
Test status
Simulation time 42865081 ps
CPU time 1.4 seconds
Started Apr 21 01:38:16 PM PDT 24
Finished Apr 21 01:38:18 PM PDT 24
Peak memory 219024 kb
Host smart-885ca765-fa5e-4be7-b8ac-20c8ee54c94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090861615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3090861615
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.1674323538
Short name T772
Test name
Test status
Simulation time 34742937 ps
CPU time 1.4 seconds
Started Apr 21 01:38:17 PM PDT 24
Finished Apr 21 01:38:19 PM PDT 24
Peak memory 218644 kb
Host smart-7b929bef-6167-4037-80c2-76817a58caf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674323538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1674323538
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.2904363447
Short name T296
Test name
Test status
Simulation time 208414158 ps
CPU time 2.69 seconds
Started Apr 21 01:38:14 PM PDT 24
Finished Apr 21 01:38:17 PM PDT 24
Peak memory 219960 kb
Host smart-0f1b2878-5b7f-4bc5-a79e-ae5ffe8e3203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904363447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2904363447
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1879992567
Short name T306
Test name
Test status
Simulation time 34056872 ps
CPU time 1.31 seconds
Started Apr 21 01:38:13 PM PDT 24
Finished Apr 21 01:38:15 PM PDT 24
Peak memory 218508 kb
Host smart-3e02e52f-d8a0-426b-8774-66d5519b8f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879992567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1879992567
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.1916855974
Short name T614
Test name
Test status
Simulation time 32432525 ps
CPU time 1.39 seconds
Started Apr 21 01:38:15 PM PDT 24
Finished Apr 21 01:38:17 PM PDT 24
Peak memory 218440 kb
Host smart-a47b3368-c67e-4a9f-872e-588ba928a243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916855974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1916855974
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert_test.2526824747
Short name T764
Test name
Test status
Simulation time 121134413 ps
CPU time 0.97 seconds
Started Apr 21 01:35:55 PM PDT 24
Finished Apr 21 01:35:56 PM PDT 24
Peak memory 206968 kb
Host smart-fb8c61ba-6182-47e5-bbcc-eabecf4edfc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526824747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2526824747
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.4181339332
Short name T399
Test name
Test status
Simulation time 69999475 ps
CPU time 1.19 seconds
Started Apr 21 01:35:54 PM PDT 24
Finished Apr 21 01:35:56 PM PDT 24
Peak memory 217260 kb
Host smart-bbd8dfbd-7c94-496a-ad74-34757ce422a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181339332 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.4181339332
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2379471510
Short name T408
Test name
Test status
Simulation time 29142007 ps
CPU time 1.2 seconds
Started Apr 21 01:35:48 PM PDT 24
Finished Apr 21 01:35:50 PM PDT 24
Peak memory 220200 kb
Host smart-d2efd83c-deda-4f26-acfa-ae2d2cd6c6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379471510 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2379471510
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2441734008
Short name T274
Test name
Test status
Simulation time 21071831 ps
CPU time 1.04 seconds
Started Apr 21 01:35:50 PM PDT 24
Finished Apr 21 01:35:51 PM PDT 24
Peak memory 217420 kb
Host smart-2db69482-51ab-40c1-bc1d-ecccfeaeac04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441734008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2441734008
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.503263474
Short name T347
Test name
Test status
Simulation time 29237213 ps
CPU time 1.02 seconds
Started Apr 21 01:35:50 PM PDT 24
Finished Apr 21 01:35:52 PM PDT 24
Peak memory 224360 kb
Host smart-9342813d-0820-450d-96f0-f4b33191f833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503263474 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.503263474
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1902005199
Short name T486
Test name
Test status
Simulation time 14748058 ps
CPU time 1.05 seconds
Started Apr 21 01:35:52 PM PDT 24
Finished Apr 21 01:35:54 PM PDT 24
Peak memory 215604 kb
Host smart-05fe45f7-0641-4ea2-824a-c5403e6cad67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902005199 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1902005199
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.32199803
Short name T388
Test name
Test status
Simulation time 323855559 ps
CPU time 1.81 seconds
Started Apr 21 01:35:52 PM PDT 24
Finished Apr 21 01:35:54 PM PDT 24
Peak memory 217384 kb
Host smart-e8efbcac-34d8-4310-8985-0e2f96f7c34d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32199803 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.32199803
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.496157099
Short name T495
Test name
Test status
Simulation time 15450903677 ps
CPU time 377.01 seconds
Started Apr 21 01:35:52 PM PDT 24
Finished Apr 21 01:42:10 PM PDT 24
Peak memory 217868 kb
Host smart-c1e9d7f5-a81b-4b62-b23b-a0e9e1fe847e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496157099 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.496157099
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.3707981955
Short name T353
Test name
Test status
Simulation time 67250754 ps
CPU time 1.11 seconds
Started Apr 21 01:38:22 PM PDT 24
Finished Apr 21 01:38:23 PM PDT 24
Peak memory 217448 kb
Host smart-8410184a-18e4-406f-bd2d-f1dfd23c0216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707981955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3707981955
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.652703390
Short name T366
Test name
Test status
Simulation time 79400783 ps
CPU time 2.82 seconds
Started Apr 21 01:38:21 PM PDT 24
Finished Apr 21 01:38:24 PM PDT 24
Peak memory 217432 kb
Host smart-7bcb3ebc-48ed-40a1-8036-b3156e134107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652703390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.652703390
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.1974317865
Short name T525
Test name
Test status
Simulation time 52476619 ps
CPU time 2.05 seconds
Started Apr 21 01:38:18 PM PDT 24
Finished Apr 21 01:38:21 PM PDT 24
Peak memory 220124 kb
Host smart-a0f24f7c-a565-48d0-a5fc-fd7df8a25572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974317865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1974317865
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.324326387
Short name T333
Test name
Test status
Simulation time 63901766 ps
CPU time 1.57 seconds
Started Apr 21 01:38:18 PM PDT 24
Finished Apr 21 01:38:20 PM PDT 24
Peak memory 218624 kb
Host smart-69a1ea60-a07e-494d-98a0-95f479ab86d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324326387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.324326387
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.2728367856
Short name T556
Test name
Test status
Simulation time 45208733 ps
CPU time 1.54 seconds
Started Apr 21 01:38:18 PM PDT 24
Finished Apr 21 01:38:20 PM PDT 24
Peak memory 218676 kb
Host smart-c86c0b17-56b0-4887-8d87-2f489b726b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728367856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2728367856
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.3241883252
Short name T410
Test name
Test status
Simulation time 70438578 ps
CPU time 1.08 seconds
Started Apr 21 01:38:17 PM PDT 24
Finished Apr 21 01:38:19 PM PDT 24
Peak memory 217352 kb
Host smart-ccfe4476-6736-4edf-a607-ac8064baa1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241883252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3241883252
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.3403889896
Short name T833
Test name
Test status
Simulation time 88180925 ps
CPU time 1.16 seconds
Started Apr 21 01:38:17 PM PDT 24
Finished Apr 21 01:38:19 PM PDT 24
Peak memory 217384 kb
Host smart-f426baf5-e132-44b2-a029-a26acb6bc001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403889896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3403889896
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3712578001
Short name T502
Test name
Test status
Simulation time 46813595 ps
CPU time 1.73 seconds
Started Apr 21 01:38:17 PM PDT 24
Finished Apr 21 01:38:19 PM PDT 24
Peak memory 217336 kb
Host smart-1ea97af0-1d7e-44e9-985f-80f9627b1c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712578001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3712578001
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.1891395245
Short name T796
Test name
Test status
Simulation time 45623046 ps
CPU time 1.53 seconds
Started Apr 21 01:38:18 PM PDT 24
Finished Apr 21 01:38:20 PM PDT 24
Peak memory 218544 kb
Host smart-f03efd3c-df06-47c6-846e-e3f4a20a44d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891395245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1891395245
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.18023200
Short name T463
Test name
Test status
Simulation time 262876553 ps
CPU time 1.44 seconds
Started Apr 21 01:38:49 PM PDT 24
Finished Apr 21 01:38:50 PM PDT 24
Peak memory 219844 kb
Host smart-ff37ea58-8fff-4b1a-b1e7-e5a1dd1692f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18023200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.18023200
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.721136594
Short name T668
Test name
Test status
Simulation time 50965389 ps
CPU time 1.24 seconds
Started Apr 21 01:34:58 PM PDT 24
Finished Apr 21 01:34:59 PM PDT 24
Peak memory 216024 kb
Host smart-b1211a52-2c26-4018-a849-abfa20daab78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721136594 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.721136594
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.551445538
Short name T330
Test name
Test status
Simulation time 28385176 ps
CPU time 0.9 seconds
Started Apr 21 01:34:57 PM PDT 24
Finished Apr 21 01:34:58 PM PDT 24
Peak memory 215212 kb
Host smart-0e5118e4-1469-4af8-9a42-54d0aee384eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551445538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.551445538
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.849933093
Short name T479
Test name
Test status
Simulation time 11817455 ps
CPU time 0.87 seconds
Started Apr 21 01:34:57 PM PDT 24
Finished Apr 21 01:34:58 PM PDT 24
Peak memory 215800 kb
Host smart-e723fe12-45e1-4604-9ec4-098117a3720e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849933093 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.849933093
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.594912721
Short name T613
Test name
Test status
Simulation time 26746770 ps
CPU time 1.12 seconds
Started Apr 21 01:34:55 PM PDT 24
Finished Apr 21 01:34:56 PM PDT 24
Peak memory 218900 kb
Host smart-c8d66459-a225-428c-a87e-8b20d2db845f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594912721 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.594912721
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.208724281
Short name T235
Test name
Test status
Simulation time 123308524 ps
CPU time 1.61 seconds
Started Apr 21 01:34:54 PM PDT 24
Finished Apr 21 01:34:55 PM PDT 24
Peak memory 218896 kb
Host smart-bf101d9e-0a02-4cec-a6f3-f376c36bd1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208724281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.208724281
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2063122951
Short name T425
Test name
Test status
Simulation time 28696818 ps
CPU time 0.96 seconds
Started Apr 21 01:34:58 PM PDT 24
Finished Apr 21 01:34:59 PM PDT 24
Peak memory 215904 kb
Host smart-aa93979d-5a13-491f-986c-09d01994aa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063122951 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2063122951
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2024304494
Short name T255
Test name
Test status
Simulation time 18465092 ps
CPU time 1 seconds
Started Apr 21 01:34:54 PM PDT 24
Finished Apr 21 01:34:56 PM PDT 24
Peak memory 207420 kb
Host smart-777f66b0-34b8-4147-b920-e510ad02d2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024304494 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2024304494
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2316482672
Short name T18
Test name
Test status
Simulation time 1740703654 ps
CPU time 10.02 seconds
Started Apr 21 01:34:56 PM PDT 24
Finished Apr 21 01:35:06 PM PDT 24
Peak memory 237572 kb
Host smart-06cbe8b1-3865-407b-a7c4-02a625e9348a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316482672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2316482672
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3723472402
Short name T775
Test name
Test status
Simulation time 14602628 ps
CPU time 0.91 seconds
Started Apr 21 01:34:51 PM PDT 24
Finished Apr 21 01:34:52 PM PDT 24
Peak memory 215604 kb
Host smart-b48eaf74-7cd1-4644-ae4c-83e6750c063d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723472402 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3723472402
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2193708184
Short name T753
Test name
Test status
Simulation time 161242180 ps
CPU time 2.09 seconds
Started Apr 21 01:34:54 PM PDT 24
Finished Apr 21 01:34:56 PM PDT 24
Peak memory 215644 kb
Host smart-b1132719-07e2-460a-9e9c-54dc7ef3e31d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193708184 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2193708184
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1151702040
Short name T641
Test name
Test status
Simulation time 199791517750 ps
CPU time 1344.39 seconds
Started Apr 21 01:34:58 PM PDT 24
Finished Apr 21 01:57:23 PM PDT 24
Peak memory 225116 kb
Host smart-864a9139-275f-4bfa-836e-e4dc8a73ce3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151702040 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1151702040
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3567790990
Short name T249
Test name
Test status
Simulation time 40052742 ps
CPU time 1.2 seconds
Started Apr 21 01:35:55 PM PDT 24
Finished Apr 21 01:35:57 PM PDT 24
Peak memory 216016 kb
Host smart-732f3dd7-c693-4f83-9337-ca8608af811f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567790990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3567790990
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3132865726
Short name T327
Test name
Test status
Simulation time 86872466 ps
CPU time 1.09 seconds
Started Apr 21 01:35:55 PM PDT 24
Finished Apr 21 01:35:57 PM PDT 24
Peak memory 207060 kb
Host smart-e84d2f52-b239-4b6e-97d3-602bade66c1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132865726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3132865726
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3215201537
Short name T2
Test name
Test status
Simulation time 12962516 ps
CPU time 0.92 seconds
Started Apr 21 01:35:54 PM PDT 24
Finished Apr 21 01:35:55 PM PDT 24
Peak memory 216468 kb
Host smart-04216a52-6161-4f08-8715-3d39384d5ffd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215201537 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3215201537
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1070370037
Short name T586
Test name
Test status
Simulation time 160589946 ps
CPU time 1.01 seconds
Started Apr 21 01:35:53 PM PDT 24
Finished Apr 21 01:35:54 PM PDT 24
Peak memory 217432 kb
Host smart-2a5825f9-728d-47b5-afb6-0fb5e8df3cd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070370037 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1070370037
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.105568619
Short name T818
Test name
Test status
Simulation time 66926461 ps
CPU time 0.84 seconds
Started Apr 21 01:35:55 PM PDT 24
Finished Apr 21 01:35:57 PM PDT 24
Peak memory 218188 kb
Host smart-b8986cd3-7772-486e-b5e0-1f790170d635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105568619 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.105568619
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1378427963
Short name T233
Test name
Test status
Simulation time 38665854 ps
CPU time 1.39 seconds
Started Apr 21 01:35:53 PM PDT 24
Finished Apr 21 01:35:55 PM PDT 24
Peak memory 217368 kb
Host smart-918c9810-259f-4c6f-9e00-1dcf69b0e6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378427963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1378427963
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3465874399
Short name T524
Test name
Test status
Simulation time 22977883 ps
CPU time 1.09 seconds
Started Apr 21 01:35:54 PM PDT 24
Finished Apr 21 01:35:55 PM PDT 24
Peak memory 215920 kb
Host smart-35ab347e-c76c-47ef-a797-a03f0a2b43b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465874399 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3465874399
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3501856428
Short name T430
Test name
Test status
Simulation time 18459936 ps
CPU time 0.95 seconds
Started Apr 21 01:35:58 PM PDT 24
Finished Apr 21 01:35:59 PM PDT 24
Peak memory 215636 kb
Host smart-49135acd-66cd-4bd3-a54c-bfc457773cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501856428 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3501856428
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3381370734
Short name T789
Test name
Test status
Simulation time 632018490 ps
CPU time 3.78 seconds
Started Apr 21 01:35:57 PM PDT 24
Finished Apr 21 01:36:01 PM PDT 24
Peak memory 217344 kb
Host smart-96a85171-9aec-47b0-8500-0dfe872aa022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381370734 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3381370734
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2763366709
Short name T77
Test name
Test status
Simulation time 67008903859 ps
CPU time 870.13 seconds
Started Apr 21 01:35:54 PM PDT 24
Finished Apr 21 01:50:25 PM PDT 24
Peak memory 221492 kb
Host smart-5065b449-3790-406a-a4c2-d322b2ad3572
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763366709 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2763366709
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3814872430
Short name T448
Test name
Test status
Simulation time 40059062 ps
CPU time 0.96 seconds
Started Apr 21 01:38:19 PM PDT 24
Finished Apr 21 01:38:20 PM PDT 24
Peak memory 217368 kb
Host smart-f98bdc59-49d3-48db-b942-f339a9209dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814872430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3814872430
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.569328631
Short name T419
Test name
Test status
Simulation time 42411821 ps
CPU time 1.28 seconds
Started Apr 21 01:38:19 PM PDT 24
Finished Apr 21 01:38:20 PM PDT 24
Peak memory 218468 kb
Host smart-b1839379-8707-4864-a057-53cce53ecb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569328631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.569328631
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.4108655878
Short name T433
Test name
Test status
Simulation time 92475331 ps
CPU time 1.27 seconds
Started Apr 21 01:38:18 PM PDT 24
Finished Apr 21 01:38:20 PM PDT 24
Peak memory 219952 kb
Host smart-a114e78e-d288-4e50-a93b-cd17d7367d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108655878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.4108655878
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1930843938
Short name T760
Test name
Test status
Simulation time 58623803 ps
CPU time 1.42 seconds
Started Apr 21 01:38:20 PM PDT 24
Finished Apr 21 01:38:22 PM PDT 24
Peak memory 218768 kb
Host smart-b7b6bdd2-f69d-4718-bca4-7d23f6d8254f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930843938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1930843938
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.336345590
Short name T460
Test name
Test status
Simulation time 38237132 ps
CPU time 1.48 seconds
Started Apr 21 01:38:20 PM PDT 24
Finished Apr 21 01:38:22 PM PDT 24
Peak memory 217360 kb
Host smart-409fc60c-001b-4f5d-b36f-521ad0771b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336345590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.336345590
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3491145174
Short name T414
Test name
Test status
Simulation time 61312591 ps
CPU time 2.05 seconds
Started Apr 21 01:38:20 PM PDT 24
Finished Apr 21 01:38:22 PM PDT 24
Peak memory 220168 kb
Host smart-21fe52ee-6cfa-4e12-8792-6dc5994493eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491145174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3491145174
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3292250397
Short name T552
Test name
Test status
Simulation time 135118233 ps
CPU time 1.05 seconds
Started Apr 21 01:38:22 PM PDT 24
Finished Apr 21 01:38:23 PM PDT 24
Peak memory 217492 kb
Host smart-c883d25d-47f2-419e-b16e-f57a10834309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292250397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3292250397
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.395980587
Short name T713
Test name
Test status
Simulation time 34873093 ps
CPU time 1.24 seconds
Started Apr 21 01:38:22 PM PDT 24
Finished Apr 21 01:38:23 PM PDT 24
Peak memory 218480 kb
Host smart-289482e5-465f-4830-a5ea-c59767dc15b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395980587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.395980587
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.398228142
Short name T765
Test name
Test status
Simulation time 53665812 ps
CPU time 1.24 seconds
Started Apr 21 01:38:23 PM PDT 24
Finished Apr 21 01:38:25 PM PDT 24
Peak memory 218908 kb
Host smart-d1e9cc8d-d33c-48e4-b1aa-229f9cb98ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398228142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.398228142
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.378009504
Short name T527
Test name
Test status
Simulation time 287739409 ps
CPU time 4.12 seconds
Started Apr 21 01:38:23 PM PDT 24
Finished Apr 21 01:38:27 PM PDT 24
Peak memory 220200 kb
Host smart-90dac4ac-8dcc-4c00-8a5e-c192429a6406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378009504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.378009504
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1911496484
Short name T192
Test name
Test status
Simulation time 24097478 ps
CPU time 1.17 seconds
Started Apr 21 01:35:55 PM PDT 24
Finished Apr 21 01:35:57 PM PDT 24
Peak memory 216256 kb
Host smart-59aa7246-cea2-4149-be3f-d1576def5be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911496484 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1911496484
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1416381975
Short name T462
Test name
Test status
Simulation time 23046466 ps
CPU time 1.01 seconds
Started Apr 21 01:35:55 PM PDT 24
Finished Apr 21 01:35:56 PM PDT 24
Peak memory 207044 kb
Host smart-be568f38-d655-45d4-9957-28d3f86fdcda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416381975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1416381975
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3901247991
Short name T563
Test name
Test status
Simulation time 11962615 ps
CPU time 0.88 seconds
Started Apr 21 01:36:02 PM PDT 24
Finished Apr 21 01:36:04 PM PDT 24
Peak memory 216628 kb
Host smart-3e60edb8-cfa1-4579-9ce4-46deb2128800
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901247991 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3901247991
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_err.4035894472
Short name T316
Test name
Test status
Simulation time 21206921 ps
CPU time 0.87 seconds
Started Apr 21 01:35:57 PM PDT 24
Finished Apr 21 01:35:58 PM PDT 24
Peak memory 218412 kb
Host smart-a50ec55e-438c-496d-bb0a-8993d5e0eec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035894472 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.4035894472
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3582392224
Short name T92
Test name
Test status
Simulation time 46514276 ps
CPU time 1.54 seconds
Started Apr 21 01:35:52 PM PDT 24
Finished Apr 21 01:35:54 PM PDT 24
Peak memory 218476 kb
Host smart-c32bd7b9-2201-4eb0-9bc9-9eb89da90aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582392224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3582392224
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3230171271
Short name T15
Test name
Test status
Simulation time 21991732 ps
CPU time 1.17 seconds
Started Apr 21 01:35:55 PM PDT 24
Finished Apr 21 01:35:56 PM PDT 24
Peak memory 224332 kb
Host smart-0de54643-563d-4202-9e2d-01ef2e7215af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230171271 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3230171271
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1257026750
Short name T786
Test name
Test status
Simulation time 20208327 ps
CPU time 1.03 seconds
Started Apr 21 01:35:54 PM PDT 24
Finished Apr 21 01:35:55 PM PDT 24
Peak memory 215644 kb
Host smart-4249d466-5e45-4168-8c03-c7b09988ab2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257026750 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1257026750
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3200252607
Short name T610
Test name
Test status
Simulation time 252802367 ps
CPU time 1.85 seconds
Started Apr 21 01:35:56 PM PDT 24
Finished Apr 21 01:35:59 PM PDT 24
Peak memory 219448 kb
Host smart-04c29873-aa00-4ca2-bbb6-309315090490
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200252607 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3200252607
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2339872598
Short name T676
Test name
Test status
Simulation time 16302631803 ps
CPU time 376.1 seconds
Started Apr 21 01:35:58 PM PDT 24
Finished Apr 21 01:42:14 PM PDT 24
Peak memory 218840 kb
Host smart-ef52c00f-fc9b-4b18-a6f8-5f34d8bffe79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339872598 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2339872598
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3248593337
Short name T275
Test name
Test status
Simulation time 56478666 ps
CPU time 1.43 seconds
Started Apr 21 01:38:20 PM PDT 24
Finished Apr 21 01:38:22 PM PDT 24
Peak memory 218704 kb
Host smart-e603329f-d49d-4150-bd63-967b99412817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248593337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3248593337
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.579566745
Short name T435
Test name
Test status
Simulation time 36969628 ps
CPU time 1.54 seconds
Started Apr 21 01:38:21 PM PDT 24
Finished Apr 21 01:38:22 PM PDT 24
Peak memory 218540 kb
Host smart-b68d9580-0b9d-41aa-a0ff-dc1cba43fe3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579566745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.579566745
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2918759021
Short name T740
Test name
Test status
Simulation time 46337804 ps
CPU time 1.91 seconds
Started Apr 21 01:38:25 PM PDT 24
Finished Apr 21 01:38:28 PM PDT 24
Peak memory 217656 kb
Host smart-dbc2a381-acdf-4250-b468-d7edda4998f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918759021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2918759021
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2650544679
Short name T478
Test name
Test status
Simulation time 51282912 ps
CPU time 1.18 seconds
Started Apr 21 01:38:22 PM PDT 24
Finished Apr 21 01:38:23 PM PDT 24
Peak memory 217152 kb
Host smart-f331fa80-376d-443b-92f6-466274cf3dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650544679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2650544679
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.4125969059
Short name T820
Test name
Test status
Simulation time 71625222 ps
CPU time 1.45 seconds
Started Apr 21 01:38:25 PM PDT 24
Finished Apr 21 01:38:27 PM PDT 24
Peak memory 218532 kb
Host smart-7d8d9f09-5148-4ace-86bb-e72fa0168ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125969059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.4125969059
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.218293301
Short name T729
Test name
Test status
Simulation time 302984986 ps
CPU time 1.33 seconds
Started Apr 21 01:38:24 PM PDT 24
Finished Apr 21 01:38:25 PM PDT 24
Peak memory 217508 kb
Host smart-2c09722a-f891-4539-8b6b-04868e8bfd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218293301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.218293301
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.512265425
Short name T732
Test name
Test status
Simulation time 49813988 ps
CPU time 1.42 seconds
Started Apr 21 01:38:26 PM PDT 24
Finished Apr 21 01:38:28 PM PDT 24
Peak memory 217196 kb
Host smart-4103ec92-fac8-469b-9504-0257df91faff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512265425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.512265425
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1986639049
Short name T442
Test name
Test status
Simulation time 50764250 ps
CPU time 1.66 seconds
Started Apr 21 01:38:21 PM PDT 24
Finished Apr 21 01:38:23 PM PDT 24
Peak memory 218456 kb
Host smart-1ada8496-d17b-42b6-9540-cd143831e1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986639049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1986639049
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2384503968
Short name T501
Test name
Test status
Simulation time 70398790 ps
CPU time 1.29 seconds
Started Apr 21 01:38:23 PM PDT 24
Finished Apr 21 01:38:24 PM PDT 24
Peak memory 218692 kb
Host smart-f1e78228-3746-4d78-b19f-6037b298de06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384503968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2384503968
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1524721706
Short name T251
Test name
Test status
Simulation time 427156713 ps
CPU time 1.31 seconds
Started Apr 21 01:36:01 PM PDT 24
Finished Apr 21 01:36:02 PM PDT 24
Peak memory 216084 kb
Host smart-fcb23d9f-2040-4e84-9e5f-8e31d4da0c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524721706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1524721706
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.850511864
Short name T383
Test name
Test status
Simulation time 21250185 ps
CPU time 0.82 seconds
Started Apr 21 01:35:58 PM PDT 24
Finished Apr 21 01:35:59 PM PDT 24
Peak memory 206756 kb
Host smart-7a03efad-45b3-4082-8bfc-1daaffdcf488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850511864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.850511864
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2693431905
Short name T658
Test name
Test status
Simulation time 14095947 ps
CPU time 0.93 seconds
Started Apr 21 01:35:58 PM PDT 24
Finished Apr 21 01:36:00 PM PDT 24
Peak memory 216832 kb
Host smart-d57ae914-fc46-4b62-b8c7-a8f307ed529b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693431905 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2693431905
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3082636110
Short name T183
Test name
Test status
Simulation time 28544326 ps
CPU time 1.15 seconds
Started Apr 21 01:35:58 PM PDT 24
Finished Apr 21 01:36:00 PM PDT 24
Peak memory 217140 kb
Host smart-37c8225e-7d87-4b76-a787-b4dc5a5296a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082636110 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3082636110
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.231094591
Short name T712
Test name
Test status
Simulation time 142299372 ps
CPU time 0.93 seconds
Started Apr 21 01:35:58 PM PDT 24
Finished Apr 21 01:36:00 PM PDT 24
Peak memory 220028 kb
Host smart-88a8b60b-1598-4235-b703-875f61f8a7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231094591 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.231094591
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2110985400
Short name T447
Test name
Test status
Simulation time 41511946 ps
CPU time 1.21 seconds
Started Apr 21 01:36:01 PM PDT 24
Finished Apr 21 01:36:03 PM PDT 24
Peak memory 219904 kb
Host smart-993971d1-cbfc-4d64-bae3-e684c4b5cb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110985400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2110985400
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3602820109
Short name T409
Test name
Test status
Simulation time 41088508 ps
CPU time 0.89 seconds
Started Apr 21 01:35:55 PM PDT 24
Finished Apr 21 01:35:57 PM PDT 24
Peak memory 224156 kb
Host smart-f830398e-64a2-4a7c-ac86-86b41ed04e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602820109 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3602820109
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1009164332
Short name T370
Test name
Test status
Simulation time 19380099 ps
CPU time 1.09 seconds
Started Apr 21 01:36:03 PM PDT 24
Finished Apr 21 01:36:04 PM PDT 24
Peak memory 215656 kb
Host smart-cf919608-2a29-4714-9a92-c297c18f6927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009164332 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1009164332
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1103945600
Short name T418
Test name
Test status
Simulation time 143491526 ps
CPU time 1.88 seconds
Started Apr 21 01:35:54 PM PDT 24
Finished Apr 21 01:35:56 PM PDT 24
Peak memory 217404 kb
Host smart-35ab8367-d9e8-4ade-87f6-8fab71059650
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103945600 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1103945600
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1650348684
Short name T195
Test name
Test status
Simulation time 295215125673 ps
CPU time 1821.94 seconds
Started Apr 21 01:36:00 PM PDT 24
Finished Apr 21 02:06:23 PM PDT 24
Peak memory 228728 kb
Host smart-88efca50-1836-4ba8-9b4d-1e5e379940e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650348684 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1650348684
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1034627618
Short name T380
Test name
Test status
Simulation time 58493726 ps
CPU time 1.38 seconds
Started Apr 21 01:38:25 PM PDT 24
Finished Apr 21 01:38:27 PM PDT 24
Peak memory 218376 kb
Host smart-7e76ca67-8a0d-476a-92e9-12c9e0d601f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034627618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1034627618
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2283720537
Short name T309
Test name
Test status
Simulation time 67327475 ps
CPU time 1.11 seconds
Started Apr 21 01:38:24 PM PDT 24
Finished Apr 21 01:38:26 PM PDT 24
Peak memory 217220 kb
Host smart-7c8a3df6-9b84-4c7b-b6c7-4e107adbed71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283720537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2283720537
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.636062769
Short name T581
Test name
Test status
Simulation time 62143592 ps
CPU time 1.59 seconds
Started Apr 21 01:38:28 PM PDT 24
Finished Apr 21 01:38:30 PM PDT 24
Peak memory 218680 kb
Host smart-94827157-c0ed-4c6c-abd9-b235bd21a8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636062769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.636062769
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1337049640
Short name T824
Test name
Test status
Simulation time 633571857 ps
CPU time 3.92 seconds
Started Apr 21 01:38:26 PM PDT 24
Finished Apr 21 01:38:30 PM PDT 24
Peak memory 220308 kb
Host smart-e77f04c3-93db-4bf2-8059-6487847f9d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337049640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1337049640
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1088503321
Short name T345
Test name
Test status
Simulation time 84533786 ps
CPU time 2.82 seconds
Started Apr 21 01:38:28 PM PDT 24
Finished Apr 21 01:38:31 PM PDT 24
Peak memory 219848 kb
Host smart-6e9ad24e-94b3-4da2-94a9-7d1a5b6ee174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088503321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1088503321
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2318413042
Short name T636
Test name
Test status
Simulation time 84864342 ps
CPU time 1.5 seconds
Started Apr 21 01:38:26 PM PDT 24
Finished Apr 21 01:38:28 PM PDT 24
Peak memory 218892 kb
Host smart-9e4d4592-f0d6-4323-8316-564b3666be5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318413042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2318413042
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3044445839
Short name T511
Test name
Test status
Simulation time 76298228 ps
CPU time 1.32 seconds
Started Apr 21 01:38:26 PM PDT 24
Finished Apr 21 01:38:28 PM PDT 24
Peak memory 218784 kb
Host smart-6dad8c1a-0c66-4579-b5c1-9e634a0245bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044445839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3044445839
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3910330539
Short name T278
Test name
Test status
Simulation time 31158761 ps
CPU time 1.32 seconds
Started Apr 21 01:38:24 PM PDT 24
Finished Apr 21 01:38:26 PM PDT 24
Peak memory 217316 kb
Host smart-235ec357-4cca-4d20-bd5c-0de2d8785a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910330539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3910330539
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.225964713
Short name T424
Test name
Test status
Simulation time 111099215 ps
CPU time 0.99 seconds
Started Apr 21 01:38:25 PM PDT 24
Finished Apr 21 01:38:26 PM PDT 24
Peak memory 217244 kb
Host smart-4fd91857-f35c-4f76-aaa7-8b4803b48c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225964713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.225964713
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2644285919
Short name T398
Test name
Test status
Simulation time 63349552 ps
CPU time 1.49 seconds
Started Apr 21 01:38:25 PM PDT 24
Finished Apr 21 01:38:27 PM PDT 24
Peak memory 218644 kb
Host smart-05d0e7d7-d0da-4b75-a261-af2b58d2689d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644285919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2644285919
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert_test.2208784928
Short name T436
Test name
Test status
Simulation time 28375302 ps
CPU time 0.96 seconds
Started Apr 21 01:36:03 PM PDT 24
Finished Apr 21 01:36:05 PM PDT 24
Peak memory 215148 kb
Host smart-1577bedc-0d51-4e84-b96d-6cfe7ba890c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208784928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2208784928
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.67292131
Short name T450
Test name
Test status
Simulation time 53878695 ps
CPU time 0.78 seconds
Started Apr 21 01:36:00 PM PDT 24
Finished Apr 21 01:36:01 PM PDT 24
Peak memory 216452 kb
Host smart-2994e358-0056-4d04-93e2-58c61aff8e96
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67292131 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.67292131
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.4276567781
Short name T168
Test name
Test status
Simulation time 113538650 ps
CPU time 1.23 seconds
Started Apr 21 01:36:03 PM PDT 24
Finished Apr 21 01:36:05 PM PDT 24
Peak memory 219860 kb
Host smart-2c55efaa-1848-4fa6-9970-fc3ae8f741b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276567781 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.4276567781
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1110541687
Short name T64
Test name
Test status
Simulation time 28158348 ps
CPU time 1.05 seconds
Started Apr 21 01:36:02 PM PDT 24
Finished Apr 21 01:36:04 PM PDT 24
Peak memory 224344 kb
Host smart-193f680c-6e01-4f5d-96fd-94beb3701522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110541687 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1110541687
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.4089842781
Short name T710
Test name
Test status
Simulation time 54064436 ps
CPU time 1.42 seconds
Started Apr 21 01:36:00 PM PDT 24
Finished Apr 21 01:36:02 PM PDT 24
Peak memory 217368 kb
Host smart-8e9c0b08-c434-44bc-910c-c582c03fe4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089842781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.4089842781
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_smoke.2215671675
Short name T354
Test name
Test status
Simulation time 36803883 ps
CPU time 0.85 seconds
Started Apr 21 01:35:58 PM PDT 24
Finished Apr 21 01:35:59 PM PDT 24
Peak memory 215608 kb
Host smart-eba680af-0280-4725-bc14-667a61e12900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215671675 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2215671675
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3362976663
Short name T325
Test name
Test status
Simulation time 230154303 ps
CPU time 4.11 seconds
Started Apr 21 01:35:58 PM PDT 24
Finished Apr 21 01:36:03 PM PDT 24
Peak memory 217400 kb
Host smart-9bbfc4a2-0f82-4ece-ae5b-5f02cad336e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362976663 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3362976663
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1157095562
Short name T350
Test name
Test status
Simulation time 90713112683 ps
CPU time 321.52 seconds
Started Apr 21 01:36:02 PM PDT 24
Finished Apr 21 01:41:24 PM PDT 24
Peak memory 218892 kb
Host smart-b23abb3b-a3ac-48d2-a446-a365e4142aa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157095562 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1157095562
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.3636549869
Short name T749
Test name
Test status
Simulation time 36384556 ps
CPU time 1.41 seconds
Started Apr 21 01:38:31 PM PDT 24
Finished Apr 21 01:38:33 PM PDT 24
Peak memory 217324 kb
Host smart-d031c9f6-18ba-41a8-830e-dc84a2689df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636549869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.3636549869
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3261896967
Short name T476
Test name
Test status
Simulation time 32369235 ps
CPU time 1.27 seconds
Started Apr 21 01:38:29 PM PDT 24
Finished Apr 21 01:38:30 PM PDT 24
Peak memory 217536 kb
Host smart-2e944c70-8f90-44c1-8a95-78c202868eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261896967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3261896967
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.356416226
Short name T348
Test name
Test status
Simulation time 101176343 ps
CPU time 1.06 seconds
Started Apr 21 01:38:30 PM PDT 24
Finished Apr 21 01:38:31 PM PDT 24
Peak memory 217240 kb
Host smart-bdd03951-578b-4589-9643-0cb0757ffd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356416226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.356416226
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.913289156
Short name T755
Test name
Test status
Simulation time 40741741 ps
CPU time 1.32 seconds
Started Apr 21 01:38:29 PM PDT 24
Finished Apr 21 01:38:31 PM PDT 24
Peak memory 217220 kb
Host smart-81f701c5-add3-4c11-8eac-1e10f58ae534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913289156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.913289156
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.640015341
Short name T452
Test name
Test status
Simulation time 40699504 ps
CPU time 1.63 seconds
Started Apr 21 01:38:30 PM PDT 24
Finished Apr 21 01:38:32 PM PDT 24
Peak memory 217164 kb
Host smart-87f0ad3b-af86-480c-aa20-fb020756dde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640015341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.640015341
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2114728653
Short name T827
Test name
Test status
Simulation time 235443999 ps
CPU time 1.74 seconds
Started Apr 21 01:38:28 PM PDT 24
Finished Apr 21 01:38:30 PM PDT 24
Peak memory 220292 kb
Host smart-9d371b8c-5d89-4e29-906f-80c47a7cae5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114728653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2114728653
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.21912445
Short name T518
Test name
Test status
Simulation time 162051648 ps
CPU time 1.45 seconds
Started Apr 21 01:38:27 PM PDT 24
Finished Apr 21 01:38:29 PM PDT 24
Peak memory 219936 kb
Host smart-9a93f6f7-794b-48ba-b88e-8ef4b4f13f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21912445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.21912445
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3109374417
Short name T372
Test name
Test status
Simulation time 145047231 ps
CPU time 1.5 seconds
Started Apr 21 01:38:30 PM PDT 24
Finished Apr 21 01:38:32 PM PDT 24
Peak memory 218904 kb
Host smart-7e2bfa85-efdf-44bd-bc32-73ad906c4aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109374417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3109374417
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.4171821831
Short name T625
Test name
Test status
Simulation time 36868352 ps
CPU time 1.12 seconds
Started Apr 21 01:38:29 PM PDT 24
Finished Apr 21 01:38:30 PM PDT 24
Peak memory 218724 kb
Host smart-5b98a382-ff07-4cb7-bf32-6aee66e0c169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171821831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.4171821831
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1780564304
Short name T685
Test name
Test status
Simulation time 35676217 ps
CPU time 1.25 seconds
Started Apr 21 01:38:32 PM PDT 24
Finished Apr 21 01:38:34 PM PDT 24
Peak memory 219808 kb
Host smart-42046253-ff2f-472a-8362-766a336fb4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780564304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1780564304
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3679475934
Short name T57
Test name
Test status
Simulation time 44568892 ps
CPU time 1.16 seconds
Started Apr 21 01:36:01 PM PDT 24
Finished Apr 21 01:36:03 PM PDT 24
Peak memory 216088 kb
Host smart-d68b6825-b725-4222-935e-7c3f8d8cac46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679475934 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3679475934
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.341523076
Short name T401
Test name
Test status
Simulation time 18973897 ps
CPU time 1.02 seconds
Started Apr 21 01:36:05 PM PDT 24
Finished Apr 21 01:36:06 PM PDT 24
Peak memory 215192 kb
Host smart-0a5b4d88-4926-436a-b966-a2c0c4cb09f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341523076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.341523076
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.392944374
Short name T571
Test name
Test status
Simulation time 14782678 ps
CPU time 0.82 seconds
Started Apr 21 01:36:05 PM PDT 24
Finished Apr 21 01:36:06 PM PDT 24
Peak memory 215800 kb
Host smart-47fad42f-2ba0-40d1-a666-87c8a9d75239
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392944374 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.392944374
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2172697086
Short name T119
Test name
Test status
Simulation time 46699008 ps
CPU time 1.07 seconds
Started Apr 21 01:36:04 PM PDT 24
Finished Apr 21 01:36:06 PM PDT 24
Peak memory 217080 kb
Host smart-e8a86a82-b6bb-4a3e-b00e-2cdbc8ab4656
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172697086 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2172697086
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.88073686
Short name T526
Test name
Test status
Simulation time 20165470 ps
CPU time 1.08 seconds
Started Apr 21 01:36:08 PM PDT 24
Finished Apr 21 01:36:10 PM PDT 24
Peak memory 218824 kb
Host smart-b4555890-24fe-4214-9076-b8a2cce1e87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88073686 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.88073686
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.4029809520
Short name T599
Test name
Test status
Simulation time 64734310 ps
CPU time 2.39 seconds
Started Apr 21 01:36:01 PM PDT 24
Finished Apr 21 01:36:04 PM PDT 24
Peak memory 220232 kb
Host smart-1c01a247-e6d8-4ef3-b231-1597640a5850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029809520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.4029809520
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3692146230
Short name T570
Test name
Test status
Simulation time 24938961 ps
CPU time 1 seconds
Started Apr 21 01:36:00 PM PDT 24
Finished Apr 21 01:36:01 PM PDT 24
Peak memory 215760 kb
Host smart-1d9f64c9-7ef0-4cd1-822b-c4eff9a78ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692146230 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3692146230
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3329157427
Short name T338
Test name
Test status
Simulation time 26604455 ps
CPU time 0.95 seconds
Started Apr 21 01:36:05 PM PDT 24
Finished Apr 21 01:36:06 PM PDT 24
Peak memory 215632 kb
Host smart-802ecd67-1934-4c2e-9249-35fd7b517eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329157427 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3329157427
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2889623400
Short name T687
Test name
Test status
Simulation time 233022532 ps
CPU time 4.85 seconds
Started Apr 21 01:36:02 PM PDT 24
Finished Apr 21 01:36:08 PM PDT 24
Peak memory 215604 kb
Host smart-57e12168-7a49-48a6-8a47-85098af0cc28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889623400 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2889623400
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1351000743
Short name T281
Test name
Test status
Simulation time 279820523179 ps
CPU time 1824.34 seconds
Started Apr 21 01:36:02 PM PDT 24
Finished Apr 21 02:06:28 PM PDT 24
Peak memory 228608 kb
Host smart-f166def4-0025-4cb3-8061-ca2cd3ce9c6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351000743 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1351000743
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3849869106
Short name T657
Test name
Test status
Simulation time 46207351 ps
CPU time 1.57 seconds
Started Apr 21 01:38:31 PM PDT 24
Finished Apr 21 01:38:33 PM PDT 24
Peak memory 217324 kb
Host smart-7f6dafc0-2d16-4acc-8a0b-e86901311b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849869106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3849869106
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3175598384
Short name T269
Test name
Test status
Simulation time 8103647364 ps
CPU time 115.28 seconds
Started Apr 21 01:38:33 PM PDT 24
Finished Apr 21 01:40:28 PM PDT 24
Peak memory 220684 kb
Host smart-616e29ca-2a63-4086-a3b2-25c443e640ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175598384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3175598384
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1916022103
Short name T652
Test name
Test status
Simulation time 72472656 ps
CPU time 1.39 seconds
Started Apr 21 01:38:31 PM PDT 24
Finished Apr 21 01:38:33 PM PDT 24
Peak memory 218768 kb
Host smart-0f97de05-79a3-4ccd-9d6e-d9e7a103f4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916022103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1916022103
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.4005525652
Short name T630
Test name
Test status
Simulation time 95040211 ps
CPU time 0.98 seconds
Started Apr 21 01:38:33 PM PDT 24
Finished Apr 21 01:38:34 PM PDT 24
Peak memory 217368 kb
Host smart-714fa995-a762-46e7-824f-e68767ad0f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005525652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.4005525652
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1800685682
Short name T637
Test name
Test status
Simulation time 80800192 ps
CPU time 2.73 seconds
Started Apr 21 01:38:32 PM PDT 24
Finished Apr 21 01:38:35 PM PDT 24
Peak memory 218684 kb
Host smart-5da90809-b287-416b-89c4-918b9cf9c9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800685682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1800685682
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3784473390
Short name T794
Test name
Test status
Simulation time 57223921 ps
CPU time 1.26 seconds
Started Apr 21 01:38:36 PM PDT 24
Finished Apr 21 01:38:38 PM PDT 24
Peak memory 219876 kb
Host smart-e6af11cd-9e9c-4f54-bd81-a0dafbddf1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784473390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3784473390
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.764917479
Short name T726
Test name
Test status
Simulation time 89585336 ps
CPU time 1.08 seconds
Started Apr 21 01:38:34 PM PDT 24
Finished Apr 21 01:38:35 PM PDT 24
Peak memory 217236 kb
Host smart-bafb0758-f27c-4bde-9b84-20b46658110e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764917479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.764917479
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2349910494
Short name T802
Test name
Test status
Simulation time 65581758 ps
CPU time 1.34 seconds
Started Apr 21 01:38:35 PM PDT 24
Finished Apr 21 01:38:37 PM PDT 24
Peak memory 218312 kb
Host smart-322dde33-d915-4305-96c6-aa8612a34252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349910494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2349910494
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1356406284
Short name T507
Test name
Test status
Simulation time 43378025 ps
CPU time 1.56 seconds
Started Apr 21 01:38:41 PM PDT 24
Finished Apr 21 01:38:43 PM PDT 24
Peak memory 218604 kb
Host smart-678be183-5392-41f9-a281-119d441f5ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356406284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1356406284
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3780638587
Short name T817
Test name
Test status
Simulation time 58721543 ps
CPU time 1.17 seconds
Started Apr 21 01:36:07 PM PDT 24
Finished Apr 21 01:36:09 PM PDT 24
Peak memory 215976 kb
Host smart-2b27f382-c843-4c5e-b1c0-22323ad82996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780638587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3780638587
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.4113187850
Short name T335
Test name
Test status
Simulation time 15209080 ps
CPU time 0.96 seconds
Started Apr 21 01:36:09 PM PDT 24
Finished Apr 21 01:36:10 PM PDT 24
Peak memory 215588 kb
Host smart-af130597-bbc1-4470-b86d-3afeac2d9de4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113187850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.4113187850
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.4024387063
Short name T812
Test name
Test status
Simulation time 41115009 ps
CPU time 0.88 seconds
Started Apr 21 01:36:04 PM PDT 24
Finished Apr 21 01:36:05 PM PDT 24
Peak memory 207628 kb
Host smart-dbe22bf6-cdbb-45ce-a0a5-c7265521f3be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024387063 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.4024387063
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_genbits.3938654547
Short name T13
Test name
Test status
Simulation time 80333017 ps
CPU time 1.31 seconds
Started Apr 21 01:36:05 PM PDT 24
Finished Apr 21 01:36:06 PM PDT 24
Peak memory 218564 kb
Host smart-1787c37a-0212-473d-9e5d-97239053f5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938654547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3938654547
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2316314831
Short name T79
Test name
Test status
Simulation time 23245931 ps
CPU time 1.07 seconds
Started Apr 21 01:36:05 PM PDT 24
Finished Apr 21 01:36:06 PM PDT 24
Peak memory 215932 kb
Host smart-f9e9bcb1-ea56-4c17-981c-7394f14ce21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316314831 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2316314831
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3524237000
Short name T298
Test name
Test status
Simulation time 24306807 ps
CPU time 0.89 seconds
Started Apr 21 01:36:07 PM PDT 24
Finished Apr 21 01:36:09 PM PDT 24
Peak memory 207316 kb
Host smart-d8218946-90f0-47a8-9b89-8078f4887f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524237000 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3524237000
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.4283018935
Short name T647
Test name
Test status
Simulation time 335306647 ps
CPU time 6.44 seconds
Started Apr 21 01:36:04 PM PDT 24
Finished Apr 21 01:36:11 PM PDT 24
Peak memory 215576 kb
Host smart-ad104481-da95-444e-98e7-38944b73c230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283018935 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.4283018935
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2790013456
Short name T761
Test name
Test status
Simulation time 587690375572 ps
CPU time 998.77 seconds
Started Apr 21 01:36:10 PM PDT 24
Finished Apr 21 01:52:49 PM PDT 24
Peak memory 221208 kb
Host smart-0991fbe1-6eea-406f-b8ac-e3eeb9dbf822
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790013456 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2790013456
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2570951560
Short name T25
Test name
Test status
Simulation time 78579665 ps
CPU time 1.22 seconds
Started Apr 21 01:38:34 PM PDT 24
Finished Apr 21 01:38:36 PM PDT 24
Peak memory 217308 kb
Host smart-4b4b85ad-d469-45be-bf8f-5733399e7462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570951560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2570951560
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.292989150
Short name T285
Test name
Test status
Simulation time 47727277 ps
CPU time 1.68 seconds
Started Apr 21 01:38:34 PM PDT 24
Finished Apr 21 01:38:36 PM PDT 24
Peak memory 218664 kb
Host smart-bf55f6a0-5e7b-4b37-9b04-e0d0f5fbfffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292989150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.292989150
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2534488942
Short name T422
Test name
Test status
Simulation time 152573695 ps
CPU time 3.46 seconds
Started Apr 21 01:38:38 PM PDT 24
Finished Apr 21 01:38:41 PM PDT 24
Peak memory 220244 kb
Host smart-04c36cc8-f308-46c1-9dbe-ae3499f4a9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534488942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2534488942
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.613360804
Short name T493
Test name
Test status
Simulation time 104853137 ps
CPU time 1.21 seconds
Started Apr 21 01:38:36 PM PDT 24
Finished Apr 21 01:38:38 PM PDT 24
Peak memory 218788 kb
Host smart-bc2641c7-008b-485e-8706-1b26c706399a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613360804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.613360804
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.4227004642
Short name T664
Test name
Test status
Simulation time 80031224 ps
CPU time 1.24 seconds
Started Apr 21 01:38:33 PM PDT 24
Finished Apr 21 01:38:35 PM PDT 24
Peak memory 218784 kb
Host smart-0b06e2ba-deaf-4bf1-812a-fef25b68fe6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227004642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.4227004642
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3065538864
Short name T545
Test name
Test status
Simulation time 33202665 ps
CPU time 1.26 seconds
Started Apr 21 01:38:34 PM PDT 24
Finished Apr 21 01:38:36 PM PDT 24
Peak memory 218412 kb
Host smart-242365c7-2a23-439d-98c3-9322bafc9939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065538864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3065538864
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.277445163
Short name T406
Test name
Test status
Simulation time 100243793 ps
CPU time 1.43 seconds
Started Apr 21 01:38:38 PM PDT 24
Finished Apr 21 01:38:39 PM PDT 24
Peak memory 218964 kb
Host smart-69c282bd-dc30-43a6-8f79-1d9fc4ecee7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277445163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.277445163
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1047781865
Short name T86
Test name
Test status
Simulation time 115811854 ps
CPU time 1.32 seconds
Started Apr 21 01:38:37 PM PDT 24
Finished Apr 21 01:38:38 PM PDT 24
Peak memory 218688 kb
Host smart-a913233e-e2f2-477a-98a3-7728796aec93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047781865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1047781865
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.646176789
Short name T68
Test name
Test status
Simulation time 33079298 ps
CPU time 1.43 seconds
Started Apr 21 01:38:37 PM PDT 24
Finished Apr 21 01:38:38 PM PDT 24
Peak memory 217264 kb
Host smart-8b44bd04-278f-4db8-8839-cd13baf57933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646176789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.646176789
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2919780605
Short name T22
Test name
Test status
Simulation time 312638370 ps
CPU time 1.41 seconds
Started Apr 21 01:38:36 PM PDT 24
Finished Apr 21 01:38:38 PM PDT 24
Peak memory 218932 kb
Host smart-1199482f-f9b6-45ab-af66-b579494ea600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919780605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2919780605
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2260923477
Short name T752
Test name
Test status
Simulation time 22397197 ps
CPU time 1.22 seconds
Started Apr 21 01:36:14 PM PDT 24
Finished Apr 21 01:36:15 PM PDT 24
Peak memory 216012 kb
Host smart-0987e8da-1205-40ea-b394-26c1323fe027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260923477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2260923477
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2404981854
Short name T697
Test name
Test status
Simulation time 62907164 ps
CPU time 0.92 seconds
Started Apr 21 01:36:11 PM PDT 24
Finished Apr 21 01:36:12 PM PDT 24
Peak memory 206964 kb
Host smart-2ae5fbb9-813e-4a9d-ba02-a1bd104736bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404981854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2404981854
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_err.3371797695
Short name T619
Test name
Test status
Simulation time 39141365 ps
CPU time 1.08 seconds
Started Apr 21 01:36:10 PM PDT 24
Finished Apr 21 01:36:12 PM PDT 24
Peak memory 217644 kb
Host smart-826443a1-c5ca-4ea7-b80f-701cb86b92ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371797695 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3371797695
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.4289204429
Short name T569
Test name
Test status
Simulation time 36931207 ps
CPU time 1.44 seconds
Started Apr 21 01:36:10 PM PDT 24
Finished Apr 21 01:36:11 PM PDT 24
Peak memory 218856 kb
Host smart-5b6bca01-967b-4983-9ad1-6fd045825725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289204429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.4289204429
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3672504582
Short name T612
Test name
Test status
Simulation time 19904165 ps
CPU time 1.12 seconds
Started Apr 21 01:36:08 PM PDT 24
Finished Apr 21 01:36:10 PM PDT 24
Peak memory 216232 kb
Host smart-adbc24dd-050b-47d5-9c79-757292dc704a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672504582 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3672504582
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.296664364
Short name T540
Test name
Test status
Simulation time 36314577 ps
CPU time 0.89 seconds
Started Apr 21 01:36:09 PM PDT 24
Finished Apr 21 01:36:10 PM PDT 24
Peak memory 215644 kb
Host smart-28f236c2-b7bf-4a84-8f30-2e8a93ff8bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296664364 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.296664364
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3914239151
Short name T420
Test name
Test status
Simulation time 150967730 ps
CPU time 3.36 seconds
Started Apr 21 01:36:09 PM PDT 24
Finished Apr 21 01:36:13 PM PDT 24
Peak memory 218528 kb
Host smart-adf10d7a-795e-4ec8-81c5-8c37e586abe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914239151 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3914239151
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.137535163
Short name T201
Test name
Test status
Simulation time 95666309464 ps
CPU time 1019.74 seconds
Started Apr 21 01:36:08 PM PDT 24
Finished Apr 21 01:53:08 PM PDT 24
Peak memory 221420 kb
Host smart-e6b1569f-97e1-4065-8e9f-0311f18fa5db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137535163 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.137535163
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.964675281
Short name T670
Test name
Test status
Simulation time 181152656 ps
CPU time 1.56 seconds
Started Apr 21 01:38:35 PM PDT 24
Finished Apr 21 01:38:37 PM PDT 24
Peak memory 218960 kb
Host smart-33f7ef92-315c-459b-8ad8-1ca682ffc4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964675281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.964675281
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.808664549
Short name T20
Test name
Test status
Simulation time 370619020 ps
CPU time 2.98 seconds
Started Apr 21 01:38:37 PM PDT 24
Finished Apr 21 01:38:41 PM PDT 24
Peak memory 217460 kb
Host smart-3f7d73c3-569f-453a-a112-9e13b7d969f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808664549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.808664549
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3518455604
Short name T48
Test name
Test status
Simulation time 99294882 ps
CPU time 0.92 seconds
Started Apr 21 01:38:37 PM PDT 24
Finished Apr 21 01:38:38 PM PDT 24
Peak memory 217260 kb
Host smart-066dc356-f121-4201-94ea-0496b3f348b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518455604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3518455604
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2277493384
Short name T449
Test name
Test status
Simulation time 74135736 ps
CPU time 1.27 seconds
Started Apr 21 01:38:37 PM PDT 24
Finished Apr 21 01:38:39 PM PDT 24
Peak memory 219316 kb
Host smart-9b5153bf-63ef-485d-be5f-775a60fda4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277493384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2277493384
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.860480164
Short name T264
Test name
Test status
Simulation time 47779045 ps
CPU time 1.84 seconds
Started Apr 21 01:38:36 PM PDT 24
Finished Apr 21 01:38:38 PM PDT 24
Peak memory 217384 kb
Host smart-3820ef88-928f-47e1-92cd-a04c5cb5a99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860480164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.860480164
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.4186492239
Short name T381
Test name
Test status
Simulation time 48289008 ps
CPU time 1.77 seconds
Started Apr 21 01:38:39 PM PDT 24
Finished Apr 21 01:38:41 PM PDT 24
Peak memory 218400 kb
Host smart-ca6cddd7-0184-4c59-b071-5088901507da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186492239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.4186492239
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3077677296
Short name T638
Test name
Test status
Simulation time 36870262 ps
CPU time 1.37 seconds
Started Apr 21 01:38:43 PM PDT 24
Finished Apr 21 01:38:44 PM PDT 24
Peak memory 217676 kb
Host smart-a7927ab0-132a-41d8-92f2-7d6004570378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077677296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3077677296
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1754676042
Short name T698
Test name
Test status
Simulation time 40931051 ps
CPU time 1.06 seconds
Started Apr 21 01:38:37 PM PDT 24
Finished Apr 21 01:38:39 PM PDT 24
Peak memory 217400 kb
Host smart-0713e9f7-2dc0-48b5-992b-8e0bd1cd4c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754676042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1754676042
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2404848248
Short name T280
Test name
Test status
Simulation time 36418713 ps
CPU time 1.33 seconds
Started Apr 21 01:38:43 PM PDT 24
Finished Apr 21 01:38:45 PM PDT 24
Peak memory 216812 kb
Host smart-abfa2dae-3ffd-418e-960e-87555540b3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404848248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2404848248
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3475578624
Short name T645
Test name
Test status
Simulation time 54537451 ps
CPU time 1.29 seconds
Started Apr 21 01:38:43 PM PDT 24
Finished Apr 21 01:38:45 PM PDT 24
Peak memory 218264 kb
Host smart-78fbc16c-9529-4e26-9df1-5adaf801b48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475578624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3475578624
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2631629630
Short name T135
Test name
Test status
Simulation time 47012039 ps
CPU time 1.19 seconds
Started Apr 21 01:36:14 PM PDT 24
Finished Apr 21 01:36:15 PM PDT 24
Peak memory 216052 kb
Host smart-51c1d5e6-4725-4098-a0eb-20552eea166f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631629630 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2631629630
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1646586921
Short name T618
Test name
Test status
Simulation time 18498435 ps
CPU time 0.95 seconds
Started Apr 21 01:36:12 PM PDT 24
Finished Apr 21 01:36:13 PM PDT 24
Peak memory 215244 kb
Host smart-63e55fe2-bf72-44e5-9946-584236e3fc0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646586921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1646586921
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1402202037
Short name T453
Test name
Test status
Simulation time 38293599 ps
CPU time 0.87 seconds
Started Apr 21 01:36:13 PM PDT 24
Finished Apr 21 01:36:15 PM PDT 24
Peak memory 215832 kb
Host smart-b7e30f8a-a3a5-42aa-8f46-f9c2763f0cb2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402202037 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1402202037
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3661197425
Short name T167
Test name
Test status
Simulation time 58234201 ps
CPU time 1.14 seconds
Started Apr 21 01:36:12 PM PDT 24
Finished Apr 21 01:36:14 PM PDT 24
Peak memory 217352 kb
Host smart-0ec6c6d3-b0ef-41e2-a3f3-d6631adffca1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661197425 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3661197425
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3603582043
Short name T147
Test name
Test status
Simulation time 18717736 ps
CPU time 1.14 seconds
Started Apr 21 01:36:14 PM PDT 24
Finished Apr 21 01:36:16 PM PDT 24
Peak memory 224420 kb
Host smart-6fab0501-bbbf-42b8-b324-ca68d574be7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603582043 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3603582043
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2586781122
Short name T733
Test name
Test status
Simulation time 70550412 ps
CPU time 1.29 seconds
Started Apr 21 01:36:15 PM PDT 24
Finished Apr 21 01:36:16 PM PDT 24
Peak memory 217160 kb
Host smart-750b6b12-ade8-402a-80c4-3909f8c0d95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586781122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2586781122
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.433842936
Short name T394
Test name
Test status
Simulation time 22067399 ps
CPU time 1.09 seconds
Started Apr 21 01:36:12 PM PDT 24
Finished Apr 21 01:36:13 PM PDT 24
Peak memory 215940 kb
Host smart-e3676362-2ce8-4bc8-a57a-36d8db09096f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433842936 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.433842936
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2424686132
Short name T332
Test name
Test status
Simulation time 18838715 ps
CPU time 1 seconds
Started Apr 21 01:36:14 PM PDT 24
Finished Apr 21 01:36:16 PM PDT 24
Peak memory 215608 kb
Host smart-ffeeb1a5-0b8f-4b64-ba98-dcd63523e65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424686132 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2424686132
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2002539911
Short name T395
Test name
Test status
Simulation time 254993409 ps
CPU time 5.21 seconds
Started Apr 21 01:36:14 PM PDT 24
Finished Apr 21 01:36:19 PM PDT 24
Peak memory 215564 kb
Host smart-fe55ace3-b1a8-4231-a78d-b1b80bbed837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002539911 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2002539911
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/270.edn_genbits.3478748359
Short name T587
Test name
Test status
Simulation time 47316101 ps
CPU time 1.16 seconds
Started Apr 21 01:38:35 PM PDT 24
Finished Apr 21 01:38:37 PM PDT 24
Peak memory 217576 kb
Host smart-4d196794-6aff-459a-a28e-4cec0fd25ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478748359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3478748359
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.4219045865
Short name T292
Test name
Test status
Simulation time 49643141 ps
CPU time 1.28 seconds
Started Apr 21 01:38:36 PM PDT 24
Finished Apr 21 01:38:38 PM PDT 24
Peak memory 217384 kb
Host smart-38b8b33e-d2bc-41d1-bb1a-3d747191a384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219045865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.4219045865
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3697831349
Short name T719
Test name
Test status
Simulation time 75002759 ps
CPU time 0.93 seconds
Started Apr 21 01:38:36 PM PDT 24
Finished Apr 21 01:38:37 PM PDT 24
Peak memory 219176 kb
Host smart-b6e57248-b0dd-4747-8d24-524307fd71dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697831349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3697831349
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.4074756574
Short name T665
Test name
Test status
Simulation time 51228883 ps
CPU time 1.33 seconds
Started Apr 21 01:38:42 PM PDT 24
Finished Apr 21 01:38:44 PM PDT 24
Peak memory 218908 kb
Host smart-03618139-8a00-4fb7-bfbe-39ab5a803a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074756574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.4074756574
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.256024381
Short name T397
Test name
Test status
Simulation time 119369116 ps
CPU time 1.39 seconds
Started Apr 21 01:38:37 PM PDT 24
Finished Apr 21 01:38:39 PM PDT 24
Peak memory 218988 kb
Host smart-d9e60c64-63bc-4b8d-9a32-fa22df960289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256024381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.256024381
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.253778598
Short name T600
Test name
Test status
Simulation time 42615710 ps
CPU time 1.66 seconds
Started Apr 21 01:38:41 PM PDT 24
Finished Apr 21 01:38:43 PM PDT 24
Peak memory 219792 kb
Host smart-94fb6f0a-765e-4957-8965-dc15828233da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253778598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.253778598
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3941392675
Short name T596
Test name
Test status
Simulation time 95071167 ps
CPU time 2.1 seconds
Started Apr 21 01:38:40 PM PDT 24
Finished Apr 21 01:38:42 PM PDT 24
Peak memory 219880 kb
Host smart-3b8bd5db-03a1-4743-ba4f-b0c704bcab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941392675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3941392675
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.599499946
Short name T374
Test name
Test status
Simulation time 175740203 ps
CPU time 1.14 seconds
Started Apr 21 01:38:43 PM PDT 24
Finished Apr 21 01:38:45 PM PDT 24
Peak memory 217420 kb
Host smart-e9def643-0e0d-4c5e-899b-dbe7aae3d791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599499946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.599499946
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3032471046
Short name T52
Test name
Test status
Simulation time 51237508 ps
CPU time 1.46 seconds
Started Apr 21 01:38:40 PM PDT 24
Finished Apr 21 01:38:42 PM PDT 24
Peak memory 218620 kb
Host smart-6fb973fc-1abf-4498-8cc8-621da7e4022c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032471046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3032471046
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.4000390335
Short name T389
Test name
Test status
Simulation time 82905015 ps
CPU time 1.04 seconds
Started Apr 21 01:38:42 PM PDT 24
Finished Apr 21 01:38:43 PM PDT 24
Peak memory 217384 kb
Host smart-ff56bbc3-0e12-4d3b-a4a2-0b6f796a64ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000390335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.4000390335
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3360825028
Short name T757
Test name
Test status
Simulation time 29390559 ps
CPU time 1.18 seconds
Started Apr 21 01:36:22 PM PDT 24
Finished Apr 21 01:36:23 PM PDT 24
Peak memory 215884 kb
Host smart-501bf787-1be8-4ee7-bbba-cb150455f283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360825028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3360825028
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1090079392
Short name T375
Test name
Test status
Simulation time 17090394 ps
CPU time 0.92 seconds
Started Apr 21 01:36:18 PM PDT 24
Finished Apr 21 01:36:20 PM PDT 24
Peak memory 215204 kb
Host smart-a6702c35-c8df-40c7-95dc-dc217f4f13d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090079392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1090079392
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.84059671
Short name T132
Test name
Test status
Simulation time 11350914 ps
CPU time 0.87 seconds
Started Apr 21 01:36:16 PM PDT 24
Finished Apr 21 01:36:18 PM PDT 24
Peak memory 215804 kb
Host smart-38f24019-9e12-46bc-a5f8-436484b2eb14
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84059671 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.84059671
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1207917392
Short name T445
Test name
Test status
Simulation time 23662370 ps
CPU time 0.99 seconds
Started Apr 21 01:36:17 PM PDT 24
Finished Apr 21 01:36:19 PM PDT 24
Peak memory 218320 kb
Host smart-9bbb979b-3a95-488d-b1a8-d0272ddfc669
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207917392 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1207917392
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.748551368
Short name T393
Test name
Test status
Simulation time 18689394 ps
CPU time 1.1 seconds
Started Apr 21 01:36:16 PM PDT 24
Finished Apr 21 01:36:18 PM PDT 24
Peak memory 218640 kb
Host smart-964d5400-8755-4668-8e3f-f9b96eae3f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748551368 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.748551368
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2367961519
Short name T415
Test name
Test status
Simulation time 28393324 ps
CPU time 1.29 seconds
Started Apr 21 01:36:22 PM PDT 24
Finished Apr 21 01:36:24 PM PDT 24
Peak memory 217552 kb
Host smart-c96e73de-c5c0-43db-9be5-7e1baef0c301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367961519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2367961519
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.872959392
Short name T40
Test name
Test status
Simulation time 20025268 ps
CPU time 1.02 seconds
Started Apr 21 01:36:16 PM PDT 24
Finished Apr 21 01:36:17 PM PDT 24
Peak memory 216116 kb
Host smart-36a08211-e315-463a-95d1-abe94ec0a3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872959392 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.872959392
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.564922157
Short name T513
Test name
Test status
Simulation time 16351829 ps
CPU time 1 seconds
Started Apr 21 01:36:18 PM PDT 24
Finished Apr 21 01:36:19 PM PDT 24
Peak memory 215636 kb
Host smart-486d88d3-2cde-4908-bf63-ad69d0f99ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564922157 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.564922157
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.42082325
Short name T595
Test name
Test status
Simulation time 657733857 ps
CPU time 1.97 seconds
Started Apr 21 01:36:18 PM PDT 24
Finished Apr 21 01:36:20 PM PDT 24
Peak memory 215696 kb
Host smart-0e0f4494-a365-4407-b133-0604a3a10bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42082325 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.42082325
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1993752650
Short name T546
Test name
Test status
Simulation time 121530304514 ps
CPU time 1157.02 seconds
Started Apr 21 01:36:17 PM PDT 24
Finished Apr 21 01:55:34 PM PDT 24
Peak memory 224336 kb
Host smart-31756e25-9337-441b-82be-8e83f47a1a0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993752650 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1993752650
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3538451535
Short name T829
Test name
Test status
Simulation time 115419450 ps
CPU time 1.41 seconds
Started Apr 21 01:38:42 PM PDT 24
Finished Apr 21 01:38:44 PM PDT 24
Peak memory 220056 kb
Host smart-942a9eb5-ff0f-4780-b423-ce92d1fad039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538451535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3538451535
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.557724082
Short name T564
Test name
Test status
Simulation time 69396537 ps
CPU time 1.66 seconds
Started Apr 21 01:38:42 PM PDT 24
Finished Apr 21 01:38:44 PM PDT 24
Peak memory 218752 kb
Host smart-c23b69c5-2c4f-4fe2-9299-4db36b1a7552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557724082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.557724082
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3229907391
Short name T340
Test name
Test status
Simulation time 73048569 ps
CPU time 1.21 seconds
Started Apr 21 01:38:40 PM PDT 24
Finished Apr 21 01:38:42 PM PDT 24
Peak memory 217268 kb
Host smart-369b993f-e850-471d-92cc-41568ec81381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229907391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3229907391
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2388115992
Short name T456
Test name
Test status
Simulation time 173964300 ps
CPU time 1.31 seconds
Started Apr 21 01:38:45 PM PDT 24
Finished Apr 21 01:38:47 PM PDT 24
Peak memory 215644 kb
Host smart-9c918823-910e-488d-a171-873ce3e41bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388115992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2388115992
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3203051496
Short name T311
Test name
Test status
Simulation time 34751733 ps
CPU time 1.3 seconds
Started Apr 21 01:38:42 PM PDT 24
Finished Apr 21 01:38:44 PM PDT 24
Peak memory 218628 kb
Host smart-4d930bc4-9b34-4708-8d30-000b20b2782d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203051496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3203051496
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3029009599
Short name T532
Test name
Test status
Simulation time 88341586 ps
CPU time 1.11 seconds
Started Apr 21 01:38:44 PM PDT 24
Finished Apr 21 01:38:45 PM PDT 24
Peak memory 217220 kb
Host smart-99f1b67f-ff19-4758-81cd-878e22ac945a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029009599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3029009599
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1665975483
Short name T261
Test name
Test status
Simulation time 31718076 ps
CPU time 1.02 seconds
Started Apr 21 01:38:42 PM PDT 24
Finished Apr 21 01:38:43 PM PDT 24
Peak memory 218804 kb
Host smart-523332c9-67f2-4869-a6d3-59bb6ee0388a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665975483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1665975483
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2090099720
Short name T360
Test name
Test status
Simulation time 57898002 ps
CPU time 2.44 seconds
Started Apr 21 01:38:45 PM PDT 24
Finished Apr 21 01:38:48 PM PDT 24
Peak memory 220108 kb
Host smart-46bb44b6-dc35-41a6-a5fb-03aa77afcefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090099720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2090099720
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3260041946
Short name T549
Test name
Test status
Simulation time 147444018 ps
CPU time 1.41 seconds
Started Apr 21 01:38:43 PM PDT 24
Finished Apr 21 01:38:45 PM PDT 24
Peak memory 217636 kb
Host smart-1f593bb7-9982-4bba-9fe4-8449c228a44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260041946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3260041946
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2234179937
Short name T247
Test name
Test status
Simulation time 29922982 ps
CPU time 1.23 seconds
Started Apr 21 01:36:20 PM PDT 24
Finished Apr 21 01:36:21 PM PDT 24
Peak memory 216092 kb
Host smart-d3db9dd8-963f-4c5a-9380-c0c8bfdec8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234179937 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2234179937
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2670333744
Short name T58
Test name
Test status
Simulation time 24003056 ps
CPU time 1.09 seconds
Started Apr 21 01:36:20 PM PDT 24
Finished Apr 21 01:36:21 PM PDT 24
Peak memory 207008 kb
Host smart-828f64e1-ea1f-41eb-bb0f-24609ac77679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670333744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2670333744
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1207563072
Short name T99
Test name
Test status
Simulation time 11818690 ps
CPU time 0.9 seconds
Started Apr 21 01:36:23 PM PDT 24
Finished Apr 21 01:36:25 PM PDT 24
Peak memory 216240 kb
Host smart-a6fd6b66-5eb0-495b-8b12-be779d087cd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207563072 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1207563072
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.4274236829
Short name T98
Test name
Test status
Simulation time 44486923 ps
CPU time 1.02 seconds
Started Apr 21 01:36:20 PM PDT 24
Finished Apr 21 01:36:22 PM PDT 24
Peak memory 217260 kb
Host smart-d8b0fd77-e3f6-4025-bcbf-6024a2f23989
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274236829 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.4274236829
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2350180519
Short name T440
Test name
Test status
Simulation time 68596323 ps
CPU time 0.99 seconds
Started Apr 21 01:36:20 PM PDT 24
Finished Apr 21 01:36:22 PM PDT 24
Peak memory 224168 kb
Host smart-a4465b51-deb1-4750-b461-ad2ff08c688c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350180519 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2350180519
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.753308786
Short name T557
Test name
Test status
Simulation time 34414405 ps
CPU time 1.05 seconds
Started Apr 21 01:36:22 PM PDT 24
Finished Apr 21 01:36:23 PM PDT 24
Peak memory 217520 kb
Host smart-7082dccb-9b31-41e6-b07e-22ed253071a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753308786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.753308786
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2237905200
Short name T768
Test name
Test status
Simulation time 39426679 ps
CPU time 1.01 seconds
Started Apr 21 01:36:21 PM PDT 24
Finished Apr 21 01:36:23 PM PDT 24
Peak memory 224364 kb
Host smart-78e54c56-ebe5-4ad4-b9cd-983ddea76a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237905200 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2237905200
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2280404799
Short name T423
Test name
Test status
Simulation time 48964878 ps
CPU time 0.86 seconds
Started Apr 21 01:36:22 PM PDT 24
Finished Apr 21 01:36:23 PM PDT 24
Peak memory 215420 kb
Host smart-293816a5-9e41-4ebc-80fe-c1ce0e78adfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280404799 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2280404799
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.212882770
Short name T355
Test name
Test status
Simulation time 123164189 ps
CPU time 0.93 seconds
Started Apr 21 01:36:16 PM PDT 24
Finished Apr 21 01:36:17 PM PDT 24
Peak memory 206936 kb
Host smart-0c9772fe-4b7e-4108-bc6e-ebf4f6dcba1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212882770 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.212882770
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2606689254
Short name T200
Test name
Test status
Simulation time 433429278990 ps
CPU time 1558.41 seconds
Started Apr 21 01:36:22 PM PDT 24
Finished Apr 21 02:02:21 PM PDT 24
Peak memory 224140 kb
Host smart-b219d87e-1ad2-42f4-894b-2104ce7537e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606689254 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2606689254
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2659926849
Short name T88
Test name
Test status
Simulation time 44149855 ps
CPU time 1.64 seconds
Started Apr 21 01:38:51 PM PDT 24
Finished Apr 21 01:38:53 PM PDT 24
Peak memory 217528 kb
Host smart-cc64efe3-3242-4d5f-ab7c-0c2ac997ba03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659926849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2659926849
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1517006047
Short name T294
Test name
Test status
Simulation time 27576586 ps
CPU time 1.3 seconds
Started Apr 21 01:38:47 PM PDT 24
Finished Apr 21 01:38:49 PM PDT 24
Peak memory 218716 kb
Host smart-265a95a3-d46e-4def-b3d2-dcd41e5456bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517006047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1517006047
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1446537699
Short name T590
Test name
Test status
Simulation time 188743290 ps
CPU time 1.71 seconds
Started Apr 21 01:38:51 PM PDT 24
Finished Apr 21 01:38:53 PM PDT 24
Peak memory 220288 kb
Host smart-b87a17f3-c48a-4d92-b963-dc5f98ef9263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446537699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1446537699
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.771247509
Short name T597
Test name
Test status
Simulation time 63171368 ps
CPU time 1.54 seconds
Started Apr 21 01:38:50 PM PDT 24
Finished Apr 21 01:38:52 PM PDT 24
Peak memory 218552 kb
Host smart-56e47c3c-c157-417f-8a0b-6f68e29ae46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771247509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.771247509
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1496955858
Short name T623
Test name
Test status
Simulation time 387263404 ps
CPU time 3.45 seconds
Started Apr 21 01:38:52 PM PDT 24
Finished Apr 21 01:38:56 PM PDT 24
Peak memory 220252 kb
Host smart-6762df72-1f09-4aca-a24b-9835f89ee2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496955858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1496955858
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2829929488
Short name T565
Test name
Test status
Simulation time 35402514 ps
CPU time 1.49 seconds
Started Apr 21 01:38:52 PM PDT 24
Finished Apr 21 01:38:54 PM PDT 24
Peak memory 218484 kb
Host smart-175da5eb-3e09-475f-91db-6d9fd9710a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829929488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2829929488
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1182309612
Short name T520
Test name
Test status
Simulation time 53594258 ps
CPU time 1.2 seconds
Started Apr 21 01:38:52 PM PDT 24
Finished Apr 21 01:38:53 PM PDT 24
Peak memory 218900 kb
Host smart-2fe6ade8-f7bf-41ae-b71c-8b4c828d51fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182309612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1182309612
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.878678650
Short name T674
Test name
Test status
Simulation time 59132267 ps
CPU time 1.19 seconds
Started Apr 21 01:38:52 PM PDT 24
Finished Apr 21 01:38:53 PM PDT 24
Peak memory 219184 kb
Host smart-fa91a7c8-42cd-4e31-b6a3-bf50107444b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878678650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.878678650
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3747521009
Short name T534
Test name
Test status
Simulation time 35911162 ps
CPU time 1.54 seconds
Started Apr 21 01:38:47 PM PDT 24
Finished Apr 21 01:38:48 PM PDT 24
Peak memory 217172 kb
Host smart-08525731-eaca-466e-9824-120b070c5f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747521009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3747521009
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1902151826
Short name T762
Test name
Test status
Simulation time 34154415 ps
CPU time 1.3 seconds
Started Apr 21 01:38:52 PM PDT 24
Finished Apr 21 01:38:53 PM PDT 24
Peak memory 217424 kb
Host smart-8a00c503-ab4b-42bc-ba56-d1ccc46645b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902151826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1902151826
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.4178235882
Short name T31
Test name
Test status
Simulation time 409886217 ps
CPU time 1.33 seconds
Started Apr 21 01:34:58 PM PDT 24
Finished Apr 21 01:35:00 PM PDT 24
Peak memory 216020 kb
Host smart-3f91499d-79fc-4db7-a2fa-44aa8f9f11a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178235882 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.4178235882
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.128375648
Short name T308
Test name
Test status
Simulation time 43692482 ps
CPU time 0.96 seconds
Started Apr 21 01:35:03 PM PDT 24
Finished Apr 21 01:35:05 PM PDT 24
Peak memory 206948 kb
Host smart-1cb39e0c-59d2-4206-abfa-780f3b62249a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128375648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.128375648
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1781122251
Short name T152
Test name
Test status
Simulation time 29500588 ps
CPU time 0.81 seconds
Started Apr 21 01:35:00 PM PDT 24
Finished Apr 21 01:35:01 PM PDT 24
Peak memory 216668 kb
Host smart-9a43afbb-fa32-4c5a-9af5-6dc3827169b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781122251 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1781122251
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1747048355
Short name T128
Test name
Test status
Simulation time 122528460 ps
CPU time 1.26 seconds
Started Apr 21 01:35:00 PM PDT 24
Finished Apr 21 01:35:01 PM PDT 24
Peak memory 217268 kb
Host smart-a34d80c7-55b1-43fc-bc44-c0e03fbcc03f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747048355 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1747048355
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2152617667
Short name T129
Test name
Test status
Simulation time 22386061 ps
CPU time 0.95 seconds
Started Apr 21 01:35:00 PM PDT 24
Finished Apr 21 01:35:01 PM PDT 24
Peak memory 218808 kb
Host smart-98b28516-e7a9-4111-a0ff-d4c322e20fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152617667 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2152617667
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.401071524
Short name T578
Test name
Test status
Simulation time 176877880 ps
CPU time 1.81 seconds
Started Apr 21 01:35:00 PM PDT 24
Finished Apr 21 01:35:02 PM PDT 24
Peak memory 219104 kb
Host smart-80f5be52-f3d0-4440-9526-3c1515ee434b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401071524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.401071524
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.472549538
Short name T319
Test name
Test status
Simulation time 22712842 ps
CPU time 1.12 seconds
Started Apr 21 01:34:58 PM PDT 24
Finished Apr 21 01:35:00 PM PDT 24
Peak memory 215880 kb
Host smart-7b584bb0-800e-4ec4-8195-7bcc273b7c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472549538 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.472549538
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.3575335320
Short name T30
Test name
Test status
Simulation time 51834113 ps
CPU time 1.07 seconds
Started Apr 21 01:35:00 PM PDT 24
Finished Apr 21 01:35:01 PM PDT 24
Peak memory 207400 kb
Host smart-9d55ef4a-ee42-41d4-9cfb-b6f30068a3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575335320 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3575335320
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.185139775
Short name T17
Test name
Test status
Simulation time 2098533350 ps
CPU time 4.97 seconds
Started Apr 21 01:35:02 PM PDT 24
Finished Apr 21 01:35:08 PM PDT 24
Peak memory 236216 kb
Host smart-8c46ca46-3b54-48db-beae-dbbff18fb85a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185139775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.185139775
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.1627765152
Short name T750
Test name
Test status
Simulation time 53252211 ps
CPU time 0.9 seconds
Started Apr 21 01:34:57 PM PDT 24
Finished Apr 21 01:34:58 PM PDT 24
Peak memory 215672 kb
Host smart-750ebe1f-fa33-4ed2-a68d-c3c071c58eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627765152 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1627765152
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1866018581
Short name T558
Test name
Test status
Simulation time 569454189 ps
CPU time 1.74 seconds
Started Apr 21 01:34:59 PM PDT 24
Finished Apr 21 01:35:01 PM PDT 24
Peak memory 215696 kb
Host smart-4a4842e6-f574-43fc-a475-abf08dbc8a0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866018581 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1866018581
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2589283040
Short name T505
Test name
Test status
Simulation time 971690832775 ps
CPU time 2095.65 seconds
Started Apr 21 01:34:59 PM PDT 24
Finished Apr 21 02:09:55 PM PDT 24
Peak memory 229912 kb
Host smart-5e30c5a9-2abb-4421-84af-3b21f72d3eb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589283040 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2589283040
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2605743530
Short name T254
Test name
Test status
Simulation time 230413170 ps
CPU time 1.42 seconds
Started Apr 21 01:36:25 PM PDT 24
Finished Apr 21 01:36:27 PM PDT 24
Peak memory 216104 kb
Host smart-1e00dff7-8d26-427b-a286-fbd1144b5007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605743530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2605743530
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3640829549
Short name T615
Test name
Test status
Simulation time 12095079 ps
CPU time 0.97 seconds
Started Apr 21 01:36:23 PM PDT 24
Finished Apr 21 01:36:24 PM PDT 24
Peak memory 207444 kb
Host smart-a1852b73-a8ad-4642-afb2-28bc0b980411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640829549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3640829549
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_err.1097339418
Short name T331
Test name
Test status
Simulation time 20073641 ps
CPU time 1.06 seconds
Started Apr 21 01:36:21 PM PDT 24
Finished Apr 21 01:36:23 PM PDT 24
Peak memory 218808 kb
Host smart-8b93d88d-9c9c-49f1-9313-4f6cec569305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097339418 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1097339418
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3972934098
Short name T788
Test name
Test status
Simulation time 153814402 ps
CPU time 1.02 seconds
Started Apr 21 01:36:25 PM PDT 24
Finished Apr 21 01:36:27 PM PDT 24
Peak memory 217324 kb
Host smart-e77176fd-44e7-43de-921f-6b2f1c32a076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972934098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3972934098
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.245774569
Short name T488
Test name
Test status
Simulation time 23813483 ps
CPU time 0.91 seconds
Started Apr 21 01:36:23 PM PDT 24
Finished Apr 21 01:36:25 PM PDT 24
Peak memory 215920 kb
Host smart-474adc01-692c-4a45-82cc-4ec51b564a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245774569 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.245774569
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1187078578
Short name T455
Test name
Test status
Simulation time 70199667 ps
CPU time 0.89 seconds
Started Apr 21 01:36:18 PM PDT 24
Finished Apr 21 01:36:19 PM PDT 24
Peak memory 215372 kb
Host smart-0b231458-270b-41a0-b7dd-2ead1006f8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187078578 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1187078578
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2086646288
Short name T446
Test name
Test status
Simulation time 177906597 ps
CPU time 2.34 seconds
Started Apr 21 01:36:25 PM PDT 24
Finished Apr 21 01:36:28 PM PDT 24
Peak memory 217276 kb
Host smart-213ddd0b-57a2-430f-b3c4-642cf23f3e57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086646288 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2086646288
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.26407763
Short name T441
Test name
Test status
Simulation time 65356277962 ps
CPU time 1621.81 seconds
Started Apr 21 01:36:22 PM PDT 24
Finished Apr 21 02:03:25 PM PDT 24
Peak memory 226496 kb
Host smart-ed303fbd-8b0c-4c3d-b70d-2a140d2ecda3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26407763 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.26407763
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.52419936
Short name T257
Test name
Test status
Simulation time 180750534 ps
CPU time 1.08 seconds
Started Apr 21 01:36:27 PM PDT 24
Finished Apr 21 01:36:28 PM PDT 24
Peak memory 216060 kb
Host smart-22452590-5e53-4918-a9c8-df75e08e5d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52419936 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.52419936
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2153356597
Short name T646
Test name
Test status
Simulation time 16049932 ps
CPU time 0.91 seconds
Started Apr 21 01:36:29 PM PDT 24
Finished Apr 21 01:36:30 PM PDT 24
Peak memory 206972 kb
Host smart-2137ee19-7ace-41bb-98aa-d6c809c2f2e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153356597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2153356597
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.1782262685
Short name T49
Test name
Test status
Simulation time 11192714 ps
CPU time 0.87 seconds
Started Apr 21 01:36:30 PM PDT 24
Finished Apr 21 01:36:31 PM PDT 24
Peak memory 215820 kb
Host smart-d59dfd0b-9826-4062-8058-907d6135b89f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782262685 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1782262685
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2401152084
Short name T700
Test name
Test status
Simulation time 85071826 ps
CPU time 1.15 seconds
Started Apr 21 01:36:27 PM PDT 24
Finished Apr 21 01:36:28 PM PDT 24
Peak memory 217312 kb
Host smart-cdf99cc8-bdd9-462a-bd4e-df7c7a3b8c5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401152084 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2401152084
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1288796985
Short name T139
Test name
Test status
Simulation time 23469512 ps
CPU time 1.05 seconds
Started Apr 21 01:36:24 PM PDT 24
Finished Apr 21 01:36:25 PM PDT 24
Peak memory 224376 kb
Host smart-625433be-4ddd-4797-bf7e-a1e75270d4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288796985 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1288796985
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1920395005
Short name T745
Test name
Test status
Simulation time 24468040 ps
CPU time 1.06 seconds
Started Apr 21 01:36:24 PM PDT 24
Finished Apr 21 01:36:25 PM PDT 24
Peak memory 217384 kb
Host smart-71ef5128-9619-44d3-8423-6efdfd9ee54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920395005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1920395005
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.800097394
Short name T35
Test name
Test status
Simulation time 21075551 ps
CPU time 1.05 seconds
Started Apr 21 01:36:24 PM PDT 24
Finished Apr 21 01:36:25 PM PDT 24
Peak memory 216096 kb
Host smart-6489dfe9-0334-4ca1-a1ba-2c6abb0201a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800097394 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.800097394
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3059043827
Short name T315
Test name
Test status
Simulation time 21590092 ps
CPU time 0.97 seconds
Started Apr 21 01:36:25 PM PDT 24
Finished Apr 21 01:36:26 PM PDT 24
Peak memory 215640 kb
Host smart-93ba47f2-99a6-4f9b-8c08-fafdaa78380f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059043827 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3059043827
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.4228813913
Short name T699
Test name
Test status
Simulation time 130688614 ps
CPU time 1.38 seconds
Started Apr 21 01:36:34 PM PDT 24
Finished Apr 21 01:36:36 PM PDT 24
Peak memory 217144 kb
Host smart-3517b31c-eabe-4d4a-97f3-6353184c7dd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228813913 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.4228813913
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.937103061
Short name T205
Test name
Test status
Simulation time 202571578015 ps
CPU time 1212.78 seconds
Started Apr 21 01:36:28 PM PDT 24
Finished Apr 21 01:56:41 PM PDT 24
Peak memory 223380 kb
Host smart-0c9d3bab-6770-4f72-8482-8d2fcd18be3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937103061 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.937103061
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.4275639046
Short name T140
Test name
Test status
Simulation time 87112933 ps
CPU time 1.1 seconds
Started Apr 21 01:36:25 PM PDT 24
Finished Apr 21 01:36:27 PM PDT 24
Peak memory 216116 kb
Host smart-a430c240-7cc4-415b-a71a-23d5a1af8182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275639046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.4275639046
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2619986085
Short name T26
Test name
Test status
Simulation time 16721387 ps
CPU time 0.98 seconds
Started Apr 21 01:36:31 PM PDT 24
Finished Apr 21 01:36:32 PM PDT 24
Peak memory 215176 kb
Host smart-158088ba-2290-42c1-b3ed-5e3cdd817f83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619986085 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2619986085
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.971519073
Short name T191
Test name
Test status
Simulation time 11177880 ps
CPU time 0.86 seconds
Started Apr 21 01:36:23 PM PDT 24
Finished Apr 21 01:36:25 PM PDT 24
Peak memory 215784 kb
Host smart-34e079fe-3122-44b2-b281-368fbf777607
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971519073 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.971519073
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.85331483
Short name T723
Test name
Test status
Simulation time 69758518 ps
CPU time 1.02 seconds
Started Apr 21 01:36:35 PM PDT 24
Finished Apr 21 01:36:36 PM PDT 24
Peak memory 217156 kb
Host smart-2e9dcbc6-987b-4aea-8b7c-74ad87c2a7c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85331483 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_dis
able_auto_req_mode.85331483
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.4243443321
Short name T172
Test name
Test status
Simulation time 44071265 ps
CPU time 1.2 seconds
Started Apr 21 01:36:28 PM PDT 24
Finished Apr 21 01:36:29 PM PDT 24
Peak memory 225768 kb
Host smart-a46e3ed8-a5f7-4d9f-8abd-8c71a38fcb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243443321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.4243443321
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3163089804
Short name T273
Test name
Test status
Simulation time 57489506 ps
CPU time 1.37 seconds
Started Apr 21 01:36:29 PM PDT 24
Finished Apr 21 01:36:30 PM PDT 24
Peak memory 220112 kb
Host smart-d5df3a35-ec0d-4181-8dee-cb2eebe7eb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163089804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3163089804
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1435759653
Short name T153
Test name
Test status
Simulation time 36800076 ps
CPU time 0.85 seconds
Started Apr 21 01:36:35 PM PDT 24
Finished Apr 21 01:36:36 PM PDT 24
Peak memory 215988 kb
Host smart-26f834d0-e8ad-4109-8082-1d3bddfe68a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435759653 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1435759653
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2824265382
Short name T324
Test name
Test status
Simulation time 31268269 ps
CPU time 0.99 seconds
Started Apr 21 01:36:30 PM PDT 24
Finished Apr 21 01:36:31 PM PDT 24
Peak memory 215668 kb
Host smart-2f66b89c-f5bb-4c10-b4c5-6835efb9a3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824265382 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2824265382
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3742453876
Short name T361
Test name
Test status
Simulation time 78594103 ps
CPU time 2.08 seconds
Started Apr 21 01:36:34 PM PDT 24
Finished Apr 21 01:36:36 PM PDT 24
Peak memory 217172 kb
Host smart-1e10b7ba-007c-4206-afa6-a73cfbb4614b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742453876 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3742453876
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.81025056
Short name T703
Test name
Test status
Simulation time 166440634484 ps
CPU time 1949.04 seconds
Started Apr 21 01:36:28 PM PDT 24
Finished Apr 21 02:08:57 PM PDT 24
Peak memory 226572 kb
Host smart-9ff56af1-cfe4-4b33-a851-5c4003ed3672
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81025056 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.81025056
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2231955150
Short name T773
Test name
Test status
Simulation time 45177563 ps
CPU time 1.19 seconds
Started Apr 21 01:36:27 PM PDT 24
Finished Apr 21 01:36:28 PM PDT 24
Peak memory 216096 kb
Host smart-5c675ca1-6707-413a-9d7f-47ae8fe7d35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231955150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2231955150
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1170545433
Short name T560
Test name
Test status
Simulation time 15143582 ps
CPU time 0.91 seconds
Started Apr 21 01:36:31 PM PDT 24
Finished Apr 21 01:36:32 PM PDT 24
Peak memory 207400 kb
Host smart-be95af79-fd83-4a46-917c-7cb5d052c97c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170545433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1170545433
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_err.917075703
Short name T80
Test name
Test status
Simulation time 19908624 ps
CPU time 1.07 seconds
Started Apr 21 01:36:29 PM PDT 24
Finished Apr 21 01:36:31 PM PDT 24
Peak memory 218840 kb
Host smart-35c14b03-af08-4769-ab71-1d0fed06c507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917075703 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.917075703
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.95867552
Short name T407
Test name
Test status
Simulation time 137130561 ps
CPU time 1.62 seconds
Started Apr 21 01:36:33 PM PDT 24
Finished Apr 21 01:36:35 PM PDT 24
Peak memory 218604 kb
Host smart-be82f8a3-0650-4205-90d1-e658bad0f7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95867552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.95867552
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3383402915
Short name T105
Test name
Test status
Simulation time 20582041 ps
CPU time 1.09 seconds
Started Apr 21 01:36:29 PM PDT 24
Finished Apr 21 01:36:30 PM PDT 24
Peak memory 216300 kb
Host smart-2f421a9a-07fb-4ca8-8356-90e8390eb088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383402915 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3383402915
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3759170397
Short name T758
Test name
Test status
Simulation time 17785222 ps
CPU time 0.96 seconds
Started Apr 21 01:36:27 PM PDT 24
Finished Apr 21 01:36:28 PM PDT 24
Peak memory 215672 kb
Host smart-cd3e03db-a086-4106-aa27-a3ae381b7894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759170397 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3759170397
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2690080939
Short name T785
Test name
Test status
Simulation time 271207913 ps
CPU time 5.19 seconds
Started Apr 21 01:36:34 PM PDT 24
Finished Apr 21 01:36:39 PM PDT 24
Peak memory 217140 kb
Host smart-02272732-cdce-4b64-b0ae-a21e2da0bbf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690080939 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2690080939
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.4083424769
Short name T834
Test name
Test status
Simulation time 356578945582 ps
CPU time 1759.66 seconds
Started Apr 21 01:36:28 PM PDT 24
Finished Apr 21 02:05:48 PM PDT 24
Peak memory 227952 kb
Host smart-92929de3-bd12-47b5-b639-290a8399c65d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083424769 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.4083424769
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1989628924
Short name T608
Test name
Test status
Simulation time 104434149 ps
CPU time 1.14 seconds
Started Apr 21 01:36:34 PM PDT 24
Finished Apr 21 01:36:36 PM PDT 24
Peak memory 216084 kb
Host smart-b54b07a6-5c58-4edf-96b9-2b899506b2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989628924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1989628924
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3983442762
Short name T411
Test name
Test status
Simulation time 61796934 ps
CPU time 0.87 seconds
Started Apr 21 01:36:34 PM PDT 24
Finished Apr 21 01:36:35 PM PDT 24
Peak memory 206944 kb
Host smart-438c0985-c1b7-4d86-8610-1986cb6257f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983442762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3983442762
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1472416104
Short name T178
Test name
Test status
Simulation time 28460309 ps
CPU time 0.8 seconds
Started Apr 21 01:36:34 PM PDT 24
Finished Apr 21 01:36:35 PM PDT 24
Peak memory 216628 kb
Host smart-b813310f-f165-4db4-8905-85322c26bd41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472416104 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1472416104
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3245092869
Short name T113
Test name
Test status
Simulation time 63054205 ps
CPU time 1.15 seconds
Started Apr 21 01:36:35 PM PDT 24
Finished Apr 21 01:36:37 PM PDT 24
Peak memory 217196 kb
Host smart-42cd2b98-63f0-4107-bfc0-805e490e5e51
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245092869 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3245092869
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2993423482
Short name T185
Test name
Test status
Simulation time 29726592 ps
CPU time 1.38 seconds
Started Apr 21 01:36:38 PM PDT 24
Finished Apr 21 01:36:40 PM PDT 24
Peak memory 226012 kb
Host smart-c2306d58-7e67-47b5-aba8-5e3d6eae1c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993423482 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2993423482
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.4236378237
Short name T276
Test name
Test status
Simulation time 148794209 ps
CPU time 1.21 seconds
Started Apr 21 01:36:31 PM PDT 24
Finished Apr 21 01:36:32 PM PDT 24
Peak memory 218876 kb
Host smart-5e007364-a280-40f0-ab6e-250b41aa3cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236378237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.4236378237
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_smoke.1099085874
Short name T339
Test name
Test status
Simulation time 15632048 ps
CPU time 0.96 seconds
Started Apr 21 01:36:34 PM PDT 24
Finished Apr 21 01:36:35 PM PDT 24
Peak memory 215644 kb
Host smart-4448aad1-d89a-4311-ab7d-a99dbc2417a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099085874 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1099085874
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2739866166
Short name T503
Test name
Test status
Simulation time 163985468 ps
CPU time 1.53 seconds
Started Apr 21 01:36:30 PM PDT 24
Finished Apr 21 01:36:32 PM PDT 24
Peak memory 217456 kb
Host smart-fbfb0e69-e06f-474f-a492-c138cc38a3ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739866166 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2739866166
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2027071996
Short name T352
Test name
Test status
Simulation time 47402604157 ps
CPU time 1162.1 seconds
Started Apr 21 01:36:30 PM PDT 24
Finished Apr 21 01:55:53 PM PDT 24
Peak memory 222240 kb
Host smart-79304fc0-2d75-4408-a5a6-16ea3ee7962b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027071996 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2027071996
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3454973892
Short name T691
Test name
Test status
Simulation time 98236209 ps
CPU time 1.16 seconds
Started Apr 21 01:36:41 PM PDT 24
Finished Apr 21 01:36:42 PM PDT 24
Peak memory 216080 kb
Host smart-15fb56fa-6139-4c3c-9124-a7cd842ecc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454973892 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3454973892
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3100907146
Short name T349
Test name
Test status
Simulation time 17578026 ps
CPU time 0.91 seconds
Started Apr 21 01:36:39 PM PDT 24
Finished Apr 21 01:36:40 PM PDT 24
Peak memory 206924 kb
Host smart-19b5a89e-eae2-43b3-8f20-f93185fb0b1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100907146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3100907146
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2528455081
Short name T634
Test name
Test status
Simulation time 23018363 ps
CPU time 0.85 seconds
Started Apr 21 01:36:39 PM PDT 24
Finished Apr 21 01:36:40 PM PDT 24
Peak memory 216592 kb
Host smart-bfc32b52-6e23-48cb-8bd8-cc3b1931aebc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528455081 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2528455081
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.54691442
Short name T126
Test name
Test status
Simulation time 111057212 ps
CPU time 1.09 seconds
Started Apr 21 01:36:37 PM PDT 24
Finished Apr 21 01:36:38 PM PDT 24
Peak memory 217132 kb
Host smart-786ef98e-0aef-4499-842c-21c7dc8e4f1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54691442 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_dis
able_auto_req_mode.54691442
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2924019662
Short name T102
Test name
Test status
Simulation time 24982139 ps
CPU time 0.96 seconds
Started Apr 21 01:36:39 PM PDT 24
Finished Apr 21 01:36:41 PM PDT 24
Peak memory 219856 kb
Host smart-3bd7fa17-827c-4883-ad0a-6ca44035e0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924019662 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2924019662
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.868103474
Short name T87
Test name
Test status
Simulation time 178772339 ps
CPU time 0.97 seconds
Started Apr 21 01:36:34 PM PDT 24
Finished Apr 21 01:36:35 PM PDT 24
Peak memory 217424 kb
Host smart-19ba1bff-bee8-4510-9dba-452635afa742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868103474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.868103474
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2032332540
Short name T826
Test name
Test status
Simulation time 19960566 ps
CPU time 1.07 seconds
Started Apr 21 01:36:34 PM PDT 24
Finished Apr 21 01:36:35 PM PDT 24
Peak memory 216212 kb
Host smart-18f63b37-72cd-4a34-8cec-608d4032d811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032332540 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2032332540
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2210659817
Short name T543
Test name
Test status
Simulation time 42730630 ps
CPU time 0.88 seconds
Started Apr 21 01:36:36 PM PDT 24
Finished Apr 21 01:36:37 PM PDT 24
Peak memory 215632 kb
Host smart-0ddf84af-bdb8-44fa-b5b8-50e2e06b74ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210659817 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2210659817
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2886836942
Short name T470
Test name
Test status
Simulation time 1154284064 ps
CPU time 2.26 seconds
Started Apr 21 01:36:36 PM PDT 24
Finished Apr 21 01:36:39 PM PDT 24
Peak memory 217360 kb
Host smart-8600b32a-da76-4e74-9e2d-d755d009ff42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886836942 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2886836942
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1006367967
Short name T402
Test name
Test status
Simulation time 120081985295 ps
CPU time 1912.17 seconds
Started Apr 21 01:36:33 PM PDT 24
Finished Apr 21 02:08:26 PM PDT 24
Peak memory 226760 kb
Host smart-52de756d-6b22-415e-a965-6ac40b78d61a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006367967 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1006367967
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3713155579
Short name T158
Test name
Test status
Simulation time 25768215 ps
CPU time 1.17 seconds
Started Apr 21 01:36:43 PM PDT 24
Finished Apr 21 01:36:44 PM PDT 24
Peak memory 216072 kb
Host smart-251072b9-14c6-493b-97b2-c715e381700b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713155579 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3713155579
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2465376544
Short name T475
Test name
Test status
Simulation time 15251320 ps
CPU time 0.91 seconds
Started Apr 21 01:36:42 PM PDT 24
Finished Apr 21 01:36:43 PM PDT 24
Peak memory 206928 kb
Host smart-9ac12aa8-8d7f-45ce-a029-bac2854b8bd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465376544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2465376544
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.838060226
Short name T163
Test name
Test status
Simulation time 11956592 ps
CPU time 0.92 seconds
Started Apr 21 01:36:41 PM PDT 24
Finished Apr 21 01:36:42 PM PDT 24
Peak memory 216844 kb
Host smart-9e76923e-26d4-4b5b-a301-6b796d056b84
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838060226 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.838060226
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2803928645
Short name T509
Test name
Test status
Simulation time 166077116 ps
CPU time 1.11 seconds
Started Apr 21 01:36:42 PM PDT 24
Finished Apr 21 01:36:44 PM PDT 24
Peak memory 218500 kb
Host smart-6959edd7-1598-48cb-af07-9843ad1e6be3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803928645 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2803928645
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2021465184
Short name T715
Test name
Test status
Simulation time 28423887 ps
CPU time 0.97 seconds
Started Apr 21 01:36:42 PM PDT 24
Finished Apr 21 01:36:43 PM PDT 24
Peak memory 224152 kb
Host smart-a3eb1dff-3aee-428e-8d56-e5268739fd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021465184 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2021465184
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1582082993
Short name T358
Test name
Test status
Simulation time 32235281 ps
CPU time 1.3 seconds
Started Apr 21 01:36:40 PM PDT 24
Finished Apr 21 01:36:42 PM PDT 24
Peak memory 217428 kb
Host smart-e26caf5e-ece5-4559-a73c-d204f87dcfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582082993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1582082993
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.460287285
Short name T780
Test name
Test status
Simulation time 22065628 ps
CPU time 1.05 seconds
Started Apr 21 01:36:37 PM PDT 24
Finished Apr 21 01:36:39 PM PDT 24
Peak memory 216172 kb
Host smart-f73ce84b-7375-4938-9d0d-e2963003cb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460287285 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.460287285
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3656835305
Short name T611
Test name
Test status
Simulation time 18957086 ps
CPU time 1 seconds
Started Apr 21 01:36:37 PM PDT 24
Finished Apr 21 01:36:38 PM PDT 24
Peak memory 215628 kb
Host smart-99d6731c-8275-44d6-b28d-550c19c7f388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656835305 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3656835305
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.4237847197
Short name T504
Test name
Test status
Simulation time 172684796 ps
CPU time 2.34 seconds
Started Apr 21 01:36:37 PM PDT 24
Finished Apr 21 01:36:40 PM PDT 24
Peak memory 215692 kb
Host smart-556cc065-44ba-4ef1-a7fe-ae03bf17cad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237847197 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.4237847197
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2988919441
Short name T198
Test name
Test status
Simulation time 60637578481 ps
CPU time 364.11 seconds
Started Apr 21 01:36:38 PM PDT 24
Finished Apr 21 01:42:43 PM PDT 24
Peak memory 221332 kb
Host smart-c9dfda72-91d0-472d-97fe-4cc30c2e335e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988919441 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2988919441
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.930891395
Short name T727
Test name
Test status
Simulation time 23355832 ps
CPU time 1.17 seconds
Started Apr 21 01:36:42 PM PDT 24
Finished Apr 21 01:36:44 PM PDT 24
Peak memory 216048 kb
Host smart-185278e9-e6a2-456b-9365-b4a4bd4bc3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930891395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.930891395
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2363265885
Short name T574
Test name
Test status
Simulation time 25724774 ps
CPU time 0.88 seconds
Started Apr 21 01:36:42 PM PDT 24
Finished Apr 21 01:36:43 PM PDT 24
Peak memory 206984 kb
Host smart-fd299c70-4319-47f4-a368-aa87e183ec17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363265885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2363265885
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.998020292
Short name T45
Test name
Test status
Simulation time 13238797 ps
CPU time 0.89 seconds
Started Apr 21 01:36:44 PM PDT 24
Finished Apr 21 01:36:46 PM PDT 24
Peak memory 216948 kb
Host smart-e0d99863-c7b2-4f44-a644-756dfd4f62db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998020292 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.998020292
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_err.2068100544
Short name T519
Test name
Test status
Simulation time 31365108 ps
CPU time 1.13 seconds
Started Apr 21 01:36:43 PM PDT 24
Finished Apr 21 01:36:44 PM PDT 24
Peak memory 229932 kb
Host smart-ebad7431-29b3-497b-9fa9-f270014b63b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068100544 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2068100544
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2326530380
Short name T378
Test name
Test status
Simulation time 64475163 ps
CPU time 1.72 seconds
Started Apr 21 01:36:41 PM PDT 24
Finished Apr 21 01:36:43 PM PDT 24
Peak memory 218668 kb
Host smart-a8962f91-3a1c-4726-8a49-31ecc61e7030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326530380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2326530380
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.4146682208
Short name T73
Test name
Test status
Simulation time 21407796 ps
CPU time 1.12 seconds
Started Apr 21 01:36:39 PM PDT 24
Finished Apr 21 01:36:40 PM PDT 24
Peak memory 224308 kb
Host smart-02481e81-14f5-41d7-b79d-c4ea1ae6f2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146682208 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.4146682208
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1345037004
Short name T662
Test name
Test status
Simulation time 37706308 ps
CPU time 0.88 seconds
Started Apr 21 01:36:41 PM PDT 24
Finished Apr 21 01:36:42 PM PDT 24
Peak memory 215632 kb
Host smart-ab1251cb-b942-491a-ad3e-e275cc3357a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345037004 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1345037004
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2128184605
Short name T499
Test name
Test status
Simulation time 429960277 ps
CPU time 3.08 seconds
Started Apr 21 01:36:42 PM PDT 24
Finished Apr 21 01:36:46 PM PDT 24
Peak memory 215644 kb
Host smart-5e511682-9638-4a46-a0cb-b226db6c4593
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128184605 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2128184605
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3002356151
Short name T547
Test name
Test status
Simulation time 64349152236 ps
CPU time 1536.94 seconds
Started Apr 21 01:36:41 PM PDT 24
Finished Apr 21 02:02:19 PM PDT 24
Peak memory 225472 kb
Host smart-f134ca16-9257-4f0b-8992-8030a1fa41d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002356151 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3002356151
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert_test.321422887
Short name T799
Test name
Test status
Simulation time 17038885 ps
CPU time 0.93 seconds
Started Apr 21 01:36:47 PM PDT 24
Finished Apr 21 01:36:48 PM PDT 24
Peak memory 215040 kb
Host smart-0d7d6514-2e3c-4f82-a07c-95ef5141eb2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321422887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.321422887
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3678310348
Short name T184
Test name
Test status
Simulation time 47853469 ps
CPU time 0.82 seconds
Started Apr 21 01:36:44 PM PDT 24
Finished Apr 21 01:36:45 PM PDT 24
Peak memory 216624 kb
Host smart-fa3c0b7f-7137-4ab4-bae9-13887da965ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678310348 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3678310348
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.4054968
Short name T124
Test name
Test status
Simulation time 31574498 ps
CPU time 1.21 seconds
Started Apr 21 01:36:44 PM PDT 24
Finished Apr 21 01:36:45 PM PDT 24
Peak memory 217256 kb
Host smart-3772c4bc-8091-4c15-ba7b-a7b2f1d83526
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054968 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disab
le_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disa
ble_auto_req_mode.4054968
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.4111342065
Short name T170
Test name
Test status
Simulation time 35419933 ps
CPU time 0.83 seconds
Started Apr 21 01:36:45 PM PDT 24
Finished Apr 21 01:36:47 PM PDT 24
Peak memory 218532 kb
Host smart-32e89040-1853-411d-a15b-7eacccdd07da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111342065 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.4111342065
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_intr.393733641
Short name T104
Test name
Test status
Simulation time 36076945 ps
CPU time 0.85 seconds
Started Apr 21 01:36:45 PM PDT 24
Finished Apr 21 01:36:46 PM PDT 24
Peak memory 216000 kb
Host smart-005dd401-3a40-435a-9c1d-9f78dae2e530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393733641 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.393733641
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.4230980456
Short name T529
Test name
Test status
Simulation time 57819091 ps
CPU time 0.92 seconds
Started Apr 21 01:36:44 PM PDT 24
Finished Apr 21 01:36:45 PM PDT 24
Peak memory 215632 kb
Host smart-7f32af5b-dca0-404c-b039-c3f98aaf79d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230980456 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.4230980456
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3942737062
Short name T155
Test name
Test status
Simulation time 350603196 ps
CPU time 6.51 seconds
Started Apr 21 01:36:43 PM PDT 24
Finished Apr 21 01:36:50 PM PDT 24
Peak memory 217232 kb
Host smart-6f61b060-16c7-4c5a-acf2-88983cae3473
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942737062 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3942737062
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1704556565
Short name T602
Test name
Test status
Simulation time 230304321418 ps
CPU time 1232.52 seconds
Started Apr 21 01:36:45 PM PDT 24
Finished Apr 21 01:57:18 PM PDT 24
Peak memory 225376 kb
Host smart-cad6b896-bfd1-4b16-aca8-ffd54d1a0ebe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704556565 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1704556565
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1609190893
Short name T769
Test name
Test status
Simulation time 92362484 ps
CPU time 1.12 seconds
Started Apr 21 01:36:48 PM PDT 24
Finished Apr 21 01:36:50 PM PDT 24
Peak memory 216100 kb
Host smart-65682e23-cb95-4d49-8dc0-8cdceb93d64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609190893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1609190893
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1361897342
Short name T650
Test name
Test status
Simulation time 28091231 ps
CPU time 0.91 seconds
Started Apr 21 01:36:51 PM PDT 24
Finished Apr 21 01:36:53 PM PDT 24
Peak memory 215152 kb
Host smart-53cc94c7-99c4-4b3e-8e82-fe4c8c61c33b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361897342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1361897342
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2610429144
Short name T175
Test name
Test status
Simulation time 11082448 ps
CPU time 0.87 seconds
Started Apr 21 01:36:49 PM PDT 24
Finished Apr 21 01:36:50 PM PDT 24
Peak memory 216644 kb
Host smart-08176750-be2c-4cfa-a231-70b07e60832e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610429144 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2610429144
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2246427973
Short name T23
Test name
Test status
Simulation time 37349088 ps
CPU time 1.23 seconds
Started Apr 21 01:36:51 PM PDT 24
Finished Apr 21 01:36:53 PM PDT 24
Peak memory 217144 kb
Host smart-1975a80d-22c5-4ab0-b8a9-1457bdacc310
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246427973 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2246427973
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.281768066
Short name T734
Test name
Test status
Simulation time 52927337 ps
CPU time 0.97 seconds
Started Apr 21 01:36:50 PM PDT 24
Finished Apr 21 01:36:51 PM PDT 24
Peak memory 219068 kb
Host smart-b8e08530-48ef-4dad-9066-54628fa8b8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281768066 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.281768066
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1334643995
Short name T562
Test name
Test status
Simulation time 37792249 ps
CPU time 1.49 seconds
Started Apr 21 01:36:48 PM PDT 24
Finished Apr 21 01:36:49 PM PDT 24
Peak memory 217580 kb
Host smart-f389d502-40e2-446a-8248-7e2cdadc0273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334643995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1334643995
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.471634216
Short name T377
Test name
Test status
Simulation time 39626756 ps
CPU time 0.96 seconds
Started Apr 21 01:36:48 PM PDT 24
Finished Apr 21 01:36:49 PM PDT 24
Peak memory 224352 kb
Host smart-f425c6e2-7abd-45d3-9322-275fb2f62c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471634216 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.471634216
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2988103173
Short name T744
Test name
Test status
Simulation time 42057528 ps
CPU time 0.85 seconds
Started Apr 21 01:36:49 PM PDT 24
Finished Apr 21 01:36:50 PM PDT 24
Peak memory 215572 kb
Host smart-2c238e77-52d0-4bc4-8dc9-0d0a84cba64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988103173 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2988103173
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1782030151
Short name T437
Test name
Test status
Simulation time 57734320 ps
CPU time 1.66 seconds
Started Apr 21 01:36:49 PM PDT 24
Finished Apr 21 01:36:51 PM PDT 24
Peak memory 217168 kb
Host smart-d36b204d-dd9b-48bd-b39d-6b6e3f516722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782030151 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1782030151
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2003360090
Short name T202
Test name
Test status
Simulation time 191495428130 ps
CPU time 1029.61 seconds
Started Apr 21 01:36:50 PM PDT 24
Finished Apr 21 01:54:00 PM PDT 24
Peak memory 221076 kb
Host smart-939f759f-c8f8-427f-804f-aeba1188909f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003360090 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2003360090
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3139722419
Short name T232
Test name
Test status
Simulation time 62100895 ps
CPU time 1.12 seconds
Started Apr 21 01:35:05 PM PDT 24
Finished Apr 21 01:35:06 PM PDT 24
Peak memory 216084 kb
Host smart-f8270f5c-2f7d-46eb-a491-bc6be8034cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139722419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3139722419
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1522358356
Short name T707
Test name
Test status
Simulation time 24940739 ps
CPU time 0.97 seconds
Started Apr 21 01:35:04 PM PDT 24
Finished Apr 21 01:35:06 PM PDT 24
Peak memory 207024 kb
Host smart-a1f01d2b-c8b4-4155-97c2-0eceeca04d81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522358356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1522358356
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1210904209
Short name T179
Test name
Test status
Simulation time 16882388 ps
CPU time 0.85 seconds
Started Apr 21 01:35:07 PM PDT 24
Finished Apr 21 01:35:08 PM PDT 24
Peak memory 216796 kb
Host smart-59cc519b-6296-489a-9170-c002154d233a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210904209 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1210904209
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2011419445
Short name T572
Test name
Test status
Simulation time 84017252 ps
CPU time 1.03 seconds
Started Apr 21 01:35:06 PM PDT 24
Finished Apr 21 01:35:08 PM PDT 24
Peak memory 218504 kb
Host smart-302b7164-8c97-4950-9cb3-8f182ac18e81
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011419445 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2011419445
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.478844897
Short name T738
Test name
Test status
Simulation time 32547017 ps
CPU time 1.16 seconds
Started Apr 21 01:35:11 PM PDT 24
Finished Apr 21 01:35:12 PM PDT 24
Peak memory 219072 kb
Host smart-f0a31f6d-dadc-4227-8dbb-47d6e8867da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478844897 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.478844897
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.33925430
Short name T473
Test name
Test status
Simulation time 131773465 ps
CPU time 1.79 seconds
Started Apr 21 01:35:02 PM PDT 24
Finished Apr 21 01:35:05 PM PDT 24
Peak memory 218976 kb
Host smart-68bffa12-3caf-420e-8e41-37aafb235e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33925430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.33925430
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.4200677576
Short name T803
Test name
Test status
Simulation time 36948615 ps
CPU time 1.09 seconds
Started Apr 21 01:35:02 PM PDT 24
Finished Apr 21 01:35:03 PM PDT 24
Peak memory 224408 kb
Host smart-d3520b54-26a0-4719-be5d-5cdbdd930950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200677576 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.4200677576
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.524525055
Short name T245
Test name
Test status
Simulation time 53592336 ps
CPU time 0.86 seconds
Started Apr 21 01:35:02 PM PDT 24
Finished Apr 21 01:35:04 PM PDT 24
Peak memory 207396 kb
Host smart-01c0320e-608c-40ad-b9e3-a769f277a695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524525055 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.524525055
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.446547766
Short name T66
Test name
Test status
Simulation time 1939383888 ps
CPU time 7.29 seconds
Started Apr 21 01:35:04 PM PDT 24
Finished Apr 21 01:35:12 PM PDT 24
Peak memory 237880 kb
Host smart-8ca3a3ea-90a5-439b-ba7a-5e4fd0813823
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446547766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.446547766
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.406527738
Short name T498
Test name
Test status
Simulation time 229918878 ps
CPU time 0.9 seconds
Started Apr 21 01:35:02 PM PDT 24
Finished Apr 21 01:35:04 PM PDT 24
Peak memory 215636 kb
Host smart-89a49fc7-3854-49a7-9a9f-f836c1d05f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406527738 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.406527738
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.4246124522
Short name T265
Test name
Test status
Simulation time 906305679 ps
CPU time 3.74 seconds
Started Apr 21 01:35:03 PM PDT 24
Finished Apr 21 01:35:07 PM PDT 24
Peak memory 217440 kb
Host smart-d6d35cd2-12dd-4187-826f-d4e33b030b39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246124522 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.4246124522
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.4244802409
Short name T196
Test name
Test status
Simulation time 10468743149 ps
CPU time 63.33 seconds
Started Apr 21 01:35:04 PM PDT 24
Finished Apr 21 01:36:08 PM PDT 24
Peak memory 219176 kb
Host smart-83d627be-22b2-470c-9b69-cb81145dc36f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244802409 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.4244802409
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.4024251589
Short name T778
Test name
Test status
Simulation time 84622554 ps
CPU time 1.22 seconds
Started Apr 21 01:36:53 PM PDT 24
Finished Apr 21 01:36:55 PM PDT 24
Peak memory 216068 kb
Host smart-72f9e491-2d2c-4c3d-a450-6e40d2326476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024251589 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.4024251589
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1553249885
Short name T561
Test name
Test status
Simulation time 36584202 ps
CPU time 0.85 seconds
Started Apr 21 01:36:55 PM PDT 24
Finished Apr 21 01:36:56 PM PDT 24
Peak memory 206980 kb
Host smart-bbc73158-bcf6-4a9d-ab22-a22317401334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553249885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1553249885
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.209931881
Short name T603
Test name
Test status
Simulation time 21882695 ps
CPU time 0.87 seconds
Started Apr 21 01:36:56 PM PDT 24
Finished Apr 21 01:36:58 PM PDT 24
Peak memory 216776 kb
Host smart-cda4df9f-7a1c-48a4-9d69-0b11df4c6241
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209931881 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.209931881
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_err.38720559
Short name T182
Test name
Test status
Simulation time 33397518 ps
CPU time 1.09 seconds
Started Apr 21 01:36:54 PM PDT 24
Finished Apr 21 01:36:55 PM PDT 24
Peak memory 220004 kb
Host smart-00002d0a-2fad-4f96-8262-e66de4985356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38720559 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.38720559
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1660613900
Short name T580
Test name
Test status
Simulation time 189106366 ps
CPU time 2.44 seconds
Started Apr 21 01:36:51 PM PDT 24
Finished Apr 21 01:36:54 PM PDT 24
Peak memory 218632 kb
Host smart-df0484a1-0026-4b37-b6f8-40c7402dd065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660613900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1660613900
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.902785725
Short name T94
Test name
Test status
Simulation time 22793400 ps
CPU time 1.08 seconds
Started Apr 21 01:36:50 PM PDT 24
Finished Apr 21 01:36:51 PM PDT 24
Peak memory 215924 kb
Host smart-6b04b7f5-ec84-45c7-8fb0-36c2bc60c523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902785725 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.902785725
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2655489486
Short name T722
Test name
Test status
Simulation time 29296427 ps
CPU time 0.97 seconds
Started Apr 21 01:36:51 PM PDT 24
Finished Apr 21 01:36:52 PM PDT 24
Peak memory 215660 kb
Host smart-a03076c7-7d83-40d0-b27d-5762448b3d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655489486 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2655489486
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.176617371
Short name T266
Test name
Test status
Simulation time 439895121 ps
CPU time 2.9 seconds
Started Apr 21 01:36:52 PM PDT 24
Finished Apr 21 01:36:55 PM PDT 24
Peak memory 217324 kb
Host smart-3473f5de-3653-42b4-a968-fa3739651c9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176617371 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.176617371
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.4010915156
Short name T387
Test name
Test status
Simulation time 25222982402 ps
CPU time 621.05 seconds
Started Apr 21 01:36:52 PM PDT 24
Finished Apr 21 01:47:14 PM PDT 24
Peak memory 217904 kb
Host smart-9bcecf6b-e6ab-4f52-9f06-95e798707c71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010915156 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.4010915156
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2784536868
Short name T451
Test name
Test status
Simulation time 26752340 ps
CPU time 1.26 seconds
Started Apr 21 01:36:53 PM PDT 24
Finished Apr 21 01:36:55 PM PDT 24
Peak memory 216080 kb
Host smart-d34d96db-21ab-465f-acc0-3022edddcf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784536868 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2784536868
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.795907327
Short name T671
Test name
Test status
Simulation time 89968354 ps
CPU time 0.9 seconds
Started Apr 21 01:36:57 PM PDT 24
Finished Apr 21 01:36:58 PM PDT 24
Peak memory 206984 kb
Host smart-bb7817b6-6bcc-4e4b-84e8-d6f94e00e494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795907327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.795907327
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1492234825
Short name T429
Test name
Test status
Simulation time 10760809 ps
CPU time 0.85 seconds
Started Apr 21 01:36:54 PM PDT 24
Finished Apr 21 01:36:55 PM PDT 24
Peak memory 216800 kb
Host smart-7cd8b5c5-1d64-4639-8c84-901cdd4e465b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492234825 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1492234825
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2056114206
Short name T655
Test name
Test status
Simulation time 78459357 ps
CPU time 1.16 seconds
Started Apr 21 01:36:57 PM PDT 24
Finished Apr 21 01:36:58 PM PDT 24
Peak memory 217164 kb
Host smart-9189a2c6-8a45-4db0-938b-f936800cac40
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056114206 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2056114206
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3828433614
Short name T63
Test name
Test status
Simulation time 32340565 ps
CPU time 0.98 seconds
Started Apr 21 01:36:54 PM PDT 24
Finished Apr 21 01:36:55 PM PDT 24
Peak memory 224172 kb
Host smart-305d5282-0676-4fbf-bf2f-e0ac0902242b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828433614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3828433614
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2054360531
Short name T533
Test name
Test status
Simulation time 70200896 ps
CPU time 2.18 seconds
Started Apr 21 01:36:56 PM PDT 24
Finished Apr 21 01:36:59 PM PDT 24
Peak memory 218576 kb
Host smart-2f2da62d-f252-4c29-9877-885bf46ce68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054360531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2054360531
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3353096103
Short name T75
Test name
Test status
Simulation time 26255850 ps
CPU time 0.9 seconds
Started Apr 21 01:36:54 PM PDT 24
Finished Apr 21 01:36:55 PM PDT 24
Peak memory 216172 kb
Host smart-615a73d0-1c9d-4d38-ab3a-ef825f2274ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353096103 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3353096103
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1038312682
Short name T465
Test name
Test status
Simulation time 54936020 ps
CPU time 0.91 seconds
Started Apr 21 01:36:54 PM PDT 24
Finished Apr 21 01:36:55 PM PDT 24
Peak memory 215640 kb
Host smart-60187310-eb91-49af-b6d9-ce9805940933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038312682 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1038312682
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1041238465
Short name T506
Test name
Test status
Simulation time 93438802 ps
CPU time 1.51 seconds
Started Apr 21 01:36:52 PM PDT 24
Finished Apr 21 01:36:54 PM PDT 24
Peak memory 218440 kb
Host smart-afaa78fe-2441-45f2-8606-fb64779201e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041238465 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1041238465
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1588337409
Short name T74
Test name
Test status
Simulation time 35582213556 ps
CPU time 910.86 seconds
Started Apr 21 01:36:53 PM PDT 24
Finished Apr 21 01:52:04 PM PDT 24
Peak memory 219640 kb
Host smart-6c7a27f8-94e4-4d1c-a56a-96bb2f6fe57a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588337409 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1588337409
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert_test.948089058
Short name T76
Test name
Test status
Simulation time 29711603 ps
CPU time 0.92 seconds
Started Apr 21 01:36:59 PM PDT 24
Finished Apr 21 01:37:00 PM PDT 24
Peak memory 206960 kb
Host smart-b8d8c079-42bd-4e4f-8bbd-b0f2d05a5ae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948089058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.948089058
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.538752810
Short name T621
Test name
Test status
Simulation time 36854668 ps
CPU time 0.86 seconds
Started Apr 21 01:36:59 PM PDT 24
Finished Apr 21 01:37:00 PM PDT 24
Peak memory 216312 kb
Host smart-9e10f7e5-2ba5-4768-ab6c-7e426ec2e1bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538752810 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.538752810
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_err.45160391
Short name T528
Test name
Test status
Simulation time 55150992 ps
CPU time 1.14 seconds
Started Apr 21 01:37:00 PM PDT 24
Finished Apr 21 01:37:02 PM PDT 24
Peak memory 232588 kb
Host smart-a5b771fe-450f-4031-a308-43639542b812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45160391 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.45160391
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.389426357
Short name T359
Test name
Test status
Simulation time 37663801 ps
CPU time 1.46 seconds
Started Apr 21 01:36:57 PM PDT 24
Finished Apr 21 01:36:59 PM PDT 24
Peak memory 218372 kb
Host smart-bd7e03a7-4e4c-49c7-b529-26b976371c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389426357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.389426357
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3255758107
Short name T81
Test name
Test status
Simulation time 23420479 ps
CPU time 1.05 seconds
Started Apr 21 01:36:58 PM PDT 24
Finished Apr 21 01:37:00 PM PDT 24
Peak memory 215928 kb
Host smart-b9495848-4a89-4bdf-b292-52bf3968a710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255758107 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3255758107
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2017948105
Short name T367
Test name
Test status
Simulation time 18013333 ps
CPU time 0.94 seconds
Started Apr 21 01:36:58 PM PDT 24
Finished Apr 21 01:37:00 PM PDT 24
Peak memory 215640 kb
Host smart-da4d4ef9-bc70-495d-a1a1-cd79be13228e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017948105 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2017948105
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.81354641
Short name T326
Test name
Test status
Simulation time 213121811 ps
CPU time 4.2 seconds
Started Apr 21 01:36:57 PM PDT 24
Finished Apr 21 01:37:01 PM PDT 24
Peak memory 215612 kb
Host smart-32d5f300-b999-489e-b898-81f2fa2cb77e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81354641 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.81354641
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1422933171
Short name T741
Test name
Test status
Simulation time 136954448059 ps
CPU time 871.08 seconds
Started Apr 21 01:36:58 PM PDT 24
Finished Apr 21 01:51:29 PM PDT 24
Peak memory 224052 kb
Host smart-4ba52d9e-7057-49c8-977e-b3608954a2d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422933171 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1422933171
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.3233835524
Short name T231
Test name
Test status
Simulation time 208140076 ps
CPU time 1.36 seconds
Started Apr 21 01:37:01 PM PDT 24
Finished Apr 21 01:37:02 PM PDT 24
Peak memory 216048 kb
Host smart-a63ee21a-d327-42a1-8585-6d57b169a2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233835524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3233835524
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.946263263
Short name T481
Test name
Test status
Simulation time 44968566 ps
CPU time 0.85 seconds
Started Apr 21 01:37:02 PM PDT 24
Finished Apr 21 01:37:03 PM PDT 24
Peak memory 207008 kb
Host smart-d3f71309-c068-4a28-bc56-0693df0a5ccd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946263263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.946263263
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1615263381
Short name T187
Test name
Test status
Simulation time 16117163 ps
CPU time 0.87 seconds
Started Apr 21 01:37:04 PM PDT 24
Finished Apr 21 01:37:05 PM PDT 24
Peak memory 216968 kb
Host smart-17843023-f414-4aa0-8964-e0fee99ba56c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615263381 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1615263381
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.4149117590
Short name T522
Test name
Test status
Simulation time 38356214 ps
CPU time 1.03 seconds
Started Apr 21 01:37:04 PM PDT 24
Finished Apr 21 01:37:06 PM PDT 24
Peak memory 218448 kb
Host smart-7647818e-ca58-46e4-ad92-70e79c12c5c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149117590 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.4149117590
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.636902060
Short name T130
Test name
Test status
Simulation time 18876691 ps
CPU time 1.19 seconds
Started Apr 21 01:37:02 PM PDT 24
Finished Apr 21 01:37:04 PM PDT 24
Peak memory 224264 kb
Host smart-24596900-026e-4218-afd7-aff2e59edbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636902060 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.636902060
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_intr.1204136500
Short name T512
Test name
Test status
Simulation time 25582301 ps
CPU time 0.96 seconds
Started Apr 21 01:37:00 PM PDT 24
Finished Apr 21 01:37:01 PM PDT 24
Peak memory 215952 kb
Host smart-e9e0f9ba-4452-4eea-bb25-4914b9ed4542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204136500 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1204136500
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.973360000
Short name T748
Test name
Test status
Simulation time 95063714 ps
CPU time 0.89 seconds
Started Apr 21 01:36:59 PM PDT 24
Finished Apr 21 01:37:00 PM PDT 24
Peak memory 215660 kb
Host smart-926a42b3-4603-4916-9069-5edf95ebc67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973360000 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.973360000
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1077378694
Short name T5
Test name
Test status
Simulation time 167921586 ps
CPU time 3.57 seconds
Started Apr 21 01:36:59 PM PDT 24
Finished Apr 21 01:37:03 PM PDT 24
Peak memory 215708 kb
Host smart-255cc3b8-1042-43b1-9749-0769e913a9e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077378694 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1077378694
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2237429428
Short name T523
Test name
Test status
Simulation time 121034251845 ps
CPU time 1346.36 seconds
Started Apr 21 01:36:59 PM PDT 24
Finished Apr 21 01:59:26 PM PDT 24
Peak memory 224160 kb
Host smart-b1564d42-ba6f-44ef-b1fb-6190fbc940c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237429428 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2237429428
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.706984756
Short name T109
Test name
Test status
Simulation time 172532433 ps
CPU time 1.29 seconds
Started Apr 21 01:37:10 PM PDT 24
Finished Apr 21 01:37:11 PM PDT 24
Peak memory 216080 kb
Host smart-0d686ebc-d5a6-471e-856a-2b147b8b6f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706984756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.706984756
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.670488451
Short name T342
Test name
Test status
Simulation time 34127570 ps
CPU time 0.88 seconds
Started Apr 21 01:37:05 PM PDT 24
Finished Apr 21 01:37:06 PM PDT 24
Peak memory 215060 kb
Host smart-0c285777-7be8-4d57-a682-88cfacc8c4b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670488451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.670488451
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3408011234
Short name T145
Test name
Test status
Simulation time 33211626 ps
CPU time 0.78 seconds
Started Apr 21 01:37:04 PM PDT 24
Finished Apr 21 01:37:05 PM PDT 24
Peak memory 216660 kb
Host smart-e4f72a34-20b4-4edd-9916-c4fdba55e2d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408011234 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3408011234
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_err.3352276623
Short name T176
Test name
Test status
Simulation time 20757160 ps
CPU time 1.13 seconds
Started Apr 21 01:37:07 PM PDT 24
Finished Apr 21 01:37:08 PM PDT 24
Peak memory 220260 kb
Host smart-c727abcd-61c4-42f0-ac61-cf72fdea4d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352276623 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3352276623
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.347948884
Short name T404
Test name
Test status
Simulation time 98538388 ps
CPU time 1.26 seconds
Started Apr 21 01:37:01 PM PDT 24
Finished Apr 21 01:37:03 PM PDT 24
Peak memory 219856 kb
Host smart-2649ef2a-cc3a-411c-a9b1-00db7639b2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347948884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.347948884
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.788257083
Short name T718
Test name
Test status
Simulation time 73424798 ps
CPU time 0.89 seconds
Started Apr 21 01:37:09 PM PDT 24
Finished Apr 21 01:37:10 PM PDT 24
Peak memory 215924 kb
Host smart-3d31bba0-965b-49bb-a44b-c32e64e2ac50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788257083 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.788257083
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.204926163
Short name T156
Test name
Test status
Simulation time 17319922 ps
CPU time 0.97 seconds
Started Apr 21 01:37:03 PM PDT 24
Finished Apr 21 01:37:04 PM PDT 24
Peak memory 215760 kb
Host smart-58965bea-9c36-41a9-a3f5-0688814bc871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204926163 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.204926163
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3162681474
Short name T575
Test name
Test status
Simulation time 157176770 ps
CPU time 2.25 seconds
Started Apr 21 01:37:04 PM PDT 24
Finished Apr 21 01:37:07 PM PDT 24
Peak memory 218492 kb
Host smart-d5406bc6-f540-4686-a986-27b815bb1466
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162681474 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3162681474
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.836025743
Short name T204
Test name
Test status
Simulation time 21647772879 ps
CPU time 471.07 seconds
Started Apr 21 01:37:08 PM PDT 24
Finished Apr 21 01:44:59 PM PDT 24
Peak memory 218180 kb
Host smart-b73bbecd-d163-44b9-be4d-9b7dada4e328
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836025743 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.836025743
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1267569515
Short name T666
Test name
Test status
Simulation time 224469503 ps
CPU time 1.43 seconds
Started Apr 21 01:37:07 PM PDT 24
Finished Apr 21 01:37:09 PM PDT 24
Peak memory 216056 kb
Host smart-61e67260-6a6e-427e-8a37-1fba2f3b55bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267569515 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1267569515
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1196560666
Short name T443
Test name
Test status
Simulation time 85276120 ps
CPU time 0.93 seconds
Started Apr 21 01:37:08 PM PDT 24
Finished Apr 21 01:37:09 PM PDT 24
Peak memory 206964 kb
Host smart-880cb745-0b43-406f-a3af-cfce31ae8cb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196560666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1196560666
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3796244227
Short name T50
Test name
Test status
Simulation time 56284986 ps
CPU time 0.87 seconds
Started Apr 21 01:37:10 PM PDT 24
Finished Apr 21 01:37:11 PM PDT 24
Peak memory 216532 kb
Host smart-dfbaa0c8-6619-40e1-b4d7-80b79a55b0b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796244227 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3796244227
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.752266293
Short name T598
Test name
Test status
Simulation time 30709191 ps
CPU time 1 seconds
Started Apr 21 01:37:11 PM PDT 24
Finished Apr 21 01:37:12 PM PDT 24
Peak memory 218516 kb
Host smart-655d865d-1407-4e47-b18f-a3b5f49059d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752266293 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.752266293
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2434987646
Short name T624
Test name
Test status
Simulation time 17885667 ps
CPU time 1.03 seconds
Started Apr 21 01:37:09 PM PDT 24
Finished Apr 21 01:37:11 PM PDT 24
Peak memory 218688 kb
Host smart-d5c059aa-4d6a-4313-bbbf-20372656048e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434987646 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2434987646
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.4027508389
Short name T584
Test name
Test status
Simulation time 43751976 ps
CPU time 1.44 seconds
Started Apr 21 01:37:06 PM PDT 24
Finished Apr 21 01:37:08 PM PDT 24
Peak memory 218540 kb
Host smart-0713a70e-31e9-40ad-a357-3a2fc5d92e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027508389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.4027508389
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3944918587
Short name T413
Test name
Test status
Simulation time 30952991 ps
CPU time 0.86 seconds
Started Apr 21 01:37:09 PM PDT 24
Finished Apr 21 01:37:11 PM PDT 24
Peak memory 215776 kb
Host smart-f43f1b23-d64c-4353-b4cb-568c05cc8471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944918587 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3944918587
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3403956277
Short name T609
Test name
Test status
Simulation time 18299340 ps
CPU time 0.98 seconds
Started Apr 21 01:37:06 PM PDT 24
Finished Apr 21 01:37:07 PM PDT 24
Peak memory 215620 kb
Host smart-1a73d9b0-0c60-4e7e-9627-708454bfa410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403956277 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3403956277
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1834732474
Short name T206
Test name
Test status
Simulation time 378171674 ps
CPU time 7.2 seconds
Started Apr 21 01:37:06 PM PDT 24
Finished Apr 21 01:37:13 PM PDT 24
Peak memory 218468 kb
Host smart-351eb984-d049-4aaf-bcd4-3810bbb34e22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834732474 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1834732474
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.668176122
Short name T604
Test name
Test status
Simulation time 137659925029 ps
CPU time 1817.44 seconds
Started Apr 21 01:37:07 PM PDT 24
Finished Apr 21 02:07:25 PM PDT 24
Peak memory 228292 kb
Host smart-2f8c815d-ff75-4687-80f3-d4dc9811968b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668176122 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.668176122
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3051786507
Short name T248
Test name
Test status
Simulation time 22669371 ps
CPU time 1.14 seconds
Started Apr 21 01:37:09 PM PDT 24
Finished Apr 21 01:37:11 PM PDT 24
Peak memory 216080 kb
Host smart-f67a274d-04e6-4832-ac20-b6fbba524cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051786507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3051786507
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3470245893
Short name T651
Test name
Test status
Simulation time 33623409 ps
CPU time 0.97 seconds
Started Apr 21 01:37:09 PM PDT 24
Finished Apr 21 01:37:11 PM PDT 24
Peak memory 206992 kb
Host smart-112cfc9f-4cdc-4dcb-bffb-d72bfd7ad1d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470245893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3470245893
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3119228070
Short name T131
Test name
Test status
Simulation time 40560530 ps
CPU time 0.85 seconds
Started Apr 21 01:37:10 PM PDT 24
Finished Apr 21 01:37:11 PM PDT 24
Peak memory 215744 kb
Host smart-993743d0-9145-44fb-9bc0-2668d3b18b93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119228070 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3119228070
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_err.2065690919
Short name T805
Test name
Test status
Simulation time 29069936 ps
CPU time 0.86 seconds
Started Apr 21 01:37:11 PM PDT 24
Finished Apr 21 01:37:12 PM PDT 24
Peak memory 218456 kb
Host smart-f22f215e-c7b7-4fd3-b1cd-5c19aaf70359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065690919 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2065690919
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.3652019154
Short name T100
Test name
Test status
Simulation time 50575402 ps
CPU time 1.96 seconds
Started Apr 21 01:37:11 PM PDT 24
Finished Apr 21 01:37:13 PM PDT 24
Peak memory 217492 kb
Host smart-7800e2a1-52f8-4449-b891-4b0b5aa7f49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652019154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3652019154
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_smoke.1382766549
Short name T356
Test name
Test status
Simulation time 19004069 ps
CPU time 0.97 seconds
Started Apr 21 01:37:05 PM PDT 24
Finished Apr 21 01:37:07 PM PDT 24
Peak memory 215824 kb
Host smart-d8b1815a-5de1-48d3-8176-d7c9d340581b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382766549 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1382766549
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2406649983
Short name T464
Test name
Test status
Simulation time 38343559 ps
CPU time 1.04 seconds
Started Apr 21 01:37:11 PM PDT 24
Finished Apr 21 01:37:12 PM PDT 24
Peak memory 215672 kb
Host smart-969f3d1a-e947-417e-ba18-459dc02dbed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406649983 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2406649983
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_alert.2312984324
Short name T468
Test name
Test status
Simulation time 28836503 ps
CPU time 1.23 seconds
Started Apr 21 01:37:13 PM PDT 24
Finished Apr 21 01:37:14 PM PDT 24
Peak memory 216080 kb
Host smart-631e8835-63b4-4660-8a55-aa78f2b60e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312984324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2312984324
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1353285526
Short name T59
Test name
Test status
Simulation time 29473317 ps
CPU time 0.81 seconds
Started Apr 21 01:37:18 PM PDT 24
Finished Apr 21 01:37:20 PM PDT 24
Peak memory 206664 kb
Host smart-736d5476-3161-42b4-a3b6-e26fd6ea4f1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353285526 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1353285526
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2865145090
Short name T190
Test name
Test status
Simulation time 13538891 ps
CPU time 0.9 seconds
Started Apr 21 01:37:12 PM PDT 24
Finished Apr 21 01:37:13 PM PDT 24
Peak memory 215964 kb
Host smart-df3deabc-d0d7-4ff7-9506-df188aa77518
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865145090 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2865145090
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3846761224
Short name T118
Test name
Test status
Simulation time 84424816 ps
CPU time 1.06 seconds
Started Apr 21 01:37:17 PM PDT 24
Finished Apr 21 01:37:19 PM PDT 24
Peak memory 218688 kb
Host smart-957d582b-7ee7-46ad-94b7-2cb045022da1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846761224 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3846761224
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2249076302
Short name T582
Test name
Test status
Simulation time 18657924 ps
CPU time 1.01 seconds
Started Apr 21 01:37:14 PM PDT 24
Finished Apr 21 01:37:15 PM PDT 24
Peak memory 219068 kb
Host smart-cc9e325f-124e-446e-a77c-4be4d08705c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249076302 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2249076302
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2655116308
Short name T284
Test name
Test status
Simulation time 201519408 ps
CPU time 2.69 seconds
Started Apr 21 01:37:12 PM PDT 24
Finished Apr 21 01:37:15 PM PDT 24
Peak memory 220036 kb
Host smart-9bfba2f1-5dc4-4724-b502-eb27a56114e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655116308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2655116308
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1542405478
Short name T312
Test name
Test status
Simulation time 32050871 ps
CPU time 0.93 seconds
Started Apr 21 01:37:12 PM PDT 24
Finished Apr 21 01:37:13 PM PDT 24
Peak memory 215748 kb
Host smart-a254c49c-62de-46c3-a7e3-fdd83d9598b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542405478 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1542405478
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.905113070
Short name T313
Test name
Test status
Simulation time 17995930 ps
CPU time 1.02 seconds
Started Apr 21 01:37:16 PM PDT 24
Finished Apr 21 01:37:17 PM PDT 24
Peak memory 215640 kb
Host smart-e9811161-0396-4463-b62b-ff5a021521a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905113070 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.905113070
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1358605843
Short name T165
Test name
Test status
Simulation time 277441152 ps
CPU time 5.2 seconds
Started Apr 21 01:37:10 PM PDT 24
Finished Apr 21 01:37:15 PM PDT 24
Peak memory 220404 kb
Host smart-af2427d9-2a31-44a3-9788-444098e99bf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358605843 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1358605843
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1987257268
Short name T724
Test name
Test status
Simulation time 270883688599 ps
CPU time 1586.51 seconds
Started Apr 21 01:37:13 PM PDT 24
Finished Apr 21 02:03:40 PM PDT 24
Peak memory 224768 kb
Host smart-6bd9fbc7-a923-4915-89ec-e4570f40a062
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987257268 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1987257268
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2222620223
Short name T489
Test name
Test status
Simulation time 78139359 ps
CPU time 1.17 seconds
Started Apr 21 01:37:13 PM PDT 24
Finished Apr 21 01:37:15 PM PDT 24
Peak memory 216084 kb
Host smart-e2d969ba-3b01-4970-a5c2-b8dddad7820c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222620223 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2222620223
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2542807055
Short name T320
Test name
Test status
Simulation time 29683937 ps
CPU time 0.92 seconds
Started Apr 21 01:37:17 PM PDT 24
Finished Apr 21 01:37:18 PM PDT 24
Peak memory 207012 kb
Host smart-14ae60a7-3ff5-4a7b-b988-62eb1cca4998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542807055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2542807055
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_err.2902435583
Short name T244
Test name
Test status
Simulation time 27090355 ps
CPU time 0.99 seconds
Started Apr 21 01:37:16 PM PDT 24
Finished Apr 21 01:37:17 PM PDT 24
Peak memory 224312 kb
Host smart-d9ce8676-0a23-4ac7-a056-53c2f0ce31f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902435583 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2902435583
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1824283057
Short name T771
Test name
Test status
Simulation time 32392929 ps
CPU time 1.45 seconds
Started Apr 21 01:37:13 PM PDT 24
Finished Apr 21 01:37:14 PM PDT 24
Peak memory 218608 kb
Host smart-cd2ad9bd-4076-4b69-9ea9-e0896bc160f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824283057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1824283057
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.193925247
Short name T37
Test name
Test status
Simulation time 32571780 ps
CPU time 0.87 seconds
Started Apr 21 01:37:17 PM PDT 24
Finished Apr 21 01:37:19 PM PDT 24
Peak memory 215940 kb
Host smart-c5b362d0-934d-4c43-98f4-28b972d6090f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193925247 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.193925247
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.4155276507
Short name T594
Test name
Test status
Simulation time 98170361 ps
CPU time 0.87 seconds
Started Apr 21 01:37:13 PM PDT 24
Finished Apr 21 01:37:14 PM PDT 24
Peak memory 215604 kb
Host smart-ef69cb6a-9cbc-45e4-be91-9bd849df5734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155276507 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.4155276507
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1288618225
Short name T482
Test name
Test status
Simulation time 33687541 ps
CPU time 1.21 seconds
Started Apr 21 01:37:16 PM PDT 24
Finished Apr 21 01:37:17 PM PDT 24
Peak memory 207456 kb
Host smart-00e41aad-207b-402c-9220-a31585359bf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288618225 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1288618225
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2399041618
Short name T390
Test name
Test status
Simulation time 6144136073 ps
CPU time 141.63 seconds
Started Apr 21 01:37:16 PM PDT 24
Finished Apr 21 01:39:38 PM PDT 24
Peak memory 218596 kb
Host smart-6285fb21-ca65-4652-aa19-815a202fdb5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399041618 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2399041618
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert_test.260412757
Short name T496
Test name
Test status
Simulation time 90407587 ps
CPU time 0.88 seconds
Started Apr 21 01:37:21 PM PDT 24
Finished Apr 21 01:37:22 PM PDT 24
Peak memory 206728 kb
Host smart-2927d5d9-3f45-4440-a8de-0460db198635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260412757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.260412757
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2373555071
Short name T412
Test name
Test status
Simulation time 10490141 ps
CPU time 0.89 seconds
Started Apr 21 01:37:21 PM PDT 24
Finished Apr 21 01:37:22 PM PDT 24
Peak memory 216248 kb
Host smart-84ab4c32-2389-4ef6-ad0d-25646cfd2b49
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373555071 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2373555071
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.4203196310
Short name T767
Test name
Test status
Simulation time 55558274 ps
CPU time 1.14 seconds
Started Apr 21 01:37:19 PM PDT 24
Finished Apr 21 01:37:20 PM PDT 24
Peak memory 218328 kb
Host smart-b36f20ae-c048-41ef-a8ca-ddabb675364d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203196310 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.4203196310
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.771441146
Short name T166
Test name
Test status
Simulation time 20337545 ps
CPU time 1.04 seconds
Started Apr 21 01:37:19 PM PDT 24
Finished Apr 21 01:37:20 PM PDT 24
Peak memory 218632 kb
Host smart-f4973a47-928e-4447-ab4a-40ae1c3951a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771441146 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.771441146
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1180546501
Short name T639
Test name
Test status
Simulation time 51085120 ps
CPU time 1.72 seconds
Started Apr 21 01:37:14 PM PDT 24
Finished Apr 21 01:37:16 PM PDT 24
Peak memory 218616 kb
Host smart-92efe664-1a84-4f78-943b-ef7e42500674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180546501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1180546501
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1837630028
Short name T633
Test name
Test status
Simulation time 34634968 ps
CPU time 0.98 seconds
Started Apr 21 01:37:18 PM PDT 24
Finished Apr 21 01:37:19 PM PDT 24
Peak memory 224324 kb
Host smart-a1e6c478-18e5-4250-b90c-aabda7b709b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837630028 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1837630028
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.742734943
Short name T573
Test name
Test status
Simulation time 32485160 ps
CPU time 0.9 seconds
Started Apr 21 01:37:17 PM PDT 24
Finished Apr 21 01:37:18 PM PDT 24
Peak memory 215632 kb
Host smart-61d9295b-c206-4184-85de-59100f1a3b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742734943 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.742734943
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.442839029
Short name T814
Test name
Test status
Simulation time 828250043 ps
CPU time 4.43 seconds
Started Apr 21 01:37:14 PM PDT 24
Finished Apr 21 01:37:19 PM PDT 24
Peak memory 217268 kb
Host smart-d6abcea5-9ff1-4299-acc0-897bbe65832c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442839029 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.442839029
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1143048245
Short name T783
Test name
Test status
Simulation time 304149030533 ps
CPU time 2051.48 seconds
Started Apr 21 01:37:15 PM PDT 24
Finished Apr 21 02:11:27 PM PDT 24
Peak memory 229180 kb
Host smart-134ef66a-8f9a-48a0-b886-d900bbb993dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143048245 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1143048245
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.2702621235
Short name T806
Test name
Test status
Simulation time 84854746 ps
CPU time 1.21 seconds
Started Apr 21 01:35:07 PM PDT 24
Finished Apr 21 01:35:08 PM PDT 24
Peak memory 216084 kb
Host smart-ed5b9c62-828c-4fba-9040-56b878ffe565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702621235 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2702621235
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3934861255
Short name T800
Test name
Test status
Simulation time 15352702 ps
CPU time 0.96 seconds
Started Apr 21 01:35:10 PM PDT 24
Finished Apr 21 01:35:11 PM PDT 24
Peak memory 215208 kb
Host smart-6235c90a-34bf-4e03-8965-030a56312e04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934861255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3934861255
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1292141994
Short name T174
Test name
Test status
Simulation time 14076276 ps
CPU time 0.89 seconds
Started Apr 21 01:35:11 PM PDT 24
Finished Apr 21 01:35:12 PM PDT 24
Peak memory 216824 kb
Host smart-c7050c11-aae2-4d86-bbcf-4620c98bf4f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292141994 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1292141994
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_err.560055603
Short name T9
Test name
Test status
Simulation time 130749781 ps
CPU time 1.19 seconds
Started Apr 21 01:35:13 PM PDT 24
Finished Apr 21 01:35:15 PM PDT 24
Peak memory 229780 kb
Host smart-6b64c7fd-5af5-4ff8-970f-a8fc50601717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560055603 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.560055603
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.4122099088
Short name T70
Test name
Test status
Simulation time 80996642 ps
CPU time 1.1 seconds
Started Apr 21 01:35:09 PM PDT 24
Finished Apr 21 01:35:10 PM PDT 24
Peak memory 217412 kb
Host smart-895a69f6-86e1-49ba-9f1c-446c917eed1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122099088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.4122099088
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3645240533
Short name T811
Test name
Test status
Simulation time 26769973 ps
CPU time 0.95 seconds
Started Apr 21 01:35:10 PM PDT 24
Finished Apr 21 01:35:12 PM PDT 24
Peak memory 216168 kb
Host smart-4a479e3a-1ae9-4bd8-a339-af800dcdd297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645240533 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3645240533
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_smoke.1590768298
Short name T648
Test name
Test status
Simulation time 58144779 ps
CPU time 0.92 seconds
Started Apr 21 01:35:07 PM PDT 24
Finished Apr 21 01:35:08 PM PDT 24
Peak memory 215608 kb
Host smart-f2001a2e-67d9-4173-8f50-aff206094ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590768298 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1590768298
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1064085517
Short name T781
Test name
Test status
Simulation time 2810351852 ps
CPU time 4.74 seconds
Started Apr 21 01:35:09 PM PDT 24
Finished Apr 21 01:35:14 PM PDT 24
Peak memory 217480 kb
Host smart-b6f8e2b4-47a5-427b-866d-93bf9f707b43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064085517 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1064085517
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1463592859
Short name T199
Test name
Test status
Simulation time 104464469733 ps
CPU time 2325.02 seconds
Started Apr 21 01:35:09 PM PDT 24
Finished Apr 21 02:13:54 PM PDT 24
Peak memory 227624 kb
Host smart-0ae0126e-6f31-4906-953d-ae55ea02760a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463592859 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1463592859
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.1566461958
Short name T593
Test name
Test status
Simulation time 24315700 ps
CPU time 0.9 seconds
Started Apr 21 01:37:21 PM PDT 24
Finished Apr 21 01:37:22 PM PDT 24
Peak memory 218792 kb
Host smart-f44ac2bc-5bba-492a-9527-0278f69f3afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566461958 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1566461958
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2637799240
Short name T787
Test name
Test status
Simulation time 37938172 ps
CPU time 1.35 seconds
Started Apr 21 01:37:17 PM PDT 24
Finished Apr 21 01:37:19 PM PDT 24
Peak memory 218724 kb
Host smart-34edb34d-8cfd-4286-886d-e05b278c61a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637799240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2637799240
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.3848936378
Short name T181
Test name
Test status
Simulation time 73431055 ps
CPU time 1.06 seconds
Started Apr 21 01:37:23 PM PDT 24
Finished Apr 21 01:37:24 PM PDT 24
Peak memory 219940 kb
Host smart-ebd6b65f-75a5-4436-a057-d4442ae3422f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848936378 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3848936378
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2593988896
Short name T317
Test name
Test status
Simulation time 95572984 ps
CPU time 1.21 seconds
Started Apr 21 01:37:27 PM PDT 24
Finished Apr 21 01:37:29 PM PDT 24
Peak memory 218868 kb
Host smart-acce9b18-85af-4b92-84a0-831aff655d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593988896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2593988896
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.1561630802
Short name T82
Test name
Test status
Simulation time 19375021 ps
CPU time 1.01 seconds
Started Apr 21 01:37:26 PM PDT 24
Finished Apr 21 01:37:27 PM PDT 24
Peak memory 218636 kb
Host smart-b64a43c6-e8e2-4c9f-a1bf-8ece1b974110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561630802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1561630802
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1027207722
Short name T731
Test name
Test status
Simulation time 41397346 ps
CPU time 1.48 seconds
Started Apr 21 01:37:24 PM PDT 24
Finished Apr 21 01:37:26 PM PDT 24
Peak memory 217276 kb
Host smart-72cdfc62-5414-4de9-a021-df9048e009e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027207722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1027207722
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.1681822985
Short name T133
Test name
Test status
Simulation time 25675522 ps
CPU time 1.03 seconds
Started Apr 21 01:37:23 PM PDT 24
Finished Apr 21 01:37:24 PM PDT 24
Peak memory 224372 kb
Host smart-507c2a68-0b18-4884-a51f-01add93fbbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681822985 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1681822985
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.730398932
Short name T337
Test name
Test status
Simulation time 38271714 ps
CPU time 1.35 seconds
Started Apr 21 01:37:21 PM PDT 24
Finished Apr 21 01:37:23 PM PDT 24
Peak memory 218436 kb
Host smart-f52f2394-acd6-45e9-a767-5da093bd885d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730398932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.730398932
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.640268775
Short name T148
Test name
Test status
Simulation time 23046010 ps
CPU time 1.07 seconds
Started Apr 21 01:37:25 PM PDT 24
Finished Apr 21 01:37:26 PM PDT 24
Peak memory 218868 kb
Host smart-4d05862f-ba68-4361-98ef-309e64cb3ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640268775 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.640268775
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3829682916
Short name T660
Test name
Test status
Simulation time 269641886 ps
CPU time 3.12 seconds
Started Apr 21 01:37:20 PM PDT 24
Finished Apr 21 01:37:24 PM PDT 24
Peak memory 217708 kb
Host smart-afc1414c-502c-4691-8f67-5482dc052878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829682916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3829682916
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.3110316291
Short name T643
Test name
Test status
Simulation time 23187281 ps
CPU time 0.87 seconds
Started Apr 21 01:37:24 PM PDT 24
Finished Apr 21 01:37:25 PM PDT 24
Peak memory 218564 kb
Host smart-95f62b6d-7468-43c4-8bf6-e152d1f82ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110316291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3110316291
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.748364651
Short name T721
Test name
Test status
Simulation time 27981209 ps
CPU time 1.26 seconds
Started Apr 21 01:37:23 PM PDT 24
Finished Apr 21 01:37:24 PM PDT 24
Peak memory 218956 kb
Host smart-9ec94f16-640f-4cdd-a994-8c401df74bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748364651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.748364651
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.274773146
Short name T821
Test name
Test status
Simulation time 29777831 ps
CPU time 0.89 seconds
Started Apr 21 01:37:25 PM PDT 24
Finished Apr 21 01:37:26 PM PDT 24
Peak memory 218504 kb
Host smart-2d009179-7b58-4a66-8e21-feee2f805886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274773146 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.274773146
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3644872881
Short name T711
Test name
Test status
Simulation time 50594062 ps
CPU time 1.21 seconds
Started Apr 21 01:37:25 PM PDT 24
Finished Apr 21 01:37:27 PM PDT 24
Peak memory 219980 kb
Host smart-a8d5fa3d-6282-4ebc-9bab-c265faf746a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644872881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3644872881
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2810224743
Short name T137
Test name
Test status
Simulation time 20765112 ps
CPU time 1.06 seconds
Started Apr 21 01:37:24 PM PDT 24
Finished Apr 21 01:37:25 PM PDT 24
Peak memory 224368 kb
Host smart-328781a2-c8d2-4593-87d6-b6e84a3e264a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810224743 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2810224743
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/58.edn_err.968706014
Short name T461
Test name
Test status
Simulation time 19630429 ps
CPU time 1.02 seconds
Started Apr 21 01:37:26 PM PDT 24
Finished Apr 21 01:37:27 PM PDT 24
Peak memory 218776 kb
Host smart-6e00b08a-6437-452d-a4ca-fae2c1e0f22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968706014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.968706014
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.476627180
Short name T287
Test name
Test status
Simulation time 45015402 ps
CPU time 1.39 seconds
Started Apr 21 01:37:26 PM PDT 24
Finished Apr 21 01:37:28 PM PDT 24
Peak memory 218792 kb
Host smart-2b8f0d0e-1ee0-46c6-a981-ca067e713b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476627180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.476627180
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.1478968605
Short name T186
Test name
Test status
Simulation time 38877938 ps
CPU time 0.96 seconds
Started Apr 21 01:37:27 PM PDT 24
Finished Apr 21 01:37:28 PM PDT 24
Peak memory 224196 kb
Host smart-9c73b9e7-ed2a-4d64-9087-3d96616a16f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478968605 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1478968605
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2694776861
Short name T55
Test name
Test status
Simulation time 108517820 ps
CPU time 1.57 seconds
Started Apr 21 01:37:29 PM PDT 24
Finished Apr 21 01:37:31 PM PDT 24
Peak memory 218740 kb
Host smart-75fbe137-2ee4-44ef-9114-667608c2f8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694776861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2694776861
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.966525874
Short name T831
Test name
Test status
Simulation time 95693604 ps
CPU time 1.14 seconds
Started Apr 21 01:35:15 PM PDT 24
Finished Apr 21 01:35:16 PM PDT 24
Peak memory 216112 kb
Host smart-222df72a-cb74-448e-b752-2d890594b924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966525874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.966525874
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3038362355
Short name T683
Test name
Test status
Simulation time 21069523 ps
CPU time 0.84 seconds
Started Apr 21 01:35:13 PM PDT 24
Finished Apr 21 01:35:14 PM PDT 24
Peak memory 206856 kb
Host smart-38107ee9-6f52-41bb-bb7a-2b1d0ce8ba71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038362355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3038362355
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3506326576
Short name T194
Test name
Test status
Simulation time 12155571 ps
CPU time 0.88 seconds
Started Apr 21 01:35:14 PM PDT 24
Finished Apr 21 01:35:15 PM PDT 24
Peak memory 216864 kb
Host smart-b788d27e-367c-4772-bdc9-1ef79240291a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506326576 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3506326576
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.551720120
Short name T123
Test name
Test status
Simulation time 49665296 ps
CPU time 1.01 seconds
Started Apr 21 01:35:13 PM PDT 24
Finished Apr 21 01:35:14 PM PDT 24
Peak memory 217200 kb
Host smart-427960e1-35f3-4521-b3f2-841abff00c86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551720120 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.551720120
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.905588721
Short name T515
Test name
Test status
Simulation time 32832107 ps
CPU time 1.04 seconds
Started Apr 21 01:35:14 PM PDT 24
Finished Apr 21 01:35:16 PM PDT 24
Peak memory 219160 kb
Host smart-d968835e-8666-410b-8c43-bb51389c7a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905588721 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.905588721
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_intr.2487598149
Short name T106
Test name
Test status
Simulation time 38661565 ps
CPU time 0.83 seconds
Started Apr 21 01:35:12 PM PDT 24
Finished Apr 21 01:35:13 PM PDT 24
Peak memory 215964 kb
Host smart-ff46ec4f-bce5-4021-bf67-13efe07ec7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487598149 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2487598149
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.69673859
Short name T260
Test name
Test status
Simulation time 31196994 ps
CPU time 0.92 seconds
Started Apr 21 01:35:12 PM PDT 24
Finished Apr 21 01:35:13 PM PDT 24
Peak memory 207448 kb
Host smart-17fcdd08-d47c-4c46-b88b-4892285c7f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69673859 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.69673859
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.728306710
Short name T307
Test name
Test status
Simulation time 30228461 ps
CPU time 0.9 seconds
Started Apr 21 01:35:12 PM PDT 24
Finished Apr 21 01:35:13 PM PDT 24
Peak memory 215656 kb
Host smart-c9db0f21-4f26-4733-9e03-c92dd84dcadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728306710 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.728306710
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2364151111
Short name T262
Test name
Test status
Simulation time 253012056 ps
CPU time 5.19 seconds
Started Apr 21 01:35:10 PM PDT 24
Finished Apr 21 01:35:16 PM PDT 24
Peak memory 219504 kb
Host smart-8199968a-687f-49fd-8131-f388c0b8865e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364151111 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2364151111
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3686935625
Short name T770
Test name
Test status
Simulation time 536731530260 ps
CPU time 1884.06 seconds
Started Apr 21 01:35:10 PM PDT 24
Finished Apr 21 02:06:35 PM PDT 24
Peak memory 226376 kb
Host smart-7b2312cc-9c71-489d-b70a-cd3da7fb6e8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686935625 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3686935625
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.3111886004
Short name T616
Test name
Test status
Simulation time 30427151 ps
CPU time 1.16 seconds
Started Apr 21 01:37:28 PM PDT 24
Finished Apr 21 01:37:30 PM PDT 24
Peak memory 224300 kb
Host smart-003d9c32-4d4f-4b77-905f-459a9433043b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111886004 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3111886004
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3218685843
Short name T667
Test name
Test status
Simulation time 156630358 ps
CPU time 1.1 seconds
Started Apr 21 01:37:27 PM PDT 24
Finished Apr 21 01:37:28 PM PDT 24
Peak memory 217132 kb
Host smart-806f6213-816b-48e8-89cd-808225283b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218685843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3218685843
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.2231254130
Short name T797
Test name
Test status
Simulation time 40718001 ps
CPU time 0.96 seconds
Started Apr 21 01:37:27 PM PDT 24
Finished Apr 21 01:37:28 PM PDT 24
Peak memory 224172 kb
Host smart-65b196cd-84f9-4994-bef7-9500898e182c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231254130 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2231254130
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3909613561
Short name T539
Test name
Test status
Simulation time 69787526 ps
CPU time 1.11 seconds
Started Apr 21 01:37:27 PM PDT 24
Finished Apr 21 01:37:29 PM PDT 24
Peak memory 218948 kb
Host smart-54e180d3-6422-48f4-8518-b944fabf0a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909613561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3909613561
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.3150611185
Short name T305
Test name
Test status
Simulation time 32012641 ps
CPU time 0.79 seconds
Started Apr 21 01:37:25 PM PDT 24
Finished Apr 21 01:37:26 PM PDT 24
Peak memory 215568 kb
Host smart-6d8f4f22-ef1c-47ee-acff-0c0fffda65bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150611185 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3150611185
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.47478695
Short name T508
Test name
Test status
Simulation time 80195838 ps
CPU time 1.25 seconds
Started Apr 21 01:37:26 PM PDT 24
Finished Apr 21 01:37:27 PM PDT 24
Peak memory 217384 kb
Host smart-24f98342-3dce-446a-b2f4-b715f1734777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47478695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.47478695
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.852461586
Short name T431
Test name
Test status
Simulation time 22942859 ps
CPU time 0.97 seconds
Started Apr 21 01:37:25 PM PDT 24
Finished Apr 21 01:37:26 PM PDT 24
Peak memory 224328 kb
Host smart-1419a094-f745-4cad-b073-da063c88695e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852461586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.852461586
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3587386471
Short name T434
Test name
Test status
Simulation time 124130180 ps
CPU time 1.53 seconds
Started Apr 21 01:37:28 PM PDT 24
Finished Apr 21 01:37:30 PM PDT 24
Peak memory 218608 kb
Host smart-9b6751b4-1a95-45ff-a2c6-a6c13fceb233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587386471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3587386471
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.76289415
Short name T177
Test name
Test status
Simulation time 28820956 ps
CPU time 0.85 seconds
Started Apr 21 01:37:30 PM PDT 24
Finished Apr 21 01:37:31 PM PDT 24
Peak memory 218824 kb
Host smart-36e3adf9-a2cb-4e02-ad4b-4fca04e83f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76289415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.76289415
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2991886811
Short name T669
Test name
Test status
Simulation time 68376529 ps
CPU time 1.11 seconds
Started Apr 21 01:37:28 PM PDT 24
Finished Apr 21 01:37:29 PM PDT 24
Peak memory 219080 kb
Host smart-92145c75-fc59-4b70-aa50-2148a40c0be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991886811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2991886811
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_genbits.981375115
Short name T7
Test name
Test status
Simulation time 108787693 ps
CPU time 2.27 seconds
Started Apr 21 01:37:30 PM PDT 24
Finished Apr 21 01:37:32 PM PDT 24
Peak memory 220212 kb
Host smart-7b81f67f-8e44-41ba-a196-7b48c2de6e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981375115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.981375115
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.1961429612
Short name T583
Test name
Test status
Simulation time 21007283 ps
CPU time 0.94 seconds
Started Apr 21 01:37:29 PM PDT 24
Finished Apr 21 01:37:30 PM PDT 24
Peak memory 218968 kb
Host smart-99aef231-10a3-4579-b076-84f16723d673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961429612 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1961429612
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3963887635
Short name T521
Test name
Test status
Simulation time 43052967 ps
CPU time 1.46 seconds
Started Apr 21 01:37:28 PM PDT 24
Finished Apr 21 01:37:30 PM PDT 24
Peak memory 217400 kb
Host smart-88e25f85-593d-42b5-9d75-cab94b37787c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963887635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3963887635
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.1507097199
Short name T6
Test name
Test status
Simulation time 31991755 ps
CPU time 0.91 seconds
Started Apr 21 01:37:33 PM PDT 24
Finished Apr 21 01:37:34 PM PDT 24
Peak memory 218600 kb
Host smart-d74d516c-2032-4136-8925-6ee5efefe0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507097199 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1507097199
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1125954648
Short name T730
Test name
Test status
Simulation time 61909247 ps
CPU time 1.11 seconds
Started Apr 21 01:37:29 PM PDT 24
Finished Apr 21 01:37:30 PM PDT 24
Peak memory 218984 kb
Host smart-48cb5071-284f-425f-9479-167da6b1eccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125954648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1125954648
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.3495731353
Short name T541
Test name
Test status
Simulation time 20888392 ps
CPU time 1 seconds
Started Apr 21 01:37:31 PM PDT 24
Finished Apr 21 01:37:32 PM PDT 24
Peak memory 218812 kb
Host smart-54c63252-a22c-49d1-8ca9-f4ed9d78b15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495731353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3495731353
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.971255745
Short name T791
Test name
Test status
Simulation time 126578539 ps
CPU time 1.22 seconds
Started Apr 21 01:37:29 PM PDT 24
Finished Apr 21 01:37:31 PM PDT 24
Peak memory 217644 kb
Host smart-0201798c-9c49-4887-9549-f6a8ceacdd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971255745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.971255745
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.3530617790
Short name T122
Test name
Test status
Simulation time 35853355 ps
CPU time 1.03 seconds
Started Apr 21 01:37:31 PM PDT 24
Finished Apr 21 01:37:32 PM PDT 24
Peak memory 230076 kb
Host smart-dec6c1a7-8c07-44e5-bb5b-d01e66ae7c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530617790 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3530617790
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1525051624
Short name T754
Test name
Test status
Simulation time 228659386 ps
CPU time 3.55 seconds
Started Apr 21 01:37:31 PM PDT 24
Finished Apr 21 01:37:35 PM PDT 24
Peak memory 220396 kb
Host smart-c51240a5-76f8-4018-898e-0fe1dc3a767c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525051624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1525051624
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert_test.1804805327
Short name T310
Test name
Test status
Simulation time 12896517 ps
CPU time 0.89 seconds
Started Apr 21 01:35:18 PM PDT 24
Finished Apr 21 01:35:19 PM PDT 24
Peak memory 207424 kb
Host smart-22f1280d-16ff-49d6-a245-60ac4d027b12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804805327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1804805327
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.878816989
Short name T180
Test name
Test status
Simulation time 17638098 ps
CPU time 0.82 seconds
Started Apr 21 01:35:16 PM PDT 24
Finished Apr 21 01:35:17 PM PDT 24
Peak memory 216816 kb
Host smart-b8347599-8aef-4133-8f54-ad486b2c6638
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878816989 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.878816989
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.4261701794
Short name T725
Test name
Test status
Simulation time 45506492 ps
CPU time 1.09 seconds
Started Apr 21 01:35:17 PM PDT 24
Finished Apr 21 01:35:18 PM PDT 24
Peak memory 217080 kb
Host smart-249c1fd0-0c50-4550-ab98-378cec7529d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261701794 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.4261701794
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3270325408
Short name T61
Test name
Test status
Simulation time 18802762 ps
CPU time 1.18 seconds
Started Apr 21 01:35:16 PM PDT 24
Finished Apr 21 01:35:18 PM PDT 24
Peak memory 224376 kb
Host smart-d45a0a04-785a-47dd-8e49-f44366e40ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270325408 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3270325408
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2455752424
Short name T822
Test name
Test status
Simulation time 63363479 ps
CPU time 1.3 seconds
Started Apr 21 01:35:18 PM PDT 24
Finished Apr 21 01:35:20 PM PDT 24
Peak memory 217296 kb
Host smart-3fcbbc49-92ed-4f6c-8787-5e61120fc234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455752424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2455752424
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_regwen.4092403584
Short name T663
Test name
Test status
Simulation time 18527119 ps
CPU time 0.93 seconds
Started Apr 21 01:35:23 PM PDT 24
Finished Apr 21 01:35:24 PM PDT 24
Peak memory 207440 kb
Host smart-1def59ff-d408-4a1a-9a7e-405efad4ad74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092403584 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.4092403584
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.4098743169
Short name T368
Test name
Test status
Simulation time 47839498 ps
CPU time 1.03 seconds
Started Apr 21 01:35:19 PM PDT 24
Finished Apr 21 01:35:20 PM PDT 24
Peak memory 215632 kb
Host smart-581485e3-8a8f-436a-b9be-a919a1098290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098743169 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.4098743169
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1155561196
Short name T804
Test name
Test status
Simulation time 472850733 ps
CPU time 5.58 seconds
Started Apr 21 01:35:15 PM PDT 24
Finished Apr 21 01:35:21 PM PDT 24
Peak memory 217288 kb
Host smart-59da7d02-11d3-4f92-98f7-ddb4a00069af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155561196 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1155561196
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1463102488
Short name T369
Test name
Test status
Simulation time 115471014060 ps
CPU time 501.18 seconds
Started Apr 21 01:35:12 PM PDT 24
Finished Apr 21 01:43:33 PM PDT 24
Peak memory 219264 kb
Host smart-5ebaf863-da21-4a58-bb51-336a8c1091f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463102488 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1463102488
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.2784715725
Short name T736
Test name
Test status
Simulation time 23563098 ps
CPU time 0.9 seconds
Started Apr 21 01:37:31 PM PDT 24
Finished Apr 21 01:37:32 PM PDT 24
Peak memory 218736 kb
Host smart-973172cb-0af5-4588-bceb-8146de132685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784715725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2784715725
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.558200052
Short name T776
Test name
Test status
Simulation time 225654384 ps
CPU time 2.44 seconds
Started Apr 21 01:37:33 PM PDT 24
Finished Apr 21 01:37:35 PM PDT 24
Peak memory 217408 kb
Host smart-e7fd1239-f277-4c72-8b2c-6c7b22c944d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558200052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.558200052
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.3864611024
Short name T4
Test name
Test status
Simulation time 59383742 ps
CPU time 1.03 seconds
Started Apr 21 01:37:32 PM PDT 24
Finished Apr 21 01:37:33 PM PDT 24
Peak memory 229912 kb
Host smart-8cbf42a6-53ad-4756-b7e9-18138884c8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864611024 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3864611024
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2389968735
Short name T314
Test name
Test status
Simulation time 48100639 ps
CPU time 1.15 seconds
Started Apr 21 01:37:33 PM PDT 24
Finished Apr 21 01:37:34 PM PDT 24
Peak memory 218436 kb
Host smart-304271bd-d894-440b-8c22-c245bf11a187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389968735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2389968735
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.255445642
Short name T801
Test name
Test status
Simulation time 28143029 ps
CPU time 0.85 seconds
Started Apr 21 01:37:34 PM PDT 24
Finished Apr 21 01:37:35 PM PDT 24
Peak memory 218360 kb
Host smart-8ae582e2-ee4c-4515-8ea0-5e6303cc9a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255445642 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.255445642
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3821774941
Short name T346
Test name
Test status
Simulation time 42856015 ps
CPU time 1.42 seconds
Started Apr 21 01:37:33 PM PDT 24
Finished Apr 21 01:37:35 PM PDT 24
Peak memory 218368 kb
Host smart-1332d664-a3b7-4363-ab61-4943e8aba094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821774941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3821774941
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.1394086497
Short name T8
Test name
Test status
Simulation time 24317108 ps
CPU time 1.15 seconds
Started Apr 21 01:37:33 PM PDT 24
Finished Apr 21 01:37:34 PM PDT 24
Peak memory 220876 kb
Host smart-37c3f872-c1a4-4dd2-8a28-ca4f200e09c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394086497 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1394086497
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1717044595
Short name T537
Test name
Test status
Simulation time 167571032 ps
CPU time 1.45 seconds
Started Apr 21 01:37:31 PM PDT 24
Finished Apr 21 01:37:33 PM PDT 24
Peak memory 219052 kb
Host smart-c3a4f152-0fc4-443e-9373-625ffb3d5144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717044595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1717044595
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.1318003767
Short name T810
Test name
Test status
Simulation time 18420078 ps
CPU time 1.04 seconds
Started Apr 21 01:37:34 PM PDT 24
Finished Apr 21 01:37:36 PM PDT 24
Peak memory 218564 kb
Host smart-4b9228a5-6d9e-4816-b5ee-d54ad1d47a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318003767 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1318003767
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1183522551
Short name T282
Test name
Test status
Simulation time 68009868 ps
CPU time 1.39 seconds
Started Apr 21 01:37:36 PM PDT 24
Finished Apr 21 01:37:37 PM PDT 24
Peak memory 218880 kb
Host smart-52679570-134a-4947-bb42-2693ba6e2e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183522551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1183522551
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.1952034856
Short name T396
Test name
Test status
Simulation time 29456268 ps
CPU time 0.95 seconds
Started Apr 21 01:37:36 PM PDT 24
Finished Apr 21 01:37:37 PM PDT 24
Peak memory 224064 kb
Host smart-2d040acb-c95c-46b8-b718-5af089a67d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952034856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1952034856
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.4119421980
Short name T813
Test name
Test status
Simulation time 74534432 ps
CPU time 1 seconds
Started Apr 21 01:37:35 PM PDT 24
Finished Apr 21 01:37:36 PM PDT 24
Peak memory 217468 kb
Host smart-deff0b8d-6342-414a-b175-27de89812743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119421980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.4119421980
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.2408858307
Short name T704
Test name
Test status
Simulation time 18782613 ps
CPU time 1.04 seconds
Started Apr 21 01:37:33 PM PDT 24
Finished Apr 21 01:37:35 PM PDT 24
Peak memory 218952 kb
Host smart-966d6aa1-de81-482a-96af-411190ed000e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408858307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2408858307
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3600857178
Short name T386
Test name
Test status
Simulation time 48438652 ps
CPU time 1.9 seconds
Started Apr 21 01:37:35 PM PDT 24
Finished Apr 21 01:37:37 PM PDT 24
Peak memory 220180 kb
Host smart-0a2b2617-d58f-4802-9fcd-7bbb4d2ef2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600857178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3600857178
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.1014875719
Short name T117
Test name
Test status
Simulation time 24266993 ps
CPU time 1.05 seconds
Started Apr 21 01:37:39 PM PDT 24
Finished Apr 21 01:37:40 PM PDT 24
Peak memory 229952 kb
Host smart-b34c6992-2cd7-4bb3-a171-dc27e3da3ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014875719 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1014875719
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.326199154
Short name T679
Test name
Test status
Simulation time 78269027 ps
CPU time 1.34 seconds
Started Apr 21 01:37:38 PM PDT 24
Finished Apr 21 01:37:40 PM PDT 24
Peak memory 218732 kb
Host smart-af5945d2-f00a-4f08-90ab-547d4cc074ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326199154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.326199154
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.3997717498
Short name T108
Test name
Test status
Simulation time 40029455 ps
CPU time 1.02 seconds
Started Apr 21 01:37:40 PM PDT 24
Finished Apr 21 01:37:41 PM PDT 24
Peak memory 229944 kb
Host smart-09b3272d-bb82-464b-820b-dd84d22c6b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997717498 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3997717498
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.618638805
Short name T293
Test name
Test status
Simulation time 42567383 ps
CPU time 1.55 seconds
Started Apr 21 01:37:40 PM PDT 24
Finished Apr 21 01:37:42 PM PDT 24
Peak memory 219908 kb
Host smart-5e8452bd-30c6-4128-b383-a84dbed47030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618638805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.618638805
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.34808887
Short name T134
Test name
Test status
Simulation time 26011629 ps
CPU time 1.02 seconds
Started Apr 21 01:37:39 PM PDT 24
Finished Apr 21 01:37:41 PM PDT 24
Peak memory 224388 kb
Host smart-6474edf3-a7c9-4bba-b892-ccd014f3fe3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34808887 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.34808887
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2383350110
Short name T617
Test name
Test status
Simulation time 54190901 ps
CPU time 1.03 seconds
Started Apr 21 01:37:39 PM PDT 24
Finished Apr 21 01:37:41 PM PDT 24
Peak memory 217452 kb
Host smart-21006989-4879-455d-b46c-cfd6ce214662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383350110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2383350110
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1001201974
Short name T161
Test name
Test status
Simulation time 29570559 ps
CPU time 1.25 seconds
Started Apr 21 01:35:20 PM PDT 24
Finished Apr 21 01:35:22 PM PDT 24
Peak memory 216096 kb
Host smart-6771e249-0fce-4ebb-a373-3a363a709c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001201974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1001201974
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3513495673
Short name T459
Test name
Test status
Simulation time 27331365 ps
CPU time 0.75 seconds
Started Apr 21 01:35:21 PM PDT 24
Finished Apr 21 01:35:22 PM PDT 24
Peak memory 206360 kb
Host smart-148e3167-96aa-4359-a05b-2a15460d1ee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513495673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3513495673
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1938597183
Short name T323
Test name
Test status
Simulation time 36687354 ps
CPU time 0.82 seconds
Started Apr 21 01:35:18 PM PDT 24
Finished Apr 21 01:35:19 PM PDT 24
Peak memory 216428 kb
Host smart-0a349c55-942a-4e7c-8122-39e62ce8f286
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938597183 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1938597183
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3769732530
Short name T832
Test name
Test status
Simulation time 51977275 ps
CPU time 1.41 seconds
Started Apr 21 01:35:19 PM PDT 24
Finished Apr 21 01:35:20 PM PDT 24
Peak memory 217320 kb
Host smart-1694e1aa-a935-4f7b-b96a-a8011708fe0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769732530 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3769732530
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3244109377
Short name T746
Test name
Test status
Simulation time 24258216 ps
CPU time 1.01 seconds
Started Apr 21 01:35:18 PM PDT 24
Finished Apr 21 01:35:19 PM PDT 24
Peak memory 224384 kb
Host smart-7e0208bd-1922-4923-95a9-a0648ed2abe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244109377 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3244109377
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3980452740
Short name T357
Test name
Test status
Simulation time 55564742 ps
CPU time 2.27 seconds
Started Apr 21 01:35:21 PM PDT 24
Finished Apr 21 01:35:24 PM PDT 24
Peak memory 220188 kb
Host smart-461bad89-0547-4c27-9658-7295152c9518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980452740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3980452740
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3710519071
Short name T708
Test name
Test status
Simulation time 19646172 ps
CPU time 1.08 seconds
Started Apr 21 01:35:24 PM PDT 24
Finished Apr 21 01:35:26 PM PDT 24
Peak memory 216120 kb
Host smart-20a093ac-951b-4f9e-9ff7-c8a0ae936340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710519071 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3710519071
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.2096671128
Short name T29
Test name
Test status
Simulation time 46163071 ps
CPU time 0.91 seconds
Started Apr 21 01:35:20 PM PDT 24
Finished Apr 21 01:35:21 PM PDT 24
Peak memory 207432 kb
Host smart-4a58cd37-2f4d-4a2f-accb-5387ccf07039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096671128 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2096671128
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1031814333
Short name T823
Test name
Test status
Simulation time 26347208 ps
CPU time 0.94 seconds
Started Apr 21 01:35:20 PM PDT 24
Finished Apr 21 01:35:21 PM PDT 24
Peak memory 215640 kb
Host smart-79722efd-16eb-4d47-9ce1-0348cbf3bfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031814333 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1031814333
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1464657231
Short name T516
Test name
Test status
Simulation time 191895455 ps
CPU time 4.01 seconds
Started Apr 21 01:35:23 PM PDT 24
Finished Apr 21 01:35:27 PM PDT 24
Peak memory 218548 kb
Host smart-5c05472c-b121-4732-8d08-aeaf4623d64c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464657231 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1464657231
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.733817818
Short name T44
Test name
Test status
Simulation time 370830333981 ps
CPU time 1078.91 seconds
Started Apr 21 01:35:21 PM PDT 24
Finished Apr 21 01:53:20 PM PDT 24
Peak memory 222920 kb
Host smart-30e53706-a484-41b7-b1f5-8ef193b74723
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733817818 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.733817818
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.672741639
Short name T62
Test name
Test status
Simulation time 85765805 ps
CPU time 1.02 seconds
Started Apr 21 01:37:44 PM PDT 24
Finished Apr 21 01:37:45 PM PDT 24
Peak memory 224372 kb
Host smart-38dfc37b-6b7f-4e04-ab3b-c45fbf0f3d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672741639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.672741639
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2620144212
Short name T90
Test name
Test status
Simulation time 109216917 ps
CPU time 1.31 seconds
Started Apr 21 01:37:39 PM PDT 24
Finished Apr 21 01:37:41 PM PDT 24
Peak memory 218480 kb
Host smart-6d44bdcd-2d0b-4d6f-b73a-2b77b7a442ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620144212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2620144212
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.3046462791
Short name T365
Test name
Test status
Simulation time 45994524 ps
CPU time 1.05 seconds
Started Apr 21 01:37:41 PM PDT 24
Finished Apr 21 01:37:42 PM PDT 24
Peak memory 224384 kb
Host smart-43ac7635-5db6-4123-9513-ef315ca57dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046462791 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3046462791
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3871754844
Short name T555
Test name
Test status
Simulation time 140923296 ps
CPU time 2.03 seconds
Started Apr 21 01:37:41 PM PDT 24
Finished Apr 21 01:37:43 PM PDT 24
Peak memory 220096 kb
Host smart-e634e064-1a81-48c2-9043-3bbd178c577b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871754844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3871754844
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.4197370972
Short name T107
Test name
Test status
Simulation time 50920299 ps
CPU time 0.96 seconds
Started Apr 21 01:37:43 PM PDT 24
Finished Apr 21 01:37:45 PM PDT 24
Peak memory 220064 kb
Host smart-64c2e9c3-bc4b-4553-aac7-fabd348f040b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197370972 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.4197370972
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3126031904
Short name T96
Test name
Test status
Simulation time 68462329 ps
CPU time 1.01 seconds
Started Apr 21 01:37:40 PM PDT 24
Finished Apr 21 01:37:42 PM PDT 24
Peak memory 217256 kb
Host smart-a7c3fbfa-4580-4a55-a455-a5cd06888a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126031904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3126031904
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.2658190308
Short name T514
Test name
Test status
Simulation time 28326000 ps
CPU time 1.01 seconds
Started Apr 21 01:37:40 PM PDT 24
Finished Apr 21 01:37:41 PM PDT 24
Peak memory 224368 kb
Host smart-d7ed5236-49ed-41a0-b814-11cba6e42ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658190308 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2658190308
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2423098482
Short name T376
Test name
Test status
Simulation time 98176567 ps
CPU time 1.14 seconds
Started Apr 21 01:37:40 PM PDT 24
Finished Apr 21 01:37:42 PM PDT 24
Peak memory 217256 kb
Host smart-f1ccd27f-1b0e-4c5a-ad88-1502749298d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423098482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2423098482
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.2463103516
Short name T825
Test name
Test status
Simulation time 23319307 ps
CPU time 1.02 seconds
Started Apr 21 01:37:39 PM PDT 24
Finished Apr 21 01:37:41 PM PDT 24
Peak memory 224508 kb
Host smart-84baf5ec-d48b-480a-9aa8-e714e48b9e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463103516 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2463103516
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3151093432
Short name T705
Test name
Test status
Simulation time 51411820 ps
CPU time 1.4 seconds
Started Apr 21 01:37:40 PM PDT 24
Finished Apr 21 01:37:41 PM PDT 24
Peak memory 218676 kb
Host smart-4a522c7a-39e7-4997-99ba-1d4b2f991b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151093432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3151093432
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.329773470
Short name T121
Test name
Test status
Simulation time 77335887 ps
CPU time 0.93 seconds
Started Apr 21 01:37:40 PM PDT 24
Finished Apr 21 01:37:42 PM PDT 24
Peak memory 219960 kb
Host smart-673f9d32-9331-4446-a478-de4810f6cb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329773470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.329773470
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2290253385
Short name T277
Test name
Test status
Simulation time 40466386 ps
CPU time 1.39 seconds
Started Apr 21 01:37:41 PM PDT 24
Finished Apr 21 01:37:43 PM PDT 24
Peak memory 218524 kb
Host smart-b62abf2b-f2b4-4ccb-8e03-760da5fdfa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290253385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2290253385
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.2989754461
Short name T329
Test name
Test status
Simulation time 19048709 ps
CPU time 0.94 seconds
Started Apr 21 01:37:44 PM PDT 24
Finished Apr 21 01:37:45 PM PDT 24
Peak memory 218672 kb
Host smart-dbcf3bff-d3df-48ba-a62a-60806089c201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989754461 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2989754461
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2090947970
Short name T53
Test name
Test status
Simulation time 127342808 ps
CPU time 1.21 seconds
Started Apr 21 01:37:43 PM PDT 24
Finished Apr 21 01:37:44 PM PDT 24
Peak memory 218696 kb
Host smart-89c9589b-0d71-4061-82af-48c722a25d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090947970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2090947970
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1701369308
Short name T491
Test name
Test status
Simulation time 23113941 ps
CPU time 1.1 seconds
Started Apr 21 01:37:44 PM PDT 24
Finished Apr 21 01:37:46 PM PDT 24
Peak memory 224360 kb
Host smart-fa572cf3-2065-47ad-bff0-079b7c80529b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701369308 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1701369308
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2000213578
Short name T629
Test name
Test status
Simulation time 42838173 ps
CPU time 1.63 seconds
Started Apr 21 01:37:45 PM PDT 24
Finished Apr 21 01:37:47 PM PDT 24
Peak memory 217416 kb
Host smart-7ca9b13a-6ce7-42be-bc5c-6568ec443328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000213578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2000213578
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.1947899521
Short name T116
Test name
Test status
Simulation time 55920281 ps
CPU time 1.02 seconds
Started Apr 21 01:37:45 PM PDT 24
Finished Apr 21 01:37:46 PM PDT 24
Peak memory 220972 kb
Host smart-9bbd7454-9655-438c-ae53-0d42ad4c2a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947899521 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1947899521
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2866148577
Short name T382
Test name
Test status
Simulation time 187419470 ps
CPU time 1.64 seconds
Started Apr 21 01:37:43 PM PDT 24
Finished Apr 21 01:37:45 PM PDT 24
Peak memory 219036 kb
Host smart-a0fbfd75-f4a3-4469-9b7a-21704134e799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866148577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2866148577
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.3640087826
Short name T689
Test name
Test status
Simulation time 22600994 ps
CPU time 0.94 seconds
Started Apr 21 01:37:45 PM PDT 24
Finished Apr 21 01:37:46 PM PDT 24
Peak memory 218832 kb
Host smart-9c988ebb-4cee-48b5-ab7b-cc4259df60e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640087826 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3640087826
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.4110416314
Short name T675
Test name
Test status
Simulation time 89225774 ps
CPU time 1.14 seconds
Started Apr 21 01:37:44 PM PDT 24
Finished Apr 21 01:37:45 PM PDT 24
Peak memory 218400 kb
Host smart-a04e37be-e428-4e6a-b8dd-c0bfb7272938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110416314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.4110416314
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.722780047
Short name T136
Test name
Test status
Simulation time 24604400 ps
CPU time 1.1 seconds
Started Apr 21 01:35:24 PM PDT 24
Finished Apr 21 01:35:25 PM PDT 24
Peak memory 216072 kb
Host smart-0d5928fb-55b9-4efb-9923-97887ecbb134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722780047 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.722780047
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2406228344
Short name T421
Test name
Test status
Simulation time 47692306 ps
CPU time 0.88 seconds
Started Apr 21 01:35:31 PM PDT 24
Finished Apr 21 01:35:32 PM PDT 24
Peak memory 206944 kb
Host smart-4956f563-9e94-4a9f-94c3-1989ac74b296
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406228344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2406228344
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3904387591
Short name T591
Test name
Test status
Simulation time 12740733 ps
CPU time 0.92 seconds
Started Apr 21 01:35:24 PM PDT 24
Finished Apr 21 01:35:25 PM PDT 24
Peak memory 216804 kb
Host smart-5f9f98f6-6343-4db4-abe3-3c2d35de21c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904387591 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3904387591
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.940590656
Short name T784
Test name
Test status
Simulation time 84107304 ps
CPU time 0.98 seconds
Started Apr 21 01:35:23 PM PDT 24
Finished Apr 21 01:35:24 PM PDT 24
Peak memory 217316 kb
Host smart-73eb7e1f-333b-40e2-858a-8722d94e6c58
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940590656 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.940590656
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3780986192
Short name T654
Test name
Test status
Simulation time 30851106 ps
CPU time 0.98 seconds
Started Apr 21 01:35:24 PM PDT 24
Finished Apr 21 01:35:25 PM PDT 24
Peak memory 224136 kb
Host smart-6c61f799-9766-4593-8987-9742e11539af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780986192 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3780986192
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1690363255
Short name T472
Test name
Test status
Simulation time 44718193 ps
CPU time 1.82 seconds
Started Apr 21 01:35:21 PM PDT 24
Finished Apr 21 01:35:23 PM PDT 24
Peak memory 218600 kb
Host smart-1b343418-138f-4ae4-989b-ebbf0b8deb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690363255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1690363255
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1831493434
Short name T154
Test name
Test status
Simulation time 19783743 ps
CPU time 1.03 seconds
Started Apr 21 01:35:31 PM PDT 24
Finished Apr 21 01:35:32 PM PDT 24
Peak memory 216096 kb
Host smart-673a376a-78c4-4535-812c-1b3a5267cd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831493434 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1831493434
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1921499165
Short name T256
Test name
Test status
Simulation time 26223479 ps
CPU time 0.91 seconds
Started Apr 21 01:35:19 PM PDT 24
Finished Apr 21 01:35:20 PM PDT 24
Peak memory 207608 kb
Host smart-5b60fef8-9408-4bc0-b166-d268069aaa6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921499165 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1921499165
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.527585087
Short name T548
Test name
Test status
Simulation time 26045535 ps
CPU time 0.92 seconds
Started Apr 21 01:35:19 PM PDT 24
Finished Apr 21 01:35:21 PM PDT 24
Peak memory 215648 kb
Host smart-31693115-09f4-4fab-860d-a16049811094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527585087 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.527585087
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2564119772
Short name T162
Test name
Test status
Simulation time 618956715 ps
CPU time 1.53 seconds
Started Apr 21 01:35:19 PM PDT 24
Finished Apr 21 01:35:21 PM PDT 24
Peak memory 215628 kb
Host smart-50aafed8-f201-4a15-a8a8-e28d9cfb2528
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564119772 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2564119772
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2291354681
Short name T686
Test name
Test status
Simulation time 145207529037 ps
CPU time 964.17 seconds
Started Apr 21 01:35:19 PM PDT 24
Finished Apr 21 01:51:23 PM PDT 24
Peak memory 223516 kb
Host smart-9ceea77a-86da-46b5-aa24-5dcaff6cc7d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291354681 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2291354681
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.444307694
Short name T146
Test name
Test status
Simulation time 22059253 ps
CPU time 0.89 seconds
Started Apr 21 01:37:43 PM PDT 24
Finished Apr 21 01:37:44 PM PDT 24
Peak memory 218792 kb
Host smart-743512a8-01a3-4543-9bd5-636b9d1c4e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444307694 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.444307694
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1033714433
Short name T605
Test name
Test status
Simulation time 42285471 ps
CPU time 1.35 seconds
Started Apr 21 01:37:47 PM PDT 24
Finished Apr 21 01:37:49 PM PDT 24
Peak memory 218744 kb
Host smart-dbc95784-bcaf-41c1-b747-5b2c5e7b12b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033714433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1033714433
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.2017692520
Short name T438
Test name
Test status
Simulation time 58254781 ps
CPU time 0.88 seconds
Started Apr 21 01:37:45 PM PDT 24
Finished Apr 21 01:37:46 PM PDT 24
Peak memory 220292 kb
Host smart-1743fbee-e07c-46a3-b0a6-60e750be2172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017692520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2017692520
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2264161136
Short name T720
Test name
Test status
Simulation time 50613454 ps
CPU time 1.51 seconds
Started Apr 21 01:37:44 PM PDT 24
Finished Apr 21 01:37:46 PM PDT 24
Peak memory 218252 kb
Host smart-9a52b0c2-f041-456d-a5af-60285c19f49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264161136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2264161136
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.2701951729
Short name T300
Test name
Test status
Simulation time 29785929 ps
CPU time 0.83 seconds
Started Apr 21 01:37:47 PM PDT 24
Finished Apr 21 01:37:48 PM PDT 24
Peak memory 218228 kb
Host smart-3fae0c00-14a9-4162-bb12-890076677041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701951729 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2701951729
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3677281083
Short name T477
Test name
Test status
Simulation time 221920665 ps
CPU time 1.36 seconds
Started Apr 21 01:37:46 PM PDT 24
Finished Apr 21 01:37:48 PM PDT 24
Peak memory 218720 kb
Host smart-e64abd74-7a15-4e9c-a3dc-76ebf14bc0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677281083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3677281083
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.129252274
Short name T809
Test name
Test status
Simulation time 32732224 ps
CPU time 0.81 seconds
Started Apr 21 01:37:48 PM PDT 24
Finished Apr 21 01:37:49 PM PDT 24
Peak memory 218700 kb
Host smart-d50211a8-6b87-4668-9543-305ebe63b471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129252274 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.129252274
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.872074899
Short name T11
Test name
Test status
Simulation time 66268492 ps
CPU time 1.1 seconds
Started Apr 21 01:37:47 PM PDT 24
Finished Apr 21 01:37:48 PM PDT 24
Peak memory 219796 kb
Host smart-7d712d86-b023-442f-9da3-1d0e126ef8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872074899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.872074899
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.2878214933
Short name T627
Test name
Test status
Simulation time 24014326 ps
CPU time 1.11 seconds
Started Apr 21 01:37:45 PM PDT 24
Finished Apr 21 01:37:46 PM PDT 24
Peak memory 220028 kb
Host smart-cc0d29e8-5846-4259-827a-bff7f1f94e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878214933 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2878214933
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2415857726
Short name T272
Test name
Test status
Simulation time 175064963 ps
CPU time 2.45 seconds
Started Apr 21 01:37:44 PM PDT 24
Finished Apr 21 01:37:47 PM PDT 24
Peak memory 220356 kb
Host smart-ae69abdf-0240-40da-baf7-95a8f4060002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415857726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2415857726
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.4274370119
Short name T681
Test name
Test status
Simulation time 27030493 ps
CPU time 1 seconds
Started Apr 21 01:37:46 PM PDT 24
Finished Apr 21 01:37:47 PM PDT 24
Peak memory 219872 kb
Host smart-a0128614-ff85-4379-a387-96745ce99c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274370119 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.4274370119
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.851284242
Short name T628
Test name
Test status
Simulation time 35770654 ps
CPU time 1.4 seconds
Started Apr 21 01:37:48 PM PDT 24
Finished Apr 21 01:37:50 PM PDT 24
Peak memory 219432 kb
Host smart-5c81080b-73af-4d57-be0a-8bef15321820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851284242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.851284242
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.2126189542
Short name T150
Test name
Test status
Simulation time 111513277 ps
CPU time 0.92 seconds
Started Apr 21 01:37:51 PM PDT 24
Finished Apr 21 01:37:52 PM PDT 24
Peak memory 224192 kb
Host smart-22e15411-0d49-45c5-b810-cea16bc9e44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126189542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2126189542
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.4192857588
Short name T268
Test name
Test status
Simulation time 43840188 ps
CPU time 1.71 seconds
Started Apr 21 01:37:51 PM PDT 24
Finished Apr 21 01:37:53 PM PDT 24
Peak memory 218700 kb
Host smart-a52e96c6-3f31-43e6-94ce-98ba2ec42bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192857588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.4192857588
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.3596897465
Short name T138
Test name
Test status
Simulation time 126646310 ps
CPU time 1.02 seconds
Started Apr 21 01:37:51 PM PDT 24
Finished Apr 21 01:37:52 PM PDT 24
Peak memory 219848 kb
Host smart-be30cfea-97c7-41ed-bebe-4709a51eae4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596897465 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3596897465
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.4021986023
Short name T46
Test name
Test status
Simulation time 57064381 ps
CPU time 1.43 seconds
Started Apr 21 01:37:52 PM PDT 24
Finished Apr 21 01:37:53 PM PDT 24
Peak memory 218948 kb
Host smart-2d1da794-0190-4afb-b2ca-153c1456f7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021986023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.4021986023
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.3963313428
Short name T795
Test name
Test status
Simulation time 72834863 ps
CPU time 1.16 seconds
Started Apr 21 01:37:49 PM PDT 24
Finished Apr 21 01:37:50 PM PDT 24
Peak memory 225048 kb
Host smart-14570c3b-4d13-4392-a8c7-c9bf26318b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963313428 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3963313428
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.565364667
Short name T554
Test name
Test status
Simulation time 90485158 ps
CPU time 1.36 seconds
Started Apr 21 01:37:51 PM PDT 24
Finished Apr 21 01:37:53 PM PDT 24
Peak memory 218800 kb
Host smart-a1b583d8-a96f-467b-95e2-4eac452ab2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565364667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.565364667
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.2361987742
Short name T65
Test name
Test status
Simulation time 31192342 ps
CPU time 0.94 seconds
Started Apr 21 01:37:50 PM PDT 24
Finished Apr 21 01:37:51 PM PDT 24
Peak memory 224188 kb
Host smart-8f0f0ce4-54f6-4a12-9581-734949f1b392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361987742 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2361987742
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.111133862
Short name T483
Test name
Test status
Simulation time 33253237 ps
CPU time 1.29 seconds
Started Apr 21 01:37:49 PM PDT 24
Finished Apr 21 01:37:51 PM PDT 24
Peak memory 217336 kb
Host smart-f8bd19d9-66d3-48cf-a602-16af4b53e485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111133862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.111133862
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%