Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 2 0 2 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 7472 1 T4 141 T51 8 T38 156
all_values[1] 7472 1 T4 141 T51 8 T38 156


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7726 1 T4 139 T51 6 T38 166
auto[1] 7218 1 T4 143 T51 10 T38 146


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5888 1 T4 110 T51 6 T38 135
auto[1] 9056 1 T4 172 T51 10 T38 177


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8897 1 T4 167 T51 10 T38 191
auto[1] 6047 1 T4 115 T51 6 T38 121


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 12 0 12 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 1473 1 T4 28 T51 1 T38 33
all_values[0] auto[0] auto[0] auto[1] 777 1 T4 13 T38 18 T154 5
all_values[0] auto[0] auto[1] auto[0] 1465 1 T4 36 T51 4 T38 34
all_values[0] auto[0] auto[1] auto[1] 745 1 T4 9 T51 1 T38 7
all_values[0] auto[1] auto[0] auto[1] 1594 1 T4 30 T51 1 T38 36
all_values[0] auto[1] auto[1] auto[1] 1418 1 T4 25 T51 1 T38 28
all_values[1] auto[0] auto[0] auto[0] 1522 1 T4 22 T51 1 T38 37
all_values[1] auto[0] auto[0] auto[1] 775 1 T4 16 T51 1 T38 15
all_values[1] auto[0] auto[1] auto[0] 1428 1 T4 24 T38 31 T154 4
all_values[1] auto[0] auto[1] auto[1] 712 1 T4 19 T51 2 T38 16
all_values[1] auto[1] auto[0] auto[1] 1585 1 T4 30 T51 2 T38 27
all_values[1] auto[1] auto[1] auto[1] 1450 1 T4 30 T51 2 T38 30


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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