Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.41 98.24 93.82 97.01 82.66 96.76 99.77 92.64


Total test records in report: 975
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T786 /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2484909322 Apr 23 02:08:37 PM PDT 24 Apr 23 02:18:55 PM PDT 24 49319563080 ps
T787 /workspace/coverage/default/19.edn_intr.3063519394 Apr 23 02:08:42 PM PDT 24 Apr 23 02:08:43 PM PDT 24 33742057 ps
T788 /workspace/coverage/default/5.edn_disable.2594925235 Apr 23 02:08:07 PM PDT 24 Apr 23 02:08:09 PM PDT 24 12433967 ps
T789 /workspace/coverage/default/7.edn_genbits.2999677182 Apr 23 02:08:13 PM PDT 24 Apr 23 02:08:15 PM PDT 24 67665419 ps
T790 /workspace/coverage/default/201.edn_genbits.3505132455 Apr 23 02:10:45 PM PDT 24 Apr 23 02:10:47 PM PDT 24 53068396 ps
T791 /workspace/coverage/default/18.edn_disable.2001851607 Apr 23 02:08:42 PM PDT 24 Apr 23 02:08:43 PM PDT 24 14323760 ps
T792 /workspace/coverage/default/31.edn_smoke.1543664874 Apr 23 02:09:10 PM PDT 24 Apr 23 02:09:11 PM PDT 24 37705734 ps
T793 /workspace/coverage/default/247.edn_genbits.2001519659 Apr 23 02:10:59 PM PDT 24 Apr 23 02:11:02 PM PDT 24 61510335 ps
T794 /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2694322904 Apr 23 02:09:43 PM PDT 24 Apr 23 02:37:56 PM PDT 24 136532436830 ps
T795 /workspace/coverage/default/216.edn_genbits.2747252514 Apr 23 02:10:49 PM PDT 24 Apr 23 02:10:51 PM PDT 24 193403852 ps
T796 /workspace/coverage/default/34.edn_genbits.4113035178 Apr 23 02:09:14 PM PDT 24 Apr 23 02:09:16 PM PDT 24 85289616 ps
T797 /workspace/coverage/default/36.edn_intr.35589569 Apr 23 02:09:19 PM PDT 24 Apr 23 02:09:20 PM PDT 24 31476454 ps
T798 /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3704763195 Apr 23 02:09:23 PM PDT 24 Apr 23 02:19:20 PM PDT 24 23520985802 ps
T799 /workspace/coverage/default/25.edn_alert.3377565446 Apr 23 02:08:58 PM PDT 24 Apr 23 02:09:00 PM PDT 24 89297912 ps
T800 /workspace/coverage/default/40.edn_genbits.3813987100 Apr 23 02:09:29 PM PDT 24 Apr 23 02:09:32 PM PDT 24 233139435 ps
T801 /workspace/coverage/default/42.edn_alert_test.1074659045 Apr 23 02:09:35 PM PDT 24 Apr 23 02:09:36 PM PDT 24 12769317 ps
T802 /workspace/coverage/default/2.edn_stress_all.694380658 Apr 23 02:08:00 PM PDT 24 Apr 23 02:08:05 PM PDT 24 223544590 ps
T803 /workspace/coverage/default/68.edn_err.2770562329 Apr 23 02:10:02 PM PDT 24 Apr 23 02:10:03 PM PDT 24 18952133 ps
T804 /workspace/coverage/default/2.edn_smoke.2370350336 Apr 23 02:07:57 PM PDT 24 Apr 23 02:07:58 PM PDT 24 19260474 ps
T805 /workspace/coverage/default/27.edn_intr.3446236569 Apr 23 02:09:04 PM PDT 24 Apr 23 02:09:06 PM PDT 24 28920188 ps
T806 /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3691954965 Apr 23 02:08:01 PM PDT 24 Apr 23 02:19:18 PM PDT 24 145457707604 ps
T807 /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3971238519 Apr 23 02:08:07 PM PDT 24 Apr 23 02:18:44 PM PDT 24 31803953666 ps
T808 /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2912434152 Apr 23 02:09:30 PM PDT 24 Apr 23 02:28:52 PM PDT 24 138827579006 ps
T809 /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3517556305 Apr 23 02:08:14 PM PDT 24 Apr 23 02:30:06 PM PDT 24 227922864618 ps
T810 /workspace/coverage/default/12.edn_genbits.2415845939 Apr 23 02:08:25 PM PDT 24 Apr 23 02:08:27 PM PDT 24 58160975 ps
T811 /workspace/coverage/default/29.edn_genbits.1878346395 Apr 23 02:09:06 PM PDT 24 Apr 23 02:09:08 PM PDT 24 36261227 ps
T812 /workspace/coverage/default/73.edn_err.1532482347 Apr 23 02:10:17 PM PDT 24 Apr 23 02:10:19 PM PDT 24 42527948 ps
T813 /workspace/coverage/default/161.edn_genbits.214627946 Apr 23 02:10:37 PM PDT 24 Apr 23 02:10:40 PM PDT 24 65049240 ps
T814 /workspace/coverage/default/271.edn_genbits.3084375773 Apr 23 02:11:12 PM PDT 24 Apr 23 02:11:16 PM PDT 24 117325690 ps
T815 /workspace/coverage/default/4.edn_alert.1083678394 Apr 23 02:08:06 PM PDT 24 Apr 23 02:08:08 PM PDT 24 87076548 ps
T816 /workspace/coverage/default/44.edn_stress_all.928200829 Apr 23 02:09:39 PM PDT 24 Apr 23 02:09:45 PM PDT 24 453742370 ps
T817 /workspace/coverage/default/17.edn_disable_auto_req_mode.17338829 Apr 23 02:08:36 PM PDT 24 Apr 23 02:08:38 PM PDT 24 110564232 ps
T818 /workspace/coverage/default/45.edn_disable_auto_req_mode.2480889387 Apr 23 02:09:40 PM PDT 24 Apr 23 02:09:42 PM PDT 24 37214418 ps
T819 /workspace/coverage/default/6.edn_smoke.1065871843 Apr 23 02:08:08 PM PDT 24 Apr 23 02:08:09 PM PDT 24 49770179 ps
T820 /workspace/coverage/default/188.edn_genbits.1401167489 Apr 23 02:10:42 PM PDT 24 Apr 23 02:10:44 PM PDT 24 56894617 ps
T821 /workspace/coverage/default/1.edn_intr.1433091432 Apr 23 02:07:57 PM PDT 24 Apr 23 02:07:59 PM PDT 24 30542867 ps
T822 /workspace/coverage/default/33.edn_genbits.1863804919 Apr 23 02:09:15 PM PDT 24 Apr 23 02:09:17 PM PDT 24 219911027 ps
T823 /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3936886802 Apr 23 02:08:52 PM PDT 24 Apr 23 02:24:56 PM PDT 24 128141352809 ps
T824 /workspace/coverage/default/245.edn_genbits.2561144902 Apr 23 02:10:56 PM PDT 24 Apr 23 02:10:58 PM PDT 24 52134779 ps
T825 /workspace/coverage/default/2.edn_alert.2922835475 Apr 23 02:07:59 PM PDT 24 Apr 23 02:08:00 PM PDT 24 34379730 ps
T826 /workspace/coverage/default/74.edn_err.1116299268 Apr 23 02:10:13 PM PDT 24 Apr 23 02:10:14 PM PDT 24 26279253 ps
T827 /workspace/coverage/default/108.edn_genbits.1187328386 Apr 23 02:10:30 PM PDT 24 Apr 23 02:10:34 PM PDT 24 233015168 ps
T828 /workspace/coverage/default/183.edn_genbits.925377955 Apr 23 02:10:42 PM PDT 24 Apr 23 02:10:44 PM PDT 24 49800513 ps
T829 /workspace/coverage/default/37.edn_intr.2582009534 Apr 23 02:09:26 PM PDT 24 Apr 23 02:09:28 PM PDT 24 122823131 ps
T830 /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2897092693 Apr 23 02:09:17 PM PDT 24 Apr 23 02:18:56 PM PDT 24 25633677642 ps
T831 /workspace/coverage/default/41.edn_disable_auto_req_mode.347021414 Apr 23 02:09:34 PM PDT 24 Apr 23 02:09:36 PM PDT 24 150458459 ps
T832 /workspace/coverage/default/270.edn_genbits.2456062310 Apr 23 02:11:04 PM PDT 24 Apr 23 02:11:06 PM PDT 24 60151708 ps
T833 /workspace/coverage/default/78.edn_err.1450587192 Apr 23 02:10:18 PM PDT 24 Apr 23 02:10:19 PM PDT 24 37730602 ps
T834 /workspace/coverage/default/52.edn_err.430742122 Apr 23 02:10:09 PM PDT 24 Apr 23 02:10:10 PM PDT 24 39280858 ps
T835 /workspace/coverage/default/4.edn_disable_auto_req_mode.670344466 Apr 23 02:08:05 PM PDT 24 Apr 23 02:08:06 PM PDT 24 112065028 ps
T836 /workspace/coverage/default/124.edn_genbits.550682567 Apr 23 02:10:34 PM PDT 24 Apr 23 02:10:37 PM PDT 24 35992196 ps
T837 /workspace/coverage/default/282.edn_genbits.2257066144 Apr 23 02:11:03 PM PDT 24 Apr 23 02:11:05 PM PDT 24 33088168 ps
T838 /workspace/coverage/default/55.edn_err.3825293810 Apr 23 02:10:10 PM PDT 24 Apr 23 02:10:12 PM PDT 24 20947234 ps
T170 /workspace/coverage/default/8.edn_disable.371515741 Apr 23 02:08:16 PM PDT 24 Apr 23 02:08:18 PM PDT 24 14572509 ps
T839 /workspace/coverage/default/73.edn_genbits.1806811918 Apr 23 02:10:15 PM PDT 24 Apr 23 02:10:16 PM PDT 24 26801577 ps
T840 /workspace/coverage/default/20.edn_disable.2836820083 Apr 23 02:08:43 PM PDT 24 Apr 23 02:08:44 PM PDT 24 40541202 ps
T841 /workspace/coverage/default/0.edn_intr.1539494294 Apr 23 02:07:51 PM PDT 24 Apr 23 02:07:53 PM PDT 24 71245785 ps
T171 /workspace/coverage/default/12.edn_disable_auto_req_mode.3689386097 Apr 23 02:08:28 PM PDT 24 Apr 23 02:08:30 PM PDT 24 54716907 ps
T172 /workspace/coverage/default/50.edn_err.2529402317 Apr 23 02:10:10 PM PDT 24 Apr 23 02:10:12 PM PDT 24 29846772 ps
T842 /workspace/coverage/default/19.edn_genbits.2549187422 Apr 23 02:08:40 PM PDT 24 Apr 23 02:08:42 PM PDT 24 57825268 ps
T843 /workspace/coverage/cover_reg_top/25.edn_intr_test.3524056203 Apr 23 02:46:40 PM PDT 24 Apr 23 02:46:41 PM PDT 24 20205968 ps
T844 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3088289709 Apr 23 02:46:15 PM PDT 24 Apr 23 02:46:19 PM PDT 24 43855161 ps
T845 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2839219367 Apr 23 02:46:24 PM PDT 24 Apr 23 02:46:26 PM PDT 24 23694894 ps
T246 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.174735934 Apr 23 02:46:10 PM PDT 24 Apr 23 02:46:13 PM PDT 24 401918466 ps
T846 /workspace/coverage/cover_reg_top/11.edn_intr_test.3891822064 Apr 23 02:46:28 PM PDT 24 Apr 23 02:46:29 PM PDT 24 25455632 ps
T847 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3814405877 Apr 23 02:46:19 PM PDT 24 Apr 23 02:46:21 PM PDT 24 65738469 ps
T848 /workspace/coverage/cover_reg_top/46.edn_intr_test.2426833795 Apr 23 02:46:42 PM PDT 24 Apr 23 02:46:44 PM PDT 24 17058429 ps
T849 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.799323587 Apr 23 02:46:35 PM PDT 24 Apr 23 02:46:37 PM PDT 24 39661391 ps
T850 /workspace/coverage/cover_reg_top/18.edn_intr_test.2312469864 Apr 23 02:46:40 PM PDT 24 Apr 23 02:46:41 PM PDT 24 154825952 ps
T851 /workspace/coverage/cover_reg_top/8.edn_intr_test.176592953 Apr 23 02:46:24 PM PDT 24 Apr 23 02:46:25 PM PDT 24 16302419 ps
T852 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2687334603 Apr 23 02:46:36 PM PDT 24 Apr 23 02:46:38 PM PDT 24 74325825 ps
T247 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3922416039 Apr 23 02:46:13 PM PDT 24 Apr 23 02:46:15 PM PDT 24 23998431 ps
T248 /workspace/coverage/cover_reg_top/18.edn_csr_rw.2812844258 Apr 23 02:46:38 PM PDT 24 Apr 23 02:46:40 PM PDT 24 13694709 ps
T853 /workspace/coverage/cover_reg_top/3.edn_intr_test.2113760703 Apr 23 02:46:15 PM PDT 24 Apr 23 02:46:16 PM PDT 24 14177925 ps
T250 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2103113698 Apr 23 02:46:27 PM PDT 24 Apr 23 02:46:30 PM PDT 24 1156019699 ps
T854 /workspace/coverage/cover_reg_top/13.edn_tl_errors.396140054 Apr 23 02:46:29 PM PDT 24 Apr 23 02:46:32 PM PDT 24 55758245 ps
T855 /workspace/coverage/cover_reg_top/6.edn_intr_test.2378819020 Apr 23 02:46:23 PM PDT 24 Apr 23 02:46:24 PM PDT 24 12477854 ps
T251 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1842071102 Apr 23 02:46:29 PM PDT 24 Apr 23 02:46:31 PM PDT 24 38348723 ps
T856 /workspace/coverage/cover_reg_top/20.edn_intr_test.491674740 Apr 23 02:46:42 PM PDT 24 Apr 23 02:46:43 PM PDT 24 49643019 ps
T223 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2294545461 Apr 23 02:46:20 PM PDT 24 Apr 23 02:46:21 PM PDT 24 54274381 ps
T252 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1297013003 Apr 23 02:46:30 PM PDT 24 Apr 23 02:46:32 PM PDT 24 45540655 ps
T857 /workspace/coverage/cover_reg_top/33.edn_intr_test.3568050437 Apr 23 02:46:41 PM PDT 24 Apr 23 02:46:43 PM PDT 24 22567735 ps
T224 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2663990380 Apr 23 02:46:26 PM PDT 24 Apr 23 02:46:28 PM PDT 24 28730009 ps
T249 /workspace/coverage/cover_reg_top/1.edn_csr_rw.671038706 Apr 23 02:46:10 PM PDT 24 Apr 23 02:46:12 PM PDT 24 30951449 ps
T242 /workspace/coverage/cover_reg_top/8.edn_csr_rw.802932781 Apr 23 02:46:24 PM PDT 24 Apr 23 02:46:26 PM PDT 24 45551403 ps
T255 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1424280373 Apr 23 02:46:08 PM PDT 24 Apr 23 02:46:11 PM PDT 24 75406781 ps
T858 /workspace/coverage/cover_reg_top/23.edn_intr_test.3580731873 Apr 23 02:46:45 PM PDT 24 Apr 23 02:46:46 PM PDT 24 29779059 ps
T225 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.93730963 Apr 23 02:46:17 PM PDT 24 Apr 23 02:46:19 PM PDT 24 39319162 ps
T226 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.809518881 Apr 23 02:46:36 PM PDT 24 Apr 23 02:46:38 PM PDT 24 30366635 ps
T859 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.4176124620 Apr 23 02:46:22 PM PDT 24 Apr 23 02:46:25 PM PDT 24 68960279 ps
T227 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3996884218 Apr 23 02:46:34 PM PDT 24 Apr 23 02:46:35 PM PDT 24 39973899 ps
T228 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3594147817 Apr 23 02:46:09 PM PDT 24 Apr 23 02:46:11 PM PDT 24 17521346 ps
T860 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2605834485 Apr 23 02:46:12 PM PDT 24 Apr 23 02:46:14 PM PDT 24 22979065 ps
T229 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3323364528 Apr 23 02:46:21 PM PDT 24 Apr 23 02:46:23 PM PDT 24 57894047 ps
T243 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3174391209 Apr 23 02:46:20 PM PDT 24 Apr 23 02:46:22 PM PDT 24 12209987 ps
T861 /workspace/coverage/cover_reg_top/2.edn_intr_test.1745587223 Apr 23 02:46:12 PM PDT 24 Apr 23 02:46:13 PM PDT 24 27392958 ps
T862 /workspace/coverage/cover_reg_top/34.edn_intr_test.1013990701 Apr 23 02:46:40 PM PDT 24 Apr 23 02:46:41 PM PDT 24 182856350 ps
T863 /workspace/coverage/cover_reg_top/16.edn_tl_errors.671096812 Apr 23 02:46:35 PM PDT 24 Apr 23 02:46:39 PM PDT 24 337702346 ps
T864 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3108323448 Apr 23 02:46:30 PM PDT 24 Apr 23 02:46:32 PM PDT 24 17313303 ps
T865 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2995432904 Apr 23 02:46:21 PM PDT 24 Apr 23 02:46:23 PM PDT 24 21729365 ps
T230 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.780864108 Apr 23 02:46:27 PM PDT 24 Apr 23 02:46:29 PM PDT 24 64857179 ps
T231 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2813824198 Apr 23 02:46:19 PM PDT 24 Apr 23 02:46:22 PM PDT 24 58143300 ps
T866 /workspace/coverage/cover_reg_top/1.edn_intr_test.926946062 Apr 23 02:46:12 PM PDT 24 Apr 23 02:46:13 PM PDT 24 44393680 ps
T867 /workspace/coverage/cover_reg_top/4.edn_intr_test.4073787839 Apr 23 02:46:17 PM PDT 24 Apr 23 02:46:18 PM PDT 24 23292897 ps
T868 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.472726177 Apr 23 02:46:24 PM PDT 24 Apr 23 02:46:27 PM PDT 24 304060081 ps
T232 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2880213783 Apr 23 02:46:12 PM PDT 24 Apr 23 02:46:14 PM PDT 24 90914386 ps
T869 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2492371964 Apr 23 02:46:34 PM PDT 24 Apr 23 02:46:36 PM PDT 24 25637419 ps
T244 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2343720170 Apr 23 02:46:19 PM PDT 24 Apr 23 02:46:21 PM PDT 24 46398643 ps
T870 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.669301485 Apr 23 02:46:33 PM PDT 24 Apr 23 02:46:34 PM PDT 24 126141429 ps
T871 /workspace/coverage/cover_reg_top/24.edn_intr_test.765085512 Apr 23 02:46:38 PM PDT 24 Apr 23 02:46:40 PM PDT 24 16392868 ps
T872 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2476550566 Apr 23 02:46:16 PM PDT 24 Apr 23 02:46:19 PM PDT 24 62806819 ps
T245 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.505906930 Apr 23 02:46:37 PM PDT 24 Apr 23 02:46:38 PM PDT 24 15446612 ps
T873 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1477051349 Apr 23 02:46:37 PM PDT 24 Apr 23 02:46:38 PM PDT 24 55836590 ps
T874 /workspace/coverage/cover_reg_top/9.edn_intr_test.2932344006 Apr 23 02:46:24 PM PDT 24 Apr 23 02:46:25 PM PDT 24 24173310 ps
T875 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2378023537 Apr 23 02:46:27 PM PDT 24 Apr 23 02:46:29 PM PDT 24 75845858 ps
T876 /workspace/coverage/cover_reg_top/30.edn_intr_test.1881289930 Apr 23 02:46:40 PM PDT 24 Apr 23 02:46:41 PM PDT 24 27068333 ps
T233 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1476084436 Apr 23 02:46:26 PM PDT 24 Apr 23 02:46:27 PM PDT 24 37144902 ps
T877 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2147285506 Apr 23 02:46:22 PM PDT 24 Apr 23 02:46:24 PM PDT 24 226688454 ps
T878 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2373282576 Apr 23 02:46:13 PM PDT 24 Apr 23 02:46:15 PM PDT 24 161683030 ps
T879 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2687554482 Apr 23 02:46:24 PM PDT 24 Apr 23 02:46:27 PM PDT 24 41402710 ps
T234 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2465449103 Apr 23 02:46:33 PM PDT 24 Apr 23 02:46:35 PM PDT 24 31791605 ps
T256 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2433469984 Apr 23 02:46:38 PM PDT 24 Apr 23 02:46:41 PM PDT 24 229087399 ps
T880 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.246206969 Apr 23 02:46:34 PM PDT 24 Apr 23 02:46:36 PM PDT 24 88219453 ps
T881 /workspace/coverage/cover_reg_top/48.edn_intr_test.1337754091 Apr 23 02:46:44 PM PDT 24 Apr 23 02:46:45 PM PDT 24 16750864 ps
T882 /workspace/coverage/cover_reg_top/43.edn_intr_test.2926233039 Apr 23 02:46:43 PM PDT 24 Apr 23 02:46:45 PM PDT 24 21181738 ps
T883 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1163616227 Apr 23 02:46:27 PM PDT 24 Apr 23 02:46:30 PM PDT 24 160042983 ps
T884 /workspace/coverage/cover_reg_top/16.edn_intr_test.220687293 Apr 23 02:46:35 PM PDT 24 Apr 23 02:46:36 PM PDT 24 13276424 ps
T885 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3312910504 Apr 23 02:46:37 PM PDT 24 Apr 23 02:46:41 PM PDT 24 205704855 ps
T886 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3016594276 Apr 23 02:46:08 PM PDT 24 Apr 23 02:46:10 PM PDT 24 41230188 ps
T887 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1991790647 Apr 23 02:46:24 PM PDT 24 Apr 23 02:46:28 PM PDT 24 539104344 ps
T888 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1802531455 Apr 23 02:46:27 PM PDT 24 Apr 23 02:46:28 PM PDT 24 14313675 ps
T889 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3836270668 Apr 23 02:46:20 PM PDT 24 Apr 23 02:46:22 PM PDT 24 93008366 ps
T890 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1240453474 Apr 23 02:46:12 PM PDT 24 Apr 23 02:46:15 PM PDT 24 36673712 ps
T891 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2450709208 Apr 23 02:46:34 PM PDT 24 Apr 23 02:46:36 PM PDT 24 26514179 ps
T892 /workspace/coverage/cover_reg_top/12.edn_tl_errors.4197405298 Apr 23 02:46:29 PM PDT 24 Apr 23 02:46:32 PM PDT 24 262040008 ps
T893 /workspace/coverage/cover_reg_top/45.edn_intr_test.1397672254 Apr 23 02:46:49 PM PDT 24 Apr 23 02:46:51 PM PDT 24 14190792 ps
T894 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2243791939 Apr 23 02:46:40 PM PDT 24 Apr 23 02:46:44 PM PDT 24 673589555 ps
T895 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1190817860 Apr 23 02:46:11 PM PDT 24 Apr 23 02:46:13 PM PDT 24 57771069 ps
T896 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3034206591 Apr 23 02:46:31 PM PDT 24 Apr 23 02:46:33 PM PDT 24 26284191 ps
T897 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4202880227 Apr 23 02:46:29 PM PDT 24 Apr 23 02:46:31 PM PDT 24 66946908 ps
T898 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3224440163 Apr 23 02:46:37 PM PDT 24 Apr 23 02:46:44 PM PDT 24 350106074 ps
T899 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2077409871 Apr 23 02:46:28 PM PDT 24 Apr 23 02:46:31 PM PDT 24 101623035 ps
T900 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2243733891 Apr 23 02:46:37 PM PDT 24 Apr 23 02:46:42 PM PDT 24 1582275637 ps
T901 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3658117632 Apr 23 02:46:13 PM PDT 24 Apr 23 02:46:15 PM PDT 24 58895277 ps
T902 /workspace/coverage/cover_reg_top/17.edn_intr_test.2017990114 Apr 23 02:46:37 PM PDT 24 Apr 23 02:46:39 PM PDT 24 13007796 ps
T903 /workspace/coverage/cover_reg_top/32.edn_intr_test.3200920671 Apr 23 02:46:45 PM PDT 24 Apr 23 02:46:47 PM PDT 24 61327946 ps
T904 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2054767149 Apr 23 02:46:34 PM PDT 24 Apr 23 02:46:36 PM PDT 24 60249960 ps
T905 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1030846377 Apr 23 02:46:16 PM PDT 24 Apr 23 02:46:18 PM PDT 24 74515048 ps
T235 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2498717230 Apr 23 02:46:28 PM PDT 24 Apr 23 02:46:30 PM PDT 24 12188954 ps
T906 /workspace/coverage/cover_reg_top/26.edn_intr_test.4187173148 Apr 23 02:46:41 PM PDT 24 Apr 23 02:46:42 PM PDT 24 12160177 ps
T907 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3220836300 Apr 23 02:46:12 PM PDT 24 Apr 23 02:46:14 PM PDT 24 24083818 ps
T908 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1785386750 Apr 23 02:46:25 PM PDT 24 Apr 23 02:46:27 PM PDT 24 56054598 ps
T909 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1082415243 Apr 23 02:46:11 PM PDT 24 Apr 23 02:46:14 PM PDT 24 192440064 ps
T910 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.4280001605 Apr 23 02:46:19 PM PDT 24 Apr 23 02:46:21 PM PDT 24 140693355 ps
T911 /workspace/coverage/cover_reg_top/0.edn_intr_test.530395463 Apr 23 02:46:10 PM PDT 24 Apr 23 02:46:11 PM PDT 24 39339888 ps
T912 /workspace/coverage/cover_reg_top/41.edn_intr_test.3991258753 Apr 23 02:46:44 PM PDT 24 Apr 23 02:46:45 PM PDT 24 136193158 ps
T913 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1289186412 Apr 23 02:46:40 PM PDT 24 Apr 23 02:46:42 PM PDT 24 167326702 ps
T914 /workspace/coverage/cover_reg_top/39.edn_intr_test.2569718472 Apr 23 02:46:40 PM PDT 24 Apr 23 02:46:42 PM PDT 24 51974057 ps
T915 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3667162368 Apr 23 02:46:30 PM PDT 24 Apr 23 02:46:32 PM PDT 24 24859225 ps
T236 /workspace/coverage/cover_reg_top/0.edn_csr_rw.4271186080 Apr 23 02:46:09 PM PDT 24 Apr 23 02:46:11 PM PDT 24 61292381 ps
T916 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2489243630 Apr 23 02:46:27 PM PDT 24 Apr 23 02:46:29 PM PDT 24 143344359 ps
T917 /workspace/coverage/cover_reg_top/29.edn_intr_test.1628402848 Apr 23 02:46:41 PM PDT 24 Apr 23 02:46:42 PM PDT 24 24074358 ps
T918 /workspace/coverage/cover_reg_top/14.edn_intr_test.2477814960 Apr 23 02:46:30 PM PDT 24 Apr 23 02:46:32 PM PDT 24 14309241 ps
T919 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3105585886 Apr 23 02:46:24 PM PDT 24 Apr 23 02:46:26 PM PDT 24 106250991 ps
T920 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4164379682 Apr 23 02:46:26 PM PDT 24 Apr 23 02:46:27 PM PDT 24 20347867 ps
T921 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1810381786 Apr 23 02:46:29 PM PDT 24 Apr 23 02:46:33 PM PDT 24 820145755 ps
T922 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3725118168 Apr 23 02:46:29 PM PDT 24 Apr 23 02:46:31 PM PDT 24 21748843 ps
T923 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1525733334 Apr 23 02:46:31 PM PDT 24 Apr 23 02:46:34 PM PDT 24 70137492 ps
T924 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.100345780 Apr 23 02:46:14 PM PDT 24 Apr 23 02:46:16 PM PDT 24 25720661 ps
T237 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1774006993 Apr 23 02:46:11 PM PDT 24 Apr 23 02:46:13 PM PDT 24 15019281 ps
T925 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.733551141 Apr 23 02:46:17 PM PDT 24 Apr 23 02:46:19 PM PDT 24 18879531 ps
T926 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1533859608 Apr 23 02:46:36 PM PDT 24 Apr 23 02:46:38 PM PDT 24 14468447 ps
T927 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.774702844 Apr 23 02:46:38 PM PDT 24 Apr 23 02:46:39 PM PDT 24 45708911 ps
T928 /workspace/coverage/cover_reg_top/13.edn_intr_test.3421536540 Apr 23 02:46:30 PM PDT 24 Apr 23 02:46:32 PM PDT 24 13676551 ps
T929 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3106929972 Apr 23 02:46:30 PM PDT 24 Apr 23 02:46:32 PM PDT 24 79516176 ps
T930 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1503972499 Apr 23 02:46:13 PM PDT 24 Apr 23 02:46:15 PM PDT 24 39567250 ps
T931 /workspace/coverage/cover_reg_top/21.edn_intr_test.2528739336 Apr 23 02:46:42 PM PDT 24 Apr 23 02:46:44 PM PDT 24 16646669 ps
T238 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.884404548 Apr 23 02:46:16 PM PDT 24 Apr 23 02:46:18 PM PDT 24 55302488 ps
T932 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3752565452 Apr 23 02:46:28 PM PDT 24 Apr 23 02:46:30 PM PDT 24 34453265 ps
T933 /workspace/coverage/cover_reg_top/44.edn_intr_test.2042506665 Apr 23 02:46:42 PM PDT 24 Apr 23 02:46:44 PM PDT 24 31133357 ps
T934 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3110487960 Apr 23 02:46:23 PM PDT 24 Apr 23 02:46:25 PM PDT 24 97638833 ps
T935 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.738996172 Apr 23 02:46:32 PM PDT 24 Apr 23 02:46:34 PM PDT 24 74601979 ps
T936 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2235741012 Apr 23 02:46:14 PM PDT 24 Apr 23 02:46:20 PM PDT 24 353325263 ps
T239 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2717913704 Apr 23 02:46:12 PM PDT 24 Apr 23 02:46:16 PM PDT 24 228626016 ps
T937 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3216560520 Apr 23 02:46:08 PM PDT 24 Apr 23 02:46:11 PM PDT 24 62447417 ps
T938 /workspace/coverage/cover_reg_top/3.edn_csr_rw.185770041 Apr 23 02:46:15 PM PDT 24 Apr 23 02:46:16 PM PDT 24 16939827 ps
T939 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.763717607 Apr 23 02:46:22 PM PDT 24 Apr 23 02:46:25 PM PDT 24 196350836 ps
T240 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3981722780 Apr 23 02:46:08 PM PDT 24 Apr 23 02:46:10 PM PDT 24 51052012 ps
T940 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1419764978 Apr 23 02:46:31 PM PDT 24 Apr 23 02:46:37 PM PDT 24 499727898 ps
T941 /workspace/coverage/cover_reg_top/15.edn_tl_errors.398591640 Apr 23 02:46:33 PM PDT 24 Apr 23 02:46:37 PM PDT 24 41388330 ps
T942 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1369499757 Apr 23 02:46:18 PM PDT 24 Apr 23 02:46:20 PM PDT 24 34532482 ps
T943 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4282360814 Apr 23 02:46:24 PM PDT 24 Apr 23 02:46:27 PM PDT 24 142980059 ps
T944 /workspace/coverage/cover_reg_top/40.edn_intr_test.114004602 Apr 23 02:46:45 PM PDT 24 Apr 23 02:46:46 PM PDT 24 31427948 ps
T241 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2755725777 Apr 23 02:46:19 PM PDT 24 Apr 23 02:46:20 PM PDT 24 51859767 ps
T945 /workspace/coverage/cover_reg_top/36.edn_intr_test.4246476827 Apr 23 02:46:45 PM PDT 24 Apr 23 02:46:46 PM PDT 24 22557993 ps
T946 /workspace/coverage/cover_reg_top/37.edn_intr_test.2912513013 Apr 23 02:46:45 PM PDT 24 Apr 23 02:46:47 PM PDT 24 27312429 ps
T947 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3726885630 Apr 23 02:46:22 PM PDT 24 Apr 23 02:46:25 PM PDT 24 85953267 ps
T948 /workspace/coverage/cover_reg_top/42.edn_intr_test.846599878 Apr 23 02:46:44 PM PDT 24 Apr 23 02:46:46 PM PDT 24 43233979 ps
T949 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.972908971 Apr 23 02:46:29 PM PDT 24 Apr 23 02:46:31 PM PDT 24 22718703 ps
T950 /workspace/coverage/cover_reg_top/38.edn_intr_test.4134691058 Apr 23 02:46:41 PM PDT 24 Apr 23 02:46:42 PM PDT 24 37397604 ps
T951 /workspace/coverage/cover_reg_top/10.edn_intr_test.3721277375 Apr 23 02:46:29 PM PDT 24 Apr 23 02:46:31 PM PDT 24 29404192 ps
T952 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1554684106 Apr 23 02:46:24 PM PDT 24 Apr 23 02:46:26 PM PDT 24 31670120 ps
T953 /workspace/coverage/cover_reg_top/12.edn_intr_test.3174789102 Apr 23 02:46:31 PM PDT 24 Apr 23 02:46:33 PM PDT 24 27835359 ps
T954 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.15525934 Apr 23 02:46:33 PM PDT 24 Apr 23 02:46:35 PM PDT 24 88564588 ps
T955 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.4123755328 Apr 23 02:46:31 PM PDT 24 Apr 23 02:46:33 PM PDT 24 95028147 ps
T956 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1024298906 Apr 23 02:46:24 PM PDT 24 Apr 23 02:46:26 PM PDT 24 39002469 ps
T957 /workspace/coverage/cover_reg_top/47.edn_intr_test.3831083799 Apr 23 02:46:48 PM PDT 24 Apr 23 02:46:49 PM PDT 24 12157332 ps
T958 /workspace/coverage/cover_reg_top/22.edn_intr_test.3804371648 Apr 23 02:46:41 PM PDT 24 Apr 23 02:46:43 PM PDT 24 32637202 ps
T959 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2379163410 Apr 23 02:46:34 PM PDT 24 Apr 23 02:46:36 PM PDT 24 60330941 ps
T960 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.248863489 Apr 23 02:46:16 PM PDT 24 Apr 23 02:46:18 PM PDT 24 17805031 ps
T961 /workspace/coverage/cover_reg_top/31.edn_intr_test.1416372147 Apr 23 02:46:40 PM PDT 24 Apr 23 02:46:41 PM PDT 24 36974134 ps
T962 /workspace/coverage/cover_reg_top/27.edn_intr_test.4162839538 Apr 23 02:46:41 PM PDT 24 Apr 23 02:46:43 PM PDT 24 34501065 ps
T963 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3500437616 Apr 23 02:46:36 PM PDT 24 Apr 23 02:46:38 PM PDT 24 17733730 ps
T964 /workspace/coverage/cover_reg_top/7.edn_intr_test.2517758330 Apr 23 02:46:20 PM PDT 24 Apr 23 02:46:22 PM PDT 24 12236022 ps
T965 /workspace/coverage/cover_reg_top/15.edn_intr_test.3446866352 Apr 23 02:46:34 PM PDT 24 Apr 23 02:46:36 PM PDT 24 34369286 ps
T966 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1351650187 Apr 23 02:46:12 PM PDT 24 Apr 23 02:46:14 PM PDT 24 20753277 ps
T967 /workspace/coverage/cover_reg_top/5.edn_intr_test.1343225701 Apr 23 02:46:24 PM PDT 24 Apr 23 02:46:25 PM PDT 24 109974565 ps
T968 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2029453436 Apr 23 02:46:19 PM PDT 24 Apr 23 02:46:22 PM PDT 24 73579663 ps
T969 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3626755086 Apr 23 02:46:25 PM PDT 24 Apr 23 02:46:27 PM PDT 24 24789464 ps
T970 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1472413604 Apr 23 02:46:23 PM PDT 24 Apr 23 02:46:25 PM PDT 24 63496713 ps
T971 /workspace/coverage/cover_reg_top/49.edn_intr_test.2279691437 Apr 23 02:46:46 PM PDT 24 Apr 23 02:46:47 PM PDT 24 57645269 ps
T972 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2763229802 Apr 23 02:46:39 PM PDT 24 Apr 23 02:46:40 PM PDT 24 16179337 ps
T973 /workspace/coverage/cover_reg_top/19.edn_intr_test.4290132221 Apr 23 02:46:39 PM PDT 24 Apr 23 02:46:40 PM PDT 24 70593116 ps
T974 /workspace/coverage/cover_reg_top/35.edn_intr_test.3432995150 Apr 23 02:46:39 PM PDT 24 Apr 23 02:46:40 PM PDT 24 32719321 ps
T975 /workspace/coverage/cover_reg_top/28.edn_intr_test.343720683 Apr 23 02:46:39 PM PDT 24 Apr 23 02:46:40 PM PDT 24 29627770 ps

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3739609645
Short name T4
Test name
Test status
Simulation time 177704420530 ps
CPU time 1039.28 seconds
Started Apr 23 02:08:59 PM PDT 24
Finished Apr 23 02:26:19 PM PDT 24
Peak memory 223820 kb
Host smart-a142e143-3bec-4aac-a963-674e845b9a3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739609645 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3739609645
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/281.edn_genbits.3089386284
Short name T10
Test name
Test status
Simulation time 54141333 ps
CPU time 1.66 seconds
Started Apr 23 02:11:03 PM PDT 24
Finished Apr 23 02:11:06 PM PDT 24
Peak memory 219548 kb
Host smart-e9a50e07-d2d0-44ee-9660-0c54230186bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089386284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3089386284
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_sec_cm.591566393
Short name T15
Test name
Test status
Simulation time 1238104321 ps
CPU time 9.43 seconds
Started Apr 23 02:07:59 PM PDT 24
Finished Apr 23 02:08:09 PM PDT 24
Peak memory 236512 kb
Host smart-fd440515-54ce-4aac-a9ce-33b6f82ab1fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591566393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.591566393
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/14.edn_alert.2009494440
Short name T28
Test name
Test status
Simulation time 92364779 ps
CPU time 1.22 seconds
Started Apr 23 02:08:32 PM PDT 24
Finished Apr 23 02:08:34 PM PDT 24
Peak memory 215856 kb
Host smart-e3ef694f-88a4-4ffb-b47c-d859aa8cc5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009494440 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2009494440
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/90.edn_genbits.1626989872
Short name T1
Test name
Test status
Simulation time 49777238 ps
CPU time 1.31 seconds
Started Apr 23 02:10:29 PM PDT 24
Finished Apr 23 02:10:31 PM PDT 24
Peak memory 218532 kb
Host smart-3a57d2c0-d2df-452f-a3fa-09e7f47c5e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626989872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1626989872
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_disable.2511646845
Short name T63
Test name
Test status
Simulation time 12573079 ps
CPU time 0.85 seconds
Started Apr 23 02:09:12 PM PDT 24
Finished Apr 23 02:09:13 PM PDT 24
Peak memory 216500 kb
Host smart-ab63230e-1318-499b-9293-7e0990d5ee56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511646845 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2511646845
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/23.edn_alert.2369111812
Short name T132
Test name
Test status
Simulation time 31634774 ps
CPU time 1.33 seconds
Started Apr 23 02:08:54 PM PDT 24
Finished Apr 23 02:08:56 PM PDT 24
Peak memory 216004 kb
Host smart-a048ad16-c900-4c3a-b3a1-a310fda7514b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369111812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2369111812
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.4089644377
Short name T72
Test name
Test status
Simulation time 49222328 ps
CPU time 1.15 seconds
Started Apr 23 02:09:09 PM PDT 24
Finished Apr 23 02:09:10 PM PDT 24
Peak memory 217248 kb
Host smart-cdbd3b71-9546-45a0-b343-b262edbe42cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089644377 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.4089644377
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_regwen.1537894411
Short name T23
Test name
Test status
Simulation time 17491036 ps
CPU time 0.98 seconds
Started Apr 23 02:07:51 PM PDT 24
Finished Apr 23 02:07:52 PM PDT 24
Peak memory 207380 kb
Host smart-199d6e98-1cb8-41fe-b5e9-7632f4959280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537894411 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1537894411
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_alert.2878494946
Short name T412
Test name
Test status
Simulation time 46672281 ps
CPU time 1.13 seconds
Started Apr 23 02:08:19 PM PDT 24
Finished Apr 23 02:08:21 PM PDT 24
Peak memory 215964 kb
Host smart-cd5a6696-0912-41d4-bf60-91899b16d9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878494946 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2878494946
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3333268776
Short name T195
Test name
Test status
Simulation time 97530245764 ps
CPU time 1250.52 seconds
Started Apr 23 02:09:14 PM PDT 24
Finished Apr 23 02:30:05 PM PDT 24
Peak memory 223624 kb
Host smart-25816b7c-d583-469b-863d-71379ca342d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333268776 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3333268776
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1424280373
Short name T255
Test name
Test status
Simulation time 75406781 ps
CPU time 2.09 seconds
Started Apr 23 02:46:08 PM PDT 24
Finished Apr 23 02:46:11 PM PDT 24
Peak memory 206600 kb
Host smart-04c19be7-9a41-4632-8ecc-08fddaa4186a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424280373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1424280373
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/46.edn_err.3702104567
Short name T5
Test name
Test status
Simulation time 30746092 ps
CPU time 1.09 seconds
Started Apr 23 02:09:45 PM PDT 24
Finished Apr 23 02:09:46 PM PDT 24
Peak memory 219924 kb
Host smart-4880cde3-e02e-4e5c-8e12-bced9eab59a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702104567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3702104567
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/11.edn_alert.2050379822
Short name T128
Test name
Test status
Simulation time 77907342 ps
CPU time 1.26 seconds
Started Apr 23 02:08:29 PM PDT 24
Finished Apr 23 02:08:31 PM PDT 24
Peak memory 215960 kb
Host smart-7d5cf50e-b956-4dcc-a833-d78a13e64478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050379822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2050379822
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.93730963
Short name T225
Test name
Test status
Simulation time 39319162 ps
CPU time 0.83 seconds
Started Apr 23 02:46:17 PM PDT 24
Finished Apr 23 02:46:19 PM PDT 24
Peak memory 206460 kb
Host smart-74dacbff-828c-44a2-8084-771d819fd591
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93730963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.93730963
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3613151206
Short name T95
Test name
Test status
Simulation time 85965580 ps
CPU time 1.05 seconds
Started Apr 23 02:08:24 PM PDT 24
Finished Apr 23 02:08:26 PM PDT 24
Peak memory 217236 kb
Host smart-15017182-558d-433f-a2d9-ad69902ea35c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613151206 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3613151206
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_disable.1460853953
Short name T81
Test name
Test status
Simulation time 14579848 ps
CPU time 0.94 seconds
Started Apr 23 02:08:47 PM PDT 24
Finished Apr 23 02:08:48 PM PDT 24
Peak memory 216768 kb
Host smart-e7252709-6905-48ec-a1b0-b343469d4124
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460853953 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1460853953
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/191.edn_genbits.2815743165
Short name T44
Test name
Test status
Simulation time 105896572 ps
CPU time 1.43 seconds
Started Apr 23 02:10:44 PM PDT 24
Finished Apr 23 02:10:46 PM PDT 24
Peak memory 217320 kb
Host smart-c1a8913b-983b-4a16-a06d-4ae93b7790fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815743165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2815743165
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_disable.1205996634
Short name T167
Test name
Test status
Simulation time 30218238 ps
CPU time 0.84 seconds
Started Apr 23 02:08:31 PM PDT 24
Finished Apr 23 02:08:32 PM PDT 24
Peak memory 216612 kb
Host smart-a8dc72a2-f73b-46e7-9075-9a7032d21fd6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205996634 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1205996634
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable.1284010345
Short name T148
Test name
Test status
Simulation time 13506716 ps
CPU time 0.88 seconds
Started Apr 23 02:09:06 PM PDT 24
Finished Apr 23 02:09:07 PM PDT 24
Peak memory 216924 kb
Host smart-9a8d768a-4d0c-45a4-aa08-675351bd6124
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284010345 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1284010345
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable.77863299
Short name T139
Test name
Test status
Simulation time 20624209 ps
CPU time 0.82 seconds
Started Apr 23 02:09:13 PM PDT 24
Finished Apr 23 02:09:14 PM PDT 24
Peak memory 216460 kb
Host smart-4ba3e6b3-9ab7-4ba5-8683-822f97768a02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77863299 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.77863299
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3262426066
Short name T153
Test name
Test status
Simulation time 195194665146 ps
CPU time 1168.6 seconds
Started Apr 23 02:09:45 PM PDT 24
Finished Apr 23 02:29:14 PM PDT 24
Peak memory 221928 kb
Host smart-8795ab49-dcd3-4ee9-a08b-06bdc6fd0cb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262426066 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3262426066
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.163187397
Short name T115
Test name
Test status
Simulation time 94275573 ps
CPU time 1.25 seconds
Started Apr 23 02:07:53 PM PDT 24
Finished Apr 23 02:07:55 PM PDT 24
Peak memory 218404 kb
Host smart-5db6df61-7655-45a1-b4cb-8247b492b53d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163187397 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.163187397
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_intr.3779069695
Short name T88
Test name
Test status
Simulation time 65455056 ps
CPU time 0.9 seconds
Started Apr 23 02:08:58 PM PDT 24
Finished Apr 23 02:09:00 PM PDT 24
Peak memory 215768 kb
Host smart-a45e3c72-9cdf-4e41-808d-d964cf5b7f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779069695 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3779069695
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.4149300984
Short name T66
Test name
Test status
Simulation time 60429621 ps
CPU time 1.27 seconds
Started Apr 23 02:09:03 PM PDT 24
Finished Apr 23 02:09:04 PM PDT 24
Peak memory 218368 kb
Host smart-d6a93224-090c-4240-bbbe-58f640c2eaa5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149300984 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.4149300984
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_alert.1557850576
Short name T191
Test name
Test status
Simulation time 31781329 ps
CPU time 1.3 seconds
Started Apr 23 02:07:52 PM PDT 24
Finished Apr 23 02:07:54 PM PDT 24
Peak memory 215948 kb
Host smart-25a75618-271c-44d9-8017-c7f6b3746715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557850576 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1557850576
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable.3602014373
Short name T69
Test name
Test status
Simulation time 11854118 ps
CPU time 0.88 seconds
Started Apr 23 02:07:57 PM PDT 24
Finished Apr 23 02:07:59 PM PDT 24
Peak memory 215236 kb
Host smart-68a4e75e-aa4a-4bf7-bfd4-5b3f1afed297
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602014373 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3602014373
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/131.edn_genbits.2570970192
Short name T272
Test name
Test status
Simulation time 39147768 ps
CPU time 1.6 seconds
Started Apr 23 02:10:34 PM PDT 24
Finished Apr 23 02:10:37 PM PDT 24
Peak memory 218372 kb
Host smart-7fbf0f7c-0d49-4a5c-8fa9-350b9596ff3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570970192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2570970192
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_genbits.2032858017
Short name T273
Test name
Test status
Simulation time 53852424 ps
CPU time 1.57 seconds
Started Apr 23 02:08:53 PM PDT 24
Finished Apr 23 02:08:55 PM PDT 24
Peak memory 218444 kb
Host smart-cc46931e-d4f6-405c-b277-e3c1a57d254b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032858017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2032858017
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_regwen.1886070204
Short name T265
Test name
Test status
Simulation time 24345079 ps
CPU time 0.93 seconds
Started Apr 23 02:08:17 PM PDT 24
Finished Apr 23 02:08:19 PM PDT 24
Peak memory 207344 kb
Host smart-5b8d54b8-87d4-4cbe-b348-bffb6b3cff3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886070204 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1886070204
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_disable.371515741
Short name T170
Test name
Test status
Simulation time 14572509 ps
CPU time 0.93 seconds
Started Apr 23 02:08:16 PM PDT 24
Finished Apr 23 02:08:18 PM PDT 24
Peak memory 216748 kb
Host smart-191aec30-e594-4153-81f3-e9c1069b402b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371515741 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.371515741
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/12.edn_intr.4119788857
Short name T706
Test name
Test status
Simulation time 27565912 ps
CPU time 0.88 seconds
Started Apr 23 02:08:29 PM PDT 24
Finished Apr 23 02:08:30 PM PDT 24
Peak memory 215772 kb
Host smart-e5e0aac2-ce24-4bc3-b62a-6444a2dafdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119788857 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.4119788857
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/16.edn_disable.2549797412
Short name T173
Test name
Test status
Simulation time 21242749 ps
CPU time 0.88 seconds
Started Apr 23 02:08:40 PM PDT 24
Finished Apr 23 02:08:42 PM PDT 24
Peak memory 216472 kb
Host smart-f5ef746f-db33-4c0b-8502-f8335bafd7cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549797412 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2549797412
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.17338829
Short name T817
Test name
Test status
Simulation time 110564232 ps
CPU time 1.19 seconds
Started Apr 23 02:08:36 PM PDT 24
Finished Apr 23 02:08:38 PM PDT 24
Peak memory 217112 kb
Host smart-2b4f5185-15c3-4e4b-8007-97aee02ff13d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17338829 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_dis
able_auto_req_mode.17338829
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_disable.3599497966
Short name T176
Test name
Test status
Simulation time 13901161 ps
CPU time 0.9 seconds
Started Apr 23 02:08:59 PM PDT 24
Finished Apr 23 02:09:01 PM PDT 24
Peak memory 216548 kb
Host smart-8474b1c7-eba9-4f81-8c55-51af6a4851e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599497966 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3599497966
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.97525053
Short name T96
Test name
Test status
Simulation time 277942259 ps
CPU time 1.19 seconds
Started Apr 23 02:09:23 PM PDT 24
Finished Apr 23 02:09:25 PM PDT 24
Peak memory 217180 kb
Host smart-486e6cd5-444e-494a-9283-587aec10f40f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97525053 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_dis
able_auto_req_mode.97525053
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_stress_all.2528047265
Short name T274
Test name
Test status
Simulation time 772486586 ps
CPU time 3.66 seconds
Started Apr 23 02:08:43 PM PDT 24
Finished Apr 23 02:08:47 PM PDT 24
Peak memory 215632 kb
Host smart-f185cd18-b0af-426f-a863-6124627c1f92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528047265 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2528047265
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_alert_test.844730185
Short name T21
Test name
Test status
Simulation time 100720055 ps
CPU time 0.85 seconds
Started Apr 23 02:08:00 PM PDT 24
Finished Apr 23 02:08:01 PM PDT 24
Peak memory 206896 kb
Host smart-07769406-284c-451f-9716-1e678eb88e23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844730185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.844730185
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/112.edn_genbits.2375073585
Short name T302
Test name
Test status
Simulation time 35554396 ps
CPU time 1.4 seconds
Started Apr 23 02:10:30 PM PDT 24
Finished Apr 23 02:10:32 PM PDT 24
Peak memory 219824 kb
Host smart-fae9a70b-aa1c-4515-8675-ea9520fb34c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375073585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2375073585
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.2206267384
Short name T263
Test name
Test status
Simulation time 46807775 ps
CPU time 0.97 seconds
Started Apr 23 02:07:57 PM PDT 24
Finished Apr 23 02:07:59 PM PDT 24
Peak memory 207304 kb
Host smart-e3b8c99c-2640-4f3e-b13a-82a50d598768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206267384 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2206267384
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_regwen.2434572836
Short name T266
Test name
Test status
Simulation time 82920390 ps
CPU time 0.95 seconds
Started Apr 23 02:08:10 PM PDT 24
Finished Apr 23 02:08:11 PM PDT 24
Peak memory 207304 kb
Host smart-8748dee4-89e7-4fc7-b945-2547eabbc53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434572836 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2434572836
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/19.edn_intr.3063519394
Short name T787
Test name
Test status
Simulation time 33742057 ps
CPU time 0.85 seconds
Started Apr 23 02:08:42 PM PDT 24
Finished Apr 23 02:08:43 PM PDT 24
Peak memory 215868 kb
Host smart-576feac0-cde6-4d7e-bc9a-80d4b89a3d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063519394 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3063519394
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/171.edn_genbits.1799687429
Short name T289
Test name
Test status
Simulation time 33848670 ps
CPU time 1.4 seconds
Started Apr 23 02:10:38 PM PDT 24
Finished Apr 23 02:10:41 PM PDT 24
Peak memory 219752 kb
Host smart-53c0825a-2b0a-4333-830b-141ebadff5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799687429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1799687429
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_genbits.1768818530
Short name T293
Test name
Test status
Simulation time 65831348 ps
CPU time 1.33 seconds
Started Apr 23 02:08:54 PM PDT 24
Finished Apr 23 02:08:56 PM PDT 24
Peak memory 220136 kb
Host smart-43fd956e-0515-4f2a-a541-758b7f1493ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768818530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1768818530
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2717913704
Short name T239
Test name
Test status
Simulation time 228626016 ps
CPU time 3.21 seconds
Started Apr 23 02:46:12 PM PDT 24
Finished Apr 23 02:46:16 PM PDT 24
Peak memory 206304 kb
Host smart-6e6f80de-d4ab-4b18-bc50-b3fa3913f764
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717913704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2717913704
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2880213783
Short name T232
Test name
Test status
Simulation time 90914386 ps
CPU time 1.03 seconds
Started Apr 23 02:46:12 PM PDT 24
Finished Apr 23 02:46:14 PM PDT 24
Peak memory 206692 kb
Host smart-8e835044-83e5-46ac-9f64-91f0c82a21c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880213783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2880213783
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.edn_genbits.198596674
Short name T683
Test name
Test status
Simulation time 162610565 ps
CPU time 1.31 seconds
Started Apr 23 02:07:51 PM PDT 24
Finished Apr 23 02:07:53 PM PDT 24
Peak memory 218400 kb
Host smart-d25ccd6c-f971-4f9c-8d65-51ca7fa8150b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198596674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.198596674
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.1511129027
Short name T42
Test name
Test status
Simulation time 41572141 ps
CPU time 1.46 seconds
Started Apr 23 02:10:28 PM PDT 24
Finished Apr 23 02:10:31 PM PDT 24
Peak memory 219520 kb
Host smart-87779b53-21ff-4f31-ab6b-94c6df4f604f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511129027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1511129027
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.366602455
Short name T278
Test name
Test status
Simulation time 60185321 ps
CPU time 2.1 seconds
Started Apr 23 02:10:28 PM PDT 24
Finished Apr 23 02:10:31 PM PDT 24
Peak memory 218584 kb
Host smart-3cd36ba6-0025-41c6-b96a-2decd4fca5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366602455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.366602455
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.293131975
Short name T635
Test name
Test status
Simulation time 363000881 ps
CPU time 1.71 seconds
Started Apr 23 02:08:30 PM PDT 24
Finished Apr 23 02:08:32 PM PDT 24
Peak memory 215920 kb
Host smart-2ebe1fc6-b0e0-4b9b-a7ae-1ff879554e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293131975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.293131975
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_genbits.2415845939
Short name T810
Test name
Test status
Simulation time 58160975 ps
CPU time 1.36 seconds
Started Apr 23 02:08:25 PM PDT 24
Finished Apr 23 02:08:27 PM PDT 24
Peak memory 218412 kb
Host smart-c8e81ad3-15fc-4261-b880-c6e2ac8aa7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415845939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2415845939
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/130.edn_genbits.809784530
Short name T294
Test name
Test status
Simulation time 41838580 ps
CPU time 1.78 seconds
Started Apr 23 02:10:33 PM PDT 24
Finished Apr 23 02:10:37 PM PDT 24
Peak memory 218380 kb
Host smart-219a8d77-3b1b-44c3-971c-1185cbac19e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809784530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.809784530
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.3521233747
Short name T536
Test name
Test status
Simulation time 37623990 ps
CPU time 1.48 seconds
Started Apr 23 02:10:32 PM PDT 24
Finished Apr 23 02:10:34 PM PDT 24
Peak memory 219952 kb
Host smart-2a6f2bf0-d930-4007-9e83-0ec88e7b56f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521233747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3521233747
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_err.836681100
Short name T55
Test name
Test status
Simulation time 31536505 ps
CPU time 0.95 seconds
Started Apr 23 02:08:34 PM PDT 24
Finished Apr 23 02:08:36 PM PDT 24
Peak memory 224256 kb
Host smart-1d2aa227-c961-4a61-a55e-88ef649444b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836681100 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.836681100
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/176.edn_genbits.267629411
Short name T275
Test name
Test status
Simulation time 35428205 ps
CPU time 1.65 seconds
Started Apr 23 02:10:43 PM PDT 24
Finished Apr 23 02:10:45 PM PDT 24
Peak memory 218420 kb
Host smart-d3051344-ee27-46f7-b6bd-26aeca5b61c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267629411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.267629411
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1744666643
Short name T292
Test name
Test status
Simulation time 146299881 ps
CPU time 1.34 seconds
Started Apr 23 02:10:49 PM PDT 24
Finished Apr 23 02:10:51 PM PDT 24
Peak memory 218728 kb
Host smart-1b47b0ec-0443-4eb5-b03c-888d69cffa32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744666643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1744666643
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_regwen.3218878474
Short name T260
Test name
Test status
Simulation time 24628075 ps
CPU time 0.89 seconds
Started Apr 23 02:07:59 PM PDT 24
Finished Apr 23 02:08:00 PM PDT 24
Peak memory 207268 kb
Host smart-26d02271-02d5-45d6-8088-7f0de914ca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218878474 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3218878474
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/30.edn_genbits.1595156293
Short name T297
Test name
Test status
Simulation time 301001953 ps
CPU time 3.39 seconds
Started Apr 23 02:09:07 PM PDT 24
Finished Apr 23 02:09:11 PM PDT 24
Peak memory 217384 kb
Host smart-c872f7dc-bd09-4f15-81d7-44c6f6975a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595156293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1595156293
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.215146512
Short name T35
Test name
Test status
Simulation time 19436951 ps
CPU time 1.09 seconds
Started Apr 23 02:08:28 PM PDT 24
Finished Apr 23 02:08:29 PM PDT 24
Peak memory 216012 kb
Host smart-620e2cca-dc50-41bc-a218-a5650d910c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215146512 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.215146512
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/3.edn_disable.3040002385
Short name T185
Test name
Test status
Simulation time 33879420 ps
CPU time 1.01 seconds
Started Apr 23 02:08:04 PM PDT 24
Finished Apr 23 02:08:05 PM PDT 24
Peak memory 215520 kb
Host smart-28a1ccfc-4405-4ff5-ae30-b628eaa2f160
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040002385 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3040002385
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/106.edn_genbits.4279484928
Short name T330
Test name
Test status
Simulation time 60204897 ps
CPU time 1.65 seconds
Started Apr 23 02:10:29 PM PDT 24
Finished Apr 23 02:10:31 PM PDT 24
Peak memory 218728 kb
Host smart-3391f497-6225-41e5-9b53-dbbc19a28c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279484928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.4279484928
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3981722780
Short name T240
Test name
Test status
Simulation time 51052012 ps
CPU time 1.18 seconds
Started Apr 23 02:46:08 PM PDT 24
Finished Apr 23 02:46:10 PM PDT 24
Peak memory 206588 kb
Host smart-8bc82108-d0a5-44c3-8be6-bbf1913dc354
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981722780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3981722780
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.174735934
Short name T246
Test name
Test status
Simulation time 401918466 ps
CPU time 2.94 seconds
Started Apr 23 02:46:10 PM PDT 24
Finished Apr 23 02:46:13 PM PDT 24
Peak memory 206608 kb
Host smart-e5ecd9e6-4c66-4dc9-a9a0-32d4c29c8779
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174735934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.174735934
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3594147817
Short name T228
Test name
Test status
Simulation time 17521346 ps
CPU time 0.99 seconds
Started Apr 23 02:46:09 PM PDT 24
Finished Apr 23 02:46:11 PM PDT 24
Peak memory 206620 kb
Host smart-ab57ee39-ee99-488e-9c5d-755c40f81335
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594147817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3594147817
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2373282576
Short name T878
Test name
Test status
Simulation time 161683030 ps
CPU time 1.03 seconds
Started Apr 23 02:46:13 PM PDT 24
Finished Apr 23 02:46:15 PM PDT 24
Peak memory 216420 kb
Host smart-15faa06a-ff43-4a69-a746-b177dda33b71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373282576 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2373282576
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.4271186080
Short name T236
Test name
Test status
Simulation time 61292381 ps
CPU time 0.83 seconds
Started Apr 23 02:46:09 PM PDT 24
Finished Apr 23 02:46:11 PM PDT 24
Peak memory 206416 kb
Host smart-dbb35d50-a2b7-4b27-895f-a56ea6367bf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271186080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.4271186080
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.530395463
Short name T911
Test name
Test status
Simulation time 39339888 ps
CPU time 0.82 seconds
Started Apr 23 02:46:10 PM PDT 24
Finished Apr 23 02:46:11 PM PDT 24
Peak memory 206588 kb
Host smart-ff0c6b69-15d5-435c-8685-3587db8b0256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530395463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.530395463
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3016594276
Short name T886
Test name
Test status
Simulation time 41230188 ps
CPU time 1.09 seconds
Started Apr 23 02:46:08 PM PDT 24
Finished Apr 23 02:46:10 PM PDT 24
Peak memory 206616 kb
Host smart-19ce2dad-53d9-4edb-929a-e9becc589360
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016594276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3016594276
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3216560520
Short name T937
Test name
Test status
Simulation time 62447417 ps
CPU time 1.95 seconds
Started Apr 23 02:46:08 PM PDT 24
Finished Apr 23 02:46:11 PM PDT 24
Peak memory 214820 kb
Host smart-4d910fb6-809c-48e6-80d0-4146f6819d81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216560520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3216560520
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1351650187
Short name T966
Test name
Test status
Simulation time 20753277 ps
CPU time 1.23 seconds
Started Apr 23 02:46:12 PM PDT 24
Finished Apr 23 02:46:14 PM PDT 24
Peak memory 206640 kb
Host smart-403e2157-420f-4bd5-ada6-2a3c4b180102
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351650187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1351650187
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3922416039
Short name T247
Test name
Test status
Simulation time 23998431 ps
CPU time 0.89 seconds
Started Apr 23 02:46:13 PM PDT 24
Finished Apr 23 02:46:15 PM PDT 24
Peak memory 206628 kb
Host smart-c07586fd-8be3-46ab-ab0b-731358008aea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922416039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3922416039
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2605834485
Short name T860
Test name
Test status
Simulation time 22979065 ps
CPU time 1.25 seconds
Started Apr 23 02:46:12 PM PDT 24
Finished Apr 23 02:46:14 PM PDT 24
Peak memory 214984 kb
Host smart-5a99fada-14a4-46d3-93ab-654d29d39ac8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605834485 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2605834485
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.671038706
Short name T249
Test name
Test status
Simulation time 30951449 ps
CPU time 0.88 seconds
Started Apr 23 02:46:10 PM PDT 24
Finished Apr 23 02:46:12 PM PDT 24
Peak memory 206420 kb
Host smart-ad59b0c2-6128-4dde-963c-34ef391531a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671038706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.671038706
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.926946062
Short name T866
Test name
Test status
Simulation time 44393680 ps
CPU time 0.86 seconds
Started Apr 23 02:46:12 PM PDT 24
Finished Apr 23 02:46:13 PM PDT 24
Peak memory 206600 kb
Host smart-92c6c392-6e08-4225-bb0a-d78f9cd3c5a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926946062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.926946062
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3220836300
Short name T907
Test name
Test status
Simulation time 24083818 ps
CPU time 1.74 seconds
Started Apr 23 02:46:12 PM PDT 24
Finished Apr 23 02:46:14 PM PDT 24
Peak memory 218720 kb
Host smart-ea756ce6-0ac2-4886-8923-955f5e5b1e1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220836300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3220836300
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1190817860
Short name T895
Test name
Test status
Simulation time 57771069 ps
CPU time 1.78 seconds
Started Apr 23 02:46:11 PM PDT 24
Finished Apr 23 02:46:13 PM PDT 24
Peak memory 214776 kb
Host smart-ddf27fc0-c3c5-4151-b7cd-d2e87005b749
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190817860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1190817860
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3106929972
Short name T929
Test name
Test status
Simulation time 79516176 ps
CPU time 1.25 seconds
Started Apr 23 02:46:30 PM PDT 24
Finished Apr 23 02:46:32 PM PDT 24
Peak memory 214892 kb
Host smart-9dac7a76-50cd-4324-a66b-60c300c3815a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106929972 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3106929972
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3108323448
Short name T864
Test name
Test status
Simulation time 17313303 ps
CPU time 1.03 seconds
Started Apr 23 02:46:30 PM PDT 24
Finished Apr 23 02:46:32 PM PDT 24
Peak memory 206656 kb
Host smart-684f1003-bb5e-4de5-be3a-edb90f8255a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108323448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3108323448
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3721277375
Short name T951
Test name
Test status
Simulation time 29404192 ps
CPU time 0.9 seconds
Started Apr 23 02:46:29 PM PDT 24
Finished Apr 23 02:46:31 PM PDT 24
Peak memory 206628 kb
Host smart-ac35ed63-b4a4-43ea-9d8e-7e2e605a4531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721277375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3721277375
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2489243630
Short name T916
Test name
Test status
Simulation time 143344359 ps
CPU time 1.37 seconds
Started Apr 23 02:46:27 PM PDT 24
Finished Apr 23 02:46:29 PM PDT 24
Peak memory 206620 kb
Host smart-867c76b2-db77-4792-a2b4-49b782e29062
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489243630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2489243630
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1419764978
Short name T940
Test name
Test status
Simulation time 499727898 ps
CPU time 4.59 seconds
Started Apr 23 02:46:31 PM PDT 24
Finished Apr 23 02:46:37 PM PDT 24
Peak memory 214900 kb
Host smart-8a6c84a9-f9c2-48e1-9652-09d2e7981df5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419764978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1419764978
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2103113698
Short name T250
Test name
Test status
Simulation time 1156019699 ps
CPU time 2.25 seconds
Started Apr 23 02:46:27 PM PDT 24
Finished Apr 23 02:46:30 PM PDT 24
Peak memory 206788 kb
Host smart-64e3fd42-61a6-43f1-b127-441f191078d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103113698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2103113698
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2378023537
Short name T875
Test name
Test status
Simulation time 75845858 ps
CPU time 1.53 seconds
Started Apr 23 02:46:27 PM PDT 24
Finished Apr 23 02:46:29 PM PDT 24
Peak memory 214904 kb
Host smart-af8da68e-c6a9-420d-9c10-049c955d7c3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378023537 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2378023537
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3725118168
Short name T922
Test name
Test status
Simulation time 21748843 ps
CPU time 0.85 seconds
Started Apr 23 02:46:29 PM PDT 24
Finished Apr 23 02:46:31 PM PDT 24
Peak memory 206616 kb
Host smart-b5ee3e31-5b4e-406b-bdc8-a0a222e109c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725118168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3725118168
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3891822064
Short name T846
Test name
Test status
Simulation time 25455632 ps
CPU time 0.85 seconds
Started Apr 23 02:46:28 PM PDT 24
Finished Apr 23 02:46:29 PM PDT 24
Peak memory 206648 kb
Host smart-61d90e60-3386-4453-b727-dd961bf77f57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891822064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3891822064
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2077409871
Short name T899
Test name
Test status
Simulation time 101623035 ps
CPU time 1.4 seconds
Started Apr 23 02:46:28 PM PDT 24
Finished Apr 23 02:46:31 PM PDT 24
Peak memory 206648 kb
Host smart-658a6e2f-5560-4a3a-830a-e8ff5d17efec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077409871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2077409871
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1810381786
Short name T921
Test name
Test status
Simulation time 820145755 ps
CPU time 3.36 seconds
Started Apr 23 02:46:29 PM PDT 24
Finished Apr 23 02:46:33 PM PDT 24
Peak memory 214864 kb
Host smart-8779e6b9-5b69-4ead-bbb2-c4577eb486b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810381786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1810381786
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1163616227
Short name T883
Test name
Test status
Simulation time 160042983 ps
CPU time 2.35 seconds
Started Apr 23 02:46:27 PM PDT 24
Finished Apr 23 02:46:30 PM PDT 24
Peak memory 206964 kb
Host smart-bbd70682-f41e-48ba-a6d5-55f3fca2210a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163616227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1163616227
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3752565452
Short name T932
Test name
Test status
Simulation time 34453265 ps
CPU time 1.48 seconds
Started Apr 23 02:46:28 PM PDT 24
Finished Apr 23 02:46:30 PM PDT 24
Peak memory 214848 kb
Host smart-56a5f380-81d7-46ba-a2f5-37f02b91864a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752565452 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3752565452
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2498717230
Short name T235
Test name
Test status
Simulation time 12188954 ps
CPU time 0.89 seconds
Started Apr 23 02:46:28 PM PDT 24
Finished Apr 23 02:46:30 PM PDT 24
Peak memory 206632 kb
Host smart-ecbde1ed-f3fa-479a-986d-12a692f55b42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498717230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2498717230
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3174789102
Short name T953
Test name
Test status
Simulation time 27835359 ps
CPU time 0.89 seconds
Started Apr 23 02:46:31 PM PDT 24
Finished Apr 23 02:46:33 PM PDT 24
Peak memory 206644 kb
Host smart-401ed0a6-358c-4f01-b32a-5fa8579e65f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174789102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3174789102
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.972908971
Short name T949
Test name
Test status
Simulation time 22718703 ps
CPU time 1.12 seconds
Started Apr 23 02:46:29 PM PDT 24
Finished Apr 23 02:46:31 PM PDT 24
Peak memory 206696 kb
Host smart-30a3293f-7b42-4bdb-b8fe-b66d5ecaad0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972908971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.972908971
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.4197405298
Short name T892
Test name
Test status
Simulation time 262040008 ps
CPU time 2.48 seconds
Started Apr 23 02:46:29 PM PDT 24
Finished Apr 23 02:46:32 PM PDT 24
Peak memory 214852 kb
Host smart-537767f3-92b2-4c7e-bb69-659d623a3412
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197405298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.4197405298
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1842071102
Short name T251
Test name
Test status
Simulation time 38348723 ps
CPU time 1.51 seconds
Started Apr 23 02:46:29 PM PDT 24
Finished Apr 23 02:46:31 PM PDT 24
Peak memory 206640 kb
Host smart-3d70f3bf-7092-4c07-aedb-e6ad33c45c92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842071102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1842071102
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.15525934
Short name T954
Test name
Test status
Simulation time 88564588 ps
CPU time 1.56 seconds
Started Apr 23 02:46:33 PM PDT 24
Finished Apr 23 02:46:35 PM PDT 24
Peak memory 214920 kb
Host smart-d5601df6-027c-4b4a-98e1-0eb205d59b47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15525934 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.15525934
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3667162368
Short name T915
Test name
Test status
Simulation time 24859225 ps
CPU time 0.91 seconds
Started Apr 23 02:46:30 PM PDT 24
Finished Apr 23 02:46:32 PM PDT 24
Peak memory 206656 kb
Host smart-6160f6b6-6b46-42a8-b9c2-48684a4e2e0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667162368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3667162368
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3421536540
Short name T928
Test name
Test status
Simulation time 13676551 ps
CPU time 0.87 seconds
Started Apr 23 02:46:30 PM PDT 24
Finished Apr 23 02:46:32 PM PDT 24
Peak memory 206620 kb
Host smart-a5eb7703-cdb4-4688-9f98-0164b0b63266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421536540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3421536540
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3034206591
Short name T896
Test name
Test status
Simulation time 26284191 ps
CPU time 1.18 seconds
Started Apr 23 02:46:31 PM PDT 24
Finished Apr 23 02:46:33 PM PDT 24
Peak memory 206708 kb
Host smart-ffc8e10d-e6f0-402d-ba4c-c4b2044c9bce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034206591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3034206591
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.396140054
Short name T854
Test name
Test status
Simulation time 55758245 ps
CPU time 2.16 seconds
Started Apr 23 02:46:29 PM PDT 24
Finished Apr 23 02:46:32 PM PDT 24
Peak memory 214916 kb
Host smart-ffa74e9d-5e85-4dfa-84d9-a6bbb109e6bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396140054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.396140054
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.738996172
Short name T935
Test name
Test status
Simulation time 74601979 ps
CPU time 1.66 seconds
Started Apr 23 02:46:32 PM PDT 24
Finished Apr 23 02:46:34 PM PDT 24
Peak memory 206940 kb
Host smart-2f45e19c-afcb-461c-aba2-e0175814bdf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738996172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.738996172
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4202880227
Short name T897
Test name
Test status
Simulation time 66946908 ps
CPU time 0.94 seconds
Started Apr 23 02:46:29 PM PDT 24
Finished Apr 23 02:46:31 PM PDT 24
Peak memory 206720 kb
Host smart-73ae1df5-03ab-45e0-9abb-4fcf61a8f5d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202880227 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.4202880227
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2465449103
Short name T234
Test name
Test status
Simulation time 31791605 ps
CPU time 0.93 seconds
Started Apr 23 02:46:33 PM PDT 24
Finished Apr 23 02:46:35 PM PDT 24
Peak memory 206552 kb
Host smart-22633098-c878-450f-8d46-c5ac2affb7b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465449103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2465449103
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2477814960
Short name T918
Test name
Test status
Simulation time 14309241 ps
CPU time 0.88 seconds
Started Apr 23 02:46:30 PM PDT 24
Finished Apr 23 02:46:32 PM PDT 24
Peak memory 206604 kb
Host smart-1f6ca9a2-541b-4e9d-84b2-7d25a05bcde9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477814960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2477814960
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1525733334
Short name T923
Test name
Test status
Simulation time 70137492 ps
CPU time 1.53 seconds
Started Apr 23 02:46:31 PM PDT 24
Finished Apr 23 02:46:34 PM PDT 24
Peak memory 206608 kb
Host smart-2821761f-3b0b-4bdd-aea0-f1a6e9f0faa3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525733334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1525733334
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2492371964
Short name T869
Test name
Test status
Simulation time 25637419 ps
CPU time 1.71 seconds
Started Apr 23 02:46:34 PM PDT 24
Finished Apr 23 02:46:36 PM PDT 24
Peak memory 214912 kb
Host smart-91ab500e-d8f8-49b1-beea-8e5bf4e60899
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492371964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2492371964
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.4123755328
Short name T955
Test name
Test status
Simulation time 95028147 ps
CPU time 1.61 seconds
Started Apr 23 02:46:31 PM PDT 24
Finished Apr 23 02:46:33 PM PDT 24
Peak memory 214820 kb
Host smart-5965e1ee-eb6e-4bde-a3cc-c6451d39d925
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123755328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.4123755328
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.799323587
Short name T849
Test name
Test status
Simulation time 39661391 ps
CPU time 1.43 seconds
Started Apr 23 02:46:35 PM PDT 24
Finished Apr 23 02:46:37 PM PDT 24
Peak memory 217584 kb
Host smart-bae3402b-e1ca-4466-a74f-46a5b813211b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799323587 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.799323587
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2379163410
Short name T959
Test name
Test status
Simulation time 60330941 ps
CPU time 0.82 seconds
Started Apr 23 02:46:34 PM PDT 24
Finished Apr 23 02:46:36 PM PDT 24
Peak memory 206380 kb
Host smart-ec725850-ea24-4a5f-98e3-9ec7c2e9909d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379163410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2379163410
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3446866352
Short name T965
Test name
Test status
Simulation time 34369286 ps
CPU time 0.78 seconds
Started Apr 23 02:46:34 PM PDT 24
Finished Apr 23 02:46:36 PM PDT 24
Peak memory 206428 kb
Host smart-c4b7e0d4-af4e-44dc-9e55-753327a1f547
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446866352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3446866352
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2054767149
Short name T904
Test name
Test status
Simulation time 60249960 ps
CPU time 1.09 seconds
Started Apr 23 02:46:34 PM PDT 24
Finished Apr 23 02:46:36 PM PDT 24
Peak memory 206720 kb
Host smart-ef1beb4c-83e4-43d4-a723-d5e87710d51a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054767149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2054767149
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.398591640
Short name T941
Test name
Test status
Simulation time 41388330 ps
CPU time 2.74 seconds
Started Apr 23 02:46:33 PM PDT 24
Finished Apr 23 02:46:37 PM PDT 24
Peak memory 214872 kb
Host smart-285e0978-f5c6-4364-ab15-625a158c6d60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398591640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.398591640
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1297013003
Short name T252
Test name
Test status
Simulation time 45540655 ps
CPU time 1.62 seconds
Started Apr 23 02:46:30 PM PDT 24
Finished Apr 23 02:46:32 PM PDT 24
Peak memory 214796 kb
Host smart-f5ddf514-372e-447d-b906-b9ff7456a903
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297013003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1297013003
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.669301485
Short name T870
Test name
Test status
Simulation time 126141429 ps
CPU time 1.2 seconds
Started Apr 23 02:46:33 PM PDT 24
Finished Apr 23 02:46:34 PM PDT 24
Peak memory 214796 kb
Host smart-70ca8b83-8b32-4928-b511-65346bcfcef0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669301485 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.669301485
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3996884218
Short name T227
Test name
Test status
Simulation time 39973899 ps
CPU time 0.84 seconds
Started Apr 23 02:46:34 PM PDT 24
Finished Apr 23 02:46:35 PM PDT 24
Peak memory 206600 kb
Host smart-6926fc8f-5bdb-41aa-b4d0-fd675ca08cd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996884218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3996884218
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.220687293
Short name T884
Test name
Test status
Simulation time 13276424 ps
CPU time 0.82 seconds
Started Apr 23 02:46:35 PM PDT 24
Finished Apr 23 02:46:36 PM PDT 24
Peak memory 206608 kb
Host smart-64e326bb-b3db-45b7-ab4f-8e2dea62c5ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220687293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.220687293
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2450709208
Short name T891
Test name
Test status
Simulation time 26514179 ps
CPU time 0.95 seconds
Started Apr 23 02:46:34 PM PDT 24
Finished Apr 23 02:46:36 PM PDT 24
Peak memory 206600 kb
Host smart-2b93cbf5-2f97-451c-b8ef-2f1f0d885c4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450709208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2450709208
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.671096812
Short name T863
Test name
Test status
Simulation time 337702346 ps
CPU time 3.37 seconds
Started Apr 23 02:46:35 PM PDT 24
Finished Apr 23 02:46:39 PM PDT 24
Peak memory 214832 kb
Host smart-5534e4db-f8a9-4962-a379-db6b072e0c02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671096812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.671096812
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.246206969
Short name T880
Test name
Test status
Simulation time 88219453 ps
CPU time 1.54 seconds
Started Apr 23 02:46:34 PM PDT 24
Finished Apr 23 02:46:36 PM PDT 24
Peak memory 214848 kb
Host smart-496e9409-cc82-4414-9aad-64ed248c3a35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246206969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.246206969
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2687334603
Short name T852
Test name
Test status
Simulation time 74325825 ps
CPU time 1.53 seconds
Started Apr 23 02:46:36 PM PDT 24
Finished Apr 23 02:46:38 PM PDT 24
Peak memory 223128 kb
Host smart-f18f9698-9f0d-488d-9a98-868f75979a8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687334603 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2687334603
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2763229802
Short name T972
Test name
Test status
Simulation time 16179337 ps
CPU time 0.97 seconds
Started Apr 23 02:46:39 PM PDT 24
Finished Apr 23 02:46:40 PM PDT 24
Peak memory 206640 kb
Host smart-b706ffc9-1a31-4637-8d91-6caf9506f4e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763229802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2763229802
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2017990114
Short name T902
Test name
Test status
Simulation time 13007796 ps
CPU time 0.89 seconds
Started Apr 23 02:46:37 PM PDT 24
Finished Apr 23 02:46:39 PM PDT 24
Peak memory 206596 kb
Host smart-a7ea9f0b-741a-4e66-a73f-7ce002655fda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017990114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2017990114
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3500437616
Short name T963
Test name
Test status
Simulation time 17733730 ps
CPU time 1.05 seconds
Started Apr 23 02:46:36 PM PDT 24
Finished Apr 23 02:46:38 PM PDT 24
Peak memory 206604 kb
Host smart-f8918fe8-b1c2-4e0b-bca0-1efa16b6552e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500437616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3500437616
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2243733891
Short name T900
Test name
Test status
Simulation time 1582275637 ps
CPU time 4.53 seconds
Started Apr 23 02:46:37 PM PDT 24
Finished Apr 23 02:46:42 PM PDT 24
Peak memory 214868 kb
Host smart-32333994-83b9-4c6f-baad-a85063f24303
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243733891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2243733891
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2243791939
Short name T894
Test name
Test status
Simulation time 673589555 ps
CPU time 3.52 seconds
Started Apr 23 02:46:40 PM PDT 24
Finished Apr 23 02:46:44 PM PDT 24
Peak memory 214824 kb
Host smart-97966d54-cbe9-457e-b78a-ce9f8aadddd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243791939 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2243791939
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1477051349
Short name T873
Test name
Test status
Simulation time 55836590 ps
CPU time 1.2 seconds
Started Apr 23 02:46:37 PM PDT 24
Finished Apr 23 02:46:38 PM PDT 24
Peak memory 214976 kb
Host smart-218cd88e-0468-4c61-85fe-bc913edba71a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477051349 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1477051349
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2812844258
Short name T248
Test name
Test status
Simulation time 13694709 ps
CPU time 0.92 seconds
Started Apr 23 02:46:38 PM PDT 24
Finished Apr 23 02:46:40 PM PDT 24
Peak memory 206624 kb
Host smart-e6f9ce8e-9dfe-4f97-a0d1-86681f173410
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812844258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2812844258
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2312469864
Short name T850
Test name
Test status
Simulation time 154825952 ps
CPU time 0.8 seconds
Started Apr 23 02:46:40 PM PDT 24
Finished Apr 23 02:46:41 PM PDT 24
Peak memory 206388 kb
Host smart-0a9d3baa-435a-4640-9c0c-5fa00926586d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312469864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2312469864
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.505906930
Short name T245
Test name
Test status
Simulation time 15446612 ps
CPU time 0.97 seconds
Started Apr 23 02:46:37 PM PDT 24
Finished Apr 23 02:46:38 PM PDT 24
Peak memory 206592 kb
Host smart-ba8bd39b-d22d-426d-960b-2d6f4655590a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505906930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.505906930
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3312910504
Short name T885
Test name
Test status
Simulation time 205704855 ps
CPU time 3.5 seconds
Started Apr 23 02:46:37 PM PDT 24
Finished Apr 23 02:46:41 PM PDT 24
Peak memory 214820 kb
Host smart-1422eea2-43be-452c-a210-a299e23a202b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312910504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3312910504
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2433469984
Short name T256
Test name
Test status
Simulation time 229087399 ps
CPU time 2.75 seconds
Started Apr 23 02:46:38 PM PDT 24
Finished Apr 23 02:46:41 PM PDT 24
Peak memory 206632 kb
Host smart-ee18d91d-7576-4d5c-9556-373d10f6e79c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433469984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2433469984
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.774702844
Short name T927
Test name
Test status
Simulation time 45708911 ps
CPU time 0.99 seconds
Started Apr 23 02:46:38 PM PDT 24
Finished Apr 23 02:46:39 PM PDT 24
Peak memory 214880 kb
Host smart-c909fd00-e8ee-4488-823a-1f6a4b57ba51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774702844 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.774702844
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1533859608
Short name T926
Test name
Test status
Simulation time 14468447 ps
CPU time 0.87 seconds
Started Apr 23 02:46:36 PM PDT 24
Finished Apr 23 02:46:38 PM PDT 24
Peak memory 206584 kb
Host smart-f8eb3069-6ba2-4965-af4e-a1b57eddce27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533859608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1533859608
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.4290132221
Short name T973
Test name
Test status
Simulation time 70593116 ps
CPU time 0.83 seconds
Started Apr 23 02:46:39 PM PDT 24
Finished Apr 23 02:46:40 PM PDT 24
Peak memory 206408 kb
Host smart-0a8fbef8-7aae-40b1-a257-7c79430a2052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290132221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.4290132221
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.809518881
Short name T226
Test name
Test status
Simulation time 30366635 ps
CPU time 1.34 seconds
Started Apr 23 02:46:36 PM PDT 24
Finished Apr 23 02:46:38 PM PDT 24
Peak memory 206664 kb
Host smart-b4508f7a-673c-4be8-ad24-be28ec618c59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809518881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.809518881
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3224440163
Short name T898
Test name
Test status
Simulation time 350106074 ps
CPU time 5.85 seconds
Started Apr 23 02:46:37 PM PDT 24
Finished Apr 23 02:46:44 PM PDT 24
Peak memory 214948 kb
Host smart-9cc3fb18-b157-4983-918f-04336c2da833
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224440163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3224440163
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1289186412
Short name T913
Test name
Test status
Simulation time 167326702 ps
CPU time 1.54 seconds
Started Apr 23 02:46:40 PM PDT 24
Finished Apr 23 02:46:42 PM PDT 24
Peak memory 206584 kb
Host smart-6b75182a-ea3b-4e1a-ab02-85df6059d2bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289186412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1289186412
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.884404548
Short name T238
Test name
Test status
Simulation time 55302488 ps
CPU time 1.06 seconds
Started Apr 23 02:46:16 PM PDT 24
Finished Apr 23 02:46:18 PM PDT 24
Peak memory 206624 kb
Host smart-d85f70b9-e6f0-44e3-b217-a4529d9d6ab4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884404548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.884404548
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2235741012
Short name T936
Test name
Test status
Simulation time 353325263 ps
CPU time 5.32 seconds
Started Apr 23 02:46:14 PM PDT 24
Finished Apr 23 02:46:20 PM PDT 24
Peak memory 206600 kb
Host smart-345a299a-ee8f-4b57-ba72-9c60599aee4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235741012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2235741012
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1503972499
Short name T930
Test name
Test status
Simulation time 39567250 ps
CPU time 0.85 seconds
Started Apr 23 02:46:13 PM PDT 24
Finished Apr 23 02:46:15 PM PDT 24
Peak memory 206448 kb
Host smart-3e59ba24-ef9e-4102-b9d2-5585ae5c37ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503972499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1503972499
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1030846377
Short name T905
Test name
Test status
Simulation time 74515048 ps
CPU time 1.43 seconds
Started Apr 23 02:46:16 PM PDT 24
Finished Apr 23 02:46:18 PM PDT 24
Peak memory 223056 kb
Host smart-f9af0816-f2d4-45d7-a08e-a5ce88c96fb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030846377 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1030846377
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1774006993
Short name T237
Test name
Test status
Simulation time 15019281 ps
CPU time 1 seconds
Started Apr 23 02:46:11 PM PDT 24
Finished Apr 23 02:46:13 PM PDT 24
Peak memory 206612 kb
Host smart-9a90625f-8fe5-4406-b1cb-a6d7ecc74717
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774006993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1774006993
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1745587223
Short name T861
Test name
Test status
Simulation time 27392958 ps
CPU time 0.88 seconds
Started Apr 23 02:46:12 PM PDT 24
Finished Apr 23 02:46:13 PM PDT 24
Peak memory 206304 kb
Host smart-99d0cdc8-ea9c-4c55-b96a-bdef6eda0f0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745587223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1745587223
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.100345780
Short name T924
Test name
Test status
Simulation time 25720661 ps
CPU time 1.24 seconds
Started Apr 23 02:46:14 PM PDT 24
Finished Apr 23 02:46:16 PM PDT 24
Peak memory 206724 kb
Host smart-6358bb7d-4f35-48ac-9e4e-b818310ed150
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100345780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out
standing.100345780
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1240453474
Short name T890
Test name
Test status
Simulation time 36673712 ps
CPU time 2.31 seconds
Started Apr 23 02:46:12 PM PDT 24
Finished Apr 23 02:46:15 PM PDT 24
Peak memory 218768 kb
Host smart-9e7a772e-5c22-46de-962c-5017d0fd3ea5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240453474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1240453474
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1082415243
Short name T909
Test name
Test status
Simulation time 192440064 ps
CPU time 2.02 seconds
Started Apr 23 02:46:11 PM PDT 24
Finished Apr 23 02:46:14 PM PDT 24
Peak memory 214960 kb
Host smart-7d7a5fac-6014-438e-b12e-2777799abb74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082415243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1082415243
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.491674740
Short name T856
Test name
Test status
Simulation time 49643019 ps
CPU time 0.89 seconds
Started Apr 23 02:46:42 PM PDT 24
Finished Apr 23 02:46:43 PM PDT 24
Peak memory 206576 kb
Host smart-72b9e2c4-2d0a-42d0-8bd9-5aa49137d895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491674740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.491674740
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2528739336
Short name T931
Test name
Test status
Simulation time 16646669 ps
CPU time 0.91 seconds
Started Apr 23 02:46:42 PM PDT 24
Finished Apr 23 02:46:44 PM PDT 24
Peak memory 206604 kb
Host smart-65225e6a-49ff-4dad-be46-9101695f4c12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528739336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2528739336
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3804371648
Short name T958
Test name
Test status
Simulation time 32637202 ps
CPU time 0.83 seconds
Started Apr 23 02:46:41 PM PDT 24
Finished Apr 23 02:46:43 PM PDT 24
Peak memory 206428 kb
Host smart-cccaae6e-81ff-4a5e-83a6-9d86c435a41b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804371648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3804371648
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3580731873
Short name T858
Test name
Test status
Simulation time 29779059 ps
CPU time 0.82 seconds
Started Apr 23 02:46:45 PM PDT 24
Finished Apr 23 02:46:46 PM PDT 24
Peak memory 206432 kb
Host smart-ff6017b0-8d4a-4d84-bde4-28beffb7cd86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580731873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3580731873
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.765085512
Short name T871
Test name
Test status
Simulation time 16392868 ps
CPU time 0.81 seconds
Started Apr 23 02:46:38 PM PDT 24
Finished Apr 23 02:46:40 PM PDT 24
Peak memory 206400 kb
Host smart-c35c2be0-cbc5-4c6a-8dd5-1af67dcb3a6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765085512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.765085512
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3524056203
Short name T843
Test name
Test status
Simulation time 20205968 ps
CPU time 0.81 seconds
Started Apr 23 02:46:40 PM PDT 24
Finished Apr 23 02:46:41 PM PDT 24
Peak memory 206648 kb
Host smart-5e5f1dc0-bee7-4506-b603-30ebe40c65c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524056203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3524056203
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.4187173148
Short name T906
Test name
Test status
Simulation time 12160177 ps
CPU time 0.84 seconds
Started Apr 23 02:46:41 PM PDT 24
Finished Apr 23 02:46:42 PM PDT 24
Peak memory 206632 kb
Host smart-50ec7ece-4a3a-4f0e-aa3d-00068ed12cc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187173148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.4187173148
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.4162839538
Short name T962
Test name
Test status
Simulation time 34501065 ps
CPU time 0.84 seconds
Started Apr 23 02:46:41 PM PDT 24
Finished Apr 23 02:46:43 PM PDT 24
Peak memory 206440 kb
Host smart-5a7b3bae-394b-45d4-bbd3-42350f719b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162839538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.4162839538
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.343720683
Short name T975
Test name
Test status
Simulation time 29627770 ps
CPU time 0.81 seconds
Started Apr 23 02:46:39 PM PDT 24
Finished Apr 23 02:46:40 PM PDT 24
Peak memory 206344 kb
Host smart-b02729cc-4946-4663-8fa6-f13c78843cae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343720683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.343720683
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1628402848
Short name T917
Test name
Test status
Simulation time 24074358 ps
CPU time 0.87 seconds
Started Apr 23 02:46:41 PM PDT 24
Finished Apr 23 02:46:42 PM PDT 24
Peak memory 206632 kb
Host smart-617b1bc4-1448-45de-a4e1-26e2edf1267e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628402848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1628402848
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1369499757
Short name T942
Test name
Test status
Simulation time 34532482 ps
CPU time 1.25 seconds
Started Apr 23 02:46:18 PM PDT 24
Finished Apr 23 02:46:20 PM PDT 24
Peak memory 206636 kb
Host smart-fad66228-228e-4c21-ae16-1fba45589f0e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369499757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1369499757
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2476550566
Short name T872
Test name
Test status
Simulation time 62806819 ps
CPU time 3.35 seconds
Started Apr 23 02:46:16 PM PDT 24
Finished Apr 23 02:46:19 PM PDT 24
Peak memory 206592 kb
Host smart-d7649dbc-578f-4e4c-b8b3-6fc752511fa0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476550566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2476550566
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.248863489
Short name T960
Test name
Test status
Simulation time 17805031 ps
CPU time 0.99 seconds
Started Apr 23 02:46:16 PM PDT 24
Finished Apr 23 02:46:18 PM PDT 24
Peak memory 206556 kb
Host smart-b46ae479-92d8-4dc0-ad5d-d35b6b650e60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248863489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.248863489
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3814405877
Short name T847
Test name
Test status
Simulation time 65738469 ps
CPU time 1.59 seconds
Started Apr 23 02:46:19 PM PDT 24
Finished Apr 23 02:46:21 PM PDT 24
Peak memory 214812 kb
Host smart-a656090e-30d5-4313-9fa5-cceb9ea669cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814405877 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3814405877
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.185770041
Short name T938
Test name
Test status
Simulation time 16939827 ps
CPU time 0.86 seconds
Started Apr 23 02:46:15 PM PDT 24
Finished Apr 23 02:46:16 PM PDT 24
Peak memory 206624 kb
Host smart-5e94d99e-2e17-4fa7-9d02-6a88d81b37fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185770041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.185770041
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2113760703
Short name T853
Test name
Test status
Simulation time 14177925 ps
CPU time 0.84 seconds
Started Apr 23 02:46:15 PM PDT 24
Finished Apr 23 02:46:16 PM PDT 24
Peak memory 206604 kb
Host smart-65e135fb-c7fc-4138-97c6-642cdbe2f0a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113760703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2113760703
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2294545461
Short name T223
Test name
Test status
Simulation time 54274381 ps
CPU time 0.95 seconds
Started Apr 23 02:46:20 PM PDT 24
Finished Apr 23 02:46:21 PM PDT 24
Peak memory 206692 kb
Host smart-8886b489-cb36-4291-b903-4562295b6a12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294545461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2294545461
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3088289709
Short name T844
Test name
Test status
Simulation time 43855161 ps
CPU time 3.17 seconds
Started Apr 23 02:46:15 PM PDT 24
Finished Apr 23 02:46:19 PM PDT 24
Peak memory 214900 kb
Host smart-f6259ae1-7446-4dc3-a97c-342fbf2a06fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088289709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3088289709
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3658117632
Short name T901
Test name
Test status
Simulation time 58895277 ps
CPU time 1.75 seconds
Started Apr 23 02:46:13 PM PDT 24
Finished Apr 23 02:46:15 PM PDT 24
Peak memory 206900 kb
Host smart-21fe5f86-5369-42db-8fb2-d1012b7176e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658117632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3658117632
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1881289930
Short name T876
Test name
Test status
Simulation time 27068333 ps
CPU time 0.85 seconds
Started Apr 23 02:46:40 PM PDT 24
Finished Apr 23 02:46:41 PM PDT 24
Peak memory 206696 kb
Host smart-38068a74-a57c-4521-9879-1ea306040f43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881289930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1881289930
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1416372147
Short name T961
Test name
Test status
Simulation time 36974134 ps
CPU time 0.86 seconds
Started Apr 23 02:46:40 PM PDT 24
Finished Apr 23 02:46:41 PM PDT 24
Peak memory 206640 kb
Host smart-98768ec0-c80e-4cfe-be18-33ad7de41abb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416372147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1416372147
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3200920671
Short name T903
Test name
Test status
Simulation time 61327946 ps
CPU time 0.88 seconds
Started Apr 23 02:46:45 PM PDT 24
Finished Apr 23 02:46:47 PM PDT 24
Peak memory 206708 kb
Host smart-e380dc93-2f2c-4f07-a93c-543f53a5dbf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200920671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3200920671
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3568050437
Short name T857
Test name
Test status
Simulation time 22567735 ps
CPU time 0.86 seconds
Started Apr 23 02:46:41 PM PDT 24
Finished Apr 23 02:46:43 PM PDT 24
Peak memory 206624 kb
Host smart-e543040d-7106-4f6b-987a-303ffc5822f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568050437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3568050437
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1013990701
Short name T862
Test name
Test status
Simulation time 182856350 ps
CPU time 0.84 seconds
Started Apr 23 02:46:40 PM PDT 24
Finished Apr 23 02:46:41 PM PDT 24
Peak memory 206608 kb
Host smart-9c192c7e-c9d4-4fec-aa93-2907fee5eb12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013990701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1013990701
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3432995150
Short name T974
Test name
Test status
Simulation time 32719321 ps
CPU time 0.79 seconds
Started Apr 23 02:46:39 PM PDT 24
Finished Apr 23 02:46:40 PM PDT 24
Peak memory 206440 kb
Host smart-93c3bd57-ea7a-47e1-bf61-448225b8f74d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432995150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3432995150
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.4246476827
Short name T945
Test name
Test status
Simulation time 22557993 ps
CPU time 0.84 seconds
Started Apr 23 02:46:45 PM PDT 24
Finished Apr 23 02:46:46 PM PDT 24
Peak memory 206612 kb
Host smart-13bab3d1-1427-4aba-88ec-c0ae0d2b661d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246476827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.4246476827
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2912513013
Short name T946
Test name
Test status
Simulation time 27312429 ps
CPU time 0.86 seconds
Started Apr 23 02:46:45 PM PDT 24
Finished Apr 23 02:46:47 PM PDT 24
Peak memory 206628 kb
Host smart-a5621ff5-033e-4ad3-a160-b63e757bd64c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912513013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2912513013
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.4134691058
Short name T950
Test name
Test status
Simulation time 37397604 ps
CPU time 0.84 seconds
Started Apr 23 02:46:41 PM PDT 24
Finished Apr 23 02:46:42 PM PDT 24
Peak memory 206556 kb
Host smart-b8190c42-cd35-4364-9dce-fe542b3cbf1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134691058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.4134691058
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2569718472
Short name T914
Test name
Test status
Simulation time 51974057 ps
CPU time 0.88 seconds
Started Apr 23 02:46:40 PM PDT 24
Finished Apr 23 02:46:42 PM PDT 24
Peak memory 206680 kb
Host smart-f876c826-1aac-40b2-8ae3-16f23cc63891
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569718472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2569718472
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.4280001605
Short name T910
Test name
Test status
Simulation time 140693355 ps
CPU time 1.17 seconds
Started Apr 23 02:46:19 PM PDT 24
Finished Apr 23 02:46:21 PM PDT 24
Peak memory 206672 kb
Host smart-abe99f8b-738c-4917-9326-b8fc0dd4680c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280001605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.4280001605
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2813824198
Short name T231
Test name
Test status
Simulation time 58143300 ps
CPU time 3.21 seconds
Started Apr 23 02:46:19 PM PDT 24
Finished Apr 23 02:46:22 PM PDT 24
Peak memory 206644 kb
Host smart-3cd796e3-c911-4f1f-82de-c951c784c2f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813824198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2813824198
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.733551141
Short name T925
Test name
Test status
Simulation time 18879531 ps
CPU time 1.21 seconds
Started Apr 23 02:46:17 PM PDT 24
Finished Apr 23 02:46:19 PM PDT 24
Peak memory 215000 kb
Host smart-ebac5901-e396-4ab7-a9dc-528d36c5a3e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733551141 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.733551141
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2755725777
Short name T241
Test name
Test status
Simulation time 51859767 ps
CPU time 0.88 seconds
Started Apr 23 02:46:19 PM PDT 24
Finished Apr 23 02:46:20 PM PDT 24
Peak memory 206636 kb
Host smart-4c0e4817-8ac1-4f08-8dce-a4ededb4b862
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755725777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2755725777
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.4073787839
Short name T867
Test name
Test status
Simulation time 23292897 ps
CPU time 0.84 seconds
Started Apr 23 02:46:17 PM PDT 24
Finished Apr 23 02:46:18 PM PDT 24
Peak memory 206672 kb
Host smart-ea39546f-f407-4fb6-8fd1-198bae66c61a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073787839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.4073787839
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2343720170
Short name T244
Test name
Test status
Simulation time 46398643 ps
CPU time 1.18 seconds
Started Apr 23 02:46:19 PM PDT 24
Finished Apr 23 02:46:21 PM PDT 24
Peak memory 206624 kb
Host smart-6d117a51-bcf9-41bb-9e10-c2bf02f0ed98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343720170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2343720170
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2995432904
Short name T865
Test name
Test status
Simulation time 21729365 ps
CPU time 1.51 seconds
Started Apr 23 02:46:21 PM PDT 24
Finished Apr 23 02:46:23 PM PDT 24
Peak memory 214952 kb
Host smart-c72a6917-c84c-4381-9e8a-1413f7cd5ad7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995432904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2995432904
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2029453436
Short name T968
Test name
Test status
Simulation time 73579663 ps
CPU time 2.27 seconds
Started Apr 23 02:46:19 PM PDT 24
Finished Apr 23 02:46:22 PM PDT 24
Peak memory 206712 kb
Host smart-db9d4978-d44a-4a22-9466-deeb857b795b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029453436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2029453436
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.114004602
Short name T944
Test name
Test status
Simulation time 31427948 ps
CPU time 0.87 seconds
Started Apr 23 02:46:45 PM PDT 24
Finished Apr 23 02:46:46 PM PDT 24
Peak memory 206612 kb
Host smart-930bfd5c-4699-4e84-845a-384f5f170e14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114004602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.114004602
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3991258753
Short name T912
Test name
Test status
Simulation time 136193158 ps
CPU time 0.86 seconds
Started Apr 23 02:46:44 PM PDT 24
Finished Apr 23 02:46:45 PM PDT 24
Peak memory 206416 kb
Host smart-71c0deba-d87f-433c-b826-de20b514d698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991258753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3991258753
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.846599878
Short name T948
Test name
Test status
Simulation time 43233979 ps
CPU time 0.84 seconds
Started Apr 23 02:46:44 PM PDT 24
Finished Apr 23 02:46:46 PM PDT 24
Peak memory 206420 kb
Host smart-eeee2b31-5726-438f-95ec-2c12477eda76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846599878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.846599878
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2926233039
Short name T882
Test name
Test status
Simulation time 21181738 ps
CPU time 0.85 seconds
Started Apr 23 02:46:43 PM PDT 24
Finished Apr 23 02:46:45 PM PDT 24
Peak memory 206620 kb
Host smart-c996643b-0571-4bac-8a37-2b2de4c95c55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926233039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2926233039
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2042506665
Short name T933
Test name
Test status
Simulation time 31133357 ps
CPU time 0.83 seconds
Started Apr 23 02:46:42 PM PDT 24
Finished Apr 23 02:46:44 PM PDT 24
Peak memory 206448 kb
Host smart-e3e1c474-c5a4-49c6-89fd-ceddc99f76b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042506665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2042506665
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1397672254
Short name T893
Test name
Test status
Simulation time 14190792 ps
CPU time 0.88 seconds
Started Apr 23 02:46:49 PM PDT 24
Finished Apr 23 02:46:51 PM PDT 24
Peak memory 206556 kb
Host smart-2ca0d309-7a39-40c1-848e-41d0f0d09f97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397672254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1397672254
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2426833795
Short name T848
Test name
Test status
Simulation time 17058429 ps
CPU time 0.94 seconds
Started Apr 23 02:46:42 PM PDT 24
Finished Apr 23 02:46:44 PM PDT 24
Peak memory 206620 kb
Host smart-f1d6143d-3f2c-4cd7-b698-ef9387218b2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426833795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2426833795
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3831083799
Short name T957
Test name
Test status
Simulation time 12157332 ps
CPU time 0.85 seconds
Started Apr 23 02:46:48 PM PDT 24
Finished Apr 23 02:46:49 PM PDT 24
Peak memory 206612 kb
Host smart-f6782160-23a2-4a75-94c8-daa82387b240
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831083799 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3831083799
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1337754091
Short name T881
Test name
Test status
Simulation time 16750864 ps
CPU time 0.8 seconds
Started Apr 23 02:46:44 PM PDT 24
Finished Apr 23 02:46:45 PM PDT 24
Peak memory 206384 kb
Host smart-809b71bb-79c5-4f6b-b3a6-384533c02a2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337754091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1337754091
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2279691437
Short name T971
Test name
Test status
Simulation time 57645269 ps
CPU time 0.86 seconds
Started Apr 23 02:46:46 PM PDT 24
Finished Apr 23 02:46:47 PM PDT 24
Peak memory 206620 kb
Host smart-371a7b79-bf72-48ee-ba05-54e3bc5eb913
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279691437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2279691437
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2147285506
Short name T877
Test name
Test status
Simulation time 226688454 ps
CPU time 1.53 seconds
Started Apr 23 02:46:22 PM PDT 24
Finished Apr 23 02:46:24 PM PDT 24
Peak memory 217596 kb
Host smart-3f471802-cb06-4140-b02c-f25e962b4204
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147285506 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2147285506
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1802531455
Short name T888
Test name
Test status
Simulation time 14313675 ps
CPU time 0.87 seconds
Started Apr 23 02:46:27 PM PDT 24
Finished Apr 23 02:46:28 PM PDT 24
Peak memory 206640 kb
Host smart-ef82da36-32f1-4e79-8910-063a2144987d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802531455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1802531455
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1343225701
Short name T967
Test name
Test status
Simulation time 109974565 ps
CPU time 0.8 seconds
Started Apr 23 02:46:24 PM PDT 24
Finished Apr 23 02:46:25 PM PDT 24
Peak memory 206468 kb
Host smart-75ab1939-9f33-4b44-8349-4e24a2eff097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343225701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1343225701
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.780864108
Short name T230
Test name
Test status
Simulation time 64857179 ps
CPU time 1.47 seconds
Started Apr 23 02:46:27 PM PDT 24
Finished Apr 23 02:46:29 PM PDT 24
Peak memory 206648 kb
Host smart-f16d2739-490c-4a0f-a297-0e1773bbf2d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780864108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.780864108
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3110487960
Short name T934
Test name
Test status
Simulation time 97638833 ps
CPU time 1.67 seconds
Started Apr 23 02:46:23 PM PDT 24
Finished Apr 23 02:46:25 PM PDT 24
Peak memory 214848 kb
Host smart-6f1966c5-ae5c-4850-bb8e-68ee2d754d42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110487960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3110487960
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.763717607
Short name T939
Test name
Test status
Simulation time 196350836 ps
CPU time 2.41 seconds
Started Apr 23 02:46:22 PM PDT 24
Finished Apr 23 02:46:25 PM PDT 24
Peak memory 206620 kb
Host smart-dc72e7dd-bbb3-4563-aa41-e3c2baa553d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763717607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.763717607
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3836270668
Short name T889
Test name
Test status
Simulation time 93008366 ps
CPU time 1.21 seconds
Started Apr 23 02:46:20 PM PDT 24
Finished Apr 23 02:46:22 PM PDT 24
Peak memory 214988 kb
Host smart-6b98a03a-8644-4023-89db-94af0bcdb976
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836270668 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3836270668
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3174391209
Short name T243
Test name
Test status
Simulation time 12209987 ps
CPU time 0.84 seconds
Started Apr 23 02:46:20 PM PDT 24
Finished Apr 23 02:46:22 PM PDT 24
Peak memory 206604 kb
Host smart-77b30d36-86bd-48c6-86ac-553c56f17ac6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174391209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3174391209
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2378819020
Short name T855
Test name
Test status
Simulation time 12477854 ps
CPU time 0.88 seconds
Started Apr 23 02:46:23 PM PDT 24
Finished Apr 23 02:46:24 PM PDT 24
Peak memory 206584 kb
Host smart-cf465358-f6ee-44d8-a010-28537ca3a6e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378819020 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2378819020
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3323364528
Short name T229
Test name
Test status
Simulation time 57894047 ps
CPU time 1.42 seconds
Started Apr 23 02:46:21 PM PDT 24
Finished Apr 23 02:46:23 PM PDT 24
Peak memory 206660 kb
Host smart-be6d6c18-e095-4c07-b55a-db430d77ccd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323364528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3323364528
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3726885630
Short name T947
Test name
Test status
Simulation time 85953267 ps
CPU time 2.89 seconds
Started Apr 23 02:46:22 PM PDT 24
Finished Apr 23 02:46:25 PM PDT 24
Peak memory 215036 kb
Host smart-db08bde1-e863-40b0-9484-4489303bb39d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726885630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3726885630
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.4176124620
Short name T859
Test name
Test status
Simulation time 68960279 ps
CPU time 1.99 seconds
Started Apr 23 02:46:22 PM PDT 24
Finished Apr 23 02:46:25 PM PDT 24
Peak memory 214884 kb
Host smart-4049d5d3-161b-4195-8326-7bb5b59e8220
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176124620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.4176124620
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2839219367
Short name T845
Test name
Test status
Simulation time 23694894 ps
CPU time 1.22 seconds
Started Apr 23 02:46:24 PM PDT 24
Finished Apr 23 02:46:26 PM PDT 24
Peak memory 214944 kb
Host smart-edc59b2d-44ba-40bd-8d2c-142d9cbee27e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839219367 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2839219367
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2663990380
Short name T224
Test name
Test status
Simulation time 28730009 ps
CPU time 0.82 seconds
Started Apr 23 02:46:26 PM PDT 24
Finished Apr 23 02:46:28 PM PDT 24
Peak memory 206436 kb
Host smart-ab7aa218-60fe-4de1-8f57-3c6fb334f6a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663990380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2663990380
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2517758330
Short name T964
Test name
Test status
Simulation time 12236022 ps
CPU time 0.82 seconds
Started Apr 23 02:46:20 PM PDT 24
Finished Apr 23 02:46:22 PM PDT 24
Peak memory 206564 kb
Host smart-d3a69aca-6e72-410d-9613-a3ba1733ff87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517758330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2517758330
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2687554482
Short name T879
Test name
Test status
Simulation time 41402710 ps
CPU time 1.57 seconds
Started Apr 23 02:46:24 PM PDT 24
Finished Apr 23 02:46:27 PM PDT 24
Peak memory 206620 kb
Host smart-34ef0408-e479-4b79-ac0d-3c859a9803ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687554482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2687554482
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1472413604
Short name T970
Test name
Test status
Simulation time 63496713 ps
CPU time 1.9 seconds
Started Apr 23 02:46:23 PM PDT 24
Finished Apr 23 02:46:25 PM PDT 24
Peak memory 214864 kb
Host smart-c66dd4d8-ee13-4c20-a4a7-cd09daf9300e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472413604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1472413604
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.472726177
Short name T868
Test name
Test status
Simulation time 304060081 ps
CPU time 2.68 seconds
Started Apr 23 02:46:24 PM PDT 24
Finished Apr 23 02:46:27 PM PDT 24
Peak memory 206656 kb
Host smart-ba5ccda2-1b13-4e7c-968d-89395b19f8c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472726177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.472726177
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3626755086
Short name T969
Test name
Test status
Simulation time 24789464 ps
CPU time 1.2 seconds
Started Apr 23 02:46:25 PM PDT 24
Finished Apr 23 02:46:27 PM PDT 24
Peak memory 214932 kb
Host smart-dec743f3-dfcf-4df7-bc37-0d402bcd97ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626755086 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3626755086
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.802932781
Short name T242
Test name
Test status
Simulation time 45551403 ps
CPU time 0.92 seconds
Started Apr 23 02:46:24 PM PDT 24
Finished Apr 23 02:46:26 PM PDT 24
Peak memory 206616 kb
Host smart-bd52bb8b-c47a-4f85-b438-77dfae3c5fa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802932781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.802932781
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.176592953
Short name T851
Test name
Test status
Simulation time 16302419 ps
CPU time 0.9 seconds
Started Apr 23 02:46:24 PM PDT 24
Finished Apr 23 02:46:25 PM PDT 24
Peak memory 206616 kb
Host smart-53c6ec30-b227-4a88-96a6-fa5543992165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176592953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.176592953
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1554684106
Short name T952
Test name
Test status
Simulation time 31670120 ps
CPU time 1.37 seconds
Started Apr 23 02:46:24 PM PDT 24
Finished Apr 23 02:46:26 PM PDT 24
Peak memory 206652 kb
Host smart-0cdfc5bc-132a-4508-90d0-2e19ae64bef0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554684106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1554684106
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1991790647
Short name T887
Test name
Test status
Simulation time 539104344 ps
CPU time 3.31 seconds
Started Apr 23 02:46:24 PM PDT 24
Finished Apr 23 02:46:28 PM PDT 24
Peak memory 214936 kb
Host smart-81fe4822-374d-4be7-9022-b6c9130c0a1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991790647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1991790647
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4282360814
Short name T943
Test name
Test status
Simulation time 142980059 ps
CPU time 1.95 seconds
Started Apr 23 02:46:24 PM PDT 24
Finished Apr 23 02:46:27 PM PDT 24
Peak memory 206664 kb
Host smart-0f30fa1c-535a-413b-9cf7-f225c50aa6fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282360814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.4282360814
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4164379682
Short name T920
Test name
Test status
Simulation time 20347867 ps
CPU time 1.13 seconds
Started Apr 23 02:46:26 PM PDT 24
Finished Apr 23 02:46:27 PM PDT 24
Peak memory 214856 kb
Host smart-28a85a35-8378-4697-91f5-fb132e0bf614
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164379682 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.4164379682
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1476084436
Short name T233
Test name
Test status
Simulation time 37144902 ps
CPU time 0.87 seconds
Started Apr 23 02:46:26 PM PDT 24
Finished Apr 23 02:46:27 PM PDT 24
Peak memory 206464 kb
Host smart-35fcc38e-e3bf-4e87-87af-35d3ee013b66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476084436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1476084436
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2932344006
Short name T874
Test name
Test status
Simulation time 24173310 ps
CPU time 0.83 seconds
Started Apr 23 02:46:24 PM PDT 24
Finished Apr 23 02:46:25 PM PDT 24
Peak memory 206604 kb
Host smart-6026a054-1538-4207-ac71-0c3108ccc553
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932344006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2932344006
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1024298906
Short name T956
Test name
Test status
Simulation time 39002469 ps
CPU time 1.45 seconds
Started Apr 23 02:46:24 PM PDT 24
Finished Apr 23 02:46:26 PM PDT 24
Peak memory 206600 kb
Host smart-80628e6e-ff02-433f-a432-a1466908e294
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024298906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1024298906
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1785386750
Short name T908
Test name
Test status
Simulation time 56054598 ps
CPU time 1.75 seconds
Started Apr 23 02:46:25 PM PDT 24
Finished Apr 23 02:46:27 PM PDT 24
Peak memory 214936 kb
Host smart-64c6eca8-0f0d-45f9-9cf2-fa896c397a83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785386750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1785386750
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3105585886
Short name T919
Test name
Test status
Simulation time 106250991 ps
CPU time 1.46 seconds
Started Apr 23 02:46:24 PM PDT 24
Finished Apr 23 02:46:26 PM PDT 24
Peak memory 206600 kb
Host smart-6f176466-f986-4e74-ba2e-51ea88fe92f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105585886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3105585886
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_disable.1070775644
Short name T580
Test name
Test status
Simulation time 32152443 ps
CPU time 0.85 seconds
Started Apr 23 02:07:53 PM PDT 24
Finished Apr 23 02:07:55 PM PDT 24
Peak memory 216472 kb
Host smart-2e39d2f0-11fe-4844-ac96-bbe6ebb68bd3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070775644 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1070775644
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.3453229985
Short name T108
Test name
Test status
Simulation time 25193196 ps
CPU time 1.32 seconds
Started Apr 23 02:07:54 PM PDT 24
Finished Apr 23 02:07:56 PM PDT 24
Peak memory 224368 kb
Host smart-9033bdc6-dfec-49ae-a7de-09dffd553cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453229985 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3453229985
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.1539494294
Short name T841
Test name
Test status
Simulation time 71245785 ps
CPU time 0.85 seconds
Started Apr 23 02:07:51 PM PDT 24
Finished Apr 23 02:07:53 PM PDT 24
Peak memory 215480 kb
Host smart-3f575000-f06d-4ddf-92ab-cf929d4912aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539494294 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1539494294
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_smoke.2802814743
Short name T463
Test name
Test status
Simulation time 22215740 ps
CPU time 0.9 seconds
Started Apr 23 02:07:51 PM PDT 24
Finished Apr 23 02:07:52 PM PDT 24
Peak memory 215528 kb
Host smart-49307612-ad47-4280-b05c-f759dc6d3679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802814743 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2802814743
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3579735802
Short name T667
Test name
Test status
Simulation time 239187344 ps
CPU time 1.95 seconds
Started Apr 23 02:07:51 PM PDT 24
Finished Apr 23 02:07:53 PM PDT 24
Peak memory 219744 kb
Host smart-958d45f9-14fd-4635-b217-1442d0522658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579735802 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3579735802
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.4037342039
Short name T582
Test name
Test status
Simulation time 42331725073 ps
CPU time 961.64 seconds
Started Apr 23 02:07:54 PM PDT 24
Finished Apr 23 02:23:56 PM PDT 24
Peak memory 219260 kb
Host smart-ab37df33-304a-4e34-ae05-097957d08679
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037342039 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.4037342039
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.961446921
Short name T268
Test name
Test status
Simulation time 44995931 ps
CPU time 1.24 seconds
Started Apr 23 02:07:57 PM PDT 24
Finished Apr 23 02:07:59 PM PDT 24
Peak memory 215800 kb
Host smart-94db5ab6-3988-493e-bdda-b74c74df4988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961446921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.961446921
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.4105667645
Short name T676
Test name
Test status
Simulation time 37101090 ps
CPU time 0.83 seconds
Started Apr 23 02:07:57 PM PDT 24
Finished Apr 23 02:07:59 PM PDT 24
Peak memory 207136 kb
Host smart-38da3836-65e1-443b-9054-d40f1a3d018e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105667645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.4105667645
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3577792546
Short name T374
Test name
Test status
Simulation time 32279306 ps
CPU time 1.08 seconds
Started Apr 23 02:08:01 PM PDT 24
Finished Apr 23 02:08:03 PM PDT 24
Peak memory 218436 kb
Host smart-bf3ddfef-f90d-4c54-8540-6d22d7082ce9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577792546 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3577792546
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.3278000555
Short name T770
Test name
Test status
Simulation time 44962878 ps
CPU time 0.82 seconds
Started Apr 23 02:07:55 PM PDT 24
Finished Apr 23 02:07:56 PM PDT 24
Peak memory 218296 kb
Host smart-13e5d00a-d80c-4cb3-92e7-600b396126c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278000555 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3278000555
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.1553927961
Short name T324
Test name
Test status
Simulation time 64704173 ps
CPU time 1.64 seconds
Started Apr 23 02:07:58 PM PDT 24
Finished Apr 23 02:08:00 PM PDT 24
Peak memory 218632 kb
Host smart-8d5b1398-a4a0-451d-9153-0a0718ae4b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553927961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1553927961
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1433091432
Short name T821
Test name
Test status
Simulation time 30542867 ps
CPU time 0.89 seconds
Started Apr 23 02:07:57 PM PDT 24
Finished Apr 23 02:07:59 PM PDT 24
Peak memory 215856 kb
Host smart-bdfd76c3-3387-460f-9eae-fa513f9d6808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433091432 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1433091432
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.2588454457
Short name T663
Test name
Test status
Simulation time 66017572 ps
CPU time 0.98 seconds
Started Apr 23 02:07:56 PM PDT 24
Finished Apr 23 02:07:58 PM PDT 24
Peak memory 207288 kb
Host smart-53261e3b-03e5-4af2-9033-62998036240e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588454457 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2588454457
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3591771587
Short name T54
Test name
Test status
Simulation time 2010933644 ps
CPU time 8.17 seconds
Started Apr 23 02:07:56 PM PDT 24
Finished Apr 23 02:08:05 PM PDT 24
Peak memory 241144 kb
Host smart-6d3f7c93-d6f6-452f-b9af-44816a903759
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591771587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3591771587
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.4139591617
Short name T699
Test name
Test status
Simulation time 15228075 ps
CPU time 1.03 seconds
Started Apr 23 02:07:58 PM PDT 24
Finished Apr 23 02:07:59 PM PDT 24
Peak memory 215552 kb
Host smart-361dce48-819f-490e-bf92-ae5c379308d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139591617 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.4139591617
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1153210296
Short name T453
Test name
Test status
Simulation time 485477891 ps
CPU time 5.16 seconds
Started Apr 23 02:07:57 PM PDT 24
Finished Apr 23 02:08:03 PM PDT 24
Peak memory 216516 kb
Host smart-af14e72b-3b26-4fd3-9eef-06cdace7d122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153210296 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1153210296
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.754258884
Short name T565
Test name
Test status
Simulation time 66918842619 ps
CPU time 438.11 seconds
Started Apr 23 02:07:57 PM PDT 24
Finished Apr 23 02:15:15 PM PDT 24
Peak memory 223856 kb
Host smart-c3deae56-4416-4fa3-9735-f1522e3f55e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754258884 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.754258884
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1636059222
Short name T158
Test name
Test status
Simulation time 70737531 ps
CPU time 1.29 seconds
Started Apr 23 02:08:29 PM PDT 24
Finished Apr 23 02:08:31 PM PDT 24
Peak memory 215796 kb
Host smart-a2c21ec9-41d9-472d-b184-562a75e60e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636059222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1636059222
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.3680803186
Short name T689
Test name
Test status
Simulation time 89076480 ps
CPU time 0.93 seconds
Started Apr 23 02:08:28 PM PDT 24
Finished Apr 23 02:08:30 PM PDT 24
Peak memory 215488 kb
Host smart-afd46f8b-21f1-48ba-9938-9b9d63d7a561
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680803186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3680803186
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.3718209456
Short name T641
Test name
Test status
Simulation time 56669400 ps
CPU time 0.83 seconds
Started Apr 23 02:08:25 PM PDT 24
Finished Apr 23 02:08:26 PM PDT 24
Peak memory 216088 kb
Host smart-b35c45e0-a07b-4e90-9748-3142b371806b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718209456 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3718209456
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.267949920
Short name T116
Test name
Test status
Simulation time 60809048 ps
CPU time 1.18 seconds
Started Apr 23 02:08:24 PM PDT 24
Finished Apr 23 02:08:26 PM PDT 24
Peak memory 217024 kb
Host smart-52d9f792-bba8-46f7-bea3-181e0d1e34e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267949920 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.267949920
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.2301413461
Short name T183
Test name
Test status
Simulation time 34977519 ps
CPU time 1.15 seconds
Started Apr 23 02:08:21 PM PDT 24
Finished Apr 23 02:08:23 PM PDT 24
Peak memory 220104 kb
Host smart-04ea8037-0c1b-4bf7-96c8-08605f233b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301413461 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2301413461
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1600018963
Short name T761
Test name
Test status
Simulation time 156283593 ps
CPU time 1.03 seconds
Started Apr 23 02:08:20 PM PDT 24
Finished Apr 23 02:08:21 PM PDT 24
Peak memory 217332 kb
Host smart-3bb72fa4-4ace-421b-9808-f0f96b8afd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600018963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1600018963
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1950598670
Short name T581
Test name
Test status
Simulation time 28944425 ps
CPU time 1.03 seconds
Started Apr 23 02:08:28 PM PDT 24
Finished Apr 23 02:08:30 PM PDT 24
Peak memory 224328 kb
Host smart-19d5bb67-1562-479a-951d-ad89a48f0ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950598670 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1950598670
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2524070440
Short name T705
Test name
Test status
Simulation time 31207437 ps
CPU time 0.98 seconds
Started Apr 23 02:08:23 PM PDT 24
Finished Apr 23 02:08:25 PM PDT 24
Peak memory 215500 kb
Host smart-d2d479bf-ee3f-4bf0-9e14-44a504d343e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524070440 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2524070440
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2404824073
Short name T647
Test name
Test status
Simulation time 585095987 ps
CPU time 4.44 seconds
Started Apr 23 02:08:21 PM PDT 24
Finished Apr 23 02:08:26 PM PDT 24
Peak memory 216924 kb
Host smart-1003a571-db34-4a8e-bcf2-884616db88db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404824073 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2404824073
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.4166515725
Short name T657
Test name
Test status
Simulation time 151122857067 ps
CPU time 1750.72 seconds
Started Apr 23 02:08:25 PM PDT 24
Finished Apr 23 02:37:36 PM PDT 24
Peak memory 225732 kb
Host smart-e36f47f3-6f1d-417d-a597-0b1be9c5c727
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166515725 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.4166515725
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.2172630858
Short name T522
Test name
Test status
Simulation time 24012629 ps
CPU time 1.1 seconds
Started Apr 23 02:10:29 PM PDT 24
Finished Apr 23 02:10:31 PM PDT 24
Peak memory 218572 kb
Host smart-d4293712-187d-457a-af43-fd2d38787257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172630858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2172630858
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.567504371
Short name T743
Test name
Test status
Simulation time 84887590 ps
CPU time 1.09 seconds
Started Apr 23 02:10:28 PM PDT 24
Finished Apr 23 02:10:30 PM PDT 24
Peak memory 215588 kb
Host smart-0b2674ff-9dc9-4788-a266-d9d4ac97b776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567504371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.567504371
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.242302791
Short name T58
Test name
Test status
Simulation time 78708281 ps
CPU time 1.27 seconds
Started Apr 23 02:10:30 PM PDT 24
Finished Apr 23 02:10:32 PM PDT 24
Peak memory 218704 kb
Host smart-f0a21ecc-9d28-4a09-890d-cafdb6c92cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242302791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.242302791
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3500570938
Short name T715
Test name
Test status
Simulation time 45575028 ps
CPU time 1.4 seconds
Started Apr 23 02:10:29 PM PDT 24
Finished Apr 23 02:10:32 PM PDT 24
Peak memory 218824 kb
Host smart-5fc870b7-6ccc-4ee6-bf11-d18415ad7e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500570938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3500570938
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1327160437
Short name T505
Test name
Test status
Simulation time 76372355 ps
CPU time 1.09 seconds
Started Apr 23 02:10:28 PM PDT 24
Finished Apr 23 02:10:30 PM PDT 24
Peak memory 217284 kb
Host smart-42092e86-50db-4fb9-ac9c-b4c78aefa23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327160437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1327160437
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.3021584366
Short name T739
Test name
Test status
Simulation time 106005049 ps
CPU time 1.96 seconds
Started Apr 23 02:10:29 PM PDT 24
Finished Apr 23 02:10:31 PM PDT 24
Peak memory 220120 kb
Host smart-14610dc2-822f-4d7c-95d5-1b7a5003f158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021584366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3021584366
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.2969019412
Short name T623
Test name
Test status
Simulation time 60971849 ps
CPU time 2.23 seconds
Started Apr 23 02:10:29 PM PDT 24
Finished Apr 23 02:10:33 PM PDT 24
Peak memory 218768 kb
Host smart-09ac85e4-3127-4fcb-b28e-bbc094c1a88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969019412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2969019412
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.1187328386
Short name T827
Test name
Test status
Simulation time 233015168 ps
CPU time 3.25 seconds
Started Apr 23 02:10:30 PM PDT 24
Finished Apr 23 02:10:34 PM PDT 24
Peak memory 217604 kb
Host smart-246ddbeb-947b-40fb-b890-e75dc482ab95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187328386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1187328386
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.3181838838
Short name T306
Test name
Test status
Simulation time 42039047 ps
CPU time 0.87 seconds
Started Apr 23 02:08:24 PM PDT 24
Finished Apr 23 02:08:25 PM PDT 24
Peak memory 215436 kb
Host smart-d387d5f5-1df7-4d3c-a412-112d3714e86c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181838838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3181838838
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.2852456712
Short name T190
Test name
Test status
Simulation time 9994651 ps
CPU time 0.88 seconds
Started Apr 23 02:08:29 PM PDT 24
Finished Apr 23 02:08:31 PM PDT 24
Peak memory 207436 kb
Host smart-32e41ef1-c593-4b48-952b-7974dd56c3fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852456712 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2852456712
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.2077537107
Short name T73
Test name
Test status
Simulation time 28704596 ps
CPU time 0.86 seconds
Started Apr 23 02:08:25 PM PDT 24
Finished Apr 23 02:08:26 PM PDT 24
Peak memory 215448 kb
Host smart-0d554b4b-340d-4f16-be1f-b15a3481a576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077537107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2077537107
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.653219768
Short name T595
Test name
Test status
Simulation time 51753242 ps
CPU time 1.41 seconds
Started Apr 23 02:08:24 PM PDT 24
Finished Apr 23 02:08:26 PM PDT 24
Peak memory 218628 kb
Host smart-2166035b-1122-4684-b694-f596aa8b540d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653219768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.653219768
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1556874042
Short name T382
Test name
Test status
Simulation time 23887173 ps
CPU time 0.97 seconds
Started Apr 23 02:08:20 PM PDT 24
Finished Apr 23 02:08:22 PM PDT 24
Peak memory 215640 kb
Host smart-ac373283-ce3d-4002-a54b-40e6d73ffdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556874042 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1556874042
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.395800368
Short name T342
Test name
Test status
Simulation time 18367703 ps
CPU time 1.01 seconds
Started Apr 23 02:08:27 PM PDT 24
Finished Apr 23 02:08:29 PM PDT 24
Peak memory 215552 kb
Host smart-2cd70a00-7bc9-4512-9a0f-824fcf108b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395800368 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.395800368
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1151525846
Short name T362
Test name
Test status
Simulation time 106224168 ps
CPU time 2.6 seconds
Started Apr 23 02:08:25 PM PDT 24
Finished Apr 23 02:08:28 PM PDT 24
Peak memory 218556 kb
Host smart-02ae6940-8e99-4e98-ac58-7d36c3d5f035
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151525846 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1151525846
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1969601013
Short name T38
Test name
Test status
Simulation time 245213398630 ps
CPU time 1477.28 seconds
Started Apr 23 02:08:28 PM PDT 24
Finished Apr 23 02:33:07 PM PDT 24
Peak memory 223912 kb
Host smart-31a0d49c-6195-493a-95b2-3b4fc4c2c780
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969601013 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1969601013
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.834608396
Short name T466
Test name
Test status
Simulation time 30318944 ps
CPU time 1.42 seconds
Started Apr 23 02:10:30 PM PDT 24
Finished Apr 23 02:10:32 PM PDT 24
Peak memory 217464 kb
Host smart-1e05df5d-ac2a-48e6-b572-ce11db01218f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834608396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.834608396
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.1703534901
Short name T353
Test name
Test status
Simulation time 66175836 ps
CPU time 1.22 seconds
Started Apr 23 02:10:33 PM PDT 24
Finished Apr 23 02:10:35 PM PDT 24
Peak memory 219728 kb
Host smart-c3db1df9-089f-4e58-a01f-3948e5482871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703534901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1703534901
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.4245673501
Short name T768
Test name
Test status
Simulation time 33978245 ps
CPU time 1.29 seconds
Started Apr 23 02:10:28 PM PDT 24
Finished Apr 23 02:10:31 PM PDT 24
Peak memory 217336 kb
Host smart-d9d58463-57c5-4038-b56c-0c066e51e0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245673501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.4245673501
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.329720232
Short name T406
Test name
Test status
Simulation time 53974929 ps
CPU time 1.31 seconds
Started Apr 23 02:10:29 PM PDT 24
Finished Apr 23 02:10:31 PM PDT 24
Peak memory 217288 kb
Host smart-f5331393-fc76-44e3-8d50-4f5ecb029d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329720232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.329720232
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.2938684857
Short name T603
Test name
Test status
Simulation time 78895475 ps
CPU time 1.35 seconds
Started Apr 23 02:10:30 PM PDT 24
Finished Apr 23 02:10:32 PM PDT 24
Peak memory 217332 kb
Host smart-43c3e5cb-3065-461c-95b1-c0a937273f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938684857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2938684857
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.2554860677
Short name T408
Test name
Test status
Simulation time 73534355 ps
CPU time 1.41 seconds
Started Apr 23 02:10:33 PM PDT 24
Finished Apr 23 02:10:35 PM PDT 24
Peak memory 219840 kb
Host smart-ced6291d-a0fd-4e43-a5a4-8b83564faa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554860677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2554860677
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.1243465455
Short name T771
Test name
Test status
Simulation time 397583511 ps
CPU time 2.34 seconds
Started Apr 23 02:10:30 PM PDT 24
Finished Apr 23 02:10:33 PM PDT 24
Peak memory 220168 kb
Host smart-7473832e-dbcb-47f8-ba77-0c9e2489f2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243465455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1243465455
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3790038038
Short name T728
Test name
Test status
Simulation time 81078403 ps
CPU time 1.25 seconds
Started Apr 23 02:10:34 PM PDT 24
Finished Apr 23 02:10:36 PM PDT 24
Peak memory 219380 kb
Host smart-71c1f43b-5004-44d8-8960-535fc2492d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790038038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3790038038
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.3601560052
Short name T457
Test name
Test status
Simulation time 28444253 ps
CPU time 1.14 seconds
Started Apr 23 02:08:28 PM PDT 24
Finished Apr 23 02:08:30 PM PDT 24
Peak memory 207008 kb
Host smart-4d74bd2d-b313-4b92-9073-dc159bc2e09c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601560052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3601560052
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.604622326
Short name T554
Test name
Test status
Simulation time 12517278 ps
CPU time 0.96 seconds
Started Apr 23 02:08:28 PM PDT 24
Finished Apr 23 02:08:30 PM PDT 24
Peak memory 215780 kb
Host smart-436f77bb-7399-4f91-97c6-6c1a43394311
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604622326 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.604622326
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3689386097
Short name T171
Test name
Test status
Simulation time 54716907 ps
CPU time 1.15 seconds
Started Apr 23 02:08:28 PM PDT 24
Finished Apr 23 02:08:30 PM PDT 24
Peak memory 217000 kb
Host smart-17297d60-a968-4ec2-ac75-4ad852452f03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689386097 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3689386097
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.1072260836
Short name T123
Test name
Test status
Simulation time 28970244 ps
CPU time 0.89 seconds
Started Apr 23 02:08:28 PM PDT 24
Finished Apr 23 02:08:30 PM PDT 24
Peak memory 218696 kb
Host smart-be4ab553-7cd9-4371-8359-75d2fa60d1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072260836 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1072260836
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_smoke.2337892729
Short name T325
Test name
Test status
Simulation time 27983270 ps
CPU time 0.98 seconds
Started Apr 23 02:08:29 PM PDT 24
Finished Apr 23 02:08:31 PM PDT 24
Peak memory 215504 kb
Host smart-4676aadf-b53b-4f13-8c19-36a4f9612308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337892729 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2337892729
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.200529520
Short name T668
Test name
Test status
Simulation time 128573580 ps
CPU time 3.18 seconds
Started Apr 23 02:08:29 PM PDT 24
Finished Apr 23 02:08:33 PM PDT 24
Peak memory 217176 kb
Host smart-537b780e-76f1-460c-8702-16509f756c5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200529520 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.200529520
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2658372687
Short name T475
Test name
Test status
Simulation time 24372830635 ps
CPU time 558.74 seconds
Started Apr 23 02:08:28 PM PDT 24
Finished Apr 23 02:17:47 PM PDT 24
Peak memory 217592 kb
Host smart-6c843def-a799-4bfb-8e8a-e00d9b5f017f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658372687 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2658372687
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.760789310
Short name T551
Test name
Test status
Simulation time 47988440 ps
CPU time 1.19 seconds
Started Apr 23 02:10:28 PM PDT 24
Finished Apr 23 02:10:31 PM PDT 24
Peak memory 217192 kb
Host smart-c21bf5af-57e1-4253-ae73-8b5801e16ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760789310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.760789310
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.1502021168
Short name T489
Test name
Test status
Simulation time 72818234 ps
CPU time 1.02 seconds
Started Apr 23 02:10:30 PM PDT 24
Finished Apr 23 02:10:32 PM PDT 24
Peak memory 217160 kb
Host smart-e8370da1-f14f-4062-93ba-25c119b23642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502021168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1502021168
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.80497446
Short name T726
Test name
Test status
Simulation time 61283965 ps
CPU time 1.47 seconds
Started Apr 23 02:10:35 PM PDT 24
Finished Apr 23 02:10:38 PM PDT 24
Peak memory 217272 kb
Host smart-f66823de-bf7e-434e-bebf-77e401aec872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80497446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.80497446
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.3443932643
Short name T596
Test name
Test status
Simulation time 46709537 ps
CPU time 1.07 seconds
Started Apr 23 02:10:30 PM PDT 24
Finished Apr 23 02:10:32 PM PDT 24
Peak memory 217112 kb
Host smart-f35cfefa-c6f4-4183-abf6-8c833f515144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443932643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3443932643
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.550682567
Short name T836
Test name
Test status
Simulation time 35992196 ps
CPU time 1.51 seconds
Started Apr 23 02:10:34 PM PDT 24
Finished Apr 23 02:10:37 PM PDT 24
Peak memory 217276 kb
Host smart-fb08f4d9-d723-4d3e-b0c1-25f94b75c5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550682567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.550682567
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2077374975
Short name T555
Test name
Test status
Simulation time 100613302 ps
CPU time 1.57 seconds
Started Apr 23 02:10:33 PM PDT 24
Finished Apr 23 02:10:35 PM PDT 24
Peak memory 218896 kb
Host smart-6fa709f3-6e7b-48c9-88d0-aa2712ce3524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077374975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2077374975
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.2508382064
Short name T319
Test name
Test status
Simulation time 112329963 ps
CPU time 1.25 seconds
Started Apr 23 02:10:33 PM PDT 24
Finished Apr 23 02:10:35 PM PDT 24
Peak memory 217152 kb
Host smart-aa216594-5031-40cb-b54c-a18d8f4e65b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508382064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2508382064
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.3555358213
Short name T602
Test name
Test status
Simulation time 59978582 ps
CPU time 1.16 seconds
Started Apr 23 02:10:34 PM PDT 24
Finished Apr 23 02:10:37 PM PDT 24
Peak memory 218900 kb
Host smart-6aba7954-b31c-42f7-a4c9-506a348fe7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555358213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3555358213
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.3837108012
Short name T704
Test name
Test status
Simulation time 25530681 ps
CPU time 1.23 seconds
Started Apr 23 02:10:28 PM PDT 24
Finished Apr 23 02:10:30 PM PDT 24
Peak memory 217268 kb
Host smart-6e5d4f00-67a6-45af-a779-9e7bdab1104c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837108012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3837108012
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2436745141
Short name T18
Test name
Test status
Simulation time 37376461 ps
CPU time 1.44 seconds
Started Apr 23 02:10:30 PM PDT 24
Finished Apr 23 02:10:32 PM PDT 24
Peak memory 219788 kb
Host smart-883ed330-1cf3-4165-90ca-6c90de3708bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436745141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2436745141
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2431777556
Short name T151
Test name
Test status
Simulation time 45118044 ps
CPU time 1.26 seconds
Started Apr 23 02:08:28 PM PDT 24
Finished Apr 23 02:08:30 PM PDT 24
Peak memory 215900 kb
Host smart-01842df6-f8c0-4b75-b5d0-23eddc5874ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431777556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2431777556
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3448492001
Short name T669
Test name
Test status
Simulation time 43656164 ps
CPU time 0.87 seconds
Started Apr 23 02:08:30 PM PDT 24
Finished Apr 23 02:08:32 PM PDT 24
Peak memory 206964 kb
Host smart-7f5ce71d-c020-4060-8287-ed8507f3b934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448492001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3448492001
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.2038745118
Short name T722
Test name
Test status
Simulation time 39669528 ps
CPU time 0.85 seconds
Started Apr 23 02:08:34 PM PDT 24
Finished Apr 23 02:08:35 PM PDT 24
Peak memory 215600 kb
Host smart-b11ca9e7-6375-46ef-9c4a-9da1810bc76c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038745118 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2038745118
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.4291798066
Short name T111
Test name
Test status
Simulation time 74761318 ps
CPU time 1.13 seconds
Started Apr 23 02:08:34 PM PDT 24
Finished Apr 23 02:08:36 PM PDT 24
Peak memory 217096 kb
Host smart-3838f52c-ff43-4802-a09d-43e063c6cef9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291798066 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.4291798066
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.684478736
Short name T114
Test name
Test status
Simulation time 37838152 ps
CPU time 1.07 seconds
Started Apr 23 02:08:27 PM PDT 24
Finished Apr 23 02:08:29 PM PDT 24
Peak memory 220740 kb
Host smart-1298731e-5524-49d6-83df-fccc69cf2de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684478736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.684478736
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3961748629
Short name T470
Test name
Test status
Simulation time 95819672 ps
CPU time 1.42 seconds
Started Apr 23 02:08:29 PM PDT 24
Finished Apr 23 02:08:32 PM PDT 24
Peak memory 218832 kb
Host smart-56cfdeb6-c4cb-4226-b7a9-1bb64e9ec1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961748629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3961748629
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.461441495
Short name T367
Test name
Test status
Simulation time 17208252 ps
CPU time 1.05 seconds
Started Apr 23 02:08:26 PM PDT 24
Finished Apr 23 02:08:28 PM PDT 24
Peak memory 215524 kb
Host smart-a8f1f8b7-2b6f-493b-a8ff-3e11d86d7233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461441495 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.461441495
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3125217248
Short name T521
Test name
Test status
Simulation time 201148397 ps
CPU time 2.59 seconds
Started Apr 23 02:08:29 PM PDT 24
Finished Apr 23 02:08:32 PM PDT 24
Peak memory 217176 kb
Host smart-a8a8a5c3-a312-4460-8468-e75a02622880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125217248 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3125217248
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3165109849
Short name T206
Test name
Test status
Simulation time 62119128815 ps
CPU time 1311.72 seconds
Started Apr 23 02:08:28 PM PDT 24
Finished Apr 23 02:30:21 PM PDT 24
Peak memory 221764 kb
Host smart-562db12e-d54f-49d2-88fe-dd00daca28ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165109849 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3165109849
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.edn_genbits.1499514313
Short name T355
Test name
Test status
Simulation time 40865137 ps
CPU time 1.06 seconds
Started Apr 23 02:10:36 PM PDT 24
Finished Apr 23 02:10:38 PM PDT 24
Peak memory 217128 kb
Host smart-ac3dd197-6a71-432d-971f-3121c931b4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499514313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1499514313
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.594366554
Short name T660
Test name
Test status
Simulation time 169386052 ps
CPU time 1.27 seconds
Started Apr 23 02:10:31 PM PDT 24
Finished Apr 23 02:10:33 PM PDT 24
Peak memory 217364 kb
Host smart-b66a14c5-ffae-443f-8595-e94a3373d572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594366554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.594366554
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3626863700
Short name T458
Test name
Test status
Simulation time 37350443 ps
CPU time 1.26 seconds
Started Apr 23 02:10:33 PM PDT 24
Finished Apr 23 02:10:35 PM PDT 24
Peak memory 219876 kb
Host smart-5cb41272-6ca2-4296-8024-bffe7f50d894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626863700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3626863700
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.2083646241
Short name T483
Test name
Test status
Simulation time 78185585 ps
CPU time 1.29 seconds
Started Apr 23 02:10:36 PM PDT 24
Finished Apr 23 02:10:39 PM PDT 24
Peak memory 219676 kb
Host smart-adc8482f-f3de-42ce-8351-e3017485b49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083646241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2083646241
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.876850391
Short name T764
Test name
Test status
Simulation time 80617449 ps
CPU time 1.25 seconds
Started Apr 23 02:10:35 PM PDT 24
Finished Apr 23 02:10:37 PM PDT 24
Peak memory 218608 kb
Host smart-991f638d-a2a7-430b-a041-25017a3419e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876850391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.876850391
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.61010750
Short name T566
Test name
Test status
Simulation time 133869905 ps
CPU time 2.81 seconds
Started Apr 23 02:10:35 PM PDT 24
Finished Apr 23 02:10:39 PM PDT 24
Peak memory 219996 kb
Host smart-a79177a0-bb55-44b0-ad7d-447417bc716e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61010750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.61010750
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.3383745238
Short name T424
Test name
Test status
Simulation time 84986556 ps
CPU time 1.3 seconds
Started Apr 23 02:10:30 PM PDT 24
Finished Apr 23 02:10:33 PM PDT 24
Peak memory 217192 kb
Host smart-9428ebf0-82d5-49f2-9c5c-e72999a34b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383745238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3383745238
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert_test.4163460203
Short name T472
Test name
Test status
Simulation time 19601724 ps
CPU time 1 seconds
Started Apr 23 02:08:34 PM PDT 24
Finished Apr 23 02:08:35 PM PDT 24
Peak memory 206912 kb
Host smart-3960c92c-7a4a-4496-af23-025670e035eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163460203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.4163460203
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1121301414
Short name T460
Test name
Test status
Simulation time 24732503 ps
CPU time 1.01 seconds
Started Apr 23 02:08:37 PM PDT 24
Finished Apr 23 02:08:39 PM PDT 24
Peak memory 218480 kb
Host smart-0ac8f6ef-baac-438f-ad88-bb94a1a3339b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121301414 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1121301414
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3989441343
Short name T109
Test name
Test status
Simulation time 25315124 ps
CPU time 1.2 seconds
Started Apr 23 02:08:33 PM PDT 24
Finished Apr 23 02:08:35 PM PDT 24
Peak memory 220860 kb
Host smart-fb883a25-2450-4db3-b179-e70bfea7b719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989441343 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3989441343
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3840709602
Short name T528
Test name
Test status
Simulation time 67001913 ps
CPU time 1.85 seconds
Started Apr 23 02:08:34 PM PDT 24
Finished Apr 23 02:08:36 PM PDT 24
Peak memory 218596 kb
Host smart-f1f62bb0-2101-4cc0-bfb7-62d28f5b7279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840709602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3840709602
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.156932431
Short name T363
Test name
Test status
Simulation time 109222043 ps
CPU time 0.82 seconds
Started Apr 23 02:08:32 PM PDT 24
Finished Apr 23 02:08:33 PM PDT 24
Peak memory 215584 kb
Host smart-50700ca1-ecbb-44c6-9854-e32babcb1166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156932431 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.156932431
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2453847350
Short name T37
Test name
Test status
Simulation time 21095611 ps
CPU time 0.97 seconds
Started Apr 23 02:08:33 PM PDT 24
Finished Apr 23 02:08:35 PM PDT 24
Peak memory 215508 kb
Host smart-f4a71206-9abc-4392-90ad-ddcca901818d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453847350 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2453847350
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.254145407
Short name T51
Test name
Test status
Simulation time 596555240 ps
CPU time 2.97 seconds
Started Apr 23 02:08:33 PM PDT 24
Finished Apr 23 02:08:37 PM PDT 24
Peak memory 217440 kb
Host smart-3fbb7f21-520e-4dee-8913-990dd79af14a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254145407 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.254145407
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.373358201
Short name T39
Test name
Test status
Simulation time 37069462298 ps
CPU time 706.24 seconds
Started Apr 23 02:08:35 PM PDT 24
Finished Apr 23 02:20:22 PM PDT 24
Peak memory 217952 kb
Host smart-78dd5873-280f-46ef-a4cf-f742db3665b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373358201 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.373358201
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.478340429
Short name T217
Test name
Test status
Simulation time 47617824 ps
CPU time 1.45 seconds
Started Apr 23 02:10:33 PM PDT 24
Finished Apr 23 02:10:36 PM PDT 24
Peak memory 217144 kb
Host smart-1f0b78b2-b42c-476a-b767-9182988b220f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478340429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.478340429
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.4255463065
Short name T539
Test name
Test status
Simulation time 65620981 ps
CPU time 1.18 seconds
Started Apr 23 02:10:36 PM PDT 24
Finished Apr 23 02:10:38 PM PDT 24
Peak memory 218352 kb
Host smart-4d778daa-38cd-4e9b-b93b-fe5a428adedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255463065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.4255463065
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.2325774729
Short name T12
Test name
Test status
Simulation time 85414972 ps
CPU time 1.37 seconds
Started Apr 23 02:10:27 PM PDT 24
Finished Apr 23 02:10:29 PM PDT 24
Peak memory 220452 kb
Host smart-06764ad8-b218-4ac8-9b06-9b3020cbdf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325774729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2325774729
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.4158699492
Short name T497
Test name
Test status
Simulation time 84087427 ps
CPU time 1.33 seconds
Started Apr 23 02:10:33 PM PDT 24
Finished Apr 23 02:10:36 PM PDT 24
Peak memory 218448 kb
Host smart-24258f5f-3eb3-4b0a-8d80-c9b88ef7de7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158699492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.4158699492
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.2637520228
Short name T644
Test name
Test status
Simulation time 37618420 ps
CPU time 1.36 seconds
Started Apr 23 02:10:34 PM PDT 24
Finished Apr 23 02:10:37 PM PDT 24
Peak memory 217240 kb
Host smart-5bc72054-b706-441c-a091-698188250e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637520228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2637520228
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.3760403419
Short name T282
Test name
Test status
Simulation time 36775489 ps
CPU time 1.49 seconds
Started Apr 23 02:10:34 PM PDT 24
Finished Apr 23 02:10:37 PM PDT 24
Peak memory 218424 kb
Host smart-193f6efb-fd58-4a92-a430-55505ae9d814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760403419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3760403419
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1435032270
Short name T383
Test name
Test status
Simulation time 117439438 ps
CPU time 1.7 seconds
Started Apr 23 02:10:34 PM PDT 24
Finished Apr 23 02:10:37 PM PDT 24
Peak memory 219660 kb
Host smart-a1b8cc9d-32b0-4f13-a6b7-7faaef4d00fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435032270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1435032270
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.273182586
Short name T749
Test name
Test status
Simulation time 315273679 ps
CPU time 3.07 seconds
Started Apr 23 02:10:34 PM PDT 24
Finished Apr 23 02:10:38 PM PDT 24
Peak memory 218900 kb
Host smart-6ccb9c6f-1d5e-45e3-a909-53a6022b4724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273182586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.273182586
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.1592510885
Short name T527
Test name
Test status
Simulation time 44807341 ps
CPU time 1.48 seconds
Started Apr 23 02:10:34 PM PDT 24
Finished Apr 23 02:10:37 PM PDT 24
Peak memory 218208 kb
Host smart-74f31d89-9878-47c6-a26b-dcc9859594da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592510885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1592510885
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.2806225145
Short name T381
Test name
Test status
Simulation time 24599542 ps
CPU time 1.17 seconds
Started Apr 23 02:10:34 PM PDT 24
Finished Apr 23 02:10:36 PM PDT 24
Peak memory 217264 kb
Host smart-5caf4357-f474-4cc8-93b7-278d5aa67501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806225145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2806225145
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.530049290
Short name T254
Test name
Test status
Simulation time 28604158 ps
CPU time 1.24 seconds
Started Apr 23 02:08:40 PM PDT 24
Finished Apr 23 02:08:42 PM PDT 24
Peak memory 215928 kb
Host smart-d626b654-ae05-469e-af61-d2194dd88545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530049290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.530049290
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2144939961
Short name T506
Test name
Test status
Simulation time 38780011 ps
CPU time 0.87 seconds
Started Apr 23 02:08:35 PM PDT 24
Finished Apr 23 02:08:37 PM PDT 24
Peak memory 214944 kb
Host smart-56998946-a86a-4817-813d-c4d8636e0a06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144939961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2144939961
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.651929056
Short name T180
Test name
Test status
Simulation time 115747183 ps
CPU time 0.9 seconds
Started Apr 23 02:08:35 PM PDT 24
Finished Apr 23 02:08:37 PM PDT 24
Peak memory 216368 kb
Host smart-72bb5b35-da36-4ebd-85f8-c76e8d51ea44
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651929056 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.651929056
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.736230053
Short name T642
Test name
Test status
Simulation time 115406422 ps
CPU time 1.17 seconds
Started Apr 23 02:08:37 PM PDT 24
Finished Apr 23 02:08:39 PM PDT 24
Peak memory 218216 kb
Host smart-74cb8567-4519-4124-9a88-b388bdff3c03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736230053 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.736230053
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_genbits.2786379742
Short name T437
Test name
Test status
Simulation time 59132668 ps
CPU time 1.08 seconds
Started Apr 23 02:08:37 PM PDT 24
Finished Apr 23 02:08:38 PM PDT 24
Peak memory 218780 kb
Host smart-e003aca6-8b8e-4771-b70b-563b2aa03ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786379742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2786379742
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2706079466
Short name T535
Test name
Test status
Simulation time 21751043 ps
CPU time 1.15 seconds
Started Apr 23 02:08:35 PM PDT 24
Finished Apr 23 02:08:37 PM PDT 24
Peak memory 215744 kb
Host smart-36e51d4f-2d64-40f9-9eba-ae9446a1e157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706079466 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2706079466
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1583122633
Short name T785
Test name
Test status
Simulation time 53714296 ps
CPU time 0.98 seconds
Started Apr 23 02:08:34 PM PDT 24
Finished Apr 23 02:08:36 PM PDT 24
Peak memory 215480 kb
Host smart-b3382044-1b7a-4f28-b554-9574ebc568dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583122633 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1583122633
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1964514454
Short name T478
Test name
Test status
Simulation time 310991327 ps
CPU time 1.67 seconds
Started Apr 23 02:08:30 PM PDT 24
Finished Apr 23 02:08:32 PM PDT 24
Peak memory 217368 kb
Host smart-32b3915b-fcc6-49ab-aebc-c112854ce0a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964514454 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1964514454
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2907452071
Short name T540
Test name
Test status
Simulation time 50595834006 ps
CPU time 283.2 seconds
Started Apr 23 02:08:34 PM PDT 24
Finished Apr 23 02:13:18 PM PDT 24
Peak memory 218692 kb
Host smart-fb1baad3-4fd3-477e-a906-091c2077af16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907452071 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2907452071
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.401674094
Short name T283
Test name
Test status
Simulation time 104695703 ps
CPU time 1.37 seconds
Started Apr 23 02:10:34 PM PDT 24
Finished Apr 23 02:10:37 PM PDT 24
Peak memory 220224 kb
Host smart-846606d0-c9ff-4df5-968e-2a3acfa52d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401674094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.401674094
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.1985311891
Short name T573
Test name
Test status
Simulation time 49081781 ps
CPU time 1.16 seconds
Started Apr 23 02:10:33 PM PDT 24
Finished Apr 23 02:10:36 PM PDT 24
Peak memory 215552 kb
Host smart-a071adf2-3332-4c07-9887-f62fe0fbb3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985311891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1985311891
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.615147397
Short name T74
Test name
Test status
Simulation time 39682634 ps
CPU time 1.08 seconds
Started Apr 23 02:10:34 PM PDT 24
Finished Apr 23 02:10:37 PM PDT 24
Peak memory 217108 kb
Host smart-29884cd3-d39a-4654-9171-d5dfeb63437b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615147397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.615147397
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.1387867232
Short name T290
Test name
Test status
Simulation time 57285526 ps
CPU time 1.18 seconds
Started Apr 23 02:10:34 PM PDT 24
Finished Apr 23 02:10:37 PM PDT 24
Peak memory 218524 kb
Host smart-ec320b87-2fa0-4d48-b0b1-5040131304ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387867232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1387867232
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.4075177047
Short name T384
Test name
Test status
Simulation time 93928966 ps
CPU time 1.24 seconds
Started Apr 23 02:10:34 PM PDT 24
Finished Apr 23 02:10:37 PM PDT 24
Peak memory 219060 kb
Host smart-993f35bf-2bbf-4c92-9b59-ed648361bda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075177047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.4075177047
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.2461237532
Short name T516
Test name
Test status
Simulation time 45786120 ps
CPU time 1.81 seconds
Started Apr 23 02:10:35 PM PDT 24
Finished Apr 23 02:10:38 PM PDT 24
Peak memory 218584 kb
Host smart-9f4e5fca-156b-40c9-840a-b2f3c2a04191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461237532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2461237532
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.2139718507
Short name T615
Test name
Test status
Simulation time 81247929 ps
CPU time 1.35 seconds
Started Apr 23 02:10:35 PM PDT 24
Finished Apr 23 02:10:38 PM PDT 24
Peak memory 218780 kb
Host smart-876b5f3d-01a5-4890-8ab1-bd97eb309947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139718507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2139718507
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.3221103771
Short name T718
Test name
Test status
Simulation time 37863799 ps
CPU time 1.14 seconds
Started Apr 23 02:10:33 PM PDT 24
Finished Apr 23 02:10:36 PM PDT 24
Peak memory 217068 kb
Host smart-e4cca225-2f25-4769-ac01-1ee12a8c2f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221103771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3221103771
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.3529753318
Short name T763
Test name
Test status
Simulation time 206009746 ps
CPU time 1.2 seconds
Started Apr 23 02:10:34 PM PDT 24
Finished Apr 23 02:10:37 PM PDT 24
Peak memory 218632 kb
Host smart-fde939a6-f85c-4528-8194-5d59b2cc695d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529753318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3529753318
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.3801494977
Short name T440
Test name
Test status
Simulation time 55537125 ps
CPU time 1.28 seconds
Started Apr 23 02:10:37 PM PDT 24
Finished Apr 23 02:10:40 PM PDT 24
Peak memory 218496 kb
Host smart-5ebed168-0b1a-4149-996e-42357c312fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801494977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3801494977
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3295712354
Short name T29
Test name
Test status
Simulation time 130114289 ps
CPU time 1.17 seconds
Started Apr 23 02:08:36 PM PDT 24
Finished Apr 23 02:08:37 PM PDT 24
Peak memory 215940 kb
Host smart-33d7b784-af6f-40ab-9797-df5232b49191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295712354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3295712354
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1823871272
Short name T307
Test name
Test status
Simulation time 43965141 ps
CPU time 0.89 seconds
Started Apr 23 02:08:39 PM PDT 24
Finished Apr 23 02:08:41 PM PDT 24
Peak memory 215032 kb
Host smart-049dd1f2-033b-4ec1-883b-81f5456754ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823871272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1823871272
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1669012036
Short name T106
Test name
Test status
Simulation time 103888393 ps
CPU time 1.07 seconds
Started Apr 23 02:08:39 PM PDT 24
Finished Apr 23 02:08:41 PM PDT 24
Peak memory 219732 kb
Host smart-9e358e06-eebb-43b5-b204-c7f870bae123
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669012036 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1669012036
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.2921901983
Short name T696
Test name
Test status
Simulation time 53820828 ps
CPU time 1.34 seconds
Started Apr 23 02:08:39 PM PDT 24
Finished Apr 23 02:08:41 PM PDT 24
Peak memory 225836 kb
Host smart-6ce2d436-2d8d-4255-b4b4-6dc52ea64fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921901983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2921901983
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2900229163
Short name T662
Test name
Test status
Simulation time 61518615 ps
CPU time 1.31 seconds
Started Apr 23 02:08:35 PM PDT 24
Finished Apr 23 02:08:37 PM PDT 24
Peak memory 217200 kb
Host smart-406c8673-bd3e-4ff6-93a1-46fe921f3113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900229163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2900229163
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1850630237
Short name T322
Test name
Test status
Simulation time 69772381 ps
CPU time 0.89 seconds
Started Apr 23 02:08:34 PM PDT 24
Finished Apr 23 02:08:36 PM PDT 24
Peak memory 215476 kb
Host smart-b8d904ac-07eb-4b61-ac3d-b3c0b8b38568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850630237 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1850630237
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1218272240
Short name T578
Test name
Test status
Simulation time 19169713 ps
CPU time 1.05 seconds
Started Apr 23 02:08:34 PM PDT 24
Finished Apr 23 02:08:36 PM PDT 24
Peak memory 215508 kb
Host smart-0fe1e806-8395-4a4c-b4e9-492b222389f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218272240 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1218272240
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1353571996
Short name T513
Test name
Test status
Simulation time 144646920 ps
CPU time 3.3 seconds
Started Apr 23 02:08:33 PM PDT 24
Finished Apr 23 02:08:37 PM PDT 24
Peak memory 218380 kb
Host smart-940fea49-399b-4b2c-b33e-ac0e40726007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353571996 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1353571996
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2484909322
Short name T786
Test name
Test status
Simulation time 49319563080 ps
CPU time 617.84 seconds
Started Apr 23 02:08:37 PM PDT 24
Finished Apr 23 02:18:55 PM PDT 24
Peak memory 218276 kb
Host smart-b12f56d5-a7a4-4110-afdc-092bdeb44040
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484909322 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2484909322
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.3491106255
Short name T41
Test name
Test status
Simulation time 59269707 ps
CPU time 1.37 seconds
Started Apr 23 02:10:38 PM PDT 24
Finished Apr 23 02:10:40 PM PDT 24
Peak memory 219156 kb
Host smart-6b734dca-6b1e-45a5-ae90-2a8f82d834d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491106255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3491106255
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.214627946
Short name T813
Test name
Test status
Simulation time 65049240 ps
CPU time 1.08 seconds
Started Apr 23 02:10:37 PM PDT 24
Finished Apr 23 02:10:40 PM PDT 24
Peak memory 219944 kb
Host smart-ea101e29-2410-404e-904c-98ce5e42c11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214627946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.214627946
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.4285531210
Short name T433
Test name
Test status
Simulation time 52881825 ps
CPU time 1.88 seconds
Started Apr 23 02:10:33 PM PDT 24
Finished Apr 23 02:10:37 PM PDT 24
Peak memory 218460 kb
Host smart-dc72fdef-ad9e-4cea-87e3-1515e63f95cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285531210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.4285531210
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2976580330
Short name T305
Test name
Test status
Simulation time 51784063 ps
CPU time 1.53 seconds
Started Apr 23 02:10:37 PM PDT 24
Finished Apr 23 02:10:40 PM PDT 24
Peak memory 218712 kb
Host smart-521da844-659b-4e3e-bbdf-6e5e78d6698c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976580330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2976580330
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.2399232301
Short name T286
Test name
Test status
Simulation time 141870353 ps
CPU time 1.64 seconds
Started Apr 23 02:10:38 PM PDT 24
Finished Apr 23 02:10:41 PM PDT 24
Peak memory 218640 kb
Host smart-05803170-53bd-453d-872b-3156c502abee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399232301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2399232301
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3495302575
Short name T348
Test name
Test status
Simulation time 52880643 ps
CPU time 1.28 seconds
Started Apr 23 02:10:36 PM PDT 24
Finished Apr 23 02:10:38 PM PDT 24
Peak memory 217176 kb
Host smart-85bf57ea-7abb-4178-8b8b-5ebd593f9a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495302575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3495302575
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.139667272
Short name T654
Test name
Test status
Simulation time 81351617 ps
CPU time 1.3 seconds
Started Apr 23 02:10:35 PM PDT 24
Finished Apr 23 02:10:38 PM PDT 24
Peak memory 217380 kb
Host smart-9798eb3b-427e-4757-98f6-6f77eb041290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139667272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.139667272
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.75750297
Short name T341
Test name
Test status
Simulation time 52491775 ps
CPU time 1.27 seconds
Started Apr 23 02:10:36 PM PDT 24
Finished Apr 23 02:10:39 PM PDT 24
Peak memory 218672 kb
Host smart-4ed2ce78-ae32-4d89-bcd6-cac966b70756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75750297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.75750297
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.4059833676
Short name T288
Test name
Test status
Simulation time 54584254 ps
CPU time 2.02 seconds
Started Apr 23 02:10:40 PM PDT 24
Finished Apr 23 02:10:43 PM PDT 24
Peak memory 219148 kb
Host smart-d32e7009-8a44-4614-8ca0-72151f34e385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059833676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.4059833676
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.2106635182
Short name T428
Test name
Test status
Simulation time 42838956 ps
CPU time 1.28 seconds
Started Apr 23 02:10:40 PM PDT 24
Finished Apr 23 02:10:42 PM PDT 24
Peak memory 217384 kb
Host smart-257ac558-c300-4994-bb33-2aa8d77438bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106635182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2106635182
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1865587202
Short name T49
Test name
Test status
Simulation time 106412273 ps
CPU time 1.29 seconds
Started Apr 23 02:08:39 PM PDT 24
Finished Apr 23 02:08:40 PM PDT 24
Peak memory 215952 kb
Host smart-c9190fcd-7273-479d-aeea-245a601c37f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865587202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1865587202
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2898033183
Short name T451
Test name
Test status
Simulation time 31584651 ps
CPU time 0.95 seconds
Started Apr 23 02:08:39 PM PDT 24
Finished Apr 23 02:08:40 PM PDT 24
Peak memory 215104 kb
Host smart-b0a8e5f6-fb1d-436e-b3cd-0ab69533cfa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898033183 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2898033183
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.1183437467
Short name T143
Test name
Test status
Simulation time 40707719 ps
CPU time 0.86 seconds
Started Apr 23 02:08:37 PM PDT 24
Finished Apr 23 02:08:38 PM PDT 24
Peak memory 216456 kb
Host smart-be2c1b00-b1d9-4e3d-a97c-8eb0453a5e35
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183437467 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1183437467
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.526299501
Short name T680
Test name
Test status
Simulation time 57077858 ps
CPU time 0.93 seconds
Started Apr 23 02:08:39 PM PDT 24
Finished Apr 23 02:08:40 PM PDT 24
Peak memory 232604 kb
Host smart-ef7e14ad-0401-4756-b1bc-ffdd5b036ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526299501 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.526299501
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3362004503
Short name T298
Test name
Test status
Simulation time 130301115 ps
CPU time 2.36 seconds
Started Apr 23 02:08:38 PM PDT 24
Finished Apr 23 02:08:41 PM PDT 24
Peak memory 218444 kb
Host smart-fe7efc6b-9f9a-48ee-be50-a9a3439fd482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362004503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3362004503
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.698020024
Short name T542
Test name
Test status
Simulation time 36702950 ps
CPU time 0.87 seconds
Started Apr 23 02:08:38 PM PDT 24
Finished Apr 23 02:08:40 PM PDT 24
Peak memory 215892 kb
Host smart-6ced73ad-a04e-42d0-820a-6885ff382796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698020024 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.698020024
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2907490325
Short name T690
Test name
Test status
Simulation time 49007755 ps
CPU time 0.92 seconds
Started Apr 23 02:08:38 PM PDT 24
Finished Apr 23 02:08:39 PM PDT 24
Peak memory 215476 kb
Host smart-9ab4cb51-1144-4aa1-91d8-7731c86210db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907490325 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2907490325
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.818314818
Short name T552
Test name
Test status
Simulation time 135373585 ps
CPU time 2.45 seconds
Started Apr 23 02:08:36 PM PDT 24
Finished Apr 23 02:08:39 PM PDT 24
Peak memory 215564 kb
Host smart-3eb06369-bdb0-48af-b3bd-d31a729f95d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818314818 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.818314818
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2568853520
Short name T575
Test name
Test status
Simulation time 81388150825 ps
CPU time 1388.08 seconds
Started Apr 23 02:08:41 PM PDT 24
Finished Apr 23 02:31:50 PM PDT 24
Peak memory 226024 kb
Host smart-b718c289-c988-4597-afe5-85175d8dc320
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568853520 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2568853520
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.267587957
Short name T314
Test name
Test status
Simulation time 34116580 ps
CPU time 1.57 seconds
Started Apr 23 02:10:37 PM PDT 24
Finished Apr 23 02:10:40 PM PDT 24
Peak memory 218468 kb
Host smart-126e0c18-f6ed-4409-817f-d7e28f59a600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267587957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.267587957
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.1792951015
Short name T371
Test name
Test status
Simulation time 122787397 ps
CPU time 1.63 seconds
Started Apr 23 02:10:39 PM PDT 24
Finished Apr 23 02:10:42 PM PDT 24
Peak memory 218780 kb
Host smart-2c883b4a-1a13-4340-9b96-daaaf6d83067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792951015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1792951015
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.216021917
Short name T209
Test name
Test status
Simulation time 41047168 ps
CPU time 1.42 seconds
Started Apr 23 02:10:38 PM PDT 24
Finished Apr 23 02:10:41 PM PDT 24
Peak memory 215560 kb
Host smart-7a247231-839f-421f-a79a-6d9e443bf32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216021917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.216021917
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.637044358
Short name T19
Test name
Test status
Simulation time 63614340 ps
CPU time 1.36 seconds
Started Apr 23 02:10:37 PM PDT 24
Finished Apr 23 02:10:40 PM PDT 24
Peak memory 219876 kb
Host smart-c70d941b-59d3-4abd-8217-e0e185df0bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637044358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.637044358
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.3971071992
Short name T375
Test name
Test status
Simulation time 186768940 ps
CPU time 2.35 seconds
Started Apr 23 02:10:42 PM PDT 24
Finished Apr 23 02:10:45 PM PDT 24
Peak memory 219440 kb
Host smart-ee080ab4-e7f0-4886-b436-5bd96b9c21a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971071992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3971071992
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.197681743
Short name T583
Test name
Test status
Simulation time 109177530 ps
CPU time 1.32 seconds
Started Apr 23 02:10:40 PM PDT 24
Finished Apr 23 02:10:42 PM PDT 24
Peak memory 218696 kb
Host smart-03c435a0-2b70-4fe0-9fc9-83fccd073476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197681743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.197681743
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.3429098388
Short name T407
Test name
Test status
Simulation time 79653671 ps
CPU time 2.78 seconds
Started Apr 23 02:10:38 PM PDT 24
Finished Apr 23 02:10:42 PM PDT 24
Peak memory 220108 kb
Host smart-ce90b00f-6271-47e3-a0b0-b7d50c9b1c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429098388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3429098388
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.3772850866
Short name T501
Test name
Test status
Simulation time 28242335 ps
CPU time 1.56 seconds
Started Apr 23 02:10:38 PM PDT 24
Finished Apr 23 02:10:41 PM PDT 24
Peak memory 217204 kb
Host smart-76b1372d-0a40-4290-8de6-d2c897fd96c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772850866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3772850866
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3980715908
Short name T253
Test name
Test status
Simulation time 78956411 ps
CPU time 1.2 seconds
Started Apr 23 02:08:40 PM PDT 24
Finished Apr 23 02:08:42 PM PDT 24
Peak memory 215900 kb
Host smart-25be16cc-7c6b-4b36-b8f3-7655a52c3c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980715908 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3980715908
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.773067547
Short name T486
Test name
Test status
Simulation time 45916995 ps
CPU time 0.91 seconds
Started Apr 23 02:08:39 PM PDT 24
Finished Apr 23 02:08:40 PM PDT 24
Peak memory 215476 kb
Host smart-d8c1f6c3-035b-485e-9614-d23a805c802a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773067547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.773067547
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2001851607
Short name T791
Test name
Test status
Simulation time 14323760 ps
CPU time 0.91 seconds
Started Apr 23 02:08:42 PM PDT 24
Finished Apr 23 02:08:43 PM PDT 24
Peak memory 216352 kb
Host smart-84a5a4a1-0722-46bc-860f-a93eb4544d52
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001851607 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2001851607
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1046215813
Short name T416
Test name
Test status
Simulation time 25602656 ps
CPU time 1.38 seconds
Started Apr 23 02:08:42 PM PDT 24
Finished Apr 23 02:08:44 PM PDT 24
Peak memory 218472 kb
Host smart-9b39448e-19e0-4a00-b433-a04b6cf775c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046215813 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1046215813
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.3971206724
Short name T124
Test name
Test status
Simulation time 20074892 ps
CPU time 1.14 seconds
Started Apr 23 02:08:41 PM PDT 24
Finished Apr 23 02:08:43 PM PDT 24
Peak memory 218796 kb
Host smart-93f8d355-26e7-485c-ad23-8888c2474983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971206724 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3971206724
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.4209465775
Short name T380
Test name
Test status
Simulation time 43898067 ps
CPU time 1.37 seconds
Started Apr 23 02:08:40 PM PDT 24
Finished Apr 23 02:08:41 PM PDT 24
Peak memory 218204 kb
Host smart-e4258709-a08e-4b11-9c62-a86fff550394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209465775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.4209465775
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.918460448
Short name T544
Test name
Test status
Simulation time 27184232 ps
CPU time 0.86 seconds
Started Apr 23 02:08:37 PM PDT 24
Finished Apr 23 02:08:39 PM PDT 24
Peak memory 215836 kb
Host smart-210eb733-3c00-4be1-893a-db0fbbdaf6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918460448 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.918460448
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1409917102
Short name T733
Test name
Test status
Simulation time 85735304 ps
CPU time 0.94 seconds
Started Apr 23 02:08:40 PM PDT 24
Finished Apr 23 02:08:41 PM PDT 24
Peak memory 215592 kb
Host smart-26dfd8b7-5471-4111-b6ba-7edb76640493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409917102 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1409917102
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1752484209
Short name T531
Test name
Test status
Simulation time 101107758 ps
CPU time 2.54 seconds
Started Apr 23 02:08:36 PM PDT 24
Finished Apr 23 02:08:40 PM PDT 24
Peak memory 218500 kb
Host smart-f7ac26a9-27af-4fbf-977b-4df475b048a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752484209 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1752484209
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2943129692
Short name T200
Test name
Test status
Simulation time 208908248978 ps
CPU time 1239.31 seconds
Started Apr 23 02:08:36 PM PDT 24
Finished Apr 23 02:29:16 PM PDT 24
Peak memory 221804 kb
Host smart-e4fca828-3dd1-4a94-ba2e-86e62df6be21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943129692 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2943129692
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.2586367604
Short name T218
Test name
Test status
Simulation time 59917725 ps
CPU time 1.73 seconds
Started Apr 23 02:10:42 PM PDT 24
Finished Apr 23 02:10:44 PM PDT 24
Peak memory 218248 kb
Host smart-9ee42a19-f3e6-4fc7-949d-f62b25c31e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586367604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2586367604
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.1326572506
Short name T585
Test name
Test status
Simulation time 100532125 ps
CPU time 1.61 seconds
Started Apr 23 02:10:40 PM PDT 24
Finished Apr 23 02:10:42 PM PDT 24
Peak memory 218448 kb
Host smart-872d3f83-ad79-43a2-a044-8858d15b6a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326572506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1326572506
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.614091922
Short name T756
Test name
Test status
Simulation time 67895264 ps
CPU time 1.1 seconds
Started Apr 23 02:10:43 PM PDT 24
Finished Apr 23 02:10:44 PM PDT 24
Peak memory 219672 kb
Host smart-70240d33-6446-40eb-a8a6-b8e3c5ac616c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614091922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.614091922
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.925377955
Short name T828
Test name
Test status
Simulation time 49800513 ps
CPU time 1.48 seconds
Started Apr 23 02:10:42 PM PDT 24
Finished Apr 23 02:10:44 PM PDT 24
Peak memory 218436 kb
Host smart-c539c9b7-9f2f-4a69-a450-b7d84d033e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925377955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.925377955
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.2866770927
Short name T398
Test name
Test status
Simulation time 63018700 ps
CPU time 1.11 seconds
Started Apr 23 02:10:43 PM PDT 24
Finished Apr 23 02:10:45 PM PDT 24
Peak memory 217424 kb
Host smart-30cb1521-b420-4473-81d7-6262212750bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866770927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2866770927
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.192650409
Short name T420
Test name
Test status
Simulation time 51992165 ps
CPU time 1.23 seconds
Started Apr 23 02:10:41 PM PDT 24
Finished Apr 23 02:10:43 PM PDT 24
Peak memory 217408 kb
Host smart-9ce5197c-d964-427d-899f-9de42848911c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192650409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.192650409
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.3064859063
Short name T45
Test name
Test status
Simulation time 54169699 ps
CPU time 1.26 seconds
Started Apr 23 02:10:41 PM PDT 24
Finished Apr 23 02:10:43 PM PDT 24
Peak memory 220060 kb
Host smart-8c1a62e3-1a17-4bc1-bd12-4c15886b2e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064859063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3064859063
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.2913104506
Short name T691
Test name
Test status
Simulation time 35356118 ps
CPU time 1.34 seconds
Started Apr 23 02:10:46 PM PDT 24
Finished Apr 23 02:10:48 PM PDT 24
Peak memory 219868 kb
Host smart-224f84b0-2feb-4918-95ae-1b6918109b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913104506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2913104506
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1401167489
Short name T820
Test name
Test status
Simulation time 56894617 ps
CPU time 1.35 seconds
Started Apr 23 02:10:42 PM PDT 24
Finished Apr 23 02:10:44 PM PDT 24
Peak memory 218552 kb
Host smart-27eb09ae-e742-4709-bb6a-33a4c74c63f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401167489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1401167489
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.791319007
Short name T333
Test name
Test status
Simulation time 34973369 ps
CPU time 1.52 seconds
Started Apr 23 02:10:47 PM PDT 24
Finished Apr 23 02:10:49 PM PDT 24
Peak memory 217404 kb
Host smart-0e47396d-f54f-4874-a57f-5552344c3702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791319007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.791319007
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.985715374
Short name T262
Test name
Test status
Simulation time 50556603 ps
CPU time 1.23 seconds
Started Apr 23 02:08:42 PM PDT 24
Finished Apr 23 02:08:43 PM PDT 24
Peak memory 215896 kb
Host smart-696adc04-2487-410c-b28e-96a4bd938cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985715374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.985715374
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2440281004
Short name T618
Test name
Test status
Simulation time 26608469 ps
CPU time 0.89 seconds
Started Apr 23 02:08:41 PM PDT 24
Finished Apr 23 02:08:43 PM PDT 24
Peak memory 206880 kb
Host smart-c8de1ff2-8f67-428d-a0de-b165c5c9d5b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440281004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2440281004
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2028288050
Short name T56
Test name
Test status
Simulation time 11103619 ps
CPU time 0.86 seconds
Started Apr 23 02:08:45 PM PDT 24
Finished Apr 23 02:08:47 PM PDT 24
Peak memory 216624 kb
Host smart-02ac67aa-9778-4e83-a0d3-5c4eaa4efd45
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028288050 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2028288050
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.425239107
Short name T113
Test name
Test status
Simulation time 38188167 ps
CPU time 1.01 seconds
Started Apr 23 02:08:43 PM PDT 24
Finished Apr 23 02:08:45 PM PDT 24
Peak memory 219872 kb
Host smart-55b40e5b-7ab0-41d3-b3e3-00ef11d67a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425239107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.425239107
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2549187422
Short name T842
Test name
Test status
Simulation time 57825268 ps
CPU time 1.23 seconds
Started Apr 23 02:08:40 PM PDT 24
Finished Apr 23 02:08:42 PM PDT 24
Peak memory 219976 kb
Host smart-c9eba4ac-1cdf-44a4-a482-ed98a5202133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549187422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2549187422
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_smoke.2571049257
Short name T697
Test name
Test status
Simulation time 42270038 ps
CPU time 0.92 seconds
Started Apr 23 02:08:40 PM PDT 24
Finished Apr 23 02:08:41 PM PDT 24
Peak memory 215540 kb
Host smart-ce413ec3-219c-4770-9dfb-e1d78c79b263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571049257 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2571049257
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1916703796
Short name T68
Test name
Test status
Simulation time 639589150 ps
CPU time 2.51 seconds
Started Apr 23 02:08:41 PM PDT 24
Finished Apr 23 02:08:44 PM PDT 24
Peak memory 217388 kb
Host smart-441ff797-df87-4826-9e43-267e04b7e8a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916703796 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1916703796
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2362699179
Short name T198
Test name
Test status
Simulation time 16691450209 ps
CPU time 227.99 seconds
Started Apr 23 02:08:43 PM PDT 24
Finished Apr 23 02:12:31 PM PDT 24
Peak memory 218404 kb
Host smart-fdba73a6-8844-41ab-ac1c-e4ce15e6da26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362699179 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2362699179
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.3037628405
Short name T562
Test name
Test status
Simulation time 43447982 ps
CPU time 1.14 seconds
Started Apr 23 02:10:46 PM PDT 24
Finished Apr 23 02:10:48 PM PDT 24
Peak memory 219872 kb
Host smart-bb701081-a9e7-425a-90e7-e4b7feb7fe91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037628405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3037628405
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.2630884012
Short name T315
Test name
Test status
Simulation time 49223545 ps
CPU time 1.28 seconds
Started Apr 23 02:10:42 PM PDT 24
Finished Apr 23 02:10:44 PM PDT 24
Peak memory 218468 kb
Host smart-bda7bb2b-8d01-4912-a977-ec6f9dc9fd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630884012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2630884012
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.1310715082
Short name T82
Test name
Test status
Simulation time 90908289 ps
CPU time 1.26 seconds
Started Apr 23 02:10:39 PM PDT 24
Finished Apr 23 02:10:41 PM PDT 24
Peak memory 217136 kb
Host smart-95a9b889-766d-47f5-b063-d7d43f272092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310715082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1310715082
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.246531799
Short name T784
Test name
Test status
Simulation time 53576801 ps
CPU time 1.31 seconds
Started Apr 23 02:10:42 PM PDT 24
Finished Apr 23 02:10:44 PM PDT 24
Peak memory 218716 kb
Host smart-7b18143d-b6ac-4f68-9f9d-98fc34a3484c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246531799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.246531799
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.1422300081
Short name T304
Test name
Test status
Simulation time 99887781 ps
CPU time 1.4 seconds
Started Apr 23 02:10:39 PM PDT 24
Finished Apr 23 02:10:42 PM PDT 24
Peak memory 219052 kb
Host smart-262c1b07-38bc-4ae1-a1d8-5318aaaf8455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422300081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1422300081
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.3147416010
Short name T85
Test name
Test status
Simulation time 32386084 ps
CPU time 1.28 seconds
Started Apr 23 02:10:46 PM PDT 24
Finished Apr 23 02:10:49 PM PDT 24
Peak memory 215536 kb
Host smart-f9bc2465-846b-4469-95a3-d284fb2bf2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147416010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3147416010
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.2096256115
Short name T352
Test name
Test status
Simulation time 63066280 ps
CPU time 1.27 seconds
Started Apr 23 02:10:41 PM PDT 24
Finished Apr 23 02:10:43 PM PDT 24
Peak memory 218456 kb
Host smart-77dd8633-6623-453b-b2f9-0f9c7282115f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096256115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2096256115
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.1352449060
Short name T564
Test name
Test status
Simulation time 101193328 ps
CPU time 1.21 seconds
Started Apr 23 02:10:43 PM PDT 24
Finished Apr 23 02:10:44 PM PDT 24
Peak memory 217372 kb
Host smart-0c36fcf4-56bb-4e98-aac0-99b9a9ea41e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352449060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1352449060
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.979494515
Short name T624
Test name
Test status
Simulation time 65913029 ps
CPU time 2.17 seconds
Started Apr 23 02:10:44 PM PDT 24
Finished Apr 23 02:10:47 PM PDT 24
Peak memory 217464 kb
Host smart-1f56d26d-5c5d-4697-8c96-8b1c1ab1add9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979494515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.979494515
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2922835475
Short name T825
Test name
Test status
Simulation time 34379730 ps
CPU time 1.22 seconds
Started Apr 23 02:07:59 PM PDT 24
Finished Apr 23 02:08:00 PM PDT 24
Peak memory 215880 kb
Host smart-933bd6c4-22d4-4e24-a7a7-579fcd462f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922835475 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2922835475
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3770469695
Short name T783
Test name
Test status
Simulation time 50268593 ps
CPU time 0.88 seconds
Started Apr 23 02:07:59 PM PDT 24
Finished Apr 23 02:08:01 PM PDT 24
Peak memory 215484 kb
Host smart-91b454b3-16b4-40bf-ba7a-eed9decb7b49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770469695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3770469695
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1442187467
Short name T708
Test name
Test status
Simulation time 126572576 ps
CPU time 0.84 seconds
Started Apr 23 02:08:00 PM PDT 24
Finished Apr 23 02:08:01 PM PDT 24
Peak memory 216144 kb
Host smart-5b5155d6-abb6-45c8-bc4e-2e7653a0a5ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442187467 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1442187467
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1432375858
Short name T490
Test name
Test status
Simulation time 35926990 ps
CPU time 1.21 seconds
Started Apr 23 02:07:59 PM PDT 24
Finished Apr 23 02:08:01 PM PDT 24
Peak memory 217124 kb
Host smart-8dc0f627-513d-48c9-8703-c2b098037b45
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432375858 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1432375858
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.693533369
Short name T748
Test name
Test status
Simulation time 21372138 ps
CPU time 1.14 seconds
Started Apr 23 02:07:59 PM PDT 24
Finished Apr 23 02:08:00 PM PDT 24
Peak memory 220124 kb
Host smart-33e5aeff-03d7-49d1-a231-0fdb16c0106d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693533369 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.693533369
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1668179081
Short name T679
Test name
Test status
Simulation time 47200472 ps
CPU time 1.68 seconds
Started Apr 23 02:08:06 PM PDT 24
Finished Apr 23 02:08:08 PM PDT 24
Peak memory 218352 kb
Host smart-a27e4acc-df4a-4123-8ae7-b2568e0e68ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668179081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1668179081
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3739012981
Short name T496
Test name
Test status
Simulation time 21419149 ps
CPU time 1.19 seconds
Started Apr 23 02:08:00 PM PDT 24
Finished Apr 23 02:08:01 PM PDT 24
Peak memory 224384 kb
Host smart-e12976ea-68bb-46d1-887d-a814e6e72b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739012981 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3739012981
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1239028103
Short name T17
Test name
Test status
Simulation time 314893019 ps
CPU time 4.35 seconds
Started Apr 23 02:08:05 PM PDT 24
Finished Apr 23 02:08:10 PM PDT 24
Peak memory 236972 kb
Host smart-2fd9c55e-8e36-4652-ada0-97ab38a9ba55
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239028103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1239028103
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.2370350336
Short name T804
Test name
Test status
Simulation time 19260474 ps
CPU time 1.03 seconds
Started Apr 23 02:07:57 PM PDT 24
Finished Apr 23 02:07:58 PM PDT 24
Peak memory 215576 kb
Host smart-453eebe4-4026-4458-80d3-d708ea4fdb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370350336 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2370350336
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.694380658
Short name T802
Test name
Test status
Simulation time 223544590 ps
CPU time 3.74 seconds
Started Apr 23 02:08:00 PM PDT 24
Finished Apr 23 02:08:05 PM PDT 24
Peak memory 217220 kb
Host smart-9b7f6ea3-b89c-479e-a062-ccfb2cac2941
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694380658 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.694380658
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3691954965
Short name T806
Test name
Test status
Simulation time 145457707604 ps
CPU time 676.77 seconds
Started Apr 23 02:08:01 PM PDT 24
Finished Apr 23 02:19:18 PM PDT 24
Peak memory 220792 kb
Host smart-db8f7965-d3ab-4bfa-8b3e-ab93833708aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691954965 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3691954965
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1321515670
Short name T9
Test name
Test status
Simulation time 29811617 ps
CPU time 1.25 seconds
Started Apr 23 02:08:45 PM PDT 24
Finished Apr 23 02:08:47 PM PDT 24
Peak memory 215944 kb
Host smart-a80ae80e-0d90-41a4-a688-71d9176a637b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321515670 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1321515670
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3978938875
Short name T405
Test name
Test status
Simulation time 20959557 ps
CPU time 1.06 seconds
Started Apr 23 02:08:49 PM PDT 24
Finished Apr 23 02:08:51 PM PDT 24
Peak memory 206960 kb
Host smart-a0b5f0bc-e68e-4ad6-837f-e5b789d16c25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978938875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3978938875
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.2836820083
Short name T840
Test name
Test status
Simulation time 40541202 ps
CPU time 0.86 seconds
Started Apr 23 02:08:43 PM PDT 24
Finished Apr 23 02:08:44 PM PDT 24
Peak memory 216512 kb
Host smart-179a846b-b2bd-4f5d-8938-565b5bdcbf6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836820083 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2836820083
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.892573759
Short name T212
Test name
Test status
Simulation time 192688019 ps
CPU time 1.22 seconds
Started Apr 23 02:08:42 PM PDT 24
Finished Apr 23 02:08:44 PM PDT 24
Peak memory 216980 kb
Host smart-dab6cbd3-754d-4dec-a2b4-3dd95e3ae697
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892573759 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.892573759
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2667587487
Short name T110
Test name
Test status
Simulation time 64648368 ps
CPU time 1.08 seconds
Started Apr 23 02:08:42 PM PDT 24
Finished Apr 23 02:08:44 PM PDT 24
Peak memory 230196 kb
Host smart-edb59661-07b8-4586-85f0-10bd8a57120b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667587487 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2667587487
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2991818382
Short name T526
Test name
Test status
Simulation time 47902922 ps
CPU time 1.46 seconds
Started Apr 23 02:08:44 PM PDT 24
Finished Apr 23 02:08:46 PM PDT 24
Peak memory 218700 kb
Host smart-762bc9f8-e473-4b8b-9921-ba7c161dfb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991818382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2991818382
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1319632112
Short name T684
Test name
Test status
Simulation time 37340339 ps
CPU time 0.97 seconds
Started Apr 23 02:08:44 PM PDT 24
Finished Apr 23 02:08:46 PM PDT 24
Peak memory 224468 kb
Host smart-b822eae9-e207-45e0-a9cc-7546a34fe4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319632112 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1319632112
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.418848926
Short name T316
Test name
Test status
Simulation time 23813098 ps
CPU time 0.91 seconds
Started Apr 23 02:08:47 PM PDT 24
Finished Apr 23 02:08:48 PM PDT 24
Peak memory 215520 kb
Host smart-f48b8483-8101-4a4e-ac21-190c0f89de50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418848926 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.418848926
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/200.edn_genbits.57001763
Short name T83
Test name
Test status
Simulation time 71563787 ps
CPU time 1.2 seconds
Started Apr 23 02:10:46 PM PDT 24
Finished Apr 23 02:10:48 PM PDT 24
Peak memory 218876 kb
Host smart-266d5601-d1da-4dae-b793-6c071fc7ce44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57001763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.57001763
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3505132455
Short name T790
Test name
Test status
Simulation time 53068396 ps
CPU time 1.34 seconds
Started Apr 23 02:10:45 PM PDT 24
Finished Apr 23 02:10:47 PM PDT 24
Peak memory 218892 kb
Host smart-b27f9a0e-4aba-4533-86fd-28ab2f0e927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505132455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3505132455
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2259055586
Short name T589
Test name
Test status
Simulation time 79279864 ps
CPU time 2.18 seconds
Started Apr 23 02:10:45 PM PDT 24
Finished Apr 23 02:10:48 PM PDT 24
Peak memory 220124 kb
Host smart-7f158177-97ca-405b-b580-f5c0820283e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259055586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2259055586
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2316937672
Short name T745
Test name
Test status
Simulation time 87622048 ps
CPU time 1.22 seconds
Started Apr 23 02:10:44 PM PDT 24
Finished Apr 23 02:10:46 PM PDT 24
Peak memory 218932 kb
Host smart-6c75ba9a-6bc5-4764-97dd-bfef4009b852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316937672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2316937672
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.338086754
Short name T495
Test name
Test status
Simulation time 53797904 ps
CPU time 1.29 seconds
Started Apr 23 02:10:45 PM PDT 24
Finished Apr 23 02:10:47 PM PDT 24
Peak memory 218444 kb
Host smart-939da7dc-fb0b-432a-8fa2-668762aeb46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338086754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.338086754
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3549659989
Short name T701
Test name
Test status
Simulation time 97116883 ps
CPU time 1.61 seconds
Started Apr 23 02:10:43 PM PDT 24
Finished Apr 23 02:10:46 PM PDT 24
Peak memory 218804 kb
Host smart-dff2b863-d876-4489-a1d1-4da1fb6465f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549659989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3549659989
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1608894626
Short name T370
Test name
Test status
Simulation time 81390134 ps
CPU time 1.16 seconds
Started Apr 23 02:10:44 PM PDT 24
Finished Apr 23 02:10:46 PM PDT 24
Peak memory 218640 kb
Host smart-e104c1b6-4128-4b84-b816-b1a5805a15e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608894626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1608894626
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2889256218
Short name T47
Test name
Test status
Simulation time 63112162 ps
CPU time 1.51 seconds
Started Apr 23 02:10:46 PM PDT 24
Finished Apr 23 02:10:48 PM PDT 24
Peak memory 218804 kb
Host smart-73667bd4-1d60-4216-b755-69023182569c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889256218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2889256218
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.574037771
Short name T608
Test name
Test status
Simulation time 75891812 ps
CPU time 1.06 seconds
Started Apr 23 02:10:45 PM PDT 24
Finished Apr 23 02:10:47 PM PDT 24
Peak memory 217324 kb
Host smart-acc8830c-2495-4471-89d4-a6f7f74c70b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574037771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.574037771
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3790427800
Short name T43
Test name
Test status
Simulation time 46127752 ps
CPU time 1.57 seconds
Started Apr 23 02:10:44 PM PDT 24
Finished Apr 23 02:10:46 PM PDT 24
Peak memory 215512 kb
Host smart-196f3873-d0bd-4f1e-9ffc-de6bb6a46eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790427800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3790427800
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1053929344
Short name T157
Test name
Test status
Simulation time 27178524 ps
CPU time 1.21 seconds
Started Apr 23 02:08:47 PM PDT 24
Finished Apr 23 02:08:49 PM PDT 24
Peak memory 215988 kb
Host smart-18b33f3d-58ca-4ed7-8b7b-459724c55253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053929344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1053929344
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.950350147
Short name T529
Test name
Test status
Simulation time 120962807 ps
CPU time 0.9 seconds
Started Apr 23 02:08:47 PM PDT 24
Finished Apr 23 02:08:49 PM PDT 24
Peak memory 206880 kb
Host smart-fb9698c5-d129-4ff2-9cd4-50d7469b249f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950350147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.950350147
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1422002729
Short name T441
Test name
Test status
Simulation time 37376554 ps
CPU time 1.04 seconds
Started Apr 23 02:08:49 PM PDT 24
Finished Apr 23 02:08:50 PM PDT 24
Peak memory 218028 kb
Host smart-7c34b879-cd37-47d0-a9f2-6f54baf8a7b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422002729 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1422002729
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3569568038
Short name T141
Test name
Test status
Simulation time 27420272 ps
CPU time 0.93 seconds
Started Apr 23 02:08:47 PM PDT 24
Finished Apr 23 02:08:48 PM PDT 24
Peak memory 224184 kb
Host smart-d52ace5c-7c20-43da-8dd0-da469c496353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569568038 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3569568038
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.4260906918
Short name T561
Test name
Test status
Simulation time 105365734 ps
CPU time 1.31 seconds
Started Apr 23 02:08:47 PM PDT 24
Finished Apr 23 02:08:49 PM PDT 24
Peak memory 217224 kb
Host smart-0a1654f0-5b16-473a-93c9-ff61a6b69efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260906918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.4260906918
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1819865121
Short name T425
Test name
Test status
Simulation time 30660692 ps
CPU time 0.88 seconds
Started Apr 23 02:08:46 PM PDT 24
Finished Apr 23 02:08:48 PM PDT 24
Peak memory 215656 kb
Host smart-210e3bd7-a31d-4b5a-b17a-c8f3d00cc66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819865121 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1819865121
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1591866456
Short name T609
Test name
Test status
Simulation time 30843041 ps
CPU time 0.96 seconds
Started Apr 23 02:08:46 PM PDT 24
Finished Apr 23 02:08:47 PM PDT 24
Peak memory 215448 kb
Host smart-8a7dab06-2f99-429d-a924-e852c51ed119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591866456 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1591866456
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1993771087
Short name T219
Test name
Test status
Simulation time 97017372 ps
CPU time 1 seconds
Started Apr 23 02:08:47 PM PDT 24
Finished Apr 23 02:08:49 PM PDT 24
Peak memory 206712 kb
Host smart-b932ae66-e4c4-4482-8375-dd2f0b9b76fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993771087 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1993771087
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3688989309
Short name T196
Test name
Test status
Simulation time 107499784496 ps
CPU time 1180.72 seconds
Started Apr 23 02:08:46 PM PDT 24
Finished Apr 23 02:28:28 PM PDT 24
Peak memory 224344 kb
Host smart-0c7ba78c-5891-4534-81d4-a8aeff1bcf11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688989309 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3688989309
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3189919400
Short name T271
Test name
Test status
Simulation time 56050394 ps
CPU time 1.21 seconds
Started Apr 23 02:10:44 PM PDT 24
Finished Apr 23 02:10:46 PM PDT 24
Peak memory 218288 kb
Host smart-efeb9f0f-61e7-4b9a-964b-74106cd12621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189919400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3189919400
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2543702597
Short name T558
Test name
Test status
Simulation time 50364610 ps
CPU time 1.17 seconds
Started Apr 23 02:10:46 PM PDT 24
Finished Apr 23 02:10:48 PM PDT 24
Peak memory 217256 kb
Host smart-8453769d-99aa-4303-bd7b-39441cbf72e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543702597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2543702597
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.4076040234
Short name T411
Test name
Test status
Simulation time 122547498 ps
CPU time 2.46 seconds
Started Apr 23 02:10:44 PM PDT 24
Finished Apr 23 02:10:48 PM PDT 24
Peak memory 219584 kb
Host smart-42339c8c-123b-4c9e-80cb-8f7416a4ae09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076040234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.4076040234
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.572225
Short name T338
Test name
Test status
Simulation time 48689759 ps
CPU time 1.66 seconds
Started Apr 23 02:10:45 PM PDT 24
Finished Apr 23 02:10:48 PM PDT 24
Peak memory 217884 kb
Host smart-89ae5747-8cf9-427d-ab0e-6e603bb719ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.572225
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1541729641
Short name T687
Test name
Test status
Simulation time 60850753 ps
CPU time 1.13 seconds
Started Apr 23 02:10:46 PM PDT 24
Finished Apr 23 02:10:48 PM PDT 24
Peak memory 217080 kb
Host smart-2cb19fb0-f6e3-4ed3-a48d-1cf7d2d9130b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541729641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1541729641
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1407346058
Short name T393
Test name
Test status
Simulation time 52299242 ps
CPU time 1.23 seconds
Started Apr 23 02:10:44 PM PDT 24
Finished Apr 23 02:10:45 PM PDT 24
Peak memory 217148 kb
Host smart-22521506-d493-4fd6-b697-dfeeff64613f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407346058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1407346058
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2747252514
Short name T795
Test name
Test status
Simulation time 193403852 ps
CPU time 1.26 seconds
Started Apr 23 02:10:49 PM PDT 24
Finished Apr 23 02:10:51 PM PDT 24
Peak memory 217184 kb
Host smart-2356ecf8-c74d-4109-a1d8-e12387328620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747252514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2747252514
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2237319093
Short name T481
Test name
Test status
Simulation time 91204808 ps
CPU time 1.63 seconds
Started Apr 23 02:10:47 PM PDT 24
Finished Apr 23 02:10:49 PM PDT 24
Peak memory 218720 kb
Host smart-df5f8ca7-df07-4da8-89b4-34166edca15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237319093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2237319093
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1835368761
Short name T772
Test name
Test status
Simulation time 76883670 ps
CPU time 1.14 seconds
Started Apr 23 02:10:46 PM PDT 24
Finished Apr 23 02:10:48 PM PDT 24
Peak memory 217324 kb
Host smart-4b5c9f32-16d5-448d-98a9-d43f63028b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835368761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1835368761
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3502901920
Short name T280
Test name
Test status
Simulation time 175770055 ps
CPU time 3.53 seconds
Started Apr 23 02:10:53 PM PDT 24
Finished Apr 23 02:10:57 PM PDT 24
Peak memory 220192 kb
Host smart-183f7c27-da89-48e1-9ac1-926f85096a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502901920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3502901920
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2663964981
Short name T257
Test name
Test status
Simulation time 69927803 ps
CPU time 1.15 seconds
Started Apr 23 02:08:49 PM PDT 24
Finished Apr 23 02:08:51 PM PDT 24
Peak memory 215872 kb
Host smart-69913770-caae-412a-aa5b-14d58238d8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663964981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2663964981
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3352349779
Short name T762
Test name
Test status
Simulation time 20018467 ps
CPU time 0.98 seconds
Started Apr 23 02:08:49 PM PDT 24
Finished Apr 23 02:08:50 PM PDT 24
Peak memory 206876 kb
Host smart-3779fa08-a6a1-464d-a967-e24c39c79c26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352349779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3352349779
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2629084674
Short name T178
Test name
Test status
Simulation time 42830468 ps
CPU time 0.83 seconds
Started Apr 23 02:08:53 PM PDT 24
Finished Apr 23 02:08:55 PM PDT 24
Peak memory 216384 kb
Host smart-4a6f3a2b-039d-4b92-94df-8d4785e7ff67
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629084674 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2629084674
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.958918010
Short name T117
Test name
Test status
Simulation time 78905298 ps
CPU time 1.06 seconds
Started Apr 23 02:08:51 PM PDT 24
Finished Apr 23 02:08:52 PM PDT 24
Peak memory 217100 kb
Host smart-c4e16e09-c700-4b7a-a55c-439025b4b881
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958918010 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_di
sable_auto_req_mode.958918010
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1664008378
Short name T175
Test name
Test status
Simulation time 28897290 ps
CPU time 1.27 seconds
Started Apr 23 02:08:50 PM PDT 24
Finished Apr 23 02:08:51 PM PDT 24
Peak memory 220016 kb
Host smart-c7ad2552-0629-4ce6-9443-140ab534dbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664008378 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1664008378
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3388403115
Short name T621
Test name
Test status
Simulation time 25884867 ps
CPU time 0.97 seconds
Started Apr 23 02:08:49 PM PDT 24
Finished Apr 23 02:08:51 PM PDT 24
Peak memory 217172 kb
Host smart-7bf9ebf0-a1fc-4c26-ba80-e0e758d93ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388403115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3388403115
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.201813636
Short name T675
Test name
Test status
Simulation time 34507041 ps
CPU time 0.92 seconds
Started Apr 23 02:08:53 PM PDT 24
Finished Apr 23 02:08:55 PM PDT 24
Peak memory 215848 kb
Host smart-1bcefd88-aeb7-4e13-b329-4d083a7fac50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201813636 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.201813636
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3887376301
Short name T443
Test name
Test status
Simulation time 27705203 ps
CPU time 1.04 seconds
Started Apr 23 02:08:55 PM PDT 24
Finished Apr 23 02:08:57 PM PDT 24
Peak memory 215504 kb
Host smart-82303726-d290-4ce4-88a8-5a66f789ea14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887376301 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3887376301
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1446690471
Short name T587
Test name
Test status
Simulation time 551707628 ps
CPU time 5.72 seconds
Started Apr 23 02:08:48 PM PDT 24
Finished Apr 23 02:08:55 PM PDT 24
Peak memory 220548 kb
Host smart-114413ea-1a41-419e-b716-237c4d73401b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446690471 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1446690471
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3946974072
Short name T571
Test name
Test status
Simulation time 178238993153 ps
CPU time 1993.38 seconds
Started Apr 23 02:08:52 PM PDT 24
Finished Apr 23 02:42:07 PM PDT 24
Peak memory 227012 kb
Host smart-e213a80c-cbfa-4122-8dc3-d6502c90f563
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946974072 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3946974072
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.289238687
Short name T397
Test name
Test status
Simulation time 34889276 ps
CPU time 1.53 seconds
Started Apr 23 02:10:47 PM PDT 24
Finished Apr 23 02:10:50 PM PDT 24
Peak memory 218336 kb
Host smart-f8f30324-459f-43f0-8aa1-0344b4ca9153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289238687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.289238687
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1419312396
Short name T59
Test name
Test status
Simulation time 30158975 ps
CPU time 1.36 seconds
Started Apr 23 02:10:48 PM PDT 24
Finished Apr 23 02:10:50 PM PDT 24
Peak memory 217324 kb
Host smart-a87ce78b-b053-4d3c-8f78-c302e8d72cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419312396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1419312396
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.876748709
Short name T503
Test name
Test status
Simulation time 40921575 ps
CPU time 1.09 seconds
Started Apr 23 02:10:48 PM PDT 24
Finished Apr 23 02:10:50 PM PDT 24
Peak memory 217352 kb
Host smart-5178ce6d-af2f-4987-aa01-b8835cf1362e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876748709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.876748709
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2498136676
Short name T532
Test name
Test status
Simulation time 27452658 ps
CPU time 0.92 seconds
Started Apr 23 02:10:52 PM PDT 24
Finished Apr 23 02:10:54 PM PDT 24
Peak memory 217052 kb
Host smart-4b7f67c4-7f4f-4764-aae8-724654e3a266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498136676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2498136676
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1334572541
Short name T354
Test name
Test status
Simulation time 271671877 ps
CPU time 3.98 seconds
Started Apr 23 02:10:48 PM PDT 24
Finished Apr 23 02:10:53 PM PDT 24
Peak memory 217696 kb
Host smart-124a47c4-c9c2-40b9-b814-fdeb008f988e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334572541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1334572541
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3863973167
Short name T754
Test name
Test status
Simulation time 22354660 ps
CPU time 1.12 seconds
Started Apr 23 02:10:46 PM PDT 24
Finished Apr 23 02:10:48 PM PDT 24
Peak memory 217296 kb
Host smart-e8f94eaf-8d36-4023-b991-c123c1f60110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863973167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3863973167
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2721642392
Short name T360
Test name
Test status
Simulation time 63245163 ps
CPU time 1.72 seconds
Started Apr 23 02:10:47 PM PDT 24
Finished Apr 23 02:10:50 PM PDT 24
Peak memory 218544 kb
Host smart-fb104345-34e9-4133-b4bf-20306ac74d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721642392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2721642392
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3249992434
Short name T388
Test name
Test status
Simulation time 56863007 ps
CPU time 1.34 seconds
Started Apr 23 02:10:47 PM PDT 24
Finished Apr 23 02:10:50 PM PDT 24
Peak memory 218664 kb
Host smart-b9361fa2-a22a-4ef7-9d2c-edb3216ef115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249992434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3249992434
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.112102614
Short name T605
Test name
Test status
Simulation time 59453524 ps
CPU time 1.16 seconds
Started Apr 23 02:10:50 PM PDT 24
Finished Apr 23 02:10:52 PM PDT 24
Peak memory 217364 kb
Host smart-255d1962-8ce1-4ea9-abe0-504a7ab0d4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112102614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.112102614
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert_test.1195678536
Short name T359
Test name
Test status
Simulation time 25026652 ps
CPU time 0.83 seconds
Started Apr 23 02:08:53 PM PDT 24
Finished Apr 23 02:08:54 PM PDT 24
Peak memory 207148 kb
Host smart-34716f03-12f0-4942-a000-0f17aa56f539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195678536 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1195678536
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3285870902
Short name T418
Test name
Test status
Simulation time 23660287 ps
CPU time 0.84 seconds
Started Apr 23 02:08:53 PM PDT 24
Finished Apr 23 02:08:55 PM PDT 24
Peak memory 216660 kb
Host smart-5d9b6bb7-4352-4aec-83b2-48700ee2f41b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285870902 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3285870902
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1750341550
Short name T448
Test name
Test status
Simulation time 33139920 ps
CPU time 1.28 seconds
Started Apr 23 02:08:55 PM PDT 24
Finished Apr 23 02:08:57 PM PDT 24
Peak memory 219784 kb
Host smart-5269e95d-63fa-4f29-9e1f-80375befcb5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750341550 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1750341550
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.583142954
Short name T729
Test name
Test status
Simulation time 21837627 ps
CPU time 0.92 seconds
Started Apr 23 02:08:54 PM PDT 24
Finished Apr 23 02:08:56 PM PDT 24
Peak memory 218372 kb
Host smart-c0a88c9e-9af0-44d9-92e2-9a7be772d46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583142954 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.583142954
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_intr.1660473120
Short name T366
Test name
Test status
Simulation time 32847365 ps
CPU time 1.13 seconds
Started Apr 23 02:08:54 PM PDT 24
Finished Apr 23 02:08:56 PM PDT 24
Peak memory 224400 kb
Host smart-b58d2fd9-a122-49e0-83ba-7fd7c26ccf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660473120 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1660473120
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1014579127
Short name T311
Test name
Test status
Simulation time 43382910 ps
CPU time 0.9 seconds
Started Apr 23 02:08:51 PM PDT 24
Finished Apr 23 02:08:53 PM PDT 24
Peak memory 215480 kb
Host smart-d8a6f9c3-b725-403d-9459-5e85c6effb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014579127 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1014579127
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3462225724
Short name T447
Test name
Test status
Simulation time 171631880 ps
CPU time 2.45 seconds
Started Apr 23 02:08:50 PM PDT 24
Finished Apr 23 02:08:53 PM PDT 24
Peak memory 215636 kb
Host smart-9dd2a95c-4c63-4b3e-baff-7c1393674ecb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462225724 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3462225724
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3328351786
Short name T476
Test name
Test status
Simulation time 262647396818 ps
CPU time 1050.98 seconds
Started Apr 23 02:08:53 PM PDT 24
Finished Apr 23 02:26:25 PM PDT 24
Peak memory 222824 kb
Host smart-5704862a-6458-473a-ad07-da72f1e06652
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328351786 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3328351786
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1126140315
Short name T653
Test name
Test status
Simulation time 100941825 ps
CPU time 1.58 seconds
Started Apr 23 02:10:46 PM PDT 24
Finished Apr 23 02:10:48 PM PDT 24
Peak memory 218980 kb
Host smart-e94ca383-b2b4-4de1-b53c-5a220878a26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126140315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1126140315
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1626526510
Short name T720
Test name
Test status
Simulation time 229235733 ps
CPU time 1.2 seconds
Started Apr 23 02:10:52 PM PDT 24
Finished Apr 23 02:10:54 PM PDT 24
Peak memory 219980 kb
Host smart-a6d09c1a-e198-4259-a5c9-3b14e2ed429c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626526510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1626526510
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3915071597
Short name T723
Test name
Test status
Simulation time 38286945 ps
CPU time 1.39 seconds
Started Apr 23 02:10:49 PM PDT 24
Finished Apr 23 02:10:51 PM PDT 24
Peak memory 220100 kb
Host smart-e94b9b9f-54c8-47d0-96c8-e102d52b4e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915071597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3915071597
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1097917998
Short name T310
Test name
Test status
Simulation time 78043563 ps
CPU time 1.58 seconds
Started Apr 23 02:10:50 PM PDT 24
Finished Apr 23 02:10:52 PM PDT 24
Peak memory 218492 kb
Host smart-651205ab-8259-432d-86a7-3afc34da7a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097917998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1097917998
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2384457737
Short name T79
Test name
Test status
Simulation time 63214383 ps
CPU time 1.22 seconds
Started Apr 23 02:10:49 PM PDT 24
Finished Apr 23 02:10:51 PM PDT 24
Peak memory 217336 kb
Host smart-96188d5c-fd7d-4516-8741-dfd5a84ba28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384457737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2384457737
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3085110765
Short name T331
Test name
Test status
Simulation time 71592277 ps
CPU time 1.19 seconds
Started Apr 23 02:10:49 PM PDT 24
Finished Apr 23 02:10:51 PM PDT 24
Peak memory 218496 kb
Host smart-175fd506-328e-4969-94e7-7bcc8b910e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085110765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3085110765
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2680141422
Short name T714
Test name
Test status
Simulation time 55836257 ps
CPU time 1.1 seconds
Started Apr 23 02:10:49 PM PDT 24
Finished Apr 23 02:10:50 PM PDT 24
Peak memory 220120 kb
Host smart-6660c26c-f718-487f-a4cd-30a479f5d24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680141422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2680141422
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.659470247
Short name T713
Test name
Test status
Simulation time 275976804 ps
CPU time 1.28 seconds
Started Apr 23 02:10:51 PM PDT 24
Finished Apr 23 02:10:53 PM PDT 24
Peak memory 220016 kb
Host smart-95490cb0-9e97-4df7-bc38-e7810d7c354b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659470247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.659470247
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.309757387
Short name T296
Test name
Test status
Simulation time 35700941 ps
CPU time 1.33 seconds
Started Apr 23 02:10:50 PM PDT 24
Finished Apr 23 02:10:52 PM PDT 24
Peak memory 218512 kb
Host smart-5f75fe34-afe3-4c39-8e2b-e51040a3b57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309757387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.309757387
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1433345821
Short name T498
Test name
Test status
Simulation time 141299879 ps
CPU time 1.86 seconds
Started Apr 23 02:10:50 PM PDT 24
Finished Apr 23 02:10:52 PM PDT 24
Peak memory 218880 kb
Host smart-5fe93336-c7ad-48fe-91df-a0a6baf9fd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433345821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1433345821
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1217825762
Short name T666
Test name
Test status
Simulation time 27214612 ps
CPU time 1.27 seconds
Started Apr 23 02:08:52 PM PDT 24
Finished Apr 23 02:08:54 PM PDT 24
Peak memory 215932 kb
Host smart-3a70a7be-33b2-4d30-ad74-9dafc2ad37fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217825762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1217825762
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.4006353872
Short name T334
Test name
Test status
Simulation time 11321924 ps
CPU time 0.86 seconds
Started Apr 23 02:08:56 PM PDT 24
Finished Apr 23 02:08:58 PM PDT 24
Peak memory 206700 kb
Host smart-59d3888f-a8cb-401f-a696-9fa80576871f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006353872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.4006353872
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2973033929
Short name T189
Test name
Test status
Simulation time 19806824 ps
CPU time 0.91 seconds
Started Apr 23 02:08:57 PM PDT 24
Finished Apr 23 02:08:59 PM PDT 24
Peak memory 215672 kb
Host smart-9bc0eae3-5938-448f-a47d-2f436dc5721d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973033929 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2973033929
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.129548953
Short name T101
Test name
Test status
Simulation time 40528321 ps
CPU time 1.43 seconds
Started Apr 23 02:08:58 PM PDT 24
Finished Apr 23 02:09:00 PM PDT 24
Peak memory 217192 kb
Host smart-0280b435-059b-4578-b5cd-27fa317f6b9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129548953 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.129548953
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2885742531
Short name T14
Test name
Test status
Simulation time 38606669 ps
CPU time 1.33 seconds
Started Apr 23 02:08:55 PM PDT 24
Finished Apr 23 02:08:58 PM PDT 24
Peak memory 226032 kb
Host smart-998b100d-9473-4161-b93c-3f1634dce7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885742531 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2885742531
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3864172023
Short name T738
Test name
Test status
Simulation time 187556523 ps
CPU time 3.7 seconds
Started Apr 23 02:08:53 PM PDT 24
Finished Apr 23 02:08:57 PM PDT 24
Peak memory 218420 kb
Host smart-e931d155-c1c1-44a0-9676-014eaf24f9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864172023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3864172023
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3994974665
Short name T34
Test name
Test status
Simulation time 20306338 ps
CPU time 1.1 seconds
Started Apr 23 02:08:51 PM PDT 24
Finished Apr 23 02:08:52 PM PDT 24
Peak memory 216068 kb
Host smart-22a045cf-a5bc-40cc-bb8e-73836d894949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994974665 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3994974665
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3701960656
Short name T656
Test name
Test status
Simulation time 27467486 ps
CPU time 1 seconds
Started Apr 23 02:08:53 PM PDT 24
Finished Apr 23 02:08:55 PM PDT 24
Peak memory 215572 kb
Host smart-34813204-68c2-4979-95ff-49790b076716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701960656 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3701960656
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2397497648
Short name T313
Test name
Test status
Simulation time 613520506 ps
CPU time 1.7 seconds
Started Apr 23 02:08:51 PM PDT 24
Finished Apr 23 02:08:54 PM PDT 24
Peak memory 215588 kb
Host smart-5a3c6c4b-42ac-45a7-9867-f690c487fef3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397497648 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2397497648
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3936886802
Short name T823
Test name
Test status
Simulation time 128141352809 ps
CPU time 963.55 seconds
Started Apr 23 02:08:52 PM PDT 24
Finished Apr 23 02:24:56 PM PDT 24
Peak memory 223592 kb
Host smart-a1a1cc13-50c0-4612-9605-3601fe7f9d1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936886802 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3936886802
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1548510452
Short name T276
Test name
Test status
Simulation time 94901252 ps
CPU time 1.34 seconds
Started Apr 23 02:10:49 PM PDT 24
Finished Apr 23 02:10:51 PM PDT 24
Peak memory 218700 kb
Host smart-04cabbee-92eb-4e4d-8655-e284a5e19e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548510452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1548510452
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1134218896
Short name T80
Test name
Test status
Simulation time 35250677 ps
CPU time 1.07 seconds
Started Apr 23 02:10:51 PM PDT 24
Finished Apr 23 02:10:52 PM PDT 24
Peak memory 217116 kb
Host smart-bef49e7d-d016-4e14-a991-312ae8f1ee1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134218896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1134218896
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.27423217
Short name T410
Test name
Test status
Simulation time 248684157 ps
CPU time 1.72 seconds
Started Apr 23 02:10:52 PM PDT 24
Finished Apr 23 02:10:54 PM PDT 24
Peak memory 217164 kb
Host smart-f3b5cb26-9e2f-42d5-be7f-9795b4d37591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27423217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.27423217
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.712810063
Short name T553
Test name
Test status
Simulation time 49876629 ps
CPU time 1.22 seconds
Started Apr 23 02:10:54 PM PDT 24
Finished Apr 23 02:10:55 PM PDT 24
Peak memory 217340 kb
Host smart-105979a9-287e-4b93-b64f-f3e792acc4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712810063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.712810063
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.428441820
Short name T709
Test name
Test status
Simulation time 33789416 ps
CPU time 1.09 seconds
Started Apr 23 02:10:57 PM PDT 24
Finished Apr 23 02:10:59 PM PDT 24
Peak memory 217180 kb
Host smart-d7f31785-549b-4b52-9161-508364e8a04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428441820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.428441820
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2561144902
Short name T824
Test name
Test status
Simulation time 52134779 ps
CPU time 1.64 seconds
Started Apr 23 02:10:56 PM PDT 24
Finished Apr 23 02:10:58 PM PDT 24
Peak memory 219912 kb
Host smart-d4ee637a-f92d-497e-bf0d-546c3f469671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561144902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2561144902
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2548233589
Short name T67
Test name
Test status
Simulation time 57123024 ps
CPU time 1.33 seconds
Started Apr 23 02:10:57 PM PDT 24
Finished Apr 23 02:10:58 PM PDT 24
Peak memory 218448 kb
Host smart-7d405abc-6d82-449c-8445-ae12f9113971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548233589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2548233589
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2001519659
Short name T793
Test name
Test status
Simulation time 61510335 ps
CPU time 2.27 seconds
Started Apr 23 02:10:59 PM PDT 24
Finished Apr 23 02:11:02 PM PDT 24
Peak memory 220004 kb
Host smart-ab819e68-4383-467a-9234-831189cfdebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001519659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2001519659
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1118719202
Short name T287
Test name
Test status
Simulation time 114220973 ps
CPU time 1.41 seconds
Started Apr 23 02:11:00 PM PDT 24
Finished Apr 23 02:11:02 PM PDT 24
Peak memory 218780 kb
Host smart-c767eff9-379a-48ff-aba5-ec4baa3e7615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118719202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1118719202
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3992731779
Short name T533
Test name
Test status
Simulation time 64733550 ps
CPU time 2.46 seconds
Started Apr 23 02:11:00 PM PDT 24
Finished Apr 23 02:11:03 PM PDT 24
Peak memory 220264 kb
Host smart-cc5b3eb3-fa67-444d-98db-4061ec214a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992731779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3992731779
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3377565446
Short name T799
Test name
Test status
Simulation time 89297912 ps
CPU time 1.14 seconds
Started Apr 23 02:08:58 PM PDT 24
Finished Apr 23 02:09:00 PM PDT 24
Peak memory 215972 kb
Host smart-5952baad-5391-491b-8441-0b3cc83fbe08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377565446 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3377565446
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3155768157
Short name T543
Test name
Test status
Simulation time 19510494 ps
CPU time 1.05 seconds
Started Apr 23 02:09:00 PM PDT 24
Finished Apr 23 02:09:01 PM PDT 24
Peak memory 206920 kb
Host smart-8603bca4-8281-49fb-aa09-5a9502cedc9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155768157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3155768157
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.728029545
Short name T102
Test name
Test status
Simulation time 59552315 ps
CPU time 1.24 seconds
Started Apr 23 02:09:00 PM PDT 24
Finished Apr 23 02:09:02 PM PDT 24
Peak memory 217252 kb
Host smart-2edbc2c1-6cd8-49af-ab1a-08f02b23192f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728029545 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.728029545
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1844401519
Short name T507
Test name
Test status
Simulation time 25014545 ps
CPU time 0.98 seconds
Started Apr 23 02:09:01 PM PDT 24
Finished Apr 23 02:09:02 PM PDT 24
Peak memory 218532 kb
Host smart-d764c847-ecb3-4027-b3a0-e27dacb5ca17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844401519 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1844401519
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_smoke.2424632872
Short name T467
Test name
Test status
Simulation time 29828013 ps
CPU time 0.92 seconds
Started Apr 23 02:08:55 PM PDT 24
Finished Apr 23 02:08:57 PM PDT 24
Peak memory 215576 kb
Host smart-b109d92d-2b20-485a-af99-b026b4568150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424632872 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2424632872
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2060148010
Short name T636
Test name
Test status
Simulation time 174852075 ps
CPU time 3.59 seconds
Started Apr 23 02:08:57 PM PDT 24
Finished Apr 23 02:09:01 PM PDT 24
Peak memory 218372 kb
Host smart-05fc5e15-1f0a-420e-a0be-1fdd8f4cb7f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060148010 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2060148010
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1551428336
Short name T686
Test name
Test status
Simulation time 159189556572 ps
CPU time 1409.74 seconds
Started Apr 23 02:08:57 PM PDT 24
Finished Apr 23 02:32:28 PM PDT 24
Peak memory 224128 kb
Host smart-eaf2afb7-2d19-4704-82d3-2014b2620b90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551428336 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1551428336
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1100536973
Short name T364
Test name
Test status
Simulation time 35652549 ps
CPU time 1.34 seconds
Started Apr 23 02:10:58 PM PDT 24
Finished Apr 23 02:11:00 PM PDT 24
Peak memory 218364 kb
Host smart-992b5394-2823-4e1b-916b-260be3db1b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100536973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1100536973
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.3329713965
Short name T210
Test name
Test status
Simulation time 55802378 ps
CPU time 1.28 seconds
Started Apr 23 02:10:59 PM PDT 24
Finished Apr 23 02:11:01 PM PDT 24
Peak memory 218280 kb
Host smart-95bfbbed-e6bc-46f9-aff8-354e9459aed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329713965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3329713965
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1840745785
Short name T677
Test name
Test status
Simulation time 62939234 ps
CPU time 1.47 seconds
Started Apr 23 02:11:00 PM PDT 24
Finished Apr 23 02:11:02 PM PDT 24
Peak memory 218888 kb
Host smart-4b411ff7-0d69-4fe6-9a06-883f99f639db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840745785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1840745785
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3615681807
Short name T332
Test name
Test status
Simulation time 47631792 ps
CPU time 1.73 seconds
Started Apr 23 02:11:01 PM PDT 24
Finished Apr 23 02:11:03 PM PDT 24
Peak memory 218528 kb
Host smart-169982ab-67b9-4d40-b19e-cc8eebf2135d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615681807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3615681807
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1432350719
Short name T339
Test name
Test status
Simulation time 64065293 ps
CPU time 2.68 seconds
Started Apr 23 02:10:58 PM PDT 24
Finished Apr 23 02:11:02 PM PDT 24
Peak memory 220112 kb
Host smart-46f4bd20-829d-45f2-8602-84e288c53c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432350719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1432350719
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1869790186
Short name T409
Test name
Test status
Simulation time 41212460 ps
CPU time 1.39 seconds
Started Apr 23 02:10:58 PM PDT 24
Finished Apr 23 02:10:59 PM PDT 24
Peak memory 218472 kb
Host smart-4e96d72b-80a1-4e66-b789-5be90f409a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869790186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1869790186
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3716153640
Short name T301
Test name
Test status
Simulation time 45539779 ps
CPU time 1.5 seconds
Started Apr 23 02:10:58 PM PDT 24
Finished Apr 23 02:11:00 PM PDT 24
Peak memory 218664 kb
Host smart-c9ae4e71-b8e2-4bca-9f6d-ae19aec23ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716153640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3716153640
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1889280962
Short name T421
Test name
Test status
Simulation time 152127328 ps
CPU time 2.03 seconds
Started Apr 23 02:10:59 PM PDT 24
Finished Apr 23 02:11:02 PM PDT 24
Peak memory 218448 kb
Host smart-f4176fcf-16f0-4c1b-af4b-297a5e0a4242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889280962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1889280962
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.198998031
Short name T321
Test name
Test status
Simulation time 153355765 ps
CPU time 2.17 seconds
Started Apr 23 02:11:00 PM PDT 24
Finished Apr 23 02:11:03 PM PDT 24
Peak memory 219696 kb
Host smart-e3ebf548-76de-4943-92ed-d276b50011d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198998031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.198998031
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.4127313678
Short name T632
Test name
Test status
Simulation time 27019250 ps
CPU time 1.18 seconds
Started Apr 23 02:11:00 PM PDT 24
Finished Apr 23 02:11:02 PM PDT 24
Peak memory 218280 kb
Host smart-f862da8d-7100-4fe4-a77d-824d82a28175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127313678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.4127313678
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2575812263
Short name T698
Test name
Test status
Simulation time 152472488 ps
CPU time 1.1 seconds
Started Apr 23 02:09:00 PM PDT 24
Finished Apr 23 02:09:01 PM PDT 24
Peak memory 215896 kb
Host smart-be37847f-9be0-4433-9620-1cc02dc73c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575812263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2575812263
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.4114856241
Short name T358
Test name
Test status
Simulation time 11516461 ps
CPU time 0.81 seconds
Started Apr 23 02:09:03 PM PDT 24
Finished Apr 23 02:09:04 PM PDT 24
Peak memory 207316 kb
Host smart-168e65be-d775-4aa5-9c10-2b0f9b8a8c85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114856241 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.4114856241
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1632628360
Short name T138
Test name
Test status
Simulation time 12037142 ps
CPU time 0.91 seconds
Started Apr 23 02:09:04 PM PDT 24
Finished Apr 23 02:09:06 PM PDT 24
Peak memory 216840 kb
Host smart-a96aa167-8579-429a-b44b-287768df1c6c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632628360 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1632628360
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3055449792
Short name T161
Test name
Test status
Simulation time 86654013 ps
CPU time 1.08 seconds
Started Apr 23 02:09:01 PM PDT 24
Finished Apr 23 02:09:03 PM PDT 24
Peak memory 216952 kb
Host smart-42ea50c4-6b25-40ec-984b-0c84d2f01a24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055449792 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3055449792
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3309862434
Short name T130
Test name
Test status
Simulation time 19102805 ps
CPU time 1.15 seconds
Started Apr 23 02:09:04 PM PDT 24
Finished Apr 23 02:09:06 PM PDT 24
Peak memory 224460 kb
Host smart-51a01d22-2f02-4ae1-b406-82c5a8da061d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309862434 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3309862434
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3006124901
Short name T766
Test name
Test status
Simulation time 96555001 ps
CPU time 1.55 seconds
Started Apr 23 02:08:59 PM PDT 24
Finished Apr 23 02:09:01 PM PDT 24
Peak memory 218800 kb
Host smart-8ddf8c70-825e-4a3c-b163-2f676aabe65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006124901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3006124901
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.362068590
Short name T430
Test name
Test status
Simulation time 30667687 ps
CPU time 0.87 seconds
Started Apr 23 02:08:59 PM PDT 24
Finished Apr 23 02:09:00 PM PDT 24
Peak memory 215796 kb
Host smart-be33b79b-22e3-417f-8bf3-9a2ccc266b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362068590 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.362068590
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.196541148
Short name T401
Test name
Test status
Simulation time 17299351 ps
CPU time 0.99 seconds
Started Apr 23 02:09:02 PM PDT 24
Finished Apr 23 02:09:03 PM PDT 24
Peak memory 215408 kb
Host smart-4dff652c-5a09-415d-a688-c30018430629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196541148 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.196541148
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2963887753
Short name T461
Test name
Test status
Simulation time 159312074 ps
CPU time 1.5 seconds
Started Apr 23 02:08:59 PM PDT 24
Finished Apr 23 02:09:01 PM PDT 24
Peak memory 217044 kb
Host smart-2729a1c1-9108-4a28-9fa3-5e9b531bc5a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963887753 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2963887753
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/260.edn_genbits.3439540999
Short name T694
Test name
Test status
Simulation time 52482028 ps
CPU time 2.14 seconds
Started Apr 23 02:11:01 PM PDT 24
Finished Apr 23 02:11:04 PM PDT 24
Peak memory 218372 kb
Host smart-c1adddb9-25ae-4c7a-9514-3e4e36df4e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439540999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3439540999
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.974341608
Short name T386
Test name
Test status
Simulation time 19452729 ps
CPU time 1.09 seconds
Started Apr 23 02:11:03 PM PDT 24
Finished Apr 23 02:11:05 PM PDT 24
Peak memory 217276 kb
Host smart-451c6cba-bb93-4101-a361-861a7f7fe580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974341608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.974341608
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1926575076
Short name T485
Test name
Test status
Simulation time 51951307 ps
CPU time 1.22 seconds
Started Apr 23 02:11:03 PM PDT 24
Finished Apr 23 02:11:05 PM PDT 24
Peak memory 217400 kb
Host smart-e8910764-6088-48d4-b2cd-ab9214bf0438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926575076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1926575076
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.602665712
Short name T548
Test name
Test status
Simulation time 109583424 ps
CPU time 1.44 seconds
Started Apr 23 02:11:02 PM PDT 24
Finished Apr 23 02:11:05 PM PDT 24
Peak memory 219948 kb
Host smart-49dca709-198d-4117-9a86-3553593e0bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602665712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.602665712
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.913587315
Short name T620
Test name
Test status
Simulation time 181915777 ps
CPU time 1.28 seconds
Started Apr 23 02:11:02 PM PDT 24
Finished Apr 23 02:11:04 PM PDT 24
Peak memory 219076 kb
Host smart-5170af5b-4eca-4e3d-9ccc-626707eaef03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913587315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.913587315
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.1104939764
Short name T432
Test name
Test status
Simulation time 170571136 ps
CPU time 1.5 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:13 PM PDT 24
Peak memory 218796 kb
Host smart-d648431c-5b14-447a-9880-e18c1f0a7e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104939764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1104939764
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.496513464
Short name T538
Test name
Test status
Simulation time 62342564 ps
CPU time 1.3 seconds
Started Apr 23 02:11:13 PM PDT 24
Finished Apr 23 02:11:16 PM PDT 24
Peak memory 218896 kb
Host smart-05cd250b-6c3f-40c8-9c10-2a33d350338a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496513464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.496513464
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.625269852
Short name T598
Test name
Test status
Simulation time 245671774 ps
CPU time 3.18 seconds
Started Apr 23 02:11:04 PM PDT 24
Finished Apr 23 02:11:08 PM PDT 24
Peak memory 219984 kb
Host smart-bcdaca5e-1343-49be-8df7-28ac333dcf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625269852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.625269852
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.627480655
Short name T534
Test name
Test status
Simulation time 74786710 ps
CPU time 1.18 seconds
Started Apr 23 02:11:04 PM PDT 24
Finished Apr 23 02:11:06 PM PDT 24
Peak memory 219444 kb
Host smart-b6839e0d-52f8-4052-b667-bf6b046ffce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627480655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.627480655
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.999703124
Short name T337
Test name
Test status
Simulation time 74737576 ps
CPU time 2.6 seconds
Started Apr 23 02:11:04 PM PDT 24
Finished Apr 23 02:11:08 PM PDT 24
Peak memory 218428 kb
Host smart-b4272dd1-665a-46d7-812b-b2ce0584ca19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999703124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.999703124
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3808506944
Short name T387
Test name
Test status
Simulation time 26037638 ps
CPU time 1.27 seconds
Started Apr 23 02:09:04 PM PDT 24
Finished Apr 23 02:09:06 PM PDT 24
Peak memory 215952 kb
Host smart-49eb6622-2e25-4c3b-b64e-f71701695eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808506944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3808506944
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.4050060368
Short name T673
Test name
Test status
Simulation time 28716695 ps
CPU time 0.94 seconds
Started Apr 23 02:09:04 PM PDT 24
Finished Apr 23 02:09:05 PM PDT 24
Peak memory 206924 kb
Host smart-91369617-e606-47d6-9101-f3adf2337884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050060368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.4050060368
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3494623876
Short name T755
Test name
Test status
Simulation time 15259644 ps
CPU time 0.94 seconds
Started Apr 23 02:09:00 PM PDT 24
Finished Apr 23 02:09:01 PM PDT 24
Peak memory 216604 kb
Host smart-146351c6-39be-4ac8-ab0d-b78273b89586
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494623876 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3494623876
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2295688856
Short name T716
Test name
Test status
Simulation time 14997904 ps
CPU time 0.93 seconds
Started Apr 23 02:09:04 PM PDT 24
Finished Apr 23 02:09:06 PM PDT 24
Peak memory 218088 kb
Host smart-2e191d79-00e7-48ad-acce-a203deb0ed95
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295688856 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2295688856
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2432660309
Short name T604
Test name
Test status
Simulation time 27596542 ps
CPU time 0.97 seconds
Started Apr 23 02:09:09 PM PDT 24
Finished Apr 23 02:09:10 PM PDT 24
Peak memory 224284 kb
Host smart-9a073c6e-8b60-41de-a28f-a2e41c782207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432660309 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2432660309
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2406250934
Short name T649
Test name
Test status
Simulation time 51431898 ps
CPU time 1.31 seconds
Started Apr 23 02:09:01 PM PDT 24
Finished Apr 23 02:09:03 PM PDT 24
Peak memory 218676 kb
Host smart-bbfb1129-b12e-4517-b7d5-bfbf79e6d7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406250934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2406250934
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.3446236569
Short name T805
Test name
Test status
Simulation time 28920188 ps
CPU time 1.2 seconds
Started Apr 23 02:09:04 PM PDT 24
Finished Apr 23 02:09:06 PM PDT 24
Peak memory 217080 kb
Host smart-eab912a0-3b3a-434a-be8c-7865b114bd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446236569 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3446236569
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2227574505
Short name T216
Test name
Test status
Simulation time 18964882 ps
CPU time 1.03 seconds
Started Apr 23 02:09:02 PM PDT 24
Finished Apr 23 02:09:03 PM PDT 24
Peak memory 207380 kb
Host smart-738a883d-6ef8-41b0-95d1-e4433b884ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227574505 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2227574505
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.4187231846
Short name T678
Test name
Test status
Simulation time 925100462 ps
CPU time 4.9 seconds
Started Apr 23 02:09:01 PM PDT 24
Finished Apr 23 02:09:06 PM PDT 24
Peak memory 217228 kb
Host smart-dc36106f-c807-4809-b733-932f057b78f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187231846 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.4187231846
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1376807607
Short name T628
Test name
Test status
Simulation time 206490378297 ps
CPU time 672.67 seconds
Started Apr 23 02:09:05 PM PDT 24
Finished Apr 23 02:20:18 PM PDT 24
Peak memory 228044 kb
Host smart-72aca412-3182-440a-a396-3b36ac18c9ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376807607 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1376807607
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2456062310
Short name T832
Test name
Test status
Simulation time 60151708 ps
CPU time 1.25 seconds
Started Apr 23 02:11:04 PM PDT 24
Finished Apr 23 02:11:06 PM PDT 24
Peak memory 217336 kb
Host smart-5b43539c-f1bd-48b4-8aed-0ff12dfed332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456062310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2456062310
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3084375773
Short name T814
Test name
Test status
Simulation time 117325690 ps
CPU time 2.6 seconds
Started Apr 23 02:11:12 PM PDT 24
Finished Apr 23 02:11:16 PM PDT 24
Peak memory 220028 kb
Host smart-8647f475-a412-4a9b-bcda-a94c06045c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084375773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3084375773
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1055880066
Short name T281
Test name
Test status
Simulation time 25002039 ps
CPU time 1.26 seconds
Started Apr 23 02:11:13 PM PDT 24
Finished Apr 23 02:11:16 PM PDT 24
Peak memory 217324 kb
Host smart-cd0d770a-591c-432d-838c-73eff87fc289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055880066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1055880066
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.195417255
Short name T2
Test name
Test status
Simulation time 95889846 ps
CPU time 2.23 seconds
Started Apr 23 02:11:04 PM PDT 24
Finished Apr 23 02:11:07 PM PDT 24
Peak memory 218684 kb
Host smart-cef6f814-79ff-49fd-be60-3a19ec40f2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195417255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.195417255
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.27033325
Short name T60
Test name
Test status
Simulation time 72275240 ps
CPU time 1.31 seconds
Started Apr 23 02:11:13 PM PDT 24
Finished Apr 23 02:11:16 PM PDT 24
Peak memory 215440 kb
Host smart-1b134bf5-da92-492c-9ff1-bcab10e2beda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27033325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.27033325
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2130304198
Short name T326
Test name
Test status
Simulation time 28757556 ps
CPU time 1.21 seconds
Started Apr 23 02:11:02 PM PDT 24
Finished Apr 23 02:11:04 PM PDT 24
Peak memory 218304 kb
Host smart-280cd0ef-cd13-479c-a66f-2575d7d6bd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130304198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2130304198
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2772772978
Short name T693
Test name
Test status
Simulation time 60279084 ps
CPU time 1.16 seconds
Started Apr 23 02:11:06 PM PDT 24
Finished Apr 23 02:11:08 PM PDT 24
Peak memory 219940 kb
Host smart-7f88633b-765a-498c-9374-3a3234134120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772772978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2772772978
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2120843764
Short name T62
Test name
Test status
Simulation time 91874851 ps
CPU time 1.23 seconds
Started Apr 23 02:11:14 PM PDT 24
Finished Apr 23 02:11:16 PM PDT 24
Peak memory 218828 kb
Host smart-7ec7ba02-7992-4f4b-b164-ce7cfc0877e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120843764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2120843764
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.82587080
Short name T214
Test name
Test status
Simulation time 473037589 ps
CPU time 3.76 seconds
Started Apr 23 02:11:03 PM PDT 24
Finished Apr 23 02:11:08 PM PDT 24
Peak memory 217536 kb
Host smart-e26d99d6-d9a1-4341-b5bd-dac0eb9ed56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82587080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.82587080
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1407807083
Short name T593
Test name
Test status
Simulation time 62663987 ps
CPU time 1.16 seconds
Started Apr 23 02:11:13 PM PDT 24
Finished Apr 23 02:11:15 PM PDT 24
Peak memory 218484 kb
Host smart-40d8d9a1-f71e-4af7-8892-470f5d9db365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407807083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1407807083
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.4107533889
Short name T149
Test name
Test status
Simulation time 88877114 ps
CPU time 1.26 seconds
Started Apr 23 02:09:09 PM PDT 24
Finished Apr 23 02:09:11 PM PDT 24
Peak memory 215956 kb
Host smart-96fc930a-09fb-4f05-b688-8f260fe8e54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107533889 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.4107533889
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2516037132
Short name T70
Test name
Test status
Simulation time 25648412 ps
CPU time 0.91 seconds
Started Apr 23 02:09:03 PM PDT 24
Finished Apr 23 02:09:05 PM PDT 24
Peak memory 215432 kb
Host smart-f6ad277f-c765-4498-baad-a9b6671c13e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516037132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2516037132
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1336495099
Short name T122
Test name
Test status
Simulation time 60559981 ps
CPU time 0.83 seconds
Started Apr 23 02:09:04 PM PDT 24
Finished Apr 23 02:09:05 PM PDT 24
Peak memory 215568 kb
Host smart-17e6539e-d52f-44b0-a39a-3577cde7baec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336495099 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1336495099
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.2337821988
Short name T118
Test name
Test status
Simulation time 79167178 ps
CPU time 1.22 seconds
Started Apr 23 02:09:09 PM PDT 24
Finished Apr 23 02:09:11 PM PDT 24
Peak memory 226156 kb
Host smart-7c0ee618-2f6f-4eab-a5dc-35ec9c8e7041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337821988 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2337821988
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.729293122
Short name T736
Test name
Test status
Simulation time 33256294 ps
CPU time 1.14 seconds
Started Apr 23 02:09:04 PM PDT 24
Finished Apr 23 02:09:06 PM PDT 24
Peak memory 217212 kb
Host smart-2e4007ba-64de-44b2-9bf7-f4117f241d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729293122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.729293122
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.1502278170
Short name T711
Test name
Test status
Simulation time 21560442 ps
CPU time 1.18 seconds
Started Apr 23 02:09:08 PM PDT 24
Finished Apr 23 02:09:10 PM PDT 24
Peak memory 224556 kb
Host smart-fc446f05-7b49-444d-b3a4-ac7ea62faa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502278170 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1502278170
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.430121562
Short name T563
Test name
Test status
Simulation time 29128376 ps
CPU time 1.01 seconds
Started Apr 23 02:09:01 PM PDT 24
Finished Apr 23 02:09:02 PM PDT 24
Peak memory 215580 kb
Host smart-44fc10a9-b9c9-49d7-82ca-9a11c256ad55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430121562 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.430121562
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.68875189
Short name T576
Test name
Test status
Simulation time 1006357576 ps
CPU time 4.44 seconds
Started Apr 23 02:09:09 PM PDT 24
Finished Apr 23 02:09:14 PM PDT 24
Peak memory 215584 kb
Host smart-14a9ba2c-a512-4cd9-b8bc-83e6ac996ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68875189 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.68875189
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3878375372
Short name T645
Test name
Test status
Simulation time 25126601140 ps
CPU time 639.39 seconds
Started Apr 23 02:09:08 PM PDT 24
Finished Apr 23 02:19:49 PM PDT 24
Peak memory 218700 kb
Host smart-8c902f36-2185-4fd1-a2dd-3a49f70a268d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878375372 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3878375372
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2570140413
Short name T572
Test name
Test status
Simulation time 132826488 ps
CPU time 1.53 seconds
Started Apr 23 02:11:02 PM PDT 24
Finished Apr 23 02:11:05 PM PDT 24
Peak memory 218672 kb
Host smart-9b266705-55ae-4b27-81eb-f2a8bbb591ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570140413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2570140413
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2257066144
Short name T837
Test name
Test status
Simulation time 33088168 ps
CPU time 1.31 seconds
Started Apr 23 02:11:03 PM PDT 24
Finished Apr 23 02:11:05 PM PDT 24
Peak memory 217148 kb
Host smart-3f8543a8-a6e7-443a-9848-6810c217268f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257066144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2257066144
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1618963169
Short name T284
Test name
Test status
Simulation time 88424680 ps
CPU time 1.37 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:13 PM PDT 24
Peak memory 219300 kb
Host smart-d98d6f5b-7a21-4057-baa3-7e28ea2aed26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618963169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1618963169
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2035197897
Short name T277
Test name
Test status
Simulation time 50666440 ps
CPU time 1.17 seconds
Started Apr 23 02:11:14 PM PDT 24
Finished Apr 23 02:11:17 PM PDT 24
Peak memory 218696 kb
Host smart-74d08e52-3fac-4267-9f94-b314897bc7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035197897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2035197897
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2556743581
Short name T517
Test name
Test status
Simulation time 33908906 ps
CPU time 1.04 seconds
Started Apr 23 02:11:01 PM PDT 24
Finished Apr 23 02:11:03 PM PDT 24
Peak memory 217168 kb
Host smart-62cf5073-fbe3-4e79-8472-3b0d30a6ac70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556743581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2556743581
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2062157344
Short name T650
Test name
Test status
Simulation time 39618170 ps
CPU time 1.33 seconds
Started Apr 23 02:11:13 PM PDT 24
Finished Apr 23 02:11:15 PM PDT 24
Peak memory 217068 kb
Host smart-2d18aa88-61d5-4981-86ba-3542dfe08dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062157344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2062157344
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.4160552767
Short name T11
Test name
Test status
Simulation time 81314421 ps
CPU time 1.15 seconds
Started Apr 23 02:11:03 PM PDT 24
Finished Apr 23 02:11:04 PM PDT 24
Peak memory 219788 kb
Host smart-370ebf73-77be-44fc-9f8c-c3d9b1f06fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160552767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.4160552767
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2246830492
Short name T40
Test name
Test status
Simulation time 188406281 ps
CPU time 1.39 seconds
Started Apr 23 02:11:06 PM PDT 24
Finished Apr 23 02:11:08 PM PDT 24
Peak memory 217232 kb
Host smart-7a505582-4ccf-4c00-9955-13a978e17269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246830492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2246830492
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.146635800
Short name T556
Test name
Test status
Simulation time 54581947 ps
CPU time 1.22 seconds
Started Apr 23 02:11:07 PM PDT 24
Finished Apr 23 02:11:09 PM PDT 24
Peak memory 218744 kb
Host smart-14f080f0-d5ef-4bb5-a737-6158b19f99e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146635800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.146635800
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.3424959390
Short name T133
Test name
Test status
Simulation time 28585570 ps
CPU time 1.36 seconds
Started Apr 23 02:09:06 PM PDT 24
Finished Apr 23 02:09:08 PM PDT 24
Peak memory 215972 kb
Host smart-dc5404e1-b401-4ab4-8169-ec56b7a619c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424959390 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3424959390
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.366477512
Short name T343
Test name
Test status
Simulation time 19807991 ps
CPU time 1.01 seconds
Started Apr 23 02:09:08 PM PDT 24
Finished Apr 23 02:09:10 PM PDT 24
Peak memory 206864 kb
Host smart-60169fd6-e438-4dea-928d-82625185b51b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366477512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.366477512
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2852350434
Short name T661
Test name
Test status
Simulation time 25437187 ps
CPU time 0.79 seconds
Started Apr 23 02:09:06 PM PDT 24
Finished Apr 23 02:09:08 PM PDT 24
Peak memory 216076 kb
Host smart-3b633e15-024a-4c55-9738-e3a010e044bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852350434 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2852350434
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.4271091608
Short name T468
Test name
Test status
Simulation time 40743962 ps
CPU time 1.04 seconds
Started Apr 23 02:09:06 PM PDT 24
Finished Apr 23 02:09:08 PM PDT 24
Peak memory 218548 kb
Host smart-57ecf683-ac73-4f02-89d3-1199e06bd320
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271091608 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.4271091608
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1084575671
Short name T442
Test name
Test status
Simulation time 36711724 ps
CPU time 0.94 seconds
Started Apr 23 02:09:10 PM PDT 24
Finished Apr 23 02:09:11 PM PDT 24
Peak memory 218868 kb
Host smart-aabafcbf-c44a-4c77-ad10-751b4ed75cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084575671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1084575671
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1878346395
Short name T811
Test name
Test status
Simulation time 36261227 ps
CPU time 1.47 seconds
Started Apr 23 02:09:06 PM PDT 24
Finished Apr 23 02:09:08 PM PDT 24
Peak memory 217316 kb
Host smart-4c34695e-680c-4f9e-add2-60901bd5935e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878346395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1878346395
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3765377655
Short name T725
Test name
Test status
Simulation time 31944560 ps
CPU time 0.88 seconds
Started Apr 23 02:09:07 PM PDT 24
Finished Apr 23 02:09:08 PM PDT 24
Peak memory 215764 kb
Host smart-73397dba-2ee4-4946-a496-9093d798599a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765377655 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3765377655
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.197681848
Short name T213
Test name
Test status
Simulation time 17847887 ps
CPU time 1.03 seconds
Started Apr 23 02:09:03 PM PDT 24
Finished Apr 23 02:09:04 PM PDT 24
Peak memory 214960 kb
Host smart-262e060d-b834-45b6-af4a-f03e4be357fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197681848 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.197681848
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1975633827
Short name T222
Test name
Test status
Simulation time 300196381 ps
CPU time 2.28 seconds
Started Apr 23 02:09:06 PM PDT 24
Finished Apr 23 02:09:09 PM PDT 24
Peak memory 215484 kb
Host smart-37cc8831-fd5c-4594-b695-c75d1b38a073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975633827 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1975633827
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3448496390
Short name T205
Test name
Test status
Simulation time 38728558328 ps
CPU time 882.87 seconds
Started Apr 23 02:09:08 PM PDT 24
Finished Apr 23 02:23:51 PM PDT 24
Peak memory 218640 kb
Host smart-2eb24121-702c-4e6d-9a05-bc9e89b47dc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448496390 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3448496390
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1952573937
Short name T758
Test name
Test status
Simulation time 142911700 ps
CPU time 1.15 seconds
Started Apr 23 02:11:06 PM PDT 24
Finished Apr 23 02:11:08 PM PDT 24
Peak memory 218720 kb
Host smart-261e59e5-9e96-4166-9af8-e8bccb054de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952573937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1952573937
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2599605783
Short name T574
Test name
Test status
Simulation time 31925481 ps
CPU time 1.3 seconds
Started Apr 23 02:11:04 PM PDT 24
Finished Apr 23 02:11:06 PM PDT 24
Peak memory 218368 kb
Host smart-b24c8609-e441-4cc0-b5c8-88b846832a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599605783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2599605783
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3718003943
Short name T616
Test name
Test status
Simulation time 35389019 ps
CPU time 1.31 seconds
Started Apr 23 02:11:02 PM PDT 24
Finished Apr 23 02:11:04 PM PDT 24
Peak memory 217412 kb
Host smart-46bdc591-8fc4-41ef-b8bb-5ee41ab3662b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718003943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3718003943
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.4069567225
Short name T776
Test name
Test status
Simulation time 112794528 ps
CPU time 1.33 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:12 PM PDT 24
Peak memory 217328 kb
Host smart-1db0fca9-d3e1-4082-b974-ab57dfdf1bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069567225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.4069567225
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.60441371
Short name T652
Test name
Test status
Simulation time 39900416 ps
CPU time 1.42 seconds
Started Apr 23 02:11:04 PM PDT 24
Finished Apr 23 02:11:07 PM PDT 24
Peak memory 218396 kb
Host smart-e0de5425-3093-4638-afe4-a43d25f5d8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60441371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.60441371
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1365504723
Short name T376
Test name
Test status
Simulation time 80251673 ps
CPU time 1.09 seconds
Started Apr 23 02:11:14 PM PDT 24
Finished Apr 23 02:11:16 PM PDT 24
Peak memory 217072 kb
Host smart-b10bbeb2-5e09-429c-9af2-83ea602080a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365504723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1365504723
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2221336772
Short name T64
Test name
Test status
Simulation time 59571586 ps
CPU time 1.56 seconds
Started Apr 23 02:11:13 PM PDT 24
Finished Apr 23 02:11:15 PM PDT 24
Peak memory 218764 kb
Host smart-70e2d0fb-7a18-4db8-9092-29822c78f122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221336772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2221336772
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1875885978
Short name T436
Test name
Test status
Simulation time 43309864 ps
CPU time 1.9 seconds
Started Apr 23 02:11:10 PM PDT 24
Finished Apr 23 02:11:12 PM PDT 24
Peak memory 218568 kb
Host smart-36d15304-5474-4263-be55-c6caea63962e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875885978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1875885978
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.995982285
Short name T484
Test name
Test status
Simulation time 32754332 ps
CPU time 1.17 seconds
Started Apr 23 02:11:12 PM PDT 24
Finished Apr 23 02:11:14 PM PDT 24
Peak memory 218524 kb
Host smart-f59b2c12-bd42-4a79-8d77-317a7cf5e3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995982285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.995982285
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3946967861
Short name T361
Test name
Test status
Simulation time 44301577 ps
CPU time 1.67 seconds
Started Apr 23 02:11:06 PM PDT 24
Finished Apr 23 02:11:09 PM PDT 24
Peak memory 218636 kb
Host smart-e3a111db-a118-4498-8c0d-6317dd91f2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946967861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3946967861
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2998935467
Short name T617
Test name
Test status
Simulation time 62851350 ps
CPU time 1.12 seconds
Started Apr 23 02:07:58 PM PDT 24
Finished Apr 23 02:07:59 PM PDT 24
Peak memory 215952 kb
Host smart-75cdf4e6-3c78-4432-8550-557f98c3ed55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998935467 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2998935467
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2192991164
Short name T710
Test name
Test status
Simulation time 43644628 ps
CPU time 0.92 seconds
Started Apr 23 02:08:03 PM PDT 24
Finished Apr 23 02:08:04 PM PDT 24
Peak memory 215112 kb
Host smart-039447e7-86bc-4df7-9d8c-ce56e227ee8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192991164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2192991164
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.920576730
Short name T100
Test name
Test status
Simulation time 47363729 ps
CPU time 1.15 seconds
Started Apr 23 02:08:05 PM PDT 24
Finished Apr 23 02:08:06 PM PDT 24
Peak memory 217048 kb
Host smart-13afeaca-1433-4701-9d5c-5406c0182a83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920576730 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.920576730
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1352780916
Short name T103
Test name
Test status
Simulation time 27383112 ps
CPU time 1.25 seconds
Started Apr 23 02:08:02 PM PDT 24
Finished Apr 23 02:08:04 PM PDT 24
Peak memory 219360 kb
Host smart-ee31e792-de2b-4bab-93a0-00aa24a08836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352780916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1352780916
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.456087203
Short name T614
Test name
Test status
Simulation time 167319494 ps
CPU time 2.53 seconds
Started Apr 23 02:07:59 PM PDT 24
Finished Apr 23 02:08:02 PM PDT 24
Peak memory 219608 kb
Host smart-910c645e-0839-4aa1-8442-e0adcb9ca7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456087203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.456087203
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.651122262
Short name T87
Test name
Test status
Simulation time 21878260 ps
CPU time 1.13 seconds
Started Apr 23 02:08:01 PM PDT 24
Finished Apr 23 02:08:02 PM PDT 24
Peak memory 216156 kb
Host smart-cf1903f3-092b-44e5-84cd-e54c77806822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651122262 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.651122262
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1980943073
Short name T16
Test name
Test status
Simulation time 1852381993 ps
CPU time 7.87 seconds
Started Apr 23 02:08:04 PM PDT 24
Finished Apr 23 02:08:12 PM PDT 24
Peak memory 244316 kb
Host smart-8e7243de-eab1-46c1-9a18-7a0dad469901
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980943073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1980943073
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3448986125
Short name T308
Test name
Test status
Simulation time 46896560 ps
CPU time 0.92 seconds
Started Apr 23 02:08:05 PM PDT 24
Finished Apr 23 02:08:07 PM PDT 24
Peak memory 215484 kb
Host smart-b7a78a45-8668-492f-a7f8-95839de2cdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448986125 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3448986125
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.25178364
Short name T568
Test name
Test status
Simulation time 324906386 ps
CPU time 1.14 seconds
Started Apr 23 02:08:06 PM PDT 24
Finished Apr 23 02:08:07 PM PDT 24
Peak memory 206464 kb
Host smart-ae33c676-6c89-4794-88d5-556ac97ca861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25178364 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.25178364
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3759425988
Short name T775
Test name
Test status
Simulation time 18996805636 ps
CPU time 360.48 seconds
Started Apr 23 02:08:06 PM PDT 24
Finished Apr 23 02:14:08 PM PDT 24
Peak memory 218100 kb
Host smart-952b2af1-2c37-4858-860f-3c705d08d886
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759425988 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3759425988
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3600641631
Short name T731
Test name
Test status
Simulation time 86901368 ps
CPU time 1.18 seconds
Started Apr 23 02:09:05 PM PDT 24
Finished Apr 23 02:09:07 PM PDT 24
Peak memory 215960 kb
Host smart-f7b93d27-2a4b-4f0e-a271-ab071cb00873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600641631 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3600641631
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2484206227
Short name T518
Test name
Test status
Simulation time 32114784 ps
CPU time 0.88 seconds
Started Apr 23 02:09:16 PM PDT 24
Finished Apr 23 02:09:18 PM PDT 24
Peak memory 206828 kb
Host smart-882912e8-3813-4979-8d6b-0884f531136b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484206227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2484206227
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_err.3852476218
Short name T162
Test name
Test status
Simulation time 42883629 ps
CPU time 1.14 seconds
Started Apr 23 02:09:08 PM PDT 24
Finished Apr 23 02:09:09 PM PDT 24
Peak memory 219856 kb
Host smart-a03365a8-933f-44cd-973c-48e56e8ce8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852476218 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3852476218
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_intr.4086119991
Short name T622
Test name
Test status
Simulation time 69420005 ps
CPU time 0.89 seconds
Started Apr 23 02:09:09 PM PDT 24
Finished Apr 23 02:09:11 PM PDT 24
Peak memory 215808 kb
Host smart-a4d09648-6fdb-456f-bd17-211fc4932b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086119991 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.4086119991
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2582485877
Short name T779
Test name
Test status
Simulation time 155605033 ps
CPU time 0.94 seconds
Started Apr 23 02:09:08 PM PDT 24
Finished Apr 23 02:09:10 PM PDT 24
Peak memory 215444 kb
Host smart-8ab735a4-1fae-4f09-9ac4-c3b93363cf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582485877 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2582485877
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3939227578
Short name T155
Test name
Test status
Simulation time 382780144 ps
CPU time 7.51 seconds
Started Apr 23 02:09:07 PM PDT 24
Finished Apr 23 02:09:15 PM PDT 24
Peak memory 218568 kb
Host smart-3935bd43-3b0a-46d1-be42-d5229e98ce7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939227578 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3939227578
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1224621814
Short name T193
Test name
Test status
Simulation time 53339224749 ps
CPU time 714.15 seconds
Started Apr 23 02:09:08 PM PDT 24
Finished Apr 23 02:21:03 PM PDT 24
Peak memory 220572 kb
Host smart-001425ba-bd04-4e51-abbf-8bab9095c9e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224621814 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1224621814
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.36180637
Short name T549
Test name
Test status
Simulation time 40511231 ps
CPU time 1.22 seconds
Started Apr 23 02:09:13 PM PDT 24
Finished Apr 23 02:09:14 PM PDT 24
Peak memory 215940 kb
Host smart-5d7bea48-b8d7-40a3-8204-60b50a660d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36180637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.36180637
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.819939787
Short name T349
Test name
Test status
Simulation time 43621786 ps
CPU time 0.87 seconds
Started Apr 23 02:09:14 PM PDT 24
Finished Apr 23 02:09:15 PM PDT 24
Peak memory 206916 kb
Host smart-6d771a2a-b28b-4aaf-af68-94c36521fa0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819939787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.819939787
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1864681935
Short name T591
Test name
Test status
Simulation time 63045422 ps
CPU time 1.35 seconds
Started Apr 23 02:09:10 PM PDT 24
Finished Apr 23 02:09:12 PM PDT 24
Peak memory 217136 kb
Host smart-ab43f2e6-7178-4ab2-9fd0-e4a9124dc974
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864681935 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1864681935
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3945796804
Short name T613
Test name
Test status
Simulation time 28956427 ps
CPU time 0.97 seconds
Started Apr 23 02:09:10 PM PDT 24
Finished Apr 23 02:09:12 PM PDT 24
Peak memory 224140 kb
Host smart-4b2279b5-a6ad-4d37-8980-35926add8530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945796804 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3945796804
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2247894146
Short name T258
Test name
Test status
Simulation time 57805538 ps
CPU time 1.25 seconds
Started Apr 23 02:09:10 PM PDT 24
Finished Apr 23 02:09:12 PM PDT 24
Peak memory 218904 kb
Host smart-cadc63d3-e5fe-4631-9272-f354979c4618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247894146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2247894146
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3142125189
Short name T597
Test name
Test status
Simulation time 33173961 ps
CPU time 1.08 seconds
Started Apr 23 02:09:17 PM PDT 24
Finished Apr 23 02:09:18 PM PDT 24
Peak memory 224316 kb
Host smart-497c6812-e67e-4d2d-8896-50dc381924b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142125189 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3142125189
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1543664874
Short name T792
Test name
Test status
Simulation time 37705734 ps
CPU time 0.87 seconds
Started Apr 23 02:09:10 PM PDT 24
Finished Apr 23 02:09:11 PM PDT 24
Peak memory 215512 kb
Host smart-43e7829a-9c94-4bbf-8282-af3d140daeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543664874 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1543664874
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3646919417
Short name T154
Test name
Test status
Simulation time 558462663 ps
CPU time 5.43 seconds
Started Apr 23 02:09:11 PM PDT 24
Finished Apr 23 02:09:17 PM PDT 24
Peak memory 220312 kb
Host smart-dc9ed95c-68f7-48e7-94d2-ab98decb25f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646919417 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3646919417
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2278664685
Short name T199
Test name
Test status
Simulation time 127664741616 ps
CPU time 1364.47 seconds
Started Apr 23 02:09:11 PM PDT 24
Finished Apr 23 02:31:56 PM PDT 24
Peak memory 222440 kb
Host smart-61a665c6-f837-44cc-bac0-a2a770eb1d53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278664685 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2278664685
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1496567024
Short name T439
Test name
Test status
Simulation time 77809335 ps
CPU time 1.2 seconds
Started Apr 23 02:09:10 PM PDT 24
Finished Apr 23 02:09:12 PM PDT 24
Peak memory 215904 kb
Host smart-5426a526-151c-4a02-b6b0-172900c537ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496567024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1496567024
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.568385229
Short name T391
Test name
Test status
Simulation time 35037381 ps
CPU time 0.83 seconds
Started Apr 23 02:09:13 PM PDT 24
Finished Apr 23 02:09:14 PM PDT 24
Peak memory 214856 kb
Host smart-cc2401bb-ddd3-440f-9bb8-179364af3278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568385229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.568385229
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3418256021
Short name T567
Test name
Test status
Simulation time 30861236 ps
CPU time 0.89 seconds
Started Apr 23 02:09:12 PM PDT 24
Finished Apr 23 02:09:13 PM PDT 24
Peak memory 216520 kb
Host smart-f6021b95-93d6-42d6-a3e8-8ca684d6d6be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418256021 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3418256021
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.2864284266
Short name T92
Test name
Test status
Simulation time 21078129 ps
CPU time 1.32 seconds
Started Apr 23 02:09:13 PM PDT 24
Finished Apr 23 02:09:14 PM PDT 24
Peak memory 230036 kb
Host smart-0db071b4-fd65-4679-a384-3f3998670783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864284266 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2864284266
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2626292929
Short name T369
Test name
Test status
Simulation time 72860476 ps
CPU time 1.59 seconds
Started Apr 23 02:09:14 PM PDT 24
Finished Apr 23 02:09:16 PM PDT 24
Peak memory 218576 kb
Host smart-07544423-3898-41a3-8688-070d68304364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626292929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2626292929
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2304005679
Short name T449
Test name
Test status
Simulation time 39327240 ps
CPU time 0.95 seconds
Started Apr 23 02:09:10 PM PDT 24
Finished Apr 23 02:09:12 PM PDT 24
Peak memory 215888 kb
Host smart-a688d126-2286-4298-b5cf-57aefb40d32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304005679 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2304005679
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.995204071
Short name T336
Test name
Test status
Simulation time 15491800 ps
CPU time 1 seconds
Started Apr 23 02:09:09 PM PDT 24
Finished Apr 23 02:09:11 PM PDT 24
Peak memory 215560 kb
Host smart-5dc931af-8e99-4a28-9b52-288a7857a95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995204071 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.995204071
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1615077294
Short name T612
Test name
Test status
Simulation time 342640186 ps
CPU time 6.6 seconds
Started Apr 23 02:09:12 PM PDT 24
Finished Apr 23 02:09:19 PM PDT 24
Peak memory 217132 kb
Host smart-15fb7663-b9aa-41d9-8d77-bda10bcf81f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615077294 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1615077294
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1970312931
Short name T732
Test name
Test status
Simulation time 153498598621 ps
CPU time 841.03 seconds
Started Apr 23 02:09:12 PM PDT 24
Finished Apr 23 02:23:14 PM PDT 24
Peak memory 220576 kb
Host smart-bd75279f-552a-4203-b42d-022705bf71b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970312931 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1970312931
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2304690708
Short name T759
Test name
Test status
Simulation time 27397091 ps
CPU time 1.36 seconds
Started Apr 23 02:09:14 PM PDT 24
Finished Apr 23 02:09:16 PM PDT 24
Peak memory 215916 kb
Host smart-3aaf1cc3-7a8b-4fb6-86fa-ba4dddcbb36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304690708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2304690708
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.4068584391
Short name T320
Test name
Test status
Simulation time 18017320 ps
CPU time 0.99 seconds
Started Apr 23 02:09:14 PM PDT 24
Finished Apr 23 02:09:16 PM PDT 24
Peak memory 215524 kb
Host smart-6ddfd411-edff-422b-9b1d-a06933da3c54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068584391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.4068584391
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_err.419454323
Short name T125
Test name
Test status
Simulation time 31712179 ps
CPU time 0.88 seconds
Started Apr 23 02:09:11 PM PDT 24
Finished Apr 23 02:09:13 PM PDT 24
Peak memory 218788 kb
Host smart-c1ee7e61-29d2-4d3c-856d-156be65706a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419454323 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.419454323
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1863804919
Short name T822
Test name
Test status
Simulation time 219911027 ps
CPU time 1.33 seconds
Started Apr 23 02:09:15 PM PDT 24
Finished Apr 23 02:09:17 PM PDT 24
Peak memory 218848 kb
Host smart-db0f59be-a14f-40ae-852a-b4a7c388ebb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863804919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1863804919
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1614009261
Short name T84
Test name
Test status
Simulation time 35320479 ps
CPU time 0.98 seconds
Started Apr 23 02:09:14 PM PDT 24
Finished Apr 23 02:09:16 PM PDT 24
Peak memory 216132 kb
Host smart-2ed099a0-fe78-4fbd-bb7d-f1bca204ca13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614009261 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1614009261
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3909106001
Short name T471
Test name
Test status
Simulation time 90341763 ps
CPU time 0.93 seconds
Started Apr 23 02:09:14 PM PDT 24
Finished Apr 23 02:09:16 PM PDT 24
Peak memory 215556 kb
Host smart-dc2720bf-86f5-44a2-b40b-c209945738cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909106001 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3909106001
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3093773803
Short name T519
Test name
Test status
Simulation time 568510710 ps
CPU time 3.73 seconds
Started Apr 23 02:09:17 PM PDT 24
Finished Apr 23 02:09:22 PM PDT 24
Peak memory 215520 kb
Host smart-27e2650c-4cc5-4be4-a626-ba7679461783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093773803 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3093773803
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_alert.2401628595
Short name T750
Test name
Test status
Simulation time 63495957 ps
CPU time 1.32 seconds
Started Apr 23 02:09:17 PM PDT 24
Finished Apr 23 02:09:19 PM PDT 24
Peak memory 215904 kb
Host smart-4f168c37-444c-4f98-ae4c-749ea51c6be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401628595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2401628595
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1541604463
Short name T50
Test name
Test status
Simulation time 17485002 ps
CPU time 0.94 seconds
Started Apr 23 02:09:15 PM PDT 24
Finished Apr 23 02:09:16 PM PDT 24
Peak memory 206884 kb
Host smart-13dea4ff-e9c0-4163-b1d4-a7fca3cf406a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541604463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1541604463
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3337683232
Short name T777
Test name
Test status
Simulation time 22342517 ps
CPU time 0.86 seconds
Started Apr 23 02:09:17 PM PDT 24
Finished Apr 23 02:09:19 PM PDT 24
Peak memory 216144 kb
Host smart-e53f486a-dfd4-4dce-adf3-84934accf13f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337683232 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3337683232
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1773920232
Short name T511
Test name
Test status
Simulation time 37750497 ps
CPU time 1.35 seconds
Started Apr 23 02:09:15 PM PDT 24
Finished Apr 23 02:09:17 PM PDT 24
Peak memory 217232 kb
Host smart-921ce5ab-187e-48ba-9faa-f032aa9c7093
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773920232 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1773920232
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3659772100
Short name T452
Test name
Test status
Simulation time 20245798 ps
CPU time 1.17 seconds
Started Apr 23 02:09:17 PM PDT 24
Finished Apr 23 02:09:19 PM PDT 24
Peak memory 224384 kb
Host smart-cbc364fc-04e2-4d2d-a96d-d93586926d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659772100 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3659772100
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.4113035178
Short name T796
Test name
Test status
Simulation time 85289616 ps
CPU time 1.54 seconds
Started Apr 23 02:09:14 PM PDT 24
Finished Apr 23 02:09:16 PM PDT 24
Peak memory 218864 kb
Host smart-fc2123f9-93b9-466f-ba63-6f1fccc500ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113035178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.4113035178
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.538661988
Short name T403
Test name
Test status
Simulation time 20822741 ps
CPU time 1.21 seconds
Started Apr 23 02:09:14 PM PDT 24
Finished Apr 23 02:09:16 PM PDT 24
Peak memory 224408 kb
Host smart-16245eb9-3e89-432e-8043-22f4d50ae3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538661988 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.538661988
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3109316417
Short name T737
Test name
Test status
Simulation time 27003210 ps
CPU time 0.92 seconds
Started Apr 23 02:09:15 PM PDT 24
Finished Apr 23 02:09:17 PM PDT 24
Peak memory 215452 kb
Host smart-a37ce0dd-269b-4ba0-89e7-c43ee16a9c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109316417 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3109316417
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1940121522
Short name T220
Test name
Test status
Simulation time 244916990 ps
CPU time 4.27 seconds
Started Apr 23 02:09:12 PM PDT 24
Finished Apr 23 02:09:16 PM PDT 24
Peak memory 215492 kb
Host smart-c73bf198-a6d7-4bf4-822c-283148f823cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940121522 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1940121522
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.4030077208
Short name T194
Test name
Test status
Simulation time 19349935688 ps
CPU time 443.84 seconds
Started Apr 23 02:09:24 PM PDT 24
Finished Apr 23 02:16:48 PM PDT 24
Peak memory 222516 kb
Host smart-6a7dccd7-7248-487e-9a66-69e364ab5571
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030077208 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.4030077208
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.659461533
Short name T134
Test name
Test status
Simulation time 26302712 ps
CPU time 1.19 seconds
Started Apr 23 02:09:16 PM PDT 24
Finished Apr 23 02:09:17 PM PDT 24
Peak memory 215896 kb
Host smart-eac5abfc-4f56-4fe3-a3bb-d45804598176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659461533 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.659461533
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2893024680
Short name T71
Test name
Test status
Simulation time 34493541 ps
CPU time 0.96 seconds
Started Apr 23 02:09:21 PM PDT 24
Finished Apr 23 02:09:23 PM PDT 24
Peak memory 206868 kb
Host smart-043e8d4f-8fe9-4e63-84e8-ac1f79bcf5be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893024680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2893024680
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2513608203
Short name T26
Test name
Test status
Simulation time 11347441 ps
CPU time 0.88 seconds
Started Apr 23 02:09:20 PM PDT 24
Finished Apr 23 02:09:21 PM PDT 24
Peak memory 216500 kb
Host smart-1d990284-4304-4624-9881-921b3d758363
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513608203 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2513608203
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.728182571
Short name T688
Test name
Test status
Simulation time 31087265 ps
CPU time 1.16 seconds
Started Apr 23 02:09:20 PM PDT 24
Finished Apr 23 02:09:22 PM PDT 24
Peak memory 219560 kb
Host smart-06e20555-321d-478c-bda1-d51b6658927a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728182571 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.728182571
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3461515541
Short name T126
Test name
Test status
Simulation time 37604365 ps
CPU time 1.23 seconds
Started Apr 23 02:09:17 PM PDT 24
Finished Apr 23 02:09:19 PM PDT 24
Peak memory 226088 kb
Host smart-3c61f6ba-1172-4646-b050-08f5fe10ed67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461515541 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3461515541
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2410630852
Short name T372
Test name
Test status
Simulation time 34972878 ps
CPU time 1.35 seconds
Started Apr 23 02:09:16 PM PDT 24
Finished Apr 23 02:09:18 PM PDT 24
Peak memory 220016 kb
Host smart-52104bc2-a89d-42c0-a338-63fc5ca249d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410630852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2410630852
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3919225073
Short name T30
Test name
Test status
Simulation time 20174848 ps
CPU time 0.98 seconds
Started Apr 23 02:09:16 PM PDT 24
Finished Apr 23 02:09:17 PM PDT 24
Peak memory 216068 kb
Host smart-116acfc1-4da0-482f-a5cb-a46c644ec214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919225073 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3919225073
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.174805384
Short name T494
Test name
Test status
Simulation time 15699643 ps
CPU time 0.98 seconds
Started Apr 23 02:09:18 PM PDT 24
Finished Apr 23 02:09:20 PM PDT 24
Peak memory 215564 kb
Host smart-1c0910c0-7150-4ff1-8b2e-55709f1afea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174805384 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.174805384
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.3613529212
Short name T285
Test name
Test status
Simulation time 397245989 ps
CPU time 4.72 seconds
Started Apr 23 02:09:18 PM PDT 24
Finished Apr 23 02:09:23 PM PDT 24
Peak memory 217112 kb
Host smart-b14f94be-4b2b-47c6-ad63-9dd4c7b5feea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613529212 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3613529212
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2897092693
Short name T830
Test name
Test status
Simulation time 25633677642 ps
CPU time 578.53 seconds
Started Apr 23 02:09:17 PM PDT 24
Finished Apr 23 02:18:56 PM PDT 24
Peak memory 218064 kb
Host smart-fc6a2516-9319-4927-a0a0-18eefa80a060
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897092693 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2897092693
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1988991565
Short name T719
Test name
Test status
Simulation time 78961042 ps
CPU time 1.31 seconds
Started Apr 23 02:09:21 PM PDT 24
Finished Apr 23 02:09:23 PM PDT 24
Peak memory 215792 kb
Host smart-95915a69-a566-4e0f-b86b-acc89b2c32a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988991565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1988991565
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2011652578
Short name T402
Test name
Test status
Simulation time 122148718 ps
CPU time 0.77 seconds
Started Apr 23 02:09:23 PM PDT 24
Finished Apr 23 02:09:24 PM PDT 24
Peak memory 206564 kb
Host smart-b4d9314e-7e3a-4623-80b8-c2e0054ca88b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011652578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2011652578
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1820197096
Short name T188
Test name
Test status
Simulation time 27052458 ps
CPU time 0.81 seconds
Started Apr 23 02:09:21 PM PDT 24
Finished Apr 23 02:09:22 PM PDT 24
Peak memory 215624 kb
Host smart-4f56f073-05ab-4f4f-97a9-0d1b7ca63a92
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820197096 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1820197096
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3841311392
Short name T477
Test name
Test status
Simulation time 141467953 ps
CPU time 1.28 seconds
Started Apr 23 02:09:20 PM PDT 24
Finished Apr 23 02:09:21 PM PDT 24
Peak memory 217288 kb
Host smart-06d828a6-e4ea-4f64-82d3-b92c1c1697b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841311392 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3841311392
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.4291392493
Short name T142
Test name
Test status
Simulation time 50979451 ps
CPU time 0.8 seconds
Started Apr 23 02:09:22 PM PDT 24
Finished Apr 23 02:09:23 PM PDT 24
Peak memory 218332 kb
Host smart-8a71f5a4-8b68-4002-bc42-16d1af005d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291392493 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.4291392493
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2889581116
Short name T22
Test name
Test status
Simulation time 58492615 ps
CPU time 1 seconds
Started Apr 23 02:09:18 PM PDT 24
Finished Apr 23 02:09:20 PM PDT 24
Peak memory 217172 kb
Host smart-e5ad5233-6df8-4260-8493-a92f508255b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889581116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2889581116
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.35589569
Short name T797
Test name
Test status
Simulation time 31476454 ps
CPU time 0.84 seconds
Started Apr 23 02:09:19 PM PDT 24
Finished Apr 23 02:09:20 PM PDT 24
Peak memory 215744 kb
Host smart-9b10c76a-047b-430c-afea-5b51a9c40ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35589569 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.35589569
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3847847905
Short name T450
Test name
Test status
Simulation time 19146742 ps
CPU time 1.02 seconds
Started Apr 23 02:09:19 PM PDT 24
Finished Apr 23 02:09:20 PM PDT 24
Peak memory 215568 kb
Host smart-c9a86c30-51c1-45c3-8ede-2917c52a8a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847847905 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3847847905
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2984242584
Short name T152
Test name
Test status
Simulation time 571895089 ps
CPU time 3.37 seconds
Started Apr 23 02:09:23 PM PDT 24
Finished Apr 23 02:09:27 PM PDT 24
Peak memory 215572 kb
Host smart-9e0128a5-af8e-4247-8b91-db5cf2dbecee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984242584 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2984242584
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3704763195
Short name T798
Test name
Test status
Simulation time 23520985802 ps
CPU time 596.08 seconds
Started Apr 23 02:09:23 PM PDT 24
Finished Apr 23 02:19:20 PM PDT 24
Peak memory 218124 kb
Host smart-754c59c0-14e8-4573-a09e-7241a232a50a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704763195 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3704763195
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1350976485
Short name T264
Test name
Test status
Simulation time 85139559 ps
CPU time 1.22 seconds
Started Apr 23 02:09:24 PM PDT 24
Finished Apr 23 02:09:26 PM PDT 24
Peak memory 215944 kb
Host smart-1a623251-3f25-4f7b-a99e-d5cd973b111e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350976485 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1350976485
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.737605990
Short name T658
Test name
Test status
Simulation time 23300177 ps
CPU time 1.06 seconds
Started Apr 23 02:09:26 PM PDT 24
Finished Apr 23 02:09:28 PM PDT 24
Peak memory 215092 kb
Host smart-c7810d56-7466-480a-89a1-ec4f6af0b3e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737605990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.737605990
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1658790249
Short name T671
Test name
Test status
Simulation time 54428129 ps
CPU time 0.88 seconds
Started Apr 23 02:09:22 PM PDT 24
Finished Apr 23 02:09:23 PM PDT 24
Peak memory 216416 kb
Host smart-3d7c5804-f3d3-4396-b801-590733cc93b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658790249 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1658790249
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_err.1438344934
Short name T379
Test name
Test status
Simulation time 19008018 ps
CPU time 1.06 seconds
Started Apr 23 02:09:22 PM PDT 24
Finished Apr 23 02:09:24 PM PDT 24
Peak memory 218480 kb
Host smart-5acf9911-557a-4a8b-b178-8bced3baae66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438344934 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1438344934
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3902876997
Short name T389
Test name
Test status
Simulation time 31168156 ps
CPU time 1.28 seconds
Started Apr 23 02:09:24 PM PDT 24
Finished Apr 23 02:09:26 PM PDT 24
Peak memory 219652 kb
Host smart-9d0c3bb5-1e7d-4f31-b661-1ccb82f17f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902876997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3902876997
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2582009534
Short name T829
Test name
Test status
Simulation time 122823131 ps
CPU time 0.87 seconds
Started Apr 23 02:09:26 PM PDT 24
Finished Apr 23 02:09:28 PM PDT 24
Peak memory 215672 kb
Host smart-e6f2365c-bef7-442d-b4d3-e72be2730b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582009534 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2582009534
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3494389583
Short name T781
Test name
Test status
Simulation time 47459766 ps
CPU time 0.96 seconds
Started Apr 23 02:09:19 PM PDT 24
Finished Apr 23 02:09:21 PM PDT 24
Peak memory 215560 kb
Host smart-3a74ae1c-6ceb-4c96-a8e0-776bbef7104e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494389583 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3494389583
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.155220293
Short name T365
Test name
Test status
Simulation time 833064968 ps
CPU time 3.77 seconds
Started Apr 23 02:09:23 PM PDT 24
Finished Apr 23 02:09:27 PM PDT 24
Peak memory 217164 kb
Host smart-ee5df5e1-9c34-4d28-adde-a523f0004d33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155220293 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.155220293
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1277290395
Short name T415
Test name
Test status
Simulation time 37797611823 ps
CPU time 934.45 seconds
Started Apr 23 02:09:23 PM PDT 24
Finished Apr 23 02:24:58 PM PDT 24
Peak memory 220268 kb
Host smart-2c5e174d-b33b-4c9e-b0f6-e0a7e46c7c39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277290395 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1277290395
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.2822152932
Short name T270
Test name
Test status
Simulation time 50215781 ps
CPU time 1.26 seconds
Started Apr 23 02:09:25 PM PDT 24
Finished Apr 23 02:09:26 PM PDT 24
Peak memory 215988 kb
Host smart-dd653cc3-0951-40fc-8e7a-ba8f8d1b3cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822152932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2822152932
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2890207189
Short name T317
Test name
Test status
Simulation time 74293355 ps
CPU time 0.86 seconds
Started Apr 23 02:09:26 PM PDT 24
Finished Apr 23 02:09:28 PM PDT 24
Peak memory 206880 kb
Host smart-ab71ab28-2613-413a-95b6-abd3a4ddac9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890207189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2890207189
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3841902082
Short name T160
Test name
Test status
Simulation time 41724453 ps
CPU time 0.87 seconds
Started Apr 23 02:09:25 PM PDT 24
Finished Apr 23 02:09:26 PM PDT 24
Peak memory 216380 kb
Host smart-e6a71fc4-579d-436e-b71d-6b690721ec14
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841902082 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3841902082
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.686323452
Short name T107
Test name
Test status
Simulation time 26283896 ps
CPU time 1.07 seconds
Started Apr 23 02:09:25 PM PDT 24
Finished Apr 23 02:09:26 PM PDT 24
Peak memory 216940 kb
Host smart-44080e88-7ee0-40a4-8c4e-74e23b84e514
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686323452 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.686323452
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1381509533
Short name T168
Test name
Test status
Simulation time 34751786 ps
CPU time 1.02 seconds
Started Apr 23 02:09:26 PM PDT 24
Finished Apr 23 02:09:27 PM PDT 24
Peak memory 224256 kb
Host smart-b9acefcb-c2ca-4fab-9761-637141342532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381509533 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1381509533
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2714986344
Short name T46
Test name
Test status
Simulation time 141656304 ps
CPU time 1.56 seconds
Started Apr 23 02:09:25 PM PDT 24
Finished Apr 23 02:09:27 PM PDT 24
Peak memory 218916 kb
Host smart-80431eec-e91e-4c39-a48e-9c1872955924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714986344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2714986344
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.786478123
Short name T633
Test name
Test status
Simulation time 21101366 ps
CPU time 1.13 seconds
Started Apr 23 02:09:24 PM PDT 24
Finished Apr 23 02:09:25 PM PDT 24
Peak memory 224468 kb
Host smart-9d07acce-cce7-4a42-ad87-9fa549d82b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786478123 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.786478123
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.549977135
Short name T327
Test name
Test status
Simulation time 18477164 ps
CPU time 0.99 seconds
Started Apr 23 02:09:24 PM PDT 24
Finished Apr 23 02:09:25 PM PDT 24
Peak memory 215504 kb
Host smart-39ac6496-ce5e-4362-80ad-ca7c7ecbc658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549977135 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.549977135
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.626649013
Short name T502
Test name
Test status
Simulation time 362958175 ps
CPU time 4.26 seconds
Started Apr 23 02:09:25 PM PDT 24
Finished Apr 23 02:09:30 PM PDT 24
Peak memory 215500 kb
Host smart-f934bf34-28e6-48b3-9b78-c8234f2630d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626649013 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.626649013
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3091877607
Short name T757
Test name
Test status
Simulation time 48924064408 ps
CPU time 1252.38 seconds
Started Apr 23 02:09:26 PM PDT 24
Finished Apr 23 02:30:19 PM PDT 24
Peak memory 222540 kb
Host smart-fb2981c0-52a6-469d-9e55-ed821da19ae8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091877607 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3091877607
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2247908419
Short name T129
Test name
Test status
Simulation time 26046132 ps
CPU time 1.21 seconds
Started Apr 23 02:09:27 PM PDT 24
Finished Apr 23 02:09:29 PM PDT 24
Peak memory 215928 kb
Host smart-935651bb-cfea-45f0-962e-18614b49af16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247908419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2247908419
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3271135907
Short name T211
Test name
Test status
Simulation time 54157164 ps
CPU time 0.92 seconds
Started Apr 23 02:09:28 PM PDT 24
Finished Apr 23 02:09:29 PM PDT 24
Peak memory 215104 kb
Host smart-658950bb-0cee-4ae1-bb47-cfda6154a656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271135907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3271135907
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2336169400
Short name T147
Test name
Test status
Simulation time 13520119 ps
CPU time 0.85 seconds
Started Apr 23 02:09:27 PM PDT 24
Finished Apr 23 02:09:28 PM PDT 24
Peak memory 216484 kb
Host smart-7e96dba7-50b7-455b-ac47-927e3352bc03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336169400 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2336169400
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.212864376
Short name T741
Test name
Test status
Simulation time 37531341 ps
CPU time 0.98 seconds
Started Apr 23 02:09:28 PM PDT 24
Finished Apr 23 02:09:30 PM PDT 24
Peak memory 217112 kb
Host smart-fa376381-d0ef-48b9-9ad2-1e555f849fab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212864376 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.212864376
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3761617423
Short name T120
Test name
Test status
Simulation time 31300759 ps
CPU time 0.95 seconds
Started Apr 23 02:09:27 PM PDT 24
Finished Apr 23 02:09:28 PM PDT 24
Peak memory 224260 kb
Host smart-9818f37c-204f-408e-9d9b-fba41a313c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761617423 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3761617423
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.229965229
Short name T514
Test name
Test status
Simulation time 39227774 ps
CPU time 1.12 seconds
Started Apr 23 02:09:24 PM PDT 24
Finished Apr 23 02:09:26 PM PDT 24
Peak memory 217280 kb
Host smart-c1824786-faac-4de1-9cdd-bca11089a47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229965229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.229965229
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2216016637
Short name T32
Test name
Test status
Simulation time 28339748 ps
CPU time 0.86 seconds
Started Apr 23 02:09:29 PM PDT 24
Finished Apr 23 02:09:30 PM PDT 24
Peak memory 216020 kb
Host smart-a1251e86-7c34-49db-8b36-3037f9f0e51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216016637 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2216016637
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.607912325
Short name T474
Test name
Test status
Simulation time 19183452 ps
CPU time 1.02 seconds
Started Apr 23 02:09:28 PM PDT 24
Finished Apr 23 02:09:29 PM PDT 24
Peak memory 215496 kb
Host smart-b7c1013e-0471-4f9d-a8d6-55dd58a39fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607912325 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.607912325
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.4089197687
Short name T559
Test name
Test status
Simulation time 351290969 ps
CPU time 3.62 seconds
Started Apr 23 02:09:27 PM PDT 24
Finished Apr 23 02:09:31 PM PDT 24
Peak memory 215584 kb
Host smart-cc81a601-4fcf-4188-846b-b6b919c9fb05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089197687 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.4089197687
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3582176827
Short name T204
Test name
Test status
Simulation time 71353079187 ps
CPU time 1610.32 seconds
Started Apr 23 02:09:28 PM PDT 24
Finished Apr 23 02:36:19 PM PDT 24
Peak memory 222684 kb
Host smart-78456e6a-c487-4f90-bff9-811989cb8524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582176827 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3582176827
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1083678394
Short name T815
Test name
Test status
Simulation time 87076548 ps
CPU time 1.16 seconds
Started Apr 23 02:08:06 PM PDT 24
Finished Apr 23 02:08:08 PM PDT 24
Peak memory 215844 kb
Host smart-6dbea0fe-c379-4161-8763-47fe99dda824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083678394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1083678394
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3977810456
Short name T659
Test name
Test status
Simulation time 30773230 ps
CPU time 0.76 seconds
Started Apr 23 02:08:15 PM PDT 24
Finished Apr 23 02:08:16 PM PDT 24
Peak memory 206556 kb
Host smart-3383889c-ce9e-4f8e-9f77-4a78d4f8d8e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977810456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3977810456
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1460985725
Short name T146
Test name
Test status
Simulation time 22896357 ps
CPU time 0.82 seconds
Started Apr 23 02:08:05 PM PDT 24
Finished Apr 23 02:08:07 PM PDT 24
Peak memory 216588 kb
Host smart-1001355e-1071-4f1b-8330-c5d904dd59dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460985725 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1460985725
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.670344466
Short name T835
Test name
Test status
Simulation time 112065028 ps
CPU time 1.17 seconds
Started Apr 23 02:08:05 PM PDT 24
Finished Apr 23 02:08:06 PM PDT 24
Peak memory 217052 kb
Host smart-069e7405-b822-4294-84b7-df993e6562a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670344466 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.670344466
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1237753859
Short name T672
Test name
Test status
Simulation time 76380156 ps
CPU time 1.13 seconds
Started Apr 23 02:08:02 PM PDT 24
Finished Apr 23 02:08:03 PM PDT 24
Peak memory 219860 kb
Host smart-226f6ffa-546e-41ae-996d-def87b76815a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237753859 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1237753859
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.617751885
Short name T537
Test name
Test status
Simulation time 56893296 ps
CPU time 1.58 seconds
Started Apr 23 02:08:04 PM PDT 24
Finished Apr 23 02:08:06 PM PDT 24
Peak memory 218820 kb
Host smart-0f2985dd-4f76-4758-adb1-5ede0c6c1214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617751885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.617751885
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3128113366
Short name T31
Test name
Test status
Simulation time 34921319 ps
CPU time 0.87 seconds
Started Apr 23 02:08:01 PM PDT 24
Finished Apr 23 02:08:02 PM PDT 24
Peak memory 215892 kb
Host smart-0c4c6eb9-0468-4ffb-a709-10d1331f08d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128113366 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3128113366
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1034801503
Short name T24
Test name
Test status
Simulation time 18023438 ps
CPU time 1.07 seconds
Started Apr 23 02:08:01 PM PDT 24
Finished Apr 23 02:08:03 PM PDT 24
Peak memory 207464 kb
Host smart-b3f8dcea-b0b1-4382-a958-e24bff4a70ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034801503 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1034801503
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.412422850
Short name T61
Test name
Test status
Simulation time 1675106337 ps
CPU time 7.37 seconds
Started Apr 23 02:08:15 PM PDT 24
Finished Apr 23 02:08:23 PM PDT 24
Peak memory 240260 kb
Host smart-9cca813a-d288-4fca-8c92-f0ed42015d4a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412422850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.412422850
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3367654807
Short name T639
Test name
Test status
Simulation time 48426449 ps
CPU time 0.91 seconds
Started Apr 23 02:08:02 PM PDT 24
Finished Apr 23 02:08:03 PM PDT 24
Peak memory 214908 kb
Host smart-9e1e4c4e-d318-4bde-9dc7-ae3cc5998f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367654807 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3367654807
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2840880767
Short name T395
Test name
Test status
Simulation time 219198358 ps
CPU time 4.57 seconds
Started Apr 23 02:08:00 PM PDT 24
Finished Apr 23 02:08:06 PM PDT 24
Peak memory 217192 kb
Host smart-841165cf-2697-4ac7-b79a-1f1a6dbaff8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840880767 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2840880767
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1146131600
Short name T203
Test name
Test status
Simulation time 40820001150 ps
CPU time 455.66 seconds
Started Apr 23 02:08:06 PM PDT 24
Finished Apr 23 02:15:43 PM PDT 24
Peak memory 218716 kb
Host smart-4f0bb9a5-e28a-41eb-a9fa-e5e3be2c7572
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146131600 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1146131600
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.3446932876
Short name T730
Test name
Test status
Simulation time 80191024 ps
CPU time 1.07 seconds
Started Apr 23 02:09:31 PM PDT 24
Finished Apr 23 02:09:33 PM PDT 24
Peak memory 215968 kb
Host smart-43253ca1-a44a-4d71-bb67-bb2e7683bce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446932876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3446932876
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.262658089
Short name T473
Test name
Test status
Simulation time 75939402 ps
CPU time 0.96 seconds
Started Apr 23 02:09:32 PM PDT 24
Finished Apr 23 02:09:33 PM PDT 24
Peak memory 206908 kb
Host smart-3ff850a6-888c-457d-bc01-a5e8c3127e4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262658089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.262658089
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.589215311
Short name T174
Test name
Test status
Simulation time 24736375 ps
CPU time 0.83 seconds
Started Apr 23 02:09:30 PM PDT 24
Finished Apr 23 02:09:31 PM PDT 24
Peak memory 216564 kb
Host smart-2c4bbcd1-5c4e-4903-a7eb-e7b096d0d71f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589215311 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.589215311
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.581215040
Short name T404
Test name
Test status
Simulation time 20072024 ps
CPU time 0.99 seconds
Started Apr 23 02:09:32 PM PDT 24
Finished Apr 23 02:09:33 PM PDT 24
Peak memory 219484 kb
Host smart-4671d666-aeb7-4b41-b9d7-0fa324daf84a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581215040 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.581215040
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1552657987
Short name T454
Test name
Test status
Simulation time 19408833 ps
CPU time 1.04 seconds
Started Apr 23 02:09:37 PM PDT 24
Finished Apr 23 02:09:39 PM PDT 24
Peak memory 218676 kb
Host smart-469f890e-36ae-40fb-b2b7-5d9c12736a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552657987 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1552657987
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3813987100
Short name T800
Test name
Test status
Simulation time 233139435 ps
CPU time 2.41 seconds
Started Apr 23 02:09:29 PM PDT 24
Finished Apr 23 02:09:32 PM PDT 24
Peak memory 218560 kb
Host smart-35d0305b-d865-4a01-a4d1-b57aca100c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813987100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3813987100
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1869208742
Short name T86
Test name
Test status
Simulation time 36664412 ps
CPU time 0.88 seconds
Started Apr 23 02:09:32 PM PDT 24
Finished Apr 23 02:09:33 PM PDT 24
Peak memory 215876 kb
Host smart-ed7b35b5-4c55-4d1d-91e2-5b3d1c2f9ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869208742 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1869208742
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.291353687
Short name T592
Test name
Test status
Simulation time 20422500 ps
CPU time 0.86 seconds
Started Apr 23 02:09:27 PM PDT 24
Finished Apr 23 02:09:28 PM PDT 24
Peak memory 215500 kb
Host smart-473c2675-0b2e-4521-9e17-e84efef05888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291353687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.291353687
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1534944271
Short name T742
Test name
Test status
Simulation time 352020884 ps
CPU time 1.42 seconds
Started Apr 23 02:09:33 PM PDT 24
Finished Apr 23 02:09:35 PM PDT 24
Peak memory 215544 kb
Host smart-30f5465b-5fee-4719-854f-33f1ceeafd34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534944271 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1534944271
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1941414483
Short name T202
Test name
Test status
Simulation time 302859450084 ps
CPU time 352.18 seconds
Started Apr 23 02:09:32 PM PDT 24
Finished Apr 23 02:15:24 PM PDT 24
Peak memory 220752 kb
Host smart-62502b15-8ef0-4d2e-82d9-ce7b877ed16d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941414483 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1941414483
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.4104883836
Short name T524
Test name
Test status
Simulation time 106986609 ps
CPU time 1.25 seconds
Started Apr 23 02:09:30 PM PDT 24
Finished Apr 23 02:09:32 PM PDT 24
Peak memory 215924 kb
Host smart-2927b99d-ef8d-4e2c-a026-8c14fe6603f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104883836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.4104883836
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1135505001
Short name T65
Test name
Test status
Simulation time 32567892 ps
CPU time 0.9 seconds
Started Apr 23 02:09:34 PM PDT 24
Finished Apr 23 02:09:35 PM PDT 24
Peak memory 206884 kb
Host smart-bf8db653-d447-41ac-b7ca-f102838c2ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135505001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1135505001
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.4039738966
Short name T724
Test name
Test status
Simulation time 73569990 ps
CPU time 0.85 seconds
Started Apr 23 02:09:33 PM PDT 24
Finished Apr 23 02:09:34 PM PDT 24
Peak memory 216080 kb
Host smart-1e9c8934-54a0-4c67-849a-4b571635d5d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039738966 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.4039738966
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.347021414
Short name T831
Test name
Test status
Simulation time 150458459 ps
CPU time 1.02 seconds
Started Apr 23 02:09:34 PM PDT 24
Finished Apr 23 02:09:36 PM PDT 24
Peak memory 217116 kb
Host smart-34ecc13a-405b-4aea-ac42-80ac80b08e2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347021414 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.347021414
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2662346245
Short name T181
Test name
Test status
Simulation time 75865369 ps
CPU time 1.25 seconds
Started Apr 23 02:09:37 PM PDT 24
Finished Apr 23 02:09:39 PM PDT 24
Peak memory 226044 kb
Host smart-f6143d89-31c0-48ea-9301-1c0e4700fd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662346245 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2662346245
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3323352528
Short name T417
Test name
Test status
Simulation time 40006017 ps
CPU time 1.19 seconds
Started Apr 23 02:09:31 PM PDT 24
Finished Apr 23 02:09:32 PM PDT 24
Peak memory 217212 kb
Host smart-b240f500-e424-4145-9ba1-6af28325080b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323352528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3323352528
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.83895105
Short name T547
Test name
Test status
Simulation time 26789965 ps
CPU time 0.92 seconds
Started Apr 23 02:09:32 PM PDT 24
Finished Apr 23 02:09:33 PM PDT 24
Peak memory 216160 kb
Host smart-726303e0-497e-4e3d-9500-98e66d3defa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83895105 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.83895105
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.304183796
Short name T419
Test name
Test status
Simulation time 22000791 ps
CPU time 0.96 seconds
Started Apr 23 02:09:31 PM PDT 24
Finished Apr 23 02:09:32 PM PDT 24
Peak memory 215488 kb
Host smart-480b82d1-7240-47c7-b90e-2a3c79f3ca21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304183796 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.304183796
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.122513127
Short name T378
Test name
Test status
Simulation time 106175175 ps
CPU time 1.16 seconds
Started Apr 23 02:09:31 PM PDT 24
Finished Apr 23 02:09:33 PM PDT 24
Peak memory 217236 kb
Host smart-7348560b-f590-4eab-be4b-7d309e1cdc1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122513127 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.122513127
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2912434152
Short name T808
Test name
Test status
Simulation time 138827579006 ps
CPU time 1161.5 seconds
Started Apr 23 02:09:30 PM PDT 24
Finished Apr 23 02:28:52 PM PDT 24
Peak memory 222824 kb
Host smart-f1e187ed-9329-4b07-8a8c-85441d2d3f87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912434152 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2912434152
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.4264771106
Short name T269
Test name
Test status
Simulation time 83559848 ps
CPU time 1.22 seconds
Started Apr 23 02:09:35 PM PDT 24
Finished Apr 23 02:09:36 PM PDT 24
Peak memory 215952 kb
Host smart-9cb13afb-8ef9-4af4-ac94-e68df2739cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264771106 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.4264771106
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1074659045
Short name T801
Test name
Test status
Simulation time 12769317 ps
CPU time 0.84 seconds
Started Apr 23 02:09:35 PM PDT 24
Finished Apr 23 02:09:36 PM PDT 24
Peak memory 206860 kb
Host smart-9aa5b981-9213-4722-82c4-9db1e482377e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074659045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1074659045
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.971700922
Short name T169
Test name
Test status
Simulation time 11393542 ps
CPU time 0.85 seconds
Started Apr 23 02:09:33 PM PDT 24
Finished Apr 23 02:09:34 PM PDT 24
Peak memory 216524 kb
Host smart-6ea2bf96-220f-4b16-aca5-96585b0c7d87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971700922 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.971700922
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_err.457207799
Short name T6
Test name
Test status
Simulation time 18998979 ps
CPU time 1.06 seconds
Started Apr 23 02:09:36 PM PDT 24
Finished Apr 23 02:09:38 PM PDT 24
Peak memory 215740 kb
Host smart-b9df4fed-d45e-4345-b81e-cdefaa547b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457207799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.457207799
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2063168110
Short name T569
Test name
Test status
Simulation time 40927620 ps
CPU time 1.44 seconds
Started Apr 23 02:09:32 PM PDT 24
Finished Apr 23 02:09:34 PM PDT 24
Peak memory 219900 kb
Host smart-ca601d08-e3c8-4c00-8e0a-07db0c092130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063168110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2063168110
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.87723744
Short name T557
Test name
Test status
Simulation time 22476629 ps
CPU time 1.24 seconds
Started Apr 23 02:09:37 PM PDT 24
Finished Apr 23 02:09:39 PM PDT 24
Peak memory 224380 kb
Host smart-e5b41dfb-0cad-4dcf-8bab-856684e9a40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87723744 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.87723744
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.799413047
Short name T20
Test name
Test status
Simulation time 15182461 ps
CPU time 0.93 seconds
Started Apr 23 02:09:33 PM PDT 24
Finished Apr 23 02:09:35 PM PDT 24
Peak memory 215564 kb
Host smart-2a69db52-4334-4868-b7d5-ecdee72dffe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799413047 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.799413047
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.4176947491
Short name T303
Test name
Test status
Simulation time 444954441 ps
CPU time 3.88 seconds
Started Apr 23 02:09:34 PM PDT 24
Finished Apr 23 02:09:39 PM PDT 24
Peak memory 217236 kb
Host smart-6760ffdd-bf51-4828-8360-caa08862ca12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176947491 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.4176947491
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3953817297
Short name T426
Test name
Test status
Simulation time 71635867491 ps
CPU time 952.53 seconds
Started Apr 23 02:09:33 PM PDT 24
Finished Apr 23 02:25:26 PM PDT 24
Peak memory 220104 kb
Host smart-b2d7fb35-5f08-4112-8604-4b0e9deed7d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953817297 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3953817297
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2591508097
Short name T611
Test name
Test status
Simulation time 155625286 ps
CPU time 1.3 seconds
Started Apr 23 02:09:36 PM PDT 24
Finished Apr 23 02:09:38 PM PDT 24
Peak memory 215940 kb
Host smart-6b01ba85-7cb4-4198-8af0-1f236cb03f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591508097 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2591508097
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.82451262
Short name T340
Test name
Test status
Simulation time 23278062 ps
CPU time 1.05 seconds
Started Apr 23 02:09:37 PM PDT 24
Finished Apr 23 02:09:39 PM PDT 24
Peak memory 215184 kb
Host smart-6139c2a8-d668-41e4-b3b3-75bda5b2f389
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82451262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.82451262
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2120495337
Short name T346
Test name
Test status
Simulation time 184353325 ps
CPU time 0.9 seconds
Started Apr 23 02:09:37 PM PDT 24
Finished Apr 23 02:09:38 PM PDT 24
Peak memory 216160 kb
Host smart-8c851266-8b26-457c-b8c8-6e9802a5092e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120495337 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2120495337
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1916946265
Short name T400
Test name
Test status
Simulation time 32947654 ps
CPU time 1.16 seconds
Started Apr 23 02:09:37 PM PDT 24
Finished Apr 23 02:09:38 PM PDT 24
Peak memory 217296 kb
Host smart-64c68241-0776-4ca5-974c-4c38007de34c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916946265 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1916946265
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3005100250
Short name T53
Test name
Test status
Simulation time 46922115 ps
CPU time 1.52 seconds
Started Apr 23 02:09:36 PM PDT 24
Finished Apr 23 02:09:38 PM PDT 24
Peak memory 229952 kb
Host smart-88c29708-8966-4531-a900-6c811e25f33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005100250 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3005100250
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.890920741
Short name T482
Test name
Test status
Simulation time 88930093 ps
CPU time 1.8 seconds
Started Apr 23 02:09:35 PM PDT 24
Finished Apr 23 02:09:37 PM PDT 24
Peak memory 218552 kb
Host smart-eb3c3cbf-5a0e-4902-9df6-89e300b2c5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890920741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.890920741
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2497959109
Short name T480
Test name
Test status
Simulation time 47215657 ps
CPU time 0.98 seconds
Started Apr 23 02:09:37 PM PDT 24
Finished Apr 23 02:09:39 PM PDT 24
Peak memory 224152 kb
Host smart-96df15e7-b5d1-46f4-989d-9e37a6f5a319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497959109 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2497959109
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2544617461
Short name T487
Test name
Test status
Simulation time 16979714 ps
CPU time 1.01 seconds
Started Apr 23 02:09:33 PM PDT 24
Finished Apr 23 02:09:35 PM PDT 24
Peak memory 215536 kb
Host smart-1ca7dccf-2ade-4f99-a3f4-15d3977666cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544617461 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2544617461
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1117647365
Short name T377
Test name
Test status
Simulation time 436669426 ps
CPU time 4.57 seconds
Started Apr 23 02:09:35 PM PDT 24
Finished Apr 23 02:09:40 PM PDT 24
Peak memory 217168 kb
Host smart-d8c873a8-2922-421a-b56f-7c7855e6f0cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117647365 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1117647365
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.480790119
Short name T774
Test name
Test status
Simulation time 49484498475 ps
CPU time 635.12 seconds
Started Apr 23 02:09:39 PM PDT 24
Finished Apr 23 02:20:14 PM PDT 24
Peak memory 218152 kb
Host smart-7c627594-428e-429e-be9c-af17d03737e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480790119 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.480790119
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.875820178
Short name T550
Test name
Test status
Simulation time 42550129 ps
CPU time 1.22 seconds
Started Apr 23 02:09:40 PM PDT 24
Finished Apr 23 02:09:42 PM PDT 24
Peak memory 215900 kb
Host smart-c82b6267-0562-44f5-bea8-1ce16ce6aa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875820178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.875820178
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2195686735
Short name T438
Test name
Test status
Simulation time 28067714 ps
CPU time 0.92 seconds
Started Apr 23 02:09:40 PM PDT 24
Finished Apr 23 02:09:42 PM PDT 24
Peak memory 206796 kb
Host smart-61374bad-8fd8-43cc-bfaa-f708347e931f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195686735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2195686735
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.4007201224
Short name T184
Test name
Test status
Simulation time 18529118 ps
CPU time 0.86 seconds
Started Apr 23 02:09:40 PM PDT 24
Finished Apr 23 02:09:42 PM PDT 24
Peak memory 215520 kb
Host smart-7fa45043-d525-446d-9878-9bed202e4686
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007201224 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.4007201224
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.367690543
Short name T94
Test name
Test status
Simulation time 41158963 ps
CPU time 1.14 seconds
Started Apr 23 02:09:40 PM PDT 24
Finished Apr 23 02:09:41 PM PDT 24
Peak memory 218360 kb
Host smart-a13d3278-b065-4eca-9c48-40a52c163d4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367690543 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.367690543
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2045823542
Short name T179
Test name
Test status
Simulation time 42018260 ps
CPU time 1.26 seconds
Started Apr 23 02:09:42 PM PDT 24
Finished Apr 23 02:09:44 PM PDT 24
Peak memory 219952 kb
Host smart-50f4b7ba-dd5f-4757-b44a-30f1d57992b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045823542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2045823542
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2124359496
Short name T291
Test name
Test status
Simulation time 66696904 ps
CPU time 1.36 seconds
Started Apr 23 02:09:40 PM PDT 24
Finished Apr 23 02:09:42 PM PDT 24
Peak memory 218564 kb
Host smart-a95ca020-55b3-4f73-99ed-5d97d9e7495c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124359496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2124359496
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3626077666
Short name T780
Test name
Test status
Simulation time 28524625 ps
CPU time 0.92 seconds
Started Apr 23 02:09:37 PM PDT 24
Finished Apr 23 02:09:39 PM PDT 24
Peak memory 215728 kb
Host smart-5b5d4618-1f9d-425a-bc77-25706d0fc3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626077666 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3626077666
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3501061232
Short name T491
Test name
Test status
Simulation time 17355191 ps
CPU time 0.97 seconds
Started Apr 23 02:09:39 PM PDT 24
Finished Apr 23 02:09:41 PM PDT 24
Peak memory 215508 kb
Host smart-90ac27a0-d3b0-4ac2-a969-4790cef100ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501061232 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3501061232
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.928200829
Short name T816
Test name
Test status
Simulation time 453742370 ps
CPU time 5.01 seconds
Started Apr 23 02:09:39 PM PDT 24
Finished Apr 23 02:09:45 PM PDT 24
Peak memory 217080 kb
Host smart-904027e8-3330-472e-81d1-ee5b2b818331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928200829 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.928200829
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3223812721
Short name T414
Test name
Test status
Simulation time 301647934716 ps
CPU time 3818.08 seconds
Started Apr 23 02:09:37 PM PDT 24
Finished Apr 23 03:13:16 PM PDT 24
Peak memory 240324 kb
Host smart-b73775e1-a359-4ece-bd82-957bc3adcf26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223812721 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3223812721
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.168442225
Short name T150
Test name
Test status
Simulation time 62758769 ps
CPU time 1.16 seconds
Started Apr 23 02:09:41 PM PDT 24
Finished Apr 23 02:09:42 PM PDT 24
Peak memory 216008 kb
Host smart-4a904249-882e-423f-9dbc-5cc6aedf101e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168442225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.168442225
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2333819814
Short name T606
Test name
Test status
Simulation time 40404373 ps
CPU time 0.86 seconds
Started Apr 23 02:09:43 PM PDT 24
Finished Apr 23 02:09:45 PM PDT 24
Peak memory 206952 kb
Host smart-f738f6fd-adf0-4312-b73e-9d5b90eeec3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333819814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2333819814
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.729383533
Short name T121
Test name
Test status
Simulation time 12902905 ps
CPU time 0.88 seconds
Started Apr 23 02:09:39 PM PDT 24
Finished Apr 23 02:09:41 PM PDT 24
Peak memory 215868 kb
Host smart-d5557d86-eedc-4645-b0f3-510d14f64353
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729383533 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.729383533
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2480889387
Short name T818
Test name
Test status
Simulation time 37214418 ps
CPU time 1.24 seconds
Started Apr 23 02:09:40 PM PDT 24
Finished Apr 23 02:09:42 PM PDT 24
Peak memory 218552 kb
Host smart-ee8fd419-007e-4056-805f-5fb3f7b05ca7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480889387 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2480889387
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1065051738
Short name T692
Test name
Test status
Simulation time 18166684 ps
CPU time 1.12 seconds
Started Apr 23 02:09:40 PM PDT 24
Finished Apr 23 02:09:41 PM PDT 24
Peak memory 224436 kb
Host smart-26a26afb-71bc-480b-a983-67ff33220de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065051738 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1065051738
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1250463406
Short name T295
Test name
Test status
Simulation time 54110603 ps
CPU time 1.32 seconds
Started Apr 23 02:09:40 PM PDT 24
Finished Apr 23 02:09:42 PM PDT 24
Peak memory 218660 kb
Host smart-f21be1a9-4fad-4141-8da0-cdbe6e69b186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250463406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1250463406
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2285391481
Short name T33
Test name
Test status
Simulation time 22273077 ps
CPU time 1.09 seconds
Started Apr 23 02:09:39 PM PDT 24
Finished Apr 23 02:09:41 PM PDT 24
Peak memory 216176 kb
Host smart-21fd5241-183f-493b-a594-e8c5bc93c431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285391481 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2285391481
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3153467473
Short name T464
Test name
Test status
Simulation time 21054093 ps
CPU time 0.96 seconds
Started Apr 23 02:09:40 PM PDT 24
Finished Apr 23 02:09:42 PM PDT 24
Peak memory 215576 kb
Host smart-b2ed11f5-ae3b-4863-8d6c-23043ecd32e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153467473 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3153467473
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.750258444
Short name T373
Test name
Test status
Simulation time 37490652 ps
CPU time 0.98 seconds
Started Apr 23 02:09:41 PM PDT 24
Finished Apr 23 02:09:43 PM PDT 24
Peak memory 206596 kb
Host smart-c1c9fd1e-5c41-4209-8308-6d99adfa3c2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750258444 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.750258444
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.847743026
Short name T431
Test name
Test status
Simulation time 35556235361 ps
CPU time 449.66 seconds
Started Apr 23 02:09:39 PM PDT 24
Finished Apr 23 02:17:09 PM PDT 24
Peak memory 216880 kb
Host smart-c5618326-4306-4ce2-9b6e-96e7bcba5898
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847743026 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.847743026
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2712626639
Short name T712
Test name
Test status
Simulation time 245299748 ps
CPU time 1.47 seconds
Started Apr 23 02:09:41 PM PDT 24
Finished Apr 23 02:09:43 PM PDT 24
Peak memory 215848 kb
Host smart-f57cb34a-02a0-4a1b-b044-f63c379cad69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712626639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2712626639
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1286129252
Short name T752
Test name
Test status
Simulation time 42199044 ps
CPU time 0.9 seconds
Started Apr 23 02:09:43 PM PDT 24
Finished Apr 23 02:09:44 PM PDT 24
Peak memory 206676 kb
Host smart-3db23bf2-c29b-4280-9364-08747cd27dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286129252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1286129252
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3684025474
Short name T579
Test name
Test status
Simulation time 13658024 ps
CPU time 0.95 seconds
Started Apr 23 02:09:45 PM PDT 24
Finished Apr 23 02:09:46 PM PDT 24
Peak memory 215864 kb
Host smart-f33c2786-1476-4bb7-ac2c-5aed746f551f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684025474 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3684025474
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1526770294
Short name T631
Test name
Test status
Simulation time 52446775 ps
CPU time 1.09 seconds
Started Apr 23 02:09:43 PM PDT 24
Finished Apr 23 02:09:45 PM PDT 24
Peak memory 218528 kb
Host smart-71d210fd-e9e8-47fa-a3d7-3bc0f09249f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526770294 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1526770294
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_genbits.4219306807
Short name T586
Test name
Test status
Simulation time 123520428 ps
CPU time 1.44 seconds
Started Apr 23 02:09:44 PM PDT 24
Finished Apr 23 02:09:45 PM PDT 24
Peak memory 217272 kb
Host smart-6517cd58-f589-418b-bcd3-e62a174b90c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219306807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.4219306807
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3838523924
Short name T760
Test name
Test status
Simulation time 21236370 ps
CPU time 1.15 seconds
Started Apr 23 02:09:41 PM PDT 24
Finished Apr 23 02:09:43 PM PDT 24
Peak memory 224416 kb
Host smart-28011b97-5184-4617-a937-00788301dfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838523924 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3838523924
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2722434454
Short name T778
Test name
Test status
Simulation time 14975338 ps
CPU time 0.96 seconds
Started Apr 23 02:09:41 PM PDT 24
Finished Apr 23 02:09:43 PM PDT 24
Peak memory 215604 kb
Host smart-fb3c2dbc-3ccb-41c2-8687-d0774464f8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722434454 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2722434454
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.958588506
Short name T670
Test name
Test status
Simulation time 888966249 ps
CPU time 6.77 seconds
Started Apr 23 02:09:42 PM PDT 24
Finished Apr 23 02:09:49 PM PDT 24
Peak memory 220556 kb
Host smart-4717734a-d982-41e9-b5c4-94a532a32fc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958588506 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.958588506
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2694322904
Short name T794
Test name
Test status
Simulation time 136532436830 ps
CPU time 1692.98 seconds
Started Apr 23 02:09:43 PM PDT 24
Finished Apr 23 02:37:56 PM PDT 24
Peak memory 227452 kb
Host smart-bf369732-186f-4c1e-836c-3175d69fec0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694322904 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2694322904
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1569194325
Short name T77
Test name
Test status
Simulation time 42670859 ps
CPU time 1.17 seconds
Started Apr 23 02:09:50 PM PDT 24
Finished Apr 23 02:09:52 PM PDT 24
Peak memory 215984 kb
Host smart-da0ace4a-ce38-4b70-a55a-eb0cff256429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569194325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1569194325
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1278389078
Short name T413
Test name
Test status
Simulation time 25793623 ps
CPU time 0.96 seconds
Started Apr 23 02:09:51 PM PDT 24
Finished Apr 23 02:09:53 PM PDT 24
Peak memory 206916 kb
Host smart-2f460351-b007-43b6-845f-8e73138c7b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278389078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1278389078
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1658551762
Short name T27
Test name
Test status
Simulation time 12933083 ps
CPU time 0.99 seconds
Started Apr 23 02:09:50 PM PDT 24
Finished Apr 23 02:09:52 PM PDT 24
Peak memory 216564 kb
Host smart-ae66fc38-9705-4c1d-a774-72ff899f8109
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658551762 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1658551762
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3845269383
Short name T163
Test name
Test status
Simulation time 99304851 ps
CPU time 1.15 seconds
Started Apr 23 02:09:51 PM PDT 24
Finished Apr 23 02:09:52 PM PDT 24
Peak memory 217096 kb
Host smart-e638726b-fd89-440e-be52-0749630fae62
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845269383 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3845269383
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2343709318
Short name T165
Test name
Test status
Simulation time 61554607 ps
CPU time 0.96 seconds
Started Apr 23 02:09:49 PM PDT 24
Finished Apr 23 02:09:50 PM PDT 24
Peak memory 220912 kb
Host smart-ac12234c-225e-48e0-82af-24f81751c956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343709318 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2343709318
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.518414845
Short name T368
Test name
Test status
Simulation time 27902854 ps
CPU time 1.2 seconds
Started Apr 23 02:09:42 PM PDT 24
Finished Apr 23 02:09:43 PM PDT 24
Peak memory 217296 kb
Host smart-cad67185-fe0e-4c58-826e-3e9419713b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518414845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.518414845
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.490528245
Short name T646
Test name
Test status
Simulation time 23953507 ps
CPU time 1.04 seconds
Started Apr 23 02:09:49 PM PDT 24
Finished Apr 23 02:09:51 PM PDT 24
Peak memory 216080 kb
Host smart-7a13cdd0-5d62-47b3-9ded-621c0e397099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490528245 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.490528245
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3100877921
Short name T469
Test name
Test status
Simulation time 36624877 ps
CPU time 0.85 seconds
Started Apr 23 02:09:42 PM PDT 24
Finished Apr 23 02:09:43 PM PDT 24
Peak memory 215328 kb
Host smart-204abe7d-3226-49dc-b23e-759a48e8e930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100877921 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3100877921
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2356071546
Short name T523
Test name
Test status
Simulation time 133310453 ps
CPU time 3 seconds
Started Apr 23 02:09:41 PM PDT 24
Finished Apr 23 02:09:45 PM PDT 24
Peak memory 217352 kb
Host smart-52b16e1f-2b0f-4423-94d8-723811384c5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356071546 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2356071546
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_alert.3860829828
Short name T746
Test name
Test status
Simulation time 25779879 ps
CPU time 1.26 seconds
Started Apr 23 02:09:51 PM PDT 24
Finished Apr 23 02:09:52 PM PDT 24
Peak memory 215840 kb
Host smart-d795490f-d9a3-47ba-82fc-a3ffe5103c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860829828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3860829828
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1558778798
Short name T347
Test name
Test status
Simulation time 21796049 ps
CPU time 0.85 seconds
Started Apr 23 02:09:50 PM PDT 24
Finished Apr 23 02:09:51 PM PDT 24
Peak memory 215104 kb
Host smart-0d3f2d49-6c30-4321-951f-eea3305977ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558778798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1558778798
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1934422201
Short name T187
Test name
Test status
Simulation time 11584533 ps
CPU time 0.89 seconds
Started Apr 23 02:09:49 PM PDT 24
Finished Apr 23 02:09:50 PM PDT 24
Peak memory 216372 kb
Host smart-ad6ba6db-2f48-47db-b2ef-159476a73a01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934422201 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1934422201
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.4062279348
Short name T48
Test name
Test status
Simulation time 52829691 ps
CPU time 0.97 seconds
Started Apr 23 02:09:49 PM PDT 24
Finished Apr 23 02:09:51 PM PDT 24
Peak memory 215940 kb
Host smart-6e959eeb-4343-45d9-89ff-1432c0cf3caa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062279348 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.4062279348
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2322889043
Short name T600
Test name
Test status
Simulation time 26853847 ps
CPU time 0.85 seconds
Started Apr 23 02:09:52 PM PDT 24
Finished Apr 23 02:09:54 PM PDT 24
Peak memory 215660 kb
Host smart-6f4e632c-8d78-4b2d-aa77-4eaf160ded33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322889043 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2322889043
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1919069934
Short name T356
Test name
Test status
Simulation time 44135727 ps
CPU time 1.11 seconds
Started Apr 23 02:09:48 PM PDT 24
Finished Apr 23 02:09:50 PM PDT 24
Peak memory 217256 kb
Host smart-85638742-b2c0-4ba6-b489-5fc540e0406c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919069934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1919069934
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.351077039
Short name T682
Test name
Test status
Simulation time 33626210 ps
CPU time 0.86 seconds
Started Apr 23 02:09:50 PM PDT 24
Finished Apr 23 02:09:51 PM PDT 24
Peak memory 215832 kb
Host smart-e5d8d551-a484-40f0-9817-4023e653455d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351077039 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.351077039
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3371532332
Short name T479
Test name
Test status
Simulation time 31660672 ps
CPU time 0.96 seconds
Started Apr 23 02:09:50 PM PDT 24
Finished Apr 23 02:09:52 PM PDT 24
Peak memory 215512 kb
Host smart-d89ccfe8-7140-4ebf-953b-a905bdf093e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371532332 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3371532332
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1925458169
Short name T221
Test name
Test status
Simulation time 333717438 ps
CPU time 6.7 seconds
Started Apr 23 02:09:49 PM PDT 24
Finished Apr 23 02:09:56 PM PDT 24
Peak memory 218524 kb
Host smart-d57e1c5b-b46e-4bc9-a3f9-b051055cb689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925458169 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1925458169
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1560325841
Short name T201
Test name
Test status
Simulation time 63801477309 ps
CPU time 1497.44 seconds
Started Apr 23 02:09:50 PM PDT 24
Finished Apr 23 02:34:48 PM PDT 24
Peak memory 222456 kb
Host smart-4bbe9a93-1589-4b4c-9706-f328438905c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560325841 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1560325841
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.47752539
Short name T156
Test name
Test status
Simulation time 103299948 ps
CPU time 1.43 seconds
Started Apr 23 02:10:02 PM PDT 24
Finished Apr 23 02:10:04 PM PDT 24
Peak memory 215912 kb
Host smart-edc3cb4e-6297-4770-afe2-b8f2dde3e01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47752539 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.47752539
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.600899602
Short name T500
Test name
Test status
Simulation time 33425152 ps
CPU time 0.81 seconds
Started Apr 23 02:10:07 PM PDT 24
Finished Apr 23 02:10:09 PM PDT 24
Peak memory 206264 kb
Host smart-fad1e24d-cdb6-494c-8bfc-2f795b6bd4c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600899602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.600899602
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.48015836
Short name T78
Test name
Test status
Simulation time 87753297 ps
CPU time 0.83 seconds
Started Apr 23 02:10:08 PM PDT 24
Finished Apr 23 02:10:10 PM PDT 24
Peak memory 216552 kb
Host smart-3df9c90b-4569-41fe-8b7d-490697d3b492
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48015836 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.48015836
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.786068818
Short name T751
Test name
Test status
Simulation time 55973311 ps
CPU time 1.16 seconds
Started Apr 23 02:10:05 PM PDT 24
Finished Apr 23 02:10:07 PM PDT 24
Peak memory 218184 kb
Host smart-756592bc-e4a1-4ebc-ba77-d4430adf6d59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786068818 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.786068818
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.162536288
Short name T8
Test name
Test status
Simulation time 30598462 ps
CPU time 1.01 seconds
Started Apr 23 02:10:01 PM PDT 24
Finished Apr 23 02:10:03 PM PDT 24
Peak memory 224516 kb
Host smart-1780dec7-caf8-4a1d-b9c5-9612ba447261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162536288 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.162536288
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.457310429
Short name T504
Test name
Test status
Simulation time 48648472 ps
CPU time 1.89 seconds
Started Apr 23 02:09:51 PM PDT 24
Finished Apr 23 02:09:54 PM PDT 24
Peak memory 219828 kb
Host smart-bdd06b8a-f58c-4174-ad8e-a3c428cdc2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457310429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.457310429
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2962259021
Short name T89
Test name
Test status
Simulation time 27817620 ps
CPU time 0.93 seconds
Started Apr 23 02:09:49 PM PDT 24
Finished Apr 23 02:09:50 PM PDT 24
Peak memory 216172 kb
Host smart-3cf9bbc3-d0e1-4394-8cfa-29b0a218e432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962259021 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2962259021
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.951419088
Short name T75
Test name
Test status
Simulation time 19240267 ps
CPU time 1 seconds
Started Apr 23 02:09:49 PM PDT 24
Finished Apr 23 02:09:50 PM PDT 24
Peak memory 215468 kb
Host smart-1096f041-fa69-46d5-abc6-c0e0456b6081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951419088 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.951419088
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2806272609
Short name T681
Test name
Test status
Simulation time 69817764 ps
CPU time 1.98 seconds
Started Apr 23 02:10:10 PM PDT 24
Finished Apr 23 02:10:12 PM PDT 24
Peak memory 217348 kb
Host smart-eaf8eb8a-6a7e-48c0-a38e-22b6bc1c1653
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806272609 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2806272609
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2915517796
Short name T508
Test name
Test status
Simulation time 11229348392 ps
CPU time 261.64 seconds
Started Apr 23 02:10:04 PM PDT 24
Finished Apr 23 02:14:26 PM PDT 24
Peak memory 217624 kb
Host smart-247f3935-e67c-4ca2-a9d2-184ac3ca1383
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915517796 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2915517796
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3591739517
Short name T186
Test name
Test status
Simulation time 27520723 ps
CPU time 1.23 seconds
Started Apr 23 02:08:16 PM PDT 24
Finished Apr 23 02:08:18 PM PDT 24
Peak memory 215876 kb
Host smart-cf4fe73f-fb71-41b2-9429-8b5f611f9103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591739517 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3591739517
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2398650778
Short name T208
Test name
Test status
Simulation time 24665015 ps
CPU time 0.87 seconds
Started Apr 23 02:08:04 PM PDT 24
Finished Apr 23 02:08:06 PM PDT 24
Peak memory 215436 kb
Host smart-172808da-81ac-4b74-9cd3-62217d56e424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398650778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2398650778
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2594925235
Short name T788
Test name
Test status
Simulation time 12433967 ps
CPU time 0.93 seconds
Started Apr 23 02:08:07 PM PDT 24
Finished Apr 23 02:08:09 PM PDT 24
Peak memory 216392 kb
Host smart-40a81153-20bb-4750-a6dd-57bdf5effdba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594925235 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2594925235
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3809845488
Short name T112
Test name
Test status
Simulation time 53623897 ps
CPU time 1.16 seconds
Started Apr 23 02:08:16 PM PDT 24
Finished Apr 23 02:08:18 PM PDT 24
Peak memory 217252 kb
Host smart-3b49ff17-f159-4d18-b806-50106f99a636
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809845488 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3809845488
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.440021066
Short name T570
Test name
Test status
Simulation time 53943630 ps
CPU time 1.25 seconds
Started Apr 23 02:08:10 PM PDT 24
Finished Apr 23 02:08:12 PM PDT 24
Peak memory 219844 kb
Host smart-6854b8ae-8a94-4ebf-986b-913dd3271e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440021066 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.440021066
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1801754431
Short name T493
Test name
Test status
Simulation time 71165710 ps
CPU time 2.15 seconds
Started Apr 23 02:08:06 PM PDT 24
Finished Apr 23 02:08:09 PM PDT 24
Peak memory 217272 kb
Host smart-f66d6960-9055-4dad-9cf6-3788f5b16f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801754431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1801754431
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1064732280
Short name T717
Test name
Test status
Simulation time 31820331 ps
CPU time 0.87 seconds
Started Apr 23 02:08:05 PM PDT 24
Finished Apr 23 02:08:07 PM PDT 24
Peak memory 215916 kb
Host smart-9722652b-6686-4abb-a161-3e760de0b346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064732280 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1064732280
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1637518078
Short name T259
Test name
Test status
Simulation time 26724099 ps
CPU time 0.92 seconds
Started Apr 23 02:08:06 PM PDT 24
Finished Apr 23 02:08:07 PM PDT 24
Peak memory 207316 kb
Host smart-604edbe7-ae44-43cd-8da1-62ad6630d418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637518078 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1637518078
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2264790394
Short name T329
Test name
Test status
Simulation time 26449225 ps
CPU time 0.93 seconds
Started Apr 23 02:08:05 PM PDT 24
Finished Apr 23 02:08:06 PM PDT 24
Peak memory 215540 kb
Host smart-05c0acd0-9abe-4cd6-a4ee-8371d297db8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264790394 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2264790394
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.960533540
Short name T735
Test name
Test status
Simulation time 538619464 ps
CPU time 3.22 seconds
Started Apr 23 02:08:15 PM PDT 24
Finished Apr 23 02:08:19 PM PDT 24
Peak memory 217304 kb
Host smart-43f4c685-2791-48e5-a0d7-84da2178e6ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960533540 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.960533540
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.715045197
Short name T197
Test name
Test status
Simulation time 27188310789 ps
CPU time 691.8 seconds
Started Apr 23 02:08:15 PM PDT 24
Finished Apr 23 02:19:48 PM PDT 24
Peak memory 218272 kb
Host smart-127fe113-f9d0-48ef-ba88-f82583bcf0f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715045197 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.715045197
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.2529402317
Short name T172
Test name
Test status
Simulation time 29846772 ps
CPU time 0.86 seconds
Started Apr 23 02:10:10 PM PDT 24
Finished Apr 23 02:10:12 PM PDT 24
Peak memory 218444 kb
Host smart-4b81f133-8a20-48d8-8cb7-18f04825b824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529402317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2529402317
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1715674635
Short name T57
Test name
Test status
Simulation time 87277705 ps
CPU time 1.16 seconds
Started Apr 23 02:09:59 PM PDT 24
Finished Apr 23 02:10:01 PM PDT 24
Peak memory 217416 kb
Host smart-47678ef8-9d4d-4239-8b60-18feace8ee99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715674635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1715674635
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.3172950884
Short name T312
Test name
Test status
Simulation time 30170997 ps
CPU time 0.87 seconds
Started Apr 23 02:10:02 PM PDT 24
Finished Apr 23 02:10:03 PM PDT 24
Peak memory 218380 kb
Host smart-f6ae55b8-ef6b-4b8c-acc4-e29a567c4785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172950884 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3172950884
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3072198843
Short name T700
Test name
Test status
Simulation time 52641422 ps
CPU time 1.61 seconds
Started Apr 23 02:09:59 PM PDT 24
Finished Apr 23 02:10:01 PM PDT 24
Peak memory 219452 kb
Host smart-d49c12e2-f54e-40c0-ac55-58184e25b531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072198843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3072198843
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.430742122
Short name T834
Test name
Test status
Simulation time 39280858 ps
CPU time 1.01 seconds
Started Apr 23 02:10:09 PM PDT 24
Finished Apr 23 02:10:10 PM PDT 24
Peak memory 224344 kb
Host smart-8d00bd78-3068-4607-bb4e-04da44b58a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430742122 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.430742122
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.331470325
Short name T627
Test name
Test status
Simulation time 123955182 ps
CPU time 1.57 seconds
Started Apr 23 02:10:02 PM PDT 24
Finished Apr 23 02:10:04 PM PDT 24
Peak memory 218908 kb
Host smart-a181a963-8927-47db-ae48-39f9b305607c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331470325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.331470325
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.3557715051
Short name T119
Test name
Test status
Simulation time 18374407 ps
CPU time 1.07 seconds
Started Apr 23 02:10:03 PM PDT 24
Finished Apr 23 02:10:05 PM PDT 24
Peak memory 218700 kb
Host smart-e149f950-ad95-44c4-bd94-6ef54d4063fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557715051 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3557715051
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1012320264
Short name T590
Test name
Test status
Simulation time 96092869 ps
CPU time 1.35 seconds
Started Apr 23 02:09:58 PM PDT 24
Finished Apr 23 02:10:00 PM PDT 24
Peak memory 219868 kb
Host smart-0ea6742b-3901-4191-a29a-c6ab24f42357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012320264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1012320264
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.3189829623
Short name T721
Test name
Test status
Simulation time 29131011 ps
CPU time 1.23 seconds
Started Apr 23 02:10:10 PM PDT 24
Finished Apr 23 02:10:12 PM PDT 24
Peak memory 219756 kb
Host smart-474ab342-1e36-4f70-abf1-6c55a4c19c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189829623 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3189829623
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.534963881
Short name T345
Test name
Test status
Simulation time 242141268 ps
CPU time 1.26 seconds
Started Apr 23 02:10:12 PM PDT 24
Finished Apr 23 02:10:14 PM PDT 24
Peak memory 220044 kb
Host smart-fa246c2b-707a-4237-ad15-8ebb8a045443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534963881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.534963881
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.3825293810
Short name T838
Test name
Test status
Simulation time 20947234 ps
CPU time 1.08 seconds
Started Apr 23 02:10:10 PM PDT 24
Finished Apr 23 02:10:12 PM PDT 24
Peak memory 233124 kb
Host smart-cc0a8ca6-2b8a-4688-81f0-e08484e58dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825293810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3825293810
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2956452282
Short name T390
Test name
Test status
Simulation time 51691879 ps
CPU time 1.71 seconds
Started Apr 23 02:10:14 PM PDT 24
Finished Apr 23 02:10:16 PM PDT 24
Peak memory 218312 kb
Host smart-40895239-04c6-4b6c-a0b5-e2261ebdcbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956452282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2956452282
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.301964102
Short name T499
Test name
Test status
Simulation time 36370796 ps
CPU time 1.15 seconds
Started Apr 23 02:10:08 PM PDT 24
Finished Apr 23 02:10:10 PM PDT 24
Peak memory 224304 kb
Host smart-1400c6ac-1459-4337-87b1-61b73407664c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301964102 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.301964102
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3735838280
Short name T655
Test name
Test status
Simulation time 40565993 ps
CPU time 1.54 seconds
Started Apr 23 02:10:15 PM PDT 24
Finished Apr 23 02:10:18 PM PDT 24
Peak memory 218248 kb
Host smart-b94e4fbd-ebf6-404b-b93d-91bbb930704b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735838280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3735838280
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.1923624581
Short name T492
Test name
Test status
Simulation time 21011884 ps
CPU time 1.1 seconds
Started Apr 23 02:10:11 PM PDT 24
Finished Apr 23 02:10:13 PM PDT 24
Peak memory 224272 kb
Host smart-18f5bc26-4235-4988-8d2a-c0126c1a0e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923624581 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1923624581
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.222827715
Short name T394
Test name
Test status
Simulation time 49202850 ps
CPU time 1.2 seconds
Started Apr 23 02:10:05 PM PDT 24
Finished Apr 23 02:10:07 PM PDT 24
Peak memory 217132 kb
Host smart-03bee3e1-608d-4d43-b011-6ac8bec791ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222827715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.222827715
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.1453144147
Short name T7
Test name
Test status
Simulation time 40385735 ps
CPU time 1.14 seconds
Started Apr 23 02:10:06 PM PDT 24
Finished Apr 23 02:10:08 PM PDT 24
Peak memory 220828 kb
Host smart-a60afbda-f79a-4909-a97b-4683e2c4a5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453144147 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1453144147
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2523576733
Short name T192
Test name
Test status
Simulation time 87531988 ps
CPU time 1.2 seconds
Started Apr 23 02:10:09 PM PDT 24
Finished Apr 23 02:10:11 PM PDT 24
Peak memory 218624 kb
Host smart-7e70e468-37f5-44e5-8d85-9163dc66df36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523576733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2523576733
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.3338680821
Short name T136
Test name
Test status
Simulation time 18432195 ps
CPU time 1.12 seconds
Started Apr 23 02:10:10 PM PDT 24
Finished Apr 23 02:10:11 PM PDT 24
Peak memory 224448 kb
Host smart-9f7090f8-5704-405f-8d63-58c7bc89fc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338680821 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3338680821
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2553428762
Short name T753
Test name
Test status
Simulation time 60502072 ps
CPU time 1.35 seconds
Started Apr 23 02:10:01 PM PDT 24
Finished Apr 23 02:10:03 PM PDT 24
Peak memory 217328 kb
Host smart-6aaff0ab-8b27-4cff-b803-17f9d4eedf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553428762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2553428762
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.305065704
Short name T703
Test name
Test status
Simulation time 52249380 ps
CPU time 1.22 seconds
Started Apr 23 02:08:09 PM PDT 24
Finished Apr 23 02:08:11 PM PDT 24
Peak memory 215928 kb
Host smart-4d64ca20-f284-40eb-83a9-a12d15e7b1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305065704 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.305065704
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3472521042
Short name T599
Test name
Test status
Simulation time 19881620 ps
CPU time 0.84 seconds
Started Apr 23 02:08:09 PM PDT 24
Finished Apr 23 02:08:11 PM PDT 24
Peak memory 206672 kb
Host smart-bcc7c868-d252-4d71-8c35-7d0e16bb52a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472521042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3472521042
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.4034931647
Short name T769
Test name
Test status
Simulation time 86088531 ps
CPU time 0.92 seconds
Started Apr 23 02:08:09 PM PDT 24
Finished Apr 23 02:08:10 PM PDT 24
Peak memory 216604 kb
Host smart-a1fa8eea-a088-48e1-98f3-7e9af4be4e26
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034931647 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.4034931647
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2748894492
Short name T446
Test name
Test status
Simulation time 28007301 ps
CPU time 1.14 seconds
Started Apr 23 02:08:07 PM PDT 24
Finished Apr 23 02:08:09 PM PDT 24
Peak memory 217216 kb
Host smart-88aa0865-0f9c-4a0c-9267-0356dae505cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748894492 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2748894492
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1347577086
Short name T98
Test name
Test status
Simulation time 21783533 ps
CPU time 1.09 seconds
Started Apr 23 02:08:10 PM PDT 24
Finished Apr 23 02:08:11 PM PDT 24
Peak memory 219988 kb
Host smart-cf4a545b-7a94-4581-bf1b-b9c3de8e9906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347577086 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1347577086
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.436863566
Short name T399
Test name
Test status
Simulation time 168410294 ps
CPU time 3.12 seconds
Started Apr 23 02:08:17 PM PDT 24
Finished Apr 23 02:08:21 PM PDT 24
Peak memory 220144 kb
Host smart-a54ea925-5650-411e-bc34-755a0c370fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436863566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.436863566
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.329241225
Short name T727
Test name
Test status
Simulation time 31435083 ps
CPU time 0.87 seconds
Started Apr 23 02:08:09 PM PDT 24
Finished Apr 23 02:08:10 PM PDT 24
Peak memory 215824 kb
Host smart-a48f1593-21cc-468e-bb14-d83dd31a346a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329241225 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.329241225
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.1065871843
Short name T819
Test name
Test status
Simulation time 49770179 ps
CPU time 0.99 seconds
Started Apr 23 02:08:08 PM PDT 24
Finished Apr 23 02:08:09 PM PDT 24
Peak memory 215532 kb
Host smart-5e35e4ef-1465-4173-b292-4504f761e24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065871843 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1065871843
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3558799629
Short name T601
Test name
Test status
Simulation time 95659046 ps
CPU time 1.61 seconds
Started Apr 23 02:08:09 PM PDT 24
Finished Apr 23 02:08:11 PM PDT 24
Peak memory 207292 kb
Host smart-27d1432f-183e-4414-ba3d-11c216bd4f70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558799629 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3558799629
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3971238519
Short name T807
Test name
Test status
Simulation time 31803953666 ps
CPU time 636.48 seconds
Started Apr 23 02:08:07 PM PDT 24
Finished Apr 23 02:18:44 PM PDT 24
Peak memory 223852 kb
Host smart-b268ce12-8470-4292-980b-15bee47cc3aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971238519 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3971238519
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.2729357447
Short name T525
Test name
Test status
Simulation time 31760693 ps
CPU time 0.87 seconds
Started Apr 23 02:10:06 PM PDT 24
Finished Apr 23 02:10:07 PM PDT 24
Peak memory 218836 kb
Host smart-15b460fc-aa15-4ce6-8591-0ca6cbca2306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729357447 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2729357447
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1370453332
Short name T707
Test name
Test status
Simulation time 42374726 ps
CPU time 1.7 seconds
Started Apr 23 02:10:10 PM PDT 24
Finished Apr 23 02:10:13 PM PDT 24
Peak memory 218580 kb
Host smart-54ff1908-94b2-460b-a0cd-c3305c1004d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370453332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1370453332
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.1158773329
Short name T765
Test name
Test status
Simulation time 30312925 ps
CPU time 1.29 seconds
Started Apr 23 02:10:15 PM PDT 24
Finished Apr 23 02:10:17 PM PDT 24
Peak memory 219736 kb
Host smart-e9abe367-d8c7-46f3-8506-de973909a82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158773329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1158773329
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.646142874
Short name T625
Test name
Test status
Simulation time 86970536 ps
CPU time 1.13 seconds
Started Apr 23 02:10:07 PM PDT 24
Finished Apr 23 02:10:09 PM PDT 24
Peak memory 217200 kb
Host smart-d29adabe-ca47-4e1e-813b-e869f6219cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646142874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.646142874
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.14373972
Short name T99
Test name
Test status
Simulation time 73272434 ps
CPU time 1.11 seconds
Started Apr 23 02:10:09 PM PDT 24
Finished Apr 23 02:10:11 PM PDT 24
Peak memory 230088 kb
Host smart-d00a17d7-d928-4498-a2aa-5d6bf7c5163b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14373972 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.14373972
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3247450823
Short name T545
Test name
Test status
Simulation time 45358534 ps
CPU time 1.49 seconds
Started Apr 23 02:10:05 PM PDT 24
Finished Apr 23 02:10:07 PM PDT 24
Peak memory 219708 kb
Host smart-cefbf1c4-1f1b-4461-aaf6-15eae65e9381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247450823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3247450823
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.3969541847
Short name T166
Test name
Test status
Simulation time 31467700 ps
CPU time 1.42 seconds
Started Apr 23 02:10:13 PM PDT 24
Finished Apr 23 02:10:15 PM PDT 24
Peak memory 225988 kb
Host smart-90b5e423-5480-483c-be04-b2f534c9ddcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969541847 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3969541847
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2629414
Short name T630
Test name
Test status
Simulation time 65037515 ps
CPU time 1.46 seconds
Started Apr 23 02:10:10 PM PDT 24
Finished Apr 23 02:10:12 PM PDT 24
Peak memory 218404 kb
Host smart-77dd6594-d212-40c5-8b9a-448963dababa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2629414
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.1175024962
Short name T392
Test name
Test status
Simulation time 32407068 ps
CPU time 0.89 seconds
Started Apr 23 02:10:15 PM PDT 24
Finished Apr 23 02:10:17 PM PDT 24
Peak memory 218724 kb
Host smart-93d9fdac-c2de-4722-b208-eea1332c3dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175024962 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1175024962
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.4033497606
Short name T344
Test name
Test status
Simulation time 144931727 ps
CPU time 2.1 seconds
Started Apr 23 02:10:11 PM PDT 24
Finished Apr 23 02:10:14 PM PDT 24
Peak memory 218828 kb
Host smart-b8d04fe4-2980-4037-b64b-807cd15aea30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033497606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.4033497606
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.3982029607
Short name T782
Test name
Test status
Simulation time 105186246 ps
CPU time 1.5 seconds
Started Apr 23 02:10:05 PM PDT 24
Finished Apr 23 02:10:07 PM PDT 24
Peak memory 225840 kb
Host smart-be0b90fa-2dd5-4e69-8521-d89e0458b27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982029607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3982029607
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2169664147
Short name T396
Test name
Test status
Simulation time 76954500 ps
CPU time 1.18 seconds
Started Apr 23 02:10:10 PM PDT 24
Finished Apr 23 02:10:12 PM PDT 24
Peak memory 217240 kb
Host smart-72abe007-9784-46c9-bd3e-81e31c7aa600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169664147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2169664147
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.1944835107
Short name T145
Test name
Test status
Simulation time 23112183 ps
CPU time 1.06 seconds
Started Apr 23 02:10:11 PM PDT 24
Finished Apr 23 02:10:13 PM PDT 24
Peak memory 224576 kb
Host smart-df35690c-86f9-4531-999b-3508416968fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944835107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1944835107
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2608296206
Short name T455
Test name
Test status
Simulation time 119611370 ps
CPU time 1.59 seconds
Started Apr 23 02:10:13 PM PDT 24
Finished Apr 23 02:10:15 PM PDT 24
Peak memory 218536 kb
Host smart-5c981c40-ee09-4de8-8f41-6cafdd7c1d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608296206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2608296206
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.3430349817
Short name T105
Test name
Test status
Simulation time 20586287 ps
CPU time 1.12 seconds
Started Apr 23 02:10:11 PM PDT 24
Finished Apr 23 02:10:12 PM PDT 24
Peak memory 220052 kb
Host smart-0c41f8b6-c12c-49eb-bbfa-5c4950a7b415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430349817 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3430349817
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.4096202404
Short name T76
Test name
Test status
Simulation time 60215709 ps
CPU time 1.12 seconds
Started Apr 23 02:10:06 PM PDT 24
Finished Apr 23 02:10:08 PM PDT 24
Peak memory 217144 kb
Host smart-315cf85c-482f-4620-a6a2-3c5e6802abf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096202404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.4096202404
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.2770562329
Short name T803
Test name
Test status
Simulation time 18952133 ps
CPU time 1.01 seconds
Started Apr 23 02:10:02 PM PDT 24
Finished Apr 23 02:10:03 PM PDT 24
Peak memory 218536 kb
Host smart-e698d546-1247-487d-a30e-970203a5c03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770562329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2770562329
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1991753324
Short name T512
Test name
Test status
Simulation time 58152634 ps
CPU time 1.02 seconds
Started Apr 23 02:10:00 PM PDT 24
Finished Apr 23 02:10:01 PM PDT 24
Peak memory 217344 kb
Host smart-d3f46965-6ed7-424a-8610-49136360d384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991753324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1991753324
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.3586307273
Short name T97
Test name
Test status
Simulation time 65418619 ps
CPU time 1.14 seconds
Started Apr 23 02:10:15 PM PDT 24
Finished Apr 23 02:10:17 PM PDT 24
Peak memory 220956 kb
Host smart-ca3d1acd-d340-4fa8-8fc5-1caf4c069974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586307273 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3586307273
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1494743890
Short name T744
Test name
Test status
Simulation time 113988419 ps
CPU time 2.3 seconds
Started Apr 23 02:10:05 PM PDT 24
Finished Apr 23 02:10:08 PM PDT 24
Peak memory 219480 kb
Host smart-d7edc954-9156-4d6e-b43a-482114948a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494743890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1494743890
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.183468033
Short name T127
Test name
Test status
Simulation time 42126184 ps
CPU time 1.2 seconds
Started Apr 23 02:08:13 PM PDT 24
Finished Apr 23 02:08:15 PM PDT 24
Peak memory 215876 kb
Host smart-f6678ce5-1e56-47b2-970e-ef4ae14c1a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183468033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.183468033
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3944306793
Short name T427
Test name
Test status
Simulation time 15047039 ps
CPU time 0.94 seconds
Started Apr 23 02:08:13 PM PDT 24
Finished Apr 23 02:08:15 PM PDT 24
Peak memory 206932 kb
Host smart-67d24b11-865a-4e7a-8a5c-6642bc1a0231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944306793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3944306793
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1235398384
Short name T634
Test name
Test status
Simulation time 24701706 ps
CPU time 0.94 seconds
Started Apr 23 02:08:14 PM PDT 24
Finished Apr 23 02:08:15 PM PDT 24
Peak memory 215704 kb
Host smart-301cc928-5529-4113-9e48-0d0cadeacd09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235398384 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1235398384
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1022194024
Short name T664
Test name
Test status
Simulation time 92747517 ps
CPU time 1.04 seconds
Started Apr 23 02:08:13 PM PDT 24
Finished Apr 23 02:08:15 PM PDT 24
Peak memory 218428 kb
Host smart-e25a45cb-636a-4179-a167-bca098e612bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022194024 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1022194024
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.4031281200
Short name T520
Test name
Test status
Simulation time 23223097 ps
CPU time 0.92 seconds
Started Apr 23 02:08:17 PM PDT 24
Finished Apr 23 02:08:19 PM PDT 24
Peak memory 218900 kb
Host smart-4b50ed2b-faf5-4374-add7-d16f856eb612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031281200 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.4031281200
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2999677182
Short name T789
Test name
Test status
Simulation time 67665419 ps
CPU time 1.15 seconds
Started Apr 23 02:08:13 PM PDT 24
Finished Apr 23 02:08:15 PM PDT 24
Peak memory 217308 kb
Host smart-29c30500-fa0f-473d-a3ff-92a8b777c680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999677182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2999677182
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3204312564
Short name T36
Test name
Test status
Simulation time 22898460 ps
CPU time 1.1 seconds
Started Apr 23 02:08:14 PM PDT 24
Finished Apr 23 02:08:16 PM PDT 24
Peak memory 216176 kb
Host smart-8714b6c3-d7a4-4a1c-aac8-1ddd9ef8cc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204312564 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3204312564
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.1370085073
Short name T261
Test name
Test status
Simulation time 27700713 ps
CPU time 0.98 seconds
Started Apr 23 02:08:12 PM PDT 24
Finished Apr 23 02:08:14 PM PDT 24
Peak memory 207320 kb
Host smart-165769ef-2f80-454f-94ff-c4c08450ad18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370085073 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1370085073
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1855753847
Short name T207
Test name
Test status
Simulation time 54948176 ps
CPU time 0.87 seconds
Started Apr 23 02:08:11 PM PDT 24
Finished Apr 23 02:08:12 PM PDT 24
Peak memory 215572 kb
Host smart-299effdb-6513-4fe6-9aee-434be9aff98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855753847 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1855753847
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2970278156
Short name T159
Test name
Test status
Simulation time 338624844 ps
CPU time 2.12 seconds
Started Apr 23 02:08:13 PM PDT 24
Finished Apr 23 02:08:16 PM PDT 24
Peak memory 215472 kb
Host smart-c4df1807-a01d-4c78-ab75-443c66e3b288
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970278156 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2970278156
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3517556305
Short name T809
Test name
Test status
Simulation time 227922864618 ps
CPU time 1311.97 seconds
Started Apr 23 02:08:14 PM PDT 24
Finished Apr 23 02:30:06 PM PDT 24
Peak memory 223480 kb
Host smart-7a88608c-b31c-4b31-a138-220f19ad210b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517556305 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3517556305
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.3739623807
Short name T695
Test name
Test status
Simulation time 23476740 ps
CPU time 0.97 seconds
Started Apr 23 02:10:13 PM PDT 24
Finished Apr 23 02:10:15 PM PDT 24
Peak memory 218896 kb
Host smart-83970a9b-1845-4834-b996-9a899712c26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739623807 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3739623807
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.532440352
Short name T685
Test name
Test status
Simulation time 91202518 ps
CPU time 1.48 seconds
Started Apr 23 02:10:10 PM PDT 24
Finished Apr 23 02:10:12 PM PDT 24
Peak memory 218944 kb
Host smart-e96c2292-0314-40b6-9f14-055c7ad67d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532440352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.532440352
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.932581438
Short name T309
Test name
Test status
Simulation time 41511745 ps
CPU time 0.85 seconds
Started Apr 23 02:10:07 PM PDT 24
Finished Apr 23 02:10:08 PM PDT 24
Peak memory 218768 kb
Host smart-e70e4d96-d00f-47c5-9909-b8a5baf82595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932581438 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.932581438
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2159743727
Short name T651
Test name
Test status
Simulation time 42649320 ps
CPU time 1.06 seconds
Started Apr 23 02:10:12 PM PDT 24
Finished Apr 23 02:10:14 PM PDT 24
Peak memory 217180 kb
Host smart-e79cffa4-0634-47ca-900a-3cc8c580765e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159743727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2159743727
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.1167683117
Short name T643
Test name
Test status
Simulation time 19016815 ps
CPU time 1.08 seconds
Started Apr 23 02:10:06 PM PDT 24
Finished Apr 23 02:10:08 PM PDT 24
Peak memory 218636 kb
Host smart-ef9c1aea-a61b-4aff-a5f9-f3accce94e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167683117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1167683117
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1197307328
Short name T215
Test name
Test status
Simulation time 78904190 ps
CPU time 2.78 seconds
Started Apr 23 02:10:08 PM PDT 24
Finished Apr 23 02:10:12 PM PDT 24
Peak memory 220048 kb
Host smart-860cf419-3700-4113-80c0-b245d7eb9ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197307328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1197307328
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.1532482347
Short name T812
Test name
Test status
Simulation time 42527948 ps
CPU time 0.91 seconds
Started Apr 23 02:10:17 PM PDT 24
Finished Apr 23 02:10:19 PM PDT 24
Peak memory 219988 kb
Host smart-9093410d-14bd-40bb-b37e-a620ffdd4118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532482347 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1532482347
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1806811918
Short name T839
Test name
Test status
Simulation time 26801577 ps
CPU time 1.4 seconds
Started Apr 23 02:10:15 PM PDT 24
Finished Apr 23 02:10:16 PM PDT 24
Peak memory 217636 kb
Host smart-49dd73e6-ed0e-48ab-b589-f544f0f8a015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806811918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1806811918
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.1116299268
Short name T826
Test name
Test status
Simulation time 26279253 ps
CPU time 0.98 seconds
Started Apr 23 02:10:13 PM PDT 24
Finished Apr 23 02:10:14 PM PDT 24
Peak memory 219728 kb
Host smart-fa85b812-56e5-4f5a-bff7-3bad27ca8872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116299268 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1116299268
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3681793386
Short name T323
Test name
Test status
Simulation time 45730819 ps
CPU time 1.56 seconds
Started Apr 23 02:10:14 PM PDT 24
Finished Apr 23 02:10:16 PM PDT 24
Peak memory 219940 kb
Host smart-ea430e43-fddc-47f3-b7b1-caa44cb47c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681793386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3681793386
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.250326792
Short name T459
Test name
Test status
Simulation time 31811964 ps
CPU time 0.87 seconds
Started Apr 23 02:10:14 PM PDT 24
Finished Apr 23 02:10:15 PM PDT 24
Peak memory 218724 kb
Host smart-e7de2b0a-cc00-4fb5-a45e-8bff91bedabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250326792 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.250326792
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3617343103
Short name T577
Test name
Test status
Simulation time 336825009 ps
CPU time 4.4 seconds
Started Apr 23 02:10:19 PM PDT 24
Finished Apr 23 02:10:23 PM PDT 24
Peak memory 220200 kb
Host smart-dc86ab59-81f9-4d52-af94-613df9968661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617343103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3617343103
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.1210378801
Short name T546
Test name
Test status
Simulation time 29302267 ps
CPU time 1.2 seconds
Started Apr 23 02:10:15 PM PDT 24
Finished Apr 23 02:10:17 PM PDT 24
Peak memory 220060 kb
Host smart-b78814cc-f883-4415-a6ea-e649169307fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210378801 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1210378801
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1262646071
Short name T3
Test name
Test status
Simulation time 52428029 ps
CPU time 1.08 seconds
Started Apr 23 02:10:14 PM PDT 24
Finished Apr 23 02:10:16 PM PDT 24
Peak memory 219712 kb
Host smart-a17bcbc0-bbc8-4657-872f-25de6b48be8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262646071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1262646071
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.1801687551
Short name T626
Test name
Test status
Simulation time 18701484 ps
CPU time 1.08 seconds
Started Apr 23 02:10:16 PM PDT 24
Finished Apr 23 02:10:18 PM PDT 24
Peak memory 218580 kb
Host smart-c25927aa-01b8-4e6a-8ee5-d5ea4995344d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801687551 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1801687551
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3814156609
Short name T541
Test name
Test status
Simulation time 36131043 ps
CPU time 1.38 seconds
Started Apr 23 02:10:14 PM PDT 24
Finished Apr 23 02:10:16 PM PDT 24
Peak memory 218528 kb
Host smart-1532feb0-f04d-4a3d-8c44-f43409272d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814156609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3814156609
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.1450587192
Short name T833
Test name
Test status
Simulation time 37730602 ps
CPU time 0.83 seconds
Started Apr 23 02:10:18 PM PDT 24
Finished Apr 23 02:10:19 PM PDT 24
Peak memory 218508 kb
Host smart-3a4ae065-c905-4ccc-8bc7-43d449364f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450587192 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1450587192
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2697913925
Short name T318
Test name
Test status
Simulation time 44963382 ps
CPU time 1.24 seconds
Started Apr 23 02:10:19 PM PDT 24
Finished Apr 23 02:10:20 PM PDT 24
Peak memory 218592 kb
Host smart-921ededa-4a08-44e0-bd14-9702f9639f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697913925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2697913925
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.2427175531
Short name T773
Test name
Test status
Simulation time 18242510 ps
CPU time 1.05 seconds
Started Apr 23 02:10:16 PM PDT 24
Finished Apr 23 02:10:18 PM PDT 24
Peak memory 218516 kb
Host smart-cdeec491-5ec9-48d9-bf74-1644fe29f741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427175531 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2427175531
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1489066523
Short name T434
Test name
Test status
Simulation time 110044293 ps
CPU time 1.63 seconds
Started Apr 23 02:10:25 PM PDT 24
Finished Apr 23 02:10:26 PM PDT 24
Peak memory 217688 kb
Host smart-11537c8e-d2f0-4ea6-aedc-2a863ef7b245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489066523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1489066523
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.4146995367
Short name T267
Test name
Test status
Simulation time 25548239 ps
CPU time 1.32 seconds
Started Apr 23 02:08:15 PM PDT 24
Finished Apr 23 02:08:17 PM PDT 24
Peak memory 215928 kb
Host smart-ddceb6b5-0590-4b19-9a19-96af85aad2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146995367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.4146995367
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.853587726
Short name T648
Test name
Test status
Simulation time 26097989 ps
CPU time 0.88 seconds
Started Apr 23 02:08:19 PM PDT 24
Finished Apr 23 02:08:21 PM PDT 24
Peak memory 215128 kb
Host smart-24c4a747-322b-4d77-aac8-9665e2874ef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853587726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.853587726
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2626803341
Short name T300
Test name
Test status
Simulation time 68808090 ps
CPU time 1.15 seconds
Started Apr 23 02:08:19 PM PDT 24
Finished Apr 23 02:08:20 PM PDT 24
Peak memory 218328 kb
Host smart-2cdaa4b9-1ea2-4ffe-a921-6bcfac30dae0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626803341 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2626803341
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.4054432354
Short name T740
Test name
Test status
Simulation time 25562394 ps
CPU time 1.22 seconds
Started Apr 23 02:08:13 PM PDT 24
Finished Apr 23 02:08:15 PM PDT 24
Peak memory 221128 kb
Host smart-16cbba22-5a68-4094-990c-674721a68ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054432354 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.4054432354
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.872713811
Short name T629
Test name
Test status
Simulation time 162810945 ps
CPU time 1.59 seconds
Started Apr 23 02:08:15 PM PDT 24
Finished Apr 23 02:08:17 PM PDT 24
Peak memory 220020 kb
Host smart-46b68821-2738-458d-9f89-4f4b0611d3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872713811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.872713811
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2334892409
Short name T767
Test name
Test status
Simulation time 34513658 ps
CPU time 0.89 seconds
Started Apr 23 02:08:15 PM PDT 24
Finished Apr 23 02:08:17 PM PDT 24
Peak memory 215848 kb
Host smart-5634ba36-f938-4b76-8615-0a08ccecac5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334892409 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2334892409
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.807428169
Short name T25
Test name
Test status
Simulation time 17127726 ps
CPU time 0.97 seconds
Started Apr 23 02:08:12 PM PDT 24
Finished Apr 23 02:08:13 PM PDT 24
Peak memory 207404 kb
Host smart-2aa76b1e-366a-42d0-9827-7434810d214c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807428169 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.807428169
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3675836552
Short name T465
Test name
Test status
Simulation time 18996673 ps
CPU time 1.01 seconds
Started Apr 23 02:08:14 PM PDT 24
Finished Apr 23 02:08:15 PM PDT 24
Peak memory 215536 kb
Host smart-75309243-c5f2-4459-81ec-14aa429e7bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675836552 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3675836552
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.4188013424
Short name T702
Test name
Test status
Simulation time 752978925 ps
CPU time 4.57 seconds
Started Apr 23 02:08:15 PM PDT 24
Finished Apr 23 02:08:20 PM PDT 24
Peak memory 220432 kb
Host smart-a2356a7f-9ef3-4c6b-8636-febb0a30cff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188013424 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.4188013424
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1544353191
Short name T510
Test name
Test status
Simulation time 31429296800 ps
CPU time 181.88 seconds
Started Apr 23 02:08:14 PM PDT 24
Finished Apr 23 02:11:17 PM PDT 24
Peak memory 217736 kb
Host smart-1de58e80-13ff-4dfb-9627-9395affc43be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544353191 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1544353191
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.3579519480
Short name T144
Test name
Test status
Simulation time 32727552 ps
CPU time 0.85 seconds
Started Apr 23 02:10:17 PM PDT 24
Finished Apr 23 02:10:18 PM PDT 24
Peak memory 218620 kb
Host smart-44f0a514-814e-407e-afc8-55fc284d1ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579519480 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3579519480
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.4276136338
Short name T279
Test name
Test status
Simulation time 33853314 ps
CPU time 1.31 seconds
Started Apr 23 02:10:18 PM PDT 24
Finished Apr 23 02:10:19 PM PDT 24
Peak memory 219840 kb
Host smart-62b738f5-12c6-4a32-a830-80afffb5744c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276136338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.4276136338
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.2976095224
Short name T594
Test name
Test status
Simulation time 42389146 ps
CPU time 0.86 seconds
Started Apr 23 02:10:15 PM PDT 24
Finished Apr 23 02:10:17 PM PDT 24
Peak memory 218184 kb
Host smart-d4e28cfc-368b-40b3-8ba2-b59b697be521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976095224 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2976095224
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2555686765
Short name T444
Test name
Test status
Simulation time 41451088 ps
CPU time 1.11 seconds
Started Apr 23 02:10:19 PM PDT 24
Finished Apr 23 02:10:20 PM PDT 24
Peak memory 218764 kb
Host smart-6916fcbe-c739-4b0d-9b4b-e00daea7a709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555686765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2555686765
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.392724611
Short name T13
Test name
Test status
Simulation time 24818386 ps
CPU time 1.27 seconds
Started Apr 23 02:10:12 PM PDT 24
Finished Apr 23 02:10:14 PM PDT 24
Peak memory 230016 kb
Host smart-8d82e8d3-ede8-4483-bcec-568ee496df2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392724611 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.392724611
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1705749091
Short name T357
Test name
Test status
Simulation time 43543799 ps
CPU time 1.31 seconds
Started Apr 23 02:10:16 PM PDT 24
Finished Apr 23 02:10:18 PM PDT 24
Peak memory 218484 kb
Host smart-673572c6-b698-4816-a2cd-78e6efa68766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705749091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1705749091
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.3887293208
Short name T93
Test name
Test status
Simulation time 24508081 ps
CPU time 0.97 seconds
Started Apr 23 02:10:17 PM PDT 24
Finished Apr 23 02:10:19 PM PDT 24
Peak memory 220052 kb
Host smart-5f592ea3-2bd9-4375-aeff-9ac41bcd8b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887293208 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3887293208
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.164358447
Short name T619
Test name
Test status
Simulation time 89367121 ps
CPU time 1.03 seconds
Started Apr 23 02:10:15 PM PDT 24
Finished Apr 23 02:10:17 PM PDT 24
Peak memory 217368 kb
Host smart-81f4227e-4810-4812-9ce6-8a5bb0db2c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164358447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.164358447
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.3105676314
Short name T588
Test name
Test status
Simulation time 45132405 ps
CPU time 0.82 seconds
Started Apr 23 02:10:26 PM PDT 24
Finished Apr 23 02:10:28 PM PDT 24
Peak memory 218500 kb
Host smart-e3c154cd-a6ff-4ee4-805f-d42d84a0f3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105676314 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3105676314
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.853810257
Short name T351
Test name
Test status
Simulation time 35840149 ps
CPU time 1.35 seconds
Started Apr 23 02:10:19 PM PDT 24
Finished Apr 23 02:10:21 PM PDT 24
Peak memory 219848 kb
Host smart-01f68d53-5495-440f-9ca8-6d7d024e532a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853810257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.853810257
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.1332751151
Short name T509
Test name
Test status
Simulation time 60907822 ps
CPU time 1.19 seconds
Started Apr 23 02:10:28 PM PDT 24
Finished Apr 23 02:10:29 PM PDT 24
Peak memory 226068 kb
Host smart-2b33bfb3-49b7-4ef2-bb86-37567c13c1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332751151 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1332751151
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2127980584
Short name T530
Test name
Test status
Simulation time 44856501 ps
CPU time 1.6 seconds
Started Apr 23 02:10:26 PM PDT 24
Finished Apr 23 02:10:28 PM PDT 24
Peak memory 217384 kb
Host smart-4052e6ed-a23c-418f-b702-b9694db5478e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127980584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2127980584
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1359313047
Short name T140
Test name
Test status
Simulation time 18776447 ps
CPU time 1.13 seconds
Started Apr 23 02:10:28 PM PDT 24
Finished Apr 23 02:10:30 PM PDT 24
Peak memory 224452 kb
Host smart-d85df1d6-cfbc-45b7-a01d-fa11f1b53bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359313047 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1359313047
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3021401981
Short name T734
Test name
Test status
Simulation time 72647530 ps
CPU time 1.2 seconds
Started Apr 23 02:10:27 PM PDT 24
Finished Apr 23 02:10:28 PM PDT 24
Peak memory 219844 kb
Host smart-f15e2cc6-703a-4656-9b50-0a3b1ff1725f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021401981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3021401981
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.737043419
Short name T640
Test name
Test status
Simulation time 23197374 ps
CPU time 1.15 seconds
Started Apr 23 02:10:26 PM PDT 24
Finished Apr 23 02:10:27 PM PDT 24
Peak memory 218896 kb
Host smart-c06dbae1-413c-4af1-a350-b819bc2bdc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737043419 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.737043419
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.20803952
Short name T385
Test name
Test status
Simulation time 31668311 ps
CPU time 1.27 seconds
Started Apr 23 02:10:28 PM PDT 24
Finished Apr 23 02:10:30 PM PDT 24
Peak memory 218496 kb
Host smart-e8c083ab-bbb2-49c0-9884-9f97330127e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20803952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.20803952
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.1064676715
Short name T164
Test name
Test status
Simulation time 133649414 ps
CPU time 1.22 seconds
Started Apr 23 02:10:30 PM PDT 24
Finished Apr 23 02:10:32 PM PDT 24
Peak memory 225984 kb
Host smart-3c390ce7-38b6-4818-aa46-7df165c16738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064676715 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1064676715
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2799729065
Short name T445
Test name
Test status
Simulation time 52124779 ps
CPU time 1.5 seconds
Started Apr 23 02:10:30 PM PDT 24
Finished Apr 23 02:10:32 PM PDT 24
Peak memory 218700 kb
Host smart-c6ff8a96-a81c-4f23-9fa7-72ad1c770bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799729065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2799729065
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.1714661643
Short name T584
Test name
Test status
Simulation time 23707263 ps
CPU time 1.11 seconds
Started Apr 23 02:10:25 PM PDT 24
Finished Apr 23 02:10:27 PM PDT 24
Peak memory 224424 kb
Host smart-04e93ade-18a4-435f-a0f3-0b5af8e5c159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714661643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1714661643
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.608117456
Short name T435
Test name
Test status
Simulation time 107076978 ps
CPU time 1.34 seconds
Started Apr 23 02:10:29 PM PDT 24
Finished Apr 23 02:10:32 PM PDT 24
Peak memory 220120 kb
Host smart-a22485da-2552-44d9-8a17-6b43a1d21c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608117456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.608117456
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert_test.1868254701
Short name T328
Test name
Test status
Simulation time 34325557 ps
CPU time 1.02 seconds
Started Apr 23 02:08:29 PM PDT 24
Finished Apr 23 02:08:30 PM PDT 24
Peak memory 215456 kb
Host smart-600457f4-43d0-4c85-9108-3d9b7fb0ce88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868254701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1868254701
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.872248655
Short name T177
Test name
Test status
Simulation time 40618421 ps
CPU time 0.87 seconds
Started Apr 23 02:08:20 PM PDT 24
Finished Apr 23 02:08:21 PM PDT 24
Peak memory 215680 kb
Host smart-e97dc759-077b-4dcc-bba5-c01eb5ec5352
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872248655 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.872248655
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3557093570
Short name T610
Test name
Test status
Simulation time 50619428 ps
CPU time 1.18 seconds
Started Apr 23 02:08:20 PM PDT 24
Finished Apr 23 02:08:21 PM PDT 24
Peak memory 218316 kb
Host smart-a8b7781a-d36a-4171-a231-55810e901f15
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557093570 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3557093570
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1476404373
Short name T135
Test name
Test status
Simulation time 20666458 ps
CPU time 1.06 seconds
Started Apr 23 02:08:21 PM PDT 24
Finished Apr 23 02:08:23 PM PDT 24
Peak memory 218676 kb
Host smart-e3cc08f7-aaf1-413c-a809-4c8ae96739e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476404373 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1476404373
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2650468535
Short name T423
Test name
Test status
Simulation time 62140179 ps
CPU time 1.33 seconds
Started Apr 23 02:08:19 PM PDT 24
Finished Apr 23 02:08:21 PM PDT 24
Peak memory 217176 kb
Host smart-b26ed96f-2ead-4a04-88c1-fb43c10adb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650468535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2650468535
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2032205714
Short name T456
Test name
Test status
Simulation time 26295795 ps
CPU time 0.99 seconds
Started Apr 23 02:08:22 PM PDT 24
Finished Apr 23 02:08:23 PM PDT 24
Peak memory 215668 kb
Host smart-da47e9f1-2bf8-44d4-854d-9a0fe08ac1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032205714 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2032205714
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.3238051564
Short name T462
Test name
Test status
Simulation time 36991564 ps
CPU time 0.96 seconds
Started Apr 23 02:08:20 PM PDT 24
Finished Apr 23 02:08:22 PM PDT 24
Peak memory 215580 kb
Host smart-ccf4e705-3774-4950-af96-80165ae61dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238051564 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3238051564
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3129798857
Short name T515
Test name
Test status
Simulation time 368997531 ps
CPU time 4.26 seconds
Started Apr 23 02:08:19 PM PDT 24
Finished Apr 23 02:08:24 PM PDT 24
Peak memory 215572 kb
Host smart-393fa7ea-f15a-4d16-bfa8-eed38eda57ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129798857 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3129798857
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.603519021
Short name T637
Test name
Test status
Simulation time 76495981749 ps
CPU time 481.16 seconds
Started Apr 23 02:08:18 PM PDT 24
Finished Apr 23 02:16:20 PM PDT 24
Peak memory 218980 kb
Host smart-865de930-0f44-44f4-bc1d-6db63780fdc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603519021 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.603519021
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.1431172958
Short name T638
Test name
Test status
Simulation time 25255423 ps
CPU time 1.29 seconds
Started Apr 23 02:10:26 PM PDT 24
Finished Apr 23 02:10:28 PM PDT 24
Peak memory 230032 kb
Host smart-165cb3ac-4f30-401f-a66e-b9ce15bf7c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431172958 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1431172958
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/91.edn_err.1213124290
Short name T137
Test name
Test status
Simulation time 20163069 ps
CPU time 1.07 seconds
Started Apr 23 02:10:29 PM PDT 24
Finished Apr 23 02:10:31 PM PDT 24
Peak memory 218808 kb
Host smart-f5c135c2-1f0b-42d3-ae7d-1edfe77b083d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213124290 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1213124290
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3929340715
Short name T665
Test name
Test status
Simulation time 299071626 ps
CPU time 3.69 seconds
Started Apr 23 02:10:25 PM PDT 24
Finished Apr 23 02:10:29 PM PDT 24
Peak memory 220276 kb
Host smart-a828a766-9472-45c9-ad19-1e7d007c0f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929340715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3929340715
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.362702479
Short name T104
Test name
Test status
Simulation time 100789346 ps
CPU time 1.04 seconds
Started Apr 23 02:10:30 PM PDT 24
Finished Apr 23 02:10:32 PM PDT 24
Peak memory 229840 kb
Host smart-623d4ee8-cd4c-48de-80e8-25d8d7027dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362702479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.362702479
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3789936901
Short name T488
Test name
Test status
Simulation time 141096383 ps
CPU time 2.84 seconds
Started Apr 23 02:10:31 PM PDT 24
Finished Apr 23 02:10:35 PM PDT 24
Peak memory 219888 kb
Host smart-397fa549-c7be-4eea-a670-6a54b8ba7e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789936901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3789936901
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.4214798730
Short name T182
Test name
Test status
Simulation time 311186271 ps
CPU time 1.04 seconds
Started Apr 23 02:10:28 PM PDT 24
Finished Apr 23 02:10:29 PM PDT 24
Peak memory 219888 kb
Host smart-fcdedeaa-1657-4af1-b6d1-c05a29706f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214798730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.4214798730
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2420382033
Short name T335
Test name
Test status
Simulation time 55201434 ps
CPU time 1.35 seconds
Started Apr 23 02:10:31 PM PDT 24
Finished Apr 23 02:10:33 PM PDT 24
Peak memory 218748 kb
Host smart-b42f90ef-b084-446d-8c10-3662092629c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420382033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2420382033
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.3179686354
Short name T607
Test name
Test status
Simulation time 26610728 ps
CPU time 1.29 seconds
Started Apr 23 02:10:27 PM PDT 24
Finished Apr 23 02:10:28 PM PDT 24
Peak memory 230048 kb
Host smart-494fb480-9672-442d-889e-e89cfcda31b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179686354 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3179686354
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1850974718
Short name T674
Test name
Test status
Simulation time 49524986 ps
CPU time 1.2 seconds
Started Apr 23 02:10:29 PM PDT 24
Finished Apr 23 02:10:31 PM PDT 24
Peak memory 217288 kb
Host smart-45ec3f18-0757-45f3-8663-142ee033c5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850974718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1850974718
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2296434779
Short name T350
Test name
Test status
Simulation time 31817108 ps
CPU time 0.89 seconds
Started Apr 23 02:10:26 PM PDT 24
Finished Apr 23 02:10:27 PM PDT 24
Peak memory 218800 kb
Host smart-4d5e5a51-b9c8-4be4-afcc-379412ecbf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296434779 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2296434779
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1766132868
Short name T560
Test name
Test status
Simulation time 38786954 ps
CPU time 1.43 seconds
Started Apr 23 02:10:29 PM PDT 24
Finished Apr 23 02:10:32 PM PDT 24
Peak memory 219876 kb
Host smart-f93d3a1d-2d14-47bf-8bbb-f05058bf635a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766132868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1766132868
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.2992736785
Short name T90
Test name
Test status
Simulation time 21617201 ps
CPU time 1.1 seconds
Started Apr 23 02:10:27 PM PDT 24
Finished Apr 23 02:10:29 PM PDT 24
Peak memory 220068 kb
Host smart-b3d5c311-cd5c-4f50-a793-0ee21523634d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992736785 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2992736785
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3641187183
Short name T747
Test name
Test status
Simulation time 204257672 ps
CPU time 1.81 seconds
Started Apr 23 02:10:13 PM PDT 24
Finished Apr 23 02:10:16 PM PDT 24
Peak memory 218768 kb
Host smart-45ab1318-6496-49af-9e44-a124645e0867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641187183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3641187183
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.981185648
Short name T52
Test name
Test status
Simulation time 18392517 ps
CPU time 1.12 seconds
Started Apr 23 02:10:27 PM PDT 24
Finished Apr 23 02:10:29 PM PDT 24
Peak memory 233072 kb
Host smart-76e9565b-8ce0-4094-95ee-dee88712f382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981185648 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.981185648
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3291324096
Short name T429
Test name
Test status
Simulation time 105730811 ps
CPU time 1.36 seconds
Started Apr 23 02:10:29 PM PDT 24
Finished Apr 23 02:10:32 PM PDT 24
Peak memory 219380 kb
Host smart-0dd6abd4-bdd0-4937-b8b7-f06debc4d337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291324096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3291324096
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1069763743
Short name T131
Test name
Test status
Simulation time 121915548 ps
CPU time 1.02 seconds
Started Apr 23 02:10:31 PM PDT 24
Finished Apr 23 02:10:33 PM PDT 24
Peak memory 219808 kb
Host smart-63a7706b-8720-41c5-92b4-b1ba2f34fd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069763743 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1069763743
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3833491379
Short name T299
Test name
Test status
Simulation time 110026557 ps
CPU time 2.6 seconds
Started Apr 23 02:10:30 PM PDT 24
Finished Apr 23 02:10:34 PM PDT 24
Peak memory 220132 kb
Host smart-3a8f111f-116c-40d8-a065-61b743a731ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833491379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3833491379
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.1342938088
Short name T91
Test name
Test status
Simulation time 30503289 ps
CPU time 1.21 seconds
Started Apr 23 02:10:30 PM PDT 24
Finished Apr 23 02:10:32 PM PDT 24
Peak memory 230048 kb
Host smart-a67751ee-7c0e-4c28-a5c5-f8070413689e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342938088 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1342938088
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1722283335
Short name T422
Test name
Test status
Simulation time 63523295 ps
CPU time 1.35 seconds
Started Apr 23 02:10:28 PM PDT 24
Finished Apr 23 02:10:30 PM PDT 24
Peak memory 217280 kb
Host smart-a7fcdca9-217e-4fc3-aa04-c08afba87fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722283335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1722283335
Directory /workspace/99.edn_genbits/latest
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