Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.50 98.24 93.64 91.35 82.08 96.76 99.77 92.64


Total test records in report: 975
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T791 /workspace/coverage/default/190.edn_genbits.1319407046 Apr 25 01:01:03 PM PDT 24 Apr 25 01:01:05 PM PDT 24 71435748 ps
T164 /workspace/coverage/default/19.edn_disable.3792735268 Apr 25 12:59:50 PM PDT 24 Apr 25 12:59:52 PM PDT 24 23378300 ps
T792 /workspace/coverage/default/30.edn_err.142005129 Apr 25 01:00:27 PM PDT 24 Apr 25 01:00:30 PM PDT 24 27437396 ps
T793 /workspace/coverage/default/48.edn_err.358215982 Apr 25 01:00:30 PM PDT 24 Apr 25 01:00:35 PM PDT 24 19769474 ps
T794 /workspace/coverage/default/47.edn_smoke.1974141444 Apr 25 01:00:17 PM PDT 24 Apr 25 01:00:21 PM PDT 24 76978655 ps
T159 /workspace/coverage/default/4.edn_disable.406562721 Apr 25 12:59:28 PM PDT 24 Apr 25 12:59:30 PM PDT 24 86462217 ps
T91 /workspace/coverage/default/40.edn_disable_auto_req_mode.1399327803 Apr 25 01:00:13 PM PDT 24 Apr 25 01:00:18 PM PDT 24 101172190 ps
T795 /workspace/coverage/default/39.edn_stress_all.2027613735 Apr 25 01:00:21 PM PDT 24 Apr 25 01:00:24 PM PDT 24 31408872 ps
T284 /workspace/coverage/default/8.edn_regwen.2874789081 Apr 25 12:59:31 PM PDT 24 Apr 25 12:59:33 PM PDT 24 22072025 ps
T796 /workspace/coverage/default/130.edn_genbits.470993656 Apr 25 01:00:47 PM PDT 24 Apr 25 01:00:51 PM PDT 24 110822668 ps
T797 /workspace/coverage/default/168.edn_genbits.1222335522 Apr 25 01:00:56 PM PDT 24 Apr 25 01:01:00 PM PDT 24 31683772 ps
T798 /workspace/coverage/default/37.edn_alert_test.82238087 Apr 25 01:00:17 PM PDT 24 Apr 25 01:00:20 PM PDT 24 21176693 ps
T799 /workspace/coverage/default/47.edn_genbits.3047238456 Apr 25 01:00:26 PM PDT 24 Apr 25 01:00:29 PM PDT 24 26263570 ps
T800 /workspace/coverage/default/43.edn_alert_test.2763136809 Apr 25 01:00:29 PM PDT 24 Apr 25 01:00:32 PM PDT 24 32181692 ps
T78 /workspace/coverage/default/47.edn_intr.1144597878 Apr 25 01:00:43 PM PDT 24 Apr 25 01:00:47 PM PDT 24 24546274 ps
T263 /workspace/coverage/default/275.edn_genbits.2872197055 Apr 25 01:01:18 PM PDT 24 Apr 25 01:01:22 PM PDT 24 154188230 ps
T801 /workspace/coverage/default/89.edn_genbits.1390009686 Apr 25 01:00:52 PM PDT 24 Apr 25 01:00:55 PM PDT 24 82969979 ps
T802 /workspace/coverage/default/0.edn_disable_auto_req_mode.2838828665 Apr 25 12:59:48 PM PDT 24 Apr 25 12:59:51 PM PDT 24 98833563 ps
T803 /workspace/coverage/default/95.edn_genbits.550518183 Apr 25 01:01:15 PM PDT 24 Apr 25 01:01:19 PM PDT 24 47151441 ps
T58 /workspace/coverage/default/4.edn_sec_cm.1025286042 Apr 25 12:59:33 PM PDT 24 Apr 25 12:59:39 PM PDT 24 251809276 ps
T804 /workspace/coverage/default/197.edn_genbits.2637149142 Apr 25 01:00:55 PM PDT 24 Apr 25 01:00:59 PM PDT 24 184651984 ps
T805 /workspace/coverage/default/39.edn_err.2051620946 Apr 25 01:00:37 PM PDT 24 Apr 25 01:00:42 PM PDT 24 37539656 ps
T187 /workspace/coverage/default/5.edn_disable.3901919405 Apr 25 12:59:34 PM PDT 24 Apr 25 12:59:36 PM PDT 24 12661680 ps
T806 /workspace/coverage/default/45.edn_intr.3901862936 Apr 25 01:00:23 PM PDT 24 Apr 25 01:00:25 PM PDT 24 26067000 ps
T807 /workspace/coverage/default/294.edn_genbits.1367124850 Apr 25 01:01:03 PM PDT 24 Apr 25 01:01:06 PM PDT 24 90628876 ps
T808 /workspace/coverage/default/11.edn_stress_all.3318743759 Apr 25 12:59:47 PM PDT 24 Apr 25 12:59:51 PM PDT 24 83121945 ps
T809 /workspace/coverage/default/46.edn_alert.2905002313 Apr 25 01:00:37 PM PDT 24 Apr 25 01:00:42 PM PDT 24 23238054 ps
T810 /workspace/coverage/default/133.edn_genbits.4150691433 Apr 25 01:00:50 PM PDT 24 Apr 25 01:00:54 PM PDT 24 48046467 ps
T811 /workspace/coverage/default/19.edn_err.412693343 Apr 25 12:59:50 PM PDT 24 Apr 25 12:59:53 PM PDT 24 18765718 ps
T812 /workspace/coverage/default/71.edn_err.3977860034 Apr 25 01:00:51 PM PDT 24 Apr 25 01:00:54 PM PDT 24 21094111 ps
T813 /workspace/coverage/default/18.edn_disable.3289080663 Apr 25 01:00:01 PM PDT 24 Apr 25 01:00:03 PM PDT 24 17932353 ps
T814 /workspace/coverage/default/11.edn_disable_auto_req_mode.3989016633 Apr 25 12:59:44 PM PDT 24 Apr 25 12:59:48 PM PDT 24 247163716 ps
T815 /workspace/coverage/default/60.edn_genbits.2720463473 Apr 25 01:00:41 PM PDT 24 Apr 25 01:00:46 PM PDT 24 53437447 ps
T816 /workspace/coverage/default/264.edn_genbits.882733865 Apr 25 01:01:03 PM PDT 24 Apr 25 01:01:08 PM PDT 24 126886433 ps
T817 /workspace/coverage/default/40.edn_err.2846938002 Apr 25 01:00:32 PM PDT 24 Apr 25 01:00:39 PM PDT 24 27241699 ps
T818 /workspace/coverage/default/269.edn_genbits.750973398 Apr 25 01:01:19 PM PDT 24 Apr 25 01:01:23 PM PDT 24 30971349 ps
T819 /workspace/coverage/default/25.edn_disable_auto_req_mode.3353616031 Apr 25 12:59:58 PM PDT 24 Apr 25 01:00:00 PM PDT 24 104935070 ps
T820 /workspace/coverage/default/46.edn_alert_test.3081868080 Apr 25 01:00:32 PM PDT 24 Apr 25 01:00:39 PM PDT 24 59107562 ps
T821 /workspace/coverage/default/0.edn_stress_all.2497959680 Apr 25 12:59:14 PM PDT 24 Apr 25 12:59:24 PM PDT 24 148210880 ps
T822 /workspace/coverage/default/1.edn_intr.1216598254 Apr 25 12:59:21 PM PDT 24 Apr 25 12:59:23 PM PDT 24 25513329 ps
T823 /workspace/coverage/default/44.edn_alert_test.769481338 Apr 25 01:00:26 PM PDT 24 Apr 25 01:00:36 PM PDT 24 64651586 ps
T824 /workspace/coverage/default/14.edn_err.1786147968 Apr 25 12:59:53 PM PDT 24 Apr 25 12:59:55 PM PDT 24 22388911 ps
T825 /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1379169860 Apr 25 01:00:33 PM PDT 24 Apr 25 01:23:25 PM PDT 24 674364043761 ps
T826 /workspace/coverage/default/43.edn_genbits.4071392636 Apr 25 01:00:19 PM PDT 24 Apr 25 01:00:23 PM PDT 24 189996891 ps
T827 /workspace/coverage/default/43.edn_alert.19771362 Apr 25 01:00:24 PM PDT 24 Apr 25 01:00:27 PM PDT 24 42378345 ps
T828 /workspace/coverage/default/114.edn_genbits.539067591 Apr 25 01:01:03 PM PDT 24 Apr 25 01:01:06 PM PDT 24 37776258 ps
T829 /workspace/coverage/default/58.edn_err.3806470041 Apr 25 01:00:40 PM PDT 24 Apr 25 01:00:44 PM PDT 24 21579629 ps
T59 /workspace/coverage/default/0.edn_sec_cm.317807108 Apr 25 12:59:28 PM PDT 24 Apr 25 12:59:34 PM PDT 24 1008899582 ps
T264 /workspace/coverage/default/290.edn_genbits.4037172871 Apr 25 01:01:22 PM PDT 24 Apr 25 01:01:25 PM PDT 24 17960918 ps
T103 /workspace/coverage/default/9.edn_err.1718177501 Apr 25 12:59:57 PM PDT 24 Apr 25 01:00:00 PM PDT 24 48445519 ps
T830 /workspace/coverage/default/225.edn_genbits.3882666762 Apr 25 01:01:09 PM PDT 24 Apr 25 01:01:12 PM PDT 24 60729478 ps
T831 /workspace/coverage/default/41.edn_genbits.3303370951 Apr 25 01:00:16 PM PDT 24 Apr 25 01:00:21 PM PDT 24 43056587 ps
T832 /workspace/coverage/default/22.edn_err.1434993244 Apr 25 12:59:48 PM PDT 24 Apr 25 12:59:51 PM PDT 24 19082255 ps
T833 /workspace/coverage/default/101.edn_genbits.4123573981 Apr 25 01:00:56 PM PDT 24 Apr 25 01:00:59 PM PDT 24 51029697 ps
T834 /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2672266972 Apr 25 01:00:00 PM PDT 24 Apr 25 01:09:05 PM PDT 24 25456847969 ps
T835 /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3433334599 Apr 25 01:00:26 PM PDT 24 Apr 25 01:19:43 PM PDT 24 44907833484 ps
T836 /workspace/coverage/default/145.edn_genbits.2230364226 Apr 25 01:01:03 PM PDT 24 Apr 25 01:01:05 PM PDT 24 61696788 ps
T837 /workspace/coverage/default/226.edn_genbits.3850248212 Apr 25 01:01:19 PM PDT 24 Apr 25 01:01:23 PM PDT 24 66899023 ps
T838 /workspace/coverage/default/247.edn_genbits.672182839 Apr 25 01:01:21 PM PDT 24 Apr 25 01:01:24 PM PDT 24 63803506 ps
T839 /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1622674295 Apr 25 01:00:15 PM PDT 24 Apr 25 01:08:30 PM PDT 24 63247622328 ps
T840 /workspace/coverage/cover_reg_top/0.edn_intr_test.3260563696 Apr 25 12:57:22 PM PDT 24 Apr 25 12:57:23 PM PDT 24 16435229 ps
T841 /workspace/coverage/cover_reg_top/9.edn_intr_test.3961566089 Apr 25 12:57:18 PM PDT 24 Apr 25 12:57:20 PM PDT 24 24551254 ps
T842 /workspace/coverage/cover_reg_top/3.edn_intr_test.4139385768 Apr 25 12:57:19 PM PDT 24 Apr 25 12:57:21 PM PDT 24 15957116 ps
T843 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3851569131 Apr 25 12:57:15 PM PDT 24 Apr 25 12:57:20 PM PDT 24 180558330 ps
T844 /workspace/coverage/cover_reg_top/26.edn_intr_test.2537122268 Apr 25 12:57:19 PM PDT 24 Apr 25 12:57:21 PM PDT 24 12782552 ps
T845 /workspace/coverage/cover_reg_top/19.edn_intr_test.2259653272 Apr 25 12:57:04 PM PDT 24 Apr 25 12:57:09 PM PDT 24 15595610 ps
T214 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1469073073 Apr 25 12:57:19 PM PDT 24 Apr 25 12:57:21 PM PDT 24 62091756 ps
T846 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1641237812 Apr 25 12:57:14 PM PDT 24 Apr 25 12:57:18 PM PDT 24 56169720 ps
T235 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2869745320 Apr 25 12:57:02 PM PDT 24 Apr 25 12:57:07 PM PDT 24 24083266 ps
T232 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1948638127 Apr 25 12:57:35 PM PDT 24 Apr 25 12:57:37 PM PDT 24 136358708 ps
T215 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1140302881 Apr 25 12:57:01 PM PDT 24 Apr 25 12:57:06 PM PDT 24 26816984 ps
T847 /workspace/coverage/cover_reg_top/38.edn_intr_test.2626568762 Apr 25 12:57:39 PM PDT 24 Apr 25 12:57:42 PM PDT 24 30109008 ps
T237 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.968799626 Apr 25 12:57:12 PM PDT 24 Apr 25 12:57:18 PM PDT 24 171971441 ps
T238 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3549796682 Apr 25 12:57:09 PM PDT 24 Apr 25 12:57:15 PM PDT 24 362701882 ps
T848 /workspace/coverage/cover_reg_top/45.edn_intr_test.1338882493 Apr 25 12:57:21 PM PDT 24 Apr 25 12:57:23 PM PDT 24 45279048 ps
T239 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3392680810 Apr 25 12:57:08 PM PDT 24 Apr 25 12:57:14 PM PDT 24 60589260 ps
T849 /workspace/coverage/cover_reg_top/41.edn_intr_test.2792639353 Apr 25 12:57:14 PM PDT 24 Apr 25 12:57:18 PM PDT 24 15015020 ps
T850 /workspace/coverage/cover_reg_top/12.edn_tl_errors.641191886 Apr 25 12:57:07 PM PDT 24 Apr 25 12:57:13 PM PDT 24 28154948 ps
T851 /workspace/coverage/cover_reg_top/20.edn_intr_test.2018440083 Apr 25 12:57:11 PM PDT 24 Apr 25 12:57:19 PM PDT 24 28060886 ps
T250 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3305415689 Apr 25 12:57:07 PM PDT 24 Apr 25 12:57:13 PM PDT 24 39971636 ps
T852 /workspace/coverage/cover_reg_top/28.edn_intr_test.1253391008 Apr 25 12:57:24 PM PDT 24 Apr 25 12:57:26 PM PDT 24 40738458 ps
T853 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3987774799 Apr 25 12:57:12 PM PDT 24 Apr 25 12:57:17 PM PDT 24 138789078 ps
T854 /workspace/coverage/cover_reg_top/37.edn_intr_test.3140972226 Apr 25 12:57:24 PM PDT 24 Apr 25 12:57:26 PM PDT 24 104542355 ps
T855 /workspace/coverage/cover_reg_top/32.edn_intr_test.2618333499 Apr 25 12:56:58 PM PDT 24 Apr 25 12:57:01 PM PDT 24 16138823 ps
T216 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1592612781 Apr 25 12:57:07 PM PDT 24 Apr 25 12:57:12 PM PDT 24 14046023 ps
T856 /workspace/coverage/cover_reg_top/8.edn_tl_errors.2252491175 Apr 25 12:57:01 PM PDT 24 Apr 25 12:57:08 PM PDT 24 55388055 ps
T217 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3703842875 Apr 25 12:57:01 PM PDT 24 Apr 25 12:57:07 PM PDT 24 27785127 ps
T233 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2711600620 Apr 25 12:57:19 PM PDT 24 Apr 25 12:57:22 PM PDT 24 35553986 ps
T857 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2328828953 Apr 25 12:57:38 PM PDT 24 Apr 25 12:57:41 PM PDT 24 79078004 ps
T858 /workspace/coverage/cover_reg_top/42.edn_intr_test.3501262885 Apr 25 12:57:33 PM PDT 24 Apr 25 12:57:35 PM PDT 24 14869371 ps
T859 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1134751773 Apr 25 12:56:56 PM PDT 24 Apr 25 12:57:00 PM PDT 24 37998472 ps
T860 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2628866993 Apr 25 12:57:08 PM PDT 24 Apr 25 12:57:16 PM PDT 24 166393334 ps
T236 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.4067491789 Apr 25 12:57:04 PM PDT 24 Apr 25 12:57:10 PM PDT 24 63658190 ps
T861 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2438358560 Apr 25 12:57:03 PM PDT 24 Apr 25 12:57:12 PM PDT 24 589373410 ps
T862 /workspace/coverage/cover_reg_top/48.edn_intr_test.564221853 Apr 25 12:57:16 PM PDT 24 Apr 25 12:57:19 PM PDT 24 18822243 ps
T234 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.4054856073 Apr 25 12:57:06 PM PDT 24 Apr 25 12:57:12 PM PDT 24 21947860 ps
T863 /workspace/coverage/cover_reg_top/1.edn_intr_test.134899513 Apr 25 12:56:53 PM PDT 24 Apr 25 12:56:55 PM PDT 24 14086259 ps
T864 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1015503598 Apr 25 12:57:37 PM PDT 24 Apr 25 12:57:40 PM PDT 24 78477959 ps
T865 /workspace/coverage/cover_reg_top/49.edn_intr_test.2148719537 Apr 25 12:57:25 PM PDT 24 Apr 25 12:57:27 PM PDT 24 23276750 ps
T866 /workspace/coverage/cover_reg_top/13.edn_tl_errors.969217600 Apr 25 12:57:20 PM PDT 24 Apr 25 12:57:24 PM PDT 24 148798505 ps
T867 /workspace/coverage/cover_reg_top/35.edn_intr_test.1965384729 Apr 25 12:57:25 PM PDT 24 Apr 25 12:57:27 PM PDT 24 20857849 ps
T218 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3834681816 Apr 25 12:57:08 PM PDT 24 Apr 25 12:57:13 PM PDT 24 82948626 ps
T219 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.662786968 Apr 25 12:57:07 PM PDT 24 Apr 25 12:57:17 PM PDT 24 21895559 ps
T868 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2930986403 Apr 25 12:57:13 PM PDT 24 Apr 25 12:57:18 PM PDT 24 89466104 ps
T220 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1174316889 Apr 25 12:56:58 PM PDT 24 Apr 25 12:57:02 PM PDT 24 12534889 ps
T869 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3967151326 Apr 25 12:57:02 PM PDT 24 Apr 25 12:57:08 PM PDT 24 162476048 ps
T221 /workspace/coverage/cover_reg_top/13.edn_csr_rw.826344538 Apr 25 12:57:07 PM PDT 24 Apr 25 12:57:12 PM PDT 24 57114255 ps
T870 /workspace/coverage/cover_reg_top/10.edn_intr_test.642708513 Apr 25 12:56:58 PM PDT 24 Apr 25 12:57:01 PM PDT 24 42882586 ps
T871 /workspace/coverage/cover_reg_top/31.edn_intr_test.2981228952 Apr 25 12:57:38 PM PDT 24 Apr 25 12:57:41 PM PDT 24 11886615 ps
T222 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1592845299 Apr 25 12:56:58 PM PDT 24 Apr 25 12:57:04 PM PDT 24 126154370 ps
T872 /workspace/coverage/cover_reg_top/13.edn_intr_test.1053902156 Apr 25 12:57:05 PM PDT 24 Apr 25 12:57:11 PM PDT 24 15560559 ps
T873 /workspace/coverage/cover_reg_top/47.edn_intr_test.2120311888 Apr 25 12:57:21 PM PDT 24 Apr 25 12:57:23 PM PDT 24 16476667 ps
T874 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1519318898 Apr 25 12:57:00 PM PDT 24 Apr 25 12:57:04 PM PDT 24 40733562 ps
T875 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3615687606 Apr 25 12:57:01 PM PDT 24 Apr 25 12:57:06 PM PDT 24 80899638 ps
T876 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.406493446 Apr 25 12:56:58 PM PDT 24 Apr 25 12:57:03 PM PDT 24 59751207 ps
T877 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2615039454 Apr 25 12:57:02 PM PDT 24 Apr 25 12:57:09 PM PDT 24 66416359 ps
T878 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2947043638 Apr 25 12:57:29 PM PDT 24 Apr 25 12:57:32 PM PDT 24 48269287 ps
T879 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3660247960 Apr 25 12:57:02 PM PDT 24 Apr 25 12:57:08 PM PDT 24 207933650 ps
T880 /workspace/coverage/cover_reg_top/25.edn_intr_test.972556579 Apr 25 12:57:03 PM PDT 24 Apr 25 12:57:09 PM PDT 24 42589064 ps
T881 /workspace/coverage/cover_reg_top/18.edn_intr_test.1061153915 Apr 25 12:57:19 PM PDT 24 Apr 25 12:57:22 PM PDT 24 75811801 ps
T223 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.463467302 Apr 25 12:56:59 PM PDT 24 Apr 25 12:57:03 PM PDT 24 22299798 ps
T882 /workspace/coverage/cover_reg_top/15.edn_intr_test.3092579328 Apr 25 12:57:00 PM PDT 24 Apr 25 12:57:05 PM PDT 24 10687981 ps
T252 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.85302594 Apr 25 12:57:00 PM PDT 24 Apr 25 12:57:06 PM PDT 24 130903499 ps
T883 /workspace/coverage/cover_reg_top/5.edn_intr_test.872910986 Apr 25 12:57:18 PM PDT 24 Apr 25 12:57:20 PM PDT 24 42042035 ps
T884 /workspace/coverage/cover_reg_top/22.edn_intr_test.1770068263 Apr 25 12:57:02 PM PDT 24 Apr 25 12:57:08 PM PDT 24 24439388 ps
T224 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2493975348 Apr 25 12:57:02 PM PDT 24 Apr 25 12:57:08 PM PDT 24 12355692 ps
T885 /workspace/coverage/cover_reg_top/14.edn_intr_test.402909049 Apr 25 12:57:01 PM PDT 24 Apr 25 12:57:06 PM PDT 24 21067111 ps
T886 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.260202960 Apr 25 12:57:09 PM PDT 24 Apr 25 12:57:16 PM PDT 24 91602993 ps
T887 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2671035861 Apr 25 12:56:59 PM PDT 24 Apr 25 12:57:03 PM PDT 24 171418572 ps
T888 /workspace/coverage/cover_reg_top/27.edn_intr_test.1594713208 Apr 25 12:57:42 PM PDT 24 Apr 25 12:57:45 PM PDT 24 71126912 ps
T889 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2455840979 Apr 25 12:57:36 PM PDT 24 Apr 25 12:57:39 PM PDT 24 28753433 ps
T890 /workspace/coverage/cover_reg_top/39.edn_intr_test.2859129636 Apr 25 12:57:34 PM PDT 24 Apr 25 12:57:36 PM PDT 24 42723160 ps
T891 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.367648047 Apr 25 12:56:58 PM PDT 24 Apr 25 12:57:02 PM PDT 24 37984447 ps
T892 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3733566128 Apr 25 12:57:35 PM PDT 24 Apr 25 12:57:37 PM PDT 24 27086652 ps
T893 /workspace/coverage/cover_reg_top/14.edn_tl_errors.889932721 Apr 25 12:57:12 PM PDT 24 Apr 25 12:57:17 PM PDT 24 238486041 ps
T894 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3686193039 Apr 25 12:57:02 PM PDT 24 Apr 25 12:57:09 PM PDT 24 46932785 ps
T895 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1948714226 Apr 25 12:57:10 PM PDT 24 Apr 25 12:57:16 PM PDT 24 293050235 ps
T896 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.4186638379 Apr 25 12:57:04 PM PDT 24 Apr 25 12:57:11 PM PDT 24 23927605 ps
T897 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4124542036 Apr 25 12:57:20 PM PDT 24 Apr 25 12:57:27 PM PDT 24 60428360 ps
T898 /workspace/coverage/cover_reg_top/33.edn_intr_test.163411007 Apr 25 12:57:11 PM PDT 24 Apr 25 12:57:15 PM PDT 24 29623604 ps
T899 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2646773922 Apr 25 12:57:29 PM PDT 24 Apr 25 12:57:33 PM PDT 24 36475962 ps
T900 /workspace/coverage/cover_reg_top/16.edn_intr_test.1225847805 Apr 25 12:56:59 PM PDT 24 Apr 25 12:57:03 PM PDT 24 29627280 ps
T901 /workspace/coverage/cover_reg_top/9.edn_tl_errors.839074418 Apr 25 12:57:01 PM PDT 24 Apr 25 12:57:07 PM PDT 24 92249315 ps
T902 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1770405801 Apr 25 12:57:14 PM PDT 24 Apr 25 12:57:18 PM PDT 24 124920826 ps
T903 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1517708829 Apr 25 12:57:01 PM PDT 24 Apr 25 12:57:07 PM PDT 24 66121594 ps
T904 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2257231174 Apr 25 12:56:59 PM PDT 24 Apr 25 12:57:03 PM PDT 24 36164285 ps
T905 /workspace/coverage/cover_reg_top/8.edn_intr_test.1102230442 Apr 25 12:57:10 PM PDT 24 Apr 25 12:57:14 PM PDT 24 35946221 ps
T906 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2681380127 Apr 25 12:57:03 PM PDT 24 Apr 25 12:57:09 PM PDT 24 48979106 ps
T907 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.4061778938 Apr 25 12:57:42 PM PDT 24 Apr 25 12:57:45 PM PDT 24 12731574 ps
T908 /workspace/coverage/cover_reg_top/7.edn_csr_rw.946872715 Apr 25 12:57:26 PM PDT 24 Apr 25 12:57:29 PM PDT 24 39630506 ps
T909 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.59178097 Apr 25 12:57:23 PM PDT 24 Apr 25 12:57:25 PM PDT 24 38925010 ps
T910 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1561473326 Apr 25 12:57:14 PM PDT 24 Apr 25 12:57:22 PM PDT 24 13820552 ps
T911 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3737917028 Apr 25 12:57:00 PM PDT 24 Apr 25 12:57:05 PM PDT 24 81157971 ps
T912 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1592592803 Apr 25 12:57:32 PM PDT 24 Apr 25 12:57:35 PM PDT 24 85835973 ps
T913 /workspace/coverage/cover_reg_top/46.edn_intr_test.2214454599 Apr 25 12:57:24 PM PDT 24 Apr 25 12:57:26 PM PDT 24 22692449 ps
T914 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3729131437 Apr 25 12:57:08 PM PDT 24 Apr 25 12:57:14 PM PDT 24 187894398 ps
T915 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.341368670 Apr 25 12:57:09 PM PDT 24 Apr 25 12:57:14 PM PDT 24 51714901 ps
T916 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.490829239 Apr 25 12:57:03 PM PDT 24 Apr 25 12:57:09 PM PDT 24 24482472 ps
T251 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.713166420 Apr 25 12:57:02 PM PDT 24 Apr 25 12:57:09 PM PDT 24 155228117 ps
T917 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1788927459 Apr 25 12:57:03 PM PDT 24 Apr 25 12:57:09 PM PDT 24 107792572 ps
T918 /workspace/coverage/cover_reg_top/2.edn_intr_test.3841902056 Apr 25 12:56:59 PM PDT 24 Apr 25 12:57:03 PM PDT 24 12297835 ps
T225 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4232098644 Apr 25 12:57:30 PM PDT 24 Apr 25 12:57:32 PM PDT 24 58946580 ps
T919 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1480086898 Apr 25 12:57:30 PM PDT 24 Apr 25 12:57:33 PM PDT 24 250321132 ps
T920 /workspace/coverage/cover_reg_top/43.edn_intr_test.1000081518 Apr 25 12:57:29 PM PDT 24 Apr 25 12:57:36 PM PDT 24 11358985 ps
T921 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1284031533 Apr 25 12:57:34 PM PDT 24 Apr 25 12:57:37 PM PDT 24 133488485 ps
T226 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2249804278 Apr 25 12:57:27 PM PDT 24 Apr 25 12:57:29 PM PDT 24 13520417 ps
T922 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4147222731 Apr 25 12:57:06 PM PDT 24 Apr 25 12:57:14 PM PDT 24 121071052 ps
T923 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3985792325 Apr 25 12:57:07 PM PDT 24 Apr 25 12:57:13 PM PDT 24 12656835 ps
T924 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4116320403 Apr 25 12:57:28 PM PDT 24 Apr 25 12:57:30 PM PDT 24 74154905 ps
T925 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2259457988 Apr 25 12:57:13 PM PDT 24 Apr 25 12:57:17 PM PDT 24 41456004 ps
T926 /workspace/coverage/cover_reg_top/44.edn_intr_test.3701459787 Apr 25 12:57:20 PM PDT 24 Apr 25 12:57:22 PM PDT 24 17201319 ps
T927 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3172679460 Apr 25 12:57:01 PM PDT 24 Apr 25 12:57:06 PM PDT 24 21621772 ps
T230 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.737354466 Apr 25 12:57:06 PM PDT 24 Apr 25 12:57:17 PM PDT 24 221730280 ps
T227 /workspace/coverage/cover_reg_top/18.edn_csr_rw.836601664 Apr 25 12:57:17 PM PDT 24 Apr 25 12:57:20 PM PDT 24 16532010 ps
T928 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3824958225 Apr 25 12:56:59 PM PDT 24 Apr 25 12:57:02 PM PDT 24 23338734 ps
T929 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3735625789 Apr 25 12:57:04 PM PDT 24 Apr 25 12:57:12 PM PDT 24 127468201 ps
T930 /workspace/coverage/cover_reg_top/15.edn_tl_errors.222316955 Apr 25 12:57:03 PM PDT 24 Apr 25 12:57:10 PM PDT 24 47207814 ps
T931 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3892003812 Apr 25 12:56:56 PM PDT 24 Apr 25 12:56:59 PM PDT 24 17975158 ps
T932 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.4057719228 Apr 25 12:56:54 PM PDT 24 Apr 25 12:56:57 PM PDT 24 63851397 ps
T933 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.4228188114 Apr 25 12:57:00 PM PDT 24 Apr 25 12:57:07 PM PDT 24 191161310 ps
T934 /workspace/coverage/cover_reg_top/19.edn_tl_errors.248535891 Apr 25 12:57:08 PM PDT 24 Apr 25 12:57:15 PM PDT 24 85790087 ps
T228 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3080411027 Apr 25 12:57:12 PM PDT 24 Apr 25 12:57:16 PM PDT 24 30796486 ps
T935 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3657036658 Apr 25 12:57:47 PM PDT 24 Apr 25 12:57:51 PM PDT 24 70106623 ps
T936 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.388985316 Apr 25 12:57:09 PM PDT 24 Apr 25 12:57:15 PM PDT 24 30293115 ps
T937 /workspace/coverage/cover_reg_top/40.edn_intr_test.2553317497 Apr 25 12:56:58 PM PDT 24 Apr 25 12:57:02 PM PDT 24 42051431 ps
T938 /workspace/coverage/cover_reg_top/29.edn_intr_test.2174281661 Apr 25 12:57:11 PM PDT 24 Apr 25 12:57:15 PM PDT 24 39393860 ps
T939 /workspace/coverage/cover_reg_top/30.edn_intr_test.557654639 Apr 25 12:57:16 PM PDT 24 Apr 25 12:57:18 PM PDT 24 19731660 ps
T940 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4114612534 Apr 25 12:56:53 PM PDT 24 Apr 25 12:56:55 PM PDT 24 43893384 ps
T941 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3287741290 Apr 25 12:57:15 PM PDT 24 Apr 25 12:57:18 PM PDT 24 12837585 ps
T942 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3205192366 Apr 25 12:57:14 PM PDT 24 Apr 25 12:57:18 PM PDT 24 68845159 ps
T943 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.214384781 Apr 25 12:57:14 PM PDT 24 Apr 25 12:57:19 PM PDT 24 154698817 ps
T944 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1719140030 Apr 25 12:57:18 PM PDT 24 Apr 25 12:57:24 PM PDT 24 423068511 ps
T945 /workspace/coverage/cover_reg_top/1.edn_tl_errors.2573227496 Apr 25 12:57:34 PM PDT 24 Apr 25 12:57:37 PM PDT 24 30645851 ps
T946 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.287782692 Apr 25 12:56:58 PM PDT 24 Apr 25 12:57:02 PM PDT 24 227541725 ps
T947 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1180607833 Apr 25 12:57:28 PM PDT 24 Apr 25 12:57:30 PM PDT 24 34188715 ps
T948 /workspace/coverage/cover_reg_top/7.edn_intr_test.3879482816 Apr 25 12:57:02 PM PDT 24 Apr 25 12:57:08 PM PDT 24 13536507 ps
T949 /workspace/coverage/cover_reg_top/12.edn_intr_test.3549984072 Apr 25 12:57:03 PM PDT 24 Apr 25 12:57:09 PM PDT 24 21282106 ps
T950 /workspace/coverage/cover_reg_top/6.edn_intr_test.507747227 Apr 25 12:57:03 PM PDT 24 Apr 25 12:57:09 PM PDT 24 19134615 ps
T951 /workspace/coverage/cover_reg_top/10.edn_csr_rw.4191971681 Apr 25 12:57:18 PM PDT 24 Apr 25 12:57:20 PM PDT 24 33578864 ps
T952 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2393876925 Apr 25 12:56:58 PM PDT 24 Apr 25 12:57:04 PM PDT 24 311620992 ps
T953 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1502695090 Apr 25 12:57:37 PM PDT 24 Apr 25 12:57:40 PM PDT 24 29912393 ps
T954 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.113754355 Apr 25 12:57:29 PM PDT 24 Apr 25 12:57:37 PM PDT 24 261335650 ps
T955 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1533605677 Apr 25 12:56:59 PM PDT 24 Apr 25 12:57:04 PM PDT 24 21079429 ps
T956 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3461901815 Apr 25 12:57:17 PM PDT 24 Apr 25 12:57:20 PM PDT 24 45280798 ps
T229 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2049871711 Apr 25 12:57:23 PM PDT 24 Apr 25 12:57:25 PM PDT 24 26127973 ps
T957 /workspace/coverage/cover_reg_top/24.edn_intr_test.2780974424 Apr 25 12:57:31 PM PDT 24 Apr 25 12:57:33 PM PDT 24 45515055 ps
T958 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.11523091 Apr 25 12:57:13 PM PDT 24 Apr 25 12:57:17 PM PDT 24 71906665 ps
T959 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.88718124 Apr 25 12:56:59 PM PDT 24 Apr 25 12:57:03 PM PDT 24 18508607 ps
T960 /workspace/coverage/cover_reg_top/34.edn_intr_test.4247035585 Apr 25 12:57:31 PM PDT 24 Apr 25 12:57:32 PM PDT 24 15314831 ps
T961 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1723287584 Apr 25 12:57:03 PM PDT 24 Apr 25 12:57:11 PM PDT 24 179656610 ps
T962 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1902389059 Apr 25 12:57:05 PM PDT 24 Apr 25 12:57:15 PM PDT 24 1365856061 ps
T963 /workspace/coverage/cover_reg_top/21.edn_intr_test.3815070667 Apr 25 12:57:01 PM PDT 24 Apr 25 12:57:06 PM PDT 24 24515473 ps
T964 /workspace/coverage/cover_reg_top/36.edn_intr_test.3570364089 Apr 25 12:57:40 PM PDT 24 Apr 25 12:57:42 PM PDT 24 46211392 ps
T965 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1346989013 Apr 25 12:57:26 PM PDT 24 Apr 25 12:57:29 PM PDT 24 59138417 ps
T966 /workspace/coverage/cover_reg_top/23.edn_intr_test.2076624790 Apr 25 12:57:25 PM PDT 24 Apr 25 12:57:27 PM PDT 24 44534958 ps
T967 /workspace/coverage/cover_reg_top/6.edn_tl_errors.825767592 Apr 25 12:57:35 PM PDT 24 Apr 25 12:57:41 PM PDT 24 519544288 ps
T968 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.4049292563 Apr 25 12:57:03 PM PDT 24 Apr 25 12:57:09 PM PDT 24 109230787 ps
T969 /workspace/coverage/cover_reg_top/17.edn_intr_test.1382506295 Apr 25 12:57:02 PM PDT 24 Apr 25 12:57:08 PM PDT 24 16417162 ps
T970 /workspace/coverage/cover_reg_top/4.edn_intr_test.2333598426 Apr 25 12:56:57 PM PDT 24 Apr 25 12:57:00 PM PDT 24 190140003 ps
T971 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1245954604 Apr 25 12:57:00 PM PDT 24 Apr 25 12:57:07 PM PDT 24 73199837 ps
T972 /workspace/coverage/cover_reg_top/16.edn_csr_rw.620209523 Apr 25 12:57:13 PM PDT 24 Apr 25 12:57:17 PM PDT 24 16022801 ps
T973 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2608728727 Apr 25 12:56:54 PM PDT 24 Apr 25 12:56:56 PM PDT 24 21126069 ps
T974 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1670841596 Apr 25 12:56:58 PM PDT 24 Apr 25 12:57:01 PM PDT 24 24822985 ps
T975 /workspace/coverage/cover_reg_top/11.edn_intr_test.1743809363 Apr 25 12:57:18 PM PDT 24 Apr 25 12:57:20 PM PDT 24 17942040 ps
T231 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3528119886 Apr 25 12:56:57 PM PDT 24 Apr 25 12:57:00 PM PDT 24 32277754 ps

Test location /workspace/coverage/default/83.edn_genbits.2870658022
Short name T20
Test name
Test status
Simulation time 56936747 ps
CPU time 1.8 seconds
Started Apr 25 01:00:46 PM PDT 24
Finished Apr 25 01:00:51 PM PDT 24
Peak memory 218032 kb
Host smart-23971ff2-bab7-422b-b668-0d6fd90af876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870658022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2870658022
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.3975932520
Short name T17
Test name
Test status
Simulation time 85274877 ps
CPU time 3.15 seconds
Started Apr 25 01:00:53 PM PDT 24
Finished Apr 25 01:00:58 PM PDT 24
Peak memory 218420 kb
Host smart-b73968f7-ef1f-4585-8ea8-dbf4dd66a644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975932520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3975932520
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.4161030870
Short name T65
Test name
Test status
Simulation time 55092594 ps
CPU time 0.81 seconds
Started Apr 25 01:00:42 PM PDT 24
Finished Apr 25 01:00:47 PM PDT 24
Peak memory 218284 kb
Host smart-cd370add-0d00-46c0-8a57-11dd27a7a3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161030870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.4161030870
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1984031056
Short name T39
Test name
Test status
Simulation time 552751591470 ps
CPU time 2134.16 seconds
Started Apr 25 12:59:40 PM PDT 24
Finished Apr 25 01:35:17 PM PDT 24
Peak memory 227284 kb
Host smart-e461856d-40ec-496c-aec6-3915eaade9e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984031056 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1984031056
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2470553764
Short name T12
Test name
Test status
Simulation time 249944027 ps
CPU time 4.25 seconds
Started Apr 25 12:59:34 PM PDT 24
Finished Apr 25 12:59:39 PM PDT 24
Peak memory 235248 kb
Host smart-9dd0ba90-2aff-493a-91ce-ceec1c8f33f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470553764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2470553764
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/47.edn_alert.3464927712
Short name T46
Test name
Test status
Simulation time 72521140 ps
CPU time 1.1 seconds
Started Apr 25 01:00:29 PM PDT 24
Finished Apr 25 01:00:33 PM PDT 24
Peak memory 215600 kb
Host smart-9e9218ee-0f41-45ff-9b61-bdf519383598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464927712 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3464927712
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/31.edn_disable.3520736448
Short name T54
Test name
Test status
Simulation time 13873201 ps
CPU time 0.9 seconds
Started Apr 25 01:00:21 PM PDT 24
Finished Apr 25 01:00:23 PM PDT 24
Peak memory 216376 kb
Host smart-d3de27d5-37f4-4166-909b-f611174abd90
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520736448 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3520736448
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/175.edn_genbits.2528545481
Short name T11
Test name
Test status
Simulation time 36455202 ps
CPU time 1.54 seconds
Started Apr 25 01:00:36 PM PDT 24
Finished Apr 25 01:00:42 PM PDT 24
Peak memory 219700 kb
Host smart-1fb5d3c4-684b-40bb-aa96-36e468baab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528545481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2528545481
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_alert.309240997
Short name T29
Test name
Test status
Simulation time 38983524 ps
CPU time 1.2 seconds
Started Apr 25 01:00:28 PM PDT 24
Finished Apr 25 01:00:31 PM PDT 24
Peak memory 215548 kb
Host smart-07786f59-7ce9-4fee-bdff-d9d7bd1c88bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309240997 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.309240997
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1404636452
Short name T84
Test name
Test status
Simulation time 69948471 ps
CPU time 1.18 seconds
Started Apr 25 01:00:02 PM PDT 24
Finished Apr 25 01:00:06 PM PDT 24
Peak memory 216692 kb
Host smart-ec2baaf1-607e-4411-ad6a-9cf2395e4f8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404636452 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1404636452
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.451660976
Short name T177
Test name
Test status
Simulation time 21306876858 ps
CPU time 496.63 seconds
Started Apr 25 01:00:13 PM PDT 24
Finished Apr 25 01:08:33 PM PDT 24
Peak memory 217380 kb
Host smart-03accd1f-8a5d-442a-b412-4112a67a1c48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451660976 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.451660976
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_regwen.34043654
Short name T278
Test name
Test status
Simulation time 33135977 ps
CPU time 0.95 seconds
Started Apr 25 12:59:36 PM PDT 24
Finished Apr 25 12:59:39 PM PDT 24
Peak memory 206944 kb
Host smart-6e5219a1-161f-42d0-b4c4-084638ba8218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34043654 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.34043654
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1469073073
Short name T214
Test name
Test status
Simulation time 62091756 ps
CPU time 0.84 seconds
Started Apr 25 12:57:19 PM PDT 24
Finished Apr 25 12:57:21 PM PDT 24
Peak memory 206064 kb
Host smart-025e4aef-6cf9-4295-9c81-c6ff441dc668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469073073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1469073073
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/default/31.edn_alert.2965313420
Short name T152
Test name
Test status
Simulation time 28473475 ps
CPU time 1.3 seconds
Started Apr 25 01:00:11 PM PDT 24
Finished Apr 25 01:00:16 PM PDT 24
Peak memory 215424 kb
Host smart-3621b6b7-e4a2-4740-999c-ae15311828b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965313420 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2965313420
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3305415689
Short name T250
Test name
Test status
Simulation time 39971636 ps
CPU time 1.55 seconds
Started Apr 25 12:57:07 PM PDT 24
Finished Apr 25 12:57:13 PM PDT 24
Peak memory 206588 kb
Host smart-caca8bb0-a310-4983-82df-7db0e8ea3b75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305415689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3305415689
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/11.edn_alert.500415411
Short name T700
Test name
Test status
Simulation time 55071748 ps
CPU time 1.18 seconds
Started Apr 25 12:59:43 PM PDT 24
Finished Apr 25 12:59:47 PM PDT 24
Peak memory 215596 kb
Host smart-84a6c4dc-e39a-4abc-a0e5-d2df871cab71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500415411 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.500415411
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/0.edn_intr.934807780
Short name T33
Test name
Test status
Simulation time 43217446 ps
CPU time 0.88 seconds
Started Apr 25 12:59:25 PM PDT 24
Finished Apr 25 12:59:27 PM PDT 24
Peak memory 215432 kb
Host smart-365725b8-9958-4b62-9915-022e2cf69b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934807780 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.934807780
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/35.edn_disable.510280703
Short name T133
Test name
Test status
Simulation time 42749325 ps
CPU time 0.86 seconds
Started Apr 25 01:00:14 PM PDT 24
Finished Apr 25 01:00:18 PM PDT 24
Peak memory 216208 kb
Host smart-1bcaa2c0-2c95-4740-9452-6143cc8d3717
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510280703 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.510280703
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3035217189
Short name T87
Test name
Test status
Simulation time 27161366 ps
CPU time 1.07 seconds
Started Apr 25 01:00:26 PM PDT 24
Finished Apr 25 01:00:37 PM PDT 24
Peak memory 216564 kb
Host smart-fb4b7664-0a8e-4074-b07c-5abf369590b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035217189 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3035217189
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_disable.3792688456
Short name T75
Test name
Test status
Simulation time 27339767 ps
CPU time 0.81 seconds
Started Apr 25 01:00:09 PM PDT 24
Finished Apr 25 01:00:15 PM PDT 24
Peak memory 216012 kb
Host smart-29dfe58a-4732-493d-a752-32e63260ee9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792688456 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3792688456
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1660537940
Short name T162
Test name
Test status
Simulation time 27041889 ps
CPU time 1.22 seconds
Started Apr 25 01:00:22 PM PDT 24
Finished Apr 25 01:00:25 PM PDT 24
Peak memory 216704 kb
Host smart-a98359fa-7bad-4ae9-a3d7-7642a300aa55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660537940 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1660537940
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/220.edn_genbits.4020573188
Short name T69
Test name
Test status
Simulation time 39179772 ps
CPU time 1.33 seconds
Started Apr 25 01:00:59 PM PDT 24
Finished Apr 25 01:01:01 PM PDT 24
Peak memory 218084 kb
Host smart-2181469e-7d73-44fa-a46d-91b08ad6298e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020573188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.4020573188
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2396737699
Short name T289
Test name
Test status
Simulation time 110308798 ps
CPU time 1.06 seconds
Started Apr 25 12:59:57 PM PDT 24
Finished Apr 25 12:59:59 PM PDT 24
Peak memory 215484 kb
Host smart-53157657-9413-46ec-be89-5bbbf249c226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396737699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2396737699
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/3.edn_err.3691620889
Short name T50
Test name
Test status
Simulation time 44989225 ps
CPU time 0.99 seconds
Started Apr 25 12:59:51 PM PDT 24
Finished Apr 25 12:59:53 PM PDT 24
Peak memory 223908 kb
Host smart-c95d7fb2-3b70-4cf4-a0fe-555d11392a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691620889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3691620889
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/24.edn_intr.1311221182
Short name T37
Test name
Test status
Simulation time 57339192 ps
CPU time 0.83 seconds
Started Apr 25 01:00:04 PM PDT 24
Finished Apr 25 01:00:07 PM PDT 24
Peak memory 215392 kb
Host smart-fb35626a-2130-497d-a835-2e2af133620c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311221182 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1311221182
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/204.edn_genbits.906731025
Short name T255
Test name
Test status
Simulation time 106408239 ps
CPU time 1.23 seconds
Started Apr 25 01:01:05 PM PDT 24
Finished Apr 25 01:01:07 PM PDT 24
Peak memory 218348 kb
Host smart-20daeb6e-c2ee-46cf-ac50-1d9a7bad0389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906731025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.906731025
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_stress_all.3216820373
Short name T48
Test name
Test status
Simulation time 599356305 ps
CPU time 3.68 seconds
Started Apr 25 12:59:28 PM PDT 24
Finished Apr 25 12:59:33 PM PDT 24
Peak memory 215184 kb
Host smart-02cc7953-7713-41de-931e-5d69baefd952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216820373 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3216820373
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_disable.1839107575
Short name T751
Test name
Test status
Simulation time 17432229 ps
CPU time 0.81 seconds
Started Apr 25 12:59:54 PM PDT 24
Finished Apr 25 12:59:56 PM PDT 24
Peak memory 215188 kb
Host smart-c25b6d35-5381-4a25-bce0-6c5c4097b9fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839107575 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1839107575
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable.1699727569
Short name T45
Test name
Test status
Simulation time 92676361 ps
CPU time 0.84 seconds
Started Apr 25 01:00:24 PM PDT 24
Finished Apr 25 01:00:26 PM PDT 24
Peak memory 216172 kb
Host smart-eecb6d6f-cda0-4dc0-894b-68a2a79c5e11
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699727569 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1699727569
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable.154718789
Short name T56
Test name
Test status
Simulation time 10765389 ps
CPU time 0.87 seconds
Started Apr 25 12:59:12 PM PDT 24
Finished Apr 25 12:59:16 PM PDT 24
Peak memory 216064 kb
Host smart-f27df29e-f51e-4970-a6ff-e2ae5bc29417
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154718789 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.154718789
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3989016633
Short name T814
Test name
Test status
Simulation time 247163716 ps
CPU time 1.09 seconds
Started Apr 25 12:59:44 PM PDT 24
Finished Apr 25 12:59:48 PM PDT 24
Peak memory 218036 kb
Host smart-da4b1b27-0c91-4c5e-9a28-9f143453186c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989016633 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3989016633
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3668730575
Short name T105
Test name
Test status
Simulation time 74098855 ps
CPU time 1 seconds
Started Apr 25 01:00:00 PM PDT 24
Finished Apr 25 01:00:02 PM PDT 24
Peak memory 216568 kb
Host smart-a26babeb-37fc-4f3c-aa71-b246e11c3ab8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668730575 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3668730575
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.4205249574
Short name T578
Test name
Test status
Simulation time 40607040 ps
CPU time 1.28 seconds
Started Apr 25 12:59:40 PM PDT 24
Finished Apr 25 12:59:43 PM PDT 24
Peak memory 219160 kb
Host smart-41f263a0-f797-4392-bf81-ce5db9ade16b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205249574 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.4205249574
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1298843852
Short name T90
Test name
Test status
Simulation time 38547669 ps
CPU time 1.26 seconds
Started Apr 25 01:00:21 PM PDT 24
Finished Apr 25 01:00:23 PM PDT 24
Peak memory 217704 kb
Host smart-b469ddd0-5051-4a1c-8290-7c59278ecb0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298843852 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1298843852
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_disable.406562721
Short name T159
Test name
Test status
Simulation time 86462217 ps
CPU time 0.79 seconds
Started Apr 25 12:59:28 PM PDT 24
Finished Apr 25 12:59:30 PM PDT 24
Peak memory 216072 kb
Host smart-8fd10a54-9b53-4308-9e43-c1fd657186d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406562721 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.406562721
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/273.edn_genbits.3472528617
Short name T367
Test name
Test status
Simulation time 60458975 ps
CPU time 2.07 seconds
Started Apr 25 01:01:13 PM PDT 24
Finished Apr 25 01:01:17 PM PDT 24
Peak memory 218248 kb
Host smart-18aa6d74-fe90-41ca-b79c-be241ce26368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472528617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3472528617
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_alert_test.547511083
Short name T21
Test name
Test status
Simulation time 13619644 ps
CPU time 0.95 seconds
Started Apr 25 01:00:51 PM PDT 24
Finished Apr 25 01:00:54 PM PDT 24
Peak memory 206508 kb
Host smart-9564d9c7-704f-41c6-b97a-229ae2916c15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547511083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.547511083
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/144.edn_genbits.1706253183
Short name T9
Test name
Test status
Simulation time 297471665 ps
CPU time 1.29 seconds
Started Apr 25 01:00:41 PM PDT 24
Finished Apr 25 01:00:45 PM PDT 24
Peak memory 215180 kb
Host smart-5b93d5f5-e0b3-4381-9759-43f003e1449e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706253183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1706253183
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3594529011
Short name T290
Test name
Test status
Simulation time 79103980 ps
CPU time 1.23 seconds
Started Apr 25 12:59:57 PM PDT 24
Finished Apr 25 01:00:00 PM PDT 24
Peak memory 215496 kb
Host smart-0ccde563-c882-45a2-9ebc-639c9cfde616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594529011 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3594529011
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.499941823
Short name T262
Test name
Test status
Simulation time 48634862 ps
CPU time 1.13 seconds
Started Apr 25 01:01:19 PM PDT 24
Finished Apr 25 01:01:22 PM PDT 24
Peak memory 216784 kb
Host smart-3bdc56a7-d98a-477a-aafb-6ddec68c4078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499941823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.499941823
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2882789206
Short name T10
Test name
Test status
Simulation time 121457391 ps
CPU time 1.33 seconds
Started Apr 25 01:01:08 PM PDT 24
Finished Apr 25 01:01:11 PM PDT 24
Peak memory 218208 kb
Host smart-280a70ef-949f-4a8a-9295-43b687a2d727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882789206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2882789206
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.403210616
Short name T183
Test name
Test status
Simulation time 28021328 ps
CPU time 1.16 seconds
Started Apr 25 12:59:41 PM PDT 24
Finished Apr 25 12:59:44 PM PDT 24
Peak memory 215512 kb
Host smart-dc59ec87-642f-439b-a642-6d40b202d6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403210616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.403210616
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/71.edn_genbits.20157520
Short name T260
Test name
Test status
Simulation time 59541987 ps
CPU time 1.12 seconds
Started Apr 25 01:00:36 PM PDT 24
Finished Apr 25 01:00:41 PM PDT 24
Peak memory 219400 kb
Host smart-c92c12a3-0cf2-496c-9d0c-fed2ac608e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20157520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.20157520
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert.2239781123
Short name T118
Test name
Test status
Simulation time 50221533 ps
CPU time 1.15 seconds
Started Apr 25 12:59:29 PM PDT 24
Finished Apr 25 12:59:31 PM PDT 24
Peak memory 215464 kb
Host smart-905a4dc8-2344-4bad-a8d2-f6f560734aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239781123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2239781123
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert.1972112825
Short name T116
Test name
Test status
Simulation time 71500871 ps
CPU time 1.17 seconds
Started Apr 25 01:00:15 PM PDT 24
Finished Apr 25 01:00:19 PM PDT 24
Peak memory 215544 kb
Host smart-b6b1afc5-17f0-4b76-96dd-d9a10a31f7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972112825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1972112825
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.414407876
Short name T57
Test name
Test status
Simulation time 54401579 ps
CPU time 1.25 seconds
Started Apr 25 01:00:49 PM PDT 24
Finished Apr 25 01:00:52 PM PDT 24
Peak memory 216956 kb
Host smart-6b276ebf-d65e-4dda-b3df-67bc0ee5da92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414407876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.414407876
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/110.edn_genbits.1045270261
Short name T561
Test name
Test status
Simulation time 85138873 ps
CPU time 1.44 seconds
Started Apr 25 01:00:51 PM PDT 24
Finished Apr 25 01:00:55 PM PDT 24
Peak memory 218416 kb
Host smart-7860e892-64f3-4f79-a586-67bfa39d6df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045270261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1045270261
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2554026477
Short name T268
Test name
Test status
Simulation time 44424423 ps
CPU time 1.59 seconds
Started Apr 25 01:00:51 PM PDT 24
Finished Apr 25 01:00:55 PM PDT 24
Peak memory 218204 kb
Host smart-903ea09d-d814-495d-b3e7-4de1eda03fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554026477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2554026477
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.2404088064
Short name T267
Test name
Test status
Simulation time 151913184 ps
CPU time 1.81 seconds
Started Apr 25 01:00:57 PM PDT 24
Finished Apr 25 01:01:00 PM PDT 24
Peak memory 219580 kb
Host smart-296b1320-4efe-4157-a0dd-57b1ecb7cc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404088064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2404088064
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.813546420
Short name T43
Test name
Test status
Simulation time 63582741 ps
CPU time 1.7 seconds
Started Apr 25 01:01:04 PM PDT 24
Finished Apr 25 01:01:08 PM PDT 24
Peak memory 218120 kb
Host smart-3272b58c-a31d-4ffa-b823-d4bcec22149c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813546420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.813546420
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2872197055
Short name T263
Test name
Test status
Simulation time 154188230 ps
CPU time 1.43 seconds
Started Apr 25 01:01:18 PM PDT 24
Finished Apr 25 01:01:22 PM PDT 24
Peak memory 218600 kb
Host smart-269efa4f-f5bf-485b-9f90-d4e18d9bb6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872197055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2872197055
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.362509570
Short name T153
Test name
Test status
Simulation time 45987929 ps
CPU time 1.23 seconds
Started Apr 25 01:00:09 PM PDT 24
Finished Apr 25 01:00:16 PM PDT 24
Peak memory 215548 kb
Host smart-b9903060-c160-4864-acc7-890f055d63b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362509570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.362509570
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert.3591228295
Short name T245
Test name
Test status
Simulation time 24926896 ps
CPU time 1.16 seconds
Started Apr 25 01:00:22 PM PDT 24
Finished Apr 25 01:00:25 PM PDT 24
Peak memory 215540 kb
Host smart-738fb3a2-8cba-455b-b8f4-4cdd8d6f09fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591228295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3591228295
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert.1106941654
Short name T281
Test name
Test status
Simulation time 28020573 ps
CPU time 1.25 seconds
Started Apr 25 12:59:36 PM PDT 24
Finished Apr 25 12:59:39 PM PDT 24
Peak memory 215532 kb
Host smart-b7e12d1f-139b-47a6-a2ec-c2cf48085c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106941654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1106941654
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert.4025287554
Short name T279
Test name
Test status
Simulation time 264327493 ps
CPU time 1.3 seconds
Started Apr 25 12:59:25 PM PDT 24
Finished Apr 25 12:59:27 PM PDT 24
Peak memory 215516 kb
Host smart-aef76a55-da15-42ce-bb0b-4c72519b790f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025287554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.4025287554
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.2621722581
Short name T140
Test name
Test status
Simulation time 73729140 ps
CPU time 1.14 seconds
Started Apr 25 01:00:43 PM PDT 24
Finished Apr 25 01:00:48 PM PDT 24
Peak memory 215176 kb
Host smart-092a4090-14ae-47d9-b92b-2e8c080f7288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621722581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2621722581
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1536682162
Short name T38
Test name
Test status
Simulation time 25371909 ps
CPU time 0.94 seconds
Started Apr 25 12:59:43 PM PDT 24
Finished Apr 25 12:59:46 PM PDT 24
Peak memory 215688 kb
Host smart-be558d76-e6ab-40fc-88d2-f224a5f70b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536682162 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1536682162
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/15.edn_intr.3470969801
Short name T606
Test name
Test status
Simulation time 19891952 ps
CPU time 1.03 seconds
Started Apr 25 01:00:21 PM PDT 24
Finished Apr 25 01:00:23 PM PDT 24
Peak memory 215324 kb
Host smart-5b9f213a-b919-4db2-87b1-470c516fa77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470969801 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3470969801
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/12.edn_alert.1510752521
Short name T185
Test name
Test status
Simulation time 115190672 ps
CPU time 1.14 seconds
Started Apr 25 12:59:53 PM PDT 24
Finished Apr 25 12:59:55 PM PDT 24
Peak memory 215568 kb
Host smart-eb7a4313-e864-4443-b342-c6e64bdfc036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510752521 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1510752521
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/28.edn_err.3193094669
Short name T106
Test name
Test status
Simulation time 26668386 ps
CPU time 0.99 seconds
Started Apr 25 12:59:57 PM PDT 24
Finished Apr 25 12:59:59 PM PDT 24
Peak memory 219320 kb
Host smart-d50ed975-91e2-48f1-bd68-ad2d976ae5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193094669 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3193094669
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2869745320
Short name T235
Test name
Test status
Simulation time 24083266 ps
CPU time 1.21 seconds
Started Apr 25 12:57:02 PM PDT 24
Finished Apr 25 12:57:07 PM PDT 24
Peak memory 206312 kb
Host smart-c21e57b9-62b0-4777-af7c-32f02faf52e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869745320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2869745320
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1245954604
Short name T971
Test name
Test status
Simulation time 73199837 ps
CPU time 3.15 seconds
Started Apr 25 12:57:00 PM PDT 24
Finished Apr 25 12:57:07 PM PDT 24
Peak memory 206260 kb
Host smart-88338a7b-4c5f-4e76-ab5d-71dc3c36819f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245954604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1245954604
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3615687606
Short name T875
Test name
Test status
Simulation time 80899638 ps
CPU time 0.88 seconds
Started Apr 25 12:57:01 PM PDT 24
Finished Apr 25 12:57:06 PM PDT 24
Peak memory 206320 kb
Host smart-09a0f950-f4e4-4de5-86bc-716198a9a126
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615687606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3615687606
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.388985316
Short name T936
Test name
Test status
Simulation time 30293115 ps
CPU time 1.91 seconds
Started Apr 25 12:57:09 PM PDT 24
Finished Apr 25 12:57:15 PM PDT 24
Peak memory 219388 kb
Host smart-8d7fff69-c3ed-46f2-a12b-2fe714a784bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388985316 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.388985316
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2608728727
Short name T973
Test name
Test status
Simulation time 21126069 ps
CPU time 0.95 seconds
Started Apr 25 12:56:54 PM PDT 24
Finished Apr 25 12:56:56 PM PDT 24
Peak memory 206268 kb
Host smart-69adb36a-3351-4cf0-8108-755ec050cf95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608728727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2608728727
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3260563696
Short name T840
Test name
Test status
Simulation time 16435229 ps
CPU time 0.79 seconds
Started Apr 25 12:57:22 PM PDT 24
Finished Apr 25 12:57:23 PM PDT 24
Peak memory 206020 kb
Host smart-4d533abe-8c5b-4469-b73f-425f7ce64968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260563696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3260563696
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3892003812
Short name T931
Test name
Test status
Simulation time 17975158 ps
CPU time 1.16 seconds
Started Apr 25 12:56:56 PM PDT 24
Finished Apr 25 12:56:59 PM PDT 24
Peak memory 206280 kb
Host smart-41cb03e8-25f6-4452-ba5b-8c881d34038d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892003812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3892003812
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1902389059
Short name T962
Test name
Test status
Simulation time 1365856061 ps
CPU time 5.35 seconds
Started Apr 25 12:57:05 PM PDT 24
Finished Apr 25 12:57:15 PM PDT 24
Peak memory 214468 kb
Host smart-43a52e80-c236-497c-8c10-b7557c82237c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902389059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1902389059
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.4057719228
Short name T932
Test name
Test status
Simulation time 63851397 ps
CPU time 1.64 seconds
Started Apr 25 12:56:54 PM PDT 24
Finished Apr 25 12:56:57 PM PDT 24
Peak memory 206440 kb
Host smart-11a2964b-a457-423f-861a-f482b4168395
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057719228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.4057719228
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.113754355
Short name T954
Test name
Test status
Simulation time 261335650 ps
CPU time 6.16 seconds
Started Apr 25 12:57:29 PM PDT 24
Finished Apr 25 12:57:37 PM PDT 24
Peak memory 206344 kb
Host smart-a051e0eb-b3e4-4821-9a84-bc41f596311a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113754355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.113754355
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1533605677
Short name T955
Test name
Test status
Simulation time 21079429 ps
CPU time 1.02 seconds
Started Apr 25 12:56:59 PM PDT 24
Finished Apr 25 12:57:04 PM PDT 24
Peak memory 206340 kb
Host smart-5f1ec9bc-9afc-45f4-aaf0-963c2c855157
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533605677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1533605677
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4114612534
Short name T940
Test name
Test status
Simulation time 43893384 ps
CPU time 1.12 seconds
Started Apr 25 12:56:53 PM PDT 24
Finished Apr 25 12:56:55 PM PDT 24
Peak memory 214632 kb
Host smart-aee2f743-2b2c-49e2-a246-125a601e31b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114612534 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.4114612534
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3080411027
Short name T228
Test name
Test status
Simulation time 30796486 ps
CPU time 0.94 seconds
Started Apr 25 12:57:12 PM PDT 24
Finished Apr 25 12:57:16 PM PDT 24
Peak memory 206292 kb
Host smart-61ae568c-0222-41c1-9e03-b1f27490d358
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080411027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3080411027
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.134899513
Short name T863
Test name
Test status
Simulation time 14086259 ps
CPU time 0.86 seconds
Started Apr 25 12:56:53 PM PDT 24
Finished Apr 25 12:56:55 PM PDT 24
Peak memory 206124 kb
Host smart-5c1d393a-b9f3-4cda-b952-d63ba23754c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134899513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.134899513
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.406493446
Short name T876
Test name
Test status
Simulation time 59751207 ps
CPU time 1.4 seconds
Started Apr 25 12:56:58 PM PDT 24
Finished Apr 25 12:57:03 PM PDT 24
Peak memory 206348 kb
Host smart-b2fe7ca7-e174-453c-b7a2-927e47272a83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406493446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.406493446
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2573227496
Short name T945
Test name
Test status
Simulation time 30645851 ps
CPU time 2.03 seconds
Started Apr 25 12:57:34 PM PDT 24
Finished Apr 25 12:57:37 PM PDT 24
Peak memory 218392 kb
Host smart-976d9bd0-c3b5-43b8-b70f-7f04d685cafa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573227496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2573227496
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3987774799
Short name T853
Test name
Test status
Simulation time 138789078 ps
CPU time 1.45 seconds
Started Apr 25 12:57:12 PM PDT 24
Finished Apr 25 12:57:17 PM PDT 24
Peak memory 206396 kb
Host smart-5883e102-5bee-4c62-a8a6-7de5de971593
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987774799 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3987774799
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4124542036
Short name T897
Test name
Test status
Simulation time 60428360 ps
CPU time 1.12 seconds
Started Apr 25 12:57:20 PM PDT 24
Finished Apr 25 12:57:27 PM PDT 24
Peak memory 215884 kb
Host smart-a3c7d7fe-5bcb-4649-8a70-573cea4640e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124542036 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.4124542036
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.4191971681
Short name T951
Test name
Test status
Simulation time 33578864 ps
CPU time 0.8 seconds
Started Apr 25 12:57:18 PM PDT 24
Finished Apr 25 12:57:20 PM PDT 24
Peak memory 206152 kb
Host smart-94b8088d-cee8-4814-8c66-1c7e1fbac0ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191971681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.4191971681
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.642708513
Short name T870
Test name
Test status
Simulation time 42882586 ps
CPU time 0.88 seconds
Started Apr 25 12:56:58 PM PDT 24
Finished Apr 25 12:57:01 PM PDT 24
Peak memory 206324 kb
Host smart-ae9fe28d-ade2-4db1-a1bd-0d4af82548a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642708513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.642708513
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3287741290
Short name T941
Test name
Test status
Simulation time 12837585 ps
CPU time 0.92 seconds
Started Apr 25 12:57:15 PM PDT 24
Finished Apr 25 12:57:18 PM PDT 24
Peak memory 206304 kb
Host smart-4a16b03e-e112-4461-9fbe-fca1f3164fbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287741290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3287741290
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2628866993
Short name T860
Test name
Test status
Simulation time 166393334 ps
CPU time 4.46 seconds
Started Apr 25 12:57:08 PM PDT 24
Finished Apr 25 12:57:16 PM PDT 24
Peak memory 214528 kb
Host smart-46cd149d-6e4c-41d9-a6b9-ae7afcd3d49f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628866993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2628866993
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3729131437
Short name T914
Test name
Test status
Simulation time 187894398 ps
CPU time 2.15 seconds
Started Apr 25 12:57:08 PM PDT 24
Finished Apr 25 12:57:14 PM PDT 24
Peak memory 206332 kb
Host smart-c484d556-86d6-47ad-a08e-6fdc695ae14c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729131437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3729131437
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.88718124
Short name T959
Test name
Test status
Simulation time 18508607 ps
CPU time 1.16 seconds
Started Apr 25 12:56:59 PM PDT 24
Finished Apr 25 12:57:03 PM PDT 24
Peak memory 214624 kb
Host smart-19cb0859-8de2-46e8-ae44-f1bf765c3050
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88718124 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.88718124
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3834681816
Short name T218
Test name
Test status
Simulation time 82948626 ps
CPU time 0.83 seconds
Started Apr 25 12:57:08 PM PDT 24
Finished Apr 25 12:57:13 PM PDT 24
Peak memory 206336 kb
Host smart-09a30fc6-2b94-4a1d-bde4-0a5cba576cf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834681816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3834681816
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1743809363
Short name T975
Test name
Test status
Simulation time 17942040 ps
CPU time 0.8 seconds
Started Apr 25 12:57:18 PM PDT 24
Finished Apr 25 12:57:20 PM PDT 24
Peak memory 205888 kb
Host smart-f69150f8-c1a5-4893-8573-de0c45d12d36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743809363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1743809363
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3733566128
Short name T892
Test name
Test status
Simulation time 27086652 ps
CPU time 0.99 seconds
Started Apr 25 12:57:35 PM PDT 24
Finished Apr 25 12:57:37 PM PDT 24
Peak memory 206440 kb
Host smart-c0531c92-d88f-45d3-82fe-3d7ee9a461a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733566128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3733566128
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3686193039
Short name T894
Test name
Test status
Simulation time 46932785 ps
CPU time 1.76 seconds
Started Apr 25 12:57:02 PM PDT 24
Finished Apr 25 12:57:09 PM PDT 24
Peak memory 214612 kb
Host smart-5ed4549c-886d-453f-b59c-b62c5dc68ffb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686193039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3686193039
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2930986403
Short name T868
Test name
Test status
Simulation time 89466104 ps
CPU time 2.43 seconds
Started Apr 25 12:57:13 PM PDT 24
Finished Apr 25 12:57:18 PM PDT 24
Peak memory 206328 kb
Host smart-9724510d-8eb5-437a-9faf-10eb1521f815
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930986403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2930986403
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1502695090
Short name T953
Test name
Test status
Simulation time 29912393 ps
CPU time 1.12 seconds
Started Apr 25 12:57:37 PM PDT 24
Finished Apr 25 12:57:40 PM PDT 24
Peak memory 217292 kb
Host smart-f7943b7f-97af-4d09-b105-c97c641eef7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502695090 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1502695090
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2249804278
Short name T226
Test name
Test status
Simulation time 13520417 ps
CPU time 1 seconds
Started Apr 25 12:57:27 PM PDT 24
Finished Apr 25 12:57:29 PM PDT 24
Peak memory 206292 kb
Host smart-91b365e8-6dc6-455e-9549-51d66f63fc9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249804278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2249804278
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3549984072
Short name T949
Test name
Test status
Simulation time 21282106 ps
CPU time 0.87 seconds
Started Apr 25 12:57:03 PM PDT 24
Finished Apr 25 12:57:09 PM PDT 24
Peak memory 206188 kb
Host smart-c49e446f-3879-4d9e-b63d-eecfe201b3c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549984072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3549984072
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4116320403
Short name T924
Test name
Test status
Simulation time 74154905 ps
CPU time 1.06 seconds
Started Apr 25 12:57:28 PM PDT 24
Finished Apr 25 12:57:30 PM PDT 24
Peak memory 206164 kb
Host smart-296f4688-cb1b-4563-8b65-9bd942056a0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116320403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.4116320403
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.641191886
Short name T850
Test name
Test status
Simulation time 28154948 ps
CPU time 1.66 seconds
Started Apr 25 12:57:07 PM PDT 24
Finished Apr 25 12:57:13 PM PDT 24
Peak memory 214560 kb
Host smart-d6992f32-26bd-4132-a7c3-675468fdda07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641191886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.641191886
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1346989013
Short name T965
Test name
Test status
Simulation time 59138417 ps
CPU time 1.75 seconds
Started Apr 25 12:57:26 PM PDT 24
Finished Apr 25 12:57:29 PM PDT 24
Peak memory 206428 kb
Host smart-fd2c3ee0-73d2-4855-b3fb-9ad5f1bc6868
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346989013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1346989013
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.4049292563
Short name T968
Test name
Test status
Simulation time 109230787 ps
CPU time 0.93 seconds
Started Apr 25 12:57:03 PM PDT 24
Finished Apr 25 12:57:09 PM PDT 24
Peak memory 206404 kb
Host smart-22b6958a-5955-467f-95bd-e4b9ddac29a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049292563 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.4049292563
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.826344538
Short name T221
Test name
Test status
Simulation time 57114255 ps
CPU time 0.95 seconds
Started Apr 25 12:57:07 PM PDT 24
Finished Apr 25 12:57:12 PM PDT 24
Peak memory 206356 kb
Host smart-89719e3c-136c-4427-9600-2b5b256b4d40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826344538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.826344538
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1053902156
Short name T872
Test name
Test status
Simulation time 15560559 ps
CPU time 0.87 seconds
Started Apr 25 12:57:05 PM PDT 24
Finished Apr 25 12:57:11 PM PDT 24
Peak memory 206212 kb
Host smart-ba69a092-476d-46be-b26a-ebdf3a76bf67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053902156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1053902156
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.4054856073
Short name T234
Test name
Test status
Simulation time 21947860 ps
CPU time 0.92 seconds
Started Apr 25 12:57:06 PM PDT 24
Finished Apr 25 12:57:12 PM PDT 24
Peak memory 206364 kb
Host smart-40fb5912-9e32-4883-afda-06d5d610c01a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054856073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.4054856073
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.969217600
Short name T866
Test name
Test status
Simulation time 148798505 ps
CPU time 2.81 seconds
Started Apr 25 12:57:20 PM PDT 24
Finished Apr 25 12:57:24 PM PDT 24
Peak memory 222700 kb
Host smart-ed9e9416-d8fa-4584-bb85-015930500c10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969217600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.969217600
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.713166420
Short name T251
Test name
Test status
Simulation time 155228117 ps
CPU time 1.55 seconds
Started Apr 25 12:57:02 PM PDT 24
Finished Apr 25 12:57:09 PM PDT 24
Peak memory 206384 kb
Host smart-5f2a8e1c-b3f7-4809-b5fb-db51a415cf7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713166420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.713166420
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1592592803
Short name T912
Test name
Test status
Simulation time 85835973 ps
CPU time 1.23 seconds
Started Apr 25 12:57:32 PM PDT 24
Finished Apr 25 12:57:35 PM PDT 24
Peak memory 217292 kb
Host smart-f23bbe27-b763-40f0-a37a-e7893ef959b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592592803 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1592592803
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.402909049
Short name T885
Test name
Test status
Simulation time 21067111 ps
CPU time 0.78 seconds
Started Apr 25 12:57:01 PM PDT 24
Finished Apr 25 12:57:06 PM PDT 24
Peak memory 206036 kb
Host smart-e87c7b2c-6339-4e1f-bfbd-f5870059afae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402909049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.402909049
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.4061778938
Short name T907
Test name
Test status
Simulation time 12731574 ps
CPU time 0.94 seconds
Started Apr 25 12:57:42 PM PDT 24
Finished Apr 25 12:57:45 PM PDT 24
Peak memory 206316 kb
Host smart-7fc4b31e-ea8b-4bfd-a076-f098527c30b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061778938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.4061778938
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.889932721
Short name T893
Test name
Test status
Simulation time 238486041 ps
CPU time 1.65 seconds
Started Apr 25 12:57:12 PM PDT 24
Finished Apr 25 12:57:17 PM PDT 24
Peak memory 214612 kb
Host smart-405de789-d3fa-453b-a3a4-f4cf0b62c446
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889932721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.889932721
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3392680810
Short name T239
Test name
Test status
Simulation time 60589260 ps
CPU time 1.83 seconds
Started Apr 25 12:57:08 PM PDT 24
Finished Apr 25 12:57:14 PM PDT 24
Peak memory 206272 kb
Host smart-48787319-5218-4856-873a-d5deea2768b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392680810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3392680810
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.59178097
Short name T909
Test name
Test status
Simulation time 38925010 ps
CPU time 1.14 seconds
Started Apr 25 12:57:23 PM PDT 24
Finished Apr 25 12:57:25 PM PDT 24
Peak memory 214600 kb
Host smart-372dd81e-a8bf-46c2-ab90-982fb44ca29d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59178097 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.59178097
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2049871711
Short name T229
Test name
Test status
Simulation time 26127973 ps
CPU time 0.92 seconds
Started Apr 25 12:57:23 PM PDT 24
Finished Apr 25 12:57:25 PM PDT 24
Peak memory 206272 kb
Host smart-f728c366-af37-4ca3-8e64-ccc2f7f6b7bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049871711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2049871711
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3092579328
Short name T882
Test name
Test status
Simulation time 10687981 ps
CPU time 0.82 seconds
Started Apr 25 12:57:00 PM PDT 24
Finished Apr 25 12:57:05 PM PDT 24
Peak memory 206228 kb
Host smart-51001883-30a3-4b80-8c58-8caf63d3cfc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092579328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3092579328
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3967151326
Short name T869
Test name
Test status
Simulation time 162476048 ps
CPU time 1.11 seconds
Started Apr 25 12:57:02 PM PDT 24
Finished Apr 25 12:57:08 PM PDT 24
Peak memory 206340 kb
Host smart-728eb498-e63f-46ca-8f84-9257e2ed5397
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967151326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3967151326
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.222316955
Short name T930
Test name
Test status
Simulation time 47207814 ps
CPU time 1.98 seconds
Started Apr 25 12:57:03 PM PDT 24
Finished Apr 25 12:57:10 PM PDT 24
Peak memory 214440 kb
Host smart-ac3df8f9-df30-4359-8722-aa0890e5078b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222316955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.222316955
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4147222731
Short name T922
Test name
Test status
Simulation time 121071052 ps
CPU time 2.88 seconds
Started Apr 25 12:57:06 PM PDT 24
Finished Apr 25 12:57:14 PM PDT 24
Peak memory 206512 kb
Host smart-733d4969-fca5-4b65-be47-4d2415186cdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147222731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.4147222731
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1180607833
Short name T947
Test name
Test status
Simulation time 34188715 ps
CPU time 1.07 seconds
Started Apr 25 12:57:28 PM PDT 24
Finished Apr 25 12:57:30 PM PDT 24
Peak memory 215628 kb
Host smart-3569c58a-e6df-4019-9187-50225732785d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180607833 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1180607833
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.620209523
Short name T972
Test name
Test status
Simulation time 16022801 ps
CPU time 0.79 seconds
Started Apr 25 12:57:13 PM PDT 24
Finished Apr 25 12:57:17 PM PDT 24
Peak memory 205936 kb
Host smart-a536db97-6314-458a-aa57-dc1cced3888b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620209523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.620209523
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1225847805
Short name T900
Test name
Test status
Simulation time 29627280 ps
CPU time 0.83 seconds
Started Apr 25 12:56:59 PM PDT 24
Finished Apr 25 12:57:03 PM PDT 24
Peak memory 206196 kb
Host smart-30d4cefe-93a7-42ad-b2e7-af4af41bdf85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225847805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1225847805
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.341368670
Short name T915
Test name
Test status
Simulation time 51714901 ps
CPU time 1.02 seconds
Started Apr 25 12:57:09 PM PDT 24
Finished Apr 25 12:57:14 PM PDT 24
Peak memory 206324 kb
Host smart-ed6e631d-a3ac-48e7-a470-cc91ad1248d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341368670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_ou
tstanding.341368670
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3851569131
Short name T843
Test name
Test status
Simulation time 180558330 ps
CPU time 3.2 seconds
Started Apr 25 12:57:15 PM PDT 24
Finished Apr 25 12:57:20 PM PDT 24
Peak memory 214544 kb
Host smart-41ee6bd1-4218-4a20-9d7d-44103e0badd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851569131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3851569131
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.968799626
Short name T237
Test name
Test status
Simulation time 171971441 ps
CPU time 2.12 seconds
Started Apr 25 12:57:12 PM PDT 24
Finished Apr 25 12:57:18 PM PDT 24
Peak memory 206404 kb
Host smart-3b0006d8-e2da-4db5-b108-1a51c4d97eae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968799626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.968799626
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3172679460
Short name T927
Test name
Test status
Simulation time 21621772 ps
CPU time 1.4 seconds
Started Apr 25 12:57:01 PM PDT 24
Finished Apr 25 12:57:06 PM PDT 24
Peak memory 214480 kb
Host smart-f863b39c-ac0f-4bb4-b3dd-40695e5fb30f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172679460 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3172679460
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1561473326
Short name T910
Test name
Test status
Simulation time 13820552 ps
CPU time 0.9 seconds
Started Apr 25 12:57:14 PM PDT 24
Finished Apr 25 12:57:22 PM PDT 24
Peak memory 206352 kb
Host smart-bc5215cc-d310-4aae-b923-27b261d649a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561473326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1561473326
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1382506295
Short name T969
Test name
Test status
Simulation time 16417162 ps
CPU time 0.91 seconds
Started Apr 25 12:57:02 PM PDT 24
Finished Apr 25 12:57:08 PM PDT 24
Peak memory 206212 kb
Host smart-e9af0f07-f08c-427f-ba04-b49392f152dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382506295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1382506295
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1948638127
Short name T232
Test name
Test status
Simulation time 136358708 ps
CPU time 1.11 seconds
Started Apr 25 12:57:35 PM PDT 24
Finished Apr 25 12:57:37 PM PDT 24
Peak memory 206288 kb
Host smart-6eed689b-d54c-462f-8e23-43e4d28e956e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948638127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1948638127
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3660247960
Short name T879
Test name
Test status
Simulation time 207933650 ps
CPU time 1.64 seconds
Started Apr 25 12:57:02 PM PDT 24
Finished Apr 25 12:57:08 PM PDT 24
Peak memory 214492 kb
Host smart-0d242289-d5c0-444f-8e4c-e4e32e9ece8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660247960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3660247960
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3657036658
Short name T935
Test name
Test status
Simulation time 70106623 ps
CPU time 2.15 seconds
Started Apr 25 12:57:47 PM PDT 24
Finished Apr 25 12:57:51 PM PDT 24
Peak memory 206372 kb
Host smart-4630cecc-7a2a-4b8b-b247-cd31356b8f35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657036658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3657036658
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2455840979
Short name T889
Test name
Test status
Simulation time 28753433 ps
CPU time 1.32 seconds
Started Apr 25 12:57:36 PM PDT 24
Finished Apr 25 12:57:39 PM PDT 24
Peak memory 222624 kb
Host smart-2471203d-72f0-4a74-9557-d74637dca664
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455840979 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2455840979
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.836601664
Short name T227
Test name
Test status
Simulation time 16532010 ps
CPU time 0.98 seconds
Started Apr 25 12:57:17 PM PDT 24
Finished Apr 25 12:57:20 PM PDT 24
Peak memory 206352 kb
Host smart-3e71ac90-e00a-4df4-8643-9a8412cd529e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836601664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.836601664
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1061153915
Short name T881
Test name
Test status
Simulation time 75811801 ps
CPU time 0.86 seconds
Started Apr 25 12:57:19 PM PDT 24
Finished Apr 25 12:57:22 PM PDT 24
Peak memory 206136 kb
Host smart-669bfb00-7d79-4860-867b-3844f96ba3bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061153915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1061153915
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2711600620
Short name T233
Test name
Test status
Simulation time 35553986 ps
CPU time 1.35 seconds
Started Apr 25 12:57:19 PM PDT 24
Finished Apr 25 12:57:22 PM PDT 24
Peak memory 206312 kb
Host smart-650f2540-ed56-4a59-95ad-5c47361bac81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711600620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2711600620
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2646773922
Short name T899
Test name
Test status
Simulation time 36475962 ps
CPU time 2.55 seconds
Started Apr 25 12:57:29 PM PDT 24
Finished Apr 25 12:57:33 PM PDT 24
Peak memory 214488 kb
Host smart-ae527651-b90a-457b-a923-ba5487e4ef2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646773922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2646773922
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3549796682
Short name T238
Test name
Test status
Simulation time 362701882 ps
CPU time 1.44 seconds
Started Apr 25 12:57:09 PM PDT 24
Finished Apr 25 12:57:15 PM PDT 24
Peak memory 206356 kb
Host smart-adad1b0f-7e6f-43e7-9aea-579f50275c30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549796682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3549796682
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.11523091
Short name T958
Test name
Test status
Simulation time 71906665 ps
CPU time 1.12 seconds
Started Apr 25 12:57:13 PM PDT 24
Finished Apr 25 12:57:17 PM PDT 24
Peak memory 214508 kb
Host smart-5b69cd4d-0dce-4e6c-969d-533ee583bef4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11523091 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.11523091
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2493975348
Short name T224
Test name
Test status
Simulation time 12355692 ps
CPU time 0.88 seconds
Started Apr 25 12:57:02 PM PDT 24
Finished Apr 25 12:57:08 PM PDT 24
Peak memory 206292 kb
Host smart-eb653e5d-9cd6-405d-b0b6-44ea26f4e849
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493975348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2493975348
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2259653272
Short name T845
Test name
Test status
Simulation time 15595610 ps
CPU time 0.8 seconds
Started Apr 25 12:57:04 PM PDT 24
Finished Apr 25 12:57:09 PM PDT 24
Peak memory 206028 kb
Host smart-d2afe513-7406-49ff-9c82-0418db31ee21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259653272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2259653272
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3737917028
Short name T911
Test name
Test status
Simulation time 81157971 ps
CPU time 1.11 seconds
Started Apr 25 12:57:00 PM PDT 24
Finished Apr 25 12:57:05 PM PDT 24
Peak memory 206320 kb
Host smart-4a654173-0faa-41e7-b2a3-82c2f827cda5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737917028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3737917028
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.248535891
Short name T934
Test name
Test status
Simulation time 85790087 ps
CPU time 3 seconds
Started Apr 25 12:57:08 PM PDT 24
Finished Apr 25 12:57:15 PM PDT 24
Peak memory 214536 kb
Host smart-87ebdecf-a502-4863-abd4-e41076268815
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248535891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.248535891
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1284031533
Short name T921
Test name
Test status
Simulation time 133488485 ps
CPU time 2.2 seconds
Started Apr 25 12:57:34 PM PDT 24
Finished Apr 25 12:57:37 PM PDT 24
Peak memory 206272 kb
Host smart-fef9e0e9-8b23-419d-8f46-f102d449a819
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284031533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1284031533
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4232098644
Short name T225
Test name
Test status
Simulation time 58946580 ps
CPU time 1.48 seconds
Started Apr 25 12:57:30 PM PDT 24
Finished Apr 25 12:57:32 PM PDT 24
Peak memory 206376 kb
Host smart-0e05fa78-7da7-44c6-8d76-7610650a9cda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232098644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.4232098644
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1592845299
Short name T222
Test name
Test status
Simulation time 126154370 ps
CPU time 3.2 seconds
Started Apr 25 12:56:58 PM PDT 24
Finished Apr 25 12:57:04 PM PDT 24
Peak memory 206440 kb
Host smart-3ff9ab8e-38b3-404f-ad70-584e20d6c7f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592845299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1592845299
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1015503598
Short name T864
Test name
Test status
Simulation time 78477959 ps
CPU time 0.91 seconds
Started Apr 25 12:57:37 PM PDT 24
Finished Apr 25 12:57:40 PM PDT 24
Peak memory 206336 kb
Host smart-5cc730d5-ebc7-4ac0-bc26-f113bb4963df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015503598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1015503598
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1641237812
Short name T846
Test name
Test status
Simulation time 56169720 ps
CPU time 1.4 seconds
Started Apr 25 12:57:14 PM PDT 24
Finished Apr 25 12:57:18 PM PDT 24
Peak memory 217452 kb
Host smart-3582c0a8-5561-4267-818c-57b97bbc2359
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641237812 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1641237812
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1140302881
Short name T215
Test name
Test status
Simulation time 26816984 ps
CPU time 0.85 seconds
Started Apr 25 12:57:01 PM PDT 24
Finished Apr 25 12:57:06 PM PDT 24
Peak memory 206064 kb
Host smart-3c716c0c-370c-421a-affb-8ab91df7f4ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140302881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1140302881
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3841902056
Short name T918
Test name
Test status
Simulation time 12297835 ps
CPU time 0.89 seconds
Started Apr 25 12:56:59 PM PDT 24
Finished Apr 25 12:57:03 PM PDT 24
Peak memory 206140 kb
Host smart-497686d7-db35-4e9e-bc78-6f81a8b618a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841902056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3841902056
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2947043638
Short name T878
Test name
Test status
Simulation time 48269287 ps
CPU time 0.95 seconds
Started Apr 25 12:57:29 PM PDT 24
Finished Apr 25 12:57:32 PM PDT 24
Peak memory 206320 kb
Host smart-23ab475f-e2c2-47c4-9b20-d4ea42ed9fb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947043638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2947043638
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3735625789
Short name T929
Test name
Test status
Simulation time 127468201 ps
CPU time 2.41 seconds
Started Apr 25 12:57:04 PM PDT 24
Finished Apr 25 12:57:12 PM PDT 24
Peak memory 214552 kb
Host smart-4b372b13-dff5-41fe-a700-589df4a421f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735625789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3735625789
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1480086898
Short name T919
Test name
Test status
Simulation time 250321132 ps
CPU time 1.57 seconds
Started Apr 25 12:57:30 PM PDT 24
Finished Apr 25 12:57:33 PM PDT 24
Peak memory 206324 kb
Host smart-22e83cd1-47ce-49b5-825e-1fb2bbb92c84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480086898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1480086898
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2018440083
Short name T851
Test name
Test status
Simulation time 28060886 ps
CPU time 0.93 seconds
Started Apr 25 12:57:11 PM PDT 24
Finished Apr 25 12:57:19 PM PDT 24
Peak memory 206228 kb
Host smart-34e61b3f-b74e-4f9e-af34-5546fe4a77de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018440083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2018440083
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3815070667
Short name T963
Test name
Test status
Simulation time 24515473 ps
CPU time 0.86 seconds
Started Apr 25 12:57:01 PM PDT 24
Finished Apr 25 12:57:06 PM PDT 24
Peak memory 206076 kb
Host smart-b4863b86-a505-4246-a12e-7bae803a8f48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815070667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3815070667
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1770068263
Short name T884
Test name
Test status
Simulation time 24439388 ps
CPU time 0.84 seconds
Started Apr 25 12:57:02 PM PDT 24
Finished Apr 25 12:57:08 PM PDT 24
Peak memory 206196 kb
Host smart-fbce3934-8e3e-4e7d-9a61-5cf5bbafe78c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770068263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1770068263
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2076624790
Short name T966
Test name
Test status
Simulation time 44534958 ps
CPU time 0.78 seconds
Started Apr 25 12:57:25 PM PDT 24
Finished Apr 25 12:57:27 PM PDT 24
Peak memory 206008 kb
Host smart-1181aab7-b88c-4839-b73b-af24580db221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076624790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2076624790
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2780974424
Short name T957
Test name
Test status
Simulation time 45515055 ps
CPU time 0.8 seconds
Started Apr 25 12:57:31 PM PDT 24
Finished Apr 25 12:57:33 PM PDT 24
Peak memory 205984 kb
Host smart-9163d668-93be-4359-a572-0eb4bb240626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780974424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2780974424
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.972556579
Short name T880
Test name
Test status
Simulation time 42589064 ps
CPU time 0.82 seconds
Started Apr 25 12:57:03 PM PDT 24
Finished Apr 25 12:57:09 PM PDT 24
Peak memory 206012 kb
Host smart-85e5bce9-9225-43cf-8ba7-3245f53784a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972556579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.972556579
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2537122268
Short name T844
Test name
Test status
Simulation time 12782552 ps
CPU time 0.89 seconds
Started Apr 25 12:57:19 PM PDT 24
Finished Apr 25 12:57:21 PM PDT 24
Peak memory 206240 kb
Host smart-c9b8511f-1520-41f9-819a-879e785c4527
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537122268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2537122268
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1594713208
Short name T888
Test name
Test status
Simulation time 71126912 ps
CPU time 0.86 seconds
Started Apr 25 12:57:42 PM PDT 24
Finished Apr 25 12:57:45 PM PDT 24
Peak memory 206212 kb
Host smart-ebd032b4-330d-46f8-878b-956893f602a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594713208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1594713208
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1253391008
Short name T852
Test name
Test status
Simulation time 40738458 ps
CPU time 0.78 seconds
Started Apr 25 12:57:24 PM PDT 24
Finished Apr 25 12:57:26 PM PDT 24
Peak memory 205936 kb
Host smart-f7aab660-f3e4-444d-8608-c68240083367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253391008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1253391008
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2174281661
Short name T938
Test name
Test status
Simulation time 39393860 ps
CPU time 0.81 seconds
Started Apr 25 12:57:11 PM PDT 24
Finished Apr 25 12:57:15 PM PDT 24
Peak memory 205940 kb
Host smart-d74ba3f9-f438-4da8-bcd7-2ae8d459b289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174281661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2174281661
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.463467302
Short name T223
Test name
Test status
Simulation time 22299798 ps
CPU time 1.13 seconds
Started Apr 25 12:56:59 PM PDT 24
Finished Apr 25 12:57:03 PM PDT 24
Peak memory 206388 kb
Host smart-f87ab78b-d1c5-409a-a22c-e99f148ed707
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463467302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.463467302
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.737354466
Short name T230
Test name
Test status
Simulation time 221730280 ps
CPU time 5.66 seconds
Started Apr 25 12:57:06 PM PDT 24
Finished Apr 25 12:57:17 PM PDT 24
Peak memory 206312 kb
Host smart-3c2711a6-fffb-4fd8-8936-28cf389e2ce4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737354466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.737354466
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1788927459
Short name T917
Test name
Test status
Simulation time 107792572 ps
CPU time 0.81 seconds
Started Apr 25 12:57:03 PM PDT 24
Finished Apr 25 12:57:09 PM PDT 24
Peak memory 206140 kb
Host smart-1a70cf8d-60bf-4151-a7a8-018172e94f19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788927459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1788927459
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2681380127
Short name T906
Test name
Test status
Simulation time 48979106 ps
CPU time 1.63 seconds
Started Apr 25 12:57:03 PM PDT 24
Finished Apr 25 12:57:09 PM PDT 24
Peak memory 214564 kb
Host smart-d586c973-1373-44e4-a4c0-0d011bc42cf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681380127 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2681380127
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1670841596
Short name T974
Test name
Test status
Simulation time 24822985 ps
CPU time 0.95 seconds
Started Apr 25 12:56:58 PM PDT 24
Finished Apr 25 12:57:01 PM PDT 24
Peak memory 206352 kb
Host smart-7a33d788-b80c-4efc-bbe9-36397ba379dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670841596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1670841596
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.4139385768
Short name T842
Test name
Test status
Simulation time 15957116 ps
CPU time 0.89 seconds
Started Apr 25 12:57:19 PM PDT 24
Finished Apr 25 12:57:21 PM PDT 24
Peak memory 206288 kb
Host smart-2a78af74-6f3b-43e5-b0eb-bf97c4a77dea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139385768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.4139385768
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.662786968
Short name T219
Test name
Test status
Simulation time 21895559 ps
CPU time 1.06 seconds
Started Apr 25 12:57:07 PM PDT 24
Finished Apr 25 12:57:17 PM PDT 24
Peak memory 206312 kb
Host smart-5aadf8d7-52bc-4a71-a1c3-c7f08d22753f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662786968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.662786968
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2615039454
Short name T877
Test name
Test status
Simulation time 66416359 ps
CPU time 2.4 seconds
Started Apr 25 12:57:02 PM PDT 24
Finished Apr 25 12:57:09 PM PDT 24
Peak memory 214464 kb
Host smart-c4014d06-54ae-4ea0-9caf-e03668aea657
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615039454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2615039454
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1948714226
Short name T895
Test name
Test status
Simulation time 293050235 ps
CPU time 2.25 seconds
Started Apr 25 12:57:10 PM PDT 24
Finished Apr 25 12:57:16 PM PDT 24
Peak memory 214544 kb
Host smart-6cd05592-679f-427d-9adb-a939bb500934
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948714226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1948714226
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.557654639
Short name T939
Test name
Test status
Simulation time 19731660 ps
CPU time 0.83 seconds
Started Apr 25 12:57:16 PM PDT 24
Finished Apr 25 12:57:18 PM PDT 24
Peak memory 206232 kb
Host smart-a0049ec2-3ff7-4139-93f9-3cfc2e84646b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557654639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.557654639
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2981228952
Short name T871
Test name
Test status
Simulation time 11886615 ps
CPU time 0.83 seconds
Started Apr 25 12:57:38 PM PDT 24
Finished Apr 25 12:57:41 PM PDT 24
Peak memory 206212 kb
Host smart-fc2a414d-e254-44e9-94dd-43787346d2ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981228952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2981228952
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2618333499
Short name T855
Test name
Test status
Simulation time 16138823 ps
CPU time 0.8 seconds
Started Apr 25 12:56:58 PM PDT 24
Finished Apr 25 12:57:01 PM PDT 24
Peak memory 205996 kb
Host smart-47acd903-d8d1-4831-8dab-146183b55901
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618333499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2618333499
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.163411007
Short name T898
Test name
Test status
Simulation time 29623604 ps
CPU time 0.86 seconds
Started Apr 25 12:57:11 PM PDT 24
Finished Apr 25 12:57:15 PM PDT 24
Peak memory 206088 kb
Host smart-0694cbc3-adbc-4d24-b87e-4587bc2aa274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163411007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.163411007
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.4247035585
Short name T960
Test name
Test status
Simulation time 15314831 ps
CPU time 0.89 seconds
Started Apr 25 12:57:31 PM PDT 24
Finished Apr 25 12:57:32 PM PDT 24
Peak memory 206124 kb
Host smart-cff2e897-2029-4174-a4cd-4479cfada2d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247035585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.4247035585
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1965384729
Short name T867
Test name
Test status
Simulation time 20857849 ps
CPU time 0.85 seconds
Started Apr 25 12:57:25 PM PDT 24
Finished Apr 25 12:57:27 PM PDT 24
Peak memory 206204 kb
Host smart-2d94a275-bafb-4344-86ab-163494c034d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965384729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1965384729
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3570364089
Short name T964
Test name
Test status
Simulation time 46211392 ps
CPU time 0.91 seconds
Started Apr 25 12:57:40 PM PDT 24
Finished Apr 25 12:57:42 PM PDT 24
Peak memory 206228 kb
Host smart-02cd237d-bb4c-4a9e-ae38-11f198355851
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570364089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3570364089
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3140972226
Short name T854
Test name
Test status
Simulation time 104542355 ps
CPU time 0.8 seconds
Started Apr 25 12:57:24 PM PDT 24
Finished Apr 25 12:57:26 PM PDT 24
Peak memory 205948 kb
Host smart-34cbe402-1bab-42b6-a908-c760846f779e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140972226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3140972226
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2626568762
Short name T847
Test name
Test status
Simulation time 30109008 ps
CPU time 0.83 seconds
Started Apr 25 12:57:39 PM PDT 24
Finished Apr 25 12:57:42 PM PDT 24
Peak memory 206216 kb
Host smart-512cb069-ada7-41dd-9b5d-143392158787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626568762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2626568762
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2859129636
Short name T890
Test name
Test status
Simulation time 42723160 ps
CPU time 0.79 seconds
Started Apr 25 12:57:34 PM PDT 24
Finished Apr 25 12:57:36 PM PDT 24
Peak memory 206024 kb
Host smart-a9b42bdc-c8c5-4571-9c15-54ce7083acf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859129636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2859129636
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3528119886
Short name T231
Test name
Test status
Simulation time 32277754 ps
CPU time 1.23 seconds
Started Apr 25 12:56:57 PM PDT 24
Finished Apr 25 12:57:00 PM PDT 24
Peak memory 206164 kb
Host smart-19a9e43c-c704-460f-a71e-752b246766a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528119886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3528119886
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.260202960
Short name T886
Test name
Test status
Simulation time 91602993 ps
CPU time 3.24 seconds
Started Apr 25 12:57:09 PM PDT 24
Finished Apr 25 12:57:16 PM PDT 24
Peak memory 206300 kb
Host smart-cf936073-0f8a-4480-a150-f84bdd74de05
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260202960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.260202960
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.4067491789
Short name T236
Test name
Test status
Simulation time 63658190 ps
CPU time 0.98 seconds
Started Apr 25 12:57:04 PM PDT 24
Finished Apr 25 12:57:10 PM PDT 24
Peak memory 206316 kb
Host smart-c695fad5-2fe2-4aeb-ac0b-d47923468ad3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067491789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.4067491789
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.367648047
Short name T891
Test name
Test status
Simulation time 37984447 ps
CPU time 1.3 seconds
Started Apr 25 12:56:58 PM PDT 24
Finished Apr 25 12:57:02 PM PDT 24
Peak memory 214504 kb
Host smart-0dfcc42e-4843-4197-a5a4-d5c997b86b0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367648047 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.367648047
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2259457988
Short name T925
Test name
Test status
Simulation time 41456004 ps
CPU time 0.79 seconds
Started Apr 25 12:57:13 PM PDT 24
Finished Apr 25 12:57:17 PM PDT 24
Peak memory 206236 kb
Host smart-8994a1fb-7995-4239-b8b6-4905e7db2f8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259457988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2259457988
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2333598426
Short name T970
Test name
Test status
Simulation time 190140003 ps
CPU time 0.9 seconds
Started Apr 25 12:56:57 PM PDT 24
Finished Apr 25 12:57:00 PM PDT 24
Peak memory 205900 kb
Host smart-bdf77cba-219e-4f78-95d4-528a105e3149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333598426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2333598426
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.490829239
Short name T916
Test name
Test status
Simulation time 24482472 ps
CPU time 1.16 seconds
Started Apr 25 12:57:03 PM PDT 24
Finished Apr 25 12:57:09 PM PDT 24
Peak memory 206328 kb
Host smart-2930d7ba-5a5e-4899-8551-915b7c631255
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490829239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.490829239
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1719140030
Short name T944
Test name
Test status
Simulation time 423068511 ps
CPU time 5.2 seconds
Started Apr 25 12:57:18 PM PDT 24
Finished Apr 25 12:57:24 PM PDT 24
Peak memory 214308 kb
Host smart-1308d6a1-e2b3-433b-badd-86dd85a9a6f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719140030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1719140030
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.214384781
Short name T943
Test name
Test status
Simulation time 154698817 ps
CPU time 2.13 seconds
Started Apr 25 12:57:14 PM PDT 24
Finished Apr 25 12:57:19 PM PDT 24
Peak memory 206312 kb
Host smart-fbc2919a-09c5-438b-aa3f-bad3cfe49cea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214384781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.214384781
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2553317497
Short name T937
Test name
Test status
Simulation time 42051431 ps
CPU time 0.84 seconds
Started Apr 25 12:56:58 PM PDT 24
Finished Apr 25 12:57:02 PM PDT 24
Peak memory 206124 kb
Host smart-f700622b-c655-4d32-8e3e-6c070efd20b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553317497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2553317497
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2792639353
Short name T849
Test name
Test status
Simulation time 15015020 ps
CPU time 0.91 seconds
Started Apr 25 12:57:14 PM PDT 24
Finished Apr 25 12:57:18 PM PDT 24
Peak memory 206228 kb
Host smart-538ad7a6-510e-4ed3-b097-934e5925b598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792639353 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2792639353
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3501262885
Short name T858
Test name
Test status
Simulation time 14869371 ps
CPU time 0.9 seconds
Started Apr 25 12:57:33 PM PDT 24
Finished Apr 25 12:57:35 PM PDT 24
Peak memory 206216 kb
Host smart-2ec4c942-eecf-41e0-b1b3-4d41fb8a6348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501262885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3501262885
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1000081518
Short name T920
Test name
Test status
Simulation time 11358985 ps
CPU time 0.85 seconds
Started Apr 25 12:57:29 PM PDT 24
Finished Apr 25 12:57:36 PM PDT 24
Peak memory 206232 kb
Host smart-9c047863-22d9-408e-968f-187b3f99ccb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000081518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1000081518
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3701459787
Short name T926
Test name
Test status
Simulation time 17201319 ps
CPU time 0.83 seconds
Started Apr 25 12:57:20 PM PDT 24
Finished Apr 25 12:57:22 PM PDT 24
Peak memory 206228 kb
Host smart-6c4dc01e-022e-4890-8963-3e1caa5adcae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701459787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3701459787
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1338882493
Short name T848
Test name
Test status
Simulation time 45279048 ps
CPU time 0.93 seconds
Started Apr 25 12:57:21 PM PDT 24
Finished Apr 25 12:57:23 PM PDT 24
Peak memory 206228 kb
Host smart-5a3b4c5d-9b8b-4e6c-a823-8c5e1707427f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338882493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1338882493
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2214454599
Short name T913
Test name
Test status
Simulation time 22692449 ps
CPU time 0.84 seconds
Started Apr 25 12:57:24 PM PDT 24
Finished Apr 25 12:57:26 PM PDT 24
Peak memory 206124 kb
Host smart-9de2f3e8-4099-4ea4-aec9-14802661a0fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214454599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2214454599
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2120311888
Short name T873
Test name
Test status
Simulation time 16476667 ps
CPU time 0.86 seconds
Started Apr 25 12:57:21 PM PDT 24
Finished Apr 25 12:57:23 PM PDT 24
Peak memory 206228 kb
Host smart-ae2ab7e4-3b07-406d-a290-a0d8074d8533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120311888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2120311888
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.564221853
Short name T862
Test name
Test status
Simulation time 18822243 ps
CPU time 0.82 seconds
Started Apr 25 12:57:16 PM PDT 24
Finished Apr 25 12:57:19 PM PDT 24
Peak memory 206016 kb
Host smart-1b29b4d6-1c9e-462b-b7e0-e296f026e7a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564221853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.564221853
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2148719537
Short name T865
Test name
Test status
Simulation time 23276750 ps
CPU time 0.93 seconds
Started Apr 25 12:57:25 PM PDT 24
Finished Apr 25 12:57:27 PM PDT 24
Peak memory 206192 kb
Host smart-6d9e138f-b260-4df1-bd25-3a1b85894fa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148719537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2148719537
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2328828953
Short name T857
Test name
Test status
Simulation time 79078004 ps
CPU time 1.47 seconds
Started Apr 25 12:57:38 PM PDT 24
Finished Apr 25 12:57:41 PM PDT 24
Peak memory 214668 kb
Host smart-47b375c4-c121-4da3-a58f-f59081e945ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328828953 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2328828953
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1592612781
Short name T216
Test name
Test status
Simulation time 14046023 ps
CPU time 0.88 seconds
Started Apr 25 12:57:07 PM PDT 24
Finished Apr 25 12:57:12 PM PDT 24
Peak memory 206320 kb
Host smart-91452ae4-b908-4d8d-b607-8a726407721b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592612781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1592612781
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.872910986
Short name T883
Test name
Test status
Simulation time 42042035 ps
CPU time 0.87 seconds
Started Apr 25 12:57:18 PM PDT 24
Finished Apr 25 12:57:20 PM PDT 24
Peak memory 205936 kb
Host smart-6855f134-c4be-4b52-b8a7-e9d5107bcc8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872910986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.872910986
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3703842875
Short name T217
Test name
Test status
Simulation time 27785127 ps
CPU time 1.28 seconds
Started Apr 25 12:57:01 PM PDT 24
Finished Apr 25 12:57:07 PM PDT 24
Peak memory 206276 kb
Host smart-5e24f765-4b02-4a24-83c6-42059463b100
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703842875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3703842875
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2393876925
Short name T952
Test name
Test status
Simulation time 311620992 ps
CPU time 2.58 seconds
Started Apr 25 12:56:58 PM PDT 24
Finished Apr 25 12:57:04 PM PDT 24
Peak memory 218516 kb
Host smart-39cadbcd-9b72-413f-88f2-9e9d84dba859
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393876925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2393876925
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.287782692
Short name T946
Test name
Test status
Simulation time 227541725 ps
CPU time 1.42 seconds
Started Apr 25 12:56:58 PM PDT 24
Finished Apr 25 12:57:02 PM PDT 24
Peak memory 206344 kb
Host smart-d8382c3b-1e71-4cf4-be24-31b1762a5c9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287782692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.287782692
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.4186638379
Short name T896
Test name
Test status
Simulation time 23927605 ps
CPU time 1.53 seconds
Started Apr 25 12:57:04 PM PDT 24
Finished Apr 25 12:57:11 PM PDT 24
Peak memory 214628 kb
Host smart-46d715e3-0682-4fff-9366-bcf80ea96bf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186638379 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.4186638379
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3461901815
Short name T956
Test name
Test status
Simulation time 45280798 ps
CPU time 0.86 seconds
Started Apr 25 12:57:17 PM PDT 24
Finished Apr 25 12:57:20 PM PDT 24
Peak memory 206236 kb
Host smart-28208994-81aa-4965-805e-3f53ae8e9e58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461901815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3461901815
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.507747227
Short name T950
Test name
Test status
Simulation time 19134615 ps
CPU time 0.81 seconds
Started Apr 25 12:57:03 PM PDT 24
Finished Apr 25 12:57:09 PM PDT 24
Peak memory 205996 kb
Host smart-af920052-5905-400a-afc7-61dd448ebf1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507747227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.507747227
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1517708829
Short name T903
Test name
Test status
Simulation time 66121594 ps
CPU time 1.07 seconds
Started Apr 25 12:57:01 PM PDT 24
Finished Apr 25 12:57:07 PM PDT 24
Peak memory 206364 kb
Host smart-74b7e6d9-da69-4079-8ded-046c2c3b5db0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517708829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1517708829
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.825767592
Short name T967
Test name
Test status
Simulation time 519544288 ps
CPU time 4.76 seconds
Started Apr 25 12:57:35 PM PDT 24
Finished Apr 25 12:57:41 PM PDT 24
Peak memory 214560 kb
Host smart-248aea47-7470-4abb-8deb-bf0c553a0036
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825767592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.825767592
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1723287584
Short name T961
Test name
Test status
Simulation time 179656610 ps
CPU time 2.17 seconds
Started Apr 25 12:57:03 PM PDT 24
Finished Apr 25 12:57:11 PM PDT 24
Peak memory 206668 kb
Host smart-c58181c1-5279-4be0-8bec-ba6f0599a7c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723287584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1723287584
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3985792325
Short name T923
Test name
Test status
Simulation time 12656835 ps
CPU time 0.95 seconds
Started Apr 25 12:57:07 PM PDT 24
Finished Apr 25 12:57:13 PM PDT 24
Peak memory 206320 kb
Host smart-8f7fd85a-2031-49e4-aec7-8ff13bbb3353
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985792325 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3985792325
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.946872715
Short name T908
Test name
Test status
Simulation time 39630506 ps
CPU time 0.83 seconds
Started Apr 25 12:57:26 PM PDT 24
Finished Apr 25 12:57:29 PM PDT 24
Peak memory 206008 kb
Host smart-e9ae16c4-730c-4cc3-9428-85fe74c017b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946872715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.946872715
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3879482816
Short name T948
Test name
Test status
Simulation time 13536507 ps
CPU time 0.84 seconds
Started Apr 25 12:57:02 PM PDT 24
Finished Apr 25 12:57:08 PM PDT 24
Peak memory 206172 kb
Host smart-e81ad840-c40b-48f2-8890-ef849fcf5926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879482816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3879482816
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2257231174
Short name T904
Test name
Test status
Simulation time 36164285 ps
CPU time 1.38 seconds
Started Apr 25 12:56:59 PM PDT 24
Finished Apr 25 12:57:03 PM PDT 24
Peak memory 206312 kb
Host smart-f38f5dfb-67e2-4cc8-b62c-11d93601cafa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257231174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2257231174
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2438358560
Short name T861
Test name
Test status
Simulation time 589373410 ps
CPU time 3.66 seconds
Started Apr 25 12:57:03 PM PDT 24
Finished Apr 25 12:57:12 PM PDT 24
Peak memory 214524 kb
Host smart-b4daf218-4487-4990-81b9-1b44f80c7368
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438358560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2438358560
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2671035861
Short name T887
Test name
Test status
Simulation time 171418572 ps
CPU time 1.45 seconds
Started Apr 25 12:56:59 PM PDT 24
Finished Apr 25 12:57:03 PM PDT 24
Peak memory 214540 kb
Host smart-ab36ca7f-9d2c-4611-b1f1-324a2011c0d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671035861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2671035861
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1134751773
Short name T859
Test name
Test status
Simulation time 37998472 ps
CPU time 1.71 seconds
Started Apr 25 12:56:56 PM PDT 24
Finished Apr 25 12:57:00 PM PDT 24
Peak memory 214624 kb
Host smart-2203b5ed-deda-4f5a-bbf4-517754fbb25d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134751773 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1134751773
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3824958225
Short name T928
Test name
Test status
Simulation time 23338734 ps
CPU time 0.84 seconds
Started Apr 25 12:56:59 PM PDT 24
Finished Apr 25 12:57:02 PM PDT 24
Peak memory 206264 kb
Host smart-941c4cf2-3f41-4cf8-9b01-e35596321930
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824958225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3824958225
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1102230442
Short name T905
Test name
Test status
Simulation time 35946221 ps
CPU time 0.86 seconds
Started Apr 25 12:57:10 PM PDT 24
Finished Apr 25 12:57:14 PM PDT 24
Peak memory 206228 kb
Host smart-15ca31b9-87dc-4d16-9c0e-804ebd452258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102230442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1102230442
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3205192366
Short name T942
Test name
Test status
Simulation time 68845159 ps
CPU time 0.94 seconds
Started Apr 25 12:57:14 PM PDT 24
Finished Apr 25 12:57:18 PM PDT 24
Peak memory 206400 kb
Host smart-c0f60f2f-fd8d-4ac1-83b9-e9b3b2b1b43f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205192366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3205192366
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2252491175
Short name T856
Test name
Test status
Simulation time 55388055 ps
CPU time 1.93 seconds
Started Apr 25 12:57:01 PM PDT 24
Finished Apr 25 12:57:08 PM PDT 24
Peak memory 222672 kb
Host smart-d86d5c6e-0a38-421f-8481-1f76c173ed63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252491175 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2252491175
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.85302594
Short name T252
Test name
Test status
Simulation time 130903499 ps
CPU time 1.52 seconds
Started Apr 25 12:57:00 PM PDT 24
Finished Apr 25 12:57:06 PM PDT 24
Peak memory 206360 kb
Host smart-833ed45f-8cac-412d-8bed-e733cd9b183f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85302594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.85302594
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1770405801
Short name T902
Test name
Test status
Simulation time 124920826 ps
CPU time 1.36 seconds
Started Apr 25 12:57:14 PM PDT 24
Finished Apr 25 12:57:18 PM PDT 24
Peak memory 214532 kb
Host smart-370ddd31-36c3-48a2-a0d5-f25bde2c536b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770405801 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1770405801
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1174316889
Short name T220
Test name
Test status
Simulation time 12534889 ps
CPU time 0.88 seconds
Started Apr 25 12:56:58 PM PDT 24
Finished Apr 25 12:57:02 PM PDT 24
Peak memory 206268 kb
Host smart-34a1938d-083e-4afd-8954-0ea99b7834a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174316889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1174316889
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3961566089
Short name T841
Test name
Test status
Simulation time 24551254 ps
CPU time 0.91 seconds
Started Apr 25 12:57:18 PM PDT 24
Finished Apr 25 12:57:20 PM PDT 24
Peak memory 206200 kb
Host smart-172d575b-434d-49bd-8981-b31572f0f889
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961566089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3961566089
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1519318898
Short name T874
Test name
Test status
Simulation time 40733562 ps
CPU time 1.06 seconds
Started Apr 25 12:57:00 PM PDT 24
Finished Apr 25 12:57:04 PM PDT 24
Peak memory 206364 kb
Host smart-a0319c71-a7cc-46c6-b1b1-92a15de02593
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519318898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1519318898
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.839074418
Short name T901
Test name
Test status
Simulation time 92249315 ps
CPU time 1.55 seconds
Started Apr 25 12:57:01 PM PDT 24
Finished Apr 25 12:57:07 PM PDT 24
Peak memory 214404 kb
Host smart-f5c6bbab-2178-4d97-8d6b-4f56531e90c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839074418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.839074418
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.4228188114
Short name T933
Test name
Test status
Simulation time 191161310 ps
CPU time 3.4 seconds
Started Apr 25 12:57:00 PM PDT 24
Finished Apr 25 12:57:07 PM PDT 24
Peak memory 206216 kb
Host smart-d095c684-3c81-4c34-b2b3-30e9e0b6bc57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228188114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.4228188114
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.3057733620
Short name T430
Test name
Test status
Simulation time 64455229 ps
CPU time 0.85 seconds
Started Apr 25 12:59:36 PM PDT 24
Finished Apr 25 12:59:39 PM PDT 24
Peak memory 206468 kb
Host smart-1e9294dd-c451-4746-9f0a-77ad3aa91e29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057733620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3057733620
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2838828665
Short name T802
Test name
Test status
Simulation time 98833563 ps
CPU time 1.16 seconds
Started Apr 25 12:59:48 PM PDT 24
Finished Apr 25 12:59:51 PM PDT 24
Peak memory 216904 kb
Host smart-92e02e11-36a9-444b-b2ae-10dcf4fb94a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838828665 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2838828665
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.363095641
Short name T127
Test name
Test status
Simulation time 23422674 ps
CPU time 0.97 seconds
Started Apr 25 12:59:22 PM PDT 24
Finished Apr 25 12:59:24 PM PDT 24
Peak memory 218340 kb
Host smart-ff0937f9-9fde-49c2-97a7-38337f455273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363095641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.363095641
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2403475607
Short name T395
Test name
Test status
Simulation time 43378062 ps
CPU time 1.49 seconds
Started Apr 25 12:59:33 PM PDT 24
Finished Apr 25 12:59:36 PM PDT 24
Peak memory 218144 kb
Host smart-dd1385a6-4fd2-42cd-b53e-5acdfbb67467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403475607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2403475607
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.3950496567
Short name T25
Test name
Test status
Simulation time 35738621 ps
CPU time 0.9 seconds
Started Apr 25 12:59:24 PM PDT 24
Finished Apr 25 12:59:26 PM PDT 24
Peak memory 206984 kb
Host smart-e795d609-4254-4d25-aa54-c86138442d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950496567 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3950496567
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.317807108
Short name T59
Test name
Test status
Simulation time 1008899582 ps
CPU time 4.67 seconds
Started Apr 25 12:59:28 PM PDT 24
Finished Apr 25 12:59:34 PM PDT 24
Peak memory 237276 kb
Host smart-c8b2bdea-3bb6-4868-a794-896ab96fc6e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317807108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.317807108
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2964155004
Short name T677
Test name
Test status
Simulation time 16232512 ps
CPU time 1 seconds
Started Apr 25 12:59:14 PM PDT 24
Finished Apr 25 12:59:17 PM PDT 24
Peak memory 215184 kb
Host smart-bc25e4e0-fe18-4b42-9e47-b3bcb850810d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964155004 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2964155004
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2497959680
Short name T821
Test name
Test status
Simulation time 148210880 ps
CPU time 3.4 seconds
Started Apr 25 12:59:14 PM PDT 24
Finished Apr 25 12:59:24 PM PDT 24
Peak memory 216760 kb
Host smart-c858df2c-6e7f-4455-9f45-ba424f4051b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497959680 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2497959680
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1511320150
Short name T568
Test name
Test status
Simulation time 31373206981 ps
CPU time 249.49 seconds
Started Apr 25 12:59:44 PM PDT 24
Finished Apr 25 01:03:55 PM PDT 24
Peak memory 217944 kb
Host smart-11cae3cf-4b8d-415b-a760-8050ab706461
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511320150 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1511320150
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.1693608125
Short name T497
Test name
Test status
Simulation time 46716885 ps
CPU time 0.84 seconds
Started Apr 25 12:59:40 PM PDT 24
Finished Apr 25 12:59:43 PM PDT 24
Peak memory 206472 kb
Host smart-1ab0564a-eaf3-4f4d-a0f9-55b1bc90da5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693608125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1693608125
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.3365885976
Short name T387
Test name
Test status
Simulation time 36793730 ps
CPU time 0.89 seconds
Started Apr 25 12:59:31 PM PDT 24
Finished Apr 25 12:59:33 PM PDT 24
Peak memory 216060 kb
Host smart-03f9c898-b9bc-4709-a4c7-ce705d866805
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365885976 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3365885976
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1894772163
Short name T707
Test name
Test status
Simulation time 30032508 ps
CPU time 1.1 seconds
Started Apr 25 12:59:44 PM PDT 24
Finished Apr 25 12:59:47 PM PDT 24
Peak memory 217880 kb
Host smart-61719ce8-2794-49ee-b385-55ce3d0d7549
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894772163 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1894772163
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.1517460502
Short name T166
Test name
Test status
Simulation time 23201020 ps
CPU time 0.98 seconds
Started Apr 25 12:59:29 PM PDT 24
Finished Apr 25 12:59:31 PM PDT 24
Peak memory 218456 kb
Host smart-7dfd5d6b-679e-42b7-be49-18fa160ffce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517460502 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1517460502
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.4071059705
Short name T208
Test name
Test status
Simulation time 55424470 ps
CPU time 1.19 seconds
Started Apr 25 12:59:36 PM PDT 24
Finished Apr 25 12:59:39 PM PDT 24
Peak memory 215168 kb
Host smart-6eb8fb29-df77-4784-9729-0131bb4e7a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071059705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.4071059705
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1216598254
Short name T822
Test name
Test status
Simulation time 25513329 ps
CPU time 0.92 seconds
Started Apr 25 12:59:21 PM PDT 24
Finished Apr 25 12:59:23 PM PDT 24
Peak memory 215400 kb
Host smart-7ca02dbb-dae8-4aef-86ad-e15dc9b177e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216598254 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1216598254
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2854108807
Short name T16
Test name
Test status
Simulation time 1901221882 ps
CPU time 7.86 seconds
Started Apr 25 12:59:22 PM PDT 24
Finished Apr 25 12:59:31 PM PDT 24
Peak memory 238764 kb
Host smart-9e217640-f2ae-43d2-a59d-749f8e613c06
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854108807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2854108807
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.3432345477
Short name T429
Test name
Test status
Simulation time 18560271 ps
CPU time 1.11 seconds
Started Apr 25 12:59:19 PM PDT 24
Finished Apr 25 12:59:21 PM PDT 24
Peak memory 215148 kb
Host smart-a4640485-9dad-45dd-9ea6-a353c98b4065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432345477 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3432345477
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2384657100
Short name T145
Test name
Test status
Simulation time 251971661 ps
CPU time 2.94 seconds
Started Apr 25 12:59:20 PM PDT 24
Finished Apr 25 12:59:24 PM PDT 24
Peak memory 215168 kb
Host smart-f33bb037-34e4-40a7-a81d-054b24d504af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384657100 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2384657100
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3713471254
Short name T608
Test name
Test status
Simulation time 195159224790 ps
CPU time 535.86 seconds
Started Apr 25 12:59:39 PM PDT 24
Finished Apr 25 01:08:42 PM PDT 24
Peak memory 218988 kb
Host smart-87660b98-44c2-4796-bc93-2925dd2179ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713471254 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3713471254
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1430989067
Short name T288
Test name
Test status
Simulation time 132826100 ps
CPU time 1.18 seconds
Started Apr 25 12:59:36 PM PDT 24
Finished Apr 25 12:59:39 PM PDT 24
Peak memory 215548 kb
Host smart-f3203e06-3e6d-47b6-99cc-124e3dc99cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430989067 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1430989067
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2709482800
Short name T298
Test name
Test status
Simulation time 24224537 ps
CPU time 0.9 seconds
Started Apr 25 12:59:36 PM PDT 24
Finished Apr 25 12:59:39 PM PDT 24
Peak memory 214700 kb
Host smart-81da7ff7-6304-49ad-8897-f113122d6d51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709482800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2709482800
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.2772473204
Short name T182
Test name
Test status
Simulation time 43017957 ps
CPU time 0.88 seconds
Started Apr 25 12:59:32 PM PDT 24
Finished Apr 25 12:59:34 PM PDT 24
Peak memory 216148 kb
Host smart-a9c298cf-24b2-4609-a1cc-9334e888092f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772473204 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2772473204
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1245684292
Short name T669
Test name
Test status
Simulation time 33437472 ps
CPU time 1.12 seconds
Started Apr 25 12:59:34 PM PDT 24
Finished Apr 25 12:59:36 PM PDT 24
Peak memory 219260 kb
Host smart-0326a57a-85ee-4f84-894b-8d5c9ed75cc9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245684292 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1245684292
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.431626449
Short name T656
Test name
Test status
Simulation time 37119411 ps
CPU time 0.88 seconds
Started Apr 25 12:59:40 PM PDT 24
Finished Apr 25 12:59:48 PM PDT 24
Peak memory 223660 kb
Host smart-d4191ac6-da43-42a9-8c55-eb10f221622a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431626449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.431626449
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.960931042
Short name T627
Test name
Test status
Simulation time 114993373 ps
CPU time 1.31 seconds
Started Apr 25 12:59:36 PM PDT 24
Finished Apr 25 12:59:39 PM PDT 24
Peak memory 218340 kb
Host smart-7e0e2fc4-dd7e-4fdf-b7b3-86e554bdb37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960931042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.960931042
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1254474536
Short name T544
Test name
Test status
Simulation time 84627805 ps
CPU time 0.82 seconds
Started Apr 25 12:59:46 PM PDT 24
Finished Apr 25 12:59:49 PM PDT 24
Peak memory 215208 kb
Host smart-32a36de4-aca0-4eb2-8961-881096864c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254474536 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1254474536
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.78318361
Short name T434
Test name
Test status
Simulation time 22658886 ps
CPU time 0.9 seconds
Started Apr 25 12:59:33 PM PDT 24
Finished Apr 25 12:59:36 PM PDT 24
Peak memory 215124 kb
Host smart-7146a017-4f62-48e6-9c7b-31008c1990cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78318361 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.78318361
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1130717200
Short name T458
Test name
Test status
Simulation time 1083757140 ps
CPU time 1.76 seconds
Started Apr 25 12:59:41 PM PDT 24
Finished Apr 25 12:59:45 PM PDT 24
Peak memory 215136 kb
Host smart-fd14060b-7416-402e-b118-7ecbf227e5d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130717200 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1130717200
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.604931329
Short name T711
Test name
Test status
Simulation time 279276449016 ps
CPU time 1719.63 seconds
Started Apr 25 12:59:31 PM PDT 24
Finished Apr 25 01:28:12 PM PDT 24
Peak memory 225556 kb
Host smart-5f51c3a5-0229-4a5c-86c2-4b1b985d56a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604931329 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.604931329
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.2046333543
Short name T474
Test name
Test status
Simulation time 77882159 ps
CPU time 1.2 seconds
Started Apr 25 01:00:48 PM PDT 24
Finished Apr 25 01:00:51 PM PDT 24
Peak memory 216968 kb
Host smart-102f3704-091d-4c8c-96c2-2945d2f36967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046333543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2046333543
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.4123573981
Short name T833
Test name
Test status
Simulation time 51029697 ps
CPU time 0.93 seconds
Started Apr 25 01:00:56 PM PDT 24
Finished Apr 25 01:00:59 PM PDT 24
Peak memory 216640 kb
Host smart-42dedf25-fd27-408e-ab55-9a664681c9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123573981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.4123573981
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.4009841722
Short name T352
Test name
Test status
Simulation time 83602347 ps
CPU time 1.25 seconds
Started Apr 25 01:01:12 PM PDT 24
Finished Apr 25 01:01:16 PM PDT 24
Peak memory 217908 kb
Host smart-8dc18bac-ff2e-4e99-975a-b9a02cb16c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009841722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.4009841722
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.2392203758
Short name T450
Test name
Test status
Simulation time 48669949 ps
CPU time 1.59 seconds
Started Apr 25 01:00:47 PM PDT 24
Finished Apr 25 01:00:51 PM PDT 24
Peak memory 217484 kb
Host smart-93f1ce74-c46a-4391-88d2-32131bf7fd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392203758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2392203758
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.3979456610
Short name T270
Test name
Test status
Simulation time 130423327 ps
CPU time 3.02 seconds
Started Apr 25 01:00:58 PM PDT 24
Finished Apr 25 01:01:03 PM PDT 24
Peak memory 219932 kb
Host smart-e0eb2d43-9295-4f41-853c-346cca59734f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979456610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3979456610
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.2167141548
Short name T71
Test name
Test status
Simulation time 75843588 ps
CPU time 2.63 seconds
Started Apr 25 01:00:56 PM PDT 24
Finished Apr 25 01:01:01 PM PDT 24
Peak memory 219844 kb
Host smart-06c8718d-175d-45be-84d9-cadf47c9aa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167141548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2167141548
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.3211515826
Short name T414
Test name
Test status
Simulation time 39760890 ps
CPU time 1.38 seconds
Started Apr 25 01:00:54 PM PDT 24
Finished Apr 25 01:00:57 PM PDT 24
Peak memory 217048 kb
Host smart-1fe20f91-5ada-4505-adb8-6b0af5a9ed80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211515826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3211515826
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2701276159
Short name T248
Test name
Test status
Simulation time 52260948 ps
CPU time 1.01 seconds
Started Apr 25 01:00:56 PM PDT 24
Finished Apr 25 01:00:59 PM PDT 24
Peak memory 216732 kb
Host smart-1d3d279e-1f6c-41ae-b417-8622254b8ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701276159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2701276159
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3671038325
Short name T615
Test name
Test status
Simulation time 53651558 ps
CPU time 1.56 seconds
Started Apr 25 01:01:07 PM PDT 24
Finished Apr 25 01:01:10 PM PDT 24
Peak memory 217880 kb
Host smart-873331dc-74e6-4166-be68-6f33be8f878c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671038325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3671038325
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.2641174695
Short name T683
Test name
Test status
Simulation time 42614274 ps
CPU time 0.84 seconds
Started Apr 25 01:00:01 PM PDT 24
Finished Apr 25 01:00:04 PM PDT 24
Peak memory 206268 kb
Host smart-7d77c53d-d2ff-46b4-a2a4-3dba5a330688
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641174695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2641174695
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.864342355
Short name T446
Test name
Test status
Simulation time 29974361 ps
CPU time 0.81 seconds
Started Apr 25 12:59:57 PM PDT 24
Finished Apr 25 12:59:58 PM PDT 24
Peak memory 216040 kb
Host smart-448dcbd1-b07e-4de2-a525-9a66d804241c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864342355 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.864342355
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.3836353150
Short name T583
Test name
Test status
Simulation time 20856254 ps
CPU time 0.99 seconds
Started Apr 25 12:59:52 PM PDT 24
Finished Apr 25 12:59:54 PM PDT 24
Peak memory 218064 kb
Host smart-0d634ba5-f6c2-4d26-995f-817cf7c20e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836353150 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3836353150
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.4133072867
Short name T517
Test name
Test status
Simulation time 98562716 ps
CPU time 1.17 seconds
Started Apr 25 12:59:32 PM PDT 24
Finished Apr 25 12:59:34 PM PDT 24
Peak memory 216964 kb
Host smart-c0fbbd02-9033-40ed-ac14-2a1530877e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133072867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.4133072867
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.294828541
Short name T369
Test name
Test status
Simulation time 30949554 ps
CPU time 0.86 seconds
Started Apr 25 01:00:11 PM PDT 24
Finished Apr 25 01:00:16 PM PDT 24
Peak memory 215100 kb
Host smart-310580f3-6a0d-4901-b6ff-ef401684a044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294828541 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.294828541
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3652965960
Short name T645
Test name
Test status
Simulation time 47942041 ps
CPU time 0.92 seconds
Started Apr 25 12:59:43 PM PDT 24
Finished Apr 25 12:59:46 PM PDT 24
Peak memory 215120 kb
Host smart-7b424ea7-5767-4f80-9811-d7cf4078709d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652965960 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3652965960
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.3318743759
Short name T808
Test name
Test status
Simulation time 83121945 ps
CPU time 2.19 seconds
Started Apr 25 12:59:47 PM PDT 24
Finished Apr 25 12:59:51 PM PDT 24
Peak memory 215172 kb
Host smart-393e3380-5fe9-4942-933c-4a74e0eb2992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318743759 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3318743759
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3106342207
Short name T189
Test name
Test status
Simulation time 99579633932 ps
CPU time 662.38 seconds
Started Apr 25 12:59:38 PM PDT 24
Finished Apr 25 01:10:43 PM PDT 24
Peak memory 220192 kb
Host smart-f00bf0b3-ded8-4628-b894-3e9cd230442d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106342207 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3106342207
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.edn_genbits.1425392591
Short name T593
Test name
Test status
Simulation time 52245608 ps
CPU time 1.84 seconds
Started Apr 25 01:00:56 PM PDT 24
Finished Apr 25 01:01:00 PM PDT 24
Peak memory 217996 kb
Host smart-0aa46e73-3d4e-40e2-8884-ed4383dcd36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425392591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1425392591
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1447473915
Short name T611
Test name
Test status
Simulation time 69619201 ps
CPU time 1.23 seconds
Started Apr 25 01:00:51 PM PDT 24
Finished Apr 25 01:00:54 PM PDT 24
Peak memory 216844 kb
Host smart-afe01894-9fbc-4a7d-95d1-ac5616d8ca9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447473915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1447473915
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.3453180661
Short name T655
Test name
Test status
Simulation time 42787780 ps
CPU time 1.45 seconds
Started Apr 25 01:00:52 PM PDT 24
Finished Apr 25 01:00:56 PM PDT 24
Peak memory 216736 kb
Host smart-cc5b7e72-8ff7-419a-9cb3-dc914f035f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453180661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3453180661
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.539067591
Short name T828
Test name
Test status
Simulation time 37776258 ps
CPU time 1.62 seconds
Started Apr 25 01:01:03 PM PDT 24
Finished Apr 25 01:01:06 PM PDT 24
Peak memory 216884 kb
Host smart-27fe72f7-47f2-4d7d-a03d-d82487591293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539067591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.539067591
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.359609754
Short name T668
Test name
Test status
Simulation time 87246338 ps
CPU time 2.28 seconds
Started Apr 25 01:01:03 PM PDT 24
Finished Apr 25 01:01:06 PM PDT 24
Peak memory 219676 kb
Host smart-96838bfe-e794-492f-9b6d-86337e06542d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359609754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.359609754
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.827813162
Short name T507
Test name
Test status
Simulation time 31525386 ps
CPU time 1.27 seconds
Started Apr 25 01:00:51 PM PDT 24
Finished Apr 25 01:00:55 PM PDT 24
Peak memory 218056 kb
Host smart-8819505b-8a67-42b0-b67a-1a7df364e1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827813162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.827813162
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.1152025990
Short name T423
Test name
Test status
Simulation time 100577179 ps
CPU time 1.29 seconds
Started Apr 25 01:01:01 PM PDT 24
Finished Apr 25 01:01:03 PM PDT 24
Peak memory 216796 kb
Host smart-b3c37cdc-e710-48a0-9803-5bb5e446c2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152025990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1152025990
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.82093155
Short name T206
Test name
Test status
Simulation time 39532872 ps
CPU time 1.37 seconds
Started Apr 25 01:00:56 PM PDT 24
Finished Apr 25 01:00:59 PM PDT 24
Peak memory 218180 kb
Host smart-4496b28d-be5d-4b75-8be6-5ba79522ce41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82093155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.82093155
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.3592316656
Short name T482
Test name
Test status
Simulation time 28584100 ps
CPU time 0.92 seconds
Started Apr 25 12:59:32 PM PDT 24
Finished Apr 25 12:59:34 PM PDT 24
Peak memory 214752 kb
Host smart-b9546a17-73b8-499d-ab2e-1ec1651ad78c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592316656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3592316656
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.1425568779
Short name T114
Test name
Test status
Simulation time 11836270 ps
CPU time 0.87 seconds
Started Apr 25 12:59:53 PM PDT 24
Finished Apr 25 12:59:55 PM PDT 24
Peak memory 215256 kb
Host smart-348e8e2e-d126-4511-8a2d-ebe930cfbb9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425568779 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1425568779
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3235465776
Short name T513
Test name
Test status
Simulation time 84719978 ps
CPU time 1.01 seconds
Started Apr 25 12:59:34 PM PDT 24
Finished Apr 25 12:59:36 PM PDT 24
Peak memory 216696 kb
Host smart-1bdcd79f-5bbd-4c84-9bbf-dc3af71bd9c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235465776 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3235465776
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.2552481971
Short name T413
Test name
Test status
Simulation time 21249267 ps
CPU time 1.02 seconds
Started Apr 25 01:00:38 PM PDT 24
Finished Apr 25 01:00:43 PM PDT 24
Peak memory 217924 kb
Host smart-4e0d41ad-02c8-4e62-9ef3-c84e2c87b471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552481971 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2552481971
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2469024038
Short name T757
Test name
Test status
Simulation time 128138707 ps
CPU time 2.76 seconds
Started Apr 25 12:59:52 PM PDT 24
Finished Apr 25 12:59:56 PM PDT 24
Peak memory 219872 kb
Host smart-026fca54-80f3-481b-96de-503199308d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469024038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2469024038
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3819121239
Short name T584
Test name
Test status
Simulation time 37811097 ps
CPU time 0.96 seconds
Started Apr 25 12:59:35 PM PDT 24
Finished Apr 25 12:59:38 PM PDT 24
Peak memory 223656 kb
Host smart-f9b52573-0719-481f-b4a0-3bf41cec9788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819121239 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3819121239
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.840108191
Short name T318
Test name
Test status
Simulation time 19284799 ps
CPU time 1.02 seconds
Started Apr 25 12:59:50 PM PDT 24
Finished Apr 25 12:59:53 PM PDT 24
Peak memory 215108 kb
Host smart-db255df5-5151-46eb-8e96-4fe9b9862596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840108191 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.840108191
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2676613535
Short name T533
Test name
Test status
Simulation time 143128071 ps
CPU time 3.21 seconds
Started Apr 25 01:00:02 PM PDT 24
Finished Apr 25 01:00:07 PM PDT 24
Peak memory 216752 kb
Host smart-be81e3c2-1046-4d2b-b156-6f12aee31dcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676613535 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2676613535
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.206938465
Short name T714
Test name
Test status
Simulation time 92676623284 ps
CPU time 1141.8 seconds
Started Apr 25 12:59:48 PM PDT 24
Finished Apr 25 01:18:52 PM PDT 24
Peak memory 224116 kb
Host smart-4f4615d9-6123-4d32-b232-3fdc100c70c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206938465 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.206938465
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.2340649626
Short name T689
Test name
Test status
Simulation time 47822465 ps
CPU time 1.43 seconds
Started Apr 25 01:00:56 PM PDT 24
Finished Apr 25 01:01:00 PM PDT 24
Peak memory 218016 kb
Host smart-c9cfed21-cb8c-4f45-858a-9d7bc464b2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340649626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2340649626
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.245020667
Short name T709
Test name
Test status
Simulation time 66079398 ps
CPU time 1.59 seconds
Started Apr 25 01:01:00 PM PDT 24
Finished Apr 25 01:01:03 PM PDT 24
Peak memory 218064 kb
Host smart-aba7a97a-df08-421e-8449-b94e38d46900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245020667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.245020667
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.3003905197
Short name T388
Test name
Test status
Simulation time 76884256 ps
CPU time 1.23 seconds
Started Apr 25 01:01:00 PM PDT 24
Finished Apr 25 01:01:02 PM PDT 24
Peak memory 218764 kb
Host smart-72851ad3-cc12-49d5-ab7f-256e118696ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003905197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3003905197
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.4020532383
Short name T686
Test name
Test status
Simulation time 42410431 ps
CPU time 1.76 seconds
Started Apr 25 01:00:46 PM PDT 24
Finished Apr 25 01:00:55 PM PDT 24
Peak memory 217956 kb
Host smart-ddcf4ed0-1910-4538-8e8b-3500c9f573fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020532383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.4020532383
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.2666105142
Short name T408
Test name
Test status
Simulation time 224005642 ps
CPU time 1.96 seconds
Started Apr 25 01:00:41 PM PDT 24
Finished Apr 25 01:00:46 PM PDT 24
Peak memory 219292 kb
Host smart-2765a452-d7b7-4794-8c42-2cf07539f826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666105142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2666105142
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.857032684
Short name T639
Test name
Test status
Simulation time 91453981 ps
CPU time 1.16 seconds
Started Apr 25 01:00:51 PM PDT 24
Finished Apr 25 01:00:54 PM PDT 24
Peak memory 216756 kb
Host smart-922e9b09-5c88-4f12-9983-d3cd8e0477a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857032684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.857032684
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.2881695864
Short name T717
Test name
Test status
Simulation time 73528597 ps
CPU time 1.11 seconds
Started Apr 25 01:01:00 PM PDT 24
Finished Apr 25 01:01:02 PM PDT 24
Peak memory 216656 kb
Host smart-3148bfbe-50ca-4488-a028-e7ee05fd1bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881695864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2881695864
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.1948889545
Short name T441
Test name
Test status
Simulation time 66172744 ps
CPU time 1.01 seconds
Started Apr 25 01:00:51 PM PDT 24
Finished Apr 25 01:00:54 PM PDT 24
Peak memory 216732 kb
Host smart-f92fc67c-0105-4075-a2f0-73b7f7407094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948889545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1948889545
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2759592445
Short name T207
Test name
Test status
Simulation time 73912313 ps
CPU time 1.19 seconds
Started Apr 25 01:00:58 PM PDT 24
Finished Apr 25 01:01:01 PM PDT 24
Peak memory 218124 kb
Host smart-02b0f468-c9fb-45b2-9d4f-1b8bd1edf917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759592445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2759592445
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2813300840
Short name T538
Test name
Test status
Simulation time 43675969 ps
CPU time 1.2 seconds
Started Apr 25 12:59:39 PM PDT 24
Finished Apr 25 12:59:42 PM PDT 24
Peak memory 215596 kb
Host smart-8a28a4da-7634-4fe4-a0c5-5bdc74a6e907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813300840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2813300840
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.865092773
Short name T407
Test name
Test status
Simulation time 37116723 ps
CPU time 1.06 seconds
Started Apr 25 12:59:49 PM PDT 24
Finished Apr 25 12:59:52 PM PDT 24
Peak memory 206508 kb
Host smart-3b981400-81e2-4e21-9e47-f4a1769cc258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865092773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.865092773
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_err.2083658421
Short name T83
Test name
Test status
Simulation time 25336672 ps
CPU time 1.02 seconds
Started Apr 25 12:59:42 PM PDT 24
Finished Apr 25 12:59:45 PM PDT 24
Peak memory 219608 kb
Host smart-13d550bf-d4f7-419e-89a1-35a77ec722a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083658421 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2083658421
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2831372790
Short name T713
Test name
Test status
Simulation time 56603141 ps
CPU time 1.58 seconds
Started Apr 25 12:59:58 PM PDT 24
Finished Apr 25 01:00:01 PM PDT 24
Peak memory 218100 kb
Host smart-3dea167d-07e1-4d62-b833-2fb0f5ff9740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831372790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2831372790
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2397766973
Short name T156
Test name
Test status
Simulation time 23609146 ps
CPU time 0.96 seconds
Started Apr 25 12:59:42 PM PDT 24
Finished Apr 25 12:59:45 PM PDT 24
Peak memory 215744 kb
Host smart-a3a8716b-2333-4364-8926-2af63b68b5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397766973 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2397766973
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.889247560
Short name T745
Test name
Test status
Simulation time 36754029 ps
CPU time 0.91 seconds
Started Apr 25 01:00:10 PM PDT 24
Finished Apr 25 01:00:15 PM PDT 24
Peak memory 215148 kb
Host smart-bd7eac1c-48a1-4e58-b79c-ec4bf561c32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889247560 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.889247560
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2191122404
Short name T334
Test name
Test status
Simulation time 671094426 ps
CPU time 4.78 seconds
Started Apr 25 12:59:57 PM PDT 24
Finished Apr 25 01:00:03 PM PDT 24
Peak memory 216592 kb
Host smart-28b28cda-1621-48f7-978c-ecc2ed098e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191122404 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2191122404
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.885191474
Short name T360
Test name
Test status
Simulation time 33543436897 ps
CPU time 448.56 seconds
Started Apr 25 12:59:40 PM PDT 24
Finished Apr 25 01:07:11 PM PDT 24
Peak memory 217764 kb
Host smart-3b3d3da5-899f-4461-bf1e-a544029f69b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885191474 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.885191474
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.470993656
Short name T796
Test name
Test status
Simulation time 110822668 ps
CPU time 1.1 seconds
Started Apr 25 01:00:47 PM PDT 24
Finished Apr 25 01:00:51 PM PDT 24
Peak memory 217008 kb
Host smart-0b840559-e287-4e76-92d3-91c7dd8dc5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470993656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.470993656
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.2458712068
Short name T671
Test name
Test status
Simulation time 47800382 ps
CPU time 1.31 seconds
Started Apr 25 01:00:51 PM PDT 24
Finished Apr 25 01:00:55 PM PDT 24
Peak memory 218224 kb
Host smart-201f73c1-f52a-4ff7-9f22-9e380b36b301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458712068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2458712068
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.673328701
Short name T377
Test name
Test status
Simulation time 46149694 ps
CPU time 1.69 seconds
Started Apr 25 01:01:10 PM PDT 24
Finished Apr 25 01:01:13 PM PDT 24
Peak memory 218232 kb
Host smart-95843d71-518a-4ab8-aae8-70b541abf878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673328701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.673328701
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.4150691433
Short name T810
Test name
Test status
Simulation time 48046467 ps
CPU time 1.65 seconds
Started Apr 25 01:00:50 PM PDT 24
Finished Apr 25 01:00:54 PM PDT 24
Peak memory 218084 kb
Host smart-83292d3e-018a-49c5-a3bb-4fb88d0a525e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150691433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.4150691433
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3847806854
Short name T739
Test name
Test status
Simulation time 30353578 ps
CPU time 1.1 seconds
Started Apr 25 01:00:55 PM PDT 24
Finished Apr 25 01:00:58 PM PDT 24
Peak memory 219556 kb
Host smart-493df4d0-0cb7-4e20-957e-8ca820bf17b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847806854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3847806854
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.436233224
Short name T720
Test name
Test status
Simulation time 63342557 ps
CPU time 1.43 seconds
Started Apr 25 01:00:48 PM PDT 24
Finished Apr 25 01:00:51 PM PDT 24
Peak memory 218252 kb
Host smart-d8448f11-6b5b-4968-8ca7-852c1a64ec5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436233224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.436233224
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.2322603550
Short name T204
Test name
Test status
Simulation time 52287062 ps
CPU time 1.28 seconds
Started Apr 25 01:01:10 PM PDT 24
Finished Apr 25 01:01:13 PM PDT 24
Peak memory 218400 kb
Host smart-534451f0-01c3-41ee-a37b-866906af5da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322603550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2322603550
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.3940394949
Short name T678
Test name
Test status
Simulation time 150586890 ps
CPU time 1.66 seconds
Started Apr 25 01:00:52 PM PDT 24
Finished Apr 25 01:00:55 PM PDT 24
Peak memory 218740 kb
Host smart-f8792baf-1d4f-4c8d-85f8-5b495fdbb6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940394949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3940394949
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.1382697154
Short name T276
Test name
Test status
Simulation time 98755797 ps
CPU time 1.53 seconds
Started Apr 25 01:00:54 PM PDT 24
Finished Apr 25 01:00:58 PM PDT 24
Peak memory 218280 kb
Host smart-523b5b97-509f-4fdd-9355-53bd391bc626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382697154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1382697154
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert_test.573874755
Short name T63
Test name
Test status
Simulation time 23413476 ps
CPU time 0.88 seconds
Started Apr 25 12:59:47 PM PDT 24
Finished Apr 25 12:59:50 PM PDT 24
Peak memory 206484 kb
Host smart-e9c3acac-bd29-4f62-97fd-e0c65e43b23c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573874755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.573874755
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1156226647
Short name T1
Test name
Test status
Simulation time 10918090 ps
CPU time 0.87 seconds
Started Apr 25 12:59:36 PM PDT 24
Finished Apr 25 12:59:39 PM PDT 24
Peak memory 216040 kb
Host smart-745036c6-573a-49a6-b7db-d8e2723e38ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156226647 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1156226647
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.1786147968
Short name T824
Test name
Test status
Simulation time 22388911 ps
CPU time 1.06 seconds
Started Apr 25 12:59:53 PM PDT 24
Finished Apr 25 12:59:55 PM PDT 24
Peak memory 219416 kb
Host smart-5d41db62-1b34-4e15-81e1-804d7f9e8387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786147968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1786147968
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3941569599
Short name T188
Test name
Test status
Simulation time 256247494 ps
CPU time 3.21 seconds
Started Apr 25 12:59:57 PM PDT 24
Finished Apr 25 01:00:01 PM PDT 24
Peak memory 219644 kb
Host smart-8969d174-b2c0-4915-b686-4483992b920a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941569599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3941569599
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1749927278
Short name T77
Test name
Test status
Simulation time 20729063 ps
CPU time 1.08 seconds
Started Apr 25 12:59:51 PM PDT 24
Finished Apr 25 12:59:53 PM PDT 24
Peak memory 215664 kb
Host smart-277a584e-f2ed-4cb2-a009-e40e15590bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749927278 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1749927278
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2905020863
Short name T693
Test name
Test status
Simulation time 18417334 ps
CPU time 1.01 seconds
Started Apr 25 12:59:35 PM PDT 24
Finished Apr 25 12:59:37 PM PDT 24
Peak memory 206932 kb
Host smart-92f310fe-e485-4e6d-bc94-86c4b50b8e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905020863 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2905020863
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3608113851
Short name T744
Test name
Test status
Simulation time 253103372 ps
CPU time 2.44 seconds
Started Apr 25 12:59:43 PM PDT 24
Finished Apr 25 12:59:47 PM PDT 24
Peak memory 216632 kb
Host smart-8594e820-95d2-45f2-97ef-e777c85f8e1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608113851 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3608113851
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2355740064
Short name T610
Test name
Test status
Simulation time 90352444647 ps
CPU time 333.07 seconds
Started Apr 25 01:00:08 PM PDT 24
Finished Apr 25 01:05:45 PM PDT 24
Peak memory 218952 kb
Host smart-54bb212f-b696-40aa-b517-97cbf95b866f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355740064 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2355740064
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.2946196845
Short name T19
Test name
Test status
Simulation time 26059417 ps
CPU time 1.33 seconds
Started Apr 25 01:00:56 PM PDT 24
Finished Apr 25 01:00:59 PM PDT 24
Peak memory 218224 kb
Host smart-cc835ea9-2267-4dc1-8f1c-c35564ce6985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946196845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2946196845
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.2103317204
Short name T609
Test name
Test status
Simulation time 87759522 ps
CPU time 1.16 seconds
Started Apr 25 01:01:23 PM PDT 24
Finished Apr 25 01:01:26 PM PDT 24
Peak memory 217008 kb
Host smart-c31c2c16-ab7b-4cc9-a55f-299198432721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103317204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2103317204
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.3318501137
Short name T503
Test name
Test status
Simulation time 70529163 ps
CPU time 1.07 seconds
Started Apr 25 01:01:24 PM PDT 24
Finished Apr 25 01:01:27 PM PDT 24
Peak memory 216816 kb
Host smart-1a35e901-2ee5-4fda-b32b-f0f2cf800250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318501137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3318501137
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.3535553446
Short name T384
Test name
Test status
Simulation time 84440650 ps
CPU time 1.16 seconds
Started Apr 25 01:00:47 PM PDT 24
Finished Apr 25 01:00:51 PM PDT 24
Peak memory 216784 kb
Host smart-57535051-523c-4692-8600-7ddc920ec7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535553446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3535553446
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.2230364226
Short name T836
Test name
Test status
Simulation time 61696788 ps
CPU time 1.54 seconds
Started Apr 25 01:01:03 PM PDT 24
Finished Apr 25 01:01:05 PM PDT 24
Peak memory 218132 kb
Host smart-924063f0-94f7-41d1-bec5-d9c55f52f28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230364226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2230364226
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.3163436857
Short name T404
Test name
Test status
Simulation time 56435130 ps
CPU time 1.42 seconds
Started Apr 25 01:00:42 PM PDT 24
Finished Apr 25 01:00:47 PM PDT 24
Peak memory 218376 kb
Host smart-705d6306-c9ba-4690-a7f4-4436f71e1843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163436857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3163436857
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.883018977
Short name T363
Test name
Test status
Simulation time 493941041 ps
CPU time 3.66 seconds
Started Apr 25 01:00:51 PM PDT 24
Finished Apr 25 01:00:57 PM PDT 24
Peak memory 219632 kb
Host smart-eba032e5-c236-45c0-861b-e9b99d11982a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883018977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.883018977
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.1782131954
Short name T684
Test name
Test status
Simulation time 117736036 ps
CPU time 1.9 seconds
Started Apr 25 01:01:03 PM PDT 24
Finished Apr 25 01:01:06 PM PDT 24
Peak memory 218320 kb
Host smart-a4951de0-1b11-4e19-981b-1dd1afac0f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782131954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1782131954
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.946823309
Short name T530
Test name
Test status
Simulation time 30913929 ps
CPU time 1.34 seconds
Started Apr 25 01:00:51 PM PDT 24
Finished Apr 25 01:00:55 PM PDT 24
Peak memory 218024 kb
Host smart-586f5ee7-8942-44bd-add8-10c62c1dd7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946823309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.946823309
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.3431361374
Short name T316
Test name
Test status
Simulation time 40310412 ps
CPU time 1.02 seconds
Started Apr 25 12:59:48 PM PDT 24
Finished Apr 25 12:59:51 PM PDT 24
Peak memory 206548 kb
Host smart-c63769da-fa15-4b95-8817-fbc5938d1051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431361374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3431361374
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2641134051
Short name T499
Test name
Test status
Simulation time 20999686 ps
CPU time 0.9 seconds
Started Apr 25 12:59:49 PM PDT 24
Finished Apr 25 12:59:52 PM PDT 24
Peak memory 215696 kb
Host smart-5efb53b9-b979-4281-bc20-a758c6f48cd9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641134051 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2641134051
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.171046019
Short name T319
Test name
Test status
Simulation time 21007088 ps
CPU time 0.92 seconds
Started Apr 25 12:59:57 PM PDT 24
Finished Apr 25 12:59:59 PM PDT 24
Peak memory 218292 kb
Host smart-82cacaf2-a098-49b8-8173-fbb92a67fa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171046019 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.171046019
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2091791453
Short name T633
Test name
Test status
Simulation time 114382951 ps
CPU time 1.63 seconds
Started Apr 25 12:59:38 PM PDT 24
Finished Apr 25 12:59:42 PM PDT 24
Peak memory 218336 kb
Host smart-bc2a57bf-9747-40e5-9aa2-5ca7cd0b6b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091791453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2091791453
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.1215931038
Short name T437
Test name
Test status
Simulation time 18909064 ps
CPU time 0.98 seconds
Started Apr 25 12:59:47 PM PDT 24
Finished Apr 25 12:59:50 PM PDT 24
Peak memory 215076 kb
Host smart-39f9fd58-b083-470f-b695-69b84777c639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215931038 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1215931038
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1609218225
Short name T212
Test name
Test status
Simulation time 697242635 ps
CPU time 2.93 seconds
Started Apr 25 01:00:12 PM PDT 24
Finished Apr 25 01:00:19 PM PDT 24
Peak memory 216952 kb
Host smart-50128eed-1e38-4e96-9c75-73598cdf857c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609218225 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1609218225
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2729455165
Short name T759
Test name
Test status
Simulation time 541113505593 ps
CPU time 927.52 seconds
Started Apr 25 01:00:07 PM PDT 24
Finished Apr 25 01:15:39 PM PDT 24
Peak memory 221612 kb
Host smart-112d4bd7-e632-4e80-a1e7-558f45cbc69d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729455165 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2729455165
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.369574060
Short name T779
Test name
Test status
Simulation time 71193416 ps
CPU time 1.05 seconds
Started Apr 25 01:00:52 PM PDT 24
Finished Apr 25 01:00:56 PM PDT 24
Peak memory 216908 kb
Host smart-d0d6bc41-d4f0-4fe4-847a-1d775643394c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369574060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.369574060
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.3182970354
Short name T562
Test name
Test status
Simulation time 59274641 ps
CPU time 1.29 seconds
Started Apr 25 01:00:52 PM PDT 24
Finished Apr 25 01:00:56 PM PDT 24
Peak memory 216748 kb
Host smart-efdf2d8c-cafd-4d96-8f9d-93bc62eb63ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182970354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3182970354
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.3225427495
Short name T729
Test name
Test status
Simulation time 41088065 ps
CPU time 1.44 seconds
Started Apr 25 01:02:13 PM PDT 24
Finished Apr 25 01:02:16 PM PDT 24
Peak memory 219464 kb
Host smart-0b0da2bd-92e3-4681-99c1-59e753941a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225427495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3225427495
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.4286586615
Short name T366
Test name
Test status
Simulation time 32559596 ps
CPU time 1.45 seconds
Started Apr 25 01:00:58 PM PDT 24
Finished Apr 25 01:01:01 PM PDT 24
Peak memory 217976 kb
Host smart-93714289-613d-4092-a206-3fe54e7b9f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286586615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.4286586615
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.2085972980
Short name T336
Test name
Test status
Simulation time 54060776 ps
CPU time 1.33 seconds
Started Apr 25 01:01:46 PM PDT 24
Finished Apr 25 01:01:50 PM PDT 24
Peak memory 215676 kb
Host smart-c8bf0364-b425-483c-8c01-e62b4e1193ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085972980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2085972980
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.3123370475
Short name T409
Test name
Test status
Simulation time 42472792 ps
CPU time 1.13 seconds
Started Apr 25 01:00:52 PM PDT 24
Finished Apr 25 01:00:55 PM PDT 24
Peak memory 219508 kb
Host smart-37fd42c3-e9ce-4eda-b9c8-ee50488adb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123370475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3123370475
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.3996355194
Short name T74
Test name
Test status
Simulation time 41059495 ps
CPU time 1.47 seconds
Started Apr 25 01:01:09 PM PDT 24
Finished Apr 25 01:01:11 PM PDT 24
Peak memory 216860 kb
Host smart-8ed495b0-04f4-46c6-aa82-7630a405be3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996355194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3996355194
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.939212295
Short name T333
Test name
Test status
Simulation time 49701561 ps
CPU time 1.53 seconds
Started Apr 25 01:01:01 PM PDT 24
Finished Apr 25 01:01:03 PM PDT 24
Peak memory 216804 kb
Host smart-3667c452-96c5-44d8-8033-622bdaeeba37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939212295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.939212295
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.962906275
Short name T210
Test name
Test status
Simulation time 48999022 ps
CPU time 1.53 seconds
Started Apr 25 01:00:45 PM PDT 24
Finished Apr 25 01:00:50 PM PDT 24
Peak memory 215172 kb
Host smart-fe8aaa8e-a97d-4f06-854d-67577d9157a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962906275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.962906275
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.1140418159
Short name T322
Test name
Test status
Simulation time 29148502 ps
CPU time 1.29 seconds
Started Apr 25 01:00:58 PM PDT 24
Finished Apr 25 01:01:01 PM PDT 24
Peak memory 218008 kb
Host smart-6148ad35-12e4-400e-af15-2d8bbec12a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140418159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1140418159
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2108565657
Short name T282
Test name
Test status
Simulation time 40877567 ps
CPU time 1.16 seconds
Started Apr 25 01:00:03 PM PDT 24
Finished Apr 25 01:00:06 PM PDT 24
Peak memory 215564 kb
Host smart-9c65e8f8-d821-4c4a-baa3-cac2ad26de0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108565657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2108565657
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.478025009
Short name T383
Test name
Test status
Simulation time 60651161 ps
CPU time 0.82 seconds
Started Apr 25 12:59:56 PM PDT 24
Finished Apr 25 01:00:03 PM PDT 24
Peak memory 206348 kb
Host smart-aa21c18d-6a97-4277-a6f9-fe986ca0f9b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478025009 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.478025009
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2751848458
Short name T115
Test name
Test status
Simulation time 13255139 ps
CPU time 0.9 seconds
Started Apr 25 01:00:22 PM PDT 24
Finished Apr 25 01:00:25 PM PDT 24
Peak memory 216196 kb
Host smart-984f9b20-6971-4c0a-80fc-b3c0ae3630b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751848458 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2751848458
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.490800187
Short name T448
Test name
Test status
Simulation time 58706819 ps
CPU time 1.08 seconds
Started Apr 25 12:59:45 PM PDT 24
Finished Apr 25 12:59:49 PM PDT 24
Peak memory 217780 kb
Host smart-b711677e-2626-44d9-9a01-2008785fa820
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490800187 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.490800187
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.4027029027
Short name T756
Test name
Test status
Simulation time 26414658 ps
CPU time 1.31 seconds
Started Apr 25 12:59:59 PM PDT 24
Finished Apr 25 01:00:02 PM PDT 24
Peak memory 232108 kb
Host smart-86f67b69-68fc-4ac7-8039-a0f413c8a095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027029027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.4027029027
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2140754831
Short name T680
Test name
Test status
Simulation time 40023892 ps
CPU time 1.53 seconds
Started Apr 25 01:00:03 PM PDT 24
Finished Apr 25 01:00:07 PM PDT 24
Peak memory 219528 kb
Host smart-8cd5e316-dd4b-4ba8-9126-ce7973d2b40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140754831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2140754831
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2775472230
Short name T157
Test name
Test status
Simulation time 27683984 ps
CPU time 0.86 seconds
Started Apr 25 01:00:07 PM PDT 24
Finished Apr 25 01:00:12 PM PDT 24
Peak memory 215600 kb
Host smart-c538f2e2-064d-4327-bd1c-318b2bb46698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775472230 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2775472230
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1386636276
Short name T295
Test name
Test status
Simulation time 20527590 ps
CPU time 0.91 seconds
Started Apr 25 12:59:47 PM PDT 24
Finished Apr 25 12:59:50 PM PDT 24
Peak memory 207004 kb
Host smart-1ea1be73-aa91-4038-8df9-98e22f6b7bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386636276 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1386636276
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1641694789
Short name T643
Test name
Test status
Simulation time 316186918 ps
CPU time 1.11 seconds
Started Apr 25 12:59:46 PM PDT 24
Finished Apr 25 12:59:49 PM PDT 24
Peak memory 216884 kb
Host smart-5a671607-629f-41ee-8624-14b78e50ced0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641694789 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1641694789
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3713570123
Short name T710
Test name
Test status
Simulation time 179527071607 ps
CPU time 1176.45 seconds
Started Apr 25 12:59:59 PM PDT 24
Finished Apr 25 01:19:37 PM PDT 24
Peak memory 224224 kb
Host smart-b97369ac-23e7-496a-a5fc-956005ab59ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713570123 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3713570123
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.3880823340
Short name T292
Test name
Test status
Simulation time 286278357 ps
CPU time 1.22 seconds
Started Apr 25 01:00:55 PM PDT 24
Finished Apr 25 01:00:58 PM PDT 24
Peak memory 218520 kb
Host smart-e4ec14d1-0bd9-42c6-9070-026d20e4776f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880823340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3880823340
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.3721036385
Short name T788
Test name
Test status
Simulation time 37175903 ps
CPU time 1.49 seconds
Started Apr 25 01:01:19 PM PDT 24
Finished Apr 25 01:01:22 PM PDT 24
Peak memory 218000 kb
Host smart-64224fff-c9d3-4453-9bde-9d243bdbf308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721036385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3721036385
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.925056729
Short name T294
Test name
Test status
Simulation time 56472213 ps
CPU time 1.39 seconds
Started Apr 25 01:00:51 PM PDT 24
Finished Apr 25 01:00:54 PM PDT 24
Peak memory 218148 kb
Host smart-04e06eed-102b-4bbc-b986-6a755129d122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925056729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.925056729
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.1049345349
Short name T439
Test name
Test status
Simulation time 37401918 ps
CPU time 1.46 seconds
Started Apr 25 01:00:58 PM PDT 24
Finished Apr 25 01:01:01 PM PDT 24
Peak memory 218096 kb
Host smart-bce9e338-43a4-4dd0-8f9b-01c08c39805e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049345349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1049345349
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.1806697966
Short name T515
Test name
Test status
Simulation time 48673974 ps
CPU time 1.68 seconds
Started Apr 25 01:01:46 PM PDT 24
Finished Apr 25 01:01:51 PM PDT 24
Peak memory 216740 kb
Host smart-2933ae04-83e7-4e8a-baaf-4ade858a0926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806697966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1806697966
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.444078858
Short name T337
Test name
Test status
Simulation time 57978835 ps
CPU time 1.19 seconds
Started Apr 25 01:01:09 PM PDT 24
Finished Apr 25 01:01:12 PM PDT 24
Peak memory 217816 kb
Host smart-ff502730-af96-437a-a017-40882346efd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444078858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.444078858
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.3343105167
Short name T692
Test name
Test status
Simulation time 39421510 ps
CPU time 1.23 seconds
Started Apr 25 01:00:56 PM PDT 24
Finished Apr 25 01:00:59 PM PDT 24
Peak memory 216860 kb
Host smart-a037ef00-b9d8-48a6-8143-1b458d764749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343105167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3343105167
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.1222335522
Short name T797
Test name
Test status
Simulation time 31683772 ps
CPU time 1.35 seconds
Started Apr 25 01:00:56 PM PDT 24
Finished Apr 25 01:01:00 PM PDT 24
Peak memory 217200 kb
Host smart-6d9d3528-8475-4a7a-b0df-bd91537ea711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222335522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1222335522
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.39963348
Short name T506
Test name
Test status
Simulation time 56087146 ps
CPU time 1.28 seconds
Started Apr 25 01:01:04 PM PDT 24
Finished Apr 25 01:01:07 PM PDT 24
Peak memory 216932 kb
Host smart-de124f5e-6ba1-41a3-a943-dcc4ff262efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39963348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.39963348
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.665996364
Short name T614
Test name
Test status
Simulation time 28377223 ps
CPU time 1.3 seconds
Started Apr 25 01:00:00 PM PDT 24
Finished Apr 25 01:00:03 PM PDT 24
Peak memory 215540 kb
Host smart-6e467b90-4149-4fab-b184-9256915a3ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665996364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.665996364
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3077062767
Short name T376
Test name
Test status
Simulation time 32605120 ps
CPU time 0.83 seconds
Started Apr 25 01:00:04 PM PDT 24
Finished Apr 25 01:00:06 PM PDT 24
Peak memory 206764 kb
Host smart-2e14b7fd-ec63-4932-803a-75e5686edb1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077062767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3077062767
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3590453460
Short name T112
Test name
Test status
Simulation time 13217051 ps
CPU time 0.91 seconds
Started Apr 25 12:59:48 PM PDT 24
Finished Apr 25 12:59:51 PM PDT 24
Peak memory 215436 kb
Host smart-5de32b7e-9df3-4aba-945a-20702025900b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590453460 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3590453460
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1479664576
Short name T110
Test name
Test status
Simulation time 57109956 ps
CPU time 1.43 seconds
Started Apr 25 12:59:47 PM PDT 24
Finished Apr 25 12:59:50 PM PDT 24
Peak memory 216780 kb
Host smart-97e5ba3d-637a-43fe-afed-ea1ec76bfc93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479664576 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1479664576
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1250090112
Short name T731
Test name
Test status
Simulation time 21577256 ps
CPU time 1.04 seconds
Started Apr 25 12:59:54 PM PDT 24
Finished Apr 25 12:59:56 PM PDT 24
Peak memory 223820 kb
Host smart-50b8f5a1-917e-4fac-a59a-35c001572284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250090112 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1250090112
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3976310794
Short name T464
Test name
Test status
Simulation time 78143104 ps
CPU time 1.62 seconds
Started Apr 25 12:59:46 PM PDT 24
Finished Apr 25 12:59:49 PM PDT 24
Peak memory 218408 kb
Host smart-4fe83f3f-ee0f-4bab-a748-9b59b702292d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976310794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3976310794
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.272387898
Short name T411
Test name
Test status
Simulation time 21268092 ps
CPU time 1.09 seconds
Started Apr 25 12:59:50 PM PDT 24
Finished Apr 25 12:59:53 PM PDT 24
Peak memory 215344 kb
Host smart-7f51d885-2e80-4ee1-a39d-7510a8e0867c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272387898 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.272387898
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3308314592
Short name T777
Test name
Test status
Simulation time 28230885 ps
CPU time 0.91 seconds
Started Apr 25 01:00:02 PM PDT 24
Finished Apr 25 01:00:05 PM PDT 24
Peak memory 215172 kb
Host smart-95275f1b-11d9-40cb-9721-b884a04f7304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308314592 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3308314592
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.4139387607
Short name T592
Test name
Test status
Simulation time 912306801 ps
CPU time 4.99 seconds
Started Apr 25 01:00:00 PM PDT 24
Finished Apr 25 01:00:06 PM PDT 24
Peak memory 216952 kb
Host smart-494e12a2-150e-48b3-a7e5-27e2a672cc03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139387607 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.4139387607
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.4283807679
Short name T722
Test name
Test status
Simulation time 32753237232 ps
CPU time 469.76 seconds
Started Apr 25 12:59:40 PM PDT 24
Finished Apr 25 01:07:32 PM PDT 24
Peak memory 217516 kb
Host smart-8d758643-4174-40cc-ab6c-295976db954c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283807679 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.4283807679
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.3922456255
Short name T642
Test name
Test status
Simulation time 30547610 ps
CPU time 1.32 seconds
Started Apr 25 01:01:03 PM PDT 24
Finished Apr 25 01:01:05 PM PDT 24
Peak memory 219412 kb
Host smart-8957d124-9476-4b1b-8597-c82dfea91f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922456255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3922456255
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.1708875756
Short name T330
Test name
Test status
Simulation time 35712846 ps
CPU time 1.49 seconds
Started Apr 25 01:01:03 PM PDT 24
Finished Apr 25 01:01:05 PM PDT 24
Peak memory 218136 kb
Host smart-1e3ec8bf-7ca2-4eb6-8945-7656f6a31897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708875756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1708875756
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.3790542900
Short name T297
Test name
Test status
Simulation time 56901683 ps
CPU time 1.26 seconds
Started Apr 25 01:00:49 PM PDT 24
Finished Apr 25 01:00:52 PM PDT 24
Peak memory 218068 kb
Host smart-c4b1e0e2-7adc-4c1c-827d-9133833334c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790542900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3790542900
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.2032648099
Short name T647
Test name
Test status
Simulation time 31564402 ps
CPU time 1.3 seconds
Started Apr 25 01:01:11 PM PDT 24
Finished Apr 25 01:01:15 PM PDT 24
Peak memory 218216 kb
Host smart-714ae961-821d-4777-a58f-f4e649f002d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032648099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2032648099
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.3371833438
Short name T742
Test name
Test status
Simulation time 28513467 ps
CPU time 1.19 seconds
Started Apr 25 01:00:57 PM PDT 24
Finished Apr 25 01:01:00 PM PDT 24
Peak memory 216844 kb
Host smart-c6217c25-054b-4ef9-88c7-912731e7c3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371833438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3371833438
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2100853697
Short name T432
Test name
Test status
Simulation time 39588635 ps
CPU time 1.41 seconds
Started Apr 25 01:00:45 PM PDT 24
Finished Apr 25 01:00:50 PM PDT 24
Peak memory 218252 kb
Host smart-3787ced1-6156-4488-8056-cd87daccf956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100853697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2100853697
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.3962498893
Short name T451
Test name
Test status
Simulation time 80351789 ps
CPU time 1.01 seconds
Started Apr 25 01:02:06 PM PDT 24
Finished Apr 25 01:02:09 PM PDT 24
Peak memory 218416 kb
Host smart-d73c03c4-8979-4f17-bc6e-12bb55429902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962498893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3962498893
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.343827475
Short name T274
Test name
Test status
Simulation time 79018760 ps
CPU time 1.06 seconds
Started Apr 25 01:00:57 PM PDT 24
Finished Apr 25 01:01:00 PM PDT 24
Peak memory 216676 kb
Host smart-983801d3-57dc-448c-8396-6ad790112bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343827475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.343827475
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.3915167712
Short name T399
Test name
Test status
Simulation time 68114543 ps
CPU time 1 seconds
Started Apr 25 01:00:50 PM PDT 24
Finished Apr 25 01:00:54 PM PDT 24
Peak memory 213160 kb
Host smart-e029e716-c8b5-4eb6-8a4b-20226351e5b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915167712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3915167712
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3289080663
Short name T813
Test name
Test status
Simulation time 17932353 ps
CPU time 0.85 seconds
Started Apr 25 01:00:01 PM PDT 24
Finished Apr 25 01:00:03 PM PDT 24
Peak memory 215764 kb
Host smart-8ab8b2ab-5dce-4851-9169-285b165314fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289080663 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3289080663
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2925612435
Short name T161
Test name
Test status
Simulation time 23630281 ps
CPU time 1.03 seconds
Started Apr 25 12:59:58 PM PDT 24
Finished Apr 25 01:00:00 PM PDT 24
Peak memory 217760 kb
Host smart-e9eef63a-1587-40b7-98c4-6b8f9ac0909c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925612435 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2925612435
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1677029123
Short name T712
Test name
Test status
Simulation time 26902563 ps
CPU time 1.23 seconds
Started Apr 25 12:59:56 PM PDT 24
Finished Apr 25 12:59:58 PM PDT 24
Peak memory 217508 kb
Host smart-787ed5ce-061f-4923-907f-ed081009c5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677029123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1677029123
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1636813482
Short name T456
Test name
Test status
Simulation time 31267588 ps
CPU time 1.35 seconds
Started Apr 25 12:59:40 PM PDT 24
Finished Apr 25 12:59:43 PM PDT 24
Peak memory 219668 kb
Host smart-d0f465c6-a113-49a2-b0e3-6ca7d29ba143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636813482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1636813482
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1693190586
Short name T138
Test name
Test status
Simulation time 29598945 ps
CPU time 0.87 seconds
Started Apr 25 12:59:47 PM PDT 24
Finished Apr 25 12:59:50 PM PDT 24
Peak memory 215396 kb
Host smart-2a159f5e-5bea-4387-bbb5-7d895217ffee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693190586 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1693190586
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.4292654515
Short name T391
Test name
Test status
Simulation time 38550301 ps
CPU time 0.94 seconds
Started Apr 25 12:59:54 PM PDT 24
Finished Apr 25 12:59:57 PM PDT 24
Peak memory 215144 kb
Host smart-89ef1f76-8132-4ed2-b624-8f71ba035b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292654515 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.4292654515
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.336050125
Short name T761
Test name
Test status
Simulation time 112095119 ps
CPU time 2.49 seconds
Started Apr 25 12:59:48 PM PDT 24
Finished Apr 25 12:59:52 PM PDT 24
Peak memory 218196 kb
Host smart-6bceb564-2f68-4ddd-ba47-ed27536eb2dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336050125 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.336050125
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1815124575
Short name T468
Test name
Test status
Simulation time 65658707503 ps
CPU time 1179.66 seconds
Started Apr 25 12:59:40 PM PDT 24
Finished Apr 25 01:19:22 PM PDT 24
Peak memory 222816 kb
Host smart-65b4282e-ec27-42fe-a767-4eb378d681df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815124575 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1815124575
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.3865650785
Short name T431
Test name
Test status
Simulation time 53172100 ps
CPU time 0.96 seconds
Started Apr 25 01:02:14 PM PDT 24
Finished Apr 25 01:02:17 PM PDT 24
Peak memory 216772 kb
Host smart-2c55d1d5-22ff-4194-a61f-f35677bbdd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865650785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3865650785
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.1599397996
Short name T44
Test name
Test status
Simulation time 72232924 ps
CPU time 1.14 seconds
Started Apr 25 01:01:03 PM PDT 24
Finished Apr 25 01:01:06 PM PDT 24
Peak memory 217076 kb
Host smart-303fa066-d391-4796-a757-6d903daa6d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599397996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1599397996
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.2340305172
Short name T67
Test name
Test status
Simulation time 95071788 ps
CPU time 1.41 seconds
Started Apr 25 01:01:03 PM PDT 24
Finished Apr 25 01:01:06 PM PDT 24
Peak memory 218232 kb
Host smart-35742550-0afe-4abd-be98-e86aa9d0c13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340305172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2340305172
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.3109452574
Short name T324
Test name
Test status
Simulation time 72483007 ps
CPU time 2.35 seconds
Started Apr 25 01:00:52 PM PDT 24
Finished Apr 25 01:00:57 PM PDT 24
Peak memory 219344 kb
Host smart-10ef2e56-e849-4f84-bbdf-83a31bdf1951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109452574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3109452574
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.2124535340
Short name T444
Test name
Test status
Simulation time 184587523 ps
CPU time 1.08 seconds
Started Apr 25 01:00:42 PM PDT 24
Finished Apr 25 01:00:46 PM PDT 24
Peak memory 216808 kb
Host smart-f2564eee-1af9-4cfc-8c32-d41dcf2a9fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124535340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2124535340
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.1841935150
Short name T674
Test name
Test status
Simulation time 320926757 ps
CPU time 1.61 seconds
Started Apr 25 01:01:46 PM PDT 24
Finished Apr 25 01:01:50 PM PDT 24
Peak memory 216980 kb
Host smart-251b1e3c-cc45-45c0-a46f-83f2b4de0aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841935150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1841935150
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.3400042271
Short name T721
Test name
Test status
Simulation time 61537959 ps
CPU time 1.05 seconds
Started Apr 25 01:01:06 PM PDT 24
Finished Apr 25 01:01:08 PM PDT 24
Peak memory 216840 kb
Host smart-7c25f920-b828-4f78-91ae-4a1f8790bc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400042271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3400042271
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.3704116825
Short name T781
Test name
Test status
Simulation time 309731243 ps
CPU time 1.44 seconds
Started Apr 25 01:01:05 PM PDT 24
Finished Apr 25 01:01:08 PM PDT 24
Peak memory 218152 kb
Host smart-01d4e99c-9f38-4c11-967b-a927420b6252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704116825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3704116825
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.4183645651
Short name T350
Test name
Test status
Simulation time 54813502 ps
CPU time 1.47 seconds
Started Apr 25 01:00:58 PM PDT 24
Finished Apr 25 01:01:01 PM PDT 24
Peak memory 218224 kb
Host smart-64a235d0-3e7b-4240-a4b9-f6529a7f680c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183645651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.4183645651
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.207667490
Short name T148
Test name
Test status
Simulation time 72921915 ps
CPU time 1.42 seconds
Started Apr 25 01:01:03 PM PDT 24
Finished Apr 25 01:01:06 PM PDT 24
Peak memory 216952 kb
Host smart-8b20ab3b-1fc2-442a-a507-6af8b5770b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207667490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.207667490
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2193365496
Short name T117
Test name
Test status
Simulation time 45214371 ps
CPU time 1.15 seconds
Started Apr 25 01:00:01 PM PDT 24
Finished Apr 25 01:00:03 PM PDT 24
Peak memory 215552 kb
Host smart-d2fe8662-d21f-4da7-b507-5c3f99a022f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193365496 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2193365496
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2235369222
Short name T563
Test name
Test status
Simulation time 186049187 ps
CPU time 0.92 seconds
Started Apr 25 01:00:05 PM PDT 24
Finished Apr 25 01:00:08 PM PDT 24
Peak memory 214744 kb
Host smart-75322f5b-58b1-4ec6-a2b4-26fe678f7739
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235369222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2235369222
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.3792735268
Short name T164
Test name
Test status
Simulation time 23378300 ps
CPU time 0.9 seconds
Started Apr 25 12:59:50 PM PDT 24
Finished Apr 25 12:59:52 PM PDT 24
Peak memory 215980 kb
Host smart-3ee3cd56-b559-4161-9efa-e8518c29021f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792735268 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3792735268
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3714998949
Short name T88
Test name
Test status
Simulation time 49497710 ps
CPU time 0.95 seconds
Started Apr 25 12:59:46 PM PDT 24
Finished Apr 25 12:59:49 PM PDT 24
Peak memory 216584 kb
Host smart-84ee9ed6-2d9a-4ad8-a1fa-e5e9f5bc6a97
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714998949 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3714998949
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.412693343
Short name T811
Test name
Test status
Simulation time 18765718 ps
CPU time 1.03 seconds
Started Apr 25 12:59:50 PM PDT 24
Finished Apr 25 12:59:53 PM PDT 24
Peak memory 217996 kb
Host smart-2bbcd850-4346-47b8-96f6-0ab0443866ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412693343 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.412693343
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1730916594
Short name T472
Test name
Test status
Simulation time 66590795 ps
CPU time 1.13 seconds
Started Apr 25 12:59:56 PM PDT 24
Finished Apr 25 12:59:58 PM PDT 24
Peak memory 216952 kb
Host smart-76219ebf-8506-42c9-81d9-4c31541c4c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730916594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1730916594
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3097604515
Short name T299
Test name
Test status
Simulation time 22550991 ps
CPU time 1.09 seconds
Started Apr 25 12:59:56 PM PDT 24
Finished Apr 25 12:59:58 PM PDT 24
Peak memory 215284 kb
Host smart-6d17c1a2-ec93-4531-95d1-41476a407751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097604515 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3097604515
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.483813560
Short name T139
Test name
Test status
Simulation time 49626943 ps
CPU time 0.95 seconds
Started Apr 25 12:59:52 PM PDT 24
Finished Apr 25 12:59:54 PM PDT 24
Peak memory 215192 kb
Host smart-c342d301-18ac-427c-9ca8-458d437af89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483813560 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.483813560
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.4066304517
Short name T570
Test name
Test status
Simulation time 216359549 ps
CPU time 1.54 seconds
Started Apr 25 01:01:08 PM PDT 24
Finished Apr 25 01:01:11 PM PDT 24
Peak memory 215016 kb
Host smart-85771188-b6ab-459c-a724-8c8b6c33e1b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066304517 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.4066304517
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.915056401
Short name T199
Test name
Test status
Simulation time 141123100746 ps
CPU time 900.94 seconds
Started Apr 25 01:00:08 PM PDT 24
Finished Apr 25 01:15:15 PM PDT 24
Peak memory 223488 kb
Host smart-71a86d3b-3e01-45eb-937e-5d147fc6355a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915056401 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.915056401
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.1319407046
Short name T791
Test name
Test status
Simulation time 71435748 ps
CPU time 1.28 seconds
Started Apr 25 01:01:03 PM PDT 24
Finished Apr 25 01:01:05 PM PDT 24
Peak memory 219456 kb
Host smart-ea750a7c-8d26-420b-9bbf-7d9ee8b1771e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319407046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1319407046
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.2063279837
Short name T607
Test name
Test status
Simulation time 121795902 ps
CPU time 1.28 seconds
Started Apr 25 01:01:02 PM PDT 24
Finished Apr 25 01:01:04 PM PDT 24
Peak memory 216840 kb
Host smart-9dce4e81-bc58-4ebe-b0c4-740d2ff87085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063279837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2063279837
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.997199668
Short name T603
Test name
Test status
Simulation time 40601084 ps
CPU time 1.57 seconds
Started Apr 25 01:01:00 PM PDT 24
Finished Apr 25 01:01:03 PM PDT 24
Peak memory 218236 kb
Host smart-e770ea8e-f090-47c7-8bae-3ac2b41ce1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997199668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.997199668
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.1852778102
Short name T393
Test name
Test status
Simulation time 66119109 ps
CPU time 1.53 seconds
Started Apr 25 01:01:00 PM PDT 24
Finished Apr 25 01:01:03 PM PDT 24
Peak memory 216968 kb
Host smart-07612aa0-2119-4793-acd4-bca7c1a9a798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852778102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1852778102
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.1961680184
Short name T293
Test name
Test status
Simulation time 169493701 ps
CPU time 2.59 seconds
Started Apr 25 01:01:02 PM PDT 24
Finished Apr 25 01:01:05 PM PDT 24
Peak memory 219464 kb
Host smart-9818a646-d581-4539-9ba8-35a770315c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961680184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1961680184
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.4021320468
Short name T551
Test name
Test status
Simulation time 173542948 ps
CPU time 1.07 seconds
Started Apr 25 01:01:04 PM PDT 24
Finished Apr 25 01:01:06 PM PDT 24
Peak memory 215148 kb
Host smart-d03cde30-a73d-4d61-8974-d3e0812943a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021320468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.4021320468
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.2637149142
Short name T804
Test name
Test status
Simulation time 184651984 ps
CPU time 1.47 seconds
Started Apr 25 01:00:55 PM PDT 24
Finished Apr 25 01:00:59 PM PDT 24
Peak memory 218712 kb
Host smart-e4baf835-d6bd-4530-9324-1cf4776214ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637149142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2637149142
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.2174373253
Short name T764
Test name
Test status
Simulation time 50128578 ps
CPU time 1.39 seconds
Started Apr 25 01:01:28 PM PDT 24
Finished Apr 25 01:01:31 PM PDT 24
Peak memory 218276 kb
Host smart-4a729061-01b0-49c2-b85c-42322ad2c451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174373253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2174373253
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.1284158809
Short name T659
Test name
Test status
Simulation time 176034071 ps
CPU time 1.43 seconds
Started Apr 25 01:00:50 PM PDT 24
Finished Apr 25 01:00:54 PM PDT 24
Peak memory 218508 kb
Host smart-69b933f0-3f88-4a0e-ac53-705fdecff04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284158809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1284158809
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3459555050
Short name T286
Test name
Test status
Simulation time 50312949 ps
CPU time 1.19 seconds
Started Apr 25 12:59:37 PM PDT 24
Finished Apr 25 12:59:40 PM PDT 24
Peak memory 215504 kb
Host smart-a2e68f2c-ac60-45b8-acdd-6364a9518d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459555050 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3459555050
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.1269447569
Short name T648
Test name
Test status
Simulation time 60529829 ps
CPU time 0.87 seconds
Started Apr 25 12:59:45 PM PDT 24
Finished Apr 25 12:59:48 PM PDT 24
Peak memory 206760 kb
Host smart-cb4305f1-c601-417f-aeee-e8663297ba13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269447569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1269447569
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2344934315
Short name T462
Test name
Test status
Simulation time 14449292 ps
CPU time 0.82 seconds
Started Apr 25 12:59:29 PM PDT 24
Finished Apr 25 12:59:31 PM PDT 24
Peak memory 215220 kb
Host smart-4975d69a-7505-47e5-b502-5a4762d5f592
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344934315 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2344934315
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.243307338
Short name T649
Test name
Test status
Simulation time 37562321 ps
CPU time 1.21 seconds
Started Apr 25 12:59:44 PM PDT 24
Finished Apr 25 12:59:48 PM PDT 24
Peak memory 218156 kb
Host smart-6b021b56-716f-408c-a279-645d0afef53b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243307338 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.243307338
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.371337217
Short name T86
Test name
Test status
Simulation time 25173000 ps
CPU time 1.25 seconds
Started Apr 25 12:59:34 PM PDT 24
Finished Apr 25 12:59:37 PM PDT 24
Peak memory 229452 kb
Host smart-e46c4af4-695a-4dbc-a174-d0d546f6576f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371337217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.371337217
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1301384021
Short name T641
Test name
Test status
Simulation time 62792973 ps
CPU time 1.24 seconds
Started Apr 25 12:59:42 PM PDT 24
Finished Apr 25 12:59:45 PM PDT 24
Peak memory 218308 kb
Host smart-8e560358-eedc-434f-b412-2b56a8c68996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301384021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1301384021
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.1075406335
Short name T285
Test name
Test status
Simulation time 21614450 ps
CPU time 0.9 seconds
Started Apr 25 12:59:24 PM PDT 24
Finished Apr 25 12:59:26 PM PDT 24
Peak memory 206916 kb
Host smart-591f1fcc-627a-49fe-8e8c-769e1c22fb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075406335 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1075406335
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.3177283551
Short name T351
Test name
Test status
Simulation time 40689530 ps
CPU time 0.95 seconds
Started Apr 25 12:59:37 PM PDT 24
Finished Apr 25 12:59:40 PM PDT 24
Peak memory 215128 kb
Host smart-6635945a-d38e-4f2d-b6ab-0e1e4033a7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177283551 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3177283551
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2755863466
Short name T41
Test name
Test status
Simulation time 27856497947 ps
CPU time 733.53 seconds
Started Apr 25 12:59:28 PM PDT 24
Finished Apr 25 01:11:43 PM PDT 24
Peak memory 218128 kb
Host smart-b9da014f-b67d-4ee8-8d76-85cc2f1023ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755863466 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2755863466
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.285621953
Short name T624
Test name
Test status
Simulation time 53191586 ps
CPU time 1.27 seconds
Started Apr 25 12:59:50 PM PDT 24
Finished Apr 25 12:59:53 PM PDT 24
Peak memory 215552 kb
Host smart-8fa241df-fbd1-4925-8d0b-4ac306826b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285621953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.285621953
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.4097031868
Short name T767
Test name
Test status
Simulation time 13106700 ps
CPU time 0.93 seconds
Started Apr 25 01:00:01 PM PDT 24
Finished Apr 25 01:00:04 PM PDT 24
Peak memory 206524 kb
Host smart-5afccd77-490b-47bb-8b7b-bca3680373af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097031868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.4097031868
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1021387098
Short name T163
Test name
Test status
Simulation time 40909676 ps
CPU time 0.87 seconds
Started Apr 25 12:59:59 PM PDT 24
Finished Apr 25 01:00:02 PM PDT 24
Peak memory 216180 kb
Host smart-808e6f4b-c0ce-43f6-8a15-50b67ab78a6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021387098 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1021387098
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.804604323
Short name T483
Test name
Test status
Simulation time 21814603 ps
CPU time 1.06 seconds
Started Apr 25 12:59:57 PM PDT 24
Finished Apr 25 01:00:00 PM PDT 24
Peak memory 216740 kb
Host smart-eb3cbc93-2220-42c7-8171-8b962f30ef79
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804604323 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.804604323
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1219429233
Short name T424
Test name
Test status
Simulation time 21467804 ps
CPU time 1.1 seconds
Started Apr 25 01:01:08 PM PDT 24
Finished Apr 25 01:01:11 PM PDT 24
Peak memory 218108 kb
Host smart-2bab3601-0e7f-446c-8368-2ed225f127d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219429233 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1219429233
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.273921691
Short name T763
Test name
Test status
Simulation time 47522894 ps
CPU time 1.21 seconds
Started Apr 25 01:00:50 PM PDT 24
Finished Apr 25 01:00:54 PM PDT 24
Peak memory 216384 kb
Host smart-4b2e040e-8d65-4db6-9071-3f1bdc7a45d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273921691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.273921691
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3251917480
Short name T575
Test name
Test status
Simulation time 25680392 ps
CPU time 1.02 seconds
Started Apr 25 01:00:04 PM PDT 24
Finished Apr 25 01:00:07 PM PDT 24
Peak memory 215296 kb
Host smart-0f76df06-b4a4-4fbb-a1a3-2372a7acb0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251917480 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3251917480
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.4155954888
Short name T368
Test name
Test status
Simulation time 14504593 ps
CPU time 0.99 seconds
Started Apr 25 01:00:50 PM PDT 24
Finished Apr 25 01:00:54 PM PDT 24
Peak memory 213224 kb
Host smart-794f4484-aff9-43d7-be33-dc6040c57c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155954888 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.4155954888
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3521069527
Short name T343
Test name
Test status
Simulation time 431848292 ps
CPU time 4.86 seconds
Started Apr 25 01:00:01 PM PDT 24
Finished Apr 25 01:00:07 PM PDT 24
Peak memory 215208 kb
Host smart-f1920d84-4853-408c-b1e1-97e041de3069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521069527 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3521069527
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1608290074
Short name T345
Test name
Test status
Simulation time 246715313121 ps
CPU time 835.73 seconds
Started Apr 25 01:00:03 PM PDT 24
Finished Apr 25 01:14:01 PM PDT 24
Peak memory 222392 kb
Host smart-a049934f-b8cd-4dcc-9784-ab779f972ccc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608290074 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1608290074
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2696227660
Short name T266
Test name
Test status
Simulation time 43800498 ps
CPU time 1.21 seconds
Started Apr 25 01:01:06 PM PDT 24
Finished Apr 25 01:01:08 PM PDT 24
Peak memory 219432 kb
Host smart-da5fe9b9-dd28-4fe0-a986-f235cc22e142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696227660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2696227660
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2851160524
Short name T273
Test name
Test status
Simulation time 70136302 ps
CPU time 1.17 seconds
Started Apr 25 01:01:08 PM PDT 24
Finished Apr 25 01:01:10 PM PDT 24
Peak memory 215152 kb
Host smart-12f5d26e-2251-441b-b6fb-6ae143c36707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851160524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2851160524
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1770763269
Short name T599
Test name
Test status
Simulation time 58181872 ps
CPU time 1.09 seconds
Started Apr 25 01:01:00 PM PDT 24
Finished Apr 25 01:01:03 PM PDT 24
Peak memory 216784 kb
Host smart-f6b1980b-2ccf-4f9a-a2da-945e0af01375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770763269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1770763269
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.635907270
Short name T359
Test name
Test status
Simulation time 51599797 ps
CPU time 1.39 seconds
Started Apr 25 01:01:20 PM PDT 24
Finished Apr 25 01:01:24 PM PDT 24
Peak memory 218344 kb
Host smart-020c97f9-8fbc-4275-a546-cc63b9a0ebda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635907270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.635907270
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.96600088
Short name T357
Test name
Test status
Simulation time 32345689 ps
CPU time 1.3 seconds
Started Apr 25 01:01:10 PM PDT 24
Finished Apr 25 01:01:13 PM PDT 24
Peak memory 218020 kb
Host smart-e2bea6ba-cf03-4a1c-b6f0-f52ddd8a57a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96600088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.96600088
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.149658376
Short name T240
Test name
Test status
Simulation time 72994604 ps
CPU time 1.01 seconds
Started Apr 25 01:01:12 PM PDT 24
Finished Apr 25 01:01:16 PM PDT 24
Peak memory 216804 kb
Host smart-ee010f8d-4364-42a6-b61f-bbf960e23bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149658376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.149658376
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3249710180
Short name T696
Test name
Test status
Simulation time 113649563 ps
CPU time 1.39 seconds
Started Apr 25 01:00:58 PM PDT 24
Finished Apr 25 01:01:01 PM PDT 24
Peak memory 217944 kb
Host smart-a2562557-1985-4a6c-94e4-4719c85d6b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249710180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3249710180
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3793251282
Short name T673
Test name
Test status
Simulation time 34131389 ps
CPU time 1.53 seconds
Started Apr 25 01:01:04 PM PDT 24
Finished Apr 25 01:01:08 PM PDT 24
Peak memory 216896 kb
Host smart-24529864-99e0-4241-9ad8-872627fb4bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793251282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3793251282
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2955816493
Short name T347
Test name
Test status
Simulation time 42812046 ps
CPU time 1.03 seconds
Started Apr 25 01:01:16 PM PDT 24
Finished Apr 25 01:01:19 PM PDT 24
Peak memory 216932 kb
Host smart-2633fb48-6ecb-4683-9f43-2dfefa9fc278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955816493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2955816493
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3179777247
Short name T476
Test name
Test status
Simulation time 182941704 ps
CPU time 1.31 seconds
Started Apr 25 01:00:03 PM PDT 24
Finished Apr 25 01:00:06 PM PDT 24
Peak memory 215468 kb
Host smart-bf630b52-6a0c-43df-8156-c9e5c15a548e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179777247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3179777247
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.4290755257
Short name T374
Test name
Test status
Simulation time 19533661 ps
CPU time 0.96 seconds
Started Apr 25 01:00:07 PM PDT 24
Finished Apr 25 01:00:12 PM PDT 24
Peak memory 215060 kb
Host smart-28d00e5b-251c-4356-948d-fbc52fc208ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290755257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.4290755257
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3029823287
Short name T209
Test name
Test status
Simulation time 26471957 ps
CPU time 0.85 seconds
Started Apr 25 01:01:14 PM PDT 24
Finished Apr 25 01:01:17 PM PDT 24
Peak memory 215640 kb
Host smart-57b38a34-dfd5-4fdc-a7d6-e650c9e8d0ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029823287 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3029823287
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.574224174
Short name T109
Test name
Test status
Simulation time 131423770 ps
CPU time 1 seconds
Started Apr 25 12:59:51 PM PDT 24
Finished Apr 25 12:59:54 PM PDT 24
Peak memory 216856 kb
Host smart-630a6b02-908b-4d69-8d92-883c0d9ab67f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574224174 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.574224174
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.1351606118
Short name T121
Test name
Test status
Simulation time 20405332 ps
CPU time 1.19 seconds
Started Apr 25 12:59:48 PM PDT 24
Finished Apr 25 12:59:51 PM PDT 24
Peak memory 223960 kb
Host smart-a44aa168-75a1-4dac-b5e7-a28e35be1a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351606118 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1351606118
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.193925266
Short name T338
Test name
Test status
Simulation time 44644414 ps
CPU time 1.16 seconds
Started Apr 25 01:01:23 PM PDT 24
Finished Apr 25 01:01:25 PM PDT 24
Peak memory 216780 kb
Host smart-ab9c3f4b-40d1-489f-8003-8219d95434e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193925266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.193925266
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2628646757
Short name T587
Test name
Test status
Simulation time 22148417 ps
CPU time 1.14 seconds
Started Apr 25 12:59:48 PM PDT 24
Finished Apr 25 12:59:51 PM PDT 24
Peak memory 223808 kb
Host smart-4336642b-6c50-4501-9808-42704f9cb088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628646757 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2628646757
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1185242718
Short name T694
Test name
Test status
Simulation time 16903881 ps
CPU time 0.96 seconds
Started Apr 25 12:59:57 PM PDT 24
Finished Apr 25 01:00:00 PM PDT 24
Peak memory 215148 kb
Host smart-0bcfab35-562b-4205-a779-3537dcc3029c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185242718 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1185242718
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.885499108
Short name T527
Test name
Test status
Simulation time 282102794 ps
CPU time 1.95 seconds
Started Apr 25 01:01:25 PM PDT 24
Finished Apr 25 01:01:28 PM PDT 24
Peak memory 216872 kb
Host smart-148833c1-6aa2-4de8-be85-7534824c5d40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885499108 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.885499108
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2300301696
Short name T142
Test name
Test status
Simulation time 572009462740 ps
CPU time 1703.29 seconds
Started Apr 25 01:00:04 PM PDT 24
Finished Apr 25 01:28:30 PM PDT 24
Peak memory 227800 kb
Host smart-61fb71a4-2283-4183-8f83-6c1f7282e535
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300301696 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2300301696
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3103167847
Short name T547
Test name
Test status
Simulation time 96694115 ps
CPU time 1.07 seconds
Started Apr 25 01:00:55 PM PDT 24
Finished Apr 25 01:00:58 PM PDT 24
Peak memory 216904 kb
Host smart-1152ed5f-1507-4e4c-985b-9440802490b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103167847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3103167847
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1883036921
Short name T752
Test name
Test status
Simulation time 81024531 ps
CPU time 2.84 seconds
Started Apr 25 01:00:53 PM PDT 24
Finished Apr 25 01:00:58 PM PDT 24
Peak memory 218216 kb
Host smart-01d7a2c1-99e1-45bd-8415-13f6c9ea39a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883036921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1883036921
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.558697191
Short name T514
Test name
Test status
Simulation time 42261935 ps
CPU time 1.16 seconds
Started Apr 25 01:01:11 PM PDT 24
Finished Apr 25 01:01:15 PM PDT 24
Peak memory 216968 kb
Host smart-d5cc8546-abcf-4470-a60e-adecc43aba77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558697191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.558697191
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.365193242
Short name T361
Test name
Test status
Simulation time 195428653 ps
CPU time 3.03 seconds
Started Apr 25 01:01:33 PM PDT 24
Finished Apr 25 01:01:37 PM PDT 24
Peak memory 217220 kb
Host smart-2bd4c1b2-6cfc-4427-81ce-a0398415a9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365193242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.365193242
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2070195075
Short name T549
Test name
Test status
Simulation time 27320098 ps
CPU time 1.33 seconds
Started Apr 25 01:00:57 PM PDT 24
Finished Apr 25 01:01:00 PM PDT 24
Peak memory 218172 kb
Host smart-fc11d2aa-834d-44e8-86a8-b200d287623e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070195075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2070195075
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2186806798
Short name T765
Test name
Test status
Simulation time 54229391 ps
CPU time 1.54 seconds
Started Apr 25 01:01:28 PM PDT 24
Finished Apr 25 01:01:31 PM PDT 24
Peak memory 216796 kb
Host smart-5443eb65-036a-4883-80c6-7f02b353e56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186806798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2186806798
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1908916454
Short name T705
Test name
Test status
Simulation time 44292455 ps
CPU time 1.68 seconds
Started Apr 25 01:01:12 PM PDT 24
Finished Apr 25 01:01:17 PM PDT 24
Peak memory 217004 kb
Host smart-7e8faa88-e496-494b-b59f-d020b564cf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908916454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1908916454
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2220081729
Short name T681
Test name
Test status
Simulation time 112678769 ps
CPU time 1.13 seconds
Started Apr 25 01:01:17 PM PDT 24
Finished Apr 25 01:01:20 PM PDT 24
Peak memory 217036 kb
Host smart-67aa4fb6-7ec9-45be-ad57-a6edfd989dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220081729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2220081729
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3364200614
Short name T466
Test name
Test status
Simulation time 26249865 ps
CPU time 1.25 seconds
Started Apr 25 01:00:55 PM PDT 24
Finished Apr 25 01:00:58 PM PDT 24
Peak memory 217060 kb
Host smart-9d1f50ff-f81f-4f29-83fe-c17607f6a056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364200614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3364200614
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1404393779
Short name T30
Test name
Test status
Simulation time 255682457 ps
CPU time 1.28 seconds
Started Apr 25 01:01:08 PM PDT 24
Finished Apr 25 01:01:11 PM PDT 24
Peak memory 215320 kb
Host smart-c472a408-7287-47c5-b945-68834d60d0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404393779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1404393779
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1456786962
Short name T601
Test name
Test status
Simulation time 25448386 ps
CPU time 0.9 seconds
Started Apr 25 12:59:52 PM PDT 24
Finished Apr 25 12:59:54 PM PDT 24
Peak memory 214668 kb
Host smart-3abfcf3a-b8ce-40b5-affe-5ce79fac65c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456786962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1456786962
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.669994430
Short name T589
Test name
Test status
Simulation time 25720853 ps
CPU time 0.81 seconds
Started Apr 25 12:59:48 PM PDT 24
Finished Apr 25 12:59:51 PM PDT 24
Peak memory 215736 kb
Host smart-3d3cb91b-5ab3-4e9b-a1ee-571c8e768e4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669994430 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.669994430
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3769130331
Short name T553
Test name
Test status
Simulation time 48165656 ps
CPU time 1.12 seconds
Started Apr 25 12:59:55 PM PDT 24
Finished Apr 25 12:59:57 PM PDT 24
Peak memory 216632 kb
Host smart-ccab05c4-cda3-47f1-826b-ace5e5fe1907
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769130331 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3769130331
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1434993244
Short name T832
Test name
Test status
Simulation time 19082255 ps
CPU time 1.04 seconds
Started Apr 25 12:59:48 PM PDT 24
Finished Apr 25 12:59:51 PM PDT 24
Peak memory 223932 kb
Host smart-29da7a2a-533d-469c-84c2-723f04eb4a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434993244 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1434993244
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2322916649
Short name T569
Test name
Test status
Simulation time 51964699 ps
CPU time 1.59 seconds
Started Apr 25 01:01:20 PM PDT 24
Finished Apr 25 01:01:24 PM PDT 24
Peak memory 218048 kb
Host smart-219c2752-a656-4aca-aced-57dca8c3e57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322916649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2322916649
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.4091326740
Short name T13
Test name
Test status
Simulation time 48471373 ps
CPU time 0.96 seconds
Started Apr 25 12:59:52 PM PDT 24
Finished Apr 25 12:59:54 PM PDT 24
Peak memory 223740 kb
Host smart-0d1dd4db-1a22-41ba-b030-d8c3cc12908c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091326740 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.4091326740
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2061872920
Short name T349
Test name
Test status
Simulation time 20407922 ps
CPU time 1.05 seconds
Started Apr 25 01:00:04 PM PDT 24
Finished Apr 25 01:00:07 PM PDT 24
Peak memory 215136 kb
Host smart-a0209be7-45ba-4a73-b357-03fab6f71117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061872920 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2061872920
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2257453538
Short name T525
Test name
Test status
Simulation time 286944541 ps
CPU time 1.97 seconds
Started Apr 25 01:01:10 PM PDT 24
Finished Apr 25 01:01:15 PM PDT 24
Peak memory 215044 kb
Host smart-e0fad4df-6ff9-41c1-94e7-8acf3abfd299
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257453538 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2257453538
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2336911202
Short name T191
Test name
Test status
Simulation time 11823043492 ps
CPU time 272.9 seconds
Started Apr 25 12:59:58 PM PDT 24
Finished Apr 25 01:04:42 PM PDT 24
Peak memory 217788 kb
Host smart-1318cf23-673a-40b7-9114-12aa1459354a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336911202 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2336911202
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/221.edn_genbits.513430536
Short name T147
Test name
Test status
Simulation time 42576739 ps
CPU time 1.51 seconds
Started Apr 25 01:01:10 PM PDT 24
Finished Apr 25 01:01:14 PM PDT 24
Peak memory 218028 kb
Host smart-261e4b01-b537-462d-b382-03079a7c8a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513430536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.513430536
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2481666598
Short name T770
Test name
Test status
Simulation time 89508535 ps
CPU time 1.37 seconds
Started Apr 25 01:00:57 PM PDT 24
Finished Apr 25 01:01:00 PM PDT 24
Peak memory 219500 kb
Host smart-a28c7c56-a0eb-448f-b907-7bfc703101fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481666598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2481666598
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2724860585
Short name T783
Test name
Test status
Simulation time 68644373 ps
CPU time 1.21 seconds
Started Apr 25 01:01:07 PM PDT 24
Finished Apr 25 01:01:10 PM PDT 24
Peak memory 218240 kb
Host smart-32ebcb34-06af-40d8-aaf2-9d78600343f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724860585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2724860585
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2203697635
Short name T257
Test name
Test status
Simulation time 43571815 ps
CPU time 1.64 seconds
Started Apr 25 01:01:10 PM PDT 24
Finished Apr 25 01:01:14 PM PDT 24
Peak memory 217956 kb
Host smart-696925d0-fb87-4fcc-9196-3cb205d3234e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203697635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2203697635
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3882666762
Short name T830
Test name
Test status
Simulation time 60729478 ps
CPU time 1.33 seconds
Started Apr 25 01:01:09 PM PDT 24
Finished Apr 25 01:01:12 PM PDT 24
Peak memory 218200 kb
Host smart-9781e159-91c1-4581-87d8-55cccf3860cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882666762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3882666762
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3850248212
Short name T837
Test name
Test status
Simulation time 66899023 ps
CPU time 1.53 seconds
Started Apr 25 01:01:19 PM PDT 24
Finished Apr 25 01:01:23 PM PDT 24
Peak memory 218576 kb
Host smart-4e24ae31-e0d5-43ec-a3fd-a95b72627b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850248212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3850248212
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1284625350
Short name T370
Test name
Test status
Simulation time 95146079 ps
CPU time 1.12 seconds
Started Apr 25 01:01:18 PM PDT 24
Finished Apr 25 01:01:22 PM PDT 24
Peak memory 217004 kb
Host smart-ed8e6f0c-97ff-4fcc-a32e-83e581fb78ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284625350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1284625350
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2296941243
Short name T775
Test name
Test status
Simulation time 91882834 ps
CPU time 1.15 seconds
Started Apr 25 01:01:07 PM PDT 24
Finished Apr 25 01:01:10 PM PDT 24
Peak memory 217984 kb
Host smart-53c9a705-27ef-403b-a388-8403ad774fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296941243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2296941243
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.468554082
Short name T679
Test name
Test status
Simulation time 61355157 ps
CPU time 2.18 seconds
Started Apr 25 01:01:11 PM PDT 24
Finished Apr 25 01:01:16 PM PDT 24
Peak memory 219708 kb
Host smart-b32ac739-eb7e-4e16-9aed-1a7553b2e956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468554082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.468554082
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1179591259
Short name T665
Test name
Test status
Simulation time 23255868 ps
CPU time 1.12 seconds
Started Apr 25 01:00:03 PM PDT 24
Finished Apr 25 01:00:06 PM PDT 24
Peak memory 215576 kb
Host smart-080f199b-2be7-4b6a-84a4-5eef80ca87d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179591259 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1179591259
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.4133328453
Short name T358
Test name
Test status
Simulation time 13626436 ps
CPU time 0.89 seconds
Started Apr 25 12:59:57 PM PDT 24
Finished Apr 25 12:59:59 PM PDT 24
Peak memory 206560 kb
Host smart-5b759c0f-b882-4156-941a-0635ad6fd790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133328453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.4133328453
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.952280078
Short name T381
Test name
Test status
Simulation time 11327228 ps
CPU time 0.88 seconds
Started Apr 25 01:00:55 PM PDT 24
Finished Apr 25 01:00:58 PM PDT 24
Peak memory 216004 kb
Host smart-f6f4c49b-9a7a-49b3-855c-63247431eb79
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952280078 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.952280078
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.4009121875
Short name T132
Test name
Test status
Simulation time 20366891 ps
CPU time 0.96 seconds
Started Apr 25 01:00:19 PM PDT 24
Finished Apr 25 01:00:22 PM PDT 24
Peak memory 218432 kb
Host smart-f53fc1b6-e273-4223-b968-c934e846f81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009121875 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.4009121875
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3551928456
Short name T660
Test name
Test status
Simulation time 82734704 ps
CPU time 1.23 seconds
Started Apr 25 01:00:02 PM PDT 24
Finished Apr 25 01:00:06 PM PDT 24
Peak memory 219364 kb
Host smart-80a32436-4e2e-41d5-a31d-d902be30e343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551928456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3551928456
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.955522596
Short name T543
Test name
Test status
Simulation time 41351293 ps
CPU time 0.88 seconds
Started Apr 25 12:59:59 PM PDT 24
Finished Apr 25 01:00:02 PM PDT 24
Peak memory 215308 kb
Host smart-e65e6e53-4296-49df-93f6-433c4e174a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955522596 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.955522596
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.946444018
Short name T789
Test name
Test status
Simulation time 16715205 ps
CPU time 0.98 seconds
Started Apr 25 12:59:58 PM PDT 24
Finished Apr 25 01:00:00 PM PDT 24
Peak memory 215168 kb
Host smart-ce5acb1a-2b66-4086-8cb3-99c6ac99b1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946444018 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.946444018
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.4209938722
Short name T597
Test name
Test status
Simulation time 313130314 ps
CPU time 2.52 seconds
Started Apr 25 01:00:19 PM PDT 24
Finished Apr 25 01:00:24 PM PDT 24
Peak memory 216688 kb
Host smart-83fe78b6-4e4d-4cad-b5aa-4a1dae1cff62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209938722 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.4209938722
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2672266972
Short name T834
Test name
Test status
Simulation time 25456847969 ps
CPU time 543.78 seconds
Started Apr 25 01:00:00 PM PDT 24
Finished Apr 25 01:09:05 PM PDT 24
Peak memory 217716 kb
Host smart-24ce78a6-fc8e-4371-a6db-f9b407ec6b3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672266972 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2672266972
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1969521603
Short name T467
Test name
Test status
Simulation time 83491350 ps
CPU time 1.14 seconds
Started Apr 25 01:01:08 PM PDT 24
Finished Apr 25 01:01:10 PM PDT 24
Peak memory 217084 kb
Host smart-e5101082-4050-4a2e-ac1b-d04ba4f94027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969521603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1969521603
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.291365589
Short name T344
Test name
Test status
Simulation time 128635898 ps
CPU time 1.09 seconds
Started Apr 25 01:01:09 PM PDT 24
Finished Apr 25 01:01:11 PM PDT 24
Peak memory 216924 kb
Host smart-47249bb2-d726-4e08-bc6c-b1f59707fd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291365589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.291365589
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1933284989
Short name T518
Test name
Test status
Simulation time 76631979 ps
CPU time 1.31 seconds
Started Apr 25 01:01:21 PM PDT 24
Finished Apr 25 01:01:25 PM PDT 24
Peak memory 218340 kb
Host smart-01e62fde-dc01-4d30-9ddf-43b4b59b9294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933284989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1933284989
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3687351680
Short name T353
Test name
Test status
Simulation time 57004047 ps
CPU time 1.29 seconds
Started Apr 25 01:01:05 PM PDT 24
Finished Apr 25 01:01:07 PM PDT 24
Peak memory 218244 kb
Host smart-0ba1e502-a36f-4627-8764-56d938331c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687351680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3687351680
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2717485382
Short name T644
Test name
Test status
Simulation time 51634934 ps
CPU time 1.2 seconds
Started Apr 25 01:01:10 PM PDT 24
Finished Apr 25 01:01:13 PM PDT 24
Peak memory 217992 kb
Host smart-d17eb6ea-9f93-423d-a8be-fe1c234bfbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717485382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2717485382
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1332275990
Short name T313
Test name
Test status
Simulation time 59292987 ps
CPU time 1.62 seconds
Started Apr 25 01:01:17 PM PDT 24
Finished Apr 25 01:01:20 PM PDT 24
Peak memory 218352 kb
Host smart-38a1b59a-38c6-435a-9909-31c2e5cd4575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332275990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1332275990
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3841133746
Short name T758
Test name
Test status
Simulation time 40325441 ps
CPU time 1.37 seconds
Started Apr 25 01:01:03 PM PDT 24
Finished Apr 25 01:01:06 PM PDT 24
Peak memory 218232 kb
Host smart-32df93f5-bd01-4078-8aed-0f8812d0d377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841133746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3841133746
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.674423408
Short name T392
Test name
Test status
Simulation time 83540596 ps
CPU time 1.47 seconds
Started Apr 25 01:01:10 PM PDT 24
Finished Apr 25 01:01:13 PM PDT 24
Peak memory 216772 kb
Host smart-2a69fb32-1795-4930-a8e7-a80489f43b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674423408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.674423408
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2945259938
Short name T511
Test name
Test status
Simulation time 80464020 ps
CPU time 1.18 seconds
Started Apr 25 01:01:05 PM PDT 24
Finished Apr 25 01:01:07 PM PDT 24
Peak memory 218312 kb
Host smart-9773996d-f777-4c4f-9de2-ab5eab297e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945259938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2945259938
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1637509101
Short name T70
Test name
Test status
Simulation time 41410424 ps
CPU time 1.52 seconds
Started Apr 25 01:01:13 PM PDT 24
Finished Apr 25 01:01:17 PM PDT 24
Peak memory 216700 kb
Host smart-340c53f8-5b68-4e0e-bf12-203af9056fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637509101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1637509101
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3100675441
Short name T422
Test name
Test status
Simulation time 37723423 ps
CPU time 1.16 seconds
Started Apr 25 12:59:57 PM PDT 24
Finished Apr 25 01:00:00 PM PDT 24
Peak memory 215484 kb
Host smart-11c6d1e5-d1ff-4587-99f3-fd896e104ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100675441 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3100675441
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2321277594
Short name T772
Test name
Test status
Simulation time 72910189 ps
CPU time 0.85 seconds
Started Apr 25 01:00:02 PM PDT 24
Finished Apr 25 01:00:06 PM PDT 24
Peak memory 206488 kb
Host smart-26787e87-35c5-42ad-8dd6-3f197051753b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321277594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2321277594
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2261574469
Short name T348
Test name
Test status
Simulation time 12870820 ps
CPU time 0.9 seconds
Started Apr 25 01:00:42 PM PDT 24
Finished Apr 25 01:00:46 PM PDT 24
Peak memory 216032 kb
Host smart-eb95f457-678a-4feb-9db6-5f96a8dcd4ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261574469 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2261574469
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.2646709561
Short name T113
Test name
Test status
Simulation time 28290641 ps
CPU time 0.87 seconds
Started Apr 25 01:00:05 PM PDT 24
Finished Apr 25 01:00:09 PM PDT 24
Peak memory 218208 kb
Host smart-e8442bc3-8011-427b-b273-02e1e4965a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646709561 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2646709561
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.92612151
Short name T362
Test name
Test status
Simulation time 56130998 ps
CPU time 1.17 seconds
Started Apr 25 12:59:59 PM PDT 24
Finished Apr 25 01:00:01 PM PDT 24
Peak memory 217076 kb
Host smart-e74297e3-a36d-44fe-bfa2-f8f9cadea01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92612151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.92612151
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_smoke.2539080480
Short name T465
Test name
Test status
Simulation time 76691668 ps
CPU time 0.91 seconds
Started Apr 25 12:59:57 PM PDT 24
Finished Apr 25 12:59:58 PM PDT 24
Peak memory 215144 kb
Host smart-63825bb9-207a-4d9c-bc99-44df7f1f8567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539080480 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2539080480
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3249930027
Short name T47
Test name
Test status
Simulation time 874333493 ps
CPU time 4.52 seconds
Started Apr 25 01:00:03 PM PDT 24
Finished Apr 25 01:00:10 PM PDT 24
Peak memory 216708 kb
Host smart-6eb41324-19f8-4945-8dfa-a5c46fc06c71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249930027 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3249930027
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2395836013
Short name T396
Test name
Test status
Simulation time 123505611487 ps
CPU time 806.36 seconds
Started Apr 25 01:00:05 PM PDT 24
Finished Apr 25 01:13:34 PM PDT 24
Peak memory 221216 kb
Host smart-b0f33eff-4e01-46ac-a79f-8101af0c9c38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395836013 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2395836013
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.98746026
Short name T490
Test name
Test status
Simulation time 46407481 ps
CPU time 1.76 seconds
Started Apr 25 01:01:11 PM PDT 24
Finished Apr 25 01:01:15 PM PDT 24
Peak memory 218072 kb
Host smart-57cef573-f484-4491-9074-fcfa1a655430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98746026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.98746026
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.879007414
Short name T631
Test name
Test status
Simulation time 99802495 ps
CPU time 1.35 seconds
Started Apr 25 01:00:59 PM PDT 24
Finished Apr 25 01:01:02 PM PDT 24
Peak memory 218476 kb
Host smart-976a87b4-5f96-421e-9a4c-4d8209194213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879007414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.879007414
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.70058616
Short name T463
Test name
Test status
Simulation time 57566447 ps
CPU time 1.3 seconds
Started Apr 25 01:01:02 PM PDT 24
Finished Apr 25 01:01:04 PM PDT 24
Peak memory 216772 kb
Host smart-000794d8-68e5-4a31-bf9c-f0fcd1df393f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70058616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.70058616
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.4246305227
Short name T492
Test name
Test status
Simulation time 70428367 ps
CPU time 1.08 seconds
Started Apr 25 01:01:09 PM PDT 24
Finished Apr 25 01:01:11 PM PDT 24
Peak memory 218060 kb
Host smart-072b1cf7-c23a-469d-bd87-3a9a554224c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246305227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.4246305227
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3309180260
Short name T604
Test name
Test status
Simulation time 216067106 ps
CPU time 3.07 seconds
Started Apr 25 01:01:15 PM PDT 24
Finished Apr 25 01:01:21 PM PDT 24
Peak memory 218320 kb
Host smart-9eb02331-fddc-462e-a317-12dc208635ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309180260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3309180260
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2489850713
Short name T412
Test name
Test status
Simulation time 43695090 ps
CPU time 1.28 seconds
Started Apr 25 01:01:14 PM PDT 24
Finished Apr 25 01:01:18 PM PDT 24
Peak memory 218312 kb
Host smart-60c88a24-fb45-4d79-9dd0-02a18466ff44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489850713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2489850713
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1791402246
Short name T697
Test name
Test status
Simulation time 46359701 ps
CPU time 1.05 seconds
Started Apr 25 01:01:17 PM PDT 24
Finished Apr 25 01:01:20 PM PDT 24
Peak memory 216852 kb
Host smart-91c0b9db-ee4f-476e-9f79-a486016d0eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791402246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1791402246
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.672182839
Short name T838
Test name
Test status
Simulation time 63803506 ps
CPU time 1.6 seconds
Started Apr 25 01:01:21 PM PDT 24
Finished Apr 25 01:01:24 PM PDT 24
Peak memory 219536 kb
Host smart-6e1d57f8-e9c2-49df-b5cc-e15c4bb7b3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672182839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.672182839
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1381565923
Short name T438
Test name
Test status
Simulation time 34443216 ps
CPU time 1.3 seconds
Started Apr 25 01:01:38 PM PDT 24
Finished Apr 25 01:01:40 PM PDT 24
Peak memory 216908 kb
Host smart-67e5f9f0-589e-47b6-bfba-e77e3dfab79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381565923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1381565923
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1087914005
Short name T371
Test name
Test status
Simulation time 220354163 ps
CPU time 2.39 seconds
Started Apr 25 01:01:12 PM PDT 24
Finished Apr 25 01:01:18 PM PDT 24
Peak memory 219708 kb
Host smart-c4dcbcad-d88c-45f9-b8ff-2e9e5e7bd22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087914005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1087914005
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1932528399
Short name T291
Test name
Test status
Simulation time 41227447 ps
CPU time 1.19 seconds
Started Apr 25 12:59:50 PM PDT 24
Finished Apr 25 12:59:53 PM PDT 24
Peak memory 215512 kb
Host smart-cd80ac37-1799-4681-8565-014295300152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932528399 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1932528399
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1230578162
Short name T484
Test name
Test status
Simulation time 13785098 ps
CPU time 0.87 seconds
Started Apr 25 01:00:00 PM PDT 24
Finished Apr 25 01:00:09 PM PDT 24
Peak memory 206976 kb
Host smart-e05a2d6d-1c15-461e-bb0d-0cbd4f48b8ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230578162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1230578162
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3360031341
Short name T111
Test name
Test status
Simulation time 12477686 ps
CPU time 0.88 seconds
Started Apr 25 12:59:57 PM PDT 24
Finished Apr 25 12:59:59 PM PDT 24
Peak memory 215456 kb
Host smart-c6aae0a7-598b-4efc-88ac-348b010ebea1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360031341 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3360031341
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3353616031
Short name T819
Test name
Test status
Simulation time 104935070 ps
CPU time 1.11 seconds
Started Apr 25 12:59:58 PM PDT 24
Finished Apr 25 01:00:00 PM PDT 24
Peak memory 216888 kb
Host smart-7cde7b5f-c183-401d-bd8c-ff7e1ed024ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353616031 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3353616031
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.883452910
Short name T550
Test name
Test status
Simulation time 20187986 ps
CPU time 0.93 seconds
Started Apr 25 01:00:15 PM PDT 24
Finished Apr 25 01:00:19 PM PDT 24
Peak memory 217980 kb
Host smart-d7dec5d3-bb0a-4c2a-bc40-9d42cafc4eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883452910 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.883452910
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2710895696
Short name T782
Test name
Test status
Simulation time 93975778 ps
CPU time 1.31 seconds
Started Apr 25 01:00:24 PM PDT 24
Finished Apr 25 01:00:26 PM PDT 24
Peak memory 216852 kb
Host smart-ee1876cf-d313-47ac-9d00-de7db5037946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710895696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2710895696
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1120015476
Short name T703
Test name
Test status
Simulation time 20449358 ps
CPU time 1.27 seconds
Started Apr 25 01:00:28 PM PDT 24
Finished Apr 25 01:00:31 PM PDT 24
Peak memory 223904 kb
Host smart-81373f68-7ab0-44e8-b507-46905dd2997a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120015476 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1120015476
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1842076662
Short name T64
Test name
Test status
Simulation time 33033067 ps
CPU time 0.9 seconds
Started Apr 25 01:00:04 PM PDT 24
Finished Apr 25 01:00:07 PM PDT 24
Peak memory 215136 kb
Host smart-1ca89b1a-3bf8-46a7-9c12-cd56444fa7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842076662 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1842076662
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.925789580
Short name T632
Test name
Test status
Simulation time 934313967 ps
CPU time 3.58 seconds
Started Apr 25 01:00:25 PM PDT 24
Finished Apr 25 01:00:30 PM PDT 24
Peak memory 219824 kb
Host smart-47c2955a-8539-4942-a15f-9585933368a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925789580 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.925789580
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1413229744
Short name T195
Test name
Test status
Simulation time 641883323419 ps
CPU time 1104.64 seconds
Started Apr 25 01:00:12 PM PDT 24
Finished Apr 25 01:18:45 PM PDT 24
Peak memory 221912 kb
Host smart-9104ff55-908c-47c1-8e01-1bf126045817
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413229744 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1413229744
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2979456520
Short name T580
Test name
Test status
Simulation time 247935506 ps
CPU time 3.55 seconds
Started Apr 25 01:01:21 PM PDT 24
Finished Apr 25 01:01:27 PM PDT 24
Peak memory 219876 kb
Host smart-e7653069-da92-4961-8928-aa92e9836adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979456520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2979456520
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1012406224
Short name T477
Test name
Test status
Simulation time 40224241 ps
CPU time 1.37 seconds
Started Apr 25 01:01:23 PM PDT 24
Finished Apr 25 01:01:26 PM PDT 24
Peak memory 218048 kb
Host smart-809a6dc1-1628-4729-aa87-a9430549c7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012406224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1012406224
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.15253886
Short name T636
Test name
Test status
Simulation time 60003284 ps
CPU time 1.27 seconds
Started Apr 25 01:01:15 PM PDT 24
Finished Apr 25 01:01:19 PM PDT 24
Peak memory 217996 kb
Host smart-c2ce0821-1a2c-429e-8983-87bd46f05a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15253886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.15253886
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.4040444078
Short name T473
Test name
Test status
Simulation time 173587869 ps
CPU time 2.45 seconds
Started Apr 25 01:01:18 PM PDT 24
Finished Apr 25 01:01:22 PM PDT 24
Peak memory 219556 kb
Host smart-33fd03b9-aed9-4b97-ad4e-aabade040d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040444078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.4040444078
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1906588170
Short name T329
Test name
Test status
Simulation time 43790407 ps
CPU time 1.23 seconds
Started Apr 25 01:01:28 PM PDT 24
Finished Apr 25 01:01:31 PM PDT 24
Peak memory 217948 kb
Host smart-ec08bc84-4df5-49a9-9e6e-a5d07565457a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906588170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1906588170
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1309156682
Short name T748
Test name
Test status
Simulation time 169092803 ps
CPU time 1.25 seconds
Started Apr 25 01:01:12 PM PDT 24
Finished Apr 25 01:01:16 PM PDT 24
Peak memory 219628 kb
Host smart-e6352fd7-a482-4016-9a3f-e73fbb6de6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309156682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1309156682
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1969496873
Short name T509
Test name
Test status
Simulation time 32960005 ps
CPU time 1.22 seconds
Started Apr 25 01:01:43 PM PDT 24
Finished Apr 25 01:01:45 PM PDT 24
Peak memory 216860 kb
Host smart-75b0b7b3-5e5c-4507-aee2-0c4648fa506b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969496873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1969496873
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2347471012
Short name T143
Test name
Test status
Simulation time 74606171 ps
CPU time 1.38 seconds
Started Apr 25 01:01:14 PM PDT 24
Finished Apr 25 01:01:19 PM PDT 24
Peak memory 218436 kb
Host smart-3d19bb6b-f2e4-4e4d-8516-fc3141d6f32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347471012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2347471012
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1177064359
Short name T261
Test name
Test status
Simulation time 197740339 ps
CPU time 2.92 seconds
Started Apr 25 01:01:08 PM PDT 24
Finished Apr 25 01:01:12 PM PDT 24
Peak memory 219764 kb
Host smart-32cb9789-6333-4b31-a4cd-cf198f3d5e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177064359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1177064359
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1021799943
Short name T719
Test name
Test status
Simulation time 78768282 ps
CPU time 1.34 seconds
Started Apr 25 01:01:12 PM PDT 24
Finished Apr 25 01:01:16 PM PDT 24
Peak memory 218372 kb
Host smart-d3d9e9d8-e629-4c17-ac3c-8068d2dbc3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021799943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1021799943
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1673790608
Short name T242
Test name
Test status
Simulation time 91621759 ps
CPU time 1.27 seconds
Started Apr 25 01:00:05 PM PDT 24
Finished Apr 25 01:00:10 PM PDT 24
Peak memory 215496 kb
Host smart-641e92a8-7ff7-4176-8a7c-c1a509c2f8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673790608 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1673790608
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2487619946
Short name T305
Test name
Test status
Simulation time 24784036 ps
CPU time 1.02 seconds
Started Apr 25 12:59:59 PM PDT 24
Finished Apr 25 01:00:02 PM PDT 24
Peak memory 206556 kb
Host smart-9834e4bb-9186-49e7-9b43-f237022d19c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487619946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2487619946
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3225647695
Short name T126
Test name
Test status
Simulation time 147044650 ps
CPU time 0.94 seconds
Started Apr 25 01:00:08 PM PDT 24
Finished Apr 25 01:00:15 PM PDT 24
Peak memory 216228 kb
Host smart-1b72cea4-a39b-4ce4-8fe0-0a1ae54732c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225647695 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3225647695
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2780544887
Short name T617
Test name
Test status
Simulation time 57041957 ps
CPU time 1.17 seconds
Started Apr 25 01:00:10 PM PDT 24
Finished Apr 25 01:00:16 PM PDT 24
Peak memory 216632 kb
Host smart-d98939f9-bdee-4c00-9d49-c8ce33cfbe18
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780544887 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2780544887
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2042428645
Short name T542
Test name
Test status
Simulation time 30668746 ps
CPU time 1.02 seconds
Started Apr 25 01:00:05 PM PDT 24
Finished Apr 25 01:00:09 PM PDT 24
Peak memory 219436 kb
Host smart-e3bceec9-900b-4970-b36a-d9811c5c376d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042428645 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2042428645
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3834421638
Short name T296
Test name
Test status
Simulation time 36888534 ps
CPU time 1.45 seconds
Started Apr 25 01:00:11 PM PDT 24
Finished Apr 25 01:00:17 PM PDT 24
Peak memory 216968 kb
Host smart-b731469e-84ec-46ea-a1ba-fd7272e12ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834421638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3834421638
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.438553236
Short name T773
Test name
Test status
Simulation time 27138089 ps
CPU time 0.97 seconds
Started Apr 25 01:00:09 PM PDT 24
Finished Apr 25 01:00:15 PM PDT 24
Peak memory 215320 kb
Host smart-de6cc0c7-15cf-4a2f-ac04-1acf968fbe3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438553236 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.438553236
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2059585343
Short name T734
Test name
Test status
Simulation time 67868019 ps
CPU time 0.88 seconds
Started Apr 25 01:00:02 PM PDT 24
Finished Apr 25 01:00:06 PM PDT 24
Peak memory 215164 kb
Host smart-7a56da55-40d2-411d-8a28-072cc1f418a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059585343 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2059585343
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1572366682
Short name T454
Test name
Test status
Simulation time 326104443 ps
CPU time 3.35 seconds
Started Apr 25 01:00:06 PM PDT 24
Finished Apr 25 01:00:13 PM PDT 24
Peak memory 215216 kb
Host smart-fb1cdecc-fb66-4b87-95cd-0757b1aab774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572366682 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1572366682
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.923950360
Short name T198
Test name
Test status
Simulation time 113751531152 ps
CPU time 1753.68 seconds
Started Apr 25 01:00:02 PM PDT 24
Finished Apr 25 01:29:18 PM PDT 24
Peak memory 224452 kb
Host smart-7af4934e-ee1e-4c2f-ad1e-e31678ff7909
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923950360 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.923950360
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1948968420
Short name T400
Test name
Test status
Simulation time 41555653 ps
CPU time 1.55 seconds
Started Apr 25 01:01:28 PM PDT 24
Finished Apr 25 01:01:30 PM PDT 24
Peak memory 217032 kb
Host smart-c52a0387-472a-431c-b5f1-553345ee6d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948968420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1948968420
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.928346242
Short name T241
Test name
Test status
Simulation time 45448760 ps
CPU time 1.17 seconds
Started Apr 25 01:01:14 PM PDT 24
Finished Apr 25 01:01:18 PM PDT 24
Peak memory 216836 kb
Host smart-a90e20be-c1a9-4da7-957c-4973949908c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928346242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.928346242
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3114563891
Short name T730
Test name
Test status
Simulation time 86377063 ps
CPU time 1.15 seconds
Started Apr 25 01:01:15 PM PDT 24
Finished Apr 25 01:01:19 PM PDT 24
Peak memory 218344 kb
Host smart-430a3511-8fbf-4c6c-939d-ede0e04318db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114563891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3114563891
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.4170643614
Short name T784
Test name
Test status
Simulation time 70530442 ps
CPU time 1.51 seconds
Started Apr 25 01:01:12 PM PDT 24
Finished Apr 25 01:01:16 PM PDT 24
Peak memory 218176 kb
Host smart-6eea3932-ec92-4a09-a27f-5e2ad20ef7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170643614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.4170643614
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.882733865
Short name T816
Test name
Test status
Simulation time 126886433 ps
CPU time 2.65 seconds
Started Apr 25 01:01:03 PM PDT 24
Finished Apr 25 01:01:08 PM PDT 24
Peak memory 219980 kb
Host smart-90866976-63c7-4f03-a469-bfd946c630bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882733865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.882733865
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.1669223379
Short name T778
Test name
Test status
Simulation time 96358477 ps
CPU time 1.54 seconds
Started Apr 25 01:01:11 PM PDT 24
Finished Apr 25 01:01:16 PM PDT 24
Peak memory 218320 kb
Host smart-6e064e89-d53c-446c-af5d-d1c2dd46eb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669223379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1669223379
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1400997443
Short name T637
Test name
Test status
Simulation time 94374948 ps
CPU time 1.3 seconds
Started Apr 25 01:01:32 PM PDT 24
Finished Apr 25 01:01:34 PM PDT 24
Peak memory 218388 kb
Host smart-7bf06249-7884-40fd-aae6-5e7c941b5979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400997443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1400997443
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3133567000
Short name T416
Test name
Test status
Simulation time 49442540 ps
CPU time 1.36 seconds
Started Apr 25 01:01:09 PM PDT 24
Finished Apr 25 01:01:12 PM PDT 24
Peak memory 218148 kb
Host smart-09398cce-7b8f-4511-8372-ccb65b375835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133567000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3133567000
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2856781531
Short name T320
Test name
Test status
Simulation time 41309410 ps
CPU time 1.12 seconds
Started Apr 25 01:01:28 PM PDT 24
Finished Apr 25 01:01:31 PM PDT 24
Peak memory 218092 kb
Host smart-12b6119a-7045-4d7e-844b-07ba932852f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856781531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2856781531
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.750973398
Short name T818
Test name
Test status
Simulation time 30971349 ps
CPU time 1.49 seconds
Started Apr 25 01:01:19 PM PDT 24
Finished Apr 25 01:01:23 PM PDT 24
Peak memory 218012 kb
Host smart-585ebed8-f331-4868-9903-59663a461288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750973398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.750973398
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1907073463
Short name T149
Test name
Test status
Simulation time 27498239 ps
CPU time 1.25 seconds
Started Apr 25 01:00:11 PM PDT 24
Finished Apr 25 01:00:16 PM PDT 24
Peak memory 215548 kb
Host smart-3bb73b98-7a89-4c8d-a61c-c18e6d692760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907073463 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1907073463
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3671078093
Short name T398
Test name
Test status
Simulation time 54093394 ps
CPU time 0.96 seconds
Started Apr 25 12:59:57 PM PDT 24
Finished Apr 25 01:00:00 PM PDT 24
Peak memory 206540 kb
Host smart-b44f8174-98bb-497b-a416-5f1bdd3a5994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671078093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3671078093
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1023755099
Short name T622
Test name
Test status
Simulation time 32461206 ps
CPU time 0.81 seconds
Started Apr 25 01:00:12 PM PDT 24
Finished Apr 25 01:00:17 PM PDT 24
Peak memory 216096 kb
Host smart-d5811a91-e5d5-4893-94da-973864c35223
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023755099 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1023755099
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.610035704
Short name T634
Test name
Test status
Simulation time 37583630 ps
CPU time 1.24 seconds
Started Apr 25 01:00:00 PM PDT 24
Finished Apr 25 01:00:02 PM PDT 24
Peak memory 216656 kb
Host smart-d35efb8d-ed47-4099-8303-7435f0271d31
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610035704 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.610035704
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.4288360990
Short name T170
Test name
Test status
Simulation time 34434029 ps
CPU time 1.36 seconds
Started Apr 25 01:00:17 PM PDT 24
Finished Apr 25 01:00:22 PM PDT 24
Peak memory 219472 kb
Host smart-ee04a2a3-42b8-4ec2-9662-82c550b85828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288360990 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.4288360990
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1840649933
Short name T254
Test name
Test status
Simulation time 68511665 ps
CPU time 1.23 seconds
Started Apr 25 01:00:12 PM PDT 24
Finished Apr 25 01:00:17 PM PDT 24
Peak memory 218256 kb
Host smart-fc610e69-963a-4fc9-8170-e701c5e3c40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840649933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1840649933
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.177073859
Short name T771
Test name
Test status
Simulation time 107051561 ps
CPU time 0.98 seconds
Started Apr 25 01:00:18 PM PDT 24
Finished Apr 25 01:00:21 PM PDT 24
Peak memory 223712 kb
Host smart-7b611396-b08a-4753-bd3c-8995fd643d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177073859 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.177073859
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3956840191
Short name T317
Test name
Test status
Simulation time 17599095 ps
CPU time 0.94 seconds
Started Apr 25 01:00:02 PM PDT 24
Finished Apr 25 01:00:06 PM PDT 24
Peak memory 215152 kb
Host smart-5bd1229c-9c8e-46d3-a8b9-23f9110b9b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956840191 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3956840191
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1346964292
Short name T4
Test name
Test status
Simulation time 154890862 ps
CPU time 2.02 seconds
Started Apr 25 01:00:00 PM PDT 24
Finished Apr 25 01:00:07 PM PDT 24
Peak memory 215184 kb
Host smart-6b2daca0-57b3-4434-bdf0-a08347fc95bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346964292 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1346964292
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3919709152
Short name T594
Test name
Test status
Simulation time 34795708102 ps
CPU time 872.99 seconds
Started Apr 25 12:59:57 PM PDT 24
Finished Apr 25 01:14:32 PM PDT 24
Peak memory 219152 kb
Host smart-6c96928c-0ddf-4dbd-830f-9e8f26b49bc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919709152 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3919709152
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2691520539
Short name T365
Test name
Test status
Simulation time 53919811 ps
CPU time 2.32 seconds
Started Apr 25 01:01:19 PM PDT 24
Finished Apr 25 01:01:24 PM PDT 24
Peak memory 216996 kb
Host smart-d5c25c45-52fa-40eb-890a-553c55daef7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691520539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2691520539
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.4061403975
Short name T522
Test name
Test status
Simulation time 266172280 ps
CPU time 3.9 seconds
Started Apr 25 01:01:19 PM PDT 24
Finished Apr 25 01:01:25 PM PDT 24
Peak memory 217276 kb
Host smart-bb62d43c-7345-40a2-b73e-73535c9dfeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061403975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.4061403975
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3596794385
Short name T528
Test name
Test status
Simulation time 68975859 ps
CPU time 1.67 seconds
Started Apr 25 01:01:16 PM PDT 24
Finished Apr 25 01:01:20 PM PDT 24
Peak memory 218364 kb
Host smart-d56c21a6-527d-4d05-84b7-d7c3c2f0dfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596794385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3596794385
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1173857733
Short name T433
Test name
Test status
Simulation time 116504504 ps
CPU time 2.38 seconds
Started Apr 25 01:01:27 PM PDT 24
Finished Apr 25 01:01:30 PM PDT 24
Peak memory 219568 kb
Host smart-691fce53-e141-4fad-9752-dd93613db445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173857733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1173857733
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1379804803
Short name T341
Test name
Test status
Simulation time 95563837 ps
CPU time 1.13 seconds
Started Apr 25 01:01:07 PM PDT 24
Finished Apr 25 01:01:09 PM PDT 24
Peak memory 216792 kb
Host smart-8380b1b2-cca0-47fa-9f5c-013536061cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379804803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1379804803
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2897054976
Short name T309
Test name
Test status
Simulation time 225637313 ps
CPU time 3.33 seconds
Started Apr 25 01:01:18 PM PDT 24
Finished Apr 25 01:01:23 PM PDT 24
Peak memory 219620 kb
Host smart-3a34d49c-943a-4a7b-823a-d9889ba66c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897054976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2897054976
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3571032281
Short name T342
Test name
Test status
Simulation time 47084389 ps
CPU time 1.48 seconds
Started Apr 25 01:01:19 PM PDT 24
Finished Apr 25 01:01:23 PM PDT 24
Peak memory 216968 kb
Host smart-af689041-2d93-44f2-8e35-d9f3c9eab536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571032281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3571032281
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3716062339
Short name T340
Test name
Test status
Simulation time 106440462 ps
CPU time 1.43 seconds
Started Apr 25 01:01:12 PM PDT 24
Finished Apr 25 01:01:17 PM PDT 24
Peak memory 219916 kb
Host smart-83df3a0a-078d-41ac-8c22-2114ab21d3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716062339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3716062339
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.3002827926
Short name T585
Test name
Test status
Simulation time 65585748 ps
CPU time 0.88 seconds
Started Apr 25 01:00:04 PM PDT 24
Finished Apr 25 01:00:07 PM PDT 24
Peak memory 215000 kb
Host smart-7b5626f1-dd90-4f6f-9f74-42772b4b3482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002827926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3002827926
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1542197686
Short name T104
Test name
Test status
Simulation time 143030805 ps
CPU time 1.13 seconds
Started Apr 25 01:00:13 PM PDT 24
Finished Apr 25 01:00:18 PM PDT 24
Peak memory 216848 kb
Host smart-c1b90983-9126-4c84-9a95-aeb7ce0252b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542197686 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1542197686
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_genbits.3690451779
Short name T428
Test name
Test status
Simulation time 123837219 ps
CPU time 1.34 seconds
Started Apr 25 01:00:12 PM PDT 24
Finished Apr 25 01:00:18 PM PDT 24
Peak memory 216788 kb
Host smart-5eb2c5a4-bbf4-43f8-b0c8-62f4e99bd914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690451779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3690451779
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2629699730
Short name T146
Test name
Test status
Simulation time 54247153 ps
CPU time 0.86 seconds
Started Apr 25 01:00:05 PM PDT 24
Finished Apr 25 01:00:09 PM PDT 24
Peak memory 215012 kb
Host smart-c97e9efa-78cb-4ae5-816c-9b67bcd3a11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629699730 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2629699730
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2388506870
Short name T312
Test name
Test status
Simulation time 20443332 ps
CPU time 0.98 seconds
Started Apr 25 01:00:16 PM PDT 24
Finished Apr 25 01:00:20 PM PDT 24
Peak memory 215168 kb
Host smart-c06eb93b-5570-4938-ba6c-bc9a5dd424bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388506870 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2388506870
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3342127998
Short name T508
Test name
Test status
Simulation time 402122659 ps
CPU time 4.58 seconds
Started Apr 25 01:00:17 PM PDT 24
Finished Apr 25 01:00:25 PM PDT 24
Peak memory 216856 kb
Host smart-08a77ac7-7a20-4324-8756-23ef362b5825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342127998 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3342127998
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/280.edn_genbits.1013747614
Short name T628
Test name
Test status
Simulation time 135642409 ps
CPU time 1.74 seconds
Started Apr 25 01:01:36 PM PDT 24
Finished Apr 25 01:01:39 PM PDT 24
Peak memory 218124 kb
Host smart-cd08ea6f-3d64-479c-a6fe-b2491b51a1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013747614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1013747614
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1427751391
Short name T496
Test name
Test status
Simulation time 84911472 ps
CPU time 1.25 seconds
Started Apr 25 01:01:21 PM PDT 24
Finished Apr 25 01:01:25 PM PDT 24
Peak memory 216932 kb
Host smart-97befe10-7a29-4945-8f04-f3ee6554f4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427751391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1427751391
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3624270373
Short name T73
Test name
Test status
Simulation time 85989252 ps
CPU time 1.18 seconds
Started Apr 25 01:01:23 PM PDT 24
Finished Apr 25 01:01:26 PM PDT 24
Peak memory 216724 kb
Host smart-c832620c-6546-42bc-9cf5-07fda58e0661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624270373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3624270373
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3397768112
Short name T277
Test name
Test status
Simulation time 145867519 ps
CPU time 1.78 seconds
Started Apr 25 01:01:07 PM PDT 24
Finished Apr 25 01:01:10 PM PDT 24
Peak memory 218616 kb
Host smart-937eed14-c7be-40f0-b6c1-63692ca31698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397768112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3397768112
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2103831824
Short name T22
Test name
Test status
Simulation time 51722055 ps
CPU time 1.11 seconds
Started Apr 25 01:01:11 PM PDT 24
Finished Apr 25 01:01:15 PM PDT 24
Peak memory 216800 kb
Host smart-378890f7-b7ca-47af-82ec-bf4629b81931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103831824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2103831824
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3945037822
Short name T76
Test name
Test status
Simulation time 78039844 ps
CPU time 0.98 seconds
Started Apr 25 01:01:14 PM PDT 24
Finished Apr 25 01:01:21 PM PDT 24
Peak memory 216836 kb
Host smart-5747a880-c6df-49d7-bb4f-1f63cbef551a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945037822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3945037822
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3504352870
Short name T386
Test name
Test status
Simulation time 47558605 ps
CPU time 1.21 seconds
Started Apr 25 01:01:27 PM PDT 24
Finished Apr 25 01:01:29 PM PDT 24
Peak memory 217028 kb
Host smart-e1f6284f-ccfb-4da5-abaf-6a26c8afb4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504352870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3504352870
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2398386679
Short name T42
Test name
Test status
Simulation time 39264495 ps
CPU time 1.58 seconds
Started Apr 25 01:01:31 PM PDT 24
Finished Apr 25 01:01:34 PM PDT 24
Peak memory 217132 kb
Host smart-e41c77a4-db46-49d5-afc4-4c066e023207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398386679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2398386679
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3759224798
Short name T307
Test name
Test status
Simulation time 109415503 ps
CPU time 1.22 seconds
Started Apr 25 01:01:22 PM PDT 24
Finished Apr 25 01:01:25 PM PDT 24
Peak memory 218128 kb
Host smart-a15d6230-5d54-43f5-853a-0cb8e164d87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759224798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3759224798
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1216600282
Short name T469
Test name
Test status
Simulation time 77763907 ps
CPU time 2 seconds
Started Apr 25 01:01:25 PM PDT 24
Finished Apr 25 01:01:28 PM PDT 24
Peak memory 219852 kb
Host smart-eeb03271-14ba-4e7b-8a14-c0cdb596adce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216600282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1216600282
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert_test.365052137
Short name T532
Test name
Test status
Simulation time 22245365 ps
CPU time 0.86 seconds
Started Apr 25 01:00:11 PM PDT 24
Finished Apr 25 01:00:16 PM PDT 24
Peak memory 206768 kb
Host smart-491eeabd-4bff-4a34-b51a-15879d864300
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365052137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.365052137
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2779413954
Short name T167
Test name
Test status
Simulation time 113477856 ps
CPU time 0.84 seconds
Started Apr 25 01:00:17 PM PDT 24
Finished Apr 25 01:00:20 PM PDT 24
Peak memory 216160 kb
Host smart-b2b93023-d901-4106-aaee-42e48997b0ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779413954 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2779413954
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.3721446499
Short name T554
Test name
Test status
Simulation time 37285491 ps
CPU time 1.01 seconds
Started Apr 25 01:00:19 PM PDT 24
Finished Apr 25 01:00:23 PM PDT 24
Peak memory 223708 kb
Host smart-9a86711b-45c8-4ee0-82e4-1162b242e369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721446499 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3721446499
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.4031858195
Short name T475
Test name
Test status
Simulation time 106607920 ps
CPU time 1.55 seconds
Started Apr 25 12:59:59 PM PDT 24
Finished Apr 25 01:00:03 PM PDT 24
Peak memory 218564 kb
Host smart-54823ebd-d7be-4a3e-a6c9-a47e8f58a35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031858195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.4031858195
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.1610965434
Short name T625
Test name
Test status
Simulation time 36631170 ps
CPU time 0.87 seconds
Started Apr 25 01:00:18 PM PDT 24
Finished Apr 25 01:00:21 PM PDT 24
Peak memory 215200 kb
Host smart-2f0a44ad-3f9a-4d22-9bdf-f0176ad91786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610965434 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1610965434
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3992371987
Short name T559
Test name
Test status
Simulation time 129900203 ps
CPU time 1 seconds
Started Apr 25 01:00:36 PM PDT 24
Finished Apr 25 01:00:41 PM PDT 24
Peak memory 215172 kb
Host smart-edd9105a-78bd-492d-bb45-24af6be8f523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992371987 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3992371987
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.874281302
Short name T534
Test name
Test status
Simulation time 559089563 ps
CPU time 2.97 seconds
Started Apr 25 01:00:18 PM PDT 24
Finished Apr 25 01:00:24 PM PDT 24
Peak memory 216784 kb
Host smart-d5d47e02-39ce-4037-9d74-cbc6ab3ceee7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874281302 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.874281302
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.197460798
Short name T192
Test name
Test status
Simulation time 19673354575 ps
CPU time 431.25 seconds
Started Apr 25 01:00:12 PM PDT 24
Finished Apr 25 01:07:27 PM PDT 24
Peak memory 218244 kb
Host smart-3334b87f-b9a0-4da7-815e-c77c757951eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197460798 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.197460798
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.4037172871
Short name T264
Test name
Test status
Simulation time 17960918 ps
CPU time 1.09 seconds
Started Apr 25 01:01:22 PM PDT 24
Finished Apr 25 01:01:25 PM PDT 24
Peak memory 218108 kb
Host smart-36da397f-4235-404e-b4ea-13a98e81f05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037172871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.4037172871
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3923631899
Short name T557
Test name
Test status
Simulation time 106403393 ps
CPU time 1.43 seconds
Started Apr 25 01:01:06 PM PDT 24
Finished Apr 25 01:01:08 PM PDT 24
Peak memory 218316 kb
Host smart-c8e69d95-3cd3-4269-9355-990722647eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923631899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3923631899
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3313659567
Short name T405
Test name
Test status
Simulation time 33874319 ps
CPU time 1.26 seconds
Started Apr 25 01:01:19 PM PDT 24
Finished Apr 25 01:01:22 PM PDT 24
Peak memory 216744 kb
Host smart-9556f25a-cb25-4780-a68a-f8d926bea2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313659567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3313659567
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1394305035
Short name T27
Test name
Test status
Simulation time 61465837 ps
CPU time 1.61 seconds
Started Apr 25 01:01:12 PM PDT 24
Finished Apr 25 01:01:16 PM PDT 24
Peak memory 218468 kb
Host smart-a3469b74-e5d1-4441-91a1-c768d6c104fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394305035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1394305035
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1367124850
Short name T807
Test name
Test status
Simulation time 90628876 ps
CPU time 1.05 seconds
Started Apr 25 01:01:03 PM PDT 24
Finished Apr 25 01:01:06 PM PDT 24
Peak memory 218116 kb
Host smart-71d326a1-9c34-4de5-becb-ecc294b87650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367124850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1367124850
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1492544149
Short name T626
Test name
Test status
Simulation time 33801807 ps
CPU time 1.28 seconds
Started Apr 25 01:01:18 PM PDT 24
Finished Apr 25 01:01:21 PM PDT 24
Peak memory 216904 kb
Host smart-ef7914eb-1001-4272-858f-f3439b259319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492544149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1492544149
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.4262568605
Short name T521
Test name
Test status
Simulation time 121490871 ps
CPU time 1.07 seconds
Started Apr 25 01:01:28 PM PDT 24
Finished Apr 25 01:01:31 PM PDT 24
Peak memory 215100 kb
Host smart-a871f53a-2ed5-47b1-8339-eb999d32ef24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262568605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.4262568605
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3177639195
Short name T602
Test name
Test status
Simulation time 31544640 ps
CPU time 1.27 seconds
Started Apr 25 01:01:15 PM PDT 24
Finished Apr 25 01:01:19 PM PDT 24
Peak memory 215088 kb
Host smart-5e228719-9ce9-436e-b8fa-67d42c8ba193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177639195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3177639195
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.85312199
Short name T695
Test name
Test status
Simulation time 41634164 ps
CPU time 1.38 seconds
Started Apr 25 01:01:28 PM PDT 24
Finished Apr 25 01:01:31 PM PDT 24
Peak memory 218108 kb
Host smart-72d768cc-ad70-4833-8e07-f8b4967db421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85312199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.85312199
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2345113861
Short name T531
Test name
Test status
Simulation time 52415652 ps
CPU time 1.82 seconds
Started Apr 25 01:01:23 PM PDT 24
Finished Apr 25 01:01:26 PM PDT 24
Peak memory 218080 kb
Host smart-a7f4e642-e312-4ea1-b8d7-375fca608826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345113861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2345113861
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.9112981
Short name T613
Test name
Test status
Simulation time 27676500 ps
CPU time 1.26 seconds
Started Apr 25 12:59:44 PM PDT 24
Finished Apr 25 12:59:47 PM PDT 24
Peak memory 215528 kb
Host smart-6d84317d-5ec6-4153-9776-20170235a34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9112981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.9112981
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3970579625
Short name T461
Test name
Test status
Simulation time 17691567 ps
CPU time 0.96 seconds
Started Apr 25 12:59:39 PM PDT 24
Finished Apr 25 12:59:42 PM PDT 24
Peak memory 206560 kb
Host smart-138384c3-6fad-471c-88fb-3e98323a9486
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970579625 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3970579625
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3580348368
Short name T130
Test name
Test status
Simulation time 11009387 ps
CPU time 0.88 seconds
Started Apr 25 12:59:49 PM PDT 24
Finished Apr 25 12:59:52 PM PDT 24
Peak memory 215992 kb
Host smart-ca8f3710-d911-4dff-87cc-78ca4bb92044
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580348368 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3580348368
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.108668271
Short name T565
Test name
Test status
Simulation time 37402685 ps
CPU time 1.16 seconds
Started Apr 25 12:59:29 PM PDT 24
Finished Apr 25 12:59:31 PM PDT 24
Peak memory 216956 kb
Host smart-3f844c43-162d-4276-a187-66fb75ef706e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108668271 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.108668271
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_genbits.3680426335
Short name T269
Test name
Test status
Simulation time 32554178 ps
CPU time 1.1 seconds
Started Apr 25 12:59:42 PM PDT 24
Finished Apr 25 12:59:45 PM PDT 24
Peak memory 219368 kb
Host smart-b44da56b-a541-4a56-8a6b-b97ba3b6e10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680426335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3680426335
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.611499940
Short name T427
Test name
Test status
Simulation time 37422860 ps
CPU time 0.97 seconds
Started Apr 25 12:59:55 PM PDT 24
Finished Apr 25 12:59:57 PM PDT 24
Peak memory 223836 kb
Host smart-927ae92e-5fd1-4549-bc32-5fbc0037cffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611499940 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.611499940
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.2857205619
Short name T283
Test name
Test status
Simulation time 14217533 ps
CPU time 0.92 seconds
Started Apr 25 12:59:28 PM PDT 24
Finished Apr 25 12:59:30 PM PDT 24
Peak memory 206952 kb
Host smart-8d313349-5b6b-4616-976d-7685ffae676a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857205619 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2857205619
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.249737702
Short name T15
Test name
Test status
Simulation time 2133555337 ps
CPU time 4.64 seconds
Started Apr 25 12:59:34 PM PDT 24
Finished Apr 25 12:59:40 PM PDT 24
Peak memory 236384 kb
Host smart-ab4beba7-3892-434f-a99f-59dfe0bdfb35
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249737702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.249737702
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3897183974
Short name T667
Test name
Test status
Simulation time 48294022 ps
CPU time 0.9 seconds
Started Apr 25 12:59:35 PM PDT 24
Finished Apr 25 12:59:37 PM PDT 24
Peak memory 215096 kb
Host smart-e628cea5-ed9a-4fe1-9812-5426a9c39ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897183974 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3897183974
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3946215948
Short name T573
Test name
Test status
Simulation time 610109563 ps
CPU time 6.21 seconds
Started Apr 25 01:00:06 PM PDT 24
Finished Apr 25 01:00:15 PM PDT 24
Peak memory 216896 kb
Host smart-d3ab9e15-a371-4ac2-a37d-5ba12896c6e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946215948 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3946215948
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1338260925
Short name T769
Test name
Test status
Simulation time 28912240797 ps
CPU time 739.51 seconds
Started Apr 25 12:59:30 PM PDT 24
Finished Apr 25 01:11:51 PM PDT 24
Peak memory 217908 kb
Host smart-0931055d-74f8-47a4-af09-13b38f0b935c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338260925 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1338260925
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2885134554
Short name T243
Test name
Test status
Simulation time 29952175 ps
CPU time 1.38 seconds
Started Apr 25 01:00:06 PM PDT 24
Finished Apr 25 01:00:11 PM PDT 24
Peak memory 215552 kb
Host smart-fc03a41e-3493-4554-a8cc-b8ff29a012ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885134554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2885134554
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3658651485
Short name T621
Test name
Test status
Simulation time 47583523 ps
CPU time 0.86 seconds
Started Apr 25 01:00:16 PM PDT 24
Finished Apr 25 01:00:20 PM PDT 24
Peak memory 214732 kb
Host smart-4fce497e-855a-427a-afd1-7ea33fffe521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658651485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3658651485
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2173461215
Short name T403
Test name
Test status
Simulation time 23155970 ps
CPU time 0.84 seconds
Started Apr 25 01:00:03 PM PDT 24
Finished Apr 25 01:00:06 PM PDT 24
Peak memory 216040 kb
Host smart-3fc69407-196a-4336-a7c2-633afa00b210
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173461215 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2173461215
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.273285131
Short name T688
Test name
Test status
Simulation time 36811639 ps
CPU time 1.25 seconds
Started Apr 25 01:00:04 PM PDT 24
Finished Apr 25 01:00:07 PM PDT 24
Peak memory 216584 kb
Host smart-fac8a3a3-9120-4e67-baf8-b1b60e6f27e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273285131 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.273285131
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.142005129
Short name T792
Test name
Test status
Simulation time 27437396 ps
CPU time 0.91 seconds
Started Apr 25 01:00:27 PM PDT 24
Finished Apr 25 01:00:30 PM PDT 24
Peak memory 218436 kb
Host smart-771c7775-e4c1-4f8d-8933-244c27010ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142005129 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.142005129
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3739579124
Short name T247
Test name
Test status
Simulation time 36352980 ps
CPU time 1.07 seconds
Started Apr 25 01:00:23 PM PDT 24
Finished Apr 25 01:00:26 PM PDT 24
Peak memory 216868 kb
Host smart-fa3bb249-3538-4bf0-971a-7c276a9bed4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739579124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3739579124
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3743666385
Short name T32
Test name
Test status
Simulation time 20394125 ps
CPU time 1.15 seconds
Started Apr 25 01:00:19 PM PDT 24
Finished Apr 25 01:00:22 PM PDT 24
Peak memory 215696 kb
Host smart-b6a43164-3496-4428-89a0-e326098f394e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743666385 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3743666385
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3168050198
Short name T596
Test name
Test status
Simulation time 31642812 ps
CPU time 0.92 seconds
Started Apr 25 01:00:13 PM PDT 24
Finished Apr 25 01:00:18 PM PDT 24
Peak memory 215108 kb
Host smart-a0c7a816-3b74-4781-8593-1d15b875e65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168050198 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3168050198
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.473914004
Short name T480
Test name
Test status
Simulation time 373684303 ps
CPU time 3.92 seconds
Started Apr 25 01:00:14 PM PDT 24
Finished Apr 25 01:00:21 PM PDT 24
Peak memory 215100 kb
Host smart-edeb0818-70d2-4f07-8d05-d49b7f9b4e01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473914004 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.473914004
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.908867488
Short name T201
Test name
Test status
Simulation time 26105771818 ps
CPU time 321.68 seconds
Started Apr 25 01:00:23 PM PDT 24
Finished Apr 25 01:05:46 PM PDT 24
Peak memory 223540 kb
Host smart-13c25d24-0eac-438f-8c88-7f0fbfc1d84e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908867488 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.908867488
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert_test.792044355
Short name T755
Test name
Test status
Simulation time 68157127 ps
CPU time 0.88 seconds
Started Apr 25 01:00:10 PM PDT 24
Finished Apr 25 01:00:16 PM PDT 24
Peak memory 214740 kb
Host smart-1ccd21e5-136f-483f-8ac0-7349040fba6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792044355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.792044355
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.336514675
Short name T382
Test name
Test status
Simulation time 39814375 ps
CPU time 1.07 seconds
Started Apr 25 01:00:14 PM PDT 24
Finished Apr 25 01:00:18 PM PDT 24
Peak memory 218060 kb
Host smart-b4bfee43-0d1d-49fb-865e-d3e3de8310eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336514675 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.336514675
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.116501033
Short name T552
Test name
Test status
Simulation time 42012495 ps
CPU time 0.96 seconds
Started Apr 25 01:00:13 PM PDT 24
Finished Apr 25 01:00:22 PM PDT 24
Peak memory 218412 kb
Host smart-4de5a689-22eb-4c0b-b4b8-d9a53f4fa1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116501033 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.116501033
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2974735671
Short name T510
Test name
Test status
Simulation time 55393743 ps
CPU time 1.71 seconds
Started Apr 25 12:59:59 PM PDT 24
Finished Apr 25 01:00:02 PM PDT 24
Peak memory 218240 kb
Host smart-1419b6c8-72e4-4e07-9499-d191fb1239a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974735671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2974735671
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1918104434
Short name T586
Test name
Test status
Simulation time 21815191 ps
CPU time 1.23 seconds
Started Apr 25 01:00:17 PM PDT 24
Finished Apr 25 01:00:21 PM PDT 24
Peak memory 224796 kb
Host smart-60dd9d9f-9934-4123-b42d-276f368f5176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918104434 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1918104434
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2238659854
Short name T579
Test name
Test status
Simulation time 115987874 ps
CPU time 0.93 seconds
Started Apr 25 01:00:12 PM PDT 24
Finished Apr 25 01:00:17 PM PDT 24
Peak memory 215184 kb
Host smart-dc9b7301-3e11-4c4f-b155-51e698a96442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238659854 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2238659854
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.163637795
Short name T402
Test name
Test status
Simulation time 613637715 ps
CPU time 6.02 seconds
Started Apr 25 01:00:00 PM PDT 24
Finished Apr 25 01:00:07 PM PDT 24
Peak memory 219500 kb
Host smart-0fad6be0-047c-463f-9662-d155afbca73b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163637795 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.163637795
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2625980466
Short name T401
Test name
Test status
Simulation time 282733356380 ps
CPU time 1499.55 seconds
Started Apr 25 01:00:07 PM PDT 24
Finished Apr 25 01:25:11 PM PDT 24
Peak memory 224468 kb
Host smart-1a2f4ff3-9e7a-4e91-ae01-cef988faefc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625980466 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2625980466
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1148933106
Short name T136
Test name
Test status
Simulation time 23031879 ps
CPU time 1.17 seconds
Started Apr 25 01:00:14 PM PDT 24
Finished Apr 25 01:00:18 PM PDT 24
Peak memory 215552 kb
Host smart-940c83a9-3a03-4211-ba59-43b9f7f6c4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148933106 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1148933106
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1099286510
Short name T55
Test name
Test status
Simulation time 13141688 ps
CPU time 0.88 seconds
Started Apr 25 01:00:28 PM PDT 24
Finished Apr 25 01:00:31 PM PDT 24
Peak memory 206916 kb
Host smart-cb6366ca-1645-4772-9c0d-580105bfbb12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099286510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1099286510
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3743174248
Short name T390
Test name
Test status
Simulation time 71014440 ps
CPU time 0.81 seconds
Started Apr 25 01:00:20 PM PDT 24
Finished Apr 25 01:00:23 PM PDT 24
Peak memory 215256 kb
Host smart-ff8ce500-6a2b-4987-8502-51a3f9d16522
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743174248 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3743174248
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1321117969
Short name T18
Test name
Test status
Simulation time 177390188 ps
CPU time 1.14 seconds
Started Apr 25 01:00:09 PM PDT 24
Finished Apr 25 01:00:15 PM PDT 24
Peak memory 216728 kb
Host smart-7a6fc015-55f1-4729-b5c9-7b554f9e7775
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321117969 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1321117969
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2800233001
Short name T505
Test name
Test status
Simulation time 18315688 ps
CPU time 1.06 seconds
Started Apr 25 01:00:17 PM PDT 24
Finished Apr 25 01:00:21 PM PDT 24
Peak memory 218344 kb
Host smart-f16e4128-9ac7-46b7-babe-b2612c834d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800233001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2800233001
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2042148763
Short name T421
Test name
Test status
Simulation time 220628731 ps
CPU time 2.93 seconds
Started Apr 25 01:00:15 PM PDT 24
Finished Apr 25 01:00:21 PM PDT 24
Peak memory 219664 kb
Host smart-59ab4fcb-bfa1-4016-886e-a7839a48bbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042148763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2042148763
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2176834141
Short name T726
Test name
Test status
Simulation time 35957161 ps
CPU time 0.86 seconds
Started Apr 25 01:00:17 PM PDT 24
Finished Apr 25 01:00:21 PM PDT 24
Peak memory 215516 kb
Host smart-599a1486-3fa4-4245-b208-0bacc44acb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176834141 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2176834141
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.822120338
Short name T373
Test name
Test status
Simulation time 109109495 ps
CPU time 0.87 seconds
Started Apr 25 01:00:14 PM PDT 24
Finished Apr 25 01:00:18 PM PDT 24
Peak memory 215156 kb
Host smart-f4527027-6dfe-4de3-b0d1-ac2f61aa4839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822120338 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.822120338
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.533766478
Short name T419
Test name
Test status
Simulation time 1492061162 ps
CPU time 2.88 seconds
Started Apr 25 01:00:04 PM PDT 24
Finished Apr 25 01:00:08 PM PDT 24
Peak memory 216976 kb
Host smart-7b5ef08d-3e85-4ad6-be31-ebfc54689783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533766478 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.533766478
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1299366206
Short name T196
Test name
Test status
Simulation time 23236907165 ps
CPU time 230.63 seconds
Started Apr 25 01:00:19 PM PDT 24
Finished Apr 25 01:04:12 PM PDT 24
Peak memory 218248 kb
Host smart-2822ba48-66b0-45c3-b78c-8f2ac5f519da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299366206 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1299366206
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3353765646
Short name T151
Test name
Test status
Simulation time 70236349 ps
CPU time 1.15 seconds
Started Apr 25 01:00:42 PM PDT 24
Finished Apr 25 01:00:46 PM PDT 24
Peak memory 215464 kb
Host smart-eb1fc796-961d-4f38-b26f-7bf43cb6bf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353765646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3353765646
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1440756622
Short name T651
Test name
Test status
Simulation time 49309842 ps
CPU time 0.88 seconds
Started Apr 25 01:00:12 PM PDT 24
Finished Apr 25 01:00:16 PM PDT 24
Peak memory 215128 kb
Host smart-7b654caf-ede2-4364-9d6c-b035eaa71f3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440756622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1440756622
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3901743216
Short name T541
Test name
Test status
Simulation time 38540345 ps
CPU time 0.8 seconds
Started Apr 25 01:00:32 PM PDT 24
Finished Apr 25 01:00:38 PM PDT 24
Peak memory 216044 kb
Host smart-f01dfa27-2174-421c-8e68-914061fdbdc1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901743216 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3901743216
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1297558765
Short name T727
Test name
Test status
Simulation time 73514468 ps
CPU time 1.08 seconds
Started Apr 25 01:00:14 PM PDT 24
Finished Apr 25 01:00:18 PM PDT 24
Peak memory 216876 kb
Host smart-b9faa628-3e48-4bea-a646-ef65420530cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297558765 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1297558765
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3942546111
Short name T119
Test name
Test status
Simulation time 18236689 ps
CPU time 1.03 seconds
Started Apr 25 01:00:11 PM PDT 24
Finished Apr 25 01:00:24 PM PDT 24
Peak memory 218332 kb
Host smart-0559f4ba-6867-41e8-b973-a6ae3b130074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942546111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3942546111
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2776084881
Short name T760
Test name
Test status
Simulation time 186425001 ps
CPU time 1.52 seconds
Started Apr 25 01:00:15 PM PDT 24
Finished Apr 25 01:00:20 PM PDT 24
Peak memory 218368 kb
Host smart-abe6988f-859b-4183-ba42-f7aaf9bdafc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776084881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2776084881
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.476009407
Short name T68
Test name
Test status
Simulation time 33444194 ps
CPU time 0.9 seconds
Started Apr 25 01:00:12 PM PDT 24
Finished Apr 25 01:00:16 PM PDT 24
Peak memory 215308 kb
Host smart-81d43e7b-42e9-4645-be19-947a5b397ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476009407 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.476009407
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1294948884
Short name T498
Test name
Test status
Simulation time 58942169 ps
CPU time 0.97 seconds
Started Apr 25 01:00:16 PM PDT 24
Finished Apr 25 01:00:20 PM PDT 24
Peak memory 215208 kb
Host smart-5575ff59-c1a5-4344-a0d9-1917336fba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294948884 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1294948884
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2194029135
Short name T211
Test name
Test status
Simulation time 185507984 ps
CPU time 3.9 seconds
Started Apr 25 01:00:32 PM PDT 24
Finished Apr 25 01:00:41 PM PDT 24
Peak memory 216748 kb
Host smart-df816256-a92f-4cb5-854b-b953505cc5b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194029135 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2194029135
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1318482851
Short name T452
Test name
Test status
Simulation time 434912211461 ps
CPU time 2212.03 seconds
Started Apr 25 01:00:13 PM PDT 24
Finished Apr 25 01:37:09 PM PDT 24
Peak memory 227600 kb
Host smart-677edef8-7cd5-409b-830a-9cfc662f26dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318482851 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1318482851
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1792760639
Short name T738
Test name
Test status
Simulation time 66886959 ps
CPU time 1.1 seconds
Started Apr 25 01:00:04 PM PDT 24
Finished Apr 25 01:00:07 PM PDT 24
Peak memory 215532 kb
Host smart-daa44506-301b-4592-97ad-555aedc6c1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792760639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1792760639
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.4289342935
Short name T718
Test name
Test status
Simulation time 114081833 ps
CPU time 0.85 seconds
Started Apr 25 01:00:25 PM PDT 24
Finished Apr 25 01:00:27 PM PDT 24
Peak memory 206204 kb
Host smart-908acfb8-55e3-4a8e-84fb-d21f620efa9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289342935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.4289342935
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2987660301
Short name T180
Test name
Test status
Simulation time 19620645 ps
CPU time 0.84 seconds
Started Apr 25 01:00:17 PM PDT 24
Finished Apr 25 01:00:21 PM PDT 24
Peak memory 216024 kb
Host smart-7c9d41d2-f985-4322-ab13-12d34b715046
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987660301 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2987660301
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2545825389
Short name T380
Test name
Test status
Simulation time 52770720 ps
CPU time 0.94 seconds
Started Apr 25 01:00:07 PM PDT 24
Finished Apr 25 01:00:13 PM PDT 24
Peak memory 217736 kb
Host smart-0edf59d6-efcf-4719-9ffc-043ab7bcc21e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545825389 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2545825389
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.1088939695
Short name T728
Test name
Test status
Simulation time 62627337 ps
CPU time 1 seconds
Started Apr 25 01:00:12 PM PDT 24
Finished Apr 25 01:00:17 PM PDT 24
Peak memory 218640 kb
Host smart-ae7acd23-77da-4753-b098-9cc9c0436296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088939695 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1088939695
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2404342371
Short name T303
Test name
Test status
Simulation time 58262128 ps
CPU time 1.3 seconds
Started Apr 25 01:00:35 PM PDT 24
Finished Apr 25 01:00:41 PM PDT 24
Peak memory 217992 kb
Host smart-971d0efa-e45a-45f8-b33c-79f490ebd080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404342371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2404342371
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2517026473
Short name T571
Test name
Test status
Simulation time 25020059 ps
CPU time 1.14 seconds
Started Apr 25 01:00:13 PM PDT 24
Finished Apr 25 01:00:17 PM PDT 24
Peak memory 215412 kb
Host smart-f10c52dd-6877-4b8d-9829-7a3cd5461945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517026473 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2517026473
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.4069165687
Short name T311
Test name
Test status
Simulation time 47147628 ps
CPU time 0.96 seconds
Started Apr 25 01:00:24 PM PDT 24
Finished Apr 25 01:00:27 PM PDT 24
Peak memory 215164 kb
Host smart-2d61c027-027e-4bc7-af62-c017b2d68103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069165687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.4069165687
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2304747160
Short name T564
Test name
Test status
Simulation time 252347252 ps
CPU time 2.91 seconds
Started Apr 25 01:00:12 PM PDT 24
Finished Apr 25 01:00:19 PM PDT 24
Peak memory 216928 kb
Host smart-580aeb91-4d27-4767-875f-5c7406901fa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304747160 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2304747160
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2559381707
Short name T202
Test name
Test status
Simulation time 223784508977 ps
CPU time 1316.63 seconds
Started Apr 25 01:00:13 PM PDT 24
Finished Apr 25 01:22:13 PM PDT 24
Peak memory 223012 kb
Host smart-01a13c7e-99d3-4c55-a91d-44463d96bd7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559381707 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2559381707
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.612448950
Short name T540
Test name
Test status
Simulation time 80773371 ps
CPU time 1.24 seconds
Started Apr 25 01:00:11 PM PDT 24
Finished Apr 25 01:00:16 PM PDT 24
Peak memory 215516 kb
Host smart-7df08116-071a-4ca4-bef0-996b6fed667c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612448950 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.612448950
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2824236466
Short name T459
Test name
Test status
Simulation time 44099293 ps
CPU time 0.85 seconds
Started Apr 25 01:00:32 PM PDT 24
Finished Apr 25 01:00:42 PM PDT 24
Peak memory 214724 kb
Host smart-95f7cc33-d904-45f0-ad07-b7908a33e254
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824236466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2824236466
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.851402196
Short name T715
Test name
Test status
Simulation time 43205421 ps
CPU time 1.11 seconds
Started Apr 25 01:00:35 PM PDT 24
Finished Apr 25 01:00:41 PM PDT 24
Peak memory 216880 kb
Host smart-20d78f59-3bbe-41e6-8c94-877ea6fb62bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851402196 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.851402196
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1229454950
Short name T491
Test name
Test status
Simulation time 20496251 ps
CPU time 0.93 seconds
Started Apr 25 01:00:23 PM PDT 24
Finished Apr 25 01:00:25 PM PDT 24
Peak memory 218176 kb
Host smart-20269a33-43cb-4aba-8e1e-d4119a15e0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229454950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1229454950
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2943954279
Short name T560
Test name
Test status
Simulation time 42626172 ps
CPU time 1.75 seconds
Started Apr 25 01:00:32 PM PDT 24
Finished Apr 25 01:00:40 PM PDT 24
Peak memory 216916 kb
Host smart-7cb0d8ab-444f-493b-acca-bd584e96dfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943954279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2943954279
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2493468042
Short name T36
Test name
Test status
Simulation time 61109682 ps
CPU time 0.88 seconds
Started Apr 25 01:00:24 PM PDT 24
Finished Apr 25 01:00:27 PM PDT 24
Peak memory 215504 kb
Host smart-858a52c1-18b6-4c82-a010-24103e4e0a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493468042 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2493468042
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2423570662
Short name T725
Test name
Test status
Simulation time 16329972 ps
CPU time 0.98 seconds
Started Apr 25 01:00:16 PM PDT 24
Finished Apr 25 01:00:20 PM PDT 24
Peak memory 215180 kb
Host smart-58df575d-ddf7-4fcb-9975-7d1366ef093d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423570662 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2423570662
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.39427990
Short name T666
Test name
Test status
Simulation time 878603675 ps
CPU time 4.7 seconds
Started Apr 25 01:00:33 PM PDT 24
Finished Apr 25 01:00:43 PM PDT 24
Peak memory 215140 kb
Host smart-ffab5906-3c87-4937-81f7-ec6013dd3349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39427990 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.39427990
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1904583906
Short name T691
Test name
Test status
Simulation time 70669784114 ps
CPU time 798.48 seconds
Started Apr 25 01:00:28 PM PDT 24
Finished Apr 25 01:13:48 PM PDT 24
Peak memory 223588 kb
Host smart-4670c9d1-eb51-41c5-8e51-7827bf113677
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904583906 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1904583906
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.345279959
Short name T150
Test name
Test status
Simulation time 33703964 ps
CPU time 1.21 seconds
Started Apr 25 01:00:13 PM PDT 24
Finished Apr 25 01:00:18 PM PDT 24
Peak memory 215540 kb
Host smart-87e2080c-e0a4-43da-9264-901079397901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345279959 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.345279959
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.297586971
Short name T488
Test name
Test status
Simulation time 27951288 ps
CPU time 0.95 seconds
Started Apr 25 01:00:30 PM PDT 24
Finished Apr 25 01:00:33 PM PDT 24
Peak memory 214728 kb
Host smart-8454484c-3456-4779-8cab-033a6fdb0ce0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297586971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.297586971
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2216508591
Short name T529
Test name
Test status
Simulation time 34101617 ps
CPU time 0.84 seconds
Started Apr 25 01:00:26 PM PDT 24
Finished Apr 25 01:00:36 PM PDT 24
Peak memory 216044 kb
Host smart-9e84ff9f-b310-4ea0-8a9f-e2e01064387e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216508591 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2216508591
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.567256937
Short name T96
Test name
Test status
Simulation time 84189906 ps
CPU time 1.04 seconds
Started Apr 25 01:00:34 PM PDT 24
Finished Apr 25 01:00:40 PM PDT 24
Peak memory 218112 kb
Host smart-d3f0554c-5703-4462-9eb2-f13c38008fde
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567256937 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.567256937
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1170389954
Short name T494
Test name
Test status
Simulation time 17839046 ps
CPU time 1.14 seconds
Started Apr 25 01:00:22 PM PDT 24
Finished Apr 25 01:00:24 PM PDT 24
Peak memory 223836 kb
Host smart-68f16977-9bda-4bf8-b297-034ee82e0d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170389954 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1170389954
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.4132153135
Short name T449
Test name
Test status
Simulation time 70078825 ps
CPU time 1.21 seconds
Started Apr 25 01:00:27 PM PDT 24
Finished Apr 25 01:00:38 PM PDT 24
Peak memory 217060 kb
Host smart-035530bf-4e3b-4aa9-b048-999427f48f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132153135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.4132153135
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.717000626
Short name T158
Test name
Test status
Simulation time 28463506 ps
CPU time 0.9 seconds
Started Apr 25 01:00:23 PM PDT 24
Finished Apr 25 01:00:25 PM PDT 24
Peak memory 215688 kb
Host smart-3bca9338-0f26-42b9-9aa6-553936af3b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717000626 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.717000626
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3653478947
Short name T555
Test name
Test status
Simulation time 16957417 ps
CPU time 0.95 seconds
Started Apr 25 01:00:23 PM PDT 24
Finished Apr 25 01:00:25 PM PDT 24
Peak memory 215156 kb
Host smart-3cffe68b-4f61-48b6-b3d2-d5ec66d5ecae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653478947 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3653478947
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.237839917
Short name T661
Test name
Test status
Simulation time 309610490 ps
CPU time 3.64 seconds
Started Apr 25 01:00:14 PM PDT 24
Finished Apr 25 01:00:20 PM PDT 24
Peak memory 216984 kb
Host smart-195110a3-ddf1-4c35-ac75-8bcdd172e825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237839917 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.237839917
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.4116175307
Short name T197
Test name
Test status
Simulation time 40936384898 ps
CPU time 896.01 seconds
Started Apr 25 01:00:23 PM PDT 24
Finished Apr 25 01:15:21 PM PDT 24
Peak memory 218064 kb
Host smart-5ec8eab9-d5ac-4420-8e18-d38add10891e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116175307 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.4116175307
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3931501279
Short name T246
Test name
Test status
Simulation time 146408479 ps
CPU time 1.13 seconds
Started Apr 25 01:00:44 PM PDT 24
Finished Apr 25 01:00:48 PM PDT 24
Peak memory 215576 kb
Host smart-a3c94919-746d-402b-8725-2936db9b0d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931501279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3931501279
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.82238087
Short name T798
Test name
Test status
Simulation time 21176693 ps
CPU time 1.06 seconds
Started Apr 25 01:00:17 PM PDT 24
Finished Apr 25 01:00:20 PM PDT 24
Peak memory 206532 kb
Host smart-4da61047-d3be-41c4-a38c-4017cc7bf1b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82238087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.82238087
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.96764792
Short name T72
Test name
Test status
Simulation time 13513323 ps
CPU time 0.9 seconds
Started Apr 25 01:00:28 PM PDT 24
Finished Apr 25 01:00:31 PM PDT 24
Peak memory 215232 kb
Host smart-5075f726-ed71-4c25-b1ce-674b8d2be7ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96764792 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.96764792
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_err.2219013619
Short name T723
Test name
Test status
Simulation time 29309369 ps
CPU time 0.96 seconds
Started Apr 25 01:00:31 PM PDT 24
Finished Apr 25 01:00:36 PM PDT 24
Peak memory 223688 kb
Host smart-6ad17570-7a7a-4bbf-8fc3-703c3c581523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219013619 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2219013619
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.760815719
Short name T708
Test name
Test status
Simulation time 194151253 ps
CPU time 1.87 seconds
Started Apr 25 01:00:30 PM PDT 24
Finished Apr 25 01:00:35 PM PDT 24
Peak memory 219880 kb
Host smart-e95ca1ec-d7f4-4ea9-b483-b413d818964c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760815719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.760815719
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1826449463
Short name T598
Test name
Test status
Simulation time 41940073 ps
CPU time 0.98 seconds
Started Apr 25 01:00:56 PM PDT 24
Finished Apr 25 01:00:59 PM PDT 24
Peak memory 223700 kb
Host smart-fd2f8489-a60c-46ee-91a6-529e63acd98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826449463 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1826449463
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3041156556
Short name T790
Test name
Test status
Simulation time 53710883 ps
CPU time 0.93 seconds
Started Apr 25 01:00:44 PM PDT 24
Finished Apr 25 01:00:48 PM PDT 24
Peak memory 215152 kb
Host smart-127077d6-3aa7-45dd-80f5-ad426cbfef85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041156556 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3041156556
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2190038781
Short name T306
Test name
Test status
Simulation time 149436210 ps
CPU time 2.24 seconds
Started Apr 25 01:00:26 PM PDT 24
Finished Apr 25 01:00:29 PM PDT 24
Peak memory 218048 kb
Host smart-69dce22d-9b56-43ef-9154-46694c17a440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190038781 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2190038781
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1379169860
Short name T825
Test name
Test status
Simulation time 674364043761 ps
CPU time 1366.76 seconds
Started Apr 25 01:00:33 PM PDT 24
Finished Apr 25 01:23:25 PM PDT 24
Peak memory 221988 kb
Host smart-59532032-926e-4d69-8b4b-872083f1e127
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379169860 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1379169860
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert_test.2485763419
Short name T301
Test name
Test status
Simulation time 31134131 ps
CPU time 0.88 seconds
Started Apr 25 01:00:34 PM PDT 24
Finished Apr 25 01:00:40 PM PDT 24
Peak memory 206524 kb
Host smart-3ffb4e6f-46e4-41d8-be00-e0160f80c9d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485763419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2485763419
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3715736131
Short name T171
Test name
Test status
Simulation time 20852001 ps
CPU time 0.87 seconds
Started Apr 25 01:00:21 PM PDT 24
Finished Apr 25 01:00:23 PM PDT 24
Peak memory 216044 kb
Host smart-9eec2841-327c-4ebd-91b3-4451d68f37bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715736131 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3715736131
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.2244402879
Short name T7
Test name
Test status
Simulation time 25758282 ps
CPU time 1.29 seconds
Started Apr 25 01:00:28 PM PDT 24
Finished Apr 25 01:00:32 PM PDT 24
Peak memory 217168 kb
Host smart-2be3bd38-dd82-4144-9303-e62ecacfeaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244402879 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2244402879
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1659216007
Short name T768
Test name
Test status
Simulation time 123707871 ps
CPU time 1.67 seconds
Started Apr 25 01:00:26 PM PDT 24
Finished Apr 25 01:00:29 PM PDT 24
Peak memory 218772 kb
Host smart-74439991-9388-4002-97f1-c234e29eaed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659216007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1659216007
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1121094548
Short name T638
Test name
Test status
Simulation time 29628542 ps
CPU time 1.05 seconds
Started Apr 25 01:00:39 PM PDT 24
Finished Apr 25 01:00:43 PM PDT 24
Peak memory 223908 kb
Host smart-a48968ba-9776-49a2-af9b-22162f79438b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121094548 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1121094548
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3457159495
Short name T426
Test name
Test status
Simulation time 21930271 ps
CPU time 0.9 seconds
Started Apr 25 01:00:27 PM PDT 24
Finished Apr 25 01:00:30 PM PDT 24
Peak memory 215168 kb
Host smart-918f1ad6-1d39-4f31-b913-72e6fa15eb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457159495 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3457159495
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.140556
Short name T485
Test name
Test status
Simulation time 194590034 ps
CPU time 2.6 seconds
Started Apr 25 01:00:25 PM PDT 24
Finished Apr 25 01:00:29 PM PDT 24
Peak memory 216648 kb
Host smart-f5b3b1ba-11da-425a-be0c-5320167cb749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140556 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.140556
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3433334599
Short name T835
Test name
Test status
Simulation time 44907833484 ps
CPU time 1155.12 seconds
Started Apr 25 01:00:26 PM PDT 24
Finished Apr 25 01:19:43 PM PDT 24
Peak memory 223524 kb
Host smart-6862f053-15cd-479c-9ebb-94edafbcb11a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433334599 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3433334599
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.554061886
Short name T535
Test name
Test status
Simulation time 63092679 ps
CPU time 1.24 seconds
Started Apr 25 01:00:33 PM PDT 24
Finished Apr 25 01:00:40 PM PDT 24
Peak memory 215556 kb
Host smart-5cd49a6a-a3a1-4348-b990-563a6518d1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554061886 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.554061886
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1323167611
Short name T619
Test name
Test status
Simulation time 19156896 ps
CPU time 0.78 seconds
Started Apr 25 01:00:08 PM PDT 24
Finished Apr 25 01:00:14 PM PDT 24
Peak memory 206744 kb
Host smart-b7b4f05b-8866-407c-970f-1961137141db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323167611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1323167611
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2123104634
Short name T493
Test name
Test status
Simulation time 17818257 ps
CPU time 0.91 seconds
Started Apr 25 01:00:19 PM PDT 24
Finished Apr 25 01:00:23 PM PDT 24
Peak memory 215464 kb
Host smart-e6617ba2-d141-4709-9966-35adf953a85c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123104634 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2123104634
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_err.2051620946
Short name T805
Test name
Test status
Simulation time 37539656 ps
CPU time 0.95 seconds
Started Apr 25 01:00:37 PM PDT 24
Finished Apr 25 01:00:42 PM PDT 24
Peak memory 223680 kb
Host smart-bd39e5f1-2756-4857-a4fe-3f25a6794180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051620946 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2051620946
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.282016698
Short name T675
Test name
Test status
Simulation time 66411955 ps
CPU time 1.27 seconds
Started Apr 25 01:00:24 PM PDT 24
Finished Apr 25 01:00:27 PM PDT 24
Peak memory 216804 kb
Host smart-486175cd-6859-4c38-becb-0d128e5e6d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282016698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.282016698
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3760544250
Short name T629
Test name
Test status
Simulation time 37939207 ps
CPU time 0.88 seconds
Started Apr 25 01:00:31 PM PDT 24
Finished Apr 25 01:00:36 PM PDT 24
Peak memory 215392 kb
Host smart-34a1d9db-8a9f-439f-a0f8-a50c5f9feb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760544250 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3760544250
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.3260093106
Short name T310
Test name
Test status
Simulation time 21732983 ps
CPU time 0.93 seconds
Started Apr 25 01:00:26 PM PDT 24
Finished Apr 25 01:00:28 PM PDT 24
Peak memory 215140 kb
Host smart-bbd15825-8e4c-4803-8e0a-a9fce2a9c00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260093106 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3260093106
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2027613735
Short name T795
Test name
Test status
Simulation time 31408872 ps
CPU time 1.01 seconds
Started Apr 25 01:00:21 PM PDT 24
Finished Apr 25 01:00:24 PM PDT 24
Peak memory 215156 kb
Host smart-3d5a2087-8687-41fc-9f89-d012a9e7716a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027613735 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2027613735
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.396442880
Short name T588
Test name
Test status
Simulation time 106184443103 ps
CPU time 898.45 seconds
Started Apr 25 01:00:24 PM PDT 24
Finished Apr 25 01:15:24 PM PDT 24
Peak memory 221352 kb
Host smart-55ecc751-de2a-41ba-a72d-f638084c9941
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396442880 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.396442880
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert_test.3944806226
Short name T537
Test name
Test status
Simulation time 42643338 ps
CPU time 0.88 seconds
Started Apr 25 12:59:42 PM PDT 24
Finished Apr 25 12:59:45 PM PDT 24
Peak memory 206504 kb
Host smart-887983d3-8d9e-4e18-b074-ce90172f28fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944806226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3944806226
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.474805059
Short name T3
Test name
Test status
Simulation time 33887669 ps
CPU time 1.15 seconds
Started Apr 25 12:59:33 PM PDT 24
Finished Apr 25 12:59:35 PM PDT 24
Peak memory 219324 kb
Host smart-14103014-7558-431d-93f6-c5db68eeab0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474805059 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.474805059
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.708347248
Short name T93
Test name
Test status
Simulation time 21148180 ps
CPU time 1.15 seconds
Started Apr 25 12:59:43 PM PDT 24
Finished Apr 25 12:59:47 PM PDT 24
Peak memory 219608 kb
Host smart-59c044f3-1e30-4b76-8f19-73ba024e9b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708347248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.708347248
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2385640409
Short name T746
Test name
Test status
Simulation time 56192960 ps
CPU time 1.57 seconds
Started Apr 25 12:59:38 PM PDT 24
Finished Apr 25 12:59:43 PM PDT 24
Peak memory 218108 kb
Host smart-1ed0d892-944b-4a57-bcc8-d88c2d12686c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385640409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2385640409
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2177372976
Short name T640
Test name
Test status
Simulation time 21053564 ps
CPU time 1.19 seconds
Started Apr 25 12:59:56 PM PDT 24
Finished Apr 25 12:59:58 PM PDT 24
Peak memory 223928 kb
Host smart-4c523791-40fb-41dc-bb85-f5d622fc19bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177372976 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2177372976
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.3607656962
Short name T787
Test name
Test status
Simulation time 15281022 ps
CPU time 1.04 seconds
Started Apr 25 12:59:34 PM PDT 24
Finished Apr 25 12:59:37 PM PDT 24
Peak memory 206868 kb
Host smart-8dea929d-92fd-4cc1-904c-97ad439bdfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607656962 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3607656962
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1025286042
Short name T58
Test name
Test status
Simulation time 251809276 ps
CPU time 4.06 seconds
Started Apr 25 12:59:33 PM PDT 24
Finished Apr 25 12:59:39 PM PDT 24
Peak memory 236576 kb
Host smart-f7ac27c5-31df-44a6-802f-20860e1424bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025286042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1025286042
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3850605920
Short name T435
Test name
Test status
Simulation time 15824938 ps
CPU time 0.94 seconds
Started Apr 25 12:59:44 PM PDT 24
Finished Apr 25 12:59:47 PM PDT 24
Peak memory 215196 kb
Host smart-90eff981-0b63-46d3-a367-04a0f148f03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850605920 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3850605920
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.372770184
Short name T786
Test name
Test status
Simulation time 1042940279 ps
CPU time 4.54 seconds
Started Apr 25 12:59:38 PM PDT 24
Finished Apr 25 12:59:45 PM PDT 24
Peak memory 215084 kb
Host smart-6f61b3a7-0c16-4f0a-a1fb-044dbc74f6fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372770184 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.372770184
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1127535733
Short name T193
Test name
Test status
Simulation time 99442697770 ps
CPU time 1230.54 seconds
Started Apr 25 12:59:39 PM PDT 24
Finished Apr 25 01:20:12 PM PDT 24
Peak memory 225200 kb
Host smart-ef38ad39-3690-46f3-9055-daa51bd18bc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127535733 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1127535733
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2898825708
Short name T184
Test name
Test status
Simulation time 27007190 ps
CPU time 1.22 seconds
Started Apr 25 01:00:23 PM PDT 24
Finished Apr 25 01:00:26 PM PDT 24
Peak memory 215536 kb
Host smart-db1c304b-78d4-4fd4-8e60-22ac4ce51a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898825708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2898825708
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.4104547761
Short name T332
Test name
Test status
Simulation time 66759330 ps
CPU time 0.89 seconds
Started Apr 25 01:00:46 PM PDT 24
Finished Apr 25 01:00:50 PM PDT 24
Peak memory 206852 kb
Host smart-a151914e-352a-47a9-b911-4f0a9810d098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104547761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.4104547761
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1399327803
Short name T91
Test name
Test status
Simulation time 101172190 ps
CPU time 1.13 seconds
Started Apr 25 01:00:13 PM PDT 24
Finished Apr 25 01:00:18 PM PDT 24
Peak memory 219284 kb
Host smart-54e6f676-9e9b-4d38-bb29-990154e687c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399327803 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1399327803
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2846938002
Short name T817
Test name
Test status
Simulation time 27241699 ps
CPU time 0.93 seconds
Started Apr 25 01:00:32 PM PDT 24
Finished Apr 25 01:00:39 PM PDT 24
Peak memory 218036 kb
Host smart-0d9b077f-b4c7-4d6a-af5b-2d99267243df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846938002 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2846938002
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2785297880
Short name T420
Test name
Test status
Simulation time 109361375 ps
CPU time 1.45 seconds
Started Apr 25 01:00:08 PM PDT 24
Finished Apr 25 01:00:15 PM PDT 24
Peak memory 218068 kb
Host smart-b91ab2ee-5c79-4cd8-ba3c-3c372d6ebcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785297880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2785297880
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.4008928489
Short name T685
Test name
Test status
Simulation time 42789741 ps
CPU time 0.93 seconds
Started Apr 25 01:00:04 PM PDT 24
Finished Apr 25 01:00:07 PM PDT 24
Peak memory 215292 kb
Host smart-b9351786-4bfc-4629-a62e-e2e4a7ac0986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008928489 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.4008928489
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2518953473
Short name T658
Test name
Test status
Simulation time 16937532 ps
CPU time 0.96 seconds
Started Apr 25 01:00:28 PM PDT 24
Finished Apr 25 01:00:30 PM PDT 24
Peak memory 215104 kb
Host smart-f5c5dc36-69c6-456e-8b53-22d0d69223aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518953473 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2518953473
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1462896391
Short name T489
Test name
Test status
Simulation time 1142393401 ps
CPU time 3.66 seconds
Started Apr 25 01:00:33 PM PDT 24
Finished Apr 25 01:00:42 PM PDT 24
Peak memory 216896 kb
Host smart-a184e49f-61fa-4e0c-808a-136bb5528956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462896391 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1462896391
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1622674295
Short name T839
Test name
Test status
Simulation time 63247622328 ps
CPU time 491.27 seconds
Started Apr 25 01:00:15 PM PDT 24
Finished Apr 25 01:08:30 PM PDT 24
Peak memory 218636 kb
Host smart-cdb3cdf2-a206-4500-a59f-0dff07ed0898
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622674295 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1622674295
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1363537451
Short name T123
Test name
Test status
Simulation time 22622507 ps
CPU time 1.14 seconds
Started Apr 25 01:00:13 PM PDT 24
Finished Apr 25 01:00:18 PM PDT 24
Peak memory 215588 kb
Host smart-7d551ba6-9e81-4225-97ed-f1136ebb44b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363537451 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1363537451
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3898996724
Short name T61
Test name
Test status
Simulation time 34480629 ps
CPU time 0.88 seconds
Started Apr 25 01:00:25 PM PDT 24
Finished Apr 25 01:00:27 PM PDT 24
Peak memory 214720 kb
Host smart-66dfaa01-63a0-43c2-b9e7-e2ec07cd7821
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898996724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3898996724
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1467642753
Short name T129
Test name
Test status
Simulation time 12903866 ps
CPU time 1.03 seconds
Started Apr 25 01:00:17 PM PDT 24
Finished Apr 25 01:00:20 PM PDT 24
Peak memory 216232 kb
Host smart-08982657-6dbf-4347-8c16-3fe65666b01d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467642753 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1467642753
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3597549911
Short name T97
Test name
Test status
Simulation time 35710591 ps
CPU time 1.26 seconds
Started Apr 25 01:00:19 PM PDT 24
Finished Apr 25 01:00:23 PM PDT 24
Peak memory 219068 kb
Host smart-5666bb18-1140-4e0a-8fdb-091807d9c154
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597549911 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3597549911
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.480781348
Short name T445
Test name
Test status
Simulation time 18562706 ps
CPU time 1.04 seconds
Started Apr 25 01:00:24 PM PDT 24
Finished Apr 25 01:00:26 PM PDT 24
Peak memory 218300 kb
Host smart-3618b7bc-bec7-43e6-bc20-ce90ff2a16de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480781348 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.480781348
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3303370951
Short name T831
Test name
Test status
Simulation time 43056587 ps
CPU time 1.51 seconds
Started Apr 25 01:00:16 PM PDT 24
Finished Apr 25 01:00:21 PM PDT 24
Peak memory 218404 kb
Host smart-fe16ac69-a65b-4f68-b498-dd83e37a1a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303370951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3303370951
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2759079851
Short name T194
Test name
Test status
Simulation time 42311144 ps
CPU time 0.86 seconds
Started Apr 25 01:00:27 PM PDT 24
Finished Apr 25 01:00:30 PM PDT 24
Peak memory 215148 kb
Host smart-0fcde7df-9f27-4df7-b23e-b8efd132f97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759079851 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2759079851
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.4226117641
Short name T321
Test name
Test status
Simulation time 15971547 ps
CPU time 0.96 seconds
Started Apr 25 01:00:21 PM PDT 24
Finished Apr 25 01:00:24 PM PDT 24
Peak memory 215180 kb
Host smart-5a965e87-9ea0-4b2d-94dc-28b70599899b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226117641 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.4226117641
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.4129692704
Short name T258
Test name
Test status
Simulation time 374911338 ps
CPU time 2.49 seconds
Started Apr 25 01:00:23 PM PDT 24
Finished Apr 25 01:00:27 PM PDT 24
Peak memory 215100 kb
Host smart-431ce253-b5f3-47fe-b0da-1d66e2c77bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129692704 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.4129692704
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2420731879
Short name T190
Test name
Test status
Simulation time 654927054131 ps
CPU time 1774.45 seconds
Started Apr 25 01:00:19 PM PDT 24
Finished Apr 25 01:29:56 PM PDT 24
Peak memory 227640 kb
Host smart-d21f8570-d207-4371-a3ae-614df8d5322d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420731879 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2420731879
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3245881561
Short name T122
Test name
Test status
Simulation time 38411570 ps
CPU time 1.14 seconds
Started Apr 25 01:00:25 PM PDT 24
Finished Apr 25 01:00:27 PM PDT 24
Peak memory 215560 kb
Host smart-dd40124a-780a-45fc-86c2-a1f566480d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245881561 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3245881561
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.659924155
Short name T774
Test name
Test status
Simulation time 78631201 ps
CPU time 0.86 seconds
Started Apr 25 01:00:26 PM PDT 24
Finished Apr 25 01:00:29 PM PDT 24
Peak memory 206584 kb
Host smart-a9d72673-02f0-41cf-9a37-4b333d2edf16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659924155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.659924155
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.920650159
Short name T657
Test name
Test status
Simulation time 25974045 ps
CPU time 0.83 seconds
Started Apr 25 01:00:32 PM PDT 24
Finished Apr 25 01:00:38 PM PDT 24
Peak memory 215272 kb
Host smart-56ffed2c-69b8-4a59-a5f5-ba10cf405f44
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920650159 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.920650159
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_err.3724663788
Short name T780
Test name
Test status
Simulation time 27447228 ps
CPU time 0.94 seconds
Started Apr 25 01:00:17 PM PDT 24
Finished Apr 25 01:00:21 PM PDT 24
Peak memory 217836 kb
Host smart-8b713789-0ef3-411d-a15f-a9e61ad34818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724663788 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3724663788
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.4012145216
Short name T502
Test name
Test status
Simulation time 35912989 ps
CPU time 1.33 seconds
Started Apr 25 01:00:16 PM PDT 24
Finished Apr 25 01:00:20 PM PDT 24
Peak memory 218024 kb
Host smart-7d132901-ece5-46f5-a836-931292998020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012145216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.4012145216
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.306798193
Short name T82
Test name
Test status
Simulation time 48463874 ps
CPU time 0.85 seconds
Started Apr 25 01:00:30 PM PDT 24
Finished Apr 25 01:00:35 PM PDT 24
Peak memory 215564 kb
Host smart-deac9ea0-6aec-457c-8670-dff48fbf6896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306798193 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.306798193
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2792229160
Short name T339
Test name
Test status
Simulation time 27703951 ps
CPU time 0.93 seconds
Started Apr 25 01:00:33 PM PDT 24
Finished Apr 25 01:00:39 PM PDT 24
Peak memory 215160 kb
Host smart-4c72bccd-6b1f-431b-8d9f-f638e6c70003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792229160 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2792229160
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1340946062
Short name T672
Test name
Test status
Simulation time 153671546 ps
CPU time 2.22 seconds
Started Apr 25 01:00:31 PM PDT 24
Finished Apr 25 01:00:37 PM PDT 24
Peak memory 215056 kb
Host smart-01fe88aa-be6b-4143-9afa-c9de92b8504b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340946062 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1340946062
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2640569658
Short name T664
Test name
Test status
Simulation time 35384655653 ps
CPU time 918.8 seconds
Started Apr 25 01:00:21 PM PDT 24
Finished Apr 25 01:15:41 PM PDT 24
Peak memory 218216 kb
Host smart-e85294f3-c21d-4e7f-88b2-a30e458b684c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640569658 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2640569658
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.19771362
Short name T827
Test name
Test status
Simulation time 42378345 ps
CPU time 1.16 seconds
Started Apr 25 01:00:24 PM PDT 24
Finished Apr 25 01:00:27 PM PDT 24
Peak memory 215512 kb
Host smart-c99c8ec9-a10b-4084-a414-428413009497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19771362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.19771362
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2763136809
Short name T800
Test name
Test status
Simulation time 32181692 ps
CPU time 0.81 seconds
Started Apr 25 01:00:29 PM PDT 24
Finished Apr 25 01:00:32 PM PDT 24
Peak memory 206752 kb
Host smart-674ec0bf-9070-4a78-a7f1-e8ce7477eef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763136809 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2763136809
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2104121366
Short name T581
Test name
Test status
Simulation time 92862344 ps
CPU time 0.84 seconds
Started Apr 25 01:00:27 PM PDT 24
Finished Apr 25 01:00:30 PM PDT 24
Peak memory 215744 kb
Host smart-51851184-5e34-4e9c-9ab7-34dc9ac0fd61
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104121366 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2104121366
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1264299817
Short name T172
Test name
Test status
Simulation time 48842902 ps
CPU time 1.15 seconds
Started Apr 25 01:00:24 PM PDT 24
Finished Apr 25 01:00:27 PM PDT 24
Peak memory 216648 kb
Host smart-401fc1b1-b45b-4966-a77c-10dafd66cda1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264299817 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1264299817
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3694180402
Short name T566
Test name
Test status
Simulation time 22691777 ps
CPU time 0.92 seconds
Started Apr 25 01:00:22 PM PDT 24
Finished Apr 25 01:00:25 PM PDT 24
Peak memory 218008 kb
Host smart-8494c5c0-a6cb-4dea-a5e9-f325e9bfe425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694180402 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3694180402
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.4071392636
Short name T826
Test name
Test status
Simulation time 189996891 ps
CPU time 1.63 seconds
Started Apr 25 01:00:19 PM PDT 24
Finished Apr 25 01:00:23 PM PDT 24
Peak memory 218240 kb
Host smart-afdb2ff5-8ffd-4255-80f6-30997f2237b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071392636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.4071392636
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.234568945
Short name T470
Test name
Test status
Simulation time 27712236 ps
CPU time 0.96 seconds
Started Apr 25 01:00:45 PM PDT 24
Finished Apr 25 01:00:49 PM PDT 24
Peak memory 215456 kb
Host smart-5950d015-69f0-4fc9-a4f0-8bca59fb9f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234568945 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.234568945
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1010187051
Short name T519
Test name
Test status
Simulation time 15193508 ps
CPU time 0.93 seconds
Started Apr 25 01:00:27 PM PDT 24
Finished Apr 25 01:00:30 PM PDT 24
Peak memory 215172 kb
Host smart-a928d4ab-ecd5-40d1-9028-da5f462cbf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010187051 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1010187051
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.536321758
Short name T646
Test name
Test status
Simulation time 478661552 ps
CPU time 3.12 seconds
Started Apr 25 01:00:17 PM PDT 24
Finished Apr 25 01:00:23 PM PDT 24
Peak memory 215152 kb
Host smart-d204a2f2-8e1c-4267-a6df-b372cb58a02f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536321758 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.536321758
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1458574050
Short name T141
Test name
Test status
Simulation time 819226265297 ps
CPU time 1950.12 seconds
Started Apr 25 01:00:34 PM PDT 24
Finished Apr 25 01:33:09 PM PDT 24
Peak memory 227224 kb
Host smart-5563881a-c77d-416a-a54b-05b690fefa71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458574050 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1458574050
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3161478225
Short name T287
Test name
Test status
Simulation time 70082700 ps
CPU time 1.11 seconds
Started Apr 25 01:00:30 PM PDT 24
Finished Apr 25 01:00:34 PM PDT 24
Peak memory 215544 kb
Host smart-f9b54278-2042-47a8-a281-fb750f1e509e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161478225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3161478225
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.769481338
Short name T823
Test name
Test status
Simulation time 64651586 ps
CPU time 0.86 seconds
Started Apr 25 01:00:26 PM PDT 24
Finished Apr 25 01:00:36 PM PDT 24
Peak memory 214768 kb
Host smart-f8ff7f72-bac0-49e1-86b6-065b98ca36fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769481338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.769481338
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3991869363
Short name T504
Test name
Test status
Simulation time 20203630 ps
CPU time 0.88 seconds
Started Apr 25 01:00:50 PM PDT 24
Finished Apr 25 01:00:53 PM PDT 24
Peak memory 216132 kb
Host smart-4e41c56a-06d6-44b8-a064-030ca6bbe78d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991869363 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3991869363
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1366534615
Short name T80
Test name
Test status
Simulation time 42143652 ps
CPU time 1.3 seconds
Started Apr 25 01:00:28 PM PDT 24
Finished Apr 25 01:00:31 PM PDT 24
Peak memory 218168 kb
Host smart-d4c05b14-aa19-4449-9810-b6c43b9346ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366534615 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1366534615
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1211441608
Short name T79
Test name
Test status
Simulation time 19236747 ps
CPU time 1.11 seconds
Started Apr 25 01:00:36 PM PDT 24
Finished Apr 25 01:00:41 PM PDT 24
Peak memory 218472 kb
Host smart-b68b1763-3340-4b4d-ae62-bac727d582e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211441608 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1211441608
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3974660209
Short name T378
Test name
Test status
Simulation time 68331564 ps
CPU time 1.02 seconds
Started Apr 25 01:00:22 PM PDT 24
Finished Apr 25 01:00:25 PM PDT 24
Peak memory 216948 kb
Host smart-1a65a372-8be3-4cd4-9731-f8aa5f4d70e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974660209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3974660209
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2315413472
Short name T2
Test name
Test status
Simulation time 22949979 ps
CPU time 1.09 seconds
Started Apr 25 01:00:50 PM PDT 24
Finished Apr 25 01:00:58 PM PDT 24
Peak memory 215240 kb
Host smart-24653fa2-85d2-4917-8bd3-39cba29d731a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315413472 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2315413472
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.383215813
Short name T385
Test name
Test status
Simulation time 17340348 ps
CPU time 0.98 seconds
Started Apr 25 01:00:42 PM PDT 24
Finished Apr 25 01:00:47 PM PDT 24
Peak memory 215112 kb
Host smart-95da98bb-8c65-49da-93a9-04b9226a0453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383215813 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.383215813
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3064074528
Short name T576
Test name
Test status
Simulation time 253241304 ps
CPU time 2.92 seconds
Started Apr 25 01:00:33 PM PDT 24
Finished Apr 25 01:00:42 PM PDT 24
Peak memory 219832 kb
Host smart-3a7711af-0807-4ff1-9cac-f8f2f340e8a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064074528 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3064074528
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1882423218
Short name T618
Test name
Test status
Simulation time 32831414854 ps
CPU time 396.78 seconds
Started Apr 25 01:00:43 PM PDT 24
Finished Apr 25 01:07:23 PM PDT 24
Peak memory 217488 kb
Host smart-6e8f0220-53da-42a4-a0e9-8b4fea9ad063
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882423218 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1882423218
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2624879201
Short name T28
Test name
Test status
Simulation time 50506896 ps
CPU time 1.29 seconds
Started Apr 25 01:00:27 PM PDT 24
Finished Apr 25 01:00:30 PM PDT 24
Peak memory 215548 kb
Host smart-310b846d-aaab-4dca-93df-8a073d286773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624879201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2624879201
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2864803367
Short name T62
Test name
Test status
Simulation time 49491890 ps
CPU time 0.88 seconds
Started Apr 25 01:00:27 PM PDT 24
Finished Apr 25 01:00:30 PM PDT 24
Peak memory 214720 kb
Host smart-4668c89d-703e-45f0-8d26-de16fdb87288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864803367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2864803367
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3040230751
Short name T175
Test name
Test status
Simulation time 34056040 ps
CPU time 0.93 seconds
Started Apr 25 01:00:28 PM PDT 24
Finished Apr 25 01:00:31 PM PDT 24
Peak memory 216080 kb
Host smart-95b9c91f-134e-41c0-b013-ba2807deb3c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040230751 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3040230751
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1344109260
Short name T108
Test name
Test status
Simulation time 51062905 ps
CPU time 1.13 seconds
Started Apr 25 01:00:32 PM PDT 24
Finished Apr 25 01:00:38 PM PDT 24
Peak memory 216588 kb
Host smart-3fef3c93-7320-49df-bb26-36f49b371cfa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344109260 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1344109260
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2997471434
Short name T304
Test name
Test status
Simulation time 132266516 ps
CPU time 1.03 seconds
Started Apr 25 01:00:42 PM PDT 24
Finished Apr 25 01:00:47 PM PDT 24
Peak memory 220572 kb
Host smart-aa911a69-afd1-4341-a208-5b7df0d506e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997471434 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2997471434
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1206451949
Short name T682
Test name
Test status
Simulation time 50703427 ps
CPU time 1.1 seconds
Started Apr 25 01:00:38 PM PDT 24
Finished Apr 25 01:00:43 PM PDT 24
Peak memory 216816 kb
Host smart-d7b42411-4901-4cac-902f-c0a7c95ea0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206451949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1206451949
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3901862936
Short name T806
Test name
Test status
Simulation time 26067000 ps
CPU time 0.94 seconds
Started Apr 25 01:00:23 PM PDT 24
Finished Apr 25 01:00:25 PM PDT 24
Peak memory 215620 kb
Host smart-89246ee9-e35d-4d8a-bb06-08bb727f357e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901862936 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3901862936
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1527692730
Short name T335
Test name
Test status
Simulation time 21354318 ps
CPU time 0.94 seconds
Started Apr 25 01:00:33 PM PDT 24
Finished Apr 25 01:00:39 PM PDT 24
Peak memory 215176 kb
Host smart-09c876c1-f321-4132-ad61-3d1a0aaa381c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527692730 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1527692730
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2433659497
Short name T616
Test name
Test status
Simulation time 278445815 ps
CPU time 3.21 seconds
Started Apr 25 01:00:34 PM PDT 24
Finished Apr 25 01:00:42 PM PDT 24
Peak memory 216896 kb
Host smart-7e51b16b-8ab5-4f78-b624-3322da16dc09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433659497 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2433659497
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1324642639
Short name T706
Test name
Test status
Simulation time 370767071854 ps
CPU time 1040.07 seconds
Started Apr 25 01:00:38 PM PDT 24
Finished Apr 25 01:18:01 PM PDT 24
Peak memory 220488 kb
Host smart-ed02f857-13ac-4b77-acf5-b68be638ccfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324642639 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1324642639
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2905002313
Short name T809
Test name
Test status
Simulation time 23238054 ps
CPU time 1.16 seconds
Started Apr 25 01:00:37 PM PDT 24
Finished Apr 25 01:00:42 PM PDT 24
Peak memory 215660 kb
Host smart-384989db-9fde-4f8c-8ad3-c47998d8c5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905002313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2905002313
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3081868080
Short name T820
Test name
Test status
Simulation time 59107562 ps
CPU time 0.99 seconds
Started Apr 25 01:00:32 PM PDT 24
Finished Apr 25 01:00:39 PM PDT 24
Peak memory 206604 kb
Host smart-30cd942d-b195-4a36-bac5-b7035d5ee81d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081868080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3081868080
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1032835869
Short name T415
Test name
Test status
Simulation time 32780610 ps
CPU time 0.89 seconds
Started Apr 25 01:00:34 PM PDT 24
Finished Apr 25 01:00:40 PM PDT 24
Peak memory 215892 kb
Host smart-2d822661-a9c9-4e75-b3d4-6155025e1c34
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032835869 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1032835869
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2399276490
Short name T455
Test name
Test status
Simulation time 75377649 ps
CPU time 1.07 seconds
Started Apr 25 01:00:41 PM PDT 24
Finished Apr 25 01:00:46 PM PDT 24
Peak memory 218092 kb
Host smart-fcb5317d-c77b-46a2-ab6b-4560d83e8419
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399276490 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2399276490
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3070324321
Short name T662
Test name
Test status
Simulation time 31257059 ps
CPU time 1.25 seconds
Started Apr 25 01:00:33 PM PDT 24
Finished Apr 25 01:00:40 PM PDT 24
Peak memory 219472 kb
Host smart-fdbf1fed-7f87-41f4-809a-8fe239298df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070324321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3070324321
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1644932147
Short name T328
Test name
Test status
Simulation time 53607546 ps
CPU time 1.3 seconds
Started Apr 25 01:00:54 PM PDT 24
Finished Apr 25 01:00:57 PM PDT 24
Peak memory 215196 kb
Host smart-c76199d4-b7b1-45e1-985a-881f7d9eb5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644932147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1644932147
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.4282837110
Short name T410
Test name
Test status
Simulation time 22640014 ps
CPU time 1.05 seconds
Started Apr 25 01:00:25 PM PDT 24
Finished Apr 25 01:00:27 PM PDT 24
Peak memory 215436 kb
Host smart-d250a12c-9943-4bd3-b7b2-39b968fdc536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282837110 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.4282837110
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3908812585
Short name T600
Test name
Test status
Simulation time 21944979 ps
CPU time 0.96 seconds
Started Apr 25 01:00:31 PM PDT 24
Finished Apr 25 01:00:36 PM PDT 24
Peak memory 215200 kb
Host smart-26c814f5-5f1f-433d-9147-f6e50c1992bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908812585 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3908812585
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.611072376
Short name T732
Test name
Test status
Simulation time 466342859 ps
CPU time 3.07 seconds
Started Apr 25 01:00:23 PM PDT 24
Finished Apr 25 01:00:28 PM PDT 24
Peak memory 216876 kb
Host smart-84efd078-5a73-4506-9722-a9e4eac9843b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611072376 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.611072376
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3272738493
Short name T702
Test name
Test status
Simulation time 31737987830 ps
CPU time 687.77 seconds
Started Apr 25 01:00:43 PM PDT 24
Finished Apr 25 01:12:14 PM PDT 24
Peak memory 223568 kb
Host smart-bfac9816-f7a3-41e7-a137-e4235eb38bd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272738493 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3272738493
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert_test.347921012
Short name T487
Test name
Test status
Simulation time 39658714 ps
CPU time 0.86 seconds
Started Apr 25 01:00:47 PM PDT 24
Finished Apr 25 01:00:55 PM PDT 24
Peak memory 215112 kb
Host smart-70d75bb2-56c0-4c1f-bb20-d98254da3697
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347921012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.347921012
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3806276391
Short name T173
Test name
Test status
Simulation time 18602354 ps
CPU time 0.88 seconds
Started Apr 25 01:00:45 PM PDT 24
Finished Apr 25 01:00:49 PM PDT 24
Peak memory 216008 kb
Host smart-9d3b2a08-2ef9-4d27-9598-dc07b48314c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806276391 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3806276391
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3709922723
Short name T591
Test name
Test status
Simulation time 44626753 ps
CPU time 1.05 seconds
Started Apr 25 01:00:28 PM PDT 24
Finished Apr 25 01:00:31 PM PDT 24
Peak memory 217816 kb
Host smart-7212792e-9e79-4960-bc0d-0e39189e49a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709922723 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3709922723
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3654605331
Short name T6
Test name
Test status
Simulation time 53412084 ps
CPU time 1.18 seconds
Started Apr 25 01:00:27 PM PDT 24
Finished Apr 25 01:00:30 PM PDT 24
Peak memory 219412 kb
Host smart-bb1e7457-9c05-4f32-95b4-18f4611e2904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654605331 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3654605331
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3047238456
Short name T799
Test name
Test status
Simulation time 26263570 ps
CPU time 0.96 seconds
Started Apr 25 01:00:26 PM PDT 24
Finished Apr 25 01:00:29 PM PDT 24
Peak memory 216920 kb
Host smart-92109349-375b-4ae9-aff2-e8282753be94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047238456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3047238456
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1144597878
Short name T78
Test name
Test status
Simulation time 24546274 ps
CPU time 0.92 seconds
Started Apr 25 01:00:43 PM PDT 24
Finished Apr 25 01:00:47 PM PDT 24
Peak memory 215664 kb
Host smart-98a18f73-939d-48cf-a501-03523b9bc686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144597878 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1144597878
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1974141444
Short name T794
Test name
Test status
Simulation time 76978655 ps
CPU time 0.88 seconds
Started Apr 25 01:00:17 PM PDT 24
Finished Apr 25 01:00:21 PM PDT 24
Peak memory 215132 kb
Host smart-707cd200-199b-461e-bcea-e0fb55f06fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974141444 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1974141444
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1631148815
Short name T379
Test name
Test status
Simulation time 24362100 ps
CPU time 1.05 seconds
Started Apr 25 01:00:42 PM PDT 24
Finished Apr 25 01:00:47 PM PDT 24
Peak memory 215148 kb
Host smart-6551fdbc-65e8-4c01-92eb-bf961c0a45bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631148815 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1631148815
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.75761943
Short name T200
Test name
Test status
Simulation time 138545475205 ps
CPU time 1539.72 seconds
Started Apr 25 01:00:25 PM PDT 24
Finished Apr 25 01:26:06 PM PDT 24
Peak memory 224264 kb
Host smart-94fb3529-a5e3-459d-a402-7e6964f1eaf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75761943 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.75761943
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.152887793
Short name T460
Test name
Test status
Simulation time 129543370 ps
CPU time 1.22 seconds
Started Apr 25 01:00:36 PM PDT 24
Finished Apr 25 01:00:42 PM PDT 24
Peak memory 215520 kb
Host smart-d3c63dc0-2e82-4d31-8f61-4163db8dd9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152887793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.152887793
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_disable.1799156107
Short name T134
Test name
Test status
Simulation time 37512086 ps
CPU time 0.85 seconds
Started Apr 25 01:00:48 PM PDT 24
Finished Apr 25 01:00:51 PM PDT 24
Peak memory 216008 kb
Host smart-2a06c4f7-1c70-41c8-86b1-20bc6fa160fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799156107 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1799156107
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.660564201
Short name T545
Test name
Test status
Simulation time 76946418 ps
CPU time 1.31 seconds
Started Apr 25 01:00:32 PM PDT 24
Finished Apr 25 01:00:39 PM PDT 24
Peak memory 218044 kb
Host smart-4c9485db-688a-4777-bdf9-9c88d071cb08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660564201 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.660564201
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.358215982
Short name T793
Test name
Test status
Simulation time 19769474 ps
CPU time 0.99 seconds
Started Apr 25 01:00:30 PM PDT 24
Finished Apr 25 01:00:35 PM PDT 24
Peak memory 218128 kb
Host smart-75cc1052-195c-469d-9f26-ee9929ebd073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358215982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.358215982
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3244028203
Short name T743
Test name
Test status
Simulation time 914563041 ps
CPU time 5.31 seconds
Started Apr 25 01:00:55 PM PDT 24
Finished Apr 25 01:01:02 PM PDT 24
Peak memory 219464 kb
Host smart-889c7a79-731a-49e2-afcb-25e4c99dc9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244028203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3244028203
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3038094074
Short name T425
Test name
Test status
Simulation time 36472625 ps
CPU time 0.85 seconds
Started Apr 25 01:00:52 PM PDT 24
Finished Apr 25 01:00:55 PM PDT 24
Peak memory 215364 kb
Host smart-790f31f7-39f5-4aca-b1d3-f05d68eff617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038094074 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3038094074
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.570231033
Short name T23
Test name
Test status
Simulation time 16466920 ps
CPU time 1.01 seconds
Started Apr 25 01:00:47 PM PDT 24
Finished Apr 25 01:00:50 PM PDT 24
Peak memory 215112 kb
Host smart-19d79883-7d4b-40be-95f2-1b2546319c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570231033 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.570231033
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.643281394
Short name T524
Test name
Test status
Simulation time 166115955 ps
CPU time 1.02 seconds
Started Apr 25 01:00:28 PM PDT 24
Finished Apr 25 01:00:31 PM PDT 24
Peak memory 215124 kb
Host smart-ac2b77f5-a5d2-4e93-9023-17b7990b3163
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643281394 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.643281394
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3013407583
Short name T740
Test name
Test status
Simulation time 52453885569 ps
CPU time 323.69 seconds
Started Apr 25 01:00:35 PM PDT 24
Finished Apr 25 01:06:03 PM PDT 24
Peak memory 217508 kb
Host smart-fcd0c10d-0324-4a88-a09e-5250a08e8ca4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013407583 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3013407583
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.30614945
Short name T154
Test name
Test status
Simulation time 39688385 ps
CPU time 1.21 seconds
Started Apr 25 01:00:43 PM PDT 24
Finished Apr 25 01:00:48 PM PDT 24
Peak memory 215520 kb
Host smart-bff2e98e-604a-48cf-b1bd-59fc237c2954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30614945 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.30614945
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3470830190
Short name T698
Test name
Test status
Simulation time 65600179 ps
CPU time 0.99 seconds
Started Apr 25 01:00:32 PM PDT 24
Finished Apr 25 01:00:39 PM PDT 24
Peak memory 206572 kb
Host smart-c5d52d32-7c03-4afe-8986-b94350bf1845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470830190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3470830190
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.460860883
Short name T181
Test name
Test status
Simulation time 19266050 ps
CPU time 0.87 seconds
Started Apr 25 01:00:29 PM PDT 24
Finished Apr 25 01:00:33 PM PDT 24
Peak memory 216040 kb
Host smart-a59e28a4-56f0-4409-a444-b6b12b7da115
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460860883 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.460860883
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_err.71559366
Short name T124
Test name
Test status
Simulation time 19773315 ps
CPU time 1.06 seconds
Started Apr 25 01:00:49 PM PDT 24
Finished Apr 25 01:00:52 PM PDT 24
Peak memory 218400 kb
Host smart-93f8d7f1-da07-4a1e-8a63-484fa80c06b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71559366 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.71559366
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1166893915
Short name T572
Test name
Test status
Simulation time 47098575 ps
CPU time 1.12 seconds
Started Apr 25 01:00:40 PM PDT 24
Finished Apr 25 01:00:45 PM PDT 24
Peak memory 216956 kb
Host smart-81fd3b7a-ae5c-4658-b921-fc6488fab544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166893915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1166893915
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1457883969
Short name T31
Test name
Test status
Simulation time 22946485 ps
CPU time 1.04 seconds
Started Apr 25 01:00:39 PM PDT 24
Finished Apr 25 01:00:43 PM PDT 24
Peak memory 215708 kb
Host smart-ee6549d9-43dd-4edb-b4d3-ec1439a58b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457883969 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1457883969
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3294857494
Short name T701
Test name
Test status
Simulation time 24820232 ps
CPU time 0.95 seconds
Started Apr 25 01:00:36 PM PDT 24
Finished Apr 25 01:00:41 PM PDT 24
Peak memory 215148 kb
Host smart-24ea61e2-2146-4710-9090-5e53437a7ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294857494 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3294857494
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.651924187
Short name T520
Test name
Test status
Simulation time 1740430381 ps
CPU time 4.71 seconds
Started Apr 25 01:00:37 PM PDT 24
Finished Apr 25 01:00:46 PM PDT 24
Peak memory 216784 kb
Host smart-3300edd8-4a40-4d07-b4dc-1758aa8f2576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651924187 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.651924187
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1335148342
Short name T690
Test name
Test status
Simulation time 39551666494 ps
CPU time 247.61 seconds
Started Apr 25 01:00:24 PM PDT 24
Finished Apr 25 01:04:33 PM PDT 24
Peak memory 218624 kb
Host smart-aa8088ac-77e4-41a8-98b9-0a44375c8bd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335148342 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1335148342
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert_test.3686316927
Short name T308
Test name
Test status
Simulation time 31219340 ps
CPU time 0.91 seconds
Started Apr 25 12:59:39 PM PDT 24
Finished Apr 25 12:59:43 PM PDT 24
Peak memory 206532 kb
Host smart-eb08965a-e964-4d72-bbb8-6d357a0c2e6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686316927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3686316927
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3901919405
Short name T187
Test name
Test status
Simulation time 12661680 ps
CPU time 0.92 seconds
Started Apr 25 12:59:34 PM PDT 24
Finished Apr 25 12:59:36 PM PDT 24
Peak memory 216256 kb
Host smart-e37cf562-9f5d-4b7e-b163-d3376978ec41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901919405 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3901919405
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3214703804
Short name T436
Test name
Test status
Simulation time 70129585 ps
CPU time 1.22 seconds
Started Apr 25 12:59:36 PM PDT 24
Finished Apr 25 12:59:39 PM PDT 24
Peak memory 218000 kb
Host smart-8848ea1b-2b9a-41d7-a239-6a844d9c0faa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214703804 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3214703804
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1796620584
Short name T440
Test name
Test status
Simulation time 19612816 ps
CPU time 1.15 seconds
Started Apr 25 12:59:54 PM PDT 24
Finished Apr 25 12:59:57 PM PDT 24
Peak memory 223804 kb
Host smart-f59bb1df-8402-4b2a-90de-3d26dd3f7da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796620584 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1796620584
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2024257149
Short name T526
Test name
Test status
Simulation time 63754256 ps
CPU time 1.35 seconds
Started Apr 25 12:59:53 PM PDT 24
Finished Apr 25 12:59:56 PM PDT 24
Peak memory 217988 kb
Host smart-6e8395ab-48e6-43eb-862b-db35801dfb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024257149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2024257149
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2383430653
Short name T66
Test name
Test status
Simulation time 32210274 ps
CPU time 0.88 seconds
Started Apr 25 01:00:02 PM PDT 24
Finished Apr 25 01:00:05 PM PDT 24
Peak memory 215384 kb
Host smart-874867e5-2d9e-4162-b9dc-221e0a95a8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383430653 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2383430653
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3596383940
Short name T750
Test name
Test status
Simulation time 67726683 ps
CPU time 0.9 seconds
Started Apr 25 12:59:21 PM PDT 24
Finished Apr 25 12:59:24 PM PDT 24
Peak memory 206968 kb
Host smart-0b4a850c-95d5-4925-bddf-176032702aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596383940 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3596383940
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.158325521
Short name T486
Test name
Test status
Simulation time 47667304 ps
CPU time 0.88 seconds
Started Apr 25 12:59:43 PM PDT 24
Finished Apr 25 12:59:45 PM PDT 24
Peak memory 214980 kb
Host smart-77ec839a-de12-480d-8806-ca1037e75ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158325521 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.158325521
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1114408286
Short name T213
Test name
Test status
Simulation time 1476639821 ps
CPU time 2.96 seconds
Started Apr 25 12:59:48 PM PDT 24
Finished Apr 25 12:59:53 PM PDT 24
Peak memory 217004 kb
Host smart-4279ac0e-aaf3-4bae-a7df-92df7f421cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114408286 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1114408286
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.696722990
Short name T753
Test name
Test status
Simulation time 189712167898 ps
CPU time 677.27 seconds
Started Apr 25 12:59:50 PM PDT 24
Finished Apr 25 01:11:09 PM PDT 24
Peak memory 220688 kb
Host smart-b966367d-5e6a-4416-983d-8b000eaa7ec1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696722990 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.696722990
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.25735714
Short name T650
Test name
Test status
Simulation time 18516157 ps
CPU time 1.14 seconds
Started Apr 25 01:00:36 PM PDT 24
Finished Apr 25 01:00:42 PM PDT 24
Peak memory 232556 kb
Host smart-6cde7efb-091a-4fb2-8b14-7cf7808c5cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25735714 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.25735714
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1609115514
Short name T766
Test name
Test status
Simulation time 38046461 ps
CPU time 1.41 seconds
Started Apr 25 01:00:41 PM PDT 24
Finished Apr 25 01:00:46 PM PDT 24
Peak memory 216828 kb
Host smart-c66f036d-b710-4030-ba7b-1f96a4adf970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609115514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1609115514
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.1719749564
Short name T120
Test name
Test status
Simulation time 62254930 ps
CPU time 1.14 seconds
Started Apr 25 01:00:25 PM PDT 24
Finished Apr 25 01:00:28 PM PDT 24
Peak memory 219292 kb
Host smart-8126a131-b78f-43fc-b210-9c9cdfc1db7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719749564 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1719749564
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3995409009
Short name T259
Test name
Test status
Simulation time 61537073 ps
CPU time 1.6 seconds
Started Apr 25 01:00:45 PM PDT 24
Finished Apr 25 01:00:49 PM PDT 24
Peak memory 218216 kb
Host smart-f46e7b2f-b3e2-4b4b-9378-6be1ceb53ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995409009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3995409009
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.3838085151
Short name T81
Test name
Test status
Simulation time 196867740 ps
CPU time 1.11 seconds
Started Apr 25 01:00:35 PM PDT 24
Finished Apr 25 01:00:41 PM PDT 24
Peak memory 220552 kb
Host smart-a46283a7-90e1-4231-b036-a9bd73f30114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838085151 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3838085151
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3224925285
Short name T356
Test name
Test status
Simulation time 161179233 ps
CPU time 1.07 seconds
Started Apr 25 01:00:32 PM PDT 24
Finished Apr 25 01:00:38 PM PDT 24
Peak memory 215216 kb
Host smart-05d2b666-2c6b-489f-83ff-14dd8c57ca88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224925285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3224925285
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.254466689
Short name T155
Test name
Test status
Simulation time 23538396 ps
CPU time 0.89 seconds
Started Apr 25 01:00:56 PM PDT 24
Finished Apr 25 01:00:59 PM PDT 24
Peak memory 218260 kb
Host smart-540f96d4-73a5-48b8-a3cd-36719cc0badf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254466689 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.254466689
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2102948750
Short name T704
Test name
Test status
Simulation time 48586902 ps
CPU time 1.21 seconds
Started Apr 25 01:00:51 PM PDT 24
Finished Apr 25 01:00:54 PM PDT 24
Peak memory 218316 kb
Host smart-395b7605-5153-414f-9e08-8fb77f1254dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102948750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2102948750
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.1484522454
Short name T323
Test name
Test status
Simulation time 18618983 ps
CPU time 1.1 seconds
Started Apr 25 01:00:39 PM PDT 24
Finished Apr 25 01:00:43 PM PDT 24
Peak memory 218104 kb
Host smart-7d34543d-ac71-43a8-84bc-4b596e9f3368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484522454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1484522454
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3726515732
Short name T442
Test name
Test status
Simulation time 44494377 ps
CPU time 1.14 seconds
Started Apr 25 01:00:43 PM PDT 24
Finished Apr 25 01:00:48 PM PDT 24
Peak memory 219496 kb
Host smart-1c952b2a-4b16-4bb4-b035-25156d88924c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726515732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3726515732
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.1103223835
Short name T417
Test name
Test status
Simulation time 23779810 ps
CPU time 0.89 seconds
Started Apr 25 01:00:43 PM PDT 24
Finished Apr 25 01:00:48 PM PDT 24
Peak memory 217884 kb
Host smart-1d1704ce-1baa-4d11-9b1b-1ad290f2663e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103223835 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1103223835
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3147612179
Short name T481
Test name
Test status
Simulation time 267522041 ps
CPU time 1.83 seconds
Started Apr 25 01:00:47 PM PDT 24
Finished Apr 25 01:00:51 PM PDT 24
Peak memory 218280 kb
Host smart-a53a33fc-ad49-482d-8ddc-574802019162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147612179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3147612179
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.1967689973
Short name T178
Test name
Test status
Simulation time 25746845 ps
CPU time 1.16 seconds
Started Apr 25 01:00:36 PM PDT 24
Finished Apr 25 01:00:41 PM PDT 24
Peak memory 219728 kb
Host smart-152ec7c7-c6ad-4f3f-8bb3-d8f6c9076c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967689973 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1967689973
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2675203203
Short name T635
Test name
Test status
Simulation time 74732127 ps
CPU time 1.73 seconds
Started Apr 25 01:00:40 PM PDT 24
Finished Apr 25 01:00:45 PM PDT 24
Peak memory 218292 kb
Host smart-ef893daa-d82f-4fc8-b147-14bfb8432eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675203203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2675203203
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2275545324
Short name T102
Test name
Test status
Simulation time 33041308 ps
CPU time 0.9 seconds
Started Apr 25 01:00:40 PM PDT 24
Finished Apr 25 01:00:44 PM PDT 24
Peak memory 219356 kb
Host smart-50dee89e-72af-4e35-9a5d-19d9e850d89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275545324 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2275545324
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3969905323
Short name T785
Test name
Test status
Simulation time 65328732 ps
CPU time 1.33 seconds
Started Apr 25 01:00:41 PM PDT 24
Finished Apr 25 01:00:46 PM PDT 24
Peak memory 216968 kb
Host smart-63d46ee2-a80c-4dcb-b34b-e34f585ced45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969905323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3969905323
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.3806470041
Short name T829
Test name
Test status
Simulation time 21579629 ps
CPU time 1.01 seconds
Started Apr 25 01:00:40 PM PDT 24
Finished Apr 25 01:00:44 PM PDT 24
Peak memory 223836 kb
Host smart-5e49c981-3847-4fca-8f67-6b5a367869f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806470041 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3806470041
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1490319215
Short name T375
Test name
Test status
Simulation time 28468280 ps
CPU time 1.13 seconds
Started Apr 25 01:00:45 PM PDT 24
Finished Apr 25 01:00:49 PM PDT 24
Peak memory 216756 kb
Host smart-d0d559d7-2a4f-4f11-8119-91ce757b84fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490319215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1490319215
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.2575356725
Short name T5
Test name
Test status
Simulation time 23149431 ps
CPU time 0.94 seconds
Started Apr 25 01:00:33 PM PDT 24
Finished Apr 25 01:00:39 PM PDT 24
Peak memory 218360 kb
Host smart-f963b036-c631-45d1-a559-0560607dbe17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575356725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2575356725
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2376411146
Short name T754
Test name
Test status
Simulation time 116287862 ps
CPU time 1.46 seconds
Started Apr 25 01:00:35 PM PDT 24
Finished Apr 25 01:00:41 PM PDT 24
Peak memory 218268 kb
Host smart-cdbb58b2-bd76-47e5-9d21-5d0d51f51b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376411146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2376411146
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3599888894
Short name T244
Test name
Test status
Simulation time 79875705 ps
CPU time 1.1 seconds
Started Apr 25 12:59:53 PM PDT 24
Finished Apr 25 12:59:55 PM PDT 24
Peak memory 215536 kb
Host smart-e669d597-8dea-41d0-bbe4-ef50567f9a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599888894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3599888894
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3392373989
Short name T548
Test name
Test status
Simulation time 19429872 ps
CPU time 0.98 seconds
Started Apr 25 12:59:38 PM PDT 24
Finished Apr 25 12:59:42 PM PDT 24
Peak memory 206568 kb
Host smart-be31174d-7491-4127-ba85-a560b13dce4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392373989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3392373989
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1697474252
Short name T512
Test name
Test status
Simulation time 11534934 ps
CPU time 0.85 seconds
Started Apr 25 12:59:57 PM PDT 24
Finished Apr 25 12:59:59 PM PDT 24
Peak memory 216056 kb
Host smart-11acab3d-c98a-4667-8c9f-3ec9d54946f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697474252 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1697474252
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3821956196
Short name T176
Test name
Test status
Simulation time 79279381 ps
CPU time 0.95 seconds
Started Apr 25 12:59:42 PM PDT 24
Finished Apr 25 12:59:45 PM PDT 24
Peak memory 217988 kb
Host smart-151221fc-0df1-42b5-93b7-61541e782449
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821956196 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3821956196
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.441268121
Short name T49
Test name
Test status
Simulation time 22677717 ps
CPU time 1.06 seconds
Started Apr 25 12:59:35 PM PDT 24
Finished Apr 25 12:59:38 PM PDT 24
Peak memory 223880 kb
Host smart-76c21e3a-b913-4444-8e26-6c6834740bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441268121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.441268121
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2170582297
Short name T500
Test name
Test status
Simulation time 113814211 ps
CPU time 1.3 seconds
Started Apr 25 12:59:50 PM PDT 24
Finished Apr 25 12:59:53 PM PDT 24
Peak memory 217996 kb
Host smart-968400b1-ec00-4104-b3d4-870cab0a7706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170582297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2170582297
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3224162731
Short name T605
Test name
Test status
Simulation time 27377999 ps
CPU time 1.08 seconds
Started Apr 25 12:59:43 PM PDT 24
Finished Apr 25 12:59:46 PM PDT 24
Peak memory 223892 kb
Host smart-b94163f5-a7b2-41f0-8acb-470895ac1154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224162731 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3224162731
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.159484258
Short name T24
Test name
Test status
Simulation time 19653169 ps
CPU time 1.03 seconds
Started Apr 25 12:59:27 PM PDT 24
Finished Apr 25 12:59:29 PM PDT 24
Peak memory 206948 kb
Host smart-d4d297c3-e093-4371-b67c-f539ad9d4fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159484258 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.159484258
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1560299634
Short name T315
Test name
Test status
Simulation time 105618449 ps
CPU time 0.96 seconds
Started Apr 25 12:59:25 PM PDT 24
Finished Apr 25 12:59:27 PM PDT 24
Peak memory 215180 kb
Host smart-cbddd365-6767-4543-bc19-ca3360d88a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560299634 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1560299634
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.161151568
Short name T687
Test name
Test status
Simulation time 446178585 ps
CPU time 4.93 seconds
Started Apr 25 12:59:44 PM PDT 24
Finished Apr 25 12:59:51 PM PDT 24
Peak memory 215280 kb
Host smart-a18ec731-9b8a-4419-8269-69469bfd3ec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161151568 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.161151568
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/60.edn_err.1513548278
Short name T577
Test name
Test status
Simulation time 18958430 ps
CPU time 1.07 seconds
Started Apr 25 01:00:42 PM PDT 24
Finished Apr 25 01:00:47 PM PDT 24
Peak memory 223796 kb
Host smart-cd5bb71d-a7d5-4f4e-89c2-47cca796ce15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513548278 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1513548278
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2720463473
Short name T815
Test name
Test status
Simulation time 53437447 ps
CPU time 1.98 seconds
Started Apr 25 01:00:41 PM PDT 24
Finished Apr 25 01:00:46 PM PDT 24
Peak memory 219540 kb
Host smart-a3c37228-c841-4bf2-8352-ff6f379bfd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720463473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2720463473
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.1061958642
Short name T95
Test name
Test status
Simulation time 41353893 ps
CPU time 1.15 seconds
Started Apr 25 01:00:42 PM PDT 24
Finished Apr 25 01:00:46 PM PDT 24
Peak memory 229616 kb
Host smart-85dcdbd2-900e-4f6b-b752-c34ad9e91e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061958642 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1061958642
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.413894731
Short name T394
Test name
Test status
Simulation time 51271492 ps
CPU time 1.85 seconds
Started Apr 25 01:00:40 PM PDT 24
Finished Apr 25 01:00:45 PM PDT 24
Peak memory 218112 kb
Host smart-1c3dabea-6203-4fa2-b61e-693eb0663e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413894731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.413894731
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.3605951194
Short name T92
Test name
Test status
Simulation time 26637916 ps
CPU time 1.24 seconds
Started Apr 25 01:00:38 PM PDT 24
Finished Apr 25 01:00:42 PM PDT 24
Peak memory 219708 kb
Host smart-efe32d04-d2a6-41db-ad81-f899f1828f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605951194 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3605951194
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3740207122
Short name T418
Test name
Test status
Simulation time 109980186 ps
CPU time 0.99 seconds
Started Apr 25 01:00:42 PM PDT 24
Finished Apr 25 01:00:47 PM PDT 24
Peak memory 216920 kb
Host smart-b7476cba-d735-4cb8-81a1-c3fdc7d615c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740207122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3740207122
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.1844908286
Short name T125
Test name
Test status
Simulation time 39749295 ps
CPU time 0.96 seconds
Started Apr 25 01:00:42 PM PDT 24
Finished Apr 25 01:00:47 PM PDT 24
Peak memory 223652 kb
Host smart-2771bf7a-c863-483a-9e46-2bddb880e0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844908286 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1844908286
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1993465703
Short name T523
Test name
Test status
Simulation time 31573583 ps
CPU time 1.25 seconds
Started Apr 25 01:00:37 PM PDT 24
Finished Apr 25 01:00:42 PM PDT 24
Peak memory 216988 kb
Host smart-245e1df3-1b9c-463b-a654-2ccfd010e0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993465703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1993465703
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.3456431841
Short name T165
Test name
Test status
Simulation time 23892946 ps
CPU time 0.9 seconds
Started Apr 25 01:00:36 PM PDT 24
Finished Apr 25 01:00:41 PM PDT 24
Peak memory 218548 kb
Host smart-97cb8632-7647-427c-b644-9c78baa8b9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456431841 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3456431841
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2925730155
Short name T354
Test name
Test status
Simulation time 38759901 ps
CPU time 1.58 seconds
Started Apr 25 01:00:37 PM PDT 24
Finished Apr 25 01:00:43 PM PDT 24
Peak memory 218136 kb
Host smart-74e26a9b-e865-40cc-ba27-3d768610f82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925730155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2925730155
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.1592195782
Short name T52
Test name
Test status
Simulation time 21030928 ps
CPU time 1.2 seconds
Started Apr 25 01:00:45 PM PDT 24
Finished Apr 25 01:00:50 PM PDT 24
Peak memory 229392 kb
Host smart-902a662b-ad89-49b1-8c5a-91e066d405b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592195782 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1592195782
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2574501605
Short name T265
Test name
Test status
Simulation time 116358601 ps
CPU time 3.05 seconds
Started Apr 25 01:00:32 PM PDT 24
Finished Apr 25 01:00:41 PM PDT 24
Peak memory 218140 kb
Host smart-09373c7c-96d7-4713-9e8a-a94aa9dbe7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574501605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2574501605
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.3976412320
Short name T107
Test name
Test status
Simulation time 28396945 ps
CPU time 0.96 seconds
Started Apr 25 01:00:35 PM PDT 24
Finished Apr 25 01:00:41 PM PDT 24
Peak memory 219472 kb
Host smart-a7f4c4b0-2806-473d-916b-aebdbd9abebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976412320 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3976412320
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.828876538
Short name T406
Test name
Test status
Simulation time 60965526 ps
CPU time 1.53 seconds
Started Apr 25 01:00:38 PM PDT 24
Finished Apr 25 01:00:43 PM PDT 24
Peak memory 216984 kb
Host smart-897869f8-9f9d-4dfe-b18a-1dd49a7de224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828876538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.828876538
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.3487862233
Short name T144
Test name
Test status
Simulation time 18638077 ps
CPU time 1.03 seconds
Started Apr 25 01:00:36 PM PDT 24
Finished Apr 25 01:00:41 PM PDT 24
Peak memory 218068 kb
Host smart-a53386a4-3913-4816-a0a4-ce68704634da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487862233 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3487862233
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1760811947
Short name T272
Test name
Test status
Simulation time 75377336 ps
CPU time 2.66 seconds
Started Apr 25 01:00:31 PM PDT 24
Finished Apr 25 01:00:38 PM PDT 24
Peak memory 217068 kb
Host smart-41ae997a-8195-4499-92c0-a3390f140427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760811947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1760811947
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1266134975
Short name T737
Test name
Test status
Simulation time 84981160 ps
CPU time 1.03 seconds
Started Apr 25 01:00:38 PM PDT 24
Finished Apr 25 01:00:43 PM PDT 24
Peak memory 219440 kb
Host smart-f2ec7d26-3e5d-4b3a-a261-ed2c13b510ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266134975 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1266134975
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.757936270
Short name T275
Test name
Test status
Simulation time 92772695 ps
CPU time 1.55 seconds
Started Apr 25 01:00:52 PM PDT 24
Finished Apr 25 01:00:55 PM PDT 24
Peak memory 218608 kb
Host smart-ddc6ec35-e6ad-4bae-a3f1-2d478ac5ffb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757936270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.757936270
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.1725817808
Short name T346
Test name
Test status
Simulation time 19181446 ps
CPU time 0.99 seconds
Started Apr 25 01:00:42 PM PDT 24
Finished Apr 25 01:00:46 PM PDT 24
Peak memory 218152 kb
Host smart-478ac332-2e67-4d30-90b5-ae7282834239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725817808 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1725817808
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2128156977
Short name T670
Test name
Test status
Simulation time 48177620 ps
CPU time 1.29 seconds
Started Apr 25 01:00:50 PM PDT 24
Finished Apr 25 01:00:53 PM PDT 24
Peak memory 216588 kb
Host smart-ae14d95b-69cf-4dc2-8153-6cc77b8996c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128156977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2128156977
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2809535162
Short name T135
Test name
Test status
Simulation time 24075204 ps
CPU time 1.15 seconds
Started Apr 25 12:59:41 PM PDT 24
Finished Apr 25 12:59:45 PM PDT 24
Peak memory 215540 kb
Host smart-1ac4572d-54aa-4c27-adc2-ca6aa25036a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809535162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2809535162
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1896737519
Short name T331
Test name
Test status
Simulation time 18768668 ps
CPU time 0.95 seconds
Started Apr 25 12:59:38 PM PDT 24
Finished Apr 25 12:59:41 PM PDT 24
Peak memory 215108 kb
Host smart-f67fe328-8a9d-467a-84ca-59d5a389bcb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896737519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1896737519
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2526262024
Short name T762
Test name
Test status
Simulation time 20849842 ps
CPU time 0.85 seconds
Started Apr 25 12:59:39 PM PDT 24
Finished Apr 25 12:59:42 PM PDT 24
Peak memory 215204 kb
Host smart-ea74d7eb-6688-4816-b51b-740cdf477459
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526262024 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2526262024
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2868085526
Short name T98
Test name
Test status
Simulation time 41513283 ps
CPU time 1 seconds
Started Apr 25 12:59:35 PM PDT 24
Finished Apr 25 12:59:38 PM PDT 24
Peak memory 219104 kb
Host smart-2b892efb-87f6-4c46-8a8a-b86441832798
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868085526 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2868085526
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3477543068
Short name T168
Test name
Test status
Simulation time 20588803 ps
CPU time 1.11 seconds
Started Apr 25 12:59:32 PM PDT 24
Finished Apr 25 12:59:34 PM PDT 24
Peak memory 218508 kb
Host smart-d6be9df4-9c16-48c6-b6a2-e9bd7df1ef84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477543068 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3477543068
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1478255950
Short name T203
Test name
Test status
Simulation time 98870241 ps
CPU time 0.98 seconds
Started Apr 25 12:59:58 PM PDT 24
Finished Apr 25 01:00:00 PM PDT 24
Peak memory 216840 kb
Host smart-05de459e-d9c0-45ed-a441-8628d40931fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478255950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1478255950
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3687374888
Short name T733
Test name
Test status
Simulation time 20791121 ps
CPU time 1.2 seconds
Started Apr 25 12:59:39 PM PDT 24
Finished Apr 25 12:59:42 PM PDT 24
Peak memory 223832 kb
Host smart-1824e4ed-15be-4bca-9a96-1bd67d5e1ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687374888 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3687374888
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.4150916909
Short name T280
Test name
Test status
Simulation time 17393861 ps
CPU time 0.95 seconds
Started Apr 25 12:59:46 PM PDT 24
Finished Apr 25 12:59:49 PM PDT 24
Peak memory 206896 kb
Host smart-abc1a69b-3480-491f-bebf-46c5dec7c5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150916909 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.4150916909
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1811438687
Short name T652
Test name
Test status
Simulation time 26951726 ps
CPU time 0.92 seconds
Started Apr 25 12:59:38 PM PDT 24
Finished Apr 25 12:59:41 PM PDT 24
Peak memory 215156 kb
Host smart-ec669d1a-f928-494d-8b32-97879c58e8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811438687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1811438687
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1676185360
Short name T501
Test name
Test status
Simulation time 67881522 ps
CPU time 1.14 seconds
Started Apr 25 12:59:34 PM PDT 24
Finished Apr 25 12:59:37 PM PDT 24
Peak memory 206424 kb
Host smart-69088600-70ab-4269-b7d4-a8435a60e40d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676185360 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1676185360
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.4151041070
Short name T536
Test name
Test status
Simulation time 27080232678 ps
CPU time 693.42 seconds
Started Apr 25 12:59:38 PM PDT 24
Finished Apr 25 01:11:14 PM PDT 24
Peak memory 217640 kb
Host smart-a62e48e4-5436-4da9-9154-63d6ad23eb95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151041070 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.4151041070
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.3772581361
Short name T326
Test name
Test status
Simulation time 66894167 ps
CPU time 1.08 seconds
Started Apr 25 01:00:32 PM PDT 24
Finished Apr 25 01:00:38 PM PDT 24
Peak memory 219536 kb
Host smart-5d2b2112-d98c-433b-a408-3b3df4ff14a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772581361 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3772581361
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2892280869
Short name T478
Test name
Test status
Simulation time 50936085 ps
CPU time 1.52 seconds
Started Apr 25 01:00:37 PM PDT 24
Finished Apr 25 01:00:43 PM PDT 24
Peak memory 218000 kb
Host smart-7b5293ff-e8f8-4d65-a2b9-ba3597a90728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892280869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2892280869
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.3977860034
Short name T812
Test name
Test status
Simulation time 21094111 ps
CPU time 0.92 seconds
Started Apr 25 01:00:51 PM PDT 24
Finished Apr 25 01:00:54 PM PDT 24
Peak memory 217936 kb
Host smart-99ba7c6b-243b-42ed-9f21-823af623a0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977860034 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3977860034
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/72.edn_err.312050999
Short name T716
Test name
Test status
Simulation time 24273226 ps
CPU time 0.99 seconds
Started Apr 25 01:01:03 PM PDT 24
Finished Apr 25 01:01:04 PM PDT 24
Peak memory 218516 kb
Host smart-1a72ed38-9022-4c3e-b52e-85c1d7d7311f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312050999 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.312050999
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3464494504
Short name T574
Test name
Test status
Simulation time 57481845 ps
CPU time 1.58 seconds
Started Apr 25 01:00:59 PM PDT 24
Finished Apr 25 01:01:02 PM PDT 24
Peak memory 218504 kb
Host smart-61cfa7d2-4457-4cb8-a091-2a1abb30762c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464494504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3464494504
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.2977945765
Short name T99
Test name
Test status
Simulation time 32847861 ps
CPU time 0.98 seconds
Started Apr 25 01:00:44 PM PDT 24
Finished Apr 25 01:00:48 PM PDT 24
Peak memory 218292 kb
Host smart-eade7cef-d264-48a6-ac80-008564c128e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977945765 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2977945765
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3727904567
Short name T479
Test name
Test status
Simulation time 54390041 ps
CPU time 1.23 seconds
Started Apr 25 01:00:50 PM PDT 24
Finished Apr 25 01:00:53 PM PDT 24
Peak memory 216156 kb
Host smart-167b99d6-df26-4d87-accf-38b72a767552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727904567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3727904567
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.2088282805
Short name T14
Test name
Test status
Simulation time 28335623 ps
CPU time 0.99 seconds
Started Apr 25 01:01:00 PM PDT 24
Finished Apr 25 01:01:02 PM PDT 24
Peak memory 223632 kb
Host smart-075dd072-75fa-40c7-a3c8-08daedf09762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088282805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2088282805
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.4005227958
Short name T314
Test name
Test status
Simulation time 103912431 ps
CPU time 1.75 seconds
Started Apr 25 01:00:46 PM PDT 24
Finished Apr 25 01:00:51 PM PDT 24
Peak memory 218148 kb
Host smart-c2ff2059-e267-45bd-a5f9-7d4c2d0ed283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005227958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.4005227958
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.2854898320
Short name T100
Test name
Test status
Simulation time 30846068 ps
CPU time 1.04 seconds
Started Apr 25 01:00:50 PM PDT 24
Finished Apr 25 01:00:53 PM PDT 24
Peak memory 217716 kb
Host smart-d563c21c-97c6-43c4-b608-8a7a2d1006ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854898320 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2854898320
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.966093899
Short name T457
Test name
Test status
Simulation time 624089002 ps
CPU time 4.69 seconds
Started Apr 25 01:00:33 PM PDT 24
Finished Apr 25 01:00:43 PM PDT 24
Peak memory 219872 kb
Host smart-0e680429-7fa0-43e7-9889-12106da48517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966093899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.966093899
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.1081637307
Short name T389
Test name
Test status
Simulation time 19411530 ps
CPU time 1.03 seconds
Started Apr 25 01:00:42 PM PDT 24
Finished Apr 25 01:00:47 PM PDT 24
Peak memory 218236 kb
Host smart-99ef3419-6e5e-425c-b4a3-36eda9443d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081637307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1081637307
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.285705442
Short name T630
Test name
Test status
Simulation time 77215133 ps
CPU time 1.14 seconds
Started Apr 25 01:00:30 PM PDT 24
Finished Apr 25 01:00:35 PM PDT 24
Peak memory 216780 kb
Host smart-84a29d52-2d29-4c53-bb9d-f8101dc4a9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285705442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.285705442
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.3157030777
Short name T174
Test name
Test status
Simulation time 43369288 ps
CPU time 1.03 seconds
Started Apr 25 01:00:54 PM PDT 24
Finished Apr 25 01:01:01 PM PDT 24
Peak memory 219584 kb
Host smart-d9df4610-6f6d-4155-8898-38b41dd50663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157030777 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3157030777
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3492581753
Short name T556
Test name
Test status
Simulation time 79175591 ps
CPU time 1.39 seconds
Started Apr 25 01:00:39 PM PDT 24
Finished Apr 25 01:00:44 PM PDT 24
Peak memory 218396 kb
Host smart-40fca597-6435-4b12-aa06-8f644d2e2ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492581753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3492581753
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.3889837296
Short name T443
Test name
Test status
Simulation time 26609315 ps
CPU time 0.93 seconds
Started Apr 25 01:00:58 PM PDT 24
Finished Apr 25 01:01:00 PM PDT 24
Peak memory 232068 kb
Host smart-c1137928-b412-475f-8611-bd48e8c30905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889837296 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3889837296
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2816238737
Short name T256
Test name
Test status
Simulation time 30681509 ps
CPU time 1.24 seconds
Started Apr 25 01:00:44 PM PDT 24
Finished Apr 25 01:00:48 PM PDT 24
Peak memory 215180 kb
Host smart-c56d2237-04c2-4180-8fb4-d3ffc11fe5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816238737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2816238737
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.435477498
Short name T51
Test name
Test status
Simulation time 37367981 ps
CPU time 1.49 seconds
Started Apr 25 01:00:37 PM PDT 24
Finished Apr 25 01:00:43 PM PDT 24
Peak memory 225516 kb
Host smart-89e29187-591b-48e5-be2e-e2bbb6f6968d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435477498 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.435477498
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.45419217
Short name T776
Test name
Test status
Simulation time 23240937 ps
CPU time 1.18 seconds
Started Apr 25 01:00:56 PM PDT 24
Finished Apr 25 01:00:59 PM PDT 24
Peak memory 217208 kb
Host smart-f3c99800-4cde-4e22-9435-fe3af7ffd173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45419217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.45419217
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.833643172
Short name T253
Test name
Test status
Simulation time 44515586 ps
CPU time 1.36 seconds
Started Apr 25 12:59:32 PM PDT 24
Finished Apr 25 12:59:40 PM PDT 24
Peak memory 215548 kb
Host smart-b527e29a-4d3c-4ed5-8444-e332ac1d4208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833643172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.833643172
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2345878954
Short name T60
Test name
Test status
Simulation time 13182621 ps
CPU time 0.89 seconds
Started Apr 25 01:00:01 PM PDT 24
Finished Apr 25 01:00:03 PM PDT 24
Peak memory 214748 kb
Host smart-4237d7d7-6ee2-4a2f-b4f6-3d18c69f0e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345878954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2345878954
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3413567199
Short name T654
Test name
Test status
Simulation time 19346819 ps
CPU time 1.06 seconds
Started Apr 25 12:59:35 PM PDT 24
Finished Apr 25 12:59:38 PM PDT 24
Peak memory 216368 kb
Host smart-bf1cc98e-ae0d-4c90-8822-7f3e742eed78
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413567199 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3413567199
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.4042138183
Short name T663
Test name
Test status
Simulation time 32973547 ps
CPU time 1.27 seconds
Started Apr 25 12:59:44 PM PDT 24
Finished Apr 25 12:59:57 PM PDT 24
Peak memory 216828 kb
Host smart-cf52a37d-519e-4b87-8a47-a548f9b48ca7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042138183 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.4042138183
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2640875538
Short name T160
Test name
Test status
Simulation time 82735838 ps
CPU time 1.05 seconds
Started Apr 25 12:59:42 PM PDT 24
Finished Apr 25 12:59:45 PM PDT 24
Peak memory 219492 kb
Host smart-43bbf687-d8cc-4dc4-a4fa-cdafbc3d6c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640875538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2640875538
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1402014803
Short name T623
Test name
Test status
Simulation time 93241988 ps
CPU time 1.6 seconds
Started Apr 25 12:59:34 PM PDT 24
Finished Apr 25 12:59:38 PM PDT 24
Peak memory 218084 kb
Host smart-eee326c1-b76e-4165-9855-a9adcbdb3703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402014803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1402014803
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.4270551548
Short name T35
Test name
Test status
Simulation time 34886091 ps
CPU time 0.88 seconds
Started Apr 25 12:59:47 PM PDT 24
Finished Apr 25 12:59:50 PM PDT 24
Peak memory 215472 kb
Host smart-a2a8b648-e94a-42dd-af48-1328e34c39dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270551548 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.4270551548
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.2874789081
Short name T284
Test name
Test status
Simulation time 22072025 ps
CPU time 0.9 seconds
Started Apr 25 12:59:31 PM PDT 24
Finished Apr 25 12:59:33 PM PDT 24
Peak memory 206976 kb
Host smart-d29042ec-e2c8-4e57-a915-8a7c61082acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874789081 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2874789081
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1303624567
Short name T372
Test name
Test status
Simulation time 29973952 ps
CPU time 0.95 seconds
Started Apr 25 01:00:03 PM PDT 24
Finished Apr 25 01:00:06 PM PDT 24
Peak memory 215168 kb
Host smart-cb0a2c2c-4495-441e-85c7-08d5f4d56dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303624567 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1303624567
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3299353820
Short name T516
Test name
Test status
Simulation time 86205471 ps
CPU time 2.18 seconds
Started Apr 25 12:59:55 PM PDT 24
Finished Apr 25 12:59:59 PM PDT 24
Peak memory 215064 kb
Host smart-d74e3aa6-fbc7-4c13-b667-852ef91a50b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299353820 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3299353820
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1085860633
Short name T40
Test name
Test status
Simulation time 19601841702 ps
CPU time 489.58 seconds
Started Apr 25 12:59:34 PM PDT 24
Finished Apr 25 01:07:45 PM PDT 24
Peak memory 221076 kb
Host smart-84f4251e-7a0c-49b9-b940-35ab40c45c99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085860633 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1085860633
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.2627539265
Short name T53
Test name
Test status
Simulation time 22565035 ps
CPU time 1.29 seconds
Started Apr 25 01:00:50 PM PDT 24
Finished Apr 25 01:00:54 PM PDT 24
Peak memory 229496 kb
Host smart-2a41a3a3-3ec5-4b3d-9853-811ff4adb3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627539265 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2627539265
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1891369178
Short name T735
Test name
Test status
Simulation time 57392510 ps
CPU time 1.2 seconds
Started Apr 25 01:01:05 PM PDT 24
Finished Apr 25 01:01:08 PM PDT 24
Peak memory 219548 kb
Host smart-2e79f293-bdf6-4579-8ea8-047173148e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891369178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1891369178
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.359075624
Short name T749
Test name
Test status
Simulation time 32550347 ps
CPU time 1.21 seconds
Started Apr 25 01:00:44 PM PDT 24
Finished Apr 25 01:00:48 PM PDT 24
Peak memory 219564 kb
Host smart-b77c6081-3d09-4d58-aac0-557fec699341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359075624 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.359075624
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.499366073
Short name T595
Test name
Test status
Simulation time 210644304 ps
CPU time 2.83 seconds
Started Apr 25 01:00:41 PM PDT 24
Finished Apr 25 01:00:51 PM PDT 24
Peak memory 219928 kb
Host smart-e9921086-64d8-4719-86be-4e4ca6e7d0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499366073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.499366073
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.134726288
Short name T34
Test name
Test status
Simulation time 21487687 ps
CPU time 0.93 seconds
Started Apr 25 01:00:49 PM PDT 24
Finished Apr 25 01:00:52 PM PDT 24
Peak memory 218180 kb
Host smart-2c1752b4-fa07-4e2d-8307-a5c03b5d01d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134726288 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.134726288
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.475131114
Short name T567
Test name
Test status
Simulation time 70632946 ps
CPU time 1.04 seconds
Started Apr 25 01:00:55 PM PDT 24
Finished Apr 25 01:00:58 PM PDT 24
Peak memory 216940 kb
Host smart-056ef00b-e1e4-4aa0-82fc-d1c8648a08a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475131114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.475131114
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.4222958072
Short name T85
Test name
Test status
Simulation time 27985404 ps
CPU time 1.4 seconds
Started Apr 25 01:00:43 PM PDT 24
Finished Apr 25 01:00:48 PM PDT 24
Peak memory 229544 kb
Host smart-52a7e161-e31c-457a-b00d-c05bd094b6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222958072 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.4222958072
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.219369355
Short name T539
Test name
Test status
Simulation time 28150730 ps
CPU time 1.16 seconds
Started Apr 25 01:00:36 PM PDT 24
Finished Apr 25 01:00:41 PM PDT 24
Peak memory 217036 kb
Host smart-97bc0ee8-02ec-4a2f-897c-edce86cdfc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219369355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.219369355
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.3166809690
Short name T447
Test name
Test status
Simulation time 30622672 ps
CPU time 0.91 seconds
Started Apr 25 01:00:40 PM PDT 24
Finished Apr 25 01:00:44 PM PDT 24
Peak memory 218480 kb
Host smart-cb9bf1aa-71de-434a-b40f-1a4ec6de9121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166809690 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3166809690
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2287853077
Short name T453
Test name
Test status
Simulation time 23236878 ps
CPU time 1.17 seconds
Started Apr 25 01:00:59 PM PDT 24
Finished Apr 25 01:01:02 PM PDT 24
Peak memory 219456 kb
Host smart-cf9af631-a8ab-4ca2-a107-e10b159cc429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287853077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2287853077
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.3083470145
Short name T179
Test name
Test status
Simulation time 31755893 ps
CPU time 1.01 seconds
Started Apr 25 01:00:55 PM PDT 24
Finished Apr 25 01:00:58 PM PDT 24
Peak memory 218316 kb
Host smart-a82efd19-e99f-4864-b31f-850de4ba70e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083470145 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3083470145
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.214693542
Short name T327
Test name
Test status
Simulation time 194581844 ps
CPU time 1.4 seconds
Started Apr 25 01:00:51 PM PDT 24
Finished Apr 25 01:00:54 PM PDT 24
Peak memory 218388 kb
Host smart-7ef9a228-0f34-40d5-87ba-07c5d473f027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214693542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.214693542
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.948757386
Short name T397
Test name
Test status
Simulation time 36966699 ps
CPU time 1.07 seconds
Started Apr 25 01:00:50 PM PDT 24
Finished Apr 25 01:00:53 PM PDT 24
Peak memory 219692 kb
Host smart-e6809ef0-0b10-4884-868d-d8e4f00d34e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948757386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.948757386
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2200351801
Short name T355
Test name
Test status
Simulation time 26386312 ps
CPU time 1.25 seconds
Started Apr 25 01:00:46 PM PDT 24
Finished Apr 25 01:00:50 PM PDT 24
Peak memory 218096 kb
Host smart-c3bbd664-20ef-4d0e-b3ed-69a9bd9ce38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200351801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2200351801
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.331731591
Short name T612
Test name
Test status
Simulation time 17929928 ps
CPU time 1 seconds
Started Apr 25 01:00:49 PM PDT 24
Finished Apr 25 01:00:52 PM PDT 24
Peak memory 218100 kb
Host smart-f19930e4-25d5-44f5-946a-9e4d1b8a08ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331731591 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.331731591
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2518709547
Short name T558
Test name
Test status
Simulation time 390662133 ps
CPU time 3.48 seconds
Started Apr 25 01:00:49 PM PDT 24
Finished Apr 25 01:00:55 PM PDT 24
Peak memory 219404 kb
Host smart-da8cbd3a-a36c-4dc7-82d7-c6e6a23c3f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518709547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2518709547
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.1421531129
Short name T741
Test name
Test status
Simulation time 40642942 ps
CPU time 0.87 seconds
Started Apr 25 01:00:51 PM PDT 24
Finished Apr 25 01:00:54 PM PDT 24
Peak memory 218328 kb
Host smart-afd57f98-de23-428b-8d51-f8c670279f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421531129 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1421531129
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1390009686
Short name T801
Test name
Test status
Simulation time 82969979 ps
CPU time 1.42 seconds
Started Apr 25 01:00:52 PM PDT 24
Finished Apr 25 01:00:55 PM PDT 24
Peak memory 218184 kb
Host smart-69f8a3ff-a833-48b1-8838-158223ed8c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390009686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1390009686
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1884470200
Short name T137
Test name
Test status
Simulation time 47574357 ps
CPU time 1.17 seconds
Started Apr 25 12:59:51 PM PDT 24
Finished Apr 25 12:59:54 PM PDT 24
Peak memory 215544 kb
Host smart-68182491-8d0e-4f76-a387-02b297b96deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884470200 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1884470200
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2738702835
Short name T302
Test name
Test status
Simulation time 18655620 ps
CPU time 0.84 seconds
Started Apr 25 12:59:47 PM PDT 24
Finished Apr 25 12:59:50 PM PDT 24
Peak memory 206764 kb
Host smart-254ede00-6533-4192-b673-5de234d2692b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738702835 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2738702835
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3655173533
Short name T186
Test name
Test status
Simulation time 39606095 ps
CPU time 0.86 seconds
Started Apr 25 12:59:57 PM PDT 24
Finished Apr 25 01:00:00 PM PDT 24
Peak memory 216188 kb
Host smart-bd50c26a-5bbb-4ff7-97b8-3b5a4d1ce43c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655173533 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3655173533
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.4144062151
Short name T89
Test name
Test status
Simulation time 95803295 ps
CPU time 1.19 seconds
Started Apr 25 12:59:35 PM PDT 24
Finished Apr 25 12:59:37 PM PDT 24
Peak memory 216712 kb
Host smart-f80d5171-9832-4600-b9a4-de4625a36c1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144062151 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.4144062151
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1718177501
Short name T103
Test name
Test status
Simulation time 48445519 ps
CPU time 1.05 seconds
Started Apr 25 12:59:57 PM PDT 24
Finished Apr 25 01:00:00 PM PDT 24
Peak memory 219624 kb
Host smart-ae6f72fd-1d20-4303-b434-665e23a91e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718177501 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1718177501
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1230048767
Short name T736
Test name
Test status
Simulation time 35040364 ps
CPU time 1.26 seconds
Started Apr 25 12:59:36 PM PDT 24
Finished Apr 25 12:59:40 PM PDT 24
Peak memory 215180 kb
Host smart-a6a6c45c-2fdd-49c9-82b8-3509dd86bbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230048767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1230048767
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.311346587
Short name T676
Test name
Test status
Simulation time 20917466 ps
CPU time 1.13 seconds
Started Apr 25 12:59:49 PM PDT 24
Finished Apr 25 12:59:52 PM PDT 24
Peak memory 215380 kb
Host smart-137065f7-f28c-45b9-b55d-04a91a48c41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311346587 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.311346587
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2191882695
Short name T26
Test name
Test status
Simulation time 43568001 ps
CPU time 0.93 seconds
Started Apr 25 12:59:54 PM PDT 24
Finished Apr 25 12:59:56 PM PDT 24
Peak memory 206952 kb
Host smart-e723f4bc-711b-40fb-b76d-debd9fc5592d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191882695 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2191882695
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2257421204
Short name T300
Test name
Test status
Simulation time 18845115 ps
CPU time 1.03 seconds
Started Apr 25 12:59:46 PM PDT 24
Finished Apr 25 12:59:49 PM PDT 24
Peak memory 215172 kb
Host smart-1c4bcbb3-95a6-4634-8219-3f3e5e53c599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257421204 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2257421204
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.366426508
Short name T590
Test name
Test status
Simulation time 376765581 ps
CPU time 7.58 seconds
Started Apr 25 12:59:34 PM PDT 24
Finished Apr 25 12:59:43 PM PDT 24
Peak memory 218204 kb
Host smart-2b140aff-d397-414a-b8f4-6459f72e321f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366426508 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.366426508
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1156576527
Short name T495
Test name
Test status
Simulation time 244005947349 ps
CPU time 1090.47 seconds
Started Apr 25 12:59:33 PM PDT 24
Finished Apr 25 01:17:45 PM PDT 24
Peak memory 222004 kb
Host smart-df4eb1d4-38ea-4f71-adc5-3dfd0d6effc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156576527 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1156576527
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.382646463
Short name T582
Test name
Test status
Simulation time 35362853 ps
CPU time 1.06 seconds
Started Apr 25 01:00:53 PM PDT 24
Finished Apr 25 01:00:56 PM PDT 24
Peak memory 219708 kb
Host smart-2bbb3cee-44ce-4b04-b407-1ef43dec0b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382646463 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.382646463
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2505825221
Short name T271
Test name
Test status
Simulation time 59487115 ps
CPU time 1.48 seconds
Started Apr 25 01:00:49 PM PDT 24
Finished Apr 25 01:00:53 PM PDT 24
Peak memory 218248 kb
Host smart-bd5412b3-30e0-427e-8e8b-ec5b2373f57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505825221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2505825221
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.2822452530
Short name T131
Test name
Test status
Simulation time 36532736 ps
CPU time 0.91 seconds
Started Apr 25 01:01:07 PM PDT 24
Finished Apr 25 01:01:10 PM PDT 24
Peak memory 218052 kb
Host smart-bb252844-f69e-4813-8659-f7e2fccda353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822452530 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2822452530
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3154046115
Short name T653
Test name
Test status
Simulation time 45255315 ps
CPU time 1.18 seconds
Started Apr 25 01:00:40 PM PDT 24
Finished Apr 25 01:00:44 PM PDT 24
Peak memory 216932 kb
Host smart-ef222cf0-97af-4590-be36-fbd704bb5cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154046115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3154046115
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.2233768075
Short name T128
Test name
Test status
Simulation time 22787829 ps
CPU time 0.95 seconds
Started Apr 25 01:00:56 PM PDT 24
Finished Apr 25 01:00:59 PM PDT 24
Peak memory 218164 kb
Host smart-d420ee0e-8ffa-466a-8981-e76fff59a324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233768075 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2233768075
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1796095700
Short name T249
Test name
Test status
Simulation time 95336816 ps
CPU time 1.52 seconds
Started Apr 25 01:00:55 PM PDT 24
Finished Apr 25 01:00:58 PM PDT 24
Peak memory 218396 kb
Host smart-3ba68fba-1174-460b-8da8-8935581008a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796095700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1796095700
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.820282795
Short name T546
Test name
Test status
Simulation time 49309179 ps
CPU time 0.88 seconds
Started Apr 25 01:00:39 PM PDT 24
Finished Apr 25 01:00:43 PM PDT 24
Peak memory 218204 kb
Host smart-e5a7df25-0864-49d9-a9b4-c76482e852b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820282795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.820282795
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1147210806
Short name T724
Test name
Test status
Simulation time 66693545 ps
CPU time 1.19 seconds
Started Apr 25 01:01:04 PM PDT 24
Finished Apr 25 01:01:07 PM PDT 24
Peak memory 218332 kb
Host smart-9aacacf3-6236-414b-9d62-fd7ebf3e1d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147210806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1147210806
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.4063688982
Short name T471
Test name
Test status
Simulation time 19344565 ps
CPU time 1.04 seconds
Started Apr 25 01:00:32 PM PDT 24
Finished Apr 25 01:00:38 PM PDT 24
Peak memory 218120 kb
Host smart-8f28ecbb-b1bc-4942-9816-858a2341ccd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063688982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.4063688982
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3041586826
Short name T699
Test name
Test status
Simulation time 117358037 ps
CPU time 1.63 seconds
Started Apr 25 01:00:53 PM PDT 24
Finished Apr 25 01:00:57 PM PDT 24
Peak memory 218788 kb
Host smart-ee00f38d-1c5b-48e0-98ff-dc22655f0153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041586826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3041586826
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2850241760
Short name T747
Test name
Test status
Simulation time 32178722 ps
CPU time 0.84 seconds
Started Apr 25 01:00:46 PM PDT 24
Finished Apr 25 01:00:55 PM PDT 24
Peak memory 218188 kb
Host smart-4534bbe1-4d62-4c7e-95ce-b37eb55c5ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850241760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2850241760
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.550518183
Short name T803
Test name
Test status
Simulation time 47151441 ps
CPU time 1.22 seconds
Started Apr 25 01:01:15 PM PDT 24
Finished Apr 25 01:01:19 PM PDT 24
Peak memory 218152 kb
Host smart-99db8bbf-032a-493b-b43a-38d78f183b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550518183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.550518183
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.425720711
Short name T169
Test name
Test status
Simulation time 34154642 ps
CPU time 0.86 seconds
Started Apr 25 01:00:55 PM PDT 24
Finished Apr 25 01:00:57 PM PDT 24
Peak memory 218168 kb
Host smart-67517281-5440-4a7a-8435-46032331162d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425720711 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.425720711
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.4078040468
Short name T325
Test name
Test status
Simulation time 42435751 ps
CPU time 1.26 seconds
Started Apr 25 01:00:47 PM PDT 24
Finished Apr 25 01:00:50 PM PDT 24
Peak memory 216968 kb
Host smart-403d607d-11fe-448a-841b-00f566e0bec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078040468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.4078040468
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.3238478933
Short name T364
Test name
Test status
Simulation time 22718658 ps
CPU time 1.02 seconds
Started Apr 25 01:00:53 PM PDT 24
Finished Apr 25 01:00:57 PM PDT 24
Peak memory 218492 kb
Host smart-0db94883-044c-4b59-bfcc-42e73cfdc3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238478933 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3238478933
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3813565917
Short name T205
Test name
Test status
Simulation time 39993308 ps
CPU time 1.32 seconds
Started Apr 25 01:00:57 PM PDT 24
Finished Apr 25 01:01:00 PM PDT 24
Peak memory 218084 kb
Host smart-c738bc65-9a9c-4429-bcf5-222f4f07c62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813565917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3813565917
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.15552824
Short name T101
Test name
Test status
Simulation time 114295450 ps
CPU time 1.09 seconds
Started Apr 25 01:00:52 PM PDT 24
Finished Apr 25 01:00:56 PM PDT 24
Peak memory 220508 kb
Host smart-a3c9e6b6-719b-4064-94af-de0b7fce10df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15552824 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.15552824
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3804168511
Short name T8
Test name
Test status
Simulation time 34771036 ps
CPU time 1.36 seconds
Started Apr 25 01:00:56 PM PDT 24
Finished Apr 25 01:00:59 PM PDT 24
Peak memory 219368 kb
Host smart-ec958371-7dfd-4c11-afd8-ae52a35bd2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804168511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3804168511
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.3718266642
Short name T94
Test name
Test status
Simulation time 46498775 ps
CPU time 0.97 seconds
Started Apr 25 01:00:54 PM PDT 24
Finished Apr 25 01:00:57 PM PDT 24
Peak memory 219608 kb
Host smart-dbf1968d-d7dd-4b9d-9f0c-5eb71fce6ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718266642 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3718266642
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3554607814
Short name T620
Test name
Test status
Simulation time 107841651 ps
CPU time 1.59 seconds
Started Apr 25 01:00:43 PM PDT 24
Finished Apr 25 01:00:48 PM PDT 24
Peak memory 218996 kb
Host smart-2f3baf1b-9a57-4dc3-9517-f405b3c7415d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554607814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3554607814
Directory /workspace/99.edn_genbits/latest
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