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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.24 98.24 93.76 97.01 81.50 96.76 99.77 92.64


Total test records in report: 978
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T786 /workspace/coverage/default/37.edn_genbits.1578972743 Apr 28 04:29:20 PM PDT 24 Apr 28 04:29:23 PM PDT 24 58857282 ps
T787 /workspace/coverage/default/63.edn_err.405852321 Apr 28 04:29:59 PM PDT 24 Apr 28 04:30:01 PM PDT 24 24265356 ps
T788 /workspace/coverage/default/48.edn_stress_all.3699004960 Apr 28 04:29:48 PM PDT 24 Apr 28 04:29:51 PM PDT 24 74502506 ps
T789 /workspace/coverage/default/43.edn_genbits.4107666418 Apr 28 04:29:37 PM PDT 24 Apr 28 04:29:39 PM PDT 24 41906652 ps
T790 /workspace/coverage/default/14.edn_intr.2740042037 Apr 28 04:28:32 PM PDT 24 Apr 28 04:28:34 PM PDT 24 27635462 ps
T791 /workspace/coverage/default/22.edn_err.1634714418 Apr 28 04:28:44 PM PDT 24 Apr 28 04:28:47 PM PDT 24 33537631 ps
T792 /workspace/coverage/default/8.edn_disable_auto_req_mode.3828072414 Apr 28 04:28:01 PM PDT 24 Apr 28 04:28:03 PM PDT 24 22223976 ps
T793 /workspace/coverage/default/89.edn_genbits.2008722512 Apr 28 04:30:09 PM PDT 24 Apr 28 04:30:11 PM PDT 24 33677739 ps
T794 /workspace/coverage/default/9.edn_disable_auto_req_mode.3833091214 Apr 28 04:28:06 PM PDT 24 Apr 28 04:28:08 PM PDT 24 18010471 ps
T795 /workspace/coverage/default/31.edn_disable.2722090620 Apr 28 04:29:09 PM PDT 24 Apr 28 04:29:11 PM PDT 24 13426924 ps
T796 /workspace/coverage/default/269.edn_genbits.2605243629 Apr 28 04:31:00 PM PDT 24 Apr 28 04:31:02 PM PDT 24 138684406 ps
T797 /workspace/coverage/default/108.edn_genbits.1225840045 Apr 28 04:30:24 PM PDT 24 Apr 28 04:30:25 PM PDT 24 56708534 ps
T798 /workspace/coverage/default/0.edn_disable.513206999 Apr 28 04:27:31 PM PDT 24 Apr 28 04:27:33 PM PDT 24 35313609 ps
T799 /workspace/coverage/default/219.edn_genbits.393511922 Apr 28 04:30:45 PM PDT 24 Apr 28 04:30:47 PM PDT 24 45517692 ps
T800 /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1931843274 Apr 28 04:27:39 PM PDT 24 Apr 28 04:48:09 PM PDT 24 44823896592 ps
T801 /workspace/coverage/default/40.edn_alert_test.1264953243 Apr 28 04:29:30 PM PDT 24 Apr 28 04:29:32 PM PDT 24 37154842 ps
T802 /workspace/coverage/default/23.edn_alert.2379167888 Apr 28 04:28:52 PM PDT 24 Apr 28 04:28:54 PM PDT 24 25177552 ps
T803 /workspace/coverage/default/75.edn_genbits.986369958 Apr 28 04:30:04 PM PDT 24 Apr 28 04:30:06 PM PDT 24 39781218 ps
T804 /workspace/coverage/default/45.edn_stress_all_with_rand_reset.934707089 Apr 28 04:29:48 PM PDT 24 Apr 28 04:45:07 PM PDT 24 37827956913 ps
T805 /workspace/coverage/default/18.edn_smoke.3300715844 Apr 28 04:28:33 PM PDT 24 Apr 28 04:28:34 PM PDT 24 123505777 ps
T115 /workspace/coverage/default/65.edn_err.2898791103 Apr 28 04:29:59 PM PDT 24 Apr 28 04:30:01 PM PDT 24 46879546 ps
T806 /workspace/coverage/default/273.edn_genbits.972066142 Apr 28 04:30:57 PM PDT 24 Apr 28 04:30:59 PM PDT 24 78257520 ps
T807 /workspace/coverage/default/188.edn_genbits.1864526045 Apr 28 04:30:37 PM PDT 24 Apr 28 04:30:39 PM PDT 24 85872125 ps
T808 /workspace/coverage/default/40.edn_genbits.2703006256 Apr 28 04:29:27 PM PDT 24 Apr 28 04:29:29 PM PDT 24 64555143 ps
T809 /workspace/coverage/default/45.edn_alert_test.2274912356 Apr 28 04:29:48 PM PDT 24 Apr 28 04:29:50 PM PDT 24 27864488 ps
T810 /workspace/coverage/default/109.edn_genbits.753422250 Apr 28 04:30:20 PM PDT 24 Apr 28 04:30:22 PM PDT 24 45166569 ps
T811 /workspace/coverage/default/8.edn_err.3163057601 Apr 28 04:28:01 PM PDT 24 Apr 28 04:28:03 PM PDT 24 25548348 ps
T812 /workspace/coverage/default/43.edn_disable_auto_req_mode.3471975941 Apr 28 04:29:39 PM PDT 24 Apr 28 04:29:40 PM PDT 24 121857859 ps
T813 /workspace/coverage/default/18.edn_stress_all.1043574781 Apr 28 04:28:33 PM PDT 24 Apr 28 04:28:35 PM PDT 24 59939918 ps
T814 /workspace/coverage/default/47.edn_alert_test.3962736334 Apr 28 04:29:47 PM PDT 24 Apr 28 04:29:49 PM PDT 24 47713220 ps
T815 /workspace/coverage/default/248.edn_genbits.2944907168 Apr 28 04:30:47 PM PDT 24 Apr 28 04:30:50 PM PDT 24 285636109 ps
T816 /workspace/coverage/default/250.edn_genbits.1926780161 Apr 28 04:30:56 PM PDT 24 Apr 28 04:30:58 PM PDT 24 300310803 ps
T817 /workspace/coverage/default/97.edn_genbits.2668944504 Apr 28 04:30:19 PM PDT 24 Apr 28 04:30:21 PM PDT 24 86708745 ps
T818 /workspace/coverage/default/36.edn_disable.2602434035 Apr 28 04:29:23 PM PDT 24 Apr 28 04:29:25 PM PDT 24 40852349 ps
T106 /workspace/coverage/default/38.edn_disable_auto_req_mode.3988842129 Apr 28 04:29:28 PM PDT 24 Apr 28 04:29:29 PM PDT 24 33182899 ps
T819 /workspace/coverage/default/39.edn_err.3681023633 Apr 28 04:29:25 PM PDT 24 Apr 28 04:29:26 PM PDT 24 97410473 ps
T820 /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3424830234 Apr 28 04:29:09 PM PDT 24 Apr 28 05:08:18 PM PDT 24 173064162531 ps
T821 /workspace/coverage/default/41.edn_genbits.1757990745 Apr 28 04:29:34 PM PDT 24 Apr 28 04:29:36 PM PDT 24 67930808 ps
T822 /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1058522250 Apr 28 04:28:59 PM PDT 24 Apr 28 04:41:29 PM PDT 24 63969526608 ps
T823 /workspace/coverage/default/8.edn_intr.4129701749 Apr 28 04:28:00 PM PDT 24 Apr 28 04:28:01 PM PDT 24 31457887 ps
T281 /workspace/coverage/default/65.edn_genbits.3873367181 Apr 28 04:30:00 PM PDT 24 Apr 28 04:30:02 PM PDT 24 52217382 ps
T824 /workspace/coverage/default/7.edn_intr.321582422 Apr 28 04:28:08 PM PDT 24 Apr 28 04:28:10 PM PDT 24 22147443 ps
T825 /workspace/coverage/default/4.edn_genbits.1713805600 Apr 28 04:27:49 PM PDT 24 Apr 28 04:27:51 PM PDT 24 81066409 ps
T826 /workspace/coverage/default/21.edn_intr.518339281 Apr 28 04:28:39 PM PDT 24 Apr 28 04:28:40 PM PDT 24 24189533 ps
T827 /workspace/coverage/default/6.edn_regwen.1668767284 Apr 28 04:27:57 PM PDT 24 Apr 28 04:27:58 PM PDT 24 56178315 ps
T828 /workspace/coverage/default/12.edn_disable_auto_req_mode.2279575348 Apr 28 04:28:13 PM PDT 24 Apr 28 04:28:15 PM PDT 24 52106313 ps
T829 /workspace/coverage/default/211.edn_genbits.3494654193 Apr 28 04:30:41 PM PDT 24 Apr 28 04:30:43 PM PDT 24 58667676 ps
T830 /workspace/coverage/default/14.edn_stress_all_with_rand_reset.4152522806 Apr 28 04:28:17 PM PDT 24 Apr 28 05:00:43 PM PDT 24 351338905320 ps
T831 /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3690509672 Apr 28 04:29:23 PM PDT 24 Apr 28 04:45:10 PM PDT 24 34690331404 ps
T832 /workspace/coverage/default/43.edn_intr.2611218926 Apr 28 04:29:37 PM PDT 24 Apr 28 04:29:39 PM PDT 24 21088465 ps
T833 /workspace/coverage/default/20.edn_genbits.83479817 Apr 28 04:28:48 PM PDT 24 Apr 28 04:28:50 PM PDT 24 193140990 ps
T834 /workspace/coverage/default/3.edn_alert_test.287233468 Apr 28 04:27:48 PM PDT 24 Apr 28 04:27:50 PM PDT 24 111584176 ps
T835 /workspace/coverage/default/33.edn_intr.4286995722 Apr 28 04:29:14 PM PDT 24 Apr 28 04:29:15 PM PDT 24 28929223 ps
T95 /workspace/coverage/default/88.edn_err.2402267432 Apr 28 04:30:08 PM PDT 24 Apr 28 04:30:10 PM PDT 24 26018718 ps
T836 /workspace/coverage/default/97.edn_err.1517566585 Apr 28 04:30:17 PM PDT 24 Apr 28 04:30:19 PM PDT 24 25617166 ps
T837 /workspace/coverage/default/37.edn_smoke.4242136469 Apr 28 04:29:26 PM PDT 24 Apr 28 04:29:28 PM PDT 24 15998526 ps
T838 /workspace/coverage/default/294.edn_genbits.4230581490 Apr 28 04:31:01 PM PDT 24 Apr 28 04:31:03 PM PDT 24 34647499 ps
T839 /workspace/coverage/default/28.edn_genbits.84879134 Apr 28 04:28:57 PM PDT 24 Apr 28 04:28:59 PM PDT 24 70316912 ps
T840 /workspace/coverage/default/30.edn_genbits.1049619989 Apr 28 04:29:07 PM PDT 24 Apr 28 04:29:09 PM PDT 24 29957447 ps
T841 /workspace/coverage/default/11.edn_stress_all.3848131245 Apr 28 04:28:12 PM PDT 24 Apr 28 04:28:15 PM PDT 24 130365983 ps
T842 /workspace/coverage/default/22.edn_alert_test.1225714784 Apr 28 04:28:48 PM PDT 24 Apr 28 04:28:50 PM PDT 24 25134777 ps
T843 /workspace/coverage/default/8.edn_genbits.1193459605 Apr 28 04:28:01 PM PDT 24 Apr 28 04:28:04 PM PDT 24 38345746 ps
T844 /workspace/coverage/default/7.edn_smoke.349194715 Apr 28 04:27:57 PM PDT 24 Apr 28 04:27:58 PM PDT 24 16848160 ps
T845 /workspace/coverage/cover_reg_top/15.edn_intr_test.3246399126 Apr 28 01:05:03 PM PDT 24 Apr 28 01:05:05 PM PDT 24 29398672 ps
T846 /workspace/coverage/cover_reg_top/41.edn_intr_test.4237467687 Apr 28 01:05:03 PM PDT 24 Apr 28 01:05:07 PM PDT 24 198231892 ps
T847 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3231089178 Apr 28 01:04:55 PM PDT 24 Apr 28 01:04:58 PM PDT 24 391777609 ps
T238 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.4068794853 Apr 28 01:04:43 PM PDT 24 Apr 28 01:04:46 PM PDT 24 246082537 ps
T206 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2927246338 Apr 28 01:04:59 PM PDT 24 Apr 28 01:05:02 PM PDT 24 186405423 ps
T239 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1868467684 Apr 28 01:04:48 PM PDT 24 Apr 28 01:04:51 PM PDT 24 66678704 ps
T848 /workspace/coverage/cover_reg_top/44.edn_intr_test.2076816763 Apr 28 01:05:04 PM PDT 24 Apr 28 01:05:08 PM PDT 24 18424027 ps
T849 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.71611109 Apr 28 01:04:48 PM PDT 24 Apr 28 01:04:50 PM PDT 24 35886644 ps
T850 /workspace/coverage/cover_reg_top/39.edn_intr_test.1319387226 Apr 28 01:05:01 PM PDT 24 Apr 28 01:05:04 PM PDT 24 15336385 ps
T851 /workspace/coverage/cover_reg_top/40.edn_intr_test.1111661956 Apr 28 01:05:02 PM PDT 24 Apr 28 01:05:05 PM PDT 24 14394067 ps
T852 /workspace/coverage/cover_reg_top/20.edn_intr_test.4290650477 Apr 28 01:04:58 PM PDT 24 Apr 28 01:05:01 PM PDT 24 15622363 ps
T200 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2900818707 Apr 28 01:04:43 PM PDT 24 Apr 28 01:04:44 PM PDT 24 86587880 ps
T217 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1872394406 Apr 28 01:04:57 PM PDT 24 Apr 28 01:04:59 PM PDT 24 62402542 ps
T218 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.335600258 Apr 28 01:04:54 PM PDT 24 Apr 28 01:04:56 PM PDT 24 112566730 ps
T219 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2276077223 Apr 28 01:04:37 PM PDT 24 Apr 28 01:04:38 PM PDT 24 15240935 ps
T220 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.750001821 Apr 28 01:05:02 PM PDT 24 Apr 28 01:05:05 PM PDT 24 15181583 ps
T853 /workspace/coverage/cover_reg_top/19.edn_intr_test.2157073849 Apr 28 01:05:01 PM PDT 24 Apr 28 01:05:04 PM PDT 24 48957248 ps
T854 /workspace/coverage/cover_reg_top/13.edn_intr_test.311953489 Apr 28 01:04:54 PM PDT 24 Apr 28 01:04:55 PM PDT 24 44517388 ps
T855 /workspace/coverage/cover_reg_top/30.edn_intr_test.1218830662 Apr 28 01:05:03 PM PDT 24 Apr 28 01:05:06 PM PDT 24 12744890 ps
T856 /workspace/coverage/cover_reg_top/29.edn_intr_test.411785566 Apr 28 01:05:02 PM PDT 24 Apr 28 01:05:05 PM PDT 24 11122155 ps
T857 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.581480300 Apr 28 01:04:47 PM PDT 24 Apr 28 01:04:49 PM PDT 24 331165869 ps
T247 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.428355628 Apr 28 01:04:59 PM PDT 24 Apr 28 01:05:03 PM PDT 24 55532782 ps
T237 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2943914469 Apr 28 01:04:48 PM PDT 24 Apr 28 01:04:50 PM PDT 24 46899325 ps
T858 /workspace/coverage/cover_reg_top/2.edn_intr_test.3617117027 Apr 28 01:04:42 PM PDT 24 Apr 28 01:04:44 PM PDT 24 23403203 ps
T859 /workspace/coverage/cover_reg_top/28.edn_intr_test.3199618341 Apr 28 01:05:02 PM PDT 24 Apr 28 01:05:04 PM PDT 24 19182738 ps
T231 /workspace/coverage/cover_reg_top/19.edn_csr_rw.57240203 Apr 28 01:04:59 PM PDT 24 Apr 28 01:05:02 PM PDT 24 169321278 ps
T232 /workspace/coverage/cover_reg_top/8.edn_csr_rw.2872762670 Apr 28 01:04:49 PM PDT 24 Apr 28 01:04:50 PM PDT 24 13027408 ps
T221 /workspace/coverage/cover_reg_top/16.edn_csr_rw.4211548945 Apr 28 01:05:05 PM PDT 24 Apr 28 01:05:08 PM PDT 24 32217416 ps
T222 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.4280411505 Apr 28 01:04:44 PM PDT 24 Apr 28 01:04:47 PM PDT 24 113295643 ps
T249 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1723671360 Apr 28 01:04:46 PM PDT 24 Apr 28 01:04:48 PM PDT 24 72651748 ps
T860 /workspace/coverage/cover_reg_top/10.edn_tl_errors.829378401 Apr 28 01:04:51 PM PDT 24 Apr 28 01:04:54 PM PDT 24 559073358 ps
T861 /workspace/coverage/cover_reg_top/0.edn_intr_test.1872934286 Apr 28 01:04:39 PM PDT 24 Apr 28 01:04:41 PM PDT 24 56919270 ps
T862 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1968893237 Apr 28 01:04:44 PM PDT 24 Apr 28 01:04:46 PM PDT 24 49423708 ps
T223 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3947637403 Apr 28 01:04:42 PM PDT 24 Apr 28 01:04:44 PM PDT 24 22918895 ps
T233 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1972726252 Apr 28 01:04:42 PM PDT 24 Apr 28 01:04:43 PM PDT 24 21797142 ps
T863 /workspace/coverage/cover_reg_top/18.edn_intr_test.780782782 Apr 28 01:04:59 PM PDT 24 Apr 28 01:05:02 PM PDT 24 48559953 ps
T864 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1162370910 Apr 28 01:04:42 PM PDT 24 Apr 28 01:04:45 PM PDT 24 35486264 ps
T234 /workspace/coverage/cover_reg_top/7.edn_csr_rw.282604465 Apr 28 01:04:46 PM PDT 24 Apr 28 01:04:48 PM PDT 24 64344699 ps
T865 /workspace/coverage/cover_reg_top/5.edn_tl_errors.644001141 Apr 28 01:04:45 PM PDT 24 Apr 28 01:04:48 PM PDT 24 59305349 ps
T866 /workspace/coverage/cover_reg_top/4.edn_intr_test.127422585 Apr 28 01:04:44 PM PDT 24 Apr 28 01:04:45 PM PDT 24 45031274 ps
T867 /workspace/coverage/cover_reg_top/4.edn_tl_errors.11413090 Apr 28 01:04:45 PM PDT 24 Apr 28 01:04:48 PM PDT 24 81957785 ps
T868 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2241267530 Apr 28 01:04:36 PM PDT 24 Apr 28 01:04:38 PM PDT 24 46568123 ps
T869 /workspace/coverage/cover_reg_top/6.edn_intr_test.869809122 Apr 28 01:04:49 PM PDT 24 Apr 28 01:04:50 PM PDT 24 116026485 ps
T870 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.890281218 Apr 28 01:04:44 PM PDT 24 Apr 28 01:04:51 PM PDT 24 253447948 ps
T871 /workspace/coverage/cover_reg_top/34.edn_intr_test.3360851928 Apr 28 01:05:03 PM PDT 24 Apr 28 01:05:06 PM PDT 24 23304066 ps
T224 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1579952919 Apr 28 01:04:38 PM PDT 24 Apr 28 01:04:40 PM PDT 24 43548214 ps
T872 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.737778615 Apr 28 01:04:55 PM PDT 24 Apr 28 01:04:57 PM PDT 24 31811471 ps
T873 /workspace/coverage/cover_reg_top/1.edn_tl_errors.653330299 Apr 28 01:04:41 PM PDT 24 Apr 28 01:04:43 PM PDT 24 206689622 ps
T235 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3294439408 Apr 28 01:04:46 PM PDT 24 Apr 28 01:04:48 PM PDT 24 34540484 ps
T874 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3806315394 Apr 28 01:04:44 PM PDT 24 Apr 28 01:04:46 PM PDT 24 167710984 ps
T225 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1170715440 Apr 28 01:04:59 PM PDT 24 Apr 28 01:05:02 PM PDT 24 21306115 ps
T875 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2414441339 Apr 28 01:05:02 PM PDT 24 Apr 28 01:05:06 PM PDT 24 136630224 ps
T876 /workspace/coverage/cover_reg_top/16.edn_intr_test.4156819781 Apr 28 01:04:59 PM PDT 24 Apr 28 01:05:01 PM PDT 24 21743461 ps
T877 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.4159189877 Apr 28 01:04:58 PM PDT 24 Apr 28 01:05:00 PM PDT 24 452396313 ps
T878 /workspace/coverage/cover_reg_top/14.edn_intr_test.3564781259 Apr 28 01:04:58 PM PDT 24 Apr 28 01:05:00 PM PDT 24 26293346 ps
T879 /workspace/coverage/cover_reg_top/27.edn_intr_test.2866070421 Apr 28 01:05:03 PM PDT 24 Apr 28 01:05:06 PM PDT 24 27437306 ps
T880 /workspace/coverage/cover_reg_top/8.edn_tl_errors.2546696180 Apr 28 01:04:48 PM PDT 24 Apr 28 01:04:50 PM PDT 24 286897902 ps
T881 /workspace/coverage/cover_reg_top/38.edn_intr_test.4263059885 Apr 28 01:05:02 PM PDT 24 Apr 28 01:05:05 PM PDT 24 86632882 ps
T882 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4195364119 Apr 28 01:04:59 PM PDT 24 Apr 28 01:05:02 PM PDT 24 17803697 ps
T883 /workspace/coverage/cover_reg_top/49.edn_intr_test.3801888572 Apr 28 01:05:08 PM PDT 24 Apr 28 01:05:09 PM PDT 24 35494012 ps
T226 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3016840913 Apr 28 01:04:42 PM PDT 24 Apr 28 01:04:44 PM PDT 24 35832330 ps
T884 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3886950404 Apr 28 01:04:49 PM PDT 24 Apr 28 01:04:51 PM PDT 24 47860057 ps
T885 /workspace/coverage/cover_reg_top/11.edn_csr_rw.921559101 Apr 28 01:04:53 PM PDT 24 Apr 28 01:04:54 PM PDT 24 17889689 ps
T227 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.151057169 Apr 28 01:04:38 PM PDT 24 Apr 28 01:04:40 PM PDT 24 13646968 ps
T886 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1067739853 Apr 28 01:04:41 PM PDT 24 Apr 28 01:04:43 PM PDT 24 14530411 ps
T887 /workspace/coverage/cover_reg_top/11.edn_tl_errors.4035593178 Apr 28 01:04:53 PM PDT 24 Apr 28 01:04:56 PM PDT 24 332189828 ps
T888 /workspace/coverage/cover_reg_top/25.edn_intr_test.3746480088 Apr 28 01:05:03 PM PDT 24 Apr 28 01:05:06 PM PDT 24 31603003 ps
T889 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1521148444 Apr 28 01:04:59 PM PDT 24 Apr 28 01:05:05 PM PDT 24 122161821 ps
T890 /workspace/coverage/cover_reg_top/35.edn_intr_test.319682966 Apr 28 01:05:04 PM PDT 24 Apr 28 01:05:07 PM PDT 24 13722538 ps
T236 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3996999482 Apr 28 01:05:01 PM PDT 24 Apr 28 01:05:03 PM PDT 24 16814682 ps
T891 /workspace/coverage/cover_reg_top/5.edn_intr_test.1179797150 Apr 28 01:04:50 PM PDT 24 Apr 28 01:04:52 PM PDT 24 14553376 ps
T228 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3611052488 Apr 28 01:04:52 PM PDT 24 Apr 28 01:04:53 PM PDT 24 22195399 ps
T892 /workspace/coverage/cover_reg_top/32.edn_intr_test.669104089 Apr 28 01:05:02 PM PDT 24 Apr 28 01:05:05 PM PDT 24 128565347 ps
T893 /workspace/coverage/cover_reg_top/31.edn_intr_test.4060129307 Apr 28 01:05:05 PM PDT 24 Apr 28 01:05:08 PM PDT 24 43271784 ps
T894 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3393990261 Apr 28 01:04:47 PM PDT 24 Apr 28 01:04:50 PM PDT 24 174808490 ps
T895 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.911261781 Apr 28 01:04:58 PM PDT 24 Apr 28 01:05:01 PM PDT 24 30933600 ps
T896 /workspace/coverage/cover_reg_top/26.edn_intr_test.2331958354 Apr 28 01:05:04 PM PDT 24 Apr 28 01:05:07 PM PDT 24 30494072 ps
T897 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1592380258 Apr 28 01:04:54 PM PDT 24 Apr 28 01:04:55 PM PDT 24 37658642 ps
T898 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2017809518 Apr 28 01:04:51 PM PDT 24 Apr 28 01:04:53 PM PDT 24 46086372 ps
T899 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1727628956 Apr 28 01:04:49 PM PDT 24 Apr 28 01:04:54 PM PDT 24 526303250 ps
T900 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1492581165 Apr 28 01:04:49 PM PDT 24 Apr 28 01:04:51 PM PDT 24 32460141 ps
T901 /workspace/coverage/cover_reg_top/8.edn_intr_test.1641380948 Apr 28 01:04:50 PM PDT 24 Apr 28 01:04:51 PM PDT 24 23889973 ps
T902 /workspace/coverage/cover_reg_top/21.edn_intr_test.3821720594 Apr 28 01:04:59 PM PDT 24 Apr 28 01:05:02 PM PDT 24 23166202 ps
T903 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.904167336 Apr 28 01:04:58 PM PDT 24 Apr 28 01:05:01 PM PDT 24 151449387 ps
T904 /workspace/coverage/cover_reg_top/16.edn_tl_errors.460303794 Apr 28 01:05:02 PM PDT 24 Apr 28 01:05:07 PM PDT 24 74136051 ps
T905 /workspace/coverage/cover_reg_top/10.edn_intr_test.2339275877 Apr 28 01:04:51 PM PDT 24 Apr 28 01:04:52 PM PDT 24 11538068 ps
T906 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3144564401 Apr 28 01:04:41 PM PDT 24 Apr 28 01:04:44 PM PDT 24 109024445 ps
T907 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1239075343 Apr 28 01:04:57 PM PDT 24 Apr 28 01:05:00 PM PDT 24 150079706 ps
T908 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3058755587 Apr 28 01:04:53 PM PDT 24 Apr 28 01:04:56 PM PDT 24 215900756 ps
T909 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.4216923316 Apr 28 01:04:47 PM PDT 24 Apr 28 01:04:49 PM PDT 24 71943492 ps
T910 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2792154698 Apr 28 01:04:53 PM PDT 24 Apr 28 01:04:54 PM PDT 24 19845250 ps
T911 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2345397212 Apr 28 01:04:40 PM PDT 24 Apr 28 01:04:42 PM PDT 24 17365979 ps
T912 /workspace/coverage/cover_reg_top/1.edn_intr_test.3773782088 Apr 28 01:04:38 PM PDT 24 Apr 28 01:04:40 PM PDT 24 16239087 ps
T913 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1185794188 Apr 28 01:04:59 PM PDT 24 Apr 28 01:05:03 PM PDT 24 333390022 ps
T914 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3031685872 Apr 28 01:04:58 PM PDT 24 Apr 28 01:05:00 PM PDT 24 44019559 ps
T915 /workspace/coverage/cover_reg_top/23.edn_intr_test.2001467399 Apr 28 01:05:04 PM PDT 24 Apr 28 01:05:07 PM PDT 24 78302855 ps
T229 /workspace/coverage/cover_reg_top/18.edn_csr_rw.92945000 Apr 28 01:04:58 PM PDT 24 Apr 28 01:05:00 PM PDT 24 17582931 ps
T250 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1207909861 Apr 28 01:04:39 PM PDT 24 Apr 28 01:04:41 PM PDT 24 156180069 ps
T916 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1816022686 Apr 28 01:04:44 PM PDT 24 Apr 28 01:04:46 PM PDT 24 19544909 ps
T917 /workspace/coverage/cover_reg_top/37.edn_intr_test.2342384145 Apr 28 01:05:02 PM PDT 24 Apr 28 01:05:05 PM PDT 24 47002042 ps
T918 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3526935559 Apr 28 01:04:57 PM PDT 24 Apr 28 01:05:00 PM PDT 24 59627279 ps
T919 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1048095738 Apr 28 01:05:00 PM PDT 24 Apr 28 01:05:03 PM PDT 24 32140478 ps
T920 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2041603676 Apr 28 01:04:46 PM PDT 24 Apr 28 01:04:47 PM PDT 24 46128899 ps
T921 /workspace/coverage/cover_reg_top/9.edn_intr_test.652842863 Apr 28 01:04:57 PM PDT 24 Apr 28 01:04:58 PM PDT 24 155901116 ps
T922 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.218761089 Apr 28 01:04:56 PM PDT 24 Apr 28 01:04:59 PM PDT 24 65195723 ps
T923 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2252535867 Apr 28 01:04:37 PM PDT 24 Apr 28 01:04:40 PM PDT 24 119571688 ps
T924 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2382744036 Apr 28 01:04:48 PM PDT 24 Apr 28 01:04:49 PM PDT 24 29962699 ps
T925 /workspace/coverage/cover_reg_top/15.edn_tl_errors.972773116 Apr 28 01:04:58 PM PDT 24 Apr 28 01:05:01 PM PDT 24 86188959 ps
T926 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2598655405 Apr 28 01:05:05 PM PDT 24 Apr 28 01:05:09 PM PDT 24 54388693 ps
T927 /workspace/coverage/cover_reg_top/42.edn_intr_test.2483701655 Apr 28 01:05:05 PM PDT 24 Apr 28 01:05:08 PM PDT 24 16606774 ps
T928 /workspace/coverage/cover_reg_top/48.edn_intr_test.4206939693 Apr 28 01:05:06 PM PDT 24 Apr 28 01:05:08 PM PDT 24 11593499 ps
T929 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.4261721676 Apr 28 01:04:51 PM PDT 24 Apr 28 01:04:53 PM PDT 24 27907123 ps
T930 /workspace/coverage/cover_reg_top/6.edn_tl_errors.181813000 Apr 28 01:04:47 PM PDT 24 Apr 28 01:04:50 PM PDT 24 224492815 ps
T931 /workspace/coverage/cover_reg_top/3.edn_intr_test.11944702 Apr 28 01:04:43 PM PDT 24 Apr 28 01:04:44 PM PDT 24 14495179 ps
T932 /workspace/coverage/cover_reg_top/22.edn_intr_test.3402655105 Apr 28 01:05:01 PM PDT 24 Apr 28 01:05:04 PM PDT 24 22050053 ps
T933 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2847960573 Apr 28 01:04:55 PM PDT 24 Apr 28 01:04:57 PM PDT 24 17022231 ps
T934 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3077615671 Apr 28 01:04:45 PM PDT 24 Apr 28 01:04:46 PM PDT 24 13500383 ps
T935 /workspace/coverage/cover_reg_top/7.edn_intr_test.3847527176 Apr 28 01:04:48 PM PDT 24 Apr 28 01:04:49 PM PDT 24 18640918 ps
T936 /workspace/coverage/cover_reg_top/47.edn_intr_test.1906881789 Apr 28 01:05:02 PM PDT 24 Apr 28 01:05:04 PM PDT 24 56039879 ps
T937 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.462689204 Apr 28 01:04:50 PM PDT 24 Apr 28 01:04:51 PM PDT 24 27633010 ps
T938 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3311524833 Apr 28 01:04:56 PM PDT 24 Apr 28 01:04:59 PM PDT 24 94312281 ps
T939 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.933257759 Apr 28 01:04:40 PM PDT 24 Apr 28 01:04:44 PM PDT 24 1056301673 ps
T940 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2183408020 Apr 28 01:04:58 PM PDT 24 Apr 28 01:05:01 PM PDT 24 19670746 ps
T941 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1286938309 Apr 28 01:04:42 PM PDT 24 Apr 28 01:04:45 PM PDT 24 39267967 ps
T942 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2800810202 Apr 28 01:04:43 PM PDT 24 Apr 28 01:04:44 PM PDT 24 10967199 ps
T943 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3995497198 Apr 28 01:04:40 PM PDT 24 Apr 28 01:04:44 PM PDT 24 224113079 ps
T944 /workspace/coverage/cover_reg_top/11.edn_intr_test.917575850 Apr 28 01:04:56 PM PDT 24 Apr 28 01:04:58 PM PDT 24 38789963 ps
T251 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1147358694 Apr 28 01:04:59 PM PDT 24 Apr 28 01:05:02 PM PDT 24 226236447 ps
T945 /workspace/coverage/cover_reg_top/3.edn_csr_rw.3157594579 Apr 28 01:04:44 PM PDT 24 Apr 28 01:04:46 PM PDT 24 19312640 ps
T946 /workspace/coverage/cover_reg_top/12.edn_intr_test.4111295915 Apr 28 01:04:57 PM PDT 24 Apr 28 01:04:58 PM PDT 24 25440286 ps
T947 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1141876255 Apr 28 01:05:01 PM PDT 24 Apr 28 01:05:06 PM PDT 24 40871840 ps
T948 /workspace/coverage/cover_reg_top/45.edn_intr_test.1079997799 Apr 28 01:05:03 PM PDT 24 Apr 28 01:05:06 PM PDT 24 14788422 ps
T230 /workspace/coverage/cover_reg_top/4.edn_csr_rw.79962586 Apr 28 01:04:45 PM PDT 24 Apr 28 01:04:47 PM PDT 24 14795717 ps
T949 /workspace/coverage/cover_reg_top/36.edn_intr_test.2106320962 Apr 28 01:05:04 PM PDT 24 Apr 28 01:05:07 PM PDT 24 11128469 ps
T252 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.913085351 Apr 28 01:05:00 PM PDT 24 Apr 28 01:05:03 PM PDT 24 337216984 ps
T950 /workspace/coverage/cover_reg_top/33.edn_intr_test.3406660499 Apr 28 01:05:04 PM PDT 24 Apr 28 01:05:07 PM PDT 24 33226693 ps
T951 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3552911046 Apr 28 01:04:49 PM PDT 24 Apr 28 01:04:51 PM PDT 24 47228374 ps
T952 /workspace/coverage/cover_reg_top/46.edn_intr_test.3009849986 Apr 28 01:05:03 PM PDT 24 Apr 28 01:05:06 PM PDT 24 47725967 ps
T953 /workspace/coverage/cover_reg_top/43.edn_intr_test.4117896849 Apr 28 01:05:01 PM PDT 24 Apr 28 01:05:04 PM PDT 24 29289079 ps
T954 /workspace/coverage/cover_reg_top/24.edn_intr_test.816185423 Apr 28 01:05:04 PM PDT 24 Apr 28 01:05:07 PM PDT 24 41986130 ps
T955 /workspace/coverage/cover_reg_top/17.edn_intr_test.3538627164 Apr 28 01:04:57 PM PDT 24 Apr 28 01:04:58 PM PDT 24 82487883 ps
T956 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2134562851 Apr 28 01:05:05 PM PDT 24 Apr 28 01:05:08 PM PDT 24 15944319 ps
T957 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3825571571 Apr 28 01:04:59 PM PDT 24 Apr 28 01:05:03 PM PDT 24 31529678 ps
T958 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3835570246 Apr 28 01:04:43 PM PDT 24 Apr 28 01:04:44 PM PDT 24 17443430 ps
T959 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2487123108 Apr 28 01:04:56 PM PDT 24 Apr 28 01:04:59 PM PDT 24 403829208 ps
T960 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1629652907 Apr 28 01:04:45 PM PDT 24 Apr 28 01:04:47 PM PDT 24 32534756 ps
T961 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2292074610 Apr 28 01:04:57 PM PDT 24 Apr 28 01:04:59 PM PDT 24 67665341 ps
T962 /workspace/coverage/cover_reg_top/1.edn_csr_rw.605185945 Apr 28 01:04:39 PM PDT 24 Apr 28 01:04:40 PM PDT 24 17125385 ps
T963 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3257318820 Apr 28 01:04:55 PM PDT 24 Apr 28 01:04:57 PM PDT 24 119535265 ps
T248 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.985295204 Apr 28 01:04:55 PM PDT 24 Apr 28 01:04:57 PM PDT 24 63243253 ps
T964 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1116789923 Apr 28 01:04:40 PM PDT 24 Apr 28 01:04:42 PM PDT 24 20338263 ps
T965 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1275511103 Apr 28 01:04:37 PM PDT 24 Apr 28 01:04:40 PM PDT 24 204439952 ps
T966 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3633481267 Apr 28 01:04:58 PM PDT 24 Apr 28 01:05:01 PM PDT 24 43955608 ps
T967 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.828824926 Apr 28 01:04:40 PM PDT 24 Apr 28 01:04:43 PM PDT 24 96009030 ps
T968 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1864380874 Apr 28 01:04:59 PM PDT 24 Apr 28 01:05:02 PM PDT 24 16415854 ps
T969 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3700297038 Apr 28 01:04:46 PM PDT 24 Apr 28 01:04:48 PM PDT 24 125169923 ps
T970 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3839900375 Apr 28 01:04:54 PM PDT 24 Apr 28 01:04:56 PM PDT 24 27618160 ps
T971 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3603812778 Apr 28 01:04:39 PM PDT 24 Apr 28 01:04:40 PM PDT 24 85473578 ps
T972 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.63934329 Apr 28 01:04:54 PM PDT 24 Apr 28 01:04:56 PM PDT 24 12037531 ps
T973 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2995369581 Apr 28 01:04:55 PM PDT 24 Apr 28 01:04:58 PM PDT 24 242689151 ps
T974 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3993160991 Apr 28 01:04:41 PM PDT 24 Apr 28 01:04:44 PM PDT 24 498383734 ps
T975 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1024951132 Apr 28 01:04:51 PM PDT 24 Apr 28 01:04:53 PM PDT 24 77584781 ps
T976 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1371481600 Apr 28 01:04:55 PM PDT 24 Apr 28 01:04:56 PM PDT 24 24336301 ps
T977 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3309337779 Apr 28 01:04:42 PM PDT 24 Apr 28 01:04:47 PM PDT 24 542958406 ps
T978 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1107317721 Apr 28 01:04:39 PM PDT 24 Apr 28 01:04:41 PM PDT 24 30612824 ps

Test location /workspace/coverage/default/197.edn_genbits.106684420
Short name T21
Test name
Test status
Simulation time 53969885 ps
CPU time 1.82 seconds
Started Apr 28 04:30:38 PM PDT 24
Finished Apr 28 04:30:42 PM PDT 24
Peak memory 217116 kb
Host smart-689e02ba-87cc-476e-b5d6-7b3cd48fe10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106684420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.106684420
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2687749757
Short name T14
Test name
Test status
Simulation time 308782050 ps
CPU time 4.6 seconds
Started Apr 28 04:27:40 PM PDT 24
Finished Apr 28 04:27:45 PM PDT 24
Peak memory 235844 kb
Host smart-b1056ce4-1ad0-4bc9-9a74-2d2bf09ddf42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687749757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2687749757
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.969758971
Short name T37
Test name
Test status
Simulation time 62122642247 ps
CPU time 416.66 seconds
Started Apr 28 04:29:13 PM PDT 24
Finished Apr 28 04:36:11 PM PDT 24
Peak memory 217436 kb
Host smart-c9fa2636-9999-495a-8828-64dd060c742c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969758971 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.969758971
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.edn_genbits.556866260
Short name T3
Test name
Test status
Simulation time 50579040 ps
CPU time 1.4 seconds
Started Apr 28 04:28:35 PM PDT 24
Finished Apr 28 04:28:36 PM PDT 24
Peak memory 219360 kb
Host smart-f801d9fe-0aef-4c91-a439-f388cd4a404c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556866260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.556866260
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2528105622
Short name T26
Test name
Test status
Simulation time 149247713 ps
CPU time 1.26 seconds
Started Apr 28 04:28:02 PM PDT 24
Finished Apr 28 04:28:04 PM PDT 24
Peak memory 215552 kb
Host smart-0a6e59fa-7df2-45cd-9ec1-c9e583eb2227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528105622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2528105622
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3555816391
Short name T15
Test name
Test status
Simulation time 499062602 ps
CPU time 8.51 seconds
Started Apr 28 04:27:52 PM PDT 24
Finished Apr 28 04:28:01 PM PDT 24
Peak memory 237212 kb
Host smart-0400ed34-c22d-4ccf-8a4d-a58980d240a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555816391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3555816391
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1522702944
Short name T161
Test name
Test status
Simulation time 51253418 ps
CPU time 1.14 seconds
Started Apr 28 04:29:29 PM PDT 24
Finished Apr 28 04:29:31 PM PDT 24
Peak memory 217820 kb
Host smart-0eaef53a-e477-4af4-994d-e46db77f13d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522702944 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1522702944
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_alert.1185675638
Short name T49
Test name
Test status
Simulation time 66431436 ps
CPU time 1.16 seconds
Started Apr 28 04:28:32 PM PDT 24
Finished Apr 28 04:28:34 PM PDT 24
Peak memory 215532 kb
Host smart-cab4646a-6426-4db7-839e-cf06e9f42733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185675638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1185675638
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1365642613
Short name T148
Test name
Test status
Simulation time 30412959416 ps
CPU time 371.84 seconds
Started Apr 28 04:27:52 PM PDT 24
Finished Apr 28 04:34:04 PM PDT 24
Peak memory 218172 kb
Host smart-3a93cfcb-77e0-4512-904b-9690cf2e6aeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365642613 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1365642613
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.edn_regwen.1485083608
Short name T23
Test name
Test status
Simulation time 18994587 ps
CPU time 1.09 seconds
Started Apr 28 04:27:32 PM PDT 24
Finished Apr 28 04:27:34 PM PDT 24
Peak memory 206960 kb
Host smart-087c1999-c67a-4cea-9e69-19ac76ea9876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485083608 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1485083608
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/11.edn_alert.2489855284
Short name T146
Test name
Test status
Simulation time 41143429 ps
CPU time 1.16 seconds
Started Apr 28 04:28:07 PM PDT 24
Finished Apr 28 04:28:09 PM PDT 24
Peak memory 215572 kb
Host smart-5c2dcbd0-9dcd-4a00-9a3e-9e07cce6e8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489855284 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2489855284
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/46.edn_disable.3322746800
Short name T47
Test name
Test status
Simulation time 51030136 ps
CPU time 0.95 seconds
Started Apr 28 04:29:48 PM PDT 24
Finished Apr 28 04:29:50 PM PDT 24
Peak memory 216084 kb
Host smart-3ff68ae3-398c-4424-a268-fcb95078ca2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322746800 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3322746800
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.4280411505
Short name T222
Test name
Test status
Simulation time 113295643 ps
CPU time 1.55 seconds
Started Apr 28 01:04:44 PM PDT 24
Finished Apr 28 01:04:47 PM PDT 24
Peak memory 206324 kb
Host smart-ec9a88d1-84ce-41ee-adae-d611d1822b06
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280411505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.4280411505
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3947241081
Short name T101
Test name
Test status
Simulation time 46780928 ps
CPU time 1.54 seconds
Started Apr 28 04:29:44 PM PDT 24
Finished Apr 28 04:29:46 PM PDT 24
Peak memory 216788 kb
Host smart-d56cb11a-2b51-430f-ac9f-b12de8842dd9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947241081 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3947241081
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2927246338
Short name T206
Test name
Test status
Simulation time 186405423 ps
CPU time 1.49 seconds
Started Apr 28 01:04:59 PM PDT 24
Finished Apr 28 01:05:02 PM PDT 24
Peak memory 206384 kb
Host smart-e94b852e-d9ed-4e81-9f51-dd617aaaea5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927246338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2927246338
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/default/10.edn_disable.1332496557
Short name T143
Test name
Test status
Simulation time 14060152 ps
CPU time 0.82 seconds
Started Apr 28 04:28:11 PM PDT 24
Finished Apr 28 04:28:12 PM PDT 24
Peak memory 216036 kb
Host smart-1dc89bca-7cad-4917-bffb-d4acd5352017
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332496557 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1332496557
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2331492400
Short name T118
Test name
Test status
Simulation time 46556899 ps
CPU time 1.48 seconds
Started Apr 28 04:28:15 PM PDT 24
Finished Apr 28 04:28:17 PM PDT 24
Peak memory 216756 kb
Host smart-50d61b62-4736-4f77-bc41-6e262b48def9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331492400 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2331492400
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_alert.819550463
Short name T240
Test name
Test status
Simulation time 41135763 ps
CPU time 1.33 seconds
Started Apr 28 04:29:34 PM PDT 24
Finished Apr 28 04:29:36 PM PDT 24
Peak memory 215468 kb
Host smart-08e641ef-b906-442f-ba87-2ca7c8953977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819550463 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.819550463
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.1748904423
Short name T13
Test name
Test status
Simulation time 33742245 ps
CPU time 1.07 seconds
Started Apr 28 04:30:05 PM PDT 24
Finished Apr 28 04:30:07 PM PDT 24
Peak memory 223736 kb
Host smart-664bd973-0e73-48ba-963e-8fd1d34dc094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748904423 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1748904423
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2883424434
Short name T83
Test name
Test status
Simulation time 239772268 ps
CPU time 1.23 seconds
Started Apr 28 04:27:34 PM PDT 24
Finished Apr 28 04:27:36 PM PDT 24
Peak memory 216596 kb
Host smart-98931478-ce09-402a-9a66-9821725981aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883424434 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2883424434
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_alert.1127394541
Short name T242
Test name
Test status
Simulation time 310961362 ps
CPU time 1.3 seconds
Started Apr 28 04:28:44 PM PDT 24
Finished Apr 28 04:28:46 PM PDT 24
Peak memory 215528 kb
Host smart-480dcb2d-7c70-47de-b895-59a8b6109bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127394541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1127394541
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2356932822
Short name T50
Test name
Test status
Simulation time 27178420 ps
CPU time 1.13 seconds
Started Apr 28 04:28:52 PM PDT 24
Finished Apr 28 04:28:55 PM PDT 24
Peak memory 206604 kb
Host smart-4e4c779a-9b3d-4582-b488-75b76691e00b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356932822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2356932822
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_genbits.387374185
Short name T271
Test name
Test status
Simulation time 101705247 ps
CPU time 1.39 seconds
Started Apr 28 04:28:45 PM PDT 24
Finished Apr 28 04:28:47 PM PDT 24
Peak memory 218228 kb
Host smart-fa537814-691f-4e1f-adbd-f67bc9213755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387374185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.387374185
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.327400879
Short name T33
Test name
Test status
Simulation time 28107529 ps
CPU time 0.88 seconds
Started Apr 28 04:27:58 PM PDT 24
Finished Apr 28 04:27:59 PM PDT 24
Peak memory 215588 kb
Host smart-5934c2f4-f9a7-4aba-ae86-0ca85a86fa07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327400879 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.327400879
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/119.edn_genbits.261363895
Short name T10
Test name
Test status
Simulation time 23243186 ps
CPU time 1.18 seconds
Started Apr 28 04:30:26 PM PDT 24
Finished Apr 28 04:30:28 PM PDT 24
Peak memory 217080 kb
Host smart-43de42b1-2ed9-44ee-98b7-328f6979befb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261363895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.261363895
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_regwen.2647763196
Short name T24
Test name
Test status
Simulation time 16150258 ps
CPU time 1.01 seconds
Started Apr 28 04:27:56 PM PDT 24
Finished Apr 28 04:27:58 PM PDT 24
Peak memory 206956 kb
Host smart-edf18989-68b1-487f-917d-c3bf065e0c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647763196 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2647763196
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/90.edn_genbits.1619789239
Short name T246
Test name
Test status
Simulation time 83897443 ps
CPU time 1.15 seconds
Started Apr 28 04:30:10 PM PDT 24
Finished Apr 28 04:30:12 PM PDT 24
Peak memory 216740 kb
Host smart-b8c44c8e-a77d-4c11-b5a4-1519bfc8c5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619789239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1619789239
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_disable.3311626054
Short name T84
Test name
Test status
Simulation time 38131676 ps
CPU time 0.9 seconds
Started Apr 28 04:28:23 PM PDT 24
Finished Apr 28 04:28:25 PM PDT 24
Peak memory 207080 kb
Host smart-1f51893e-541e-41d9-8a81-05395bbad39d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311626054 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3311626054
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable.856540706
Short name T156
Test name
Test status
Simulation time 13932534 ps
CPU time 0.97 seconds
Started Apr 28 04:28:28 PM PDT 24
Finished Apr 28 04:28:29 PM PDT 24
Peak memory 216416 kb
Host smart-f1646b9d-dda0-44f3-af32-25e2deedc4b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856540706 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.856540706
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3621357884
Short name T77
Test name
Test status
Simulation time 31925147 ps
CPU time 1.24 seconds
Started Apr 28 04:29:30 PM PDT 24
Finished Apr 28 04:29:32 PM PDT 24
Peak memory 216616 kb
Host smart-54efb29c-d670-4e96-b474-edda341b1851
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621357884 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3621357884
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_intr.2485280415
Short name T561
Test name
Test status
Simulation time 19644725 ps
CPU time 1.11 seconds
Started Apr 28 04:28:10 PM PDT 24
Finished Apr 28 04:28:11 PM PDT 24
Peak memory 215716 kb
Host smart-10a31cff-4b01-4222-8492-24393656ee79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485280415 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2485280415
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable.1031596297
Short name T166
Test name
Test status
Simulation time 27411664 ps
CPU time 0.94 seconds
Started Apr 28 04:27:47 PM PDT 24
Finished Apr 28 04:27:49 PM PDT 24
Peak memory 216000 kb
Host smart-3b2b5b7a-31e7-4eed-9ce2-5c6aea00a842
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031596297 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1031596297
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable.4186336636
Short name T368
Test name
Test status
Simulation time 40244881 ps
CPU time 0.96 seconds
Started Apr 28 04:28:11 PM PDT 24
Finished Apr 28 04:28:12 PM PDT 24
Peak memory 216108 kb
Host smart-8b5a0a54-12d8-4591-878e-5c922e32209f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186336636 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.4186336636
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable.192366737
Short name T175
Test name
Test status
Simulation time 14998110 ps
CPU time 1.01 seconds
Started Apr 28 04:28:20 PM PDT 24
Finished Apr 28 04:28:21 PM PDT 24
Peak memory 216376 kb
Host smart-53cb090f-204a-4df7-abed-27794cdec1ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192366737 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.192366737
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3871679443
Short name T179
Test name
Test status
Simulation time 30134268 ps
CPU time 1.3 seconds
Started Apr 28 04:28:27 PM PDT 24
Finished Apr 28 04:28:29 PM PDT 24
Peak memory 216920 kb
Host smart-57489f27-bacf-42b5-a00d-979dc9d412e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871679443 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3871679443
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.994005488
Short name T172
Test name
Test status
Simulation time 12904838782 ps
CPU time 313.41 seconds
Started Apr 28 04:28:33 PM PDT 24
Finished Apr 28 04:33:47 PM PDT 24
Peak memory 219828 kb
Host smart-81c1fc7b-6698-4d1b-8638-f24ca211036b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994005488 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.994005488
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.edn_disable.4284789944
Short name T138
Test name
Test status
Simulation time 14091261 ps
CPU time 0.93 seconds
Started Apr 28 04:29:00 PM PDT 24
Finished Apr 28 04:29:01 PM PDT 24
Peak memory 215300 kb
Host smart-2ca3f82b-26e4-4ddc-850a-245cd68446a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284789944 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.4284789944
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3988842129
Short name T106
Test name
Test status
Simulation time 33182899 ps
CPU time 1.19 seconds
Started Apr 28 04:29:28 PM PDT 24
Finished Apr 28 04:29:29 PM PDT 24
Peak memory 217952 kb
Host smart-875dc0ae-a988-4bc8-ba14-b312095598dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988842129 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3988842129
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_disable.3291599963
Short name T157
Test name
Test status
Simulation time 37806064 ps
CPU time 0.9 seconds
Started Apr 28 04:27:52 PM PDT 24
Finished Apr 28 04:27:54 PM PDT 24
Peak memory 216184 kb
Host smart-6e6ada58-95b4-4938-b604-c0725c159623
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291599963 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3291599963
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/166.edn_genbits.241117749
Short name T287
Test name
Test status
Simulation time 191628600 ps
CPU time 3.65 seconds
Started Apr 28 04:30:36 PM PDT 24
Finished Apr 28 04:30:40 PM PDT 24
Peak memory 218516 kb
Host smart-5bffc4d8-815b-4e82-84db-133bfa97be1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241117749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.241117749
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.3479785932
Short name T253
Test name
Test status
Simulation time 25999223 ps
CPU time 0.92 seconds
Started Apr 28 04:27:34 PM PDT 24
Finished Apr 28 04:27:36 PM PDT 24
Peak memory 206956 kb
Host smart-634145c7-63e4-4ad2-83da-29b9df6fec07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479785932 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3479785932
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/283.edn_genbits.240178685
Short name T276
Test name
Test status
Simulation time 400327697 ps
CPU time 1.32 seconds
Started Apr 28 04:31:01 PM PDT 24
Finished Apr 28 04:31:03 PM PDT 24
Peak memory 218348 kb
Host smart-d25b1899-6aba-41d9-8f12-cd5367413760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240178685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.240178685
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1207909861
Short name T250
Test name
Test status
Simulation time 156180069 ps
CPU time 1.52 seconds
Started Apr 28 01:04:39 PM PDT 24
Finished Apr 28 01:04:41 PM PDT 24
Peak memory 214612 kb
Host smart-09aafe27-f3c8-4deb-b9de-d3dd69e44c09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207909861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1207909861
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/10.edn_stress_all.967106388
Short name T207
Test name
Test status
Simulation time 620347998 ps
CPU time 6.25 seconds
Started Apr 28 04:28:10 PM PDT 24
Finished Apr 28 04:28:16 PM PDT 24
Peak memory 216800 kb
Host smart-c96c5db2-6071-4beb-9d95-55a3dccdc3a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967106388 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.967106388
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_intr.1664751700
Short name T34
Test name
Test status
Simulation time 23936738 ps
CPU time 1.16 seconds
Started Apr 28 04:28:22 PM PDT 24
Finished Apr 28 04:28:23 PM PDT 24
Peak memory 215820 kb
Host smart-9c3185b3-774c-46c9-b631-d73547fc373c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664751700 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1664751700
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/28.edn_alert.1992285751
Short name T182
Test name
Test status
Simulation time 29380122 ps
CPU time 1.31 seconds
Started Apr 28 04:29:00 PM PDT 24
Finished Apr 28 04:29:02 PM PDT 24
Peak memory 215556 kb
Host smart-d84bffa0-ace5-45d2-895b-d59dfd63708d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992285751 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1992285751
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1872394406
Short name T217
Test name
Test status
Simulation time 62402542 ps
CPU time 0.99 seconds
Started Apr 28 01:04:57 PM PDT 24
Finished Apr 28 01:04:59 PM PDT 24
Peak memory 206380 kb
Host smart-d2cfb08c-7fe6-4d85-a90a-fe69cf841b3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872394406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1872394406
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/114.edn_genbits.2423968199
Short name T546
Test name
Test status
Simulation time 36679907 ps
CPU time 1.39 seconds
Started Apr 28 04:30:21 PM PDT 24
Finished Apr 28 04:30:23 PM PDT 24
Peak memory 218056 kb
Host smart-3d207c7d-aaa5-4572-8bb3-3a8073ff5b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423968199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2423968199
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.3648484719
Short name T353
Test name
Test status
Simulation time 424100541 ps
CPU time 4.78 seconds
Started Apr 28 04:30:23 PM PDT 24
Finished Apr 28 04:30:28 PM PDT 24
Peak memory 218428 kb
Host smart-873d1410-1274-4f6b-872d-e839ef79dbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648484719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3648484719
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.3342824074
Short name T504
Test name
Test status
Simulation time 42779934 ps
CPU time 1.52 seconds
Started Apr 28 04:30:26 PM PDT 24
Finished Apr 28 04:30:28 PM PDT 24
Peak memory 218072 kb
Host smart-ac59c45a-efa1-4556-8a04-b0a70797350a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342824074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3342824074
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.3242012418
Short name T497
Test name
Test status
Simulation time 22637704 ps
CPU time 1.12 seconds
Started Apr 28 04:30:31 PM PDT 24
Finished Apr 28 04:30:33 PM PDT 24
Peak memory 216860 kb
Host smart-1027d037-3de5-477d-a674-fa4d82dc776f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242012418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3242012418
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/170.edn_genbits.3363297773
Short name T48
Test name
Test status
Simulation time 32197091 ps
CPU time 1.56 seconds
Started Apr 28 04:30:37 PM PDT 24
Finished Apr 28 04:30:40 PM PDT 24
Peak memory 218172 kb
Host smart-bd7d6ab4-df9c-4c17-b093-5939bc7016df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363297773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3363297773
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/190.edn_genbits.2452890509
Short name T17
Test name
Test status
Simulation time 146638821 ps
CPU time 3.37 seconds
Started Apr 28 04:30:35 PM PDT 24
Finished Apr 28 04:30:39 PM PDT 24
Peak memory 217248 kb
Host smart-07216b48-3b5c-47ef-a959-50a3934527de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452890509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2452890509
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.589247560
Short name T284
Test name
Test status
Simulation time 112766509 ps
CPU time 2.17 seconds
Started Apr 28 04:30:43 PM PDT 24
Finished Apr 28 04:30:46 PM PDT 24
Peak memory 219400 kb
Host smart-60d42cec-1d57-4c6a-831d-206609f45ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589247560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.589247560
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1765551734
Short name T293
Test name
Test status
Simulation time 53178464 ps
CPU time 1.68 seconds
Started Apr 28 04:30:50 PM PDT 24
Finished Apr 28 04:30:53 PM PDT 24
Peak memory 219420 kb
Host smart-abc17063-2844-4ae5-a858-192a56b7019d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765551734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1765551734
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.763018863
Short name T18
Test name
Test status
Simulation time 36344469 ps
CPU time 1.35 seconds
Started Apr 28 04:30:48 PM PDT 24
Finished Apr 28 04:30:50 PM PDT 24
Peak memory 217992 kb
Host smart-147be8ba-7759-42d5-b8ab-6f03343ea996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763018863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.763018863
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1175770180
Short name T76
Test name
Test status
Simulation time 44988414 ps
CPU time 1.79 seconds
Started Apr 28 04:30:46 PM PDT 24
Finished Apr 28 04:30:48 PM PDT 24
Peak memory 218100 kb
Host smart-793434b2-8c45-4872-a2f1-18f587fbb7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175770180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1175770180
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.4103292550
Short name T269
Test name
Test status
Simulation time 122043084 ps
CPU time 1.93 seconds
Started Apr 28 04:30:57 PM PDT 24
Finished Apr 28 04:30:59 PM PDT 24
Peak memory 218788 kb
Host smart-162a37be-b07f-4181-8f23-adf89b88da97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103292550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.4103292550
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2042950549
Short name T93
Test name
Test status
Simulation time 63250191 ps
CPU time 0.89 seconds
Started Apr 28 04:28:28 PM PDT 24
Finished Apr 28 04:28:29 PM PDT 24
Peak memory 215448 kb
Host smart-dbd0e4dd-2bba-46a5-9ae5-ddfc7a82e7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042950549 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2042950549
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/21.edn_disable.2073909489
Short name T387
Test name
Test status
Simulation time 14886811 ps
CPU time 0.96 seconds
Started Apr 28 04:28:43 PM PDT 24
Finished Apr 28 04:28:44 PM PDT 24
Peak memory 216292 kb
Host smart-cf86180a-d256-4021-b93c-96e04a08290e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073909489 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2073909489
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/24.edn_alert.182300740
Short name T184
Test name
Test status
Simulation time 105272435 ps
CPU time 1.35 seconds
Started Apr 28 04:28:47 PM PDT 24
Finished Apr 28 04:28:49 PM PDT 24
Peak memory 215564 kb
Host smart-ac68e08b-4c51-4cd8-8c9b-4a0d12acc722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182300740 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.182300740
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.530619997
Short name T370
Test name
Test status
Simulation time 36987852 ps
CPU time 1.55 seconds
Started Apr 28 04:30:32 PM PDT 24
Finished Apr 28 04:30:34 PM PDT 24
Peak memory 219716 kb
Host smart-df210df1-96e8-4f83-8e27-174b17d6eabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530619997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.530619997
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_err.4057816152
Short name T113
Test name
Test status
Simulation time 25465479 ps
CPU time 1.17 seconds
Started Apr 28 04:27:43 PM PDT 24
Finished Apr 28 04:27:44 PM PDT 24
Peak memory 220476 kb
Host smart-c4aa14e1-13fb-44df-96c3-73ab81d83fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057816152 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.4057816152
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2276077223
Short name T219
Test name
Test status
Simulation time 15240935 ps
CPU time 1.03 seconds
Started Apr 28 01:04:37 PM PDT 24
Finished Apr 28 01:04:38 PM PDT 24
Peak memory 206272 kb
Host smart-20130416-cdb2-4f7e-9d6e-facac3f1d1da
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276077223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2276077223
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3995497198
Short name T943
Test name
Test status
Simulation time 224113079 ps
CPU time 3.29 seconds
Started Apr 28 01:04:40 PM PDT 24
Finished Apr 28 01:04:44 PM PDT 24
Peak memory 206292 kb
Host smart-d4e83d82-9d69-4178-8a63-bd0e2c34ad1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995497198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3995497198
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2345397212
Short name T911
Test name
Test status
Simulation time 17365979 ps
CPU time 0.95 seconds
Started Apr 28 01:04:40 PM PDT 24
Finished Apr 28 01:04:42 PM PDT 24
Peak memory 206260 kb
Host smart-2bafebd6-bdbd-420c-9f6f-c93d9d640063
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345397212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2345397212
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2252535867
Short name T923
Test name
Test status
Simulation time 119571688 ps
CPU time 1.51 seconds
Started Apr 28 01:04:37 PM PDT 24
Finished Apr 28 01:04:40 PM PDT 24
Peak memory 214476 kb
Host smart-0db34299-2a7f-4559-9286-7e33797a96e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252535867 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2252535867
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2241267530
Short name T868
Test name
Test status
Simulation time 46568123 ps
CPU time 0.84 seconds
Started Apr 28 01:04:36 PM PDT 24
Finished Apr 28 01:04:38 PM PDT 24
Peak memory 206232 kb
Host smart-094908e8-4894-4f0d-8cf5-e9ab1931980f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241267530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2241267530
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1872934286
Short name T861
Test name
Test status
Simulation time 56919270 ps
CPU time 0.85 seconds
Started Apr 28 01:04:39 PM PDT 24
Finished Apr 28 01:04:41 PM PDT 24
Peak memory 206220 kb
Host smart-1120b6ed-6d8a-4313-a711-b09ab0a73bda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872934286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1872934286
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1116789923
Short name T964
Test name
Test status
Simulation time 20338263 ps
CPU time 1.16 seconds
Started Apr 28 01:04:40 PM PDT 24
Finished Apr 28 01:04:42 PM PDT 24
Peak memory 206304 kb
Host smart-575b8a89-5bfe-43c6-b48e-59a371ddacde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116789923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1116789923
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3993160991
Short name T974
Test name
Test status
Simulation time 498383734 ps
CPU time 3.15 seconds
Started Apr 28 01:04:41 PM PDT 24
Finished Apr 28 01:04:44 PM PDT 24
Peak memory 214416 kb
Host smart-1acba8cd-c5f6-42ed-9e05-7a6dec4dca31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993160991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3993160991
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.828824926
Short name T967
Test name
Test status
Simulation time 96009030 ps
CPU time 2.36 seconds
Started Apr 28 01:04:40 PM PDT 24
Finished Apr 28 01:04:43 PM PDT 24
Peak memory 206236 kb
Host smart-de2eb2b3-5eef-4b50-9f6f-43261aadb263
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828824926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.828824926
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1579952919
Short name T224
Test name
Test status
Simulation time 43548214 ps
CPU time 1.6 seconds
Started Apr 28 01:04:38 PM PDT 24
Finished Apr 28 01:04:40 PM PDT 24
Peak memory 206420 kb
Host smart-34270f9e-60e8-42f2-a0af-f27e5e041f41
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579952919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1579952919
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.933257759
Short name T939
Test name
Test status
Simulation time 1056301673 ps
CPU time 3.52 seconds
Started Apr 28 01:04:40 PM PDT 24
Finished Apr 28 01:04:44 PM PDT 24
Peak memory 206284 kb
Host smart-baef2a63-5c41-4e15-969b-4066f24081a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933257759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.933257759
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.151057169
Short name T227
Test name
Test status
Simulation time 13646968 ps
CPU time 0.89 seconds
Started Apr 28 01:04:38 PM PDT 24
Finished Apr 28 01:04:40 PM PDT 24
Peak memory 206328 kb
Host smart-f9a3d9ca-531e-488b-ab9c-963edfeb9ff1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151057169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.151057169
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1107317721
Short name T978
Test name
Test status
Simulation time 30612824 ps
CPU time 0.96 seconds
Started Apr 28 01:04:39 PM PDT 24
Finished Apr 28 01:04:41 PM PDT 24
Peak memory 206380 kb
Host smart-f4fd3ce3-73bf-4153-9fc5-c0eff1cff552
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107317721 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1107317721
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.605185945
Short name T962
Test name
Test status
Simulation time 17125385 ps
CPU time 0.91 seconds
Started Apr 28 01:04:39 PM PDT 24
Finished Apr 28 01:04:40 PM PDT 24
Peak memory 206064 kb
Host smart-1fa99511-8a4b-423e-a1a3-b2f561fae3f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605185945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.605185945
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3773782088
Short name T912
Test name
Test status
Simulation time 16239087 ps
CPU time 0.88 seconds
Started Apr 28 01:04:38 PM PDT 24
Finished Apr 28 01:04:40 PM PDT 24
Peak memory 206200 kb
Host smart-3b97fbc3-f44d-4b10-b5e0-9285e55b6b88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773782088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3773782088
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3603812778
Short name T971
Test name
Test status
Simulation time 85473578 ps
CPU time 0.98 seconds
Started Apr 28 01:04:39 PM PDT 24
Finished Apr 28 01:04:40 PM PDT 24
Peak memory 206328 kb
Host smart-2175e864-60f7-448a-91af-c4655fc06e3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603812778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3603812778
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.653330299
Short name T873
Test name
Test status
Simulation time 206689622 ps
CPU time 1.65 seconds
Started Apr 28 01:04:41 PM PDT 24
Finished Apr 28 01:04:43 PM PDT 24
Peak memory 222588 kb
Host smart-fc6636cd-c738-4255-bd23-674d4df4d98f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653330299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.653330299
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3257318820
Short name T963
Test name
Test status
Simulation time 119535265 ps
CPU time 1.46 seconds
Started Apr 28 01:04:55 PM PDT 24
Finished Apr 28 01:04:57 PM PDT 24
Peak memory 214620 kb
Host smart-bb36dc1a-8548-4324-a589-65601d3441b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257318820 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3257318820
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3611052488
Short name T228
Test name
Test status
Simulation time 22195399 ps
CPU time 0.83 seconds
Started Apr 28 01:04:52 PM PDT 24
Finished Apr 28 01:04:53 PM PDT 24
Peak memory 206256 kb
Host smart-f21f741c-8f33-4271-8ef8-960c5447b6b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611052488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3611052488
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2339275877
Short name T905
Test name
Test status
Simulation time 11538068 ps
CPU time 0.81 seconds
Started Apr 28 01:04:51 PM PDT 24
Finished Apr 28 01:04:52 PM PDT 24
Peak memory 206216 kb
Host smart-72426236-0ad3-4944-b93a-f516e0312d6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339275877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2339275877
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.829378401
Short name T860
Test name
Test status
Simulation time 559073358 ps
CPU time 2.03 seconds
Started Apr 28 01:04:51 PM PDT 24
Finished Apr 28 01:04:54 PM PDT 24
Peak memory 214484 kb
Host smart-3163ccec-1a92-48f9-815d-87849000a5e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829378401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.829378401
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2995369581
Short name T973
Test name
Test status
Simulation time 242689151 ps
CPU time 2.01 seconds
Started Apr 28 01:04:55 PM PDT 24
Finished Apr 28 01:04:58 PM PDT 24
Peak memory 206488 kb
Host smart-5e77c33c-8593-4d30-b1b1-1148e5eed30e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995369581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2995369581
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.218761089
Short name T922
Test name
Test status
Simulation time 65195723 ps
CPU time 1.52 seconds
Started Apr 28 01:04:56 PM PDT 24
Finished Apr 28 01:04:59 PM PDT 24
Peak memory 214588 kb
Host smart-02b1153d-ee33-4b82-83d5-762f84484c96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218761089 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.218761089
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.921559101
Short name T885
Test name
Test status
Simulation time 17889689 ps
CPU time 0.78 seconds
Started Apr 28 01:04:53 PM PDT 24
Finished Apr 28 01:04:54 PM PDT 24
Peak memory 206036 kb
Host smart-86c6e0c2-f105-4e9a-9d40-fe3a1cc0f6e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921559101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.921559101
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.917575850
Short name T944
Test name
Test status
Simulation time 38789963 ps
CPU time 0.86 seconds
Started Apr 28 01:04:56 PM PDT 24
Finished Apr 28 01:04:58 PM PDT 24
Peak memory 206216 kb
Host smart-bdd6540f-f0e6-4d58-8e14-463ed465fb73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917575850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.917575850
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.63934329
Short name T972
Test name
Test status
Simulation time 12037531 ps
CPU time 0.87 seconds
Started Apr 28 01:04:54 PM PDT 24
Finished Apr 28 01:04:56 PM PDT 24
Peak memory 206348 kb
Host smart-95ff651e-675c-433d-88ce-4c8ae9bd01aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63934329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_out
standing.63934329
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.4035593178
Short name T887
Test name
Test status
Simulation time 332189828 ps
CPU time 2.14 seconds
Started Apr 28 01:04:53 PM PDT 24
Finished Apr 28 01:04:56 PM PDT 24
Peak memory 214556 kb
Host smart-ad850c4b-0e8a-45ad-acb1-ca3e27d9ea97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035593178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.4035593178
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2487123108
Short name T959
Test name
Test status
Simulation time 403829208 ps
CPU time 2.4 seconds
Started Apr 28 01:04:56 PM PDT 24
Finished Apr 28 01:04:59 PM PDT 24
Peak memory 206400 kb
Host smart-d82193e3-01e7-445b-adc7-a43d3829f191
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487123108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2487123108
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2017809518
Short name T898
Test name
Test status
Simulation time 46086372 ps
CPU time 1.19 seconds
Started Apr 28 01:04:51 PM PDT 24
Finished Apr 28 01:04:53 PM PDT 24
Peak memory 214600 kb
Host smart-c13063fc-2d80-4761-a07a-8837cc8f5a30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017809518 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2017809518
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2792154698
Short name T910
Test name
Test status
Simulation time 19845250 ps
CPU time 0.88 seconds
Started Apr 28 01:04:53 PM PDT 24
Finished Apr 28 01:04:54 PM PDT 24
Peak memory 206316 kb
Host smart-b2afadff-41ba-4d82-b457-565e8489f758
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792154698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2792154698
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.4111295915
Short name T946
Test name
Test status
Simulation time 25440286 ps
CPU time 0.85 seconds
Started Apr 28 01:04:57 PM PDT 24
Finished Apr 28 01:04:58 PM PDT 24
Peak memory 206184 kb
Host smart-a440ac5b-ec39-4955-9bc2-17485b9846ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111295915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.4111295915
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3839900375
Short name T970
Test name
Test status
Simulation time 27618160 ps
CPU time 1.29 seconds
Started Apr 28 01:04:54 PM PDT 24
Finished Apr 28 01:04:56 PM PDT 24
Peak memory 206408 kb
Host smart-494f6e20-bc82-4062-aa08-b310f40a03ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839900375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3839900375
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3526935559
Short name T918
Test name
Test status
Simulation time 59627279 ps
CPU time 2.52 seconds
Started Apr 28 01:04:57 PM PDT 24
Finished Apr 28 01:05:00 PM PDT 24
Peak memory 222616 kb
Host smart-16f2a1ee-81bb-4983-95df-b3c37d19228d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526935559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3526935559
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3311524833
Short name T938
Test name
Test status
Simulation time 94312281 ps
CPU time 2.56 seconds
Started Apr 28 01:04:56 PM PDT 24
Finished Apr 28 01:04:59 PM PDT 24
Peak memory 206312 kb
Host smart-b20e8598-6bd1-417f-9132-36c1d93ae23d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311524833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3311524833
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.737778615
Short name T872
Test name
Test status
Simulation time 31811471 ps
CPU time 1.06 seconds
Started Apr 28 01:04:55 PM PDT 24
Finished Apr 28 01:04:57 PM PDT 24
Peak memory 216252 kb
Host smart-cdb75fae-8675-465b-ac36-6022a35561e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737778615 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.737778615
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1371481600
Short name T976
Test name
Test status
Simulation time 24336301 ps
CPU time 0.85 seconds
Started Apr 28 01:04:55 PM PDT 24
Finished Apr 28 01:04:56 PM PDT 24
Peak memory 206352 kb
Host smart-37fa5576-f86d-4d09-a77a-1fc4082bfab1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371481600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1371481600
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.311953489
Short name T854
Test name
Test status
Simulation time 44517388 ps
CPU time 0.86 seconds
Started Apr 28 01:04:54 PM PDT 24
Finished Apr 28 01:04:55 PM PDT 24
Peak memory 206200 kb
Host smart-5b38e9fc-6aa7-4a07-b3d5-561a0477cf47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311953489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.311953489
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1592380258
Short name T897
Test name
Test status
Simulation time 37658642 ps
CPU time 1.07 seconds
Started Apr 28 01:04:54 PM PDT 24
Finished Apr 28 01:04:55 PM PDT 24
Peak memory 206332 kb
Host smart-327fcdd8-cb20-4e98-9dc3-46436e373415
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592380258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.1592380258
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3231089178
Short name T847
Test name
Test status
Simulation time 391777609 ps
CPU time 2.44 seconds
Started Apr 28 01:04:55 PM PDT 24
Finished Apr 28 01:04:58 PM PDT 24
Peak memory 214504 kb
Host smart-ee16f15e-2d18-4324-8665-bf0f6a90ca46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231089178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3231089178
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.985295204
Short name T248
Test name
Test status
Simulation time 63243253 ps
CPU time 1.47 seconds
Started Apr 28 01:04:55 PM PDT 24
Finished Apr 28 01:04:57 PM PDT 24
Peak memory 206288 kb
Host smart-08ad81d1-bca6-4931-aab7-6e9fc22ea4b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985295204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.985295204
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.904167336
Short name T903
Test name
Test status
Simulation time 151449387 ps
CPU time 1.15 seconds
Started Apr 28 01:04:58 PM PDT 24
Finished Apr 28 01:05:01 PM PDT 24
Peak memory 214624 kb
Host smart-d1134c21-2fb8-4337-8447-15416087632b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904167336 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.904167336
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3031685872
Short name T914
Test name
Test status
Simulation time 44019559 ps
CPU time 0.83 seconds
Started Apr 28 01:04:58 PM PDT 24
Finished Apr 28 01:05:00 PM PDT 24
Peak memory 206172 kb
Host smart-8a1aeba4-5f15-48e2-8cc3-8006febfd2dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031685872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3031685872
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3564781259
Short name T878
Test name
Test status
Simulation time 26293346 ps
CPU time 0.9 seconds
Started Apr 28 01:04:58 PM PDT 24
Finished Apr 28 01:05:00 PM PDT 24
Peak memory 206132 kb
Host smart-5370a878-4368-4a23-963f-e2d902dca9c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564781259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3564781259
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3633481267
Short name T966
Test name
Test status
Simulation time 43955608 ps
CPU time 1.08 seconds
Started Apr 28 01:04:58 PM PDT 24
Finished Apr 28 01:05:01 PM PDT 24
Peak memory 206364 kb
Host smart-ae8d1618-5311-4bdb-bf2b-c92a63206382
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633481267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3633481267
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3058755587
Short name T908
Test name
Test status
Simulation time 215900756 ps
CPU time 2.28 seconds
Started Apr 28 01:04:53 PM PDT 24
Finished Apr 28 01:04:56 PM PDT 24
Peak memory 222744 kb
Host smart-cd56e421-ae51-4c4f-b66a-766c55cf5592
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058755587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3058755587
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2414441339
Short name T875
Test name
Test status
Simulation time 136630224 ps
CPU time 1.99 seconds
Started Apr 28 01:05:02 PM PDT 24
Finished Apr 28 01:05:06 PM PDT 24
Peak memory 214540 kb
Host smart-b82fee2e-00d3-4aa4-8cf8-43b79ac0f979
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414441339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2414441339
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2183408020
Short name T940
Test name
Test status
Simulation time 19670746 ps
CPU time 1.07 seconds
Started Apr 28 01:04:58 PM PDT 24
Finished Apr 28 01:05:01 PM PDT 24
Peak memory 222776 kb
Host smart-5cc9a612-c3df-45fc-9953-b7bc04eade9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183408020 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2183408020
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1170715440
Short name T225
Test name
Test status
Simulation time 21306115 ps
CPU time 0.85 seconds
Started Apr 28 01:04:59 PM PDT 24
Finished Apr 28 01:05:02 PM PDT 24
Peak memory 206296 kb
Host smart-8061a0be-8176-4e14-9eba-18e0f1d2b041
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170715440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1170715440
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3246399126
Short name T845
Test name
Test status
Simulation time 29398672 ps
CPU time 0.8 seconds
Started Apr 28 01:05:03 PM PDT 24
Finished Apr 28 01:05:05 PM PDT 24
Peak memory 205980 kb
Host smart-0b7eef0a-9e37-47bc-a3c6-8f194c45f851
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246399126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3246399126
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1185794188
Short name T913
Test name
Test status
Simulation time 333390022 ps
CPU time 1.44 seconds
Started Apr 28 01:04:59 PM PDT 24
Finished Apr 28 01:05:03 PM PDT 24
Peak memory 206308 kb
Host smart-1cd4c1cc-f2a5-4926-81cc-46cac7c63dec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185794188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1185794188
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.972773116
Short name T925
Test name
Test status
Simulation time 86188959 ps
CPU time 1.4 seconds
Started Apr 28 01:04:58 PM PDT 24
Finished Apr 28 01:05:01 PM PDT 24
Peak memory 214620 kb
Host smart-ff5a677d-96a0-4e3d-8996-4e51d0655b0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972773116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.972773116
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4195364119
Short name T882
Test name
Test status
Simulation time 17803697 ps
CPU time 1.05 seconds
Started Apr 28 01:04:59 PM PDT 24
Finished Apr 28 01:05:02 PM PDT 24
Peak memory 215680 kb
Host smart-9d184eed-934e-4bd7-ab16-93181c19b830
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195364119 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.4195364119
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.4211548945
Short name T221
Test name
Test status
Simulation time 32217416 ps
CPU time 0.85 seconds
Started Apr 28 01:05:05 PM PDT 24
Finished Apr 28 01:05:08 PM PDT 24
Peak memory 206060 kb
Host smart-611e4c2b-c1a9-4d05-803a-08d69dd5c034
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211548945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.4211548945
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.4156819781
Short name T876
Test name
Test status
Simulation time 21743461 ps
CPU time 0.83 seconds
Started Apr 28 01:04:59 PM PDT 24
Finished Apr 28 01:05:01 PM PDT 24
Peak memory 206088 kb
Host smart-48bb63e2-ac82-441a-afd3-bc40aa1b52e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156819781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.4156819781
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3996999482
Short name T236
Test name
Test status
Simulation time 16814682 ps
CPU time 1.12 seconds
Started Apr 28 01:05:01 PM PDT 24
Finished Apr 28 01:05:03 PM PDT 24
Peak memory 206440 kb
Host smart-38247e4d-2576-48aa-8bf5-f0b9a41c554e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996999482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3996999482
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.460303794
Short name T904
Test name
Test status
Simulation time 74136051 ps
CPU time 2.66 seconds
Started Apr 28 01:05:02 PM PDT 24
Finished Apr 28 01:05:07 PM PDT 24
Peak memory 222636 kb
Host smart-d6e81682-54fb-4d8c-9282-e252013b1d01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460303794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.460303794
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2598655405
Short name T926
Test name
Test status
Simulation time 54388693 ps
CPU time 1.67 seconds
Started Apr 28 01:05:05 PM PDT 24
Finished Apr 28 01:05:09 PM PDT 24
Peak memory 206296 kb
Host smart-380f1f20-7fe9-481e-b3b4-449b74d3b3c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598655405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2598655405
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1048095738
Short name T919
Test name
Test status
Simulation time 32140478 ps
CPU time 1.02 seconds
Started Apr 28 01:05:00 PM PDT 24
Finished Apr 28 01:05:03 PM PDT 24
Peak memory 206212 kb
Host smart-09a0f244-cbd3-45ed-a77f-2847f53642d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048095738 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1048095738
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1864380874
Short name T968
Test name
Test status
Simulation time 16415854 ps
CPU time 0.99 seconds
Started Apr 28 01:04:59 PM PDT 24
Finished Apr 28 01:05:02 PM PDT 24
Peak memory 206168 kb
Host smart-5e44af71-8e46-4028-8c0a-09275fff1740
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864380874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1864380874
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3538627164
Short name T955
Test name
Test status
Simulation time 82487883 ps
CPU time 0.85 seconds
Started Apr 28 01:04:57 PM PDT 24
Finished Apr 28 01:04:58 PM PDT 24
Peak memory 206268 kb
Host smart-e4085182-e3d3-4f45-90f5-4cca57c20ef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538627164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3538627164
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.750001821
Short name T220
Test name
Test status
Simulation time 15181583 ps
CPU time 1.12 seconds
Started Apr 28 01:05:02 PM PDT 24
Finished Apr 28 01:05:05 PM PDT 24
Peak memory 206316 kb
Host smart-ffc69321-90b0-4423-9e53-80998f9a84da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750001821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.750001821
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1239075343
Short name T907
Test name
Test status
Simulation time 150079706 ps
CPU time 2.64 seconds
Started Apr 28 01:04:57 PM PDT 24
Finished Apr 28 01:05:00 PM PDT 24
Peak memory 214460 kb
Host smart-e4e2f391-b4f6-4e5b-a3a3-c4becb1df1de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239075343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1239075343
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.428355628
Short name T247
Test name
Test status
Simulation time 55532782 ps
CPU time 1.78 seconds
Started Apr 28 01:04:59 PM PDT 24
Finished Apr 28 01:05:03 PM PDT 24
Peak memory 206352 kb
Host smart-82eda44a-0352-47d6-92fc-4e6af4109b05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428355628 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.428355628
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3825571571
Short name T957
Test name
Test status
Simulation time 31529678 ps
CPU time 1.2 seconds
Started Apr 28 01:04:59 PM PDT 24
Finished Apr 28 01:05:03 PM PDT 24
Peak memory 214516 kb
Host smart-e34f3c03-1955-4d12-8475-4c491e803a87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825571571 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3825571571
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.92945000
Short name T229
Test name
Test status
Simulation time 17582931 ps
CPU time 0.89 seconds
Started Apr 28 01:04:58 PM PDT 24
Finished Apr 28 01:05:00 PM PDT 24
Peak memory 206200 kb
Host smart-d8e385ce-6356-4cb6-bf87-57201ae807d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92945000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.92945000
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.780782782
Short name T863
Test name
Test status
Simulation time 48559953 ps
CPU time 0.87 seconds
Started Apr 28 01:04:59 PM PDT 24
Finished Apr 28 01:05:02 PM PDT 24
Peak memory 206172 kb
Host smart-8ffa07f1-967f-419c-9e3c-fd008ef732ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780782782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.780782782
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2134562851
Short name T956
Test name
Test status
Simulation time 15944319 ps
CPU time 1.01 seconds
Started Apr 28 01:05:05 PM PDT 24
Finished Apr 28 01:05:08 PM PDT 24
Peak memory 206272 kb
Host smart-2334549e-656b-40ec-a871-5633425709ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134562851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2134562851
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1141876255
Short name T947
Test name
Test status
Simulation time 40871840 ps
CPU time 2.73 seconds
Started Apr 28 01:05:01 PM PDT 24
Finished Apr 28 01:05:06 PM PDT 24
Peak memory 214496 kb
Host smart-f7ad404c-0c25-44f3-826e-39d6128d90af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141876255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1141876255
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1147358694
Short name T251
Test name
Test status
Simulation time 226236447 ps
CPU time 1.58 seconds
Started Apr 28 01:04:59 PM PDT 24
Finished Apr 28 01:05:02 PM PDT 24
Peak memory 206312 kb
Host smart-ffa94259-726e-4a8c-9c8c-fa492dd7206f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147358694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1147358694
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.4159189877
Short name T877
Test name
Test status
Simulation time 452396313 ps
CPU time 1.46 seconds
Started Apr 28 01:04:58 PM PDT 24
Finished Apr 28 01:05:00 PM PDT 24
Peak memory 217220 kb
Host smart-669fe3b4-e796-4f30-8152-cb67bb2e07a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159189877 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.4159189877
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.57240203
Short name T231
Test name
Test status
Simulation time 169321278 ps
CPU time 0.9 seconds
Started Apr 28 01:04:59 PM PDT 24
Finished Apr 28 01:05:02 PM PDT 24
Peak memory 206344 kb
Host smart-8f487357-28eb-42fa-99ab-1f39bcceaf93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57240203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.57240203
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2157073849
Short name T853
Test name
Test status
Simulation time 48957248 ps
CPU time 0.85 seconds
Started Apr 28 01:05:01 PM PDT 24
Finished Apr 28 01:05:04 PM PDT 24
Peak memory 206184 kb
Host smart-1be4407b-299c-439e-a774-c55c1f2c5a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157073849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2157073849
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.911261781
Short name T895
Test name
Test status
Simulation time 30933600 ps
CPU time 1.31 seconds
Started Apr 28 01:04:58 PM PDT 24
Finished Apr 28 01:05:01 PM PDT 24
Peak memory 206360 kb
Host smart-974fa2b4-e9ed-469d-bc01-32335b10449e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911261781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.911261781
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1521148444
Short name T889
Test name
Test status
Simulation time 122161821 ps
CPU time 3.85 seconds
Started Apr 28 01:04:59 PM PDT 24
Finished Apr 28 01:05:05 PM PDT 24
Peak memory 214440 kb
Host smart-07a85982-4d23-4d2c-9dc8-b5e4301aedc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521148444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1521148444
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.913085351
Short name T252
Test name
Test status
Simulation time 337216984 ps
CPU time 1.64 seconds
Started Apr 28 01:05:00 PM PDT 24
Finished Apr 28 01:05:03 PM PDT 24
Peak memory 206540 kb
Host smart-055e2def-92ae-44bd-8cb8-170cc55e8a48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913085351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.913085351
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3016840913
Short name T226
Test name
Test status
Simulation time 35832330 ps
CPU time 1.19 seconds
Started Apr 28 01:04:42 PM PDT 24
Finished Apr 28 01:04:44 PM PDT 24
Peak memory 206348 kb
Host smart-d6a48f7e-6c77-401a-adbd-142c27553d83
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016840913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3016840913
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3309337779
Short name T977
Test name
Test status
Simulation time 542958406 ps
CPU time 3.64 seconds
Started Apr 28 01:04:42 PM PDT 24
Finished Apr 28 01:04:47 PM PDT 24
Peak memory 206272 kb
Host smart-97e987d2-8b1e-4a95-8e0a-9719cbc5ef5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309337779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3309337779
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3947637403
Short name T223
Test name
Test status
Simulation time 22918895 ps
CPU time 1.01 seconds
Started Apr 28 01:04:42 PM PDT 24
Finished Apr 28 01:04:44 PM PDT 24
Peak memory 206176 kb
Host smart-c0928102-63ed-48c1-8168-4ca683941690
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947637403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3947637403
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1816022686
Short name T916
Test name
Test status
Simulation time 19544909 ps
CPU time 1.02 seconds
Started Apr 28 01:04:44 PM PDT 24
Finished Apr 28 01:04:46 PM PDT 24
Peak memory 206392 kb
Host smart-ade393dc-df8b-4df6-b54c-45a14b1b7a0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816022686 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1816022686
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2800810202
Short name T942
Test name
Test status
Simulation time 10967199 ps
CPU time 0.82 seconds
Started Apr 28 01:04:43 PM PDT 24
Finished Apr 28 01:04:44 PM PDT 24
Peak memory 206096 kb
Host smart-602d3689-9cd4-4b9e-8aed-fe6467bcf761
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800810202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2800810202
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3617117027
Short name T858
Test name
Test status
Simulation time 23403203 ps
CPU time 0.84 seconds
Started Apr 28 01:04:42 PM PDT 24
Finished Apr 28 01:04:44 PM PDT 24
Peak memory 206092 kb
Host smart-e8fe5338-9320-440a-9262-5cdcd6ceecea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617117027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3617117027
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3077615671
Short name T934
Test name
Test status
Simulation time 13500383 ps
CPU time 0.97 seconds
Started Apr 28 01:04:45 PM PDT 24
Finished Apr 28 01:04:46 PM PDT 24
Peak memory 206396 kb
Host smart-13e4c538-a0e1-4ef8-9233-fd3cc36cf6c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077615671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3077615671
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1275511103
Short name T965
Test name
Test status
Simulation time 204439952 ps
CPU time 2.34 seconds
Started Apr 28 01:04:37 PM PDT 24
Finished Apr 28 01:04:40 PM PDT 24
Peak memory 214396 kb
Host smart-06db3246-1c5d-44da-b37d-41fbfd7917ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275511103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1275511103
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3806315394
Short name T874
Test name
Test status
Simulation time 167710984 ps
CPU time 1.55 seconds
Started Apr 28 01:04:44 PM PDT 24
Finished Apr 28 01:04:46 PM PDT 24
Peak memory 206172 kb
Host smart-fc669d6f-d9f2-43af-be30-d3e252d6986b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806315394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3806315394
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.4290650477
Short name T852
Test name
Test status
Simulation time 15622363 ps
CPU time 0.89 seconds
Started Apr 28 01:04:58 PM PDT 24
Finished Apr 28 01:05:01 PM PDT 24
Peak memory 206192 kb
Host smart-25e6aff1-a31e-4a5c-a838-888b949ed034
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290650477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.4290650477
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3821720594
Short name T902
Test name
Test status
Simulation time 23166202 ps
CPU time 0.92 seconds
Started Apr 28 01:04:59 PM PDT 24
Finished Apr 28 01:05:02 PM PDT 24
Peak memory 206200 kb
Host smart-b6f53fda-2214-49e7-ab30-debf5eaed712
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821720594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3821720594
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3402655105
Short name T932
Test name
Test status
Simulation time 22050053 ps
CPU time 0.83 seconds
Started Apr 28 01:05:01 PM PDT 24
Finished Apr 28 01:05:04 PM PDT 24
Peak memory 206164 kb
Host smart-a00052bd-af33-4de4-a657-cf62e0fd3d48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402655105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3402655105
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2001467399
Short name T915
Test name
Test status
Simulation time 78302855 ps
CPU time 0.87 seconds
Started Apr 28 01:05:04 PM PDT 24
Finished Apr 28 01:05:07 PM PDT 24
Peak memory 206228 kb
Host smart-98cf22ce-b3f3-4a24-855e-ec8d3b6de7b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001467399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2001467399
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.816185423
Short name T954
Test name
Test status
Simulation time 41986130 ps
CPU time 0.84 seconds
Started Apr 28 01:05:04 PM PDT 24
Finished Apr 28 01:05:07 PM PDT 24
Peak memory 206160 kb
Host smart-5168c50c-00f5-401a-8e2a-db2bbe5e405a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816185423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.816185423
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3746480088
Short name T888
Test name
Test status
Simulation time 31603003 ps
CPU time 0.98 seconds
Started Apr 28 01:05:03 PM PDT 24
Finished Apr 28 01:05:06 PM PDT 24
Peak memory 206176 kb
Host smart-2fc30209-ec74-4462-8932-0c71535b4f76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746480088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3746480088
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2331958354
Short name T896
Test name
Test status
Simulation time 30494072 ps
CPU time 0.89 seconds
Started Apr 28 01:05:04 PM PDT 24
Finished Apr 28 01:05:07 PM PDT 24
Peak memory 206184 kb
Host smart-58b8deb3-dbb9-4a6d-864c-307435c84516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331958354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2331958354
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2866070421
Short name T879
Test name
Test status
Simulation time 27437306 ps
CPU time 0.89 seconds
Started Apr 28 01:05:03 PM PDT 24
Finished Apr 28 01:05:06 PM PDT 24
Peak memory 206232 kb
Host smart-0f336fbc-c413-45f1-b7d6-04a2f6994dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866070421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2866070421
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3199618341
Short name T859
Test name
Test status
Simulation time 19182738 ps
CPU time 0.78 seconds
Started Apr 28 01:05:02 PM PDT 24
Finished Apr 28 01:05:04 PM PDT 24
Peak memory 206008 kb
Host smart-52c10b2e-fb8b-4f9d-949d-e4b7d6d43f48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199618341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3199618341
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.411785566
Short name T856
Test name
Test status
Simulation time 11122155 ps
CPU time 0.82 seconds
Started Apr 28 01:05:02 PM PDT 24
Finished Apr 28 01:05:05 PM PDT 24
Peak memory 206216 kb
Host smart-61abacdf-be05-49e6-9c63-a8b41d2cbec5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411785566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.411785566
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2900818707
Short name T200
Test name
Test status
Simulation time 86587880 ps
CPU time 1.14 seconds
Started Apr 28 01:04:43 PM PDT 24
Finished Apr 28 01:04:44 PM PDT 24
Peak memory 206340 kb
Host smart-66dce449-082a-485b-af38-157caa193866
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900818707 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2900818707
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1162370910
Short name T864
Test name
Test status
Simulation time 35486264 ps
CPU time 2.02 seconds
Started Apr 28 01:04:42 PM PDT 24
Finished Apr 28 01:04:45 PM PDT 24
Peak memory 206348 kb
Host smart-58a49713-10f0-44d0-b0d1-85dcd13b24ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162370910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1162370910
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1067739853
Short name T886
Test name
Test status
Simulation time 14530411 ps
CPU time 0.9 seconds
Started Apr 28 01:04:41 PM PDT 24
Finished Apr 28 01:04:43 PM PDT 24
Peak memory 206180 kb
Host smart-77162f00-d255-443c-ba94-155249afbace
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067739853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1067739853
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3144564401
Short name T906
Test name
Test status
Simulation time 109024445 ps
CPU time 2.01 seconds
Started Apr 28 01:04:41 PM PDT 24
Finished Apr 28 01:04:44 PM PDT 24
Peak memory 214688 kb
Host smart-44b90ccd-19f5-4feb-8e02-5f4da15fbba9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144564401 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3144564401
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3157594579
Short name T945
Test name
Test status
Simulation time 19312640 ps
CPU time 0.85 seconds
Started Apr 28 01:04:44 PM PDT 24
Finished Apr 28 01:04:46 PM PDT 24
Peak memory 206204 kb
Host smart-e1822914-d09c-4f94-a0d8-2c500f7a3b66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157594579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3157594579
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.11944702
Short name T931
Test name
Test status
Simulation time 14495179 ps
CPU time 0.85 seconds
Started Apr 28 01:04:43 PM PDT 24
Finished Apr 28 01:04:44 PM PDT 24
Peak memory 206204 kb
Host smart-fac6896e-13e3-4f97-a045-0bf5c5ac59bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11944702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.11944702
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1972726252
Short name T233
Test name
Test status
Simulation time 21797142 ps
CPU time 1.11 seconds
Started Apr 28 01:04:42 PM PDT 24
Finished Apr 28 01:04:43 PM PDT 24
Peak memory 206220 kb
Host smart-a62a7894-a925-4a2b-9aec-7d2b5faa9182
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972726252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1972726252
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1286938309
Short name T941
Test name
Test status
Simulation time 39267967 ps
CPU time 2.47 seconds
Started Apr 28 01:04:42 PM PDT 24
Finished Apr 28 01:04:45 PM PDT 24
Peak memory 214624 kb
Host smart-c0028c03-4449-46fa-9b3b-7ba9c9f0979e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286938309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1286938309
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1723671360
Short name T249
Test name
Test status
Simulation time 72651748 ps
CPU time 1.48 seconds
Started Apr 28 01:04:46 PM PDT 24
Finished Apr 28 01:04:48 PM PDT 24
Peak memory 206352 kb
Host smart-70938f77-c55c-4347-951d-9f6fcf39a7a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723671360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1723671360
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1218830662
Short name T855
Test name
Test status
Simulation time 12744890 ps
CPU time 0.86 seconds
Started Apr 28 01:05:03 PM PDT 24
Finished Apr 28 01:05:06 PM PDT 24
Peak memory 206220 kb
Host smart-b3bfb8e9-d35c-4f5a-abe5-2f950d08779b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218830662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1218830662
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.4060129307
Short name T893
Test name
Test status
Simulation time 43271784 ps
CPU time 0.87 seconds
Started Apr 28 01:05:05 PM PDT 24
Finished Apr 28 01:05:08 PM PDT 24
Peak memory 206200 kb
Host smart-dd3dd979-2dfe-411e-91f8-84089b463494
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060129307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.4060129307
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.669104089
Short name T892
Test name
Test status
Simulation time 128565347 ps
CPU time 0.76 seconds
Started Apr 28 01:05:02 PM PDT 24
Finished Apr 28 01:05:05 PM PDT 24
Peak memory 206016 kb
Host smart-51cf04e1-e26a-4605-b6b9-ebb4cf9f14bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669104089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.669104089
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3406660499
Short name T950
Test name
Test status
Simulation time 33226693 ps
CPU time 0.79 seconds
Started Apr 28 01:05:04 PM PDT 24
Finished Apr 28 01:05:07 PM PDT 24
Peak memory 206016 kb
Host smart-74cf6f75-1013-4abb-acf0-3264d041ddc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406660499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3406660499
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3360851928
Short name T871
Test name
Test status
Simulation time 23304066 ps
CPU time 0.8 seconds
Started Apr 28 01:05:03 PM PDT 24
Finished Apr 28 01:05:06 PM PDT 24
Peak memory 205980 kb
Host smart-b57b1335-f5d4-4537-9b3d-197fb3af3ca3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360851928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3360851928
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.319682966
Short name T890
Test name
Test status
Simulation time 13722538 ps
CPU time 0.9 seconds
Started Apr 28 01:05:04 PM PDT 24
Finished Apr 28 01:05:07 PM PDT 24
Peak memory 206108 kb
Host smart-ec592436-dcb5-4f6a-a6f8-3600bc0838f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319682966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.319682966
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2106320962
Short name T949
Test name
Test status
Simulation time 11128469 ps
CPU time 0.82 seconds
Started Apr 28 01:05:04 PM PDT 24
Finished Apr 28 01:05:07 PM PDT 24
Peak memory 206148 kb
Host smart-bf0e79bc-2a69-4b0b-9e12-050dd91b978d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106320962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2106320962
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2342384145
Short name T917
Test name
Test status
Simulation time 47002042 ps
CPU time 0.81 seconds
Started Apr 28 01:05:02 PM PDT 24
Finished Apr 28 01:05:05 PM PDT 24
Peak memory 206132 kb
Host smart-d28da31d-251a-47eb-b212-2eeda362b350
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342384145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2342384145
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.4263059885
Short name T881
Test name
Test status
Simulation time 86632882 ps
CPU time 0.89 seconds
Started Apr 28 01:05:02 PM PDT 24
Finished Apr 28 01:05:05 PM PDT 24
Peak memory 206084 kb
Host smart-1e7b3495-64b4-41de-9ca4-381fb7106bf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263059885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.4263059885
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1319387226
Short name T850
Test name
Test status
Simulation time 15336385 ps
CPU time 0.88 seconds
Started Apr 28 01:05:01 PM PDT 24
Finished Apr 28 01:05:04 PM PDT 24
Peak memory 206108 kb
Host smart-3d490731-1079-437e-989e-0fa8eb80a030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319387226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1319387226
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.890281218
Short name T870
Test name
Test status
Simulation time 253447948 ps
CPU time 6.29 seconds
Started Apr 28 01:04:44 PM PDT 24
Finished Apr 28 01:04:51 PM PDT 24
Peak memory 206348 kb
Host smart-8aca7aec-5c9e-4795-b98d-723990c7f65e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890281218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.890281218
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3835570246
Short name T958
Test name
Test status
Simulation time 17443430 ps
CPU time 0.97 seconds
Started Apr 28 01:04:43 PM PDT 24
Finished Apr 28 01:04:44 PM PDT 24
Peak memory 206304 kb
Host smart-c22666b8-3120-4ce2-ad30-defdf8c66983
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835570246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3835570246
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1968893237
Short name T862
Test name
Test status
Simulation time 49423708 ps
CPU time 0.93 seconds
Started Apr 28 01:04:44 PM PDT 24
Finished Apr 28 01:04:46 PM PDT 24
Peak memory 206292 kb
Host smart-354312d3-852e-4d27-9fe1-fd8130700988
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968893237 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1968893237
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.79962586
Short name T230
Test name
Test status
Simulation time 14795717 ps
CPU time 0.98 seconds
Started Apr 28 01:04:45 PM PDT 24
Finished Apr 28 01:04:47 PM PDT 24
Peak memory 206324 kb
Host smart-ea772dd3-6937-4313-9abb-6672bf080d34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79962586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.79962586
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.127422585
Short name T866
Test name
Test status
Simulation time 45031274 ps
CPU time 0.84 seconds
Started Apr 28 01:04:44 PM PDT 24
Finished Apr 28 01:04:45 PM PDT 24
Peak memory 206016 kb
Host smart-c9e5a954-035e-4f80-82b2-f271a11b32e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127422585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.127422585
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1629652907
Short name T960
Test name
Test status
Simulation time 32534756 ps
CPU time 1.25 seconds
Started Apr 28 01:04:45 PM PDT 24
Finished Apr 28 01:04:47 PM PDT 24
Peak memory 206256 kb
Host smart-4b4f16d4-ed5c-4c80-826d-144f0767ed22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629652907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1629652907
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.11413090
Short name T867
Test name
Test status
Simulation time 81957785 ps
CPU time 2.78 seconds
Started Apr 28 01:04:45 PM PDT 24
Finished Apr 28 01:04:48 PM PDT 24
Peak memory 214516 kb
Host smart-59d73505-107c-4400-be24-18170d2bee6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11413090 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.11413090
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.4068794853
Short name T238
Test name
Test status
Simulation time 246082537 ps
CPU time 2.83 seconds
Started Apr 28 01:04:43 PM PDT 24
Finished Apr 28 01:04:46 PM PDT 24
Peak memory 206460 kb
Host smart-f9fb1104-c85e-4d54-9da4-1d147433d085
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068794853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.4068794853
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1111661956
Short name T851
Test name
Test status
Simulation time 14394067 ps
CPU time 0.92 seconds
Started Apr 28 01:05:02 PM PDT 24
Finished Apr 28 01:05:05 PM PDT 24
Peak memory 206044 kb
Host smart-878c1a22-6f0b-4dda-b470-fc63f31187b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111661956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1111661956
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.4237467687
Short name T846
Test name
Test status
Simulation time 198231892 ps
CPU time 0.84 seconds
Started Apr 28 01:05:03 PM PDT 24
Finished Apr 28 01:05:07 PM PDT 24
Peak memory 206024 kb
Host smart-cbe02175-6c10-45a4-a127-b8dde6a1c0ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237467687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.4237467687
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2483701655
Short name T927
Test name
Test status
Simulation time 16606774 ps
CPU time 0.93 seconds
Started Apr 28 01:05:05 PM PDT 24
Finished Apr 28 01:05:08 PM PDT 24
Peak memory 206088 kb
Host smart-ea5cca39-6a2a-4fae-93c4-6dbe3389fc7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483701655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2483701655
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.4117896849
Short name T953
Test name
Test status
Simulation time 29289079 ps
CPU time 0.95 seconds
Started Apr 28 01:05:01 PM PDT 24
Finished Apr 28 01:05:04 PM PDT 24
Peak memory 206176 kb
Host smart-924ff21d-14bd-484b-81aa-4d0b34529fce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117896849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.4117896849
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2076816763
Short name T848
Test name
Test status
Simulation time 18424027 ps
CPU time 0.96 seconds
Started Apr 28 01:05:04 PM PDT 24
Finished Apr 28 01:05:08 PM PDT 24
Peak memory 206148 kb
Host smart-00096d69-8b1b-4b1b-b598-30c9d76bbdf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076816763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2076816763
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1079997799
Short name T948
Test name
Test status
Simulation time 14788422 ps
CPU time 0.89 seconds
Started Apr 28 01:05:03 PM PDT 24
Finished Apr 28 01:05:06 PM PDT 24
Peak memory 206180 kb
Host smart-d5723935-e06b-400a-b41a-2bf4ff35cf78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079997799 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1079997799
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3009849986
Short name T952
Test name
Test status
Simulation time 47725967 ps
CPU time 0.87 seconds
Started Apr 28 01:05:03 PM PDT 24
Finished Apr 28 01:05:06 PM PDT 24
Peak memory 206132 kb
Host smart-cd6d4c71-f2ec-47cd-8075-1159b8fa6e53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009849986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3009849986
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1906881789
Short name T936
Test name
Test status
Simulation time 56039879 ps
CPU time 0.78 seconds
Started Apr 28 01:05:02 PM PDT 24
Finished Apr 28 01:05:04 PM PDT 24
Peak memory 205884 kb
Host smart-8297e165-3c7f-4490-82d4-df888b4fc416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906881789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1906881789
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.4206939693
Short name T928
Test name
Test status
Simulation time 11593499 ps
CPU time 0.84 seconds
Started Apr 28 01:05:06 PM PDT 24
Finished Apr 28 01:05:08 PM PDT 24
Peak memory 206136 kb
Host smart-d263d9ae-3031-4fdf-869a-4901b026e380
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206939693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.4206939693
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3801888572
Short name T883
Test name
Test status
Simulation time 35494012 ps
CPU time 0.8 seconds
Started Apr 28 01:05:08 PM PDT 24
Finished Apr 28 01:05:09 PM PDT 24
Peak memory 206088 kb
Host smart-2a624dda-bffe-4f89-a18d-70dcad05ec88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801888572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3801888572
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1492581165
Short name T900
Test name
Test status
Simulation time 32460141 ps
CPU time 1.38 seconds
Started Apr 28 01:04:49 PM PDT 24
Finished Apr 28 01:04:51 PM PDT 24
Peak memory 214592 kb
Host smart-48c0d154-f89f-42d8-adc4-5486a21b25fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492581165 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1492581165
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2943914469
Short name T237
Test name
Test status
Simulation time 46899325 ps
CPU time 0.86 seconds
Started Apr 28 01:04:48 PM PDT 24
Finished Apr 28 01:04:50 PM PDT 24
Peak memory 206316 kb
Host smart-1d9a3ea6-6d30-4800-a2ac-f97d7719a0a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943914469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2943914469
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1179797150
Short name T891
Test name
Test status
Simulation time 14553376 ps
CPU time 0.9 seconds
Started Apr 28 01:04:50 PM PDT 24
Finished Apr 28 01:04:52 PM PDT 24
Peak memory 206316 kb
Host smart-65d94342-7a4f-4f7b-9743-b4ce54276d8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179797150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1179797150
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3294439408
Short name T235
Test name
Test status
Simulation time 34540484 ps
CPU time 0.88 seconds
Started Apr 28 01:04:46 PM PDT 24
Finished Apr 28 01:04:48 PM PDT 24
Peak memory 206212 kb
Host smart-54aa6f7f-a74e-4f0b-af21-77cbaffa6fbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294439408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3294439408
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.644001141
Short name T865
Test name
Test status
Simulation time 59305349 ps
CPU time 2.31 seconds
Started Apr 28 01:04:45 PM PDT 24
Finished Apr 28 01:04:48 PM PDT 24
Peak memory 218096 kb
Host smart-7f834a5b-3d9d-42c7-a576-5f27c25f1b05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644001141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.644001141
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.4216923316
Short name T909
Test name
Test status
Simulation time 71943492 ps
CPU time 2.19 seconds
Started Apr 28 01:04:47 PM PDT 24
Finished Apr 28 01:04:49 PM PDT 24
Peak memory 214552 kb
Host smart-a41321e2-1448-423a-bea8-1006249d0f2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216923316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.4216923316
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3393990261
Short name T894
Test name
Test status
Simulation time 174808490 ps
CPU time 1.68 seconds
Started Apr 28 01:04:47 PM PDT 24
Finished Apr 28 01:04:50 PM PDT 24
Peak memory 214624 kb
Host smart-a5555edc-5204-4ff0-b7c7-7a514ad08010
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393990261 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3393990261
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2382744036
Short name T924
Test name
Test status
Simulation time 29962699 ps
CPU time 0.8 seconds
Started Apr 28 01:04:48 PM PDT 24
Finished Apr 28 01:04:49 PM PDT 24
Peak memory 206148 kb
Host smart-042c03fe-b3aa-4d6f-8e2f-e2c4aecc0526
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382744036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2382744036
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.869809122
Short name T869
Test name
Test status
Simulation time 116026485 ps
CPU time 0.8 seconds
Started Apr 28 01:04:49 PM PDT 24
Finished Apr 28 01:04:50 PM PDT 24
Peak memory 206020 kb
Host smart-553221a9-8976-4586-aa13-02788398bd7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869809122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.869809122
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3700297038
Short name T969
Test name
Test status
Simulation time 125169923 ps
CPU time 1.38 seconds
Started Apr 28 01:04:46 PM PDT 24
Finished Apr 28 01:04:48 PM PDT 24
Peak memory 206360 kb
Host smart-9df08c35-949b-41c9-a936-ef0210fec70c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700297038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3700297038
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.181813000
Short name T930
Test name
Test status
Simulation time 224492815 ps
CPU time 2.28 seconds
Started Apr 28 01:04:47 PM PDT 24
Finished Apr 28 01:04:50 PM PDT 24
Peak memory 214496 kb
Host smart-40affe1d-280e-427f-9442-8d89e67d713d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181813000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.181813000
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3886950404
Short name T884
Test name
Test status
Simulation time 47860057 ps
CPU time 1.58 seconds
Started Apr 28 01:04:49 PM PDT 24
Finished Apr 28 01:04:51 PM PDT 24
Peak memory 206420 kb
Host smart-b9516cca-1d6a-4319-a912-f120c83f9ed0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886950404 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3886950404
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2041603676
Short name T920
Test name
Test status
Simulation time 46128899 ps
CPU time 0.91 seconds
Started Apr 28 01:04:46 PM PDT 24
Finished Apr 28 01:04:47 PM PDT 24
Peak memory 206284 kb
Host smart-0d139ff2-1000-4af6-a4e6-a7c31d42bdaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041603676 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2041603676
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.282604465
Short name T234
Test name
Test status
Simulation time 64344699 ps
CPU time 0.91 seconds
Started Apr 28 01:04:46 PM PDT 24
Finished Apr 28 01:04:48 PM PDT 24
Peak memory 206336 kb
Host smart-abea976c-b0a2-4699-ab24-b45ba4ee886b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282604465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.282604465
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3847527176
Short name T935
Test name
Test status
Simulation time 18640918 ps
CPU time 0.85 seconds
Started Apr 28 01:04:48 PM PDT 24
Finished Apr 28 01:04:49 PM PDT 24
Peak memory 205932 kb
Host smart-9f41949f-6dad-4885-9c6a-017e47b60c2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847527176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3847527176
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.4261721676
Short name T929
Test name
Test status
Simulation time 27907123 ps
CPU time 1.27 seconds
Started Apr 28 01:04:51 PM PDT 24
Finished Apr 28 01:04:53 PM PDT 24
Peak memory 206440 kb
Host smart-eaf8c594-a890-4ac9-8412-65a3746dc930
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261721676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.4261721676
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3552911046
Short name T951
Test name
Test status
Simulation time 47228374 ps
CPU time 1.72 seconds
Started Apr 28 01:04:49 PM PDT 24
Finished Apr 28 01:04:51 PM PDT 24
Peak memory 222620 kb
Host smart-7c8ba666-b4e3-47d1-a03b-97440cf4c1ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552911046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3552911046
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1868467684
Short name T239
Test name
Test status
Simulation time 66678704 ps
CPU time 1.96 seconds
Started Apr 28 01:04:48 PM PDT 24
Finished Apr 28 01:04:51 PM PDT 24
Peak memory 214556 kb
Host smart-19336640-d5a9-4bae-bd17-cccef003bd9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868467684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1868467684
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.71611109
Short name T849
Test name
Test status
Simulation time 35886644 ps
CPU time 1.41 seconds
Started Apr 28 01:04:48 PM PDT 24
Finished Apr 28 01:04:50 PM PDT 24
Peak memory 214508 kb
Host smart-a1c7b698-ab11-4b30-bbe9-3051858e1643
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71611109 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.71611109
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2872762670
Short name T232
Test name
Test status
Simulation time 13027408 ps
CPU time 0.93 seconds
Started Apr 28 01:04:49 PM PDT 24
Finished Apr 28 01:04:50 PM PDT 24
Peak memory 206324 kb
Host smart-57f9f618-01da-4b0c-9702-5eacf925567e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872762670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2872762670
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1641380948
Short name T901
Test name
Test status
Simulation time 23889973 ps
CPU time 0.85 seconds
Started Apr 28 01:04:50 PM PDT 24
Finished Apr 28 01:04:51 PM PDT 24
Peak memory 206200 kb
Host smart-c01b26fd-9347-4a1d-ab30-4edc288599d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641380948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1641380948
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.462689204
Short name T937
Test name
Test status
Simulation time 27633010 ps
CPU time 0.94 seconds
Started Apr 28 01:04:50 PM PDT 24
Finished Apr 28 01:04:51 PM PDT 24
Peak memory 206348 kb
Host smart-96b088ea-6f2c-4dc4-9c7b-a81a343fd70e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462689204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_out
standing.462689204
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2546696180
Short name T880
Test name
Test status
Simulation time 286897902 ps
CPU time 1.55 seconds
Started Apr 28 01:04:48 PM PDT 24
Finished Apr 28 01:04:50 PM PDT 24
Peak memory 222696 kb
Host smart-63e4db3f-d1e5-4772-aa73-b2f238ac5c70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546696180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2546696180
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.581480300
Short name T857
Test name
Test status
Simulation time 331165869 ps
CPU time 2.3 seconds
Started Apr 28 01:04:47 PM PDT 24
Finished Apr 28 01:04:49 PM PDT 24
Peak memory 214584 kb
Host smart-31112ef5-88cb-4f1e-9fd2-aec420e1da0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581480300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.581480300
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1024951132
Short name T975
Test name
Test status
Simulation time 77584781 ps
CPU time 1.45 seconds
Started Apr 28 01:04:51 PM PDT 24
Finished Apr 28 01:04:53 PM PDT 24
Peak memory 218720 kb
Host smart-49e43d18-515f-46db-8c1e-e6ded39115de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024951132 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1024951132
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2847960573
Short name T933
Test name
Test status
Simulation time 17022231 ps
CPU time 1.02 seconds
Started Apr 28 01:04:55 PM PDT 24
Finished Apr 28 01:04:57 PM PDT 24
Peak memory 206300 kb
Host smart-0740dddc-1827-4c16-b2b9-a2f18cc2c814
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847960573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2847960573
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.652842863
Short name T921
Test name
Test status
Simulation time 155901116 ps
CPU time 0.93 seconds
Started Apr 28 01:04:57 PM PDT 24
Finished Apr 28 01:04:58 PM PDT 24
Peak memory 206172 kb
Host smart-e06efcef-3661-4046-92f5-e48fc22939a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652842863 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.652842863
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.335600258
Short name T218
Test name
Test status
Simulation time 112566730 ps
CPU time 1.27 seconds
Started Apr 28 01:04:54 PM PDT 24
Finished Apr 28 01:04:56 PM PDT 24
Peak memory 206276 kb
Host smart-ea25b2ef-1a02-42c4-b9e6-388e19f97042
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335600258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.335600258
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1727628956
Short name T899
Test name
Test status
Simulation time 526303250 ps
CPU time 4.59 seconds
Started Apr 28 01:04:49 PM PDT 24
Finished Apr 28 01:04:54 PM PDT 24
Peak memory 214476 kb
Host smart-01941577-5314-4290-a092-637396c9d295
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727628956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1727628956
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2292074610
Short name T961
Test name
Test status
Simulation time 67665341 ps
CPU time 1.42 seconds
Started Apr 28 01:04:57 PM PDT 24
Finished Apr 28 01:04:59 PM PDT 24
Peak memory 206196 kb
Host smart-63c7ab91-8a87-4626-9a1e-3d060cf1b720
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292074610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2292074610
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.2279887455
Short name T267
Test name
Test status
Simulation time 29531823 ps
CPU time 1.44 seconds
Started Apr 28 04:27:31 PM PDT 24
Finished Apr 28 04:27:32 PM PDT 24
Peak memory 215580 kb
Host smart-c2a99ef7-473f-4dc8-a99a-18ec6ccdb313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279887455 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2279887455
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2491790732
Short name T760
Test name
Test status
Simulation time 55666747 ps
CPU time 1 seconds
Started Apr 28 04:27:31 PM PDT 24
Finished Apr 28 04:27:32 PM PDT 24
Peak memory 206564 kb
Host smart-557d5f37-372a-4506-a12a-21de68763a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491790732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2491790732
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.513206999
Short name T798
Test name
Test status
Simulation time 35313609 ps
CPU time 0.91 seconds
Started Apr 28 04:27:31 PM PDT 24
Finished Apr 28 04:27:33 PM PDT 24
Peak memory 215284 kb
Host smart-19030c72-1b3f-4d97-8ec0-8dfacb51d3eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513206999 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.513206999
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.732465340
Short name T506
Test name
Test status
Simulation time 212285037 ps
CPU time 1.09 seconds
Started Apr 28 04:27:33 PM PDT 24
Finished Apr 28 04:27:35 PM PDT 24
Peak memory 219772 kb
Host smart-c4d2d6d2-bddb-4579-b573-810d1e501d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732465340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.732465340
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1969462351
Short name T460
Test name
Test status
Simulation time 76352528 ps
CPU time 1.15 seconds
Started Apr 28 04:27:32 PM PDT 24
Finished Apr 28 04:27:33 PM PDT 24
Peak memory 216920 kb
Host smart-b81015c2-0ebd-4d83-af91-22eb2d6f96ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969462351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1969462351
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.112182260
Short name T678
Test name
Test status
Simulation time 25923835 ps
CPU time 1.02 seconds
Started Apr 28 04:27:31 PM PDT 24
Finished Apr 28 04:27:32 PM PDT 24
Peak memory 215364 kb
Host smart-ba756632-04c6-4a4f-8188-dd322da32907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112182260 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.112182260
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.527378883
Short name T16
Test name
Test status
Simulation time 263506482 ps
CPU time 4.94 seconds
Started Apr 28 04:27:31 PM PDT 24
Finished Apr 28 04:27:36 PM PDT 24
Peak memory 235840 kb
Host smart-099faa7d-f767-4a1d-a0ae-05d52e76d430
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527378883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.527378883
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2726919283
Short name T377
Test name
Test status
Simulation time 15224653 ps
CPU time 1 seconds
Started Apr 28 04:27:29 PM PDT 24
Finished Apr 28 04:27:31 PM PDT 24
Peak memory 215216 kb
Host smart-b852a117-9834-43cf-a97e-032e90008cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726919283 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2726919283
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2291571915
Short name T383
Test name
Test status
Simulation time 287684621 ps
CPU time 3.57 seconds
Started Apr 28 04:27:32 PM PDT 24
Finished Apr 28 04:27:36 PM PDT 24
Peak memory 216812 kb
Host smart-4b4d72ee-13ca-43e3-8be1-ecd88638976f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291571915 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2291571915
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3316545431
Short name T393
Test name
Test status
Simulation time 253682714759 ps
CPU time 560.78 seconds
Started Apr 28 04:27:33 PM PDT 24
Finished Apr 28 04:36:54 PM PDT 24
Peak memory 220208 kb
Host smart-97329395-6701-4ac5-b077-f372caf01b59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316545431 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3316545431
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1100346845
Short name T186
Test name
Test status
Simulation time 32078368 ps
CPU time 1.24 seconds
Started Apr 28 04:27:36 PM PDT 24
Finished Apr 28 04:27:38 PM PDT 24
Peak memory 215520 kb
Host smart-b4cfc96f-e883-4f99-bbd5-70b9335b67c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100346845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1100346845
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.4138537699
Short name T611
Test name
Test status
Simulation time 22131726 ps
CPU time 0.9 seconds
Started Apr 28 04:27:40 PM PDT 24
Finished Apr 28 04:27:41 PM PDT 24
Peak memory 206488 kb
Host smart-70374181-40f8-4a1c-9d40-93a457fdeaf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138537699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.4138537699
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_err.667910261
Short name T654
Test name
Test status
Simulation time 26549390 ps
CPU time 1.08 seconds
Started Apr 28 04:27:35 PM PDT 24
Finished Apr 28 04:27:36 PM PDT 24
Peak memory 223736 kb
Host smart-d403538d-40c3-4d35-bb25-cdd44ea0c2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667910261 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.667910261
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.4127414435
Short name T213
Test name
Test status
Simulation time 32024153 ps
CPU time 1.55 seconds
Started Apr 28 04:27:35 PM PDT 24
Finished Apr 28 04:27:37 PM PDT 24
Peak memory 219620 kb
Host smart-4792643c-f08b-4127-a01a-606df7054418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127414435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.4127414435
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1409120389
Short name T345
Test name
Test status
Simulation time 25388439 ps
CPU time 1.02 seconds
Started Apr 28 04:27:36 PM PDT 24
Finished Apr 28 04:27:37 PM PDT 24
Peak memory 215408 kb
Host smart-d1117f07-abc6-4751-99ad-ae74d97f8e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409120389 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1409120389
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_smoke.3661260242
Short name T311
Test name
Test status
Simulation time 40108332 ps
CPU time 0.96 seconds
Started Apr 28 04:27:35 PM PDT 24
Finished Apr 28 04:27:36 PM PDT 24
Peak memory 215184 kb
Host smart-def76b02-1fd0-4cba-87d7-0aec0e46b96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661260242 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3661260242
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3644899206
Short name T442
Test name
Test status
Simulation time 237283304 ps
CPU time 3.25 seconds
Started Apr 28 04:27:36 PM PDT 24
Finished Apr 28 04:27:39 PM PDT 24
Peak memory 216776 kb
Host smart-5dceac32-84fe-4e36-bc86-db71f32efe94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644899206 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3644899206
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1764392658
Short name T190
Test name
Test status
Simulation time 19188648128 ps
CPU time 536.46 seconds
Started Apr 28 04:27:38 PM PDT 24
Finished Apr 28 04:36:35 PM PDT 24
Peak memory 218980 kb
Host smart-c19a5613-4d2a-44e4-a702-977e786a99d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764392658 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1764392658
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.710549174
Short name T719
Test name
Test status
Simulation time 38245276 ps
CPU time 1.31 seconds
Started Apr 28 04:28:11 PM PDT 24
Finished Apr 28 04:28:13 PM PDT 24
Peak memory 215556 kb
Host smart-226a1579-694d-49ec-957c-7c546f2bc12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710549174 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.710549174
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.3863055695
Short name T51
Test name
Test status
Simulation time 26084960 ps
CPU time 1.04 seconds
Started Apr 28 04:28:08 PM PDT 24
Finished Apr 28 04:28:10 PM PDT 24
Peak memory 206564 kb
Host smart-bfb5f6c9-f2b0-4c7d-9b9c-43322660bf72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863055695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3863055695
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3787506003
Short name T440
Test name
Test status
Simulation time 54779734 ps
CPU time 1.09 seconds
Started Apr 28 04:28:12 PM PDT 24
Finished Apr 28 04:28:13 PM PDT 24
Peak memory 216740 kb
Host smart-5ff7567b-179e-4282-9c7e-bcff479088d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787506003 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3787506003
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.807888713
Short name T405
Test name
Test status
Simulation time 18541140 ps
CPU time 1.05 seconds
Started Apr 28 04:28:09 PM PDT 24
Finished Apr 28 04:28:10 PM PDT 24
Peak memory 218376 kb
Host smart-bf9b099c-7f6b-4151-b16d-e5221c9c6539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807888713 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.807888713
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3822894889
Short name T488
Test name
Test status
Simulation time 55598838 ps
CPU time 1.41 seconds
Started Apr 28 04:28:09 PM PDT 24
Finished Apr 28 04:28:11 PM PDT 24
Peak memory 218196 kb
Host smart-4e49e330-bb84-43cb-ba2b-931ff5ba7173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822894889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3822894889
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.1981403920
Short name T776
Test name
Test status
Simulation time 49269850 ps
CPU time 0.94 seconds
Started Apr 28 04:28:06 PM PDT 24
Finished Apr 28 04:28:08 PM PDT 24
Peak memory 215152 kb
Host smart-0af6d7ad-ab21-4ce9-9887-c78e6d802478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981403920 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1981403920
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.764165845
Short name T446
Test name
Test status
Simulation time 34274131738 ps
CPU time 674.66 seconds
Started Apr 28 04:28:12 PM PDT 24
Finished Apr 28 04:39:27 PM PDT 24
Peak memory 217760 kb
Host smart-84e5bb99-5525-4fdd-9e43-e544c41c74b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764165845 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.764165845
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.1527817403
Short name T558
Test name
Test status
Simulation time 36641170 ps
CPU time 1.68 seconds
Started Apr 28 04:30:17 PM PDT 24
Finished Apr 28 04:30:19 PM PDT 24
Peak memory 218180 kb
Host smart-ad93a96f-859c-49a7-892d-6d367d3354b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527817403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1527817403
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.1602091195
Short name T706
Test name
Test status
Simulation time 109888001 ps
CPU time 1.75 seconds
Started Apr 28 04:30:19 PM PDT 24
Finished Apr 28 04:30:21 PM PDT 24
Peak memory 218468 kb
Host smart-19e02c80-4f75-4d4b-b014-b4808e002e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602091195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1602091195
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.1830513517
Short name T277
Test name
Test status
Simulation time 78829403 ps
CPU time 2.23 seconds
Started Apr 28 04:30:28 PM PDT 24
Finished Apr 28 04:30:31 PM PDT 24
Peak memory 219928 kb
Host smart-eec876aa-f89d-4e47-97df-89f8bfca209c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830513517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1830513517
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3211699866
Short name T685
Test name
Test status
Simulation time 56130975 ps
CPU time 1.29 seconds
Started Apr 28 04:30:21 PM PDT 24
Finished Apr 28 04:30:22 PM PDT 24
Peak memory 216980 kb
Host smart-65877faa-9eab-467e-a1f7-06f2edab2e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211699866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3211699866
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.2235481932
Short name T648
Test name
Test status
Simulation time 314403413 ps
CPU time 2.46 seconds
Started Apr 28 04:30:21 PM PDT 24
Finished Apr 28 04:30:24 PM PDT 24
Peak memory 218364 kb
Host smart-37d7e77e-0592-4ec7-b034-945deab6ca42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235481932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2235481932
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.2989458422
Short name T91
Test name
Test status
Simulation time 93084612 ps
CPU time 1.53 seconds
Started Apr 28 04:30:26 PM PDT 24
Finished Apr 28 04:30:29 PM PDT 24
Peak memory 219544 kb
Host smart-8ef78471-17a5-40a4-b25d-f26e43a2ee43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989458422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2989458422
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.3660934403
Short name T79
Test name
Test status
Simulation time 108373506 ps
CPU time 1.29 seconds
Started Apr 28 04:30:21 PM PDT 24
Finished Apr 28 04:30:22 PM PDT 24
Peak memory 218760 kb
Host smart-73c918a6-c28c-406a-9f6c-88cc84f7f562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660934403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3660934403
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.1949515127
Short name T647
Test name
Test status
Simulation time 43376625 ps
CPU time 1.85 seconds
Started Apr 28 04:30:22 PM PDT 24
Finished Apr 28 04:30:24 PM PDT 24
Peak memory 215256 kb
Host smart-843ec330-1a30-4752-9e04-7830442d4ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949515127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1949515127
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.1225840045
Short name T797
Test name
Test status
Simulation time 56708534 ps
CPU time 1.28 seconds
Started Apr 28 04:30:24 PM PDT 24
Finished Apr 28 04:30:25 PM PDT 24
Peak memory 215196 kb
Host smart-64d7c3ce-15e3-4f5b-90d1-e9a8a71b85aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225840045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1225840045
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.753422250
Short name T810
Test name
Test status
Simulation time 45166569 ps
CPU time 1.19 seconds
Started Apr 28 04:30:20 PM PDT 24
Finished Apr 28 04:30:22 PM PDT 24
Peak memory 216828 kb
Host smart-706d30f9-c20a-4962-83a1-c876ba2442a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753422250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.753422250
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.1837267285
Short name T69
Test name
Test status
Simulation time 19109962 ps
CPU time 1.08 seconds
Started Apr 28 04:28:14 PM PDT 24
Finished Apr 28 04:28:15 PM PDT 24
Peak memory 214760 kb
Host smart-dbd83827-2f22-48e2-add9-e37237acbae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837267285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1837267285
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_err.2395948317
Short name T464
Test name
Test status
Simulation time 21715005 ps
CPU time 1.02 seconds
Started Apr 28 04:28:12 PM PDT 24
Finished Apr 28 04:28:14 PM PDT 24
Peak memory 223916 kb
Host smart-b1fde700-3dda-45e2-98c4-61fd671bf13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395948317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2395948317
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1248567534
Short name T327
Test name
Test status
Simulation time 84572799 ps
CPU time 1.7 seconds
Started Apr 28 04:28:10 PM PDT 24
Finished Apr 28 04:28:12 PM PDT 24
Peak memory 217064 kb
Host smart-3fad0c6e-ad13-4d3e-a764-2f09066d90d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248567534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1248567534
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.412569479
Short name T491
Test name
Test status
Simulation time 30704988 ps
CPU time 1.07 seconds
Started Apr 28 04:28:10 PM PDT 24
Finished Apr 28 04:28:12 PM PDT 24
Peak memory 223672 kb
Host smart-7a2a7a70-50aa-46c5-892c-72f3c30a192a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412569479 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.412569479
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.260537884
Short name T742
Test name
Test status
Simulation time 47381497 ps
CPU time 0.95 seconds
Started Apr 28 04:28:09 PM PDT 24
Finished Apr 28 04:28:10 PM PDT 24
Peak memory 215160 kb
Host smart-67ae4903-5737-4ba3-bd87-b203d3e092d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260537884 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.260537884
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.3848131245
Short name T841
Test name
Test status
Simulation time 130365983 ps
CPU time 2.56 seconds
Started Apr 28 04:28:12 PM PDT 24
Finished Apr 28 04:28:15 PM PDT 24
Peak memory 216820 kb
Host smart-e26f089c-eea2-49c4-a62f-3b5d8c814c3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848131245 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3848131245
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.4108598659
Short name T198
Test name
Test status
Simulation time 28355198983 ps
CPU time 660.81 seconds
Started Apr 28 04:28:09 PM PDT 24
Finished Apr 28 04:39:10 PM PDT 24
Peak memory 223288 kb
Host smart-12c2a3cb-1738-4137-94b3-29bbcfa9e0b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108598659 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.4108598659
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.3758611200
Short name T691
Test name
Test status
Simulation time 16807532196 ps
CPU time 197.25 seconds
Started Apr 28 04:30:21 PM PDT 24
Finished Apr 28 04:33:39 PM PDT 24
Peak memory 220320 kb
Host smart-86338a11-b3b6-4cea-b2f5-d0181c03f9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758611200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3758611200
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.1460276275
Short name T66
Test name
Test status
Simulation time 74980447 ps
CPU time 1.14 seconds
Started Apr 28 04:30:22 PM PDT 24
Finished Apr 28 04:30:23 PM PDT 24
Peak memory 216964 kb
Host smart-2ae2fb83-a07e-4c06-ab7f-cf5e91956209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460276275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1460276275
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.3716322004
Short name T628
Test name
Test status
Simulation time 66841577 ps
CPU time 1.06 seconds
Started Apr 28 04:30:21 PM PDT 24
Finished Apr 28 04:30:23 PM PDT 24
Peak memory 216948 kb
Host smart-5518dab4-7663-4a2f-bd00-a770ed73788c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716322004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3716322004
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.228402305
Short name T624
Test name
Test status
Simulation time 181315809 ps
CPU time 2.06 seconds
Started Apr 28 04:30:20 PM PDT 24
Finished Apr 28 04:30:23 PM PDT 24
Peak memory 219352 kb
Host smart-526e25a9-47c2-4155-af2b-21a5b51ff604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228402305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.228402305
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.1544688522
Short name T730
Test name
Test status
Simulation time 70810474 ps
CPU time 1.27 seconds
Started Apr 28 04:30:23 PM PDT 24
Finished Apr 28 04:30:25 PM PDT 24
Peak memory 219872 kb
Host smart-076b6a8f-912a-429e-b4d2-ece9bf379504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544688522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1544688522
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.930316518
Short name T718
Test name
Test status
Simulation time 81499363 ps
CPU time 1.46 seconds
Started Apr 28 04:30:25 PM PDT 24
Finished Apr 28 04:30:27 PM PDT 24
Peak memory 218500 kb
Host smart-b9129567-3afc-4087-aace-664b1eafaf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930316518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.930316518
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.639062646
Short name T438
Test name
Test status
Simulation time 101575937 ps
CPU time 1.61 seconds
Started Apr 28 04:30:28 PM PDT 24
Finished Apr 28 04:30:30 PM PDT 24
Peak memory 219276 kb
Host smart-b1b61e1e-b6b3-49a5-a06f-dd8080110f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639062646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.639062646
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.599937810
Short name T153
Test name
Test status
Simulation time 27502398 ps
CPU time 1.26 seconds
Started Apr 28 04:28:12 PM PDT 24
Finished Apr 28 04:28:14 PM PDT 24
Peak memory 215536 kb
Host smart-a45d4282-0c8b-46fa-b3d5-c3058ded9950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599937810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.599937810
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2494322049
Short name T485
Test name
Test status
Simulation time 71829320 ps
CPU time 0.92 seconds
Started Apr 28 04:28:15 PM PDT 24
Finished Apr 28 04:28:16 PM PDT 24
Peak memory 206564 kb
Host smart-a9b0e702-30ad-46ff-af42-ec82b5b3d64e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494322049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2494322049
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2878215498
Short name T46
Test name
Test status
Simulation time 12273802 ps
CPU time 0.93 seconds
Started Apr 28 04:28:14 PM PDT 24
Finished Apr 28 04:28:15 PM PDT 24
Peak memory 215456 kb
Host smart-bbfed806-dc7d-484a-9f01-988e64b7c7d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878215498 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2878215498
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.2279575348
Short name T828
Test name
Test status
Simulation time 52106313 ps
CPU time 1.07 seconds
Started Apr 28 04:28:13 PM PDT 24
Finished Apr 28 04:28:15 PM PDT 24
Peak memory 219280 kb
Host smart-267b1625-79e8-48e5-980a-3ded25e57d48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279575348 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.2279575348
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.1550135206
Short name T107
Test name
Test status
Simulation time 32349963 ps
CPU time 1.14 seconds
Started Apr 28 04:28:13 PM PDT 24
Finished Apr 28 04:28:15 PM PDT 24
Peak memory 220500 kb
Host smart-d3dfc9f9-ff63-4130-ac0a-af1b4c6fe713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550135206 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1550135206
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3641136271
Short name T751
Test name
Test status
Simulation time 282956289 ps
CPU time 4.38 seconds
Started Apr 28 04:28:13 PM PDT 24
Finished Apr 28 04:28:18 PM PDT 24
Peak memory 219920 kb
Host smart-07891800-ba1e-4b1f-bd29-ab13ebd3c0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641136271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3641136271
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.246538539
Short name T690
Test name
Test status
Simulation time 22874034 ps
CPU time 1.19 seconds
Started Apr 28 04:28:13 PM PDT 24
Finished Apr 28 04:28:15 PM PDT 24
Peak memory 223972 kb
Host smart-b1852935-7c37-47c7-a1d1-68299edd2c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246538539 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.246538539
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.4245790234
Short name T507
Test name
Test status
Simulation time 30183796 ps
CPU time 1 seconds
Started Apr 28 04:28:15 PM PDT 24
Finished Apr 28 04:28:16 PM PDT 24
Peak memory 215216 kb
Host smart-946ec96e-0749-450b-9c3b-9132f96e85ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245790234 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.4245790234
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3229908735
Short name T555
Test name
Test status
Simulation time 792400680 ps
CPU time 4.84 seconds
Started Apr 28 04:28:16 PM PDT 24
Finished Apr 28 04:28:21 PM PDT 24
Peak memory 216756 kb
Host smart-598091b2-611a-4d43-8914-560fbb114d1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229908735 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3229908735
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3596534963
Short name T195
Test name
Test status
Simulation time 69008810084 ps
CPU time 1622.51 seconds
Started Apr 28 04:28:14 PM PDT 24
Finished Apr 28 04:55:17 PM PDT 24
Peak memory 223184 kb
Host smart-3386f5bf-d33e-4362-ba4c-254903d47646
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596534963 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3596534963
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.3025186321
Short name T338
Test name
Test status
Simulation time 43340827 ps
CPU time 1.57 seconds
Started Apr 28 04:30:28 PM PDT 24
Finished Apr 28 04:30:30 PM PDT 24
Peak memory 215192 kb
Host smart-eb22feb3-f170-42df-9c62-15b72baa7292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025186321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3025186321
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.3207874056
Short name T616
Test name
Test status
Simulation time 119346156 ps
CPU time 1.47 seconds
Started Apr 28 04:30:24 PM PDT 24
Finished Apr 28 04:30:26 PM PDT 24
Peak memory 216932 kb
Host smart-0533865c-8862-4c2b-8f56-273e8f4e19ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207874056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3207874056
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.782962494
Short name T708
Test name
Test status
Simulation time 32909334 ps
CPU time 1.41 seconds
Started Apr 28 04:30:25 PM PDT 24
Finished Apr 28 04:30:26 PM PDT 24
Peak memory 218132 kb
Host smart-1a2d02c4-786b-4f92-a6c0-b1309d336e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782962494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.782962494
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.1378042039
Short name T642
Test name
Test status
Simulation time 92671274 ps
CPU time 1.37 seconds
Started Apr 28 04:30:26 PM PDT 24
Finished Apr 28 04:30:28 PM PDT 24
Peak memory 218316 kb
Host smart-77377936-80ad-4786-b83f-6dd417b42bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378042039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1378042039
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.1683339611
Short name T582
Test name
Test status
Simulation time 30987073 ps
CPU time 1.29 seconds
Started Apr 28 04:30:24 PM PDT 24
Finished Apr 28 04:30:26 PM PDT 24
Peak memory 219524 kb
Host smart-8af6a7bc-ea15-407a-b585-4abe5350f64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683339611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1683339611
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2633813717
Short name T472
Test name
Test status
Simulation time 39166498 ps
CPU time 1.36 seconds
Started Apr 28 04:30:25 PM PDT 24
Finished Apr 28 04:30:27 PM PDT 24
Peak memory 218912 kb
Host smart-5afceb91-4350-48e3-bb36-5c80fd806350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633813717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2633813717
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3017417377
Short name T692
Test name
Test status
Simulation time 48617888 ps
CPU time 1.71 seconds
Started Apr 28 04:30:27 PM PDT 24
Finished Apr 28 04:30:29 PM PDT 24
Peak memory 218256 kb
Host smart-25833c02-de47-4850-9b79-26a4ca1ef968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017417377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3017417377
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.547590171
Short name T245
Test name
Test status
Simulation time 49806056 ps
CPU time 1.23 seconds
Started Apr 28 04:30:24 PM PDT 24
Finished Apr 28 04:30:26 PM PDT 24
Peak memory 217036 kb
Host smart-aff40f6d-d0d8-406c-a363-0f6e6e7c4581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547590171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.547590171
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.3071518824
Short name T527
Test name
Test status
Simulation time 30646668 ps
CPU time 1.69 seconds
Started Apr 28 04:30:29 PM PDT 24
Finished Apr 28 04:30:31 PM PDT 24
Peak memory 218168 kb
Host smart-c97f3a72-9adf-42bd-b9b7-4215473e02e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071518824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3071518824
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2509673161
Short name T663
Test name
Test status
Simulation time 75085270 ps
CPU time 1.59 seconds
Started Apr 28 04:30:24 PM PDT 24
Finished Apr 28 04:30:26 PM PDT 24
Peak memory 218424 kb
Host smart-200c8b85-528e-4413-85ed-8a82eb128017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509673161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2509673161
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1304383527
Short name T241
Test name
Test status
Simulation time 91086421 ps
CPU time 1.29 seconds
Started Apr 28 04:28:17 PM PDT 24
Finished Apr 28 04:28:19 PM PDT 24
Peak memory 215536 kb
Host smart-8034abb8-a7fa-4d84-9a85-5c6bb3d3c4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304383527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1304383527
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3072379006
Short name T695
Test name
Test status
Simulation time 33768427 ps
CPU time 0.97 seconds
Started Apr 28 04:28:22 PM PDT 24
Finished Apr 28 04:28:23 PM PDT 24
Peak memory 206556 kb
Host smart-1707eeee-2f76-4538-9134-9e23d9807ecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072379006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3072379006
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.661890340
Short name T534
Test name
Test status
Simulation time 499892527 ps
CPU time 1.42 seconds
Started Apr 28 04:28:16 PM PDT 24
Finished Apr 28 04:28:18 PM PDT 24
Peak memory 219416 kb
Host smart-cce6c500-e858-45f2-ad7d-e14d622f7f8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661890340 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.661890340
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3046779391
Short name T766
Test name
Test status
Simulation time 68188746 ps
CPU time 0.88 seconds
Started Apr 28 04:28:17 PM PDT 24
Finished Apr 28 04:28:19 PM PDT 24
Peak memory 217768 kb
Host smart-d077a408-b5d2-47e5-8415-de676e7f688b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046779391 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3046779391
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2363834357
Short name T362
Test name
Test status
Simulation time 94889314 ps
CPU time 1.3 seconds
Started Apr 28 04:28:18 PM PDT 24
Finished Apr 28 04:28:19 PM PDT 24
Peak memory 217016 kb
Host smart-6c62defd-26f6-49ee-8a35-feadd0c24d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363834357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2363834357
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.843617945
Short name T632
Test name
Test status
Simulation time 30776141 ps
CPU time 0.89 seconds
Started Apr 28 04:28:18 PM PDT 24
Finished Apr 28 04:28:19 PM PDT 24
Peak memory 215624 kb
Host smart-5b96bd69-8504-4d1b-99dd-988f79492711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843617945 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.843617945
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.40947007
Short name T486
Test name
Test status
Simulation time 18961383 ps
CPU time 1.1 seconds
Started Apr 28 04:28:14 PM PDT 24
Finished Apr 28 04:28:16 PM PDT 24
Peak memory 206956 kb
Host smart-2fa410af-5a20-49d3-bdc3-11c26fff01a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40947007 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.40947007
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1392633616
Short name T666
Test name
Test status
Simulation time 855942290 ps
CPU time 5.28 seconds
Started Apr 28 04:28:19 PM PDT 24
Finished Apr 28 04:28:25 PM PDT 24
Peak memory 216816 kb
Host smart-4e24fc2d-e3e9-4a20-add4-acd58a9c85e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392633616 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1392633616
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2946220172
Short name T38
Test name
Test status
Simulation time 64800866592 ps
CPU time 1050.62 seconds
Started Apr 28 04:28:21 PM PDT 24
Finished Apr 28 04:45:52 PM PDT 24
Peak memory 220644 kb
Host smart-9a68a808-17e0-40ef-befc-af146797cb5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946220172 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2946220172
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.2143844779
Short name T395
Test name
Test status
Simulation time 43500511 ps
CPU time 1.62 seconds
Started Apr 28 04:30:24 PM PDT 24
Finished Apr 28 04:30:26 PM PDT 24
Peak memory 218048 kb
Host smart-0f3ce507-9833-432e-8bfe-7bbc5cda6f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143844779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2143844779
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.278134732
Short name T380
Test name
Test status
Simulation time 137759407 ps
CPU time 1.36 seconds
Started Apr 28 04:30:27 PM PDT 24
Finished Apr 28 04:30:28 PM PDT 24
Peak memory 219548 kb
Host smart-85c51d8d-17d1-49c8-92ec-b23e591aab2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278134732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.278134732
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1948428297
Short name T374
Test name
Test status
Simulation time 56773530 ps
CPU time 1.19 seconds
Started Apr 28 04:30:25 PM PDT 24
Finished Apr 28 04:30:26 PM PDT 24
Peak memory 217060 kb
Host smart-d73619b0-766e-4f73-8df6-e34ed6368514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948428297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1948428297
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2225004709
Short name T651
Test name
Test status
Simulation time 60533122 ps
CPU time 1.67 seconds
Started Apr 28 04:30:25 PM PDT 24
Finished Apr 28 04:30:27 PM PDT 24
Peak memory 218408 kb
Host smart-b7845656-2003-4c94-aab5-b65b84471a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225004709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2225004709
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.1709086245
Short name T354
Test name
Test status
Simulation time 49408506 ps
CPU time 1.21 seconds
Started Apr 28 04:30:27 PM PDT 24
Finished Apr 28 04:30:28 PM PDT 24
Peak memory 218312 kb
Host smart-f8f584b6-9462-4f89-b1b7-e02de3772488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709086245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1709086245
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.2990388686
Short name T280
Test name
Test status
Simulation time 68818973 ps
CPU time 1.24 seconds
Started Apr 28 04:30:26 PM PDT 24
Finished Apr 28 04:30:28 PM PDT 24
Peak memory 216864 kb
Host smart-e29905d8-a473-4e0c-8d61-9c95ded3e4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990388686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2990388686
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.475360593
Short name T696
Test name
Test status
Simulation time 40078263 ps
CPU time 1.49 seconds
Started Apr 28 04:30:28 PM PDT 24
Finished Apr 28 04:30:30 PM PDT 24
Peak memory 216732 kb
Host smart-98901c73-feb1-48e5-8b98-00abc8529537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475360593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.475360593
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.1362222809
Short name T309
Test name
Test status
Simulation time 43855011 ps
CPU time 1.31 seconds
Started Apr 28 04:30:26 PM PDT 24
Finished Apr 28 04:30:28 PM PDT 24
Peak memory 218280 kb
Host smart-6d0c8f10-38f9-487f-a6e7-0a0e8f7bae1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362222809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1362222809
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1248729551
Short name T623
Test name
Test status
Simulation time 210616222 ps
CPU time 1.24 seconds
Started Apr 28 04:30:28 PM PDT 24
Finished Apr 28 04:30:30 PM PDT 24
Peak memory 216988 kb
Host smart-e3b0e27a-bc0b-4f9c-b6b9-c10316ca15c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248729551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1248729551
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3889844443
Short name T78
Test name
Test status
Simulation time 97998203 ps
CPU time 1.31 seconds
Started Apr 28 04:28:22 PM PDT 24
Finished Apr 28 04:28:23 PM PDT 24
Peak memory 215560 kb
Host smart-9a3fa746-905e-4ef7-b62d-dcd2bd0c4fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889844443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3889844443
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.594530671
Short name T342
Test name
Test status
Simulation time 56528804 ps
CPU time 0.96 seconds
Started Apr 28 04:28:23 PM PDT 24
Finished Apr 28 04:28:24 PM PDT 24
Peak memory 215088 kb
Host smart-f225d881-0f60-4d65-b67a-4724b9905155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594530671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.594530671
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_err.2556345902
Short name T579
Test name
Test status
Simulation time 45421752 ps
CPU time 1.2 seconds
Started Apr 28 04:28:21 PM PDT 24
Finished Apr 28 04:28:23 PM PDT 24
Peak memory 219536 kb
Host smart-a9cbee51-db97-40aa-bd7e-b3c5b4a7b06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556345902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2556345902
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3791848054
Short name T653
Test name
Test status
Simulation time 64943518 ps
CPU time 1.04 seconds
Started Apr 28 04:28:17 PM PDT 24
Finished Apr 28 04:28:19 PM PDT 24
Peak memory 216988 kb
Host smart-11f585e8-6ddb-4ac7-9995-12e8971dab64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791848054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3791848054
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2740042037
Short name T790
Test name
Test status
Simulation time 27635462 ps
CPU time 1.2 seconds
Started Apr 28 04:28:32 PM PDT 24
Finished Apr 28 04:28:34 PM PDT 24
Peak memory 223860 kb
Host smart-1b09cccb-27dc-4864-9b64-2bc06e4aef05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740042037 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2740042037
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3017574197
Short name T333
Test name
Test status
Simulation time 52754877 ps
CPU time 0.99 seconds
Started Apr 28 04:29:09 PM PDT 24
Finished Apr 28 04:29:10 PM PDT 24
Peak memory 215204 kb
Host smart-d2256a2e-4515-46aa-9691-62d038ff5141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017574197 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3017574197
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2833477327
Short name T606
Test name
Test status
Simulation time 285184066 ps
CPU time 4.54 seconds
Started Apr 28 04:28:17 PM PDT 24
Finished Apr 28 04:28:22 PM PDT 24
Peak memory 216808 kb
Host smart-aecdd909-6e2f-4dcf-80da-8a58b0984d10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833477327 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2833477327
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.4152522806
Short name T830
Test name
Test status
Simulation time 351338905320 ps
CPU time 1945.75 seconds
Started Apr 28 04:28:17 PM PDT 24
Finished Apr 28 05:00:43 PM PDT 24
Peak memory 228712 kb
Host smart-10d48a93-565b-43e7-be51-69e45e18c92d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152522806 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.4152522806
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.2443857985
Short name T596
Test name
Test status
Simulation time 108445539 ps
CPU time 1.03 seconds
Started Apr 28 04:30:28 PM PDT 24
Finished Apr 28 04:30:30 PM PDT 24
Peak memory 217012 kb
Host smart-b5624acf-d2a7-4eed-a44d-0f9070c98a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443857985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2443857985
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.2256314933
Short name T783
Test name
Test status
Simulation time 25634580 ps
CPU time 1.21 seconds
Started Apr 28 04:30:28 PM PDT 24
Finished Apr 28 04:30:30 PM PDT 24
Peak memory 216772 kb
Host smart-4db77272-9ba7-42bc-963f-0432f3c6ee19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256314933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2256314933
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.2826599610
Short name T672
Test name
Test status
Simulation time 96214681 ps
CPU time 1.1 seconds
Started Apr 28 04:30:28 PM PDT 24
Finished Apr 28 04:30:30 PM PDT 24
Peak memory 216808 kb
Host smart-91354fa8-004a-430d-8553-d4875d5409ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826599610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2826599610
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1820978139
Short name T511
Test name
Test status
Simulation time 53482327 ps
CPU time 1.86 seconds
Started Apr 28 04:30:29 PM PDT 24
Finished Apr 28 04:30:31 PM PDT 24
Peak memory 218364 kb
Host smart-9a3c2a5b-dc61-4bb9-96ae-a03cc8ae1aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820978139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1820978139
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.3008282988
Short name T272
Test name
Test status
Simulation time 50279673 ps
CPU time 1.48 seconds
Started Apr 28 04:30:30 PM PDT 24
Finished Apr 28 04:30:32 PM PDT 24
Peak memory 218088 kb
Host smart-905bd2c6-ed3e-42fe-950a-80d3fe0e209c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008282988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3008282988
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.3709793106
Short name T375
Test name
Test status
Simulation time 115297312 ps
CPU time 1.15 seconds
Started Apr 28 04:30:30 PM PDT 24
Finished Apr 28 04:30:32 PM PDT 24
Peak memory 218744 kb
Host smart-7b47accd-2093-4193-8d93-fe179bf1bf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709793106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3709793106
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.112657350
Short name T548
Test name
Test status
Simulation time 25885089 ps
CPU time 1.25 seconds
Started Apr 28 04:30:30 PM PDT 24
Finished Apr 28 04:30:32 PM PDT 24
Peak memory 219196 kb
Host smart-e818c2cf-b80a-4ed5-b519-fc206f6d54c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112657350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.112657350
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.906816262
Short name T444
Test name
Test status
Simulation time 74992163 ps
CPU time 2.94 seconds
Started Apr 28 04:30:29 PM PDT 24
Finished Apr 28 04:30:32 PM PDT 24
Peak memory 217316 kb
Host smart-6878a4e9-08f4-4122-b72a-8966821aa926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906816262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.906816262
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2473856290
Short name T145
Test name
Test status
Simulation time 26033881 ps
CPU time 1.27 seconds
Started Apr 28 04:28:23 PM PDT 24
Finished Apr 28 04:28:25 PM PDT 24
Peak memory 215540 kb
Host smart-2280a8a1-8db8-448c-8408-318a4e757e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473856290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2473856290
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.325329165
Short name T215
Test name
Test status
Simulation time 21298183 ps
CPU time 0.97 seconds
Started Apr 28 04:28:27 PM PDT 24
Finished Apr 28 04:28:28 PM PDT 24
Peak memory 206508 kb
Host smart-a95339a4-a4cb-4e56-b6fd-37e99665804c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325329165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.325329165
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2021952484
Short name T20
Test name
Test status
Simulation time 25581500 ps
CPU time 0.87 seconds
Started Apr 28 04:28:30 PM PDT 24
Finished Apr 28 04:28:31 PM PDT 24
Peak memory 215812 kb
Host smart-4d948900-dda3-4bb3-b626-d90c48408129
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021952484 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2021952484
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1657536117
Short name T116
Test name
Test status
Simulation time 93200661 ps
CPU time 1.15 seconds
Started Apr 28 04:28:27 PM PDT 24
Finished Apr 28 04:28:29 PM PDT 24
Peak memory 216676 kb
Host smart-94f47309-87f8-41a7-bda9-c57f843975f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657536117 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1657536117
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2969247733
Short name T102
Test name
Test status
Simulation time 29015526 ps
CPU time 1.53 seconds
Started Apr 28 04:28:27 PM PDT 24
Finished Apr 28 04:28:29 PM PDT 24
Peak memory 229432 kb
Host smart-babca005-070f-45b1-9dd9-8f16674d449e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969247733 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2969247733
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3635893253
Short name T407
Test name
Test status
Simulation time 67200935 ps
CPU time 2.51 seconds
Started Apr 28 04:28:23 PM PDT 24
Finished Apr 28 04:28:26 PM PDT 24
Peak memory 218216 kb
Host smart-e1f15749-63b7-4b53-919f-8386675279fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635893253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3635893253
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.2076934332
Short name T665
Test name
Test status
Simulation time 45222545 ps
CPU time 0.92 seconds
Started Apr 28 04:28:21 PM PDT 24
Finished Apr 28 04:28:22 PM PDT 24
Peak memory 215180 kb
Host smart-19031b07-b45d-4ae9-8ca2-1b44835570d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076934332 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2076934332
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3852830374
Short name T577
Test name
Test status
Simulation time 1446075896 ps
CPU time 5.7 seconds
Started Apr 28 04:28:32 PM PDT 24
Finished Apr 28 04:28:38 PM PDT 24
Peak memory 216976 kb
Host smart-109af22e-1b99-4496-b19d-912c9522bcc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852830374 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3852830374
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.61888280
Short name T770
Test name
Test status
Simulation time 139663768075 ps
CPU time 764.53 seconds
Started Apr 28 04:28:27 PM PDT 24
Finished Apr 28 04:41:12 PM PDT 24
Peak memory 227708 kb
Host smart-1e3d4072-355a-46bf-8847-14d45481a3cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61888280 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.61888280
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.3743204782
Short name T411
Test name
Test status
Simulation time 131073811 ps
CPU time 1.16 seconds
Started Apr 28 04:30:32 PM PDT 24
Finished Apr 28 04:30:34 PM PDT 24
Peak memory 216864 kb
Host smart-98f914ad-15a8-46d2-a911-e6f64bae0d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743204782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3743204782
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.1492326678
Short name T39
Test name
Test status
Simulation time 57152792 ps
CPU time 1.74 seconds
Started Apr 28 04:30:28 PM PDT 24
Finished Apr 28 04:30:30 PM PDT 24
Peak memory 218180 kb
Host smart-27d6aaf7-7769-4eb4-b3de-50011c0012af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492326678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1492326678
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.3727950081
Short name T421
Test name
Test status
Simulation time 125477434 ps
CPU time 3.03 seconds
Started Apr 28 04:30:30 PM PDT 24
Finished Apr 28 04:30:34 PM PDT 24
Peak memory 217084 kb
Host smart-997e0b52-0d1b-497e-9040-4c2027da8807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727950081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3727950081
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.2032750883
Short name T298
Test name
Test status
Simulation time 193796905 ps
CPU time 3.01 seconds
Started Apr 28 04:30:28 PM PDT 24
Finished Apr 28 04:30:31 PM PDT 24
Peak memory 219924 kb
Host smart-1f279412-7f9f-4c4e-8fe9-be807dfe8ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032750883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2032750883
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.272593836
Short name T775
Test name
Test status
Simulation time 223476097 ps
CPU time 1.4 seconds
Started Apr 28 04:30:30 PM PDT 24
Finished Apr 28 04:30:32 PM PDT 24
Peak memory 216992 kb
Host smart-587939a8-8dcc-4765-aafc-c44df65e0837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272593836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.272593836
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.17209765
Short name T649
Test name
Test status
Simulation time 75857467 ps
CPU time 1.5 seconds
Started Apr 28 04:30:42 PM PDT 24
Finished Apr 28 04:30:45 PM PDT 24
Peak memory 218616 kb
Host smart-2c8d575c-9a51-488f-b80b-658c18e558f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17209765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.17209765
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.526663449
Short name T415
Test name
Test status
Simulation time 71435852 ps
CPU time 1.6 seconds
Started Apr 28 04:30:36 PM PDT 24
Finished Apr 28 04:30:39 PM PDT 24
Peak memory 218268 kb
Host smart-9a4354b2-c22c-4ce4-ab73-b0f1750fd8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526663449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.526663449
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.2709017456
Short name T552
Test name
Test status
Simulation time 61901502 ps
CPU time 1.33 seconds
Started Apr 28 04:30:35 PM PDT 24
Finished Apr 28 04:30:37 PM PDT 24
Peak memory 218456 kb
Host smart-9b0253fa-9263-443c-8795-b554c3a5c8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709017456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2709017456
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2156161489
Short name T305
Test name
Test status
Simulation time 61795519 ps
CPU time 0.99 seconds
Started Apr 28 04:30:35 PM PDT 24
Finished Apr 28 04:30:37 PM PDT 24
Peak memory 216584 kb
Host smart-a97c8122-a69c-4e40-bca9-e82351a7de3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156161489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2156161489
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.1431504047
Short name T336
Test name
Test status
Simulation time 66557116 ps
CPU time 1.4 seconds
Started Apr 28 04:30:35 PM PDT 24
Finished Apr 28 04:30:37 PM PDT 24
Peak memory 217116 kb
Host smart-98edd330-b749-495a-93a2-3bb79a409cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431504047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1431504047
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3218941955
Short name T185
Test name
Test status
Simulation time 25877499 ps
CPU time 1.23 seconds
Started Apr 28 04:28:28 PM PDT 24
Finished Apr 28 04:28:30 PM PDT 24
Peak memory 215588 kb
Host smart-45c2df94-6872-4802-aa25-bd5112630a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218941955 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3218941955
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2794029192
Short name T755
Test name
Test status
Simulation time 57175616 ps
CPU time 0.93 seconds
Started Apr 28 04:28:27 PM PDT 24
Finished Apr 28 04:28:29 PM PDT 24
Peak memory 214580 kb
Host smart-b61ff34d-d6c9-42dd-8e1f-9d4ae1aa2e9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794029192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2794029192
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.738513387
Short name T499
Test name
Test status
Simulation time 431344630 ps
CPU time 1.56 seconds
Started Apr 28 04:28:28 PM PDT 24
Finished Apr 28 04:28:30 PM PDT 24
Peak memory 216724 kb
Host smart-5bfd7d14-ce35-4491-8345-85d073432917
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738513387 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.738513387
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.2223247762
Short name T136
Test name
Test status
Simulation time 34195729 ps
CPU time 1 seconds
Started Apr 28 04:28:28 PM PDT 24
Finished Apr 28 04:28:30 PM PDT 24
Peak memory 223712 kb
Host smart-e4fcf21a-de4c-4078-9864-d196a65c5fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223247762 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2223247762
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2647813909
Short name T396
Test name
Test status
Simulation time 32230558 ps
CPU time 1.34 seconds
Started Apr 28 04:28:29 PM PDT 24
Finished Apr 28 04:28:31 PM PDT 24
Peak memory 217000 kb
Host smart-946973dc-896f-47e0-8c93-6cb30faa4783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647813909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2647813909
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_smoke.1340465188
Short name T650
Test name
Test status
Simulation time 13915590 ps
CPU time 0.97 seconds
Started Apr 28 04:28:29 PM PDT 24
Finished Apr 28 04:28:30 PM PDT 24
Peak memory 215176 kb
Host smart-5baf0d62-de5c-4dfa-9b81-1f4ec1714586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340465188 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1340465188
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.664318618
Short name T5
Test name
Test status
Simulation time 336969752 ps
CPU time 4.12 seconds
Started Apr 28 04:28:27 PM PDT 24
Finished Apr 28 04:28:31 PM PDT 24
Peak memory 215264 kb
Host smart-d0e41db9-c797-4b05-ab56-ae512b0f5f2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664318618 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.664318618
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.4165665245
Short name T324
Test name
Test status
Simulation time 41883580806 ps
CPU time 582.01 seconds
Started Apr 28 04:28:28 PM PDT 24
Finished Apr 28 04:38:10 PM PDT 24
Peak memory 221480 kb
Host smart-dbd87912-8b1c-4d51-b93b-5ba8d77350e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165665245 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.4165665245
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.1524578104
Short name T80
Test name
Test status
Simulation time 220289681 ps
CPU time 1.3 seconds
Started Apr 28 04:30:40 PM PDT 24
Finished Apr 28 04:30:42 PM PDT 24
Peak memory 217056 kb
Host smart-b174d1b8-5e6d-428a-9c3f-43ec5abde0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524578104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1524578104
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.1552761729
Short name T484
Test name
Test status
Simulation time 38891766 ps
CPU time 1.51 seconds
Started Apr 28 04:30:36 PM PDT 24
Finished Apr 28 04:30:38 PM PDT 24
Peak memory 218204 kb
Host smart-26f03cb5-54b3-476b-beff-aa6c25ee6174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552761729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1552761729
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.3751050092
Short name T587
Test name
Test status
Simulation time 33252688 ps
CPU time 1.38 seconds
Started Apr 28 04:30:33 PM PDT 24
Finished Apr 28 04:30:34 PM PDT 24
Peak memory 217144 kb
Host smart-748b1fd3-634d-4361-84d9-89df58149d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751050092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3751050092
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.1957902915
Short name T453
Test name
Test status
Simulation time 53969436 ps
CPU time 1.44 seconds
Started Apr 28 04:30:34 PM PDT 24
Finished Apr 28 04:30:36 PM PDT 24
Peak memory 218240 kb
Host smart-dbf07af8-108b-453b-ae78-8149b201159b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957902915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1957902915
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.629129529
Short name T330
Test name
Test status
Simulation time 69937282 ps
CPU time 1.35 seconds
Started Apr 28 04:30:35 PM PDT 24
Finished Apr 28 04:30:37 PM PDT 24
Peak memory 218496 kb
Host smart-ceba8cbd-1fa3-4a6d-8e7c-2a952cd63c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629129529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.629129529
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3312611278
Short name T357
Test name
Test status
Simulation time 84829117 ps
CPU time 1.15 seconds
Started Apr 28 04:30:35 PM PDT 24
Finished Apr 28 04:30:37 PM PDT 24
Peak memory 216456 kb
Host smart-c0aea3d6-7f8f-42d1-a586-844d60bdace6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312611278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3312611278
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.3116991053
Short name T585
Test name
Test status
Simulation time 69474096 ps
CPU time 1.15 seconds
Started Apr 28 04:30:34 PM PDT 24
Finished Apr 28 04:30:36 PM PDT 24
Peak memory 217084 kb
Host smart-de9ed6b3-16f3-40de-bc35-d813e807d980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116991053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3116991053
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.3137205544
Short name T337
Test name
Test status
Simulation time 56382127 ps
CPU time 2.05 seconds
Started Apr 28 04:30:40 PM PDT 24
Finished Apr 28 04:30:43 PM PDT 24
Peak memory 218124 kb
Host smart-5e36f216-4f09-436b-abb7-d390b07e799d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137205544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3137205544
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.1618643193
Short name T700
Test name
Test status
Simulation time 133595882 ps
CPU time 1.55 seconds
Started Apr 28 04:30:42 PM PDT 24
Finished Apr 28 04:30:45 PM PDT 24
Peak memory 217148 kb
Host smart-c5c64ed3-73aa-4863-b67d-2686fc5e7689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618643193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1618643193
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1805744516
Short name T745
Test name
Test status
Simulation time 68349953 ps
CPU time 1.19 seconds
Started Apr 28 04:28:32 PM PDT 24
Finished Apr 28 04:28:33 PM PDT 24
Peak memory 215552 kb
Host smart-5a4a20d4-83bc-4970-b87c-0b2f8115dc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805744516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1805744516
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.4280488645
Short name T757
Test name
Test status
Simulation time 35766228 ps
CPU time 1.37 seconds
Started Apr 28 04:28:32 PM PDT 24
Finished Apr 28 04:28:34 PM PDT 24
Peak memory 206804 kb
Host smart-af48f507-94e0-4906-a221-fb5a60d796f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280488645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.4280488645
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.1050262136
Short name T535
Test name
Test status
Simulation time 17210111 ps
CPU time 0.88 seconds
Started Apr 28 04:28:36 PM PDT 24
Finished Apr 28 04:28:37 PM PDT 24
Peak memory 215728 kb
Host smart-97ab8b64-a614-4541-915d-0d21f49349e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050262136 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1050262136
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1225641887
Short name T432
Test name
Test status
Simulation time 63279745 ps
CPU time 1.29 seconds
Started Apr 28 04:28:30 PM PDT 24
Finished Apr 28 04:28:32 PM PDT 24
Peak memory 219240 kb
Host smart-f708dd68-5147-49cb-a05c-12f2d8a20ea8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225641887 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1225641887
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.583494987
Short name T711
Test name
Test status
Simulation time 18240902 ps
CPU time 1.13 seconds
Started Apr 28 04:28:34 PM PDT 24
Finished Apr 28 04:28:36 PM PDT 24
Peak memory 218120 kb
Host smart-05c1a74d-e306-414b-92f8-608eccef8cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583494987 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.583494987
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3595997863
Short name T12
Test name
Test status
Simulation time 60793815 ps
CPU time 1.46 seconds
Started Apr 28 04:28:32 PM PDT 24
Finished Apr 28 04:28:34 PM PDT 24
Peak memory 219484 kb
Host smart-bb82e33c-371a-4a67-9222-8476211ef7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595997863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3595997863
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.2630723441
Short name T780
Test name
Test status
Simulation time 21056138 ps
CPU time 1.1 seconds
Started Apr 28 04:28:32 PM PDT 24
Finished Apr 28 04:28:34 PM PDT 24
Peak memory 215748 kb
Host smart-6fa1253f-0a89-440f-b088-ae5dcc8ce538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630723441 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2630723441
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3922479043
Short name T738
Test name
Test status
Simulation time 44246814 ps
CPU time 0.95 seconds
Started Apr 28 04:28:27 PM PDT 24
Finished Apr 28 04:28:28 PM PDT 24
Peak memory 215156 kb
Host smart-2f91a0aa-448b-42bf-a16a-09c361579ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922479043 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3922479043
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1816941079
Short name T202
Test name
Test status
Simulation time 2157589201 ps
CPU time 4.98 seconds
Started Apr 28 04:28:30 PM PDT 24
Finished Apr 28 04:28:36 PM PDT 24
Peak memory 217140 kb
Host smart-d13dd81b-78ce-48c1-807d-8a5018ac9079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816941079 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1816941079
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/171.edn_genbits.1786970283
Short name T688
Test name
Test status
Simulation time 65556281 ps
CPU time 2.07 seconds
Started Apr 28 04:30:34 PM PDT 24
Finished Apr 28 04:30:37 PM PDT 24
Peak memory 218040 kb
Host smart-20039dbf-dae1-4aa1-b805-674d0d720b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786970283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1786970283
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2296212416
Short name T426
Test name
Test status
Simulation time 18790128 ps
CPU time 1.07 seconds
Started Apr 28 04:30:34 PM PDT 24
Finished Apr 28 04:30:36 PM PDT 24
Peak memory 217012 kb
Host smart-db7d7dde-97cd-4517-a06c-32d0dd02a9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296212416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2296212416
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.1285072042
Short name T45
Test name
Test status
Simulation time 75670623 ps
CPU time 1.41 seconds
Started Apr 28 04:30:38 PM PDT 24
Finished Apr 28 04:30:41 PM PDT 24
Peak memory 215204 kb
Host smart-5f0f5ef4-8839-4a29-9a3d-ce021f039584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285072042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1285072042
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.997716082
Short name T310
Test name
Test status
Simulation time 117988553 ps
CPU time 1.31 seconds
Started Apr 28 04:30:34 PM PDT 24
Finished Apr 28 04:30:36 PM PDT 24
Peak memory 218540 kb
Host smart-5f07aa2e-9ad1-49e5-9371-acf5fba1e571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997716082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.997716082
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.2201492258
Short name T567
Test name
Test status
Simulation time 97072872 ps
CPU time 1.37 seconds
Started Apr 28 04:30:34 PM PDT 24
Finished Apr 28 04:30:36 PM PDT 24
Peak memory 218484 kb
Host smart-b29f3e4c-bcf7-42e4-9c8f-fc8f0deb925e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201492258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2201492258
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.3912205203
Short name T673
Test name
Test status
Simulation time 26042210 ps
CPU time 1.34 seconds
Started Apr 28 04:30:41 PM PDT 24
Finished Apr 28 04:30:43 PM PDT 24
Peak memory 216780 kb
Host smart-d02ce813-bba1-43ba-9604-d7240261c1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912205203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3912205203
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.3943109733
Short name T422
Test name
Test status
Simulation time 50042814 ps
CPU time 1.25 seconds
Started Apr 28 04:30:40 PM PDT 24
Finished Apr 28 04:30:42 PM PDT 24
Peak memory 216912 kb
Host smart-1c91e9f1-d7de-47c6-b228-66be830f809c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943109733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3943109733
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.2575569855
Short name T22
Test name
Test status
Simulation time 96508384 ps
CPU time 1.18 seconds
Started Apr 28 04:30:37 PM PDT 24
Finished Apr 28 04:30:39 PM PDT 24
Peak memory 218192 kb
Host smart-3aea5cf9-7ced-4fa0-ab28-86c41e82eb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575569855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2575569855
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.571643535
Short name T431
Test name
Test status
Simulation time 63940170 ps
CPU time 2.42 seconds
Started Apr 28 04:30:34 PM PDT 24
Finished Apr 28 04:30:38 PM PDT 24
Peak memory 218348 kb
Host smart-8e5b366c-5974-443d-9b62-6de685bb80ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571643535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.571643535
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.2580970921
Short name T619
Test name
Test status
Simulation time 14953449 ps
CPU time 0.96 seconds
Started Apr 28 04:28:35 PM PDT 24
Finished Apr 28 04:28:36 PM PDT 24
Peak memory 206548 kb
Host smart-79eaea30-7093-46f8-8a00-12f84e176b9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580970921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2580970921
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2236681837
Short name T441
Test name
Test status
Simulation time 11356950 ps
CPU time 0.92 seconds
Started Apr 28 04:28:35 PM PDT 24
Finished Apr 28 04:28:36 PM PDT 24
Peak memory 215780 kb
Host smart-bb3684ae-3fa1-4e42-8a10-3cb183c2d937
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236681837 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2236681837
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.21120084
Short name T773
Test name
Test status
Simulation time 185953054 ps
CPU time 1.25 seconds
Started Apr 28 04:28:32 PM PDT 24
Finished Apr 28 04:28:34 PM PDT 24
Peak memory 219496 kb
Host smart-05009027-7e5c-4a5e-bd67-4b80bd38fa39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21120084 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_dis
able_auto_req_mode.21120084
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1776741870
Short name T114
Test name
Test status
Simulation time 34283076 ps
CPU time 0.96 seconds
Started Apr 28 04:28:35 PM PDT 24
Finished Apr 28 04:28:37 PM PDT 24
Peak memory 219668 kb
Host smart-764a3266-79e0-4c9d-b621-f887f913debb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776741870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1776741870
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.168864102
Short name T323
Test name
Test status
Simulation time 91628323 ps
CPU time 1.47 seconds
Started Apr 28 04:28:36 PM PDT 24
Finished Apr 28 04:28:38 PM PDT 24
Peak memory 218520 kb
Host smart-fe2d4de7-9600-49e4-b264-91d5c26c3697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168864102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.168864102
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1373145892
Short name T53
Test name
Test status
Simulation time 24804517 ps
CPU time 1.15 seconds
Started Apr 28 04:28:31 PM PDT 24
Finished Apr 28 04:28:32 PM PDT 24
Peak memory 223972 kb
Host smart-cfd49c24-8bcf-42f3-8323-33d454c57dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373145892 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1373145892
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3300715844
Short name T805
Test name
Test status
Simulation time 123505777 ps
CPU time 0.98 seconds
Started Apr 28 04:28:33 PM PDT 24
Finished Apr 28 04:28:34 PM PDT 24
Peak memory 215144 kb
Host smart-113af9aa-2832-4832-9d46-9ea98f798402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300715844 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3300715844
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1043574781
Short name T813
Test name
Test status
Simulation time 59939918 ps
CPU time 1.47 seconds
Started Apr 28 04:28:33 PM PDT 24
Finished Apr 28 04:28:35 PM PDT 24
Peak memory 218120 kb
Host smart-bd4c5d2a-a625-4c7b-891b-146827357ed4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043574781 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1043574781
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3629701085
Short name T321
Test name
Test status
Simulation time 43298968750 ps
CPU time 588.65 seconds
Started Apr 28 04:28:32 PM PDT 24
Finished Apr 28 04:38:22 PM PDT 24
Peak memory 217972 kb
Host smart-ceac5f48-572a-4d9d-9f8a-4e4ddadb776c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629701085 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3629701085
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.272595019
Short name T400
Test name
Test status
Simulation time 40470300 ps
CPU time 1.45 seconds
Started Apr 28 04:30:37 PM PDT 24
Finished Apr 28 04:30:40 PM PDT 24
Peak memory 217988 kb
Host smart-b205a767-1bba-4e3a-b0bf-350d6118572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272595019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.272595019
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.174629638
Short name T371
Test name
Test status
Simulation time 61103168 ps
CPU time 2.22 seconds
Started Apr 28 04:30:38 PM PDT 24
Finished Apr 28 04:30:42 PM PDT 24
Peak memory 219800 kb
Host smart-64920f99-2418-4279-8129-2aa23bc9a8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174629638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.174629638
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.3458237627
Short name T481
Test name
Test status
Simulation time 92721835 ps
CPU time 1.38 seconds
Started Apr 28 04:30:36 PM PDT 24
Finished Apr 28 04:30:38 PM PDT 24
Peak memory 217724 kb
Host smart-a725e2d2-b98c-4974-8e7c-320197411d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458237627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3458237627
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.379978795
Short name T331
Test name
Test status
Simulation time 24526862 ps
CPU time 1.32 seconds
Started Apr 28 04:30:37 PM PDT 24
Finished Apr 28 04:30:39 PM PDT 24
Peak memory 217048 kb
Host smart-8d4cc14c-7ce6-4809-be6f-56471b747060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379978795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.379978795
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.1760787182
Short name T583
Test name
Test status
Simulation time 81051458 ps
CPU time 1.45 seconds
Started Apr 28 04:30:40 PM PDT 24
Finished Apr 28 04:30:42 PM PDT 24
Peak memory 218520 kb
Host smart-45089662-419f-4515-b748-4d6e37700db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760787182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1760787182
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.3850552268
Short name T346
Test name
Test status
Simulation time 30257329 ps
CPU time 1.33 seconds
Started Apr 28 04:30:37 PM PDT 24
Finished Apr 28 04:30:39 PM PDT 24
Peak memory 216872 kb
Host smart-d0a370aa-4b31-41df-bb57-84e70481afc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850552268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3850552268
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.2593900571
Short name T601
Test name
Test status
Simulation time 24104661 ps
CPU time 1.27 seconds
Started Apr 28 04:30:35 PM PDT 24
Finished Apr 28 04:30:37 PM PDT 24
Peak memory 219636 kb
Host smart-01a3c234-9b73-419a-99e0-f6007be21da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593900571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2593900571
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.2174733434
Short name T644
Test name
Test status
Simulation time 48105545 ps
CPU time 1.61 seconds
Started Apr 28 04:30:39 PM PDT 24
Finished Apr 28 04:30:42 PM PDT 24
Peak memory 218424 kb
Host smart-c211a117-3390-4926-9950-8d01cf21e299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174733434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2174733434
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1864526045
Short name T807
Test name
Test status
Simulation time 85872125 ps
CPU time 1.17 seconds
Started Apr 28 04:30:37 PM PDT 24
Finished Apr 28 04:30:39 PM PDT 24
Peak memory 216976 kb
Host smart-9b70d266-be55-4116-83a5-e5db705201e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864526045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1864526045
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.454109488
Short name T85
Test name
Test status
Simulation time 51508357 ps
CPU time 1.49 seconds
Started Apr 28 04:30:37 PM PDT 24
Finished Apr 28 04:30:40 PM PDT 24
Peak memory 218368 kb
Host smart-4a7df1ea-813d-4e29-b6ab-e9d5426e03b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454109488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.454109488
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3934758592
Short name T266
Test name
Test status
Simulation time 57893376 ps
CPU time 1.16 seconds
Started Apr 28 04:28:39 PM PDT 24
Finished Apr 28 04:28:41 PM PDT 24
Peak memory 215564 kb
Host smart-dbc4b160-9e60-4ca8-8f8c-ba05cca6d6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934758592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3934758592
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.314123985
Short name T452
Test name
Test status
Simulation time 49955746 ps
CPU time 0.95 seconds
Started Apr 28 04:28:46 PM PDT 24
Finished Apr 28 04:28:48 PM PDT 24
Peak memory 215080 kb
Host smart-a2fb8c0b-b3ee-499a-b832-a06ee9e9ac3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314123985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.314123985
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.879716479
Short name T134
Test name
Test status
Simulation time 18696822 ps
CPU time 0.93 seconds
Started Apr 28 04:28:46 PM PDT 24
Finished Apr 28 04:28:48 PM PDT 24
Peak memory 216384 kb
Host smart-b25d5d7a-ff00-4d27-94ac-a4ba43d453a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879716479 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.879716479
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.291500718
Short name T774
Test name
Test status
Simulation time 27164114 ps
CPU time 1.15 seconds
Started Apr 28 04:28:38 PM PDT 24
Finished Apr 28 04:28:39 PM PDT 24
Peak memory 217984 kb
Host smart-662561ae-2295-4514-9a71-e065af107af6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291500718 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.291500718
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2358566604
Short name T104
Test name
Test status
Simulation time 21206065 ps
CPU time 1.28 seconds
Started Apr 28 04:28:37 PM PDT 24
Finished Apr 28 04:28:39 PM PDT 24
Peak memory 229316 kb
Host smart-571a04ac-1dfd-4a3a-aeef-64fba221f0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358566604 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2358566604
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_intr.1779479905
Short name T155
Test name
Test status
Simulation time 30659649 ps
CPU time 0.89 seconds
Started Apr 28 04:28:36 PM PDT 24
Finished Apr 28 04:28:37 PM PDT 24
Peak memory 215524 kb
Host smart-e6c2f2c2-64f3-4edb-b6f3-4f43cb0e8799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779479905 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1779479905
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1130619496
Short name T435
Test name
Test status
Simulation time 76623118 ps
CPU time 0.98 seconds
Started Apr 28 04:28:35 PM PDT 24
Finished Apr 28 04:28:36 PM PDT 24
Peak memory 207004 kb
Host smart-c5fd6534-c3ab-4c0e-a800-a98ce7cb64ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130619496 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1130619496
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1738616217
Short name T492
Test name
Test status
Simulation time 587126990 ps
CPU time 5.84 seconds
Started Apr 28 04:28:35 PM PDT 24
Finished Apr 28 04:28:42 PM PDT 24
Peak memory 218068 kb
Host smart-c88eb138-6c26-439e-bcba-ef0196cd6e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738616217 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1738616217
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3597479873
Short name T494
Test name
Test status
Simulation time 104969617003 ps
CPU time 723.72 seconds
Started Apr 28 04:28:37 PM PDT 24
Finished Apr 28 04:40:41 PM PDT 24
Peak memory 220568 kb
Host smart-63aa0269-80a4-4a40-98da-7249d2c3ca2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597479873 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3597479873
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.edn_genbits.1107651707
Short name T493
Test name
Test status
Simulation time 39063483 ps
CPU time 1.4 seconds
Started Apr 28 04:30:38 PM PDT 24
Finished Apr 28 04:30:40 PM PDT 24
Peak memory 216808 kb
Host smart-bf43dcfe-6492-4746-9dfb-3cc07fa9dfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107651707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1107651707
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.3052764907
Short name T768
Test name
Test status
Simulation time 112286731 ps
CPU time 1.21 seconds
Started Apr 28 04:30:38 PM PDT 24
Finished Apr 28 04:30:41 PM PDT 24
Peak memory 216948 kb
Host smart-a04c4d82-2865-4b04-addf-25c560fc0950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052764907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3052764907
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.997853516
Short name T630
Test name
Test status
Simulation time 29453931 ps
CPU time 1.23 seconds
Started Apr 28 04:30:38 PM PDT 24
Finished Apr 28 04:30:41 PM PDT 24
Peak memory 217076 kb
Host smart-dbb8433f-3852-44ec-bf08-579b8fdace16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997853516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.997853516
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.385797701
Short name T414
Test name
Test status
Simulation time 55020603 ps
CPU time 2.11 seconds
Started Apr 28 04:30:39 PM PDT 24
Finished Apr 28 04:30:42 PM PDT 24
Peak memory 217128 kb
Host smart-9b33121b-c676-4bce-a389-20607ef0a57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385797701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.385797701
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.965817218
Short name T675
Test name
Test status
Simulation time 93931762 ps
CPU time 2.34 seconds
Started Apr 28 04:30:37 PM PDT 24
Finished Apr 28 04:30:40 PM PDT 24
Peak memory 217064 kb
Host smart-5a95e86e-85fc-46bf-9e9b-f2636ae98b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965817218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.965817218
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.1897249423
Short name T503
Test name
Test status
Simulation time 155756086 ps
CPU time 1.36 seconds
Started Apr 28 04:30:37 PM PDT 24
Finished Apr 28 04:30:40 PM PDT 24
Peak memory 218132 kb
Host smart-cbed53d9-1ff0-4d0b-b318-38c2f5550c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897249423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1897249423
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.43331113
Short name T591
Test name
Test status
Simulation time 35438800 ps
CPU time 1.14 seconds
Started Apr 28 04:30:37 PM PDT 24
Finished Apr 28 04:30:39 PM PDT 24
Peak memory 217048 kb
Host smart-307c6417-ef2d-4ca2-a73d-a45b9a88c566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43331113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.43331113
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.2432823235
Short name T355
Test name
Test status
Simulation time 87842637 ps
CPU time 1.24 seconds
Started Apr 28 04:30:39 PM PDT 24
Finished Apr 28 04:30:41 PM PDT 24
Peak memory 217092 kb
Host smart-f4281483-f072-4b09-bee7-cb22573d0927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432823235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2432823235
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.679130689
Short name T258
Test name
Test status
Simulation time 24201561 ps
CPU time 1.28 seconds
Started Apr 28 04:27:41 PM PDT 24
Finished Apr 28 04:27:42 PM PDT 24
Peak memory 215504 kb
Host smart-0da52a89-6972-4576-a52c-9cb99dfd78aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679130689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.679130689
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2133934261
Short name T553
Test name
Test status
Simulation time 14512915 ps
CPU time 0.94 seconds
Started Apr 28 04:27:44 PM PDT 24
Finished Apr 28 04:27:45 PM PDT 24
Peak memory 206524 kb
Host smart-d833ca80-4f9b-4474-86ab-1edc2bea8bbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133934261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2133934261
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2627568821
Short name T423
Test name
Test status
Simulation time 26367535 ps
CPU time 0.88 seconds
Started Apr 28 04:27:42 PM PDT 24
Finished Apr 28 04:27:43 PM PDT 24
Peak memory 215928 kb
Host smart-1ce4903c-f4df-4b63-bf29-e34579623804
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627568821 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2627568821
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.4265208063
Short name T307
Test name
Test status
Simulation time 48462971 ps
CPU time 1.21 seconds
Started Apr 28 04:27:37 PM PDT 24
Finished Apr 28 04:27:39 PM PDT 24
Peak memory 216668 kb
Host smart-29c51f68-3488-4598-8234-cdbf2a4fdf8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265208063 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.4265208063
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3144619636
Short name T631
Test name
Test status
Simulation time 18165532 ps
CPU time 1.09 seconds
Started Apr 28 04:27:41 PM PDT 24
Finished Apr 28 04:27:43 PM PDT 24
Peak memory 218252 kb
Host smart-e7590c46-6153-4aff-ae76-e118f4dfa432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144619636 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3144619636
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1541790412
Short name T394
Test name
Test status
Simulation time 63760506 ps
CPU time 1.51 seconds
Started Apr 28 04:27:38 PM PDT 24
Finished Apr 28 04:27:41 PM PDT 24
Peak memory 219612 kb
Host smart-da43e404-27a7-44ab-8f5e-9037d81c2fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541790412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1541790412
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3726785437
Short name T88
Test name
Test status
Simulation time 26220481 ps
CPU time 1.02 seconds
Started Apr 28 04:27:47 PM PDT 24
Finished Apr 28 04:27:49 PM PDT 24
Peak memory 215100 kb
Host smart-8ffec25c-e400-4e82-aba5-46cb9ad370e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726785437 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3726785437
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3294808560
Short name T265
Test name
Test status
Simulation time 166314238 ps
CPU time 1.04 seconds
Started Apr 28 04:27:42 PM PDT 24
Finished Apr 28 04:27:44 PM PDT 24
Peak memory 206968 kb
Host smart-953b4704-2217-42ce-8cf9-3f4df869e49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294808560 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3294808560
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1575567548
Short name T62
Test name
Test status
Simulation time 601711846 ps
CPU time 10.25 seconds
Started Apr 28 04:27:45 PM PDT 24
Finished Apr 28 04:27:56 PM PDT 24
Peak memory 235440 kb
Host smart-a4f64166-9c7f-4a4b-942f-e9571a09f5f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575567548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1575567548
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.4192471462
Short name T420
Test name
Test status
Simulation time 22820205 ps
CPU time 0.93 seconds
Started Apr 28 04:27:40 PM PDT 24
Finished Apr 28 04:27:41 PM PDT 24
Peak memory 215192 kb
Host smart-485a9795-09dd-4ce3-aa39-bb7cb0ae513b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192471462 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.4192471462
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1763653096
Short name T707
Test name
Test status
Simulation time 529631680 ps
CPU time 2.83 seconds
Started Apr 28 04:27:47 PM PDT 24
Finished Apr 28 04:27:50 PM PDT 24
Peak memory 215180 kb
Host smart-9dc3c9cd-7d4f-4673-8e92-31ce14550c50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763653096 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1763653096
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1931843274
Short name T800
Test name
Test status
Simulation time 44823896592 ps
CPU time 1229.02 seconds
Started Apr 28 04:27:39 PM PDT 24
Finished Apr 28 04:48:09 PM PDT 24
Peak memory 221608 kb
Host smart-7cad1b87-eb42-4896-91d8-8397761e1a42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931843274 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1931843274
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3847052354
Short name T382
Test name
Test status
Simulation time 29170717 ps
CPU time 1.37 seconds
Started Apr 28 04:28:36 PM PDT 24
Finished Apr 28 04:28:38 PM PDT 24
Peak memory 215548 kb
Host smart-6725c095-991d-4344-bdf7-8f9609e8335d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847052354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3847052354
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1135450074
Short name T658
Test name
Test status
Simulation time 13361432 ps
CPU time 0.9 seconds
Started Apr 28 04:28:40 PM PDT 24
Finished Apr 28 04:28:41 PM PDT 24
Peak memory 215152 kb
Host smart-b2f7e295-b98d-4a21-aa79-010c2de89383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135450074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1135450074
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3387498507
Short name T177
Test name
Test status
Simulation time 34301725 ps
CPU time 0.88 seconds
Started Apr 28 04:28:41 PM PDT 24
Finished Apr 28 04:28:42 PM PDT 24
Peak memory 216104 kb
Host smart-2e570cfd-64c1-45f9-ab93-877b54a893d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387498507 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3387498507
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2117056839
Short name T122
Test name
Test status
Simulation time 43529945 ps
CPU time 1.55 seconds
Started Apr 28 04:28:39 PM PDT 24
Finished Apr 28 04:28:41 PM PDT 24
Peak memory 219312 kb
Host smart-4dbad7d3-69ba-4488-9f6a-a618497caeb2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117056839 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2117056839
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1468297408
Short name T112
Test name
Test status
Simulation time 25535657 ps
CPU time 1.31 seconds
Started Apr 28 04:28:40 PM PDT 24
Finished Apr 28 04:28:41 PM PDT 24
Peak memory 232108 kb
Host smart-d2980a81-7142-4735-8219-8349c7d4eaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468297408 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1468297408
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.83479817
Short name T833
Test name
Test status
Simulation time 193140990 ps
CPU time 1.01 seconds
Started Apr 28 04:28:48 PM PDT 24
Finished Apr 28 04:28:50 PM PDT 24
Peak memory 216764 kb
Host smart-604d1b37-30d6-47a3-94f3-76e6d9a33386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83479817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.83479817
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1324882868
Short name T372
Test name
Test status
Simulation time 26695958 ps
CPU time 1.11 seconds
Started Apr 28 04:28:46 PM PDT 24
Finished Apr 28 04:28:48 PM PDT 24
Peak memory 223812 kb
Host smart-3ae9daee-24d4-440e-9e21-b8212da2d282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324882868 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1324882868
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2790204965
Short name T408
Test name
Test status
Simulation time 29670239 ps
CPU time 0.95 seconds
Started Apr 28 04:28:40 PM PDT 24
Finished Apr 28 04:28:41 PM PDT 24
Peak memory 215172 kb
Host smart-4fd0287f-1dde-4a44-b51c-035cdbfa52d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790204965 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2790204965
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.383463231
Short name T679
Test name
Test status
Simulation time 152747787 ps
CPU time 2.24 seconds
Started Apr 28 04:28:37 PM PDT 24
Finished Apr 28 04:28:40 PM PDT 24
Peak memory 216772 kb
Host smart-9f5c92f5-4bb6-4ca5-99c2-eca3fa6327dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383463231 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.383463231
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.234574582
Short name T268
Test name
Test status
Simulation time 18686592761 ps
CPU time 503.96 seconds
Started Apr 28 04:28:34 PM PDT 24
Finished Apr 28 04:36:58 PM PDT 24
Peak memory 217872 kb
Host smart-eb47adf6-5dfe-48bc-89fc-749dd8455093
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234574582 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.234574582
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.23007812
Short name T724
Test name
Test status
Simulation time 279320322 ps
CPU time 3.78 seconds
Started Apr 28 04:30:37 PM PDT 24
Finished Apr 28 04:30:42 PM PDT 24
Peak memory 218224 kb
Host smart-775e39b1-ac10-4c9a-baf5-a547e79641b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23007812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.23007812
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2208105021
Short name T376
Test name
Test status
Simulation time 63321383 ps
CPU time 1.12 seconds
Started Apr 28 04:30:36 PM PDT 24
Finished Apr 28 04:30:38 PM PDT 24
Peak memory 216800 kb
Host smart-aaa444fd-b1cd-4d51-8fc4-bf22e42bfcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208105021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2208105021
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2412101215
Short name T476
Test name
Test status
Simulation time 88022971 ps
CPU time 3.27 seconds
Started Apr 28 04:30:38 PM PDT 24
Finished Apr 28 04:30:43 PM PDT 24
Peak memory 215168 kb
Host smart-f75d5dcd-4ad1-4a05-8efc-401953f4e097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412101215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2412101215
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.657452530
Short name T369
Test name
Test status
Simulation time 244378844 ps
CPU time 3.24 seconds
Started Apr 28 04:30:36 PM PDT 24
Finished Apr 28 04:30:41 PM PDT 24
Peak memory 218224 kb
Host smart-3a7b46ab-6c51-4ec7-94db-04a2d15f45de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657452530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.657452530
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1162252270
Short name T455
Test name
Test status
Simulation time 42114074 ps
CPU time 1.43 seconds
Started Apr 28 04:30:41 PM PDT 24
Finished Apr 28 04:30:43 PM PDT 24
Peak memory 218172 kb
Host smart-d305c5d6-8f92-49a0-93a4-a703a2620408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162252270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1162252270
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3538831786
Short name T529
Test name
Test status
Simulation time 75274428 ps
CPU time 1.14 seconds
Started Apr 28 04:30:38 PM PDT 24
Finished Apr 28 04:30:41 PM PDT 24
Peak memory 217044 kb
Host smart-e06003cf-7d07-426b-a8fd-69a9cc399f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538831786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3538831786
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.546832793
Short name T590
Test name
Test status
Simulation time 57595751 ps
CPU time 1.25 seconds
Started Apr 28 04:30:39 PM PDT 24
Finished Apr 28 04:30:41 PM PDT 24
Peak memory 216948 kb
Host smart-bf5db065-d82e-419f-a784-2bc63fbefd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546832793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.546832793
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2207646356
Short name T569
Test name
Test status
Simulation time 44862743 ps
CPU time 1.15 seconds
Started Apr 28 04:30:41 PM PDT 24
Finished Apr 28 04:30:42 PM PDT 24
Peak memory 217140 kb
Host smart-25c63bbf-f737-4ea7-afc3-b16a0241de3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207646356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2207646356
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3475501610
Short name T70
Test name
Test status
Simulation time 34086334 ps
CPU time 1.4 seconds
Started Apr 28 04:30:37 PM PDT 24
Finished Apr 28 04:30:39 PM PDT 24
Peak memory 216876 kb
Host smart-ab128d36-426e-4f1b-bb3a-1745108423f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475501610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3475501610
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.875322612
Short name T765
Test name
Test status
Simulation time 63094176 ps
CPU time 1.2 seconds
Started Apr 28 04:30:40 PM PDT 24
Finished Apr 28 04:30:42 PM PDT 24
Peak memory 218712 kb
Host smart-9bcfd835-83fa-4e67-b334-f35a0a874393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875322612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.875322612
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3237963690
Short name T261
Test name
Test status
Simulation time 26523614 ps
CPU time 1.15 seconds
Started Apr 28 04:28:38 PM PDT 24
Finished Apr 28 04:28:40 PM PDT 24
Peak memory 215572 kb
Host smart-a8d32fbc-88a0-4ad5-8dc9-b0930eadae09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237963690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3237963690
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1195821591
Short name T716
Test name
Test status
Simulation time 22317746 ps
CPU time 0.91 seconds
Started Apr 28 04:28:52 PM PDT 24
Finished Apr 28 04:28:54 PM PDT 24
Peak memory 206520 kb
Host smart-7905cb99-0b2e-4340-aba8-2b543014461c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195821591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1195821591
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.116080950
Short name T594
Test name
Test status
Simulation time 32335095 ps
CPU time 1.24 seconds
Started Apr 28 04:28:52 PM PDT 24
Finished Apr 28 04:28:54 PM PDT 24
Peak memory 216688 kb
Host smart-f20e0caf-fd0d-4581-8abb-071703bc3da8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116080950 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.116080950
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3320060337
Short name T645
Test name
Test status
Simulation time 19852106 ps
CPU time 1.18 seconds
Started Apr 28 04:28:39 PM PDT 24
Finished Apr 28 04:28:40 PM PDT 24
Peak memory 232696 kb
Host smart-9bbc1fb9-11c8-4535-8522-145ec3ffa8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320060337 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3320060337
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.361216542
Short name T392
Test name
Test status
Simulation time 61593559 ps
CPU time 1.15 seconds
Started Apr 28 04:28:40 PM PDT 24
Finished Apr 28 04:28:42 PM PDT 24
Peak memory 219492 kb
Host smart-e44b01a3-c1e9-4730-bd92-fb850ef0da43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361216542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.361216542
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.518339281
Short name T826
Test name
Test status
Simulation time 24189533 ps
CPU time 1.01 seconds
Started Apr 28 04:28:39 PM PDT 24
Finished Apr 28 04:28:40 PM PDT 24
Peak memory 215372 kb
Host smart-9e3e46ba-2d71-4be2-b1ca-283278910c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518339281 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.518339281
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.369623958
Short name T204
Test name
Test status
Simulation time 16475448 ps
CPU time 1.04 seconds
Started Apr 28 04:28:38 PM PDT 24
Finished Apr 28 04:28:40 PM PDT 24
Peak memory 215176 kb
Host smart-88906ab9-0cca-4e41-abbe-ba421e0de4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369623958 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.369623958
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3249616344
Short name T563
Test name
Test status
Simulation time 483851145 ps
CPU time 3.05 seconds
Started Apr 28 04:28:40 PM PDT 24
Finished Apr 28 04:28:43 PM PDT 24
Peak memory 215176 kb
Host smart-b450ef04-f1af-498c-b309-c3cd4e717485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249616344 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3249616344
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2245265925
Short name T191
Test name
Test status
Simulation time 118820325740 ps
CPU time 2764.74 seconds
Started Apr 28 04:28:39 PM PDT 24
Finished Apr 28 05:14:44 PM PDT 24
Peak memory 229912 kb
Host smart-c76e64f2-a36e-4c56-ad16-5111e7c6586b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245265925 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2245265925
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1953993330
Short name T541
Test name
Test status
Simulation time 585265638 ps
CPU time 4.68 seconds
Started Apr 28 04:30:42 PM PDT 24
Finished Apr 28 04:30:47 PM PDT 24
Peak memory 219436 kb
Host smart-a0dc418e-0485-437c-80b2-f13db59c8bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953993330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1953993330
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3494654193
Short name T829
Test name
Test status
Simulation time 58667676 ps
CPU time 0.98 seconds
Started Apr 28 04:30:41 PM PDT 24
Finished Apr 28 04:30:43 PM PDT 24
Peak memory 216828 kb
Host smart-5550d9a3-8cc4-4f5b-888e-c4d24a8bb28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494654193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3494654193
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.292917940
Short name T519
Test name
Test status
Simulation time 54410715 ps
CPU time 1.31 seconds
Started Apr 28 04:30:42 PM PDT 24
Finished Apr 28 04:30:44 PM PDT 24
Peak memory 218576 kb
Host smart-40e510e7-08cc-46e3-9548-de8a4fc51754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292917940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.292917940
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1416037045
Short name T661
Test name
Test status
Simulation time 83312752 ps
CPU time 1.27 seconds
Started Apr 28 04:30:42 PM PDT 24
Finished Apr 28 04:30:44 PM PDT 24
Peak memory 218068 kb
Host smart-b2cfbef1-28dc-494d-8a1e-83f6fb840f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416037045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1416037045
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2519761960
Short name T360
Test name
Test status
Simulation time 46111441 ps
CPU time 2.03 seconds
Started Apr 28 04:30:42 PM PDT 24
Finished Apr 28 04:30:45 PM PDT 24
Peak memory 219548 kb
Host smart-9940407a-c81c-48d0-92ac-51a893714408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519761960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2519761960
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.4155570278
Short name T273
Test name
Test status
Simulation time 77426452 ps
CPU time 1.41 seconds
Started Apr 28 04:30:42 PM PDT 24
Finished Apr 28 04:30:44 PM PDT 24
Peak memory 218432 kb
Host smart-7a12997a-f1a4-488c-aaa1-af53e4b84872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155570278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.4155570278
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2928269255
Short name T640
Test name
Test status
Simulation time 44274099 ps
CPU time 1.92 seconds
Started Apr 28 04:30:52 PM PDT 24
Finished Apr 28 04:30:55 PM PDT 24
Peak memory 219612 kb
Host smart-6a36716d-2529-4d4e-9cbd-34eeef211ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928269255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2928269255
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.393511922
Short name T799
Test name
Test status
Simulation time 45517692 ps
CPU time 1.93 seconds
Started Apr 28 04:30:45 PM PDT 24
Finished Apr 28 04:30:47 PM PDT 24
Peak memory 218224 kb
Host smart-d04d7623-87c0-4005-b6fe-466d2ba99590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393511922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.393511922
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert_test.1225714784
Short name T842
Test name
Test status
Simulation time 25134777 ps
CPU time 0.97 seconds
Started Apr 28 04:28:48 PM PDT 24
Finished Apr 28 04:28:50 PM PDT 24
Peak memory 215100 kb
Host smart-2f480697-ed46-4a8a-bec7-3877eac5e0b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225714784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1225714784
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1757637713
Short name T87
Test name
Test status
Simulation time 139780898 ps
CPU time 0.99 seconds
Started Apr 28 04:28:46 PM PDT 24
Finished Apr 28 04:28:48 PM PDT 24
Peak memory 215756 kb
Host smart-ff9e22b9-dd7e-46f6-86d6-740a5720c473
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757637713 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1757637713
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.665797115
Short name T169
Test name
Test status
Simulation time 81969474 ps
CPU time 1.12 seconds
Started Apr 28 04:28:46 PM PDT 24
Finished Apr 28 04:28:47 PM PDT 24
Peak memory 216780 kb
Host smart-d3e8df6c-5706-4bab-bb90-4f3aa6f5ad0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665797115 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_di
sable_auto_req_mode.665797115
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1634714418
Short name T791
Test name
Test status
Simulation time 33537631 ps
CPU time 1.32 seconds
Started Apr 28 04:28:44 PM PDT 24
Finished Apr 28 04:28:47 PM PDT 24
Peak memory 219424 kb
Host smart-9aa51e6f-6d75-4cde-a461-eca87b5592f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634714418 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1634714418
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2395813881
Short name T715
Test name
Test status
Simulation time 37228536 ps
CPU time 1.6 seconds
Started Apr 28 04:28:44 PM PDT 24
Finished Apr 28 04:28:46 PM PDT 24
Peak memory 216976 kb
Host smart-b2d24a8c-04a9-4518-a261-2ed56561b94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395813881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2395813881
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2430093431
Short name T365
Test name
Test status
Simulation time 31302727 ps
CPU time 0.94 seconds
Started Apr 28 04:28:46 PM PDT 24
Finished Apr 28 04:28:47 PM PDT 24
Peak memory 215408 kb
Host smart-8c4c30e2-4cdf-44c2-9f2d-f14e6b8958c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430093431 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2430093431
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3634750519
Short name T315
Test name
Test status
Simulation time 28915118 ps
CPU time 0.92 seconds
Started Apr 28 04:28:46 PM PDT 24
Finished Apr 28 04:28:47 PM PDT 24
Peak memory 215192 kb
Host smart-c8a45e45-0d34-4b7b-bcc2-4d0b8090e5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634750519 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3634750519
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.4250877665
Short name T602
Test name
Test status
Simulation time 88085577 ps
CPU time 1.64 seconds
Started Apr 28 04:28:44 PM PDT 24
Finished Apr 28 04:28:47 PM PDT 24
Peak memory 216836 kb
Host smart-b8b534b0-90a4-4554-8de7-54fb4cfed8e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250877665 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.4250877665
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2618761995
Short name T576
Test name
Test status
Simulation time 343911166862 ps
CPU time 2460.03 seconds
Started Apr 28 04:28:52 PM PDT 24
Finished Apr 28 05:09:53 PM PDT 24
Peak memory 230876 kb
Host smart-26a0440e-4304-4c63-aae3-0ca26de03e85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618761995 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2618761995
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1921048560
Short name T295
Test name
Test status
Simulation time 55140655 ps
CPU time 1.82 seconds
Started Apr 28 04:30:44 PM PDT 24
Finished Apr 28 04:30:46 PM PDT 24
Peak memory 219520 kb
Host smart-9af99a65-c47c-43d6-9089-8e0402887928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921048560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1921048560
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1795289621
Short name T350
Test name
Test status
Simulation time 101702836 ps
CPU time 1.72 seconds
Started Apr 28 04:30:42 PM PDT 24
Finished Apr 28 04:30:45 PM PDT 24
Peak memory 218348 kb
Host smart-26fd6a32-6601-486a-b29f-9a30a89f72ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795289621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1795289621
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.279641993
Short name T480
Test name
Test status
Simulation time 69466464 ps
CPU time 1.79 seconds
Started Apr 28 04:30:44 PM PDT 24
Finished Apr 28 04:30:46 PM PDT 24
Peak memory 218100 kb
Host smart-4ef0c368-3eac-48c2-a611-9ea6fbb3f59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279641993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.279641993
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3667284080
Short name T308
Test name
Test status
Simulation time 73984670 ps
CPU time 1.09 seconds
Started Apr 28 04:30:51 PM PDT 24
Finished Apr 28 04:30:53 PM PDT 24
Peak memory 216836 kb
Host smart-dc62fa61-4263-400d-b486-d2ae90dd0043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667284080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3667284080
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3079435382
Short name T201
Test name
Test status
Simulation time 45952130 ps
CPU time 1.2 seconds
Started Apr 28 04:30:42 PM PDT 24
Finished Apr 28 04:30:44 PM PDT 24
Peak memory 218308 kb
Host smart-24bf6e4c-6186-4df9-b41e-45c326089fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079435382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3079435382
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3174592069
Short name T9
Test name
Test status
Simulation time 175568118 ps
CPU time 2.66 seconds
Started Apr 28 04:30:50 PM PDT 24
Finished Apr 28 04:30:53 PM PDT 24
Peak memory 219584 kb
Host smart-7ab427a3-2054-4c70-895e-d8018c1f0c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174592069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3174592069
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2196173616
Short name T291
Test name
Test status
Simulation time 28457919 ps
CPU time 1.34 seconds
Started Apr 28 04:30:45 PM PDT 24
Finished Apr 28 04:30:47 PM PDT 24
Peak memory 219156 kb
Host smart-4b0909df-5a99-4da7-b54a-092feaea3af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196173616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2196173616
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2477787498
Short name T699
Test name
Test status
Simulation time 94045233 ps
CPU time 1.17 seconds
Started Apr 28 04:30:44 PM PDT 24
Finished Apr 28 04:30:45 PM PDT 24
Peak memory 217008 kb
Host smart-b44b9624-54b8-4159-ae1f-cbd2598dd34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477787498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2477787498
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3956072237
Short name T63
Test name
Test status
Simulation time 35844008 ps
CPU time 1.42 seconds
Started Apr 28 04:30:50 PM PDT 24
Finished Apr 28 04:30:52 PM PDT 24
Peak memory 216824 kb
Host smart-4925b955-39f2-4903-b0da-880c5beae8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956072237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3956072237
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1431697802
Short name T424
Test name
Test status
Simulation time 56250605 ps
CPU time 1.35 seconds
Started Apr 28 04:30:46 PM PDT 24
Finished Apr 28 04:30:48 PM PDT 24
Peak memory 217004 kb
Host smart-8c87e2d4-b944-4021-8f3e-412ad303177d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431697802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1431697802
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2379167888
Short name T802
Test name
Test status
Simulation time 25177552 ps
CPU time 1.25 seconds
Started Apr 28 04:28:52 PM PDT 24
Finished Apr 28 04:28:54 PM PDT 24
Peak memory 215600 kb
Host smart-525140e2-0846-4607-aa41-e686594a8092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379167888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2379167888
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2001126594
Short name T545
Test name
Test status
Simulation time 37296726 ps
CPU time 0.86 seconds
Started Apr 28 04:28:42 PM PDT 24
Finished Apr 28 04:28:44 PM PDT 24
Peak memory 206260 kb
Host smart-0fd3d47e-4255-45e0-b248-c2cd63c4aca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001126594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2001126594
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1303376723
Short name T758
Test name
Test status
Simulation time 37351365 ps
CPU time 0.94 seconds
Started Apr 28 04:28:44 PM PDT 24
Finished Apr 28 04:28:46 PM PDT 24
Peak memory 216112 kb
Host smart-c4303fe7-7f99-4147-876b-8a46d3952f77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303376723 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1303376723
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1695281961
Short name T178
Test name
Test status
Simulation time 239818308 ps
CPU time 1.12 seconds
Started Apr 28 04:28:45 PM PDT 24
Finished Apr 28 04:28:47 PM PDT 24
Peak memory 219112 kb
Host smart-0253fafe-d405-47bc-a473-b1d44144b8f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695281961 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1695281961
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1468888395
Short name T54
Test name
Test status
Simulation time 27436357 ps
CPU time 1.06 seconds
Started Apr 28 04:28:46 PM PDT 24
Finished Apr 28 04:28:48 PM PDT 24
Peak memory 223748 kb
Host smart-a7694537-dfa0-420c-a936-0655ab786f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468888395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1468888395
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2936117453
Short name T416
Test name
Test status
Simulation time 42813553 ps
CPU time 1.48 seconds
Started Apr 28 04:28:44 PM PDT 24
Finished Apr 28 04:28:47 PM PDT 24
Peak memory 218264 kb
Host smart-dbc77a5d-43de-4aa6-b918-b6e58d6933be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936117453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2936117453
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.877760063
Short name T734
Test name
Test status
Simulation time 43280094 ps
CPU time 0.95 seconds
Started Apr 28 04:28:46 PM PDT 24
Finished Apr 28 04:28:48 PM PDT 24
Peak memory 215132 kb
Host smart-548fadc5-7377-4179-ba46-2c6def343b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877760063 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.877760063
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.974740306
Short name T58
Test name
Test status
Simulation time 46446614 ps
CPU time 0.94 seconds
Started Apr 28 04:28:44 PM PDT 24
Finished Apr 28 04:28:46 PM PDT 24
Peak memory 215188 kb
Host smart-d9d38b7f-8609-49e7-8451-4d7ee50d642c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974740306 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.974740306
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2041592323
Short name T209
Test name
Test status
Simulation time 814226930 ps
CPU time 5.06 seconds
Started Apr 28 04:28:44 PM PDT 24
Finished Apr 28 04:28:49 PM PDT 24
Peak memory 216840 kb
Host smart-e3cc916b-18b8-4001-89f4-95e9eecda1b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041592323 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2041592323
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3405825381
Short name T741
Test name
Test status
Simulation time 77871618029 ps
CPU time 1847.1 seconds
Started Apr 28 04:28:45 PM PDT 24
Finished Apr 28 04:59:32 PM PDT 24
Peak memory 224916 kb
Host smart-067cdc89-a1e0-460e-9621-6ee5c42a4ac7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405825381 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3405825381
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.478207917
Short name T433
Test name
Test status
Simulation time 42763545 ps
CPU time 1.28 seconds
Started Apr 28 04:30:42 PM PDT 24
Finished Apr 28 04:30:44 PM PDT 24
Peak memory 215156 kb
Host smart-80c0eeb6-3ae4-4409-9635-8f0188ce6325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478207917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.478207917
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2234804350
Short name T483
Test name
Test status
Simulation time 47662093 ps
CPU time 1.47 seconds
Started Apr 28 04:30:41 PM PDT 24
Finished Apr 28 04:30:44 PM PDT 24
Peak memory 217864 kb
Host smart-b26b7c36-4e8b-4a9e-a30f-8d3d8faf893e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234804350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2234804350
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1812405888
Short name T539
Test name
Test status
Simulation time 64162926 ps
CPU time 1.37 seconds
Started Apr 28 04:30:47 PM PDT 24
Finished Apr 28 04:30:49 PM PDT 24
Peak memory 217004 kb
Host smart-5c85926f-99f6-45b8-bb5d-6501520943f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812405888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1812405888
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2716916712
Short name T275
Test name
Test status
Simulation time 56324290 ps
CPU time 1.57 seconds
Started Apr 28 04:30:47 PM PDT 24
Finished Apr 28 04:30:49 PM PDT 24
Peak memory 218356 kb
Host smart-8828b7ed-fa7a-45fa-8cd1-a44d06a3ddf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716916712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2716916712
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.917947271
Short name T500
Test name
Test status
Simulation time 79612654 ps
CPU time 1.26 seconds
Started Apr 28 04:30:48 PM PDT 24
Finished Apr 28 04:30:49 PM PDT 24
Peak memory 218240 kb
Host smart-ef605586-25fb-4864-bc64-14b0fa641974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917947271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.917947271
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1096372957
Short name T75
Test name
Test status
Simulation time 121780316 ps
CPU time 1.49 seconds
Started Apr 28 04:30:47 PM PDT 24
Finished Apr 28 04:30:48 PM PDT 24
Peak memory 218240 kb
Host smart-8e255464-78bd-4653-8f52-ed6964921cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096372957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1096372957
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3907695371
Short name T401
Test name
Test status
Simulation time 37331771 ps
CPU time 1.64 seconds
Started Apr 28 04:30:45 PM PDT 24
Finished Apr 28 04:30:47 PM PDT 24
Peak memory 217840 kb
Host smart-975909d1-c38f-4f5a-b2aa-8fecba76daf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907695371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3907695371
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2128736416
Short name T292
Test name
Test status
Simulation time 55480583 ps
CPU time 1.47 seconds
Started Apr 28 04:30:46 PM PDT 24
Finished Apr 28 04:30:48 PM PDT 24
Peak memory 219540 kb
Host smart-d38f0474-9e52-4aa2-9298-ac1276d7d0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128736416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2128736416
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3283780818
Short name T44
Test name
Test status
Simulation time 66475715 ps
CPU time 1.31 seconds
Started Apr 28 04:30:47 PM PDT 24
Finished Apr 28 04:30:49 PM PDT 24
Peak memory 217016 kb
Host smart-7e697d51-7e82-4c88-8968-65f6544e6021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283780818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3283780818
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert_test.607333463
Short name T339
Test name
Test status
Simulation time 28046536 ps
CPU time 0.93 seconds
Started Apr 28 04:28:48 PM PDT 24
Finished Apr 28 04:28:50 PM PDT 24
Peak memory 214720 kb
Host smart-afd1ffcf-ab61-46e6-a773-6a77b0520930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607333463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.607333463
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2506756693
Short name T512
Test name
Test status
Simulation time 12156492 ps
CPU time 0.95 seconds
Started Apr 28 04:28:48 PM PDT 24
Finished Apr 28 04:28:49 PM PDT 24
Peak memory 215448 kb
Host smart-a4164025-8b33-4541-bf7f-8f76dadbc6ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506756693 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2506756693
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2470249135
Short name T110
Test name
Test status
Simulation time 23195135 ps
CPU time 1.04 seconds
Started Apr 28 04:28:50 PM PDT 24
Finished Apr 28 04:28:52 PM PDT 24
Peak memory 218200 kb
Host smart-67bbaf8c-60bb-458d-93fd-b3f23d1b429f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470249135 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2470249135
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1625134478
Short name T126
Test name
Test status
Simulation time 28213190 ps
CPU time 1 seconds
Started Apr 28 04:28:52 PM PDT 24
Finished Apr 28 04:28:55 PM PDT 24
Peak memory 223768 kb
Host smart-98de92f5-788d-4ffe-9290-fd0d0f552623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625134478 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1625134478
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_intr.2156583304
Short name T29
Test name
Test status
Simulation time 32787164 ps
CPU time 0.91 seconds
Started Apr 28 04:28:50 PM PDT 24
Finished Apr 28 04:28:52 PM PDT 24
Peak memory 215548 kb
Host smart-b32d1a94-2fe7-4509-abc3-7f85b04c06e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156583304 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2156583304
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3108474070
Short name T517
Test name
Test status
Simulation time 100629999 ps
CPU time 0.95 seconds
Started Apr 28 04:28:46 PM PDT 24
Finished Apr 28 04:28:48 PM PDT 24
Peak memory 215168 kb
Host smart-0f04295b-5b89-4ac8-8692-72589cff3c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108474070 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3108474070
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1488123901
Short name T599
Test name
Test status
Simulation time 715905662 ps
CPU time 3.26 seconds
Started Apr 28 04:28:52 PM PDT 24
Finished Apr 28 04:28:57 PM PDT 24
Peak memory 215172 kb
Host smart-00c52ac0-6028-4de6-9c6a-74d04fe9114a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488123901 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1488123901
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2547383235
Short name T784
Test name
Test status
Simulation time 140317631599 ps
CPU time 796.88 seconds
Started Apr 28 04:28:50 PM PDT 24
Finished Apr 28 04:42:08 PM PDT 24
Peak memory 220948 kb
Host smart-15f37881-cbe4-4be4-aa34-fb55a4c18985
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547383235 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2547383235
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.111309567
Short name T427
Test name
Test status
Simulation time 74495239 ps
CPU time 1.1 seconds
Started Apr 28 04:30:51 PM PDT 24
Finished Apr 28 04:30:53 PM PDT 24
Peak memory 215228 kb
Host smart-d083ffb0-e00d-4a1e-984a-61c98d7f9246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111309567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.111309567
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1560526157
Short name T523
Test name
Test status
Simulation time 38263989 ps
CPU time 1.43 seconds
Started Apr 28 04:30:47 PM PDT 24
Finished Apr 28 04:30:49 PM PDT 24
Peak memory 217936 kb
Host smart-d6e8908d-e036-4221-bcb9-0526c2a1f3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560526157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1560526157
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2344359701
Short name T367
Test name
Test status
Simulation time 54591762 ps
CPU time 1.87 seconds
Started Apr 28 04:30:48 PM PDT 24
Finished Apr 28 04:30:50 PM PDT 24
Peak memory 218192 kb
Host smart-0d9a40aa-4849-465b-b094-8c2d35f16c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344359701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2344359701
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1758176959
Short name T320
Test name
Test status
Simulation time 51660977 ps
CPU time 0.95 seconds
Started Apr 28 04:30:46 PM PDT 24
Finished Apr 28 04:30:48 PM PDT 24
Peak memory 217020 kb
Host smart-d3dd952f-faca-49d8-9fd4-4b4199bb6b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758176959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1758176959
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.862636058
Short name T501
Test name
Test status
Simulation time 66957513 ps
CPU time 1.15 seconds
Started Apr 28 04:30:48 PM PDT 24
Finished Apr 28 04:30:50 PM PDT 24
Peak memory 216924 kb
Host smart-fe8ce557-5da8-4d01-980c-d7fe22be143d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862636058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.862636058
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.891821699
Short name T652
Test name
Test status
Simulation time 88519584 ps
CPU time 1.25 seconds
Started Apr 28 04:30:48 PM PDT 24
Finished Apr 28 04:30:50 PM PDT 24
Peak memory 216912 kb
Host smart-cad33726-986b-465e-8b2f-ad49da1346b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891821699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.891821699
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.4038717528
Short name T670
Test name
Test status
Simulation time 41046487 ps
CPU time 1.44 seconds
Started Apr 28 04:30:48 PM PDT 24
Finished Apr 28 04:30:50 PM PDT 24
Peak memory 216780 kb
Host smart-30f4ba3d-4a6b-492e-b5a9-bd23931f6f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038717528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.4038717528
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2944907168
Short name T815
Test name
Test status
Simulation time 285636109 ps
CPU time 1.98 seconds
Started Apr 28 04:30:47 PM PDT 24
Finished Apr 28 04:30:50 PM PDT 24
Peak memory 218552 kb
Host smart-da617d73-7d5e-4571-b48e-f657befceb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944907168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2944907168
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1845451737
Short name T82
Test name
Test status
Simulation time 133941331 ps
CPU time 1.63 seconds
Started Apr 28 04:30:47 PM PDT 24
Finished Apr 28 04:30:50 PM PDT 24
Peak memory 219172 kb
Host smart-8b31ab36-8871-4208-b76e-4b9fd39ffd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845451737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1845451737
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.493990759
Short name T633
Test name
Test status
Simulation time 53682113 ps
CPU time 1.24 seconds
Started Apr 28 04:28:47 PM PDT 24
Finished Apr 28 04:28:49 PM PDT 24
Peak memory 215536 kb
Host smart-57b183b6-8dbb-473e-bf38-84eb34618044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493990759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.493990759
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_disable.1087780892
Short name T737
Test name
Test status
Simulation time 22288246 ps
CPU time 0.88 seconds
Started Apr 28 04:28:52 PM PDT 24
Finished Apr 28 04:28:54 PM PDT 24
Peak memory 215260 kb
Host smart-5c387d51-a792-471e-957a-d6cab929b457
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087780892 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1087780892
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.921839907
Short name T657
Test name
Test status
Simulation time 101506489 ps
CPU time 1.29 seconds
Started Apr 28 04:28:53 PM PDT 24
Finished Apr 28 04:28:56 PM PDT 24
Peak memory 216860 kb
Host smart-218b261f-bc4b-4db0-9c49-56ad2fe8220f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921839907 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.921839907
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.11156825
Short name T573
Test name
Test status
Simulation time 19213858 ps
CPU time 1.11 seconds
Started Apr 28 04:28:51 PM PDT 24
Finished Apr 28 04:28:53 PM PDT 24
Peak memory 218308 kb
Host smart-58e99574-6598-4e60-91c4-e67c3c25f47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11156825 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.11156825
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1846771898
Short name T378
Test name
Test status
Simulation time 62845311 ps
CPU time 1.06 seconds
Started Apr 28 04:28:49 PM PDT 24
Finished Apr 28 04:28:50 PM PDT 24
Peak memory 216836 kb
Host smart-98f746bc-1ccb-400d-a641-5b777cef7aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846771898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1846771898
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.717177297
Short name T605
Test name
Test status
Simulation time 51655387 ps
CPU time 0.8 seconds
Started Apr 28 04:28:47 PM PDT 24
Finished Apr 28 04:28:48 PM PDT 24
Peak memory 215464 kb
Host smart-52c91e76-2209-4d1a-a291-5d913580fadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717177297 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.717177297
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2377781200
Short name T710
Test name
Test status
Simulation time 19898699 ps
CPU time 1.03 seconds
Started Apr 28 04:28:49 PM PDT 24
Finished Apr 28 04:28:51 PM PDT 24
Peak memory 215188 kb
Host smart-1f0f1964-59ff-43b5-a6e5-e211cf843c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377781200 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2377781200
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2630522464
Short name T203
Test name
Test status
Simulation time 146659441 ps
CPU time 2.54 seconds
Started Apr 28 04:28:48 PM PDT 24
Finished Apr 28 04:28:52 PM PDT 24
Peak memory 215152 kb
Host smart-837a3710-3905-4525-95ea-352d813fe0d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630522464 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2630522464
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.162051887
Short name T412
Test name
Test status
Simulation time 50832931864 ps
CPU time 609.44 seconds
Started Apr 28 04:28:49 PM PDT 24
Finished Apr 28 04:38:59 PM PDT 24
Peak memory 219028 kb
Host smart-2cec088c-d8b9-494e-9753-1dfbede40350
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162051887 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.162051887
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1926780161
Short name T816
Test name
Test status
Simulation time 300310803 ps
CPU time 1.19 seconds
Started Apr 28 04:30:56 PM PDT 24
Finished Apr 28 04:30:58 PM PDT 24
Peak memory 216896 kb
Host smart-bce88163-04e4-4ff4-9fad-5f44e86c4cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926780161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1926780161
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2523206383
Short name T294
Test name
Test status
Simulation time 30027094 ps
CPU time 1.35 seconds
Started Apr 28 04:30:48 PM PDT 24
Finished Apr 28 04:30:50 PM PDT 24
Peak memory 219140 kb
Host smart-119296e2-ed8d-4947-aa4e-590f4dc17afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523206383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2523206383
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.554608970
Short name T747
Test name
Test status
Simulation time 36834565 ps
CPU time 1.49 seconds
Started Apr 28 04:30:51 PM PDT 24
Finished Apr 28 04:30:53 PM PDT 24
Peak memory 218128 kb
Host smart-3958895f-ffa1-4115-b516-a8a97befed3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554608970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.554608970
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.222932616
Short name T516
Test name
Test status
Simulation time 25303191 ps
CPU time 1.31 seconds
Started Apr 28 04:30:51 PM PDT 24
Finished Apr 28 04:30:53 PM PDT 24
Peak memory 218104 kb
Host smart-8f9bde1f-9314-4a18-8717-f61d92055afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222932616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.222932616
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3707303884
Short name T722
Test name
Test status
Simulation time 59119052 ps
CPU time 1.35 seconds
Started Apr 28 04:30:54 PM PDT 24
Finished Apr 28 04:30:56 PM PDT 24
Peak memory 218164 kb
Host smart-96060f5a-c390-48b1-aedc-175eecb68b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707303884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3707303884
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2581833828
Short name T521
Test name
Test status
Simulation time 33811108 ps
CPU time 1.46 seconds
Started Apr 28 04:30:51 PM PDT 24
Finished Apr 28 04:30:53 PM PDT 24
Peak memory 218256 kb
Host smart-a4b36221-0356-4edb-929e-23729beab947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581833828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2581833828
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1660752188
Short name T698
Test name
Test status
Simulation time 508025935 ps
CPU time 3.85 seconds
Started Apr 28 04:30:53 PM PDT 24
Finished Apr 28 04:30:57 PM PDT 24
Peak memory 219964 kb
Host smart-35c8029f-ed9a-4005-998e-43157d76b422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660752188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1660752188
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.315311732
Short name T487
Test name
Test status
Simulation time 41486928 ps
CPU time 1.44 seconds
Started Apr 28 04:30:54 PM PDT 24
Finished Apr 28 04:30:56 PM PDT 24
Peak memory 218508 kb
Host smart-288dac96-da60-44fa-b40b-208bb9697a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315311732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.315311732
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3055438448
Short name T343
Test name
Test status
Simulation time 53200694 ps
CPU time 1.09 seconds
Started Apr 28 04:30:52 PM PDT 24
Finished Apr 28 04:30:53 PM PDT 24
Peak memory 216960 kb
Host smart-8e4e184a-7c18-4582-aa47-048e24fb39d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055438448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3055438448
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.765414841
Short name T686
Test name
Test status
Simulation time 64972477 ps
CPU time 1.39 seconds
Started Apr 28 04:30:53 PM PDT 24
Finished Apr 28 04:30:55 PM PDT 24
Peak memory 218680 kb
Host smart-1a7c6f54-7dfb-4362-948f-bf1741f92c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765414841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.765414841
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2006825342
Short name T526
Test name
Test status
Simulation time 28932953 ps
CPU time 1.19 seconds
Started Apr 28 04:28:53 PM PDT 24
Finished Apr 28 04:28:55 PM PDT 24
Peak memory 215524 kb
Host smart-cb71e00c-a209-4677-b569-13f9a7adf306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006825342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2006825342
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2662705254
Short name T550
Test name
Test status
Simulation time 33080290 ps
CPU time 1 seconds
Started Apr 28 04:28:55 PM PDT 24
Finished Apr 28 04:28:56 PM PDT 24
Peak memory 214860 kb
Host smart-09328ffe-0df5-4258-8030-ca3ad8be1000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662705254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2662705254
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2884281246
Short name T163
Test name
Test status
Simulation time 49209818 ps
CPU time 0.86 seconds
Started Apr 28 04:28:54 PM PDT 24
Finished Apr 28 04:28:55 PM PDT 24
Peak memory 216044 kb
Host smart-3c1bdbb8-9c1d-444e-bd4b-a075d5ed862e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884281246 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2884281246
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2316085732
Short name T100
Test name
Test status
Simulation time 29737112 ps
CPU time 1.2 seconds
Started Apr 28 04:28:55 PM PDT 24
Finished Apr 28 04:28:57 PM PDT 24
Peak memory 216724 kb
Host smart-62cc8710-bf2e-4829-bf02-079ecfee975e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316085732 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2316085732
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3777378704
Short name T351
Test name
Test status
Simulation time 33206677 ps
CPU time 0.93 seconds
Started Apr 28 04:28:54 PM PDT 24
Finished Apr 28 04:28:55 PM PDT 24
Peak memory 218300 kb
Host smart-c17cba8f-622e-4c14-9016-69dcb11f9396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777378704 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3777378704
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2320960173
Short name T439
Test name
Test status
Simulation time 115246826 ps
CPU time 1.67 seconds
Started Apr 28 04:28:51 PM PDT 24
Finished Apr 28 04:28:54 PM PDT 24
Peak memory 218320 kb
Host smart-59c5f1c7-2eea-40c4-9d59-16bec4d2eeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320960173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2320960173
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2897728820
Short name T571
Test name
Test status
Simulation time 26973442 ps
CPU time 1.11 seconds
Started Apr 28 04:28:53 PM PDT 24
Finished Apr 28 04:28:55 PM PDT 24
Peak memory 223876 kb
Host smart-418855b6-a901-4908-9e4b-782402a648a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897728820 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2897728820
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3437327644
Short name T604
Test name
Test status
Simulation time 19018546 ps
CPU time 1.08 seconds
Started Apr 28 04:28:53 PM PDT 24
Finished Apr 28 04:28:55 PM PDT 24
Peak memory 215064 kb
Host smart-4d826e2f-170f-4f2e-9bcb-37b12dd51e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437327644 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3437327644
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2041159765
Short name T210
Test name
Test status
Simulation time 689921517 ps
CPU time 4.09 seconds
Started Apr 28 04:28:53 PM PDT 24
Finished Apr 28 04:28:58 PM PDT 24
Peak memory 215148 kb
Host smart-496c952d-ea88-4f2a-93ae-3f8c35c37df6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041159765 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2041159765
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3254015174
Short name T36
Test name
Test status
Simulation time 19361081436 ps
CPU time 516.61 seconds
Started Apr 28 04:28:52 PM PDT 24
Finished Apr 28 04:37:30 PM PDT 24
Peak memory 217692 kb
Host smart-f60ade96-6f64-4267-8c28-5b6d66a21010
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254015174 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3254015174
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.710200707
Short name T443
Test name
Test status
Simulation time 71355203 ps
CPU time 1.19 seconds
Started Apr 28 04:30:52 PM PDT 24
Finished Apr 28 04:30:54 PM PDT 24
Peak memory 217084 kb
Host smart-a343aea9-ad0f-4f88-bd6b-95b80876825e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710200707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.710200707
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3088320195
Short name T731
Test name
Test status
Simulation time 63521211 ps
CPU time 1.75 seconds
Started Apr 28 04:30:52 PM PDT 24
Finished Apr 28 04:30:54 PM PDT 24
Peak memory 219704 kb
Host smart-2cfc9bde-f8ae-48b7-8cc7-d2bf654fbd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088320195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3088320195
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3663753108
Short name T531
Test name
Test status
Simulation time 55450409 ps
CPU time 1.3 seconds
Started Apr 28 04:30:51 PM PDT 24
Finished Apr 28 04:30:53 PM PDT 24
Peak memory 217084 kb
Host smart-ce777f07-e2ee-4f43-84ed-7f8b6d6927f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663753108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3663753108
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1953633852
Short name T65
Test name
Test status
Simulation time 79642669 ps
CPU time 1.09 seconds
Started Apr 28 04:30:59 PM PDT 24
Finished Apr 28 04:31:01 PM PDT 24
Peak memory 216848 kb
Host smart-8210f0bc-345b-4532-87ca-a9ba855d280f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953633852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1953633852
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3887615992
Short name T463
Test name
Test status
Simulation time 41575525 ps
CPU time 1.61 seconds
Started Apr 28 04:30:55 PM PDT 24
Finished Apr 28 04:30:57 PM PDT 24
Peak memory 217072 kb
Host smart-f7755845-8885-49d4-a0bc-3fe5c36ea2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887615992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3887615992
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.1114361524
Short name T318
Test name
Test status
Simulation time 168381860 ps
CPU time 1.51 seconds
Started Apr 28 04:30:55 PM PDT 24
Finished Apr 28 04:30:57 PM PDT 24
Peak memory 218484 kb
Host smart-bc2ce0db-d1fd-40e3-8a23-702bd92cf147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114361524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1114361524
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3433259361
Short name T756
Test name
Test status
Simulation time 36837103 ps
CPU time 1.6 seconds
Started Apr 28 04:30:56 PM PDT 24
Finished Apr 28 04:30:58 PM PDT 24
Peak memory 218032 kb
Host smart-4833d3d8-3a0a-40f1-bc33-d9e0239510c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433259361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3433259361
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.590156540
Short name T578
Test name
Test status
Simulation time 114371093 ps
CPU time 1.31 seconds
Started Apr 28 04:30:56 PM PDT 24
Finished Apr 28 04:30:58 PM PDT 24
Peak memory 217004 kb
Host smart-51877eaf-b0eb-47b5-adca-392c4798bd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590156540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.590156540
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2926784080
Short name T381
Test name
Test status
Simulation time 398275548 ps
CPU time 3.7 seconds
Started Apr 28 04:30:55 PM PDT 24
Finished Apr 28 04:30:59 PM PDT 24
Peak memory 218316 kb
Host smart-d99a893f-fd1c-4705-afd1-f22a8a08fc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926784080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2926784080
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2605243629
Short name T796
Test name
Test status
Simulation time 138684406 ps
CPU time 1.47 seconds
Started Apr 28 04:31:00 PM PDT 24
Finished Apr 28 04:31:02 PM PDT 24
Peak memory 219604 kb
Host smart-ad5e35c3-3714-494a-8262-2e55752a35b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605243629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2605243629
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3531958658
Short name T262
Test name
Test status
Simulation time 33348596 ps
CPU time 1.27 seconds
Started Apr 28 04:29:01 PM PDT 24
Finished Apr 28 04:29:02 PM PDT 24
Peak memory 215560 kb
Host smart-c8f72c52-e0cf-402c-9934-927104a328cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531958658 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3531958658
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2633900338
Short name T437
Test name
Test status
Simulation time 46318070 ps
CPU time 0.93 seconds
Started Apr 28 04:29:00 PM PDT 24
Finished Apr 28 04:29:01 PM PDT 24
Peak memory 214792 kb
Host smart-986270a2-aec3-4c39-b016-83971fb5a827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633900338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2633900338
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.968911677
Short name T180
Test name
Test status
Simulation time 36290571 ps
CPU time 0.86 seconds
Started Apr 28 04:28:55 PM PDT 24
Finished Apr 28 04:28:57 PM PDT 24
Peak memory 215244 kb
Host smart-99e9cc5f-7fda-45c6-96a5-e4d856ff9e93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968911677 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.968911677
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2996644168
Short name T188
Test name
Test status
Simulation time 69951842 ps
CPU time 1.07 seconds
Started Apr 28 04:28:56 PM PDT 24
Finished Apr 28 04:28:57 PM PDT 24
Peak memory 219360 kb
Host smart-d75612de-fa88-4667-878c-d6a6d5ecf33b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996644168 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2996644168
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2447477275
Short name T684
Test name
Test status
Simulation time 22739457 ps
CPU time 1.32 seconds
Started Apr 28 04:28:56 PM PDT 24
Finished Apr 28 04:28:58 PM PDT 24
Peak memory 223896 kb
Host smart-7e2c6dfe-e3d5-4320-b6f3-589361f20dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447477275 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2447477275
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.6644930
Short name T283
Test name
Test status
Simulation time 27880305 ps
CPU time 1.31 seconds
Started Apr 28 04:28:53 PM PDT 24
Finished Apr 28 04:28:56 PM PDT 24
Peak memory 219036 kb
Host smart-42b1da88-b32c-4d75-af66-93cefb5eb742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6644930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.6644930
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.757734139
Short name T668
Test name
Test status
Simulation time 41931942 ps
CPU time 0.85 seconds
Started Apr 28 04:28:56 PM PDT 24
Finished Apr 28 04:28:57 PM PDT 24
Peak memory 215552 kb
Host smart-6af4c625-3e42-4c7e-8780-e2e039078246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757734139 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.757734139
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1788779836
Short name T600
Test name
Test status
Simulation time 40466781 ps
CPU time 0.92 seconds
Started Apr 28 04:28:56 PM PDT 24
Finished Apr 28 04:28:57 PM PDT 24
Peak memory 215168 kb
Host smart-9f9c5b9a-4e58-4e53-ac7b-205230cfa953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788779836 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1788779836
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3006324223
Short name T729
Test name
Test status
Simulation time 524038740 ps
CPU time 3.16 seconds
Started Apr 28 04:28:56 PM PDT 24
Finished Apr 28 04:29:00 PM PDT 24
Peak memory 216968 kb
Host smart-864871be-9fde-4514-b5fd-47edee0fa0c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006324223 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3006324223
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2859855663
Short name T274
Test name
Test status
Simulation time 178971709382 ps
CPU time 1669.46 seconds
Started Apr 28 04:28:58 PM PDT 24
Finished Apr 28 04:56:48 PM PDT 24
Peak memory 224156 kb
Host smart-97278997-c9ab-4b30-9dcf-0f0aeb5fdd3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859855663 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2859855663
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1107327109
Short name T419
Test name
Test status
Simulation time 211751001 ps
CPU time 2.32 seconds
Started Apr 28 04:30:55 PM PDT 24
Finished Apr 28 04:30:58 PM PDT 24
Peak memory 219988 kb
Host smart-607b7667-f18b-460a-a854-22836ca4333c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107327109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1107327109
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.940658787
Short name T638
Test name
Test status
Simulation time 62346092 ps
CPU time 1.14 seconds
Started Apr 28 04:31:03 PM PDT 24
Finished Apr 28 04:31:05 PM PDT 24
Peak memory 216760 kb
Host smart-0c35a004-3fa5-4a2f-8541-2ef32c73c8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940658787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.940658787
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.4115636921
Short name T347
Test name
Test status
Simulation time 39982796 ps
CPU time 1.87 seconds
Started Apr 28 04:30:57 PM PDT 24
Finished Apr 28 04:30:59 PM PDT 24
Peak memory 219712 kb
Host smart-27508345-2289-41de-8fbd-557579c03a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115636921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.4115636921
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.972066142
Short name T806
Test name
Test status
Simulation time 78257520 ps
CPU time 1.61 seconds
Started Apr 28 04:30:57 PM PDT 24
Finished Apr 28 04:30:59 PM PDT 24
Peak memory 219704 kb
Host smart-75eac44a-8944-4e63-9bb3-10990b4f5695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972066142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.972066142
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.61759274
Short name T458
Test name
Test status
Simulation time 65975163 ps
CPU time 1.16 seconds
Started Apr 28 04:30:59 PM PDT 24
Finished Apr 28 04:31:00 PM PDT 24
Peak memory 216940 kb
Host smart-ed2cad4c-e28a-4406-9bd6-09642486cb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61759274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.61759274
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2890870187
Short name T359
Test name
Test status
Simulation time 40421406 ps
CPU time 1.45 seconds
Started Apr 28 04:30:55 PM PDT 24
Finished Apr 28 04:30:57 PM PDT 24
Peak memory 218064 kb
Host smart-94aad8e7-2989-4430-8ac1-d646f34a715a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890870187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2890870187
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3250557342
Short name T363
Test name
Test status
Simulation time 290010974 ps
CPU time 1.82 seconds
Started Apr 28 04:30:55 PM PDT 24
Finished Apr 28 04:30:57 PM PDT 24
Peak memory 218424 kb
Host smart-aa968066-021b-4ce5-8ae7-9e7b2f3cab7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250557342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3250557342
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2596811192
Short name T781
Test name
Test status
Simulation time 156628529 ps
CPU time 1.95 seconds
Started Apr 28 04:30:55 PM PDT 24
Finished Apr 28 04:30:58 PM PDT 24
Peak memory 219824 kb
Host smart-39e530db-2521-4970-8cfc-e600c4ab3444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596811192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2596811192
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2205750493
Short name T717
Test name
Test status
Simulation time 37864440 ps
CPU time 1.14 seconds
Started Apr 28 04:31:00 PM PDT 24
Finished Apr 28 04:31:02 PM PDT 24
Peak memory 216928 kb
Host smart-cb1286c4-2a8f-409e-8df9-d3e00a47c896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205750493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2205750493
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.363400032
Short name T659
Test name
Test status
Simulation time 23160837 ps
CPU time 0.94 seconds
Started Apr 28 04:29:00 PM PDT 24
Finished Apr 28 04:29:02 PM PDT 24
Peak memory 214528 kb
Host smart-6168f7c4-7b99-4b0d-9fe8-458cfaf9fcd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363400032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.363400032
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1030549227
Short name T329
Test name
Test status
Simulation time 65237439 ps
CPU time 1.44 seconds
Started Apr 28 04:29:02 PM PDT 24
Finished Apr 28 04:29:04 PM PDT 24
Peak memory 219088 kb
Host smart-ad3d0777-2612-4f8a-b72c-0f7df5a33da8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030549227 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1030549227
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2424706689
Short name T454
Test name
Test status
Simulation time 37538634 ps
CPU time 0.92 seconds
Started Apr 28 04:29:02 PM PDT 24
Finished Apr 28 04:29:04 PM PDT 24
Peak memory 217928 kb
Host smart-803e47b9-721c-461c-916a-b8d16e0a8e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424706689 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2424706689
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.84879134
Short name T839
Test name
Test status
Simulation time 70316912 ps
CPU time 1.28 seconds
Started Apr 28 04:28:57 PM PDT 24
Finished Apr 28 04:28:59 PM PDT 24
Peak memory 217020 kb
Host smart-da07b20d-ef0e-4e4c-bc27-c0606cff183b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84879134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.84879134
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.216407775
Short name T733
Test name
Test status
Simulation time 24058473 ps
CPU time 1.25 seconds
Started Apr 28 04:28:58 PM PDT 24
Finished Apr 28 04:29:00 PM PDT 24
Peak memory 223876 kb
Host smart-8d1622eb-ab75-4210-af8d-b6ccf9a59a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216407775 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.216407775
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1788694107
Short name T726
Test name
Test status
Simulation time 44727790 ps
CPU time 0.95 seconds
Started Apr 28 04:28:56 PM PDT 24
Finished Apr 28 04:28:58 PM PDT 24
Peak memory 215192 kb
Host smart-f546732e-23bc-429d-916b-bb977e42bb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788694107 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1788694107
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.532494640
Short name T592
Test name
Test status
Simulation time 1362581878 ps
CPU time 4.01 seconds
Started Apr 28 04:28:59 PM PDT 24
Finished Apr 28 04:29:03 PM PDT 24
Peak memory 215136 kb
Host smart-15badc32-24b3-4cdc-a39c-22cdbee71880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532494640 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.532494640
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1058522250
Short name T822
Test name
Test status
Simulation time 63969526608 ps
CPU time 748.98 seconds
Started Apr 28 04:28:59 PM PDT 24
Finished Apr 28 04:41:29 PM PDT 24
Peak memory 218712 kb
Host smart-133c8fe3-0003-4b3f-bfd6-9f3d3c9aea09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058522250 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1058522250
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2352144284
Short name T564
Test name
Test status
Simulation time 57238336 ps
CPU time 1.38 seconds
Started Apr 28 04:31:01 PM PDT 24
Finished Apr 28 04:31:03 PM PDT 24
Peak memory 219280 kb
Host smart-f680d551-f9cd-4a8c-b367-8f259b0f9ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352144284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2352144284
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3978997215
Short name T74
Test name
Test status
Simulation time 126571886 ps
CPU time 3.22 seconds
Started Apr 28 04:31:08 PM PDT 24
Finished Apr 28 04:31:12 PM PDT 24
Peak memory 219732 kb
Host smart-a8838fd3-ce18-4ffe-a005-14504eead438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978997215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3978997215
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2818469604
Short name T761
Test name
Test status
Simulation time 56304713 ps
CPU time 1.6 seconds
Started Apr 28 04:31:07 PM PDT 24
Finished Apr 28 04:31:09 PM PDT 24
Peak memory 218228 kb
Host smart-82aa3cca-b7eb-4223-8fab-a5bb0ccf84bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818469604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2818469604
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1790877327
Short name T430
Test name
Test status
Simulation time 49014801 ps
CPU time 1.49 seconds
Started Apr 28 04:31:04 PM PDT 24
Finished Apr 28 04:31:05 PM PDT 24
Peak memory 218240 kb
Host smart-047a2c9f-774a-4d66-879d-8bb09f0359ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790877327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1790877327
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.908283770
Short name T332
Test name
Test status
Simulation time 46989181 ps
CPU time 1.26 seconds
Started Apr 28 04:31:03 PM PDT 24
Finished Apr 28 04:31:05 PM PDT 24
Peak memory 216716 kb
Host smart-242a4b51-6d56-4ac3-abcd-800eed7211eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908283770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.908283770
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2014425865
Short name T603
Test name
Test status
Simulation time 56400837 ps
CPU time 1.11 seconds
Started Apr 28 04:31:02 PM PDT 24
Finished Apr 28 04:31:03 PM PDT 24
Peak memory 216804 kb
Host smart-2b2203be-c0f1-4ece-9fdb-54dc3b8a1f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014425865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2014425865
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.547082625
Short name T614
Test name
Test status
Simulation time 40635665 ps
CPU time 1.44 seconds
Started Apr 28 04:31:08 PM PDT 24
Finished Apr 28 04:31:10 PM PDT 24
Peak memory 216872 kb
Host smart-fd30b6c1-c8ff-4ebe-aaaa-95e8833838b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547082625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.547082625
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3612021652
Short name T418
Test name
Test status
Simulation time 57130296 ps
CPU time 1.81 seconds
Started Apr 28 04:31:11 PM PDT 24
Finished Apr 28 04:31:13 PM PDT 24
Peak memory 218332 kb
Host smart-6c4285d6-2dca-48c8-afc5-8d0d3077a66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612021652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3612021652
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.22870387
Short name T532
Test name
Test status
Simulation time 49773421 ps
CPU time 1.34 seconds
Started Apr 28 04:31:00 PM PDT 24
Finished Apr 28 04:31:02 PM PDT 24
Peak memory 218088 kb
Host smart-c2334c1c-e59e-49a8-9195-b83849e1bdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22870387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.22870387
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.430041815
Short name T131
Test name
Test status
Simulation time 229373421 ps
CPU time 1.2 seconds
Started Apr 28 04:29:01 PM PDT 24
Finished Apr 28 04:29:03 PM PDT 24
Peak memory 215588 kb
Host smart-604a118c-43eb-4480-8e25-9541280604e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430041815 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.430041815
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3004969270
Short name T627
Test name
Test status
Simulation time 31942137 ps
CPU time 1.22 seconds
Started Apr 28 04:29:05 PM PDT 24
Finished Apr 28 04:29:07 PM PDT 24
Peak memory 206600 kb
Host smart-d908f084-26b3-4f49-8680-e3ffbffcfbb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004969270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3004969270
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.782751256
Short name T778
Test name
Test status
Simulation time 41940093 ps
CPU time 0.88 seconds
Started Apr 28 04:29:07 PM PDT 24
Finished Apr 28 04:29:08 PM PDT 24
Peak memory 215772 kb
Host smart-2021b8bf-1615-42b0-ae7b-6f180c4c26df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782751256 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.782751256
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.4040094340
Short name T566
Test name
Test status
Simulation time 38986263 ps
CPU time 1.06 seconds
Started Apr 28 04:29:07 PM PDT 24
Finished Apr 28 04:29:08 PM PDT 24
Peak memory 218316 kb
Host smart-80b74642-7c74-4cfa-bdca-9f222c58141d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040094340 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.4040094340
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1577619487
Short name T502
Test name
Test status
Simulation time 31233630 ps
CPU time 0.94 seconds
Started Apr 28 04:29:00 PM PDT 24
Finished Apr 28 04:29:01 PM PDT 24
Peak memory 217932 kb
Host smart-bf29b7c1-2410-4e1e-a11d-19fcddb01724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577619487 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1577619487
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2243230168
Short name T340
Test name
Test status
Simulation time 52420962 ps
CPU time 1.28 seconds
Started Apr 28 04:29:01 PM PDT 24
Finished Apr 28 04:29:03 PM PDT 24
Peak memory 217012 kb
Host smart-3a0bf142-ca09-40f3-875f-cc98a748e9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243230168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2243230168
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3210727814
Short name T154
Test name
Test status
Simulation time 21390444 ps
CPU time 1.1 seconds
Started Apr 28 04:29:02 PM PDT 24
Finished Apr 28 04:29:03 PM PDT 24
Peak memory 215692 kb
Host smart-57c272fa-d6ef-4291-a8da-a62806f62e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210727814 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3210727814
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3050609402
Short name T1
Test name
Test status
Simulation time 27774435 ps
CPU time 1.01 seconds
Started Apr 28 04:29:02 PM PDT 24
Finished Apr 28 04:29:03 PM PDT 24
Peak memory 215176 kb
Host smart-1ce0caf0-43bd-48ab-b7ae-7370d25b87cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050609402 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3050609402
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.4022913169
Short name T352
Test name
Test status
Simulation time 879773657 ps
CPU time 2.96 seconds
Started Apr 28 04:29:04 PM PDT 24
Finished Apr 28 04:29:08 PM PDT 24
Peak memory 217112 kb
Host smart-692c651b-84a0-46e3-807b-fe204ce5a84d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022913169 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.4022913169
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.733851444
Short name T335
Test name
Test status
Simulation time 2500544577 ps
CPU time 30.49 seconds
Started Apr 28 04:29:03 PM PDT 24
Finished Apr 28 04:29:34 PM PDT 24
Peak memory 217348 kb
Host smart-e5b5238b-5a31-49a1-8690-a79d224aa032
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733851444 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.733851444
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.685770432
Short name T562
Test name
Test status
Simulation time 84626169 ps
CPU time 2.86 seconds
Started Apr 28 04:31:10 PM PDT 24
Finished Apr 28 04:31:14 PM PDT 24
Peak memory 219400 kb
Host smart-22ca87fa-83b1-462a-957f-08534758e035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685770432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.685770432
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.514446468
Short name T59
Test name
Test status
Simulation time 32793359 ps
CPU time 1.48 seconds
Started Apr 28 04:31:01 PM PDT 24
Finished Apr 28 04:31:03 PM PDT 24
Peak memory 218124 kb
Host smart-005f5733-9f42-4d67-8c24-96d5ec6e1198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514446468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.514446468
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.932183726
Short name T475
Test name
Test status
Simulation time 243453310 ps
CPU time 3.44 seconds
Started Apr 28 04:31:10 PM PDT 24
Finished Apr 28 04:31:14 PM PDT 24
Peak memory 217120 kb
Host smart-45c96309-d60a-4f9f-99b5-79d29bd3083d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932183726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.932183726
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2055362816
Short name T19
Test name
Test status
Simulation time 74012554 ps
CPU time 1.2 seconds
Started Apr 28 04:31:01 PM PDT 24
Finished Apr 28 04:31:02 PM PDT 24
Peak memory 219520 kb
Host smart-f47ff2ff-9f3c-4051-ac97-938dff85575a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055362816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2055362816
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.4230581490
Short name T838
Test name
Test status
Simulation time 34647499 ps
CPU time 1.44 seconds
Started Apr 28 04:31:01 PM PDT 24
Finished Apr 28 04:31:03 PM PDT 24
Peak memory 219128 kb
Host smart-fc6bb63e-8929-47ad-8e80-0972986e1c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230581490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.4230581490
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2916902233
Short name T402
Test name
Test status
Simulation time 49027682 ps
CPU time 1.31 seconds
Started Apr 28 04:31:08 PM PDT 24
Finished Apr 28 04:31:09 PM PDT 24
Peak memory 218140 kb
Host smart-db4da575-7e73-4644-87af-dce4e26b3986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916902233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2916902233
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3632143383
Short name T11
Test name
Test status
Simulation time 125350598 ps
CPU time 1.69 seconds
Started Apr 28 04:31:02 PM PDT 24
Finished Apr 28 04:31:05 PM PDT 24
Peak memory 219872 kb
Host smart-35062685-298c-4a9a-a739-0338384c8ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632143383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3632143383
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1709263883
Short name T637
Test name
Test status
Simulation time 93565100 ps
CPU time 1.28 seconds
Started Apr 28 04:31:08 PM PDT 24
Finished Apr 28 04:31:09 PM PDT 24
Peak memory 219404 kb
Host smart-9fa39a58-1a61-4eff-a989-c62e214b974c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709263883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1709263883
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3953187461
Short name T498
Test name
Test status
Simulation time 42555411 ps
CPU time 1.56 seconds
Started Apr 28 04:31:01 PM PDT 24
Finished Apr 28 04:31:03 PM PDT 24
Peak memory 216916 kb
Host smart-a6a4e1f4-187f-44f1-8849-6216f42e16dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953187461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3953187461
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1649508928
Short name T495
Test name
Test status
Simulation time 54984623 ps
CPU time 1.32 seconds
Started Apr 28 04:31:17 PM PDT 24
Finished Apr 28 04:31:18 PM PDT 24
Peak memory 216956 kb
Host smart-26d42c56-79f4-46c9-a009-cb0c3aec9e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649508928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1649508928
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1467869786
Short name T97
Test name
Test status
Simulation time 36756435 ps
CPU time 1.24 seconds
Started Apr 28 04:27:43 PM PDT 24
Finished Apr 28 04:27:45 PM PDT 24
Peak memory 215560 kb
Host smart-dce9c9d0-1c39-48b8-849e-a0cacbd3c0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467869786 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1467869786
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.287233468
Short name T834
Test name
Test status
Simulation time 111584176 ps
CPU time 1.04 seconds
Started Apr 28 04:27:48 PM PDT 24
Finished Apr 28 04:27:50 PM PDT 24
Peak memory 214760 kb
Host smart-604d21bf-fb75-421c-95fe-b3f7c89c57ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287233468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.287233468
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2113815157
Short name T725
Test name
Test status
Simulation time 44362512 ps
CPU time 0.89 seconds
Started Apr 28 04:27:52 PM PDT 24
Finished Apr 28 04:27:54 PM PDT 24
Peak memory 215736 kb
Host smart-ac99f5cd-12d1-4e12-99a7-d68b91c9b51e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113815157 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2113815157
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3109519018
Short name T60
Test name
Test status
Simulation time 29939209 ps
CPU time 1.16 seconds
Started Apr 28 04:27:48 PM PDT 24
Finished Apr 28 04:27:49 PM PDT 24
Peak memory 216748 kb
Host smart-f6355d55-e91b-4611-85b3-c2a44c470b93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109519018 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3109519018
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_genbits.2002831122
Short name T285
Test name
Test status
Simulation time 82327190 ps
CPU time 1.3 seconds
Started Apr 28 04:27:46 PM PDT 24
Finished Apr 28 04:27:47 PM PDT 24
Peak memory 217008 kb
Host smart-873c3727-1769-45e3-8467-6600b854a85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002831122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2002831122
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.912502728
Short name T31
Test name
Test status
Simulation time 59218495 ps
CPU time 0.86 seconds
Started Apr 28 04:27:43 PM PDT 24
Finished Apr 28 04:27:44 PM PDT 24
Peak memory 215460 kb
Host smart-10f25266-1041-46c8-8cea-ed063411b190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912502728 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.912502728
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.638938429
Short name T25
Test name
Test status
Simulation time 73111744 ps
CPU time 0.96 seconds
Started Apr 28 04:27:43 PM PDT 24
Finished Apr 28 04:27:44 PM PDT 24
Peak memory 207008 kb
Host smart-1b8a8425-29e9-4013-8d2b-bcb47460a495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638938429 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.638938429
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.282584826
Short name T300
Test name
Test status
Simulation time 21479942 ps
CPU time 0.94 seconds
Started Apr 28 04:27:43 PM PDT 24
Finished Apr 28 04:27:45 PM PDT 24
Peak memory 215168 kb
Host smart-309978f0-325e-4aca-860b-4cdc521c4c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282584826 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.282584826
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1021091123
Short name T704
Test name
Test status
Simulation time 162562536 ps
CPU time 1.32 seconds
Started Apr 28 04:27:43 PM PDT 24
Finished Apr 28 04:27:44 PM PDT 24
Peak memory 206352 kb
Host smart-f0f58432-3175-4a62-aaad-94bad4b988fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021091123 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1021091123
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.208122356
Short name T625
Test name
Test status
Simulation time 26678962030 ps
CPU time 367.8 seconds
Started Apr 28 04:27:44 PM PDT 24
Finished Apr 28 04:33:52 PM PDT 24
Peak memory 218272 kb
Host smart-291addae-1ab4-43f5-94a1-837b23f5990c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208122356 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.208122356
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1169270762
Short name T152
Test name
Test status
Simulation time 31225867 ps
CPU time 1.35 seconds
Started Apr 28 04:29:10 PM PDT 24
Finished Apr 28 04:29:12 PM PDT 24
Peak memory 215584 kb
Host smart-be845b4b-951b-4caa-ad80-f03910d58143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169270762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1169270762
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1394021102
Short name T636
Test name
Test status
Simulation time 18634920 ps
CPU time 1.03 seconds
Started Apr 28 04:29:06 PM PDT 24
Finished Apr 28 04:29:08 PM PDT 24
Peak memory 214700 kb
Host smart-1480da64-9ebf-4660-849b-4d8a25399158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394021102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1394021102
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1544706978
Short name T165
Test name
Test status
Simulation time 11721732 ps
CPU time 0.92 seconds
Started Apr 28 04:29:06 PM PDT 24
Finished Apr 28 04:29:08 PM PDT 24
Peak memory 216368 kb
Host smart-8941ea3e-f3f0-4ea6-9fae-4e578a2e5a07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544706978 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1544706978
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1910298908
Short name T117
Test name
Test status
Simulation time 138067298 ps
CPU time 1.17 seconds
Started Apr 28 04:29:06 PM PDT 24
Finished Apr 28 04:29:08 PM PDT 24
Peak memory 216844 kb
Host smart-24ae002b-23ab-40f3-94b4-d9c96fb20d4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910298908 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1910298908
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.137518348
Short name T520
Test name
Test status
Simulation time 73979257 ps
CPU time 1.1 seconds
Started Apr 28 04:29:06 PM PDT 24
Finished Apr 28 04:29:08 PM PDT 24
Peak memory 218572 kb
Host smart-d3bb8239-3b42-4069-980c-386299b336b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137518348 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.137518348
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1049619989
Short name T840
Test name
Test status
Simulation time 29957447 ps
CPU time 1.34 seconds
Started Apr 28 04:29:07 PM PDT 24
Finished Apr 28 04:29:09 PM PDT 24
Peak memory 218156 kb
Host smart-ec6afd13-f1fb-4594-a533-356443eb38ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049619989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1049619989
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1182385405
Short name T71
Test name
Test status
Simulation time 26158265 ps
CPU time 1.04 seconds
Started Apr 28 04:29:09 PM PDT 24
Finished Apr 28 04:29:11 PM PDT 24
Peak memory 215024 kb
Host smart-1dd89463-4ca2-428b-8b68-25b6e0c634a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182385405 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1182385405
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.4145411768
Short name T489
Test name
Test status
Simulation time 14705030 ps
CPU time 1.05 seconds
Started Apr 28 04:29:08 PM PDT 24
Finished Apr 28 04:29:09 PM PDT 24
Peak memory 215184 kb
Host smart-67acb4c3-3b46-4b9d-af55-5b39f901ff7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145411768 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.4145411768
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3277454709
Short name T681
Test name
Test status
Simulation time 154395321 ps
CPU time 1.46 seconds
Started Apr 28 04:29:06 PM PDT 24
Finished Apr 28 04:29:07 PM PDT 24
Peak memory 215172 kb
Host smart-d424c1e7-8104-4837-ad70-c4adcc9f93b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277454709 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3277454709
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.907735150
Short name T457
Test name
Test status
Simulation time 83277955769 ps
CPU time 1911.82 seconds
Started Apr 28 04:29:09 PM PDT 24
Finished Apr 28 05:01:02 PM PDT 24
Peak memory 225524 kb
Host smart-551f0ae1-156e-4ea3-a6ba-1f9d0049a0c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907735150 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.907735150
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1933277094
Short name T150
Test name
Test status
Simulation time 29612770 ps
CPU time 1.4 seconds
Started Apr 28 04:29:12 PM PDT 24
Finished Apr 28 04:29:14 PM PDT 24
Peak memory 215572 kb
Host smart-b5f7f2bd-1f18-46f8-9763-f3acfddb9801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933277094 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1933277094
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3413325711
Short name T391
Test name
Test status
Simulation time 32796248 ps
CPU time 0.94 seconds
Started Apr 28 04:29:09 PM PDT 24
Finished Apr 28 04:29:10 PM PDT 24
Peak memory 214748 kb
Host smart-7b473891-3038-4b71-8c7d-7aaada0a51ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413325711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3413325711
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2722090620
Short name T795
Test name
Test status
Simulation time 13426924 ps
CPU time 0.95 seconds
Started Apr 28 04:29:09 PM PDT 24
Finished Apr 28 04:29:11 PM PDT 24
Peak memory 215472 kb
Host smart-c7f06073-00fc-4d65-8b3e-166418ccb561
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722090620 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2722090620
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.1221037483
Short name T635
Test name
Test status
Simulation time 34693994 ps
CPU time 1.03 seconds
Started Apr 28 04:29:11 PM PDT 24
Finished Apr 28 04:29:12 PM PDT 24
Peak memory 223744 kb
Host smart-fb28f99c-8d7d-461e-a202-5045d0f170a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221037483 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1221037483
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3677287710
Short name T243
Test name
Test status
Simulation time 73749383 ps
CPU time 1.22 seconds
Started Apr 28 04:29:10 PM PDT 24
Finished Apr 28 04:29:12 PM PDT 24
Peak memory 217000 kb
Host smart-ebdc2280-bd88-43ae-97b7-5af2ef2c9fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677287710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3677287710
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2472163045
Short name T344
Test name
Test status
Simulation time 122880001 ps
CPU time 1.02 seconds
Started Apr 28 04:29:12 PM PDT 24
Finished Apr 28 04:29:14 PM PDT 24
Peak memory 223720 kb
Host smart-8baaf3e1-6f98-4722-8ee9-b3d34013caef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472163045 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2472163045
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1474549937
Short name T366
Test name
Test status
Simulation time 42762375 ps
CPU time 0.95 seconds
Started Apr 28 04:29:06 PM PDT 24
Finished Apr 28 04:29:08 PM PDT 24
Peak memory 215176 kb
Host smart-6d947116-eb7c-4730-bbed-424ce6853269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474549937 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1474549937
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.2950011070
Short name T524
Test name
Test status
Simulation time 175338064 ps
CPU time 3.99 seconds
Started Apr 28 04:29:10 PM PDT 24
Finished Apr 28 04:29:14 PM PDT 24
Peak memory 216880 kb
Host smart-92fbea1f-b839-450b-8a18-2ebe427909f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950011070 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2950011070
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3424830234
Short name T820
Test name
Test status
Simulation time 173064162531 ps
CPU time 2347.71 seconds
Started Apr 28 04:29:09 PM PDT 24
Finished Apr 28 05:08:18 PM PDT 24
Peak memory 230720 kb
Host smart-d1980da5-8a6b-4853-bde0-b6bb859cabbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424830234 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3424830234
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3826496095
Short name T27
Test name
Test status
Simulation time 26720058 ps
CPU time 1.28 seconds
Started Apr 28 04:29:09 PM PDT 24
Finished Apr 28 04:29:11 PM PDT 24
Peak memory 215540 kb
Host smart-8b8f9175-bf03-43be-a4ce-0591350e05de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826496095 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3826496095
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.4130891821
Short name T328
Test name
Test status
Simulation time 16921546 ps
CPU time 1.02 seconds
Started Apr 28 04:29:16 PM PDT 24
Finished Apr 28 04:29:18 PM PDT 24
Peak memory 206516 kb
Host smart-ff0f801a-817d-432c-8137-e5d1b84f2c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130891821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.4130891821
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.138659133
Short name T183
Test name
Test status
Simulation time 21295275 ps
CPU time 0.95 seconds
Started Apr 28 04:29:13 PM PDT 24
Finished Apr 28 04:29:15 PM PDT 24
Peak memory 216048 kb
Host smart-2690dd87-4507-4681-b7a0-6052efdfe73f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138659133 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.138659133
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.632683539
Short name T469
Test name
Test status
Simulation time 86638196 ps
CPU time 1.14 seconds
Started Apr 28 04:29:13 PM PDT 24
Finished Apr 28 04:29:14 PM PDT 24
Peak memory 219428 kb
Host smart-2d45e3ae-290d-4075-853b-3643e0d66e09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632683539 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.632683539
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.456426678
Short name T705
Test name
Test status
Simulation time 34391705 ps
CPU time 1.17 seconds
Started Apr 28 04:29:13 PM PDT 24
Finished Apr 28 04:29:14 PM PDT 24
Peak memory 220392 kb
Host smart-31a47849-8c8c-404f-87f0-aecc69d71408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456426678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.456426678
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2328840048
Short name T216
Test name
Test status
Simulation time 70619874 ps
CPU time 1.19 seconds
Started Apr 28 04:29:10 PM PDT 24
Finished Apr 28 04:29:11 PM PDT 24
Peak memory 216940 kb
Host smart-c0751997-5c9b-494b-9238-ce539f9d2704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328840048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2328840048
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.509524110
Short name T89
Test name
Test status
Simulation time 41468235 ps
CPU time 0.92 seconds
Started Apr 28 04:29:09 PM PDT 24
Finished Apr 28 04:29:10 PM PDT 24
Peak memory 215652 kb
Host smart-dce00976-6edc-4df8-ae08-9c6497bc21e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509524110 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.509524110
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.227421419
Short name T767
Test name
Test status
Simulation time 17968223 ps
CPU time 1.05 seconds
Started Apr 28 04:29:10 PM PDT 24
Finished Apr 28 04:29:12 PM PDT 24
Peak memory 215192 kb
Host smart-0f4f6a78-8a70-47ab-b7f4-5fba7b111676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227421419 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.227421419
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1946185341
Short name T702
Test name
Test status
Simulation time 162038842 ps
CPU time 3.2 seconds
Started Apr 28 04:29:08 PM PDT 24
Finished Apr 28 04:29:11 PM PDT 24
Peak memory 215196 kb
Host smart-1b30b628-801a-4868-b60a-5d60e5d8ef39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946185341 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1946185341
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1775464653
Short name T617
Test name
Test status
Simulation time 24148658084 ps
CPU time 258.1 seconds
Started Apr 28 04:29:09 PM PDT 24
Finished Apr 28 04:33:28 PM PDT 24
Peak memory 217484 kb
Host smart-09cad3ed-7a24-4d61-8a94-12180c641e86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775464653 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1775464653
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3409372715
Short name T514
Test name
Test status
Simulation time 44749529 ps
CPU time 1.1 seconds
Started Apr 28 04:29:17 PM PDT 24
Finished Apr 28 04:29:18 PM PDT 24
Peak memory 215572 kb
Host smart-44266ed2-d9b5-47d3-909b-49cf0df70d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409372715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3409372715
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3986491552
Short name T403
Test name
Test status
Simulation time 86679802 ps
CPU time 0.82 seconds
Started Apr 28 04:29:14 PM PDT 24
Finished Apr 28 04:29:16 PM PDT 24
Peak memory 206772 kb
Host smart-0d17bed5-e0a1-40aa-9290-842c81592f85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986491552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3986491552
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.4198262345
Short name T164
Test name
Test status
Simulation time 22752887 ps
CPU time 0.89 seconds
Started Apr 28 04:29:14 PM PDT 24
Finished Apr 28 04:29:16 PM PDT 24
Peak memory 216220 kb
Host smart-0cff4b9b-b192-4497-9185-e99a91db145c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198262345 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.4198262345
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.38810218
Short name T597
Test name
Test status
Simulation time 25264385 ps
CPU time 1.15 seconds
Started Apr 28 04:29:13 PM PDT 24
Finished Apr 28 04:29:14 PM PDT 24
Peak memory 219392 kb
Host smart-17f888d5-f0ed-4bc4-81cf-98c0c96fa4c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38810218 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_dis
able_auto_req_mode.38810218
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2927713126
Short name T55
Test name
Test status
Simulation time 95505671 ps
CPU time 1.25 seconds
Started Apr 28 04:29:15 PM PDT 24
Finished Apr 28 04:29:17 PM PDT 24
Peak memory 225456 kb
Host smart-7fad57fc-60af-4e12-a1e5-2bd27130f131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927713126 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2927713126
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2838967304
Short name T86
Test name
Test status
Simulation time 118390211 ps
CPU time 1.41 seconds
Started Apr 28 04:29:13 PM PDT 24
Finished Apr 28 04:29:15 PM PDT 24
Peak memory 216740 kb
Host smart-11c8c6b2-f67b-43af-9050-c15ba9f67f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838967304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2838967304
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.4286995722
Short name T835
Test name
Test status
Simulation time 28929223 ps
CPU time 0.97 seconds
Started Apr 28 04:29:14 PM PDT 24
Finished Apr 28 04:29:15 PM PDT 24
Peak memory 215316 kb
Host smart-fca0c0d1-01df-4c12-b78b-362bc0955fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286995722 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.4286995722
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3152332991
Short name T385
Test name
Test status
Simulation time 17013265 ps
CPU time 1.04 seconds
Started Apr 28 04:29:18 PM PDT 24
Finished Apr 28 04:29:20 PM PDT 24
Peak memory 215196 kb
Host smart-aebf906e-fe65-48ed-be2b-57cd8444eafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152332991 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3152332991
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2090287728
Short name T52
Test name
Test status
Simulation time 451789357 ps
CPU time 6.98 seconds
Started Apr 28 04:29:17 PM PDT 24
Finished Apr 28 04:29:25 PM PDT 24
Peak memory 218024 kb
Host smart-34010a46-da93-4144-9c1a-daa99dfd60aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090287728 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2090287728
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_alert.1345166442
Short name T96
Test name
Test status
Simulation time 255166447 ps
CPU time 1.35 seconds
Started Apr 28 04:29:19 PM PDT 24
Finished Apr 28 04:29:21 PM PDT 24
Peak memory 215540 kb
Host smart-15f1acfa-b505-4865-a117-91bb4d2d972b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345166442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1345166442
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.217308282
Short name T676
Test name
Test status
Simulation time 17987602 ps
CPU time 0.85 seconds
Started Apr 28 04:29:18 PM PDT 24
Finished Apr 28 04:29:20 PM PDT 24
Peak memory 206708 kb
Host smart-ee0191b6-5ff0-4745-9283-92844bfac730
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217308282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.217308282
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1619320673
Short name T574
Test name
Test status
Simulation time 11427924 ps
CPU time 0.92 seconds
Started Apr 28 04:29:18 PM PDT 24
Finished Apr 28 04:29:20 PM PDT 24
Peak memory 216228 kb
Host smart-537421c6-812f-4402-a5ff-087959cfd5ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619320673 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1619320673
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.4135468654
Short name T68
Test name
Test status
Simulation time 83084364 ps
CPU time 1.29 seconds
Started Apr 28 04:29:18 PM PDT 24
Finished Apr 28 04:29:20 PM PDT 24
Peak memory 216784 kb
Host smart-8836dfb5-fe63-4176-b124-257d6521cb4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135468654 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.4135468654
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.1740155362
Short name T341
Test name
Test status
Simulation time 20290609 ps
CPU time 1.1 seconds
Started Apr 28 04:29:17 PM PDT 24
Finished Apr 28 04:29:19 PM PDT 24
Peak memory 218268 kb
Host smart-221d492e-fe4f-461d-af5a-b1f04177d51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740155362 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1740155362
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2372726249
Short name T743
Test name
Test status
Simulation time 46579153 ps
CPU time 1.41 seconds
Started Apr 28 04:29:20 PM PDT 24
Finished Apr 28 04:29:22 PM PDT 24
Peak memory 216952 kb
Host smart-ab4e13b6-a30c-487f-b564-35c22962cc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372726249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2372726249
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.3768211388
Short name T530
Test name
Test status
Simulation time 27744865 ps
CPU time 1.1 seconds
Started Apr 28 04:29:19 PM PDT 24
Finished Apr 28 04:29:20 PM PDT 24
Peak memory 223920 kb
Host smart-a4ea8d74-fbd2-4d1c-ba45-d74b1b3eb197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768211388 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3768211388
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2423705254
Short name T588
Test name
Test status
Simulation time 20342376 ps
CPU time 0.94 seconds
Started Apr 28 04:29:13 PM PDT 24
Finished Apr 28 04:29:15 PM PDT 24
Peak memory 215240 kb
Host smart-8e0f086e-56a9-4bcf-9833-6bb9c960721b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423705254 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2423705254
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2476476299
Short name T212
Test name
Test status
Simulation time 352722555 ps
CPU time 7.25 seconds
Started Apr 28 04:29:18 PM PDT 24
Finished Apr 28 04:29:26 PM PDT 24
Peak memory 216780 kb
Host smart-6437a124-8158-4b9e-afe2-32a1731bf80f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476476299 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2476476299
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3012997150
Short name T194
Test name
Test status
Simulation time 174382959468 ps
CPU time 2097.97 seconds
Started Apr 28 04:29:19 PM PDT 24
Finished Apr 28 05:04:19 PM PDT 24
Peak memory 225940 kb
Host smart-1fc8252b-dd34-46e2-9544-2aac078da3a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012997150 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3012997150
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2029043881
Short name T263
Test name
Test status
Simulation time 86000595 ps
CPU time 1.37 seconds
Started Apr 28 04:29:17 PM PDT 24
Finished Apr 28 04:29:19 PM PDT 24
Peak memory 215512 kb
Host smart-de52901a-b899-40f1-a344-cf6397f5fa5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029043881 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2029043881
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1525807435
Short name T302
Test name
Test status
Simulation time 32849641 ps
CPU time 0.99 seconds
Started Apr 28 04:29:23 PM PDT 24
Finished Apr 28 04:29:25 PM PDT 24
Peak memory 206528 kb
Host smart-1e884bb4-b7b6-46c7-bbbe-9353e57cb71b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525807435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1525807435
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2307741854
Short name T667
Test name
Test status
Simulation time 156747551 ps
CPU time 0.96 seconds
Started Apr 28 04:29:18 PM PDT 24
Finished Apr 28 04:29:20 PM PDT 24
Peak memory 215256 kb
Host smart-d184fd7c-88a7-4d06-b969-1dec7b9ef6a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307741854 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2307741854
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1883868087
Short name T413
Test name
Test status
Simulation time 77129260 ps
CPU time 1.06 seconds
Started Apr 28 04:29:18 PM PDT 24
Finished Apr 28 04:29:20 PM PDT 24
Peak memory 219240 kb
Host smart-1661c632-fd12-4ab5-bb9d-6ab6b85f63bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883868087 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1883868087
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2549846658
Short name T349
Test name
Test status
Simulation time 26914436 ps
CPU time 0.9 seconds
Started Apr 28 04:29:20 PM PDT 24
Finished Apr 28 04:29:22 PM PDT 24
Peak memory 218284 kb
Host smart-f90b89c8-f29b-4654-ab10-03d5180ac312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549846658 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2549846658
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1093703956
Short name T286
Test name
Test status
Simulation time 36544544 ps
CPU time 1.09 seconds
Started Apr 28 04:29:22 PM PDT 24
Finished Apr 28 04:29:24 PM PDT 24
Peak memory 217692 kb
Host smart-97f41bea-ea10-4f37-941a-a59c7fe74f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093703956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1093703956
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3844673301
Short name T409
Test name
Test status
Simulation time 23499974 ps
CPU time 1.19 seconds
Started Apr 28 04:29:18 PM PDT 24
Finished Apr 28 04:29:20 PM PDT 24
Peak memory 223928 kb
Host smart-ac2a8599-c6f6-448d-aee9-1eab477ac5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844673301 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3844673301
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1967138203
Short name T313
Test name
Test status
Simulation time 13814954 ps
CPU time 0.93 seconds
Started Apr 28 04:29:17 PM PDT 24
Finished Apr 28 04:29:19 PM PDT 24
Peak memory 215164 kb
Host smart-1c54f550-2624-47c7-998e-de2d3eee6896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967138203 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1967138203
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1234849908
Short name T386
Test name
Test status
Simulation time 69248845 ps
CPU time 1.29 seconds
Started Apr 28 04:29:18 PM PDT 24
Finished Apr 28 04:29:20 PM PDT 24
Peak memory 216816 kb
Host smart-f3b60318-d6b9-4781-8d0e-635d1482b9df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234849908 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1234849908
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.4282059330
Short name T334
Test name
Test status
Simulation time 63611707106 ps
CPU time 430.61 seconds
Started Apr 28 04:29:16 PM PDT 24
Finished Apr 28 04:36:27 PM PDT 24
Peak memory 219248 kb
Host smart-c2b5a213-2bd2-4aaf-bab1-fa08b344e431
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282059330 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.4282059330
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.443442644
Short name T132
Test name
Test status
Simulation time 26491131 ps
CPU time 1.28 seconds
Started Apr 28 04:29:21 PM PDT 24
Finished Apr 28 04:29:23 PM PDT 24
Peak memory 215536 kb
Host smart-d23415b2-2987-4d7e-a093-fe0f16a87e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443442644 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.443442644
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1238123701
Short name T714
Test name
Test status
Simulation time 16489110 ps
CPU time 1.01 seconds
Started Apr 28 04:29:22 PM PDT 24
Finished Apr 28 04:29:24 PM PDT 24
Peak memory 214752 kb
Host smart-fcbe00fc-5bba-4ea3-b97c-01943846f456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238123701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1238123701
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2602434035
Short name T818
Test name
Test status
Simulation time 40852349 ps
CPU time 0.96 seconds
Started Apr 28 04:29:23 PM PDT 24
Finished Apr 28 04:29:25 PM PDT 24
Peak memory 216224 kb
Host smart-12b6e4f9-0cac-4d24-ac09-73392188a966
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602434035 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2602434035
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.574705858
Short name T660
Test name
Test status
Simulation time 52627428 ps
CPU time 1.2 seconds
Started Apr 28 04:29:22 PM PDT 24
Finished Apr 28 04:29:24 PM PDT 24
Peak memory 218092 kb
Host smart-962e663f-6330-47df-b5fe-b38cbce75bfd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574705858 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.574705858
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.4256585388
Short name T174
Test name
Test status
Simulation time 42238767 ps
CPU time 1.22 seconds
Started Apr 28 04:29:21 PM PDT 24
Finished Apr 28 04:29:23 PM PDT 24
Peak memory 220644 kb
Host smart-9827a93e-43c5-4fa5-aac7-bb62cae6c875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256585388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.4256585388
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.4137826933
Short name T618
Test name
Test status
Simulation time 38600596 ps
CPU time 1.67 seconds
Started Apr 28 04:29:22 PM PDT 24
Finished Apr 28 04:29:24 PM PDT 24
Peak memory 218064 kb
Host smart-a531f6c9-a514-4767-9b5a-b7549ab250eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137826933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.4137826933
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1372167780
Short name T736
Test name
Test status
Simulation time 31841571 ps
CPU time 0.89 seconds
Started Apr 28 04:29:22 PM PDT 24
Finished Apr 28 04:29:24 PM PDT 24
Peak memory 215176 kb
Host smart-ac5e9626-5b9d-4246-a206-a1de2d72b575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372167780 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1372167780
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2873278258
Short name T149
Test name
Test status
Simulation time 18933261 ps
CPU time 1.1 seconds
Started Apr 28 04:29:24 PM PDT 24
Finished Apr 28 04:29:26 PM PDT 24
Peak memory 215196 kb
Host smart-6dd296f8-32ad-4882-8fa6-c13fe06a9d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873278258 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2873278258
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.693183683
Short name T509
Test name
Test status
Simulation time 874452054 ps
CPU time 5.12 seconds
Started Apr 28 04:29:24 PM PDT 24
Finished Apr 28 04:29:30 PM PDT 24
Peak memory 215164 kb
Host smart-e3e44e8b-6752-4c5a-8a4f-5c601d7aa274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693183683 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.693183683
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3690509672
Short name T831
Test name
Test status
Simulation time 34690331404 ps
CPU time 946.07 seconds
Started Apr 28 04:29:23 PM PDT 24
Finished Apr 28 04:45:10 PM PDT 24
Peak memory 221144 kb
Host smart-5a3d51e0-a5a1-4ac7-98b4-80937f568d9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690509672 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3690509672
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.4112055759
Short name T732
Test name
Test status
Simulation time 49663025 ps
CPU time 1.2 seconds
Started Apr 28 04:29:27 PM PDT 24
Finished Apr 28 04:29:29 PM PDT 24
Peak memory 215040 kb
Host smart-9e58a5e1-62d3-4d0a-9aef-653227e62f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112055759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.4112055759
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2843293554
Short name T771
Test name
Test status
Simulation time 52786385 ps
CPU time 0.99 seconds
Started Apr 28 04:29:22 PM PDT 24
Finished Apr 28 04:29:23 PM PDT 24
Peak memory 206556 kb
Host smart-594a6d82-b09b-4d6c-8c95-a265cf7a0159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843293554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2843293554
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.541519779
Short name T740
Test name
Test status
Simulation time 11820717 ps
CPU time 0.9 seconds
Started Apr 28 04:29:21 PM PDT 24
Finished Apr 28 04:29:22 PM PDT 24
Peak memory 215732 kb
Host smart-cf5343fe-73cb-4b1c-b9a5-374a21841ea9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541519779 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.541519779
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1380722427
Short name T41
Test name
Test status
Simulation time 42616159 ps
CPU time 1.08 seconds
Started Apr 28 04:29:22 PM PDT 24
Finished Apr 28 04:29:24 PM PDT 24
Peak memory 218084 kb
Host smart-cff13a30-5a72-4b9d-90a3-b85fa9935084
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380722427 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1380722427
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2571350542
Short name T490
Test name
Test status
Simulation time 27931593 ps
CPU time 0.91 seconds
Started Apr 28 04:29:22 PM PDT 24
Finished Apr 28 04:29:23 PM PDT 24
Peak memory 217932 kb
Host smart-a166cacf-685a-4475-9381-942c12959c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571350542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2571350542
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1578972743
Short name T786
Test name
Test status
Simulation time 58857282 ps
CPU time 1.96 seconds
Started Apr 28 04:29:20 PM PDT 24
Finished Apr 28 04:29:23 PM PDT 24
Peak memory 219620 kb
Host smart-fec1fbec-7900-4793-b2c5-e050a03b81e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578972743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1578972743
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2837880337
Short name T90
Test name
Test status
Simulation time 19695907 ps
CPU time 1.09 seconds
Started Apr 28 04:29:27 PM PDT 24
Finished Apr 28 04:29:29 PM PDT 24
Peak memory 215124 kb
Host smart-edb0473f-9464-4354-aacf-6c7f20950f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837880337 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2837880337
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.4242136469
Short name T837
Test name
Test status
Simulation time 15998526 ps
CPU time 0.99 seconds
Started Apr 28 04:29:26 PM PDT 24
Finished Apr 28 04:29:28 PM PDT 24
Peak memory 215192 kb
Host smart-5698e8c1-9ef5-4387-828c-0b410472afef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242136469 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.4242136469
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2662123791
Short name T322
Test name
Test status
Simulation time 173241463 ps
CPU time 1.2 seconds
Started Apr 28 04:29:23 PM PDT 24
Finished Apr 28 04:29:25 PM PDT 24
Peak memory 216932 kb
Host smart-c219ec95-1ca4-4c0c-8f1d-7414e0f675cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662123791 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2662123791
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3740726782
Short name T193
Test name
Test status
Simulation time 81296156028 ps
CPU time 754.58 seconds
Started Apr 28 04:29:27 PM PDT 24
Finished Apr 28 04:42:03 PM PDT 24
Peak memory 221088 kb
Host smart-afb1d616-2cda-4bd0-9fd1-9230a520013c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740726782 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3740726782
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3490417331
Short name T720
Test name
Test status
Simulation time 41369014 ps
CPU time 1.27 seconds
Started Apr 28 04:29:27 PM PDT 24
Finished Apr 28 04:29:28 PM PDT 24
Peak memory 215532 kb
Host smart-7704b05c-adfb-4779-bb72-1c55a17de2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490417331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3490417331
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3195868137
Short name T399
Test name
Test status
Simulation time 23215179 ps
CPU time 0.96 seconds
Started Apr 28 04:29:28 PM PDT 24
Finished Apr 28 04:29:30 PM PDT 24
Peak memory 206504 kb
Host smart-b358928c-48c4-4d41-be2d-7b05bcfd2534
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195868137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3195868137
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1724476278
Short name T772
Test name
Test status
Simulation time 21245852 ps
CPU time 0.89 seconds
Started Apr 28 04:29:27 PM PDT 24
Finished Apr 28 04:29:28 PM PDT 24
Peak memory 216060 kb
Host smart-7db0033a-e3e5-4b15-9be5-38ee5438cbf6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724476278 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1724476278
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.1418463803
Short name T6
Test name
Test status
Simulation time 36167161 ps
CPU time 0.91 seconds
Started Apr 28 04:29:27 PM PDT 24
Finished Apr 28 04:29:28 PM PDT 24
Peak memory 218268 kb
Host smart-3c9f4bcc-645e-4695-99ee-ea46039cca07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418463803 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1418463803
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.978895339
Short name T40
Test name
Test status
Simulation time 81565965 ps
CPU time 1.22 seconds
Started Apr 28 04:29:25 PM PDT 24
Finished Apr 28 04:29:26 PM PDT 24
Peak memory 216948 kb
Host smart-4d63ae48-3ee7-40a7-a724-5eeee524a76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978895339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.978895339
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3863867242
Short name T459
Test name
Test status
Simulation time 34907974 ps
CPU time 0.88 seconds
Started Apr 28 04:29:27 PM PDT 24
Finished Apr 28 04:29:29 PM PDT 24
Peak memory 215428 kb
Host smart-246393d7-203f-4621-8f56-0afac24f3414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863867242 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3863867242
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.403837404
Short name T643
Test name
Test status
Simulation time 39644946 ps
CPU time 0.95 seconds
Started Apr 28 04:29:24 PM PDT 24
Finished Apr 28 04:29:26 PM PDT 24
Peak memory 215200 kb
Host smart-0dc8e31d-a365-4668-a6a7-9346d2fbb369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403837404 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.403837404
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.4015919536
Short name T703
Test name
Test status
Simulation time 1336936915 ps
CPU time 6.49 seconds
Started Apr 28 04:29:23 PM PDT 24
Finished Apr 28 04:29:30 PM PDT 24
Peak memory 218028 kb
Host smart-20f40251-23e6-431e-8f3d-e2e14767294c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015919536 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.4015919536
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.792883194
Short name T461
Test name
Test status
Simulation time 71239358785 ps
CPU time 1801.46 seconds
Started Apr 28 04:29:27 PM PDT 24
Finished Apr 28 04:59:30 PM PDT 24
Peak memory 226648 kb
Host smart-d9197e88-9d22-4b19-bbd2-a5a9920b2338
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792883194 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.792883194
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3567904000
Short name T779
Test name
Test status
Simulation time 47626372 ps
CPU time 1.25 seconds
Started Apr 28 04:29:29 PM PDT 24
Finished Apr 28 04:29:31 PM PDT 24
Peak memory 215568 kb
Host smart-5f2f4253-b2fa-4822-9a86-44afe53f0a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567904000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3567904000
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1716632631
Short name T586
Test name
Test status
Simulation time 13729984 ps
CPU time 0.92 seconds
Started Apr 28 04:29:29 PM PDT 24
Finished Apr 28 04:29:30 PM PDT 24
Peak memory 207004 kb
Host smart-638b3909-493d-43f8-8da7-ee12b195322a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716632631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1716632631
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.91688699
Short name T693
Test name
Test status
Simulation time 17710275 ps
CPU time 0.86 seconds
Started Apr 28 04:29:27 PM PDT 24
Finished Apr 28 04:29:28 PM PDT 24
Peak memory 215824 kb
Host smart-07ece248-805b-4035-af7b-10a6b9cfaf4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91688699 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.91688699
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.155024457
Short name T361
Test name
Test status
Simulation time 26287166 ps
CPU time 1.12 seconds
Started Apr 28 04:29:28 PM PDT 24
Finished Apr 28 04:29:30 PM PDT 24
Peak memory 218032 kb
Host smart-727fd07b-ff05-436c-91cb-dca9b5936c1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155024457 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.155024457
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3681023633
Short name T819
Test name
Test status
Simulation time 97410473 ps
CPU time 1.24 seconds
Started Apr 28 04:29:25 PM PDT 24
Finished Apr 28 04:29:26 PM PDT 24
Peak memory 219552 kb
Host smart-cb0458bc-1b62-4473-a1cb-b46a120d63bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681023633 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3681023633
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.544933233
Short name T316
Test name
Test status
Simulation time 56440584 ps
CPU time 1.79 seconds
Started Apr 28 04:29:28 PM PDT 24
Finished Apr 28 04:29:31 PM PDT 24
Peak memory 218104 kb
Host smart-edd38c54-a081-4e77-9515-01eb945b1e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544933233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.544933233
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3885622661
Short name T609
Test name
Test status
Simulation time 23182572 ps
CPU time 1.18 seconds
Started Apr 28 04:29:28 PM PDT 24
Finished Apr 28 04:29:29 PM PDT 24
Peak memory 215304 kb
Host smart-4818479e-91ca-4b35-8eca-782e57fd6518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885622661 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3885622661
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1621737869
Short name T429
Test name
Test status
Simulation time 14982804 ps
CPU time 1.02 seconds
Started Apr 28 04:29:26 PM PDT 24
Finished Apr 28 04:29:28 PM PDT 24
Peak memory 215152 kb
Host smart-f213f855-17ab-4614-b5f3-353d13176f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621737869 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1621737869
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2975281947
Short name T364
Test name
Test status
Simulation time 441801787 ps
CPU time 4.99 seconds
Started Apr 28 04:29:27 PM PDT 24
Finished Apr 28 04:29:32 PM PDT 24
Peak memory 216868 kb
Host smart-1ac278d8-c7ce-4cda-92ea-47e14aed73a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975281947 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2975281947
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.871426190
Short name T544
Test name
Test status
Simulation time 469415112085 ps
CPU time 975.55 seconds
Started Apr 28 04:29:27 PM PDT 24
Finished Apr 28 04:45:43 PM PDT 24
Peak memory 222620 kb
Host smart-d88f4a31-730a-4053-a42b-d6427a36cb06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871426190 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.871426190
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.156709665
Short name T701
Test name
Test status
Simulation time 181283566 ps
CPU time 1.39 seconds
Started Apr 28 04:27:48 PM PDT 24
Finished Apr 28 04:27:50 PM PDT 24
Peak memory 215564 kb
Host smart-8a0ec95d-bacd-4fcf-bcc3-0a6792397299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156709665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.156709665
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2180921940
Short name T64
Test name
Test status
Simulation time 32636601 ps
CPU time 0.88 seconds
Started Apr 28 04:27:47 PM PDT 24
Finished Apr 28 04:27:48 PM PDT 24
Peak memory 214720 kb
Host smart-4c44930f-96d5-4103-bdb1-90d9a32a3069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180921940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2180921940
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2232825449
Short name T536
Test name
Test status
Simulation time 12566343 ps
CPU time 0.94 seconds
Started Apr 28 04:27:47 PM PDT 24
Finished Apr 28 04:27:48 PM PDT 24
Peak memory 215424 kb
Host smart-6fcfbe01-f6b3-45f4-b51c-7efea5a01212
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232825449 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2232825449
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1452470939
Short name T159
Test name
Test status
Simulation time 151950190 ps
CPU time 1.25 seconds
Started Apr 28 04:27:52 PM PDT 24
Finished Apr 28 04:27:54 PM PDT 24
Peak memory 216796 kb
Host smart-79fd0ba8-6d0c-4421-832d-db53bce9cd51
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452470939 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1452470939
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.885843900
Short name T142
Test name
Test status
Simulation time 21717750 ps
CPU time 1 seconds
Started Apr 28 04:27:49 PM PDT 24
Finished Apr 28 04:27:50 PM PDT 24
Peak memory 218408 kb
Host smart-fc14da2f-91d9-4d8c-9224-969cbf371213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885843900 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.885843900
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1713805600
Short name T825
Test name
Test status
Simulation time 81066409 ps
CPU time 1.44 seconds
Started Apr 28 04:27:49 PM PDT 24
Finished Apr 28 04:27:51 PM PDT 24
Peak memory 216852 kb
Host smart-60ba53d4-1628-4153-a00c-ee2396e3bbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713805600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1713805600
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1270151698
Short name T92
Test name
Test status
Simulation time 32286239 ps
CPU time 0.94 seconds
Started Apr 28 04:27:49 PM PDT 24
Finished Apr 28 04:27:51 PM PDT 24
Peak memory 215544 kb
Host smart-d4f6b13b-89eb-43e1-8d32-e6525fb855ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270151698 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1270151698
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.3339065684
Short name T746
Test name
Test status
Simulation time 18239225 ps
CPU time 1.02 seconds
Started Apr 28 04:27:48 PM PDT 24
Finished Apr 28 04:27:49 PM PDT 24
Peak memory 206964 kb
Host smart-f45fd0cc-df73-4e8d-b701-6edc21532fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339065684 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3339065684
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2171539112
Short name T61
Test name
Test status
Simulation time 790305647 ps
CPU time 8.11 seconds
Started Apr 28 04:27:52 PM PDT 24
Finished Apr 28 04:28:01 PM PDT 24
Peak memory 236340 kb
Host smart-fe6dac9b-d1e0-4e48-b866-c0d54e73bd84
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171539112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2171539112
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.1563599058
Short name T664
Test name
Test status
Simulation time 18334295 ps
CPU time 1.02 seconds
Started Apr 28 04:27:48 PM PDT 24
Finished Apr 28 04:27:50 PM PDT 24
Peak memory 206976 kb
Host smart-f20b9e9b-dfff-405a-869e-85c0515065e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563599058 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1563599058
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3013607318
Short name T557
Test name
Test status
Simulation time 357223523 ps
CPU time 6.68 seconds
Started Apr 28 04:27:48 PM PDT 24
Finished Apr 28 04:27:56 PM PDT 24
Peak memory 218028 kb
Host smart-5ec8403d-ff83-45a7-998c-592a88c5e5c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013607318 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3013607318
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.818206746
Short name T199
Test name
Test status
Simulation time 35354181486 ps
CPU time 424.4 seconds
Started Apr 28 04:27:49 PM PDT 24
Finished Apr 28 04:34:54 PM PDT 24
Peak memory 219244 kb
Host smart-feeb75a8-d925-48ce-ad2f-7b6aa5ddb72e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818206746 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.818206746
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert_test.1264953243
Short name T801
Test name
Test status
Simulation time 37154842 ps
CPU time 1.09 seconds
Started Apr 28 04:29:30 PM PDT 24
Finished Apr 28 04:29:32 PM PDT 24
Peak memory 214860 kb
Host smart-1687c91a-a2ce-47a0-bb56-1274be5a30de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264953243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1264953243
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2851905048
Short name T739
Test name
Test status
Simulation time 21440179 ps
CPU time 0.89 seconds
Started Apr 28 04:29:31 PM PDT 24
Finished Apr 28 04:29:33 PM PDT 24
Peak memory 215792 kb
Host smart-aa78b0ac-ee0d-42e2-af0d-372e0059790a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851905048 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2851905048
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_err.2833975334
Short name T448
Test name
Test status
Simulation time 21862050 ps
CPU time 0.92 seconds
Started Apr 28 04:29:32 PM PDT 24
Finished Apr 28 04:29:33 PM PDT 24
Peak memory 217908 kb
Host smart-1104ba80-aa03-482b-acc3-060a3acbe706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833975334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2833975334
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2703006256
Short name T808
Test name
Test status
Simulation time 64555143 ps
CPU time 1.22 seconds
Started Apr 28 04:29:27 PM PDT 24
Finished Apr 28 04:29:29 PM PDT 24
Peak memory 216792 kb
Host smart-4d513ef7-d6cf-4139-8b78-e48118c897c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703006256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2703006256
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.537909195
Short name T622
Test name
Test status
Simulation time 22048319 ps
CPU time 1.14 seconds
Started Apr 28 04:29:35 PM PDT 24
Finished Apr 28 04:29:37 PM PDT 24
Peak memory 215304 kb
Host smart-b19ea55b-fd76-42de-93b7-6642333f4101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537909195 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.537909195
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.151688140
Short name T358
Test name
Test status
Simulation time 32642146 ps
CPU time 0.92 seconds
Started Apr 28 04:29:27 PM PDT 24
Finished Apr 28 04:29:29 PM PDT 24
Peak memory 215180 kb
Host smart-3ddf0c1c-048a-4a68-afee-2b8f1f942246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151688140 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.151688140
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3075248050
Short name T304
Test name
Test status
Simulation time 421090338 ps
CPU time 2.76 seconds
Started Apr 28 04:29:26 PM PDT 24
Finished Apr 28 04:29:29 PM PDT 24
Peak memory 216900 kb
Host smart-89b39ab0-34df-4065-8d0a-a73341d398ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075248050 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3075248050
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.791377218
Short name T356
Test name
Test status
Simulation time 253495645884 ps
CPU time 1257.81 seconds
Started Apr 28 04:29:29 PM PDT 24
Finished Apr 28 04:50:27 PM PDT 24
Peak memory 224748 kb
Host smart-c864dd3c-6813-4877-b846-5dd0beea4f9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791377218 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.791377218
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1017117728
Short name T28
Test name
Test status
Simulation time 343296982 ps
CPU time 1.38 seconds
Started Apr 28 04:29:32 PM PDT 24
Finished Apr 28 04:29:33 PM PDT 24
Peak memory 215548 kb
Host smart-09bb210b-b3a5-4dc5-97ce-28b7cebfe486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017117728 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1017117728
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.4161784020
Short name T325
Test name
Test status
Simulation time 18900324 ps
CPU time 0.87 seconds
Started Apr 28 04:29:33 PM PDT 24
Finished Apr 28 04:29:34 PM PDT 24
Peak memory 205936 kb
Host smart-f84a2916-51e7-424d-8a1c-f42c4d135794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161784020 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.4161784020
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2115746113
Short name T135
Test name
Test status
Simulation time 13338695 ps
CPU time 0.93 seconds
Started Apr 28 04:29:31 PM PDT 24
Finished Apr 28 04:29:32 PM PDT 24
Peak memory 216176 kb
Host smart-5e7d94d2-40a5-40e2-acc7-010fdbea1aa4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115746113 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2115746113
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_err.556972689
Short name T94
Test name
Test status
Simulation time 27842209 ps
CPU time 1.14 seconds
Started Apr 28 04:29:30 PM PDT 24
Finished Apr 28 04:29:31 PM PDT 24
Peak memory 229628 kb
Host smart-24b702aa-87e7-4c0d-a201-f6f5ba8cca10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556972689 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.556972689
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1757990745
Short name T821
Test name
Test status
Simulation time 67930808 ps
CPU time 1.05 seconds
Started Apr 28 04:29:34 PM PDT 24
Finished Apr 28 04:29:36 PM PDT 24
Peak memory 216896 kb
Host smart-c15d19c8-959c-4630-ba3f-543b0447db8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757990745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1757990745
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2650351447
Short name T35
Test name
Test status
Simulation time 21884532 ps
CPU time 1.15 seconds
Started Apr 28 04:29:30 PM PDT 24
Finished Apr 28 04:29:32 PM PDT 24
Peak memory 215876 kb
Host smart-09e20348-444b-46dc-ae37-2ea8903eb50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650351447 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2650351447
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1057419721
Short name T589
Test name
Test status
Simulation time 19813669 ps
CPU time 1.04 seconds
Started Apr 28 04:29:30 PM PDT 24
Finished Apr 28 04:29:31 PM PDT 24
Peak memory 215224 kb
Host smart-8d51730e-a102-4f6d-af31-60a9e2d3376e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057419721 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1057419721
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1822317666
Short name T608
Test name
Test status
Simulation time 296605221 ps
CPU time 3.65 seconds
Started Apr 28 04:29:31 PM PDT 24
Finished Apr 28 04:29:35 PM PDT 24
Peak memory 219568 kb
Host smart-95a029b6-35fd-4566-a2b9-5853bde4abaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822317666 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1822317666
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3429226586
Short name T158
Test name
Test status
Simulation time 25529877586 ps
CPU time 579.77 seconds
Started Apr 28 04:29:34 PM PDT 24
Finished Apr 28 04:39:15 PM PDT 24
Peak memory 220204 kb
Host smart-7a93679d-d458-4a01-b8ed-08c088d4919c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429226586 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3429226586
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1574445579
Short name T525
Test name
Test status
Simulation time 25664089 ps
CPU time 1.28 seconds
Started Apr 28 04:29:34 PM PDT 24
Finished Apr 28 04:29:36 PM PDT 24
Peak memory 215536 kb
Host smart-493e920b-0a2c-4ca7-98a2-4ae3e4ae4741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574445579 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1574445579
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1109460254
Short name T547
Test name
Test status
Simulation time 56939931 ps
CPU time 1.15 seconds
Started Apr 28 04:29:35 PM PDT 24
Finished Apr 28 04:29:36 PM PDT 24
Peak memory 206584 kb
Host smart-4d02a375-c0cc-48f7-b0a0-2061d9fe2dcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109460254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1109460254
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3584676857
Short name T73
Test name
Test status
Simulation time 28216343 ps
CPU time 0.91 seconds
Started Apr 28 04:29:35 PM PDT 24
Finished Apr 28 04:29:36 PM PDT 24
Peak memory 216104 kb
Host smart-a7c30bc2-31c6-4edb-9a65-977f7a9d927a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584676857 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3584676857
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.564320282
Short name T384
Test name
Test status
Simulation time 68521030 ps
CPU time 1.05 seconds
Started Apr 28 04:29:34 PM PDT 24
Finished Apr 28 04:29:35 PM PDT 24
Peak memory 219304 kb
Host smart-db3cc79c-299d-48b4-ae50-9c02fc47b92d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564320282 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.564320282
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2170587902
Short name T130
Test name
Test status
Simulation time 51472903 ps
CPU time 1.3 seconds
Started Apr 28 04:29:36 PM PDT 24
Finished Apr 28 04:29:38 PM PDT 24
Peak memory 225668 kb
Host smart-90e72a3e-4976-49ec-ab8a-1e139930da01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170587902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2170587902
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2207166379
Short name T607
Test name
Test status
Simulation time 118041258 ps
CPU time 1.48 seconds
Started Apr 28 04:29:34 PM PDT 24
Finished Apr 28 04:29:36 PM PDT 24
Peak memory 218388 kb
Host smart-7b3b9235-bdbc-48c5-9fd5-80d032bb89e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207166379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2207166379
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3942238289
Short name T30
Test name
Test status
Simulation time 25027787 ps
CPU time 1.03 seconds
Started Apr 28 04:29:34 PM PDT 24
Finished Apr 28 04:29:36 PM PDT 24
Peak memory 215736 kb
Host smart-1033b580-0109-49f5-a284-eaff6aef7b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942238289 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3942238289
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.26234377
Short name T556
Test name
Test status
Simulation time 53042012 ps
CPU time 0.96 seconds
Started Apr 28 04:29:31 PM PDT 24
Finished Apr 28 04:29:32 PM PDT 24
Peak memory 215180 kb
Host smart-48a2625c-ff9e-4ef0-89eb-c3e90137a452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26234377 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.26234377
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3914218119
Short name T683
Test name
Test status
Simulation time 298212982 ps
CPU time 1.71 seconds
Started Apr 28 04:29:35 PM PDT 24
Finished Apr 28 04:29:37 PM PDT 24
Peak memory 216932 kb
Host smart-2b286770-46c4-4dc9-831a-5952d7c35e31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914218119 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3914218119
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.749739605
Short name T580
Test name
Test status
Simulation time 173555781475 ps
CPU time 997.57 seconds
Started Apr 28 04:29:34 PM PDT 24
Finished Apr 28 04:46:13 PM PDT 24
Peak memory 220240 kb
Host smart-2496e3f2-d539-4b5d-8b4c-83cdcf435162
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749739605 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.749739605
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1191815223
Short name T554
Test name
Test status
Simulation time 44764251 ps
CPU time 1.22 seconds
Started Apr 28 04:29:35 PM PDT 24
Finished Apr 28 04:29:37 PM PDT 24
Peak memory 215564 kb
Host smart-32565f95-0468-468e-9803-bfb8276eab03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191815223 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1191815223
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.4231693040
Short name T474
Test name
Test status
Simulation time 50667807 ps
CPU time 0.89 seconds
Started Apr 28 04:29:37 PM PDT 24
Finished Apr 28 04:29:38 PM PDT 24
Peak memory 206564 kb
Host smart-46ae856e-06af-45c2-91ec-0cf2cc417d8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231693040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.4231693040
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.4086530148
Short name T144
Test name
Test status
Simulation time 31431428 ps
CPU time 0.86 seconds
Started Apr 28 04:29:41 PM PDT 24
Finished Apr 28 04:29:42 PM PDT 24
Peak memory 216232 kb
Host smart-50948ed7-87e5-405b-bb09-b1ec123c07ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086530148 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.4086530148
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3471975941
Short name T812
Test name
Test status
Simulation time 121857859 ps
CPU time 1.26 seconds
Started Apr 28 04:29:39 PM PDT 24
Finished Apr 28 04:29:40 PM PDT 24
Peak memory 215416 kb
Host smart-370ca698-6612-4258-b30f-914b9dba1dff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471975941 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3471975941
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3632458159
Short name T99
Test name
Test status
Simulation time 27043040 ps
CPU time 1.46 seconds
Started Apr 28 04:29:41 PM PDT 24
Finished Apr 28 04:29:43 PM PDT 24
Peak memory 229652 kb
Host smart-c220c83c-a511-48ea-940e-e651fdd5b7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632458159 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3632458159
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.4107666418
Short name T789
Test name
Test status
Simulation time 41906652 ps
CPU time 1.14 seconds
Started Apr 28 04:29:37 PM PDT 24
Finished Apr 28 04:29:39 PM PDT 24
Peak memory 218240 kb
Host smart-c730b679-3d82-43e6-a8ae-80a58b0dc2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107666418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.4107666418
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2611218926
Short name T832
Test name
Test status
Simulation time 21088465 ps
CPU time 1.25 seconds
Started Apr 28 04:29:37 PM PDT 24
Finished Apr 28 04:29:39 PM PDT 24
Peak memory 223868 kb
Host smart-20111bdb-7076-4cf9-abf8-c17811b738fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611218926 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2611218926
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3130497780
Short name T570
Test name
Test status
Simulation time 16494987 ps
CPU time 1.02 seconds
Started Apr 28 04:29:34 PM PDT 24
Finished Apr 28 04:29:36 PM PDT 24
Peak memory 206984 kb
Host smart-77f4fd8c-e42f-4e9e-b6d5-4ad5b3466e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130497780 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3130497780
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1420510792
Short name T518
Test name
Test status
Simulation time 335912944 ps
CPU time 3.99 seconds
Started Apr 28 04:29:35 PM PDT 24
Finished Apr 28 04:29:39 PM PDT 24
Peak memory 215168 kb
Host smart-6901c15c-4582-4317-91ad-db10c19fd674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420510792 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1420510792
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3942690642
Short name T641
Test name
Test status
Simulation time 51378609586 ps
CPU time 637.23 seconds
Started Apr 28 04:29:37 PM PDT 24
Finished Apr 28 04:40:15 PM PDT 24
Peak memory 218380 kb
Host smart-4094fc28-3b07-4f13-b1c4-74ba9abfaefa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942690642 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3942690642
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3876426534
Short name T254
Test name
Test status
Simulation time 42206429 ps
CPU time 1.15 seconds
Started Apr 28 04:29:47 PM PDT 24
Finished Apr 28 04:29:48 PM PDT 24
Peak memory 215516 kb
Host smart-cfb62b4a-41e7-4935-b5c7-3b35b3a5cd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876426534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3876426534
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3681111715
Short name T306
Test name
Test status
Simulation time 35871000 ps
CPU time 0.85 seconds
Started Apr 28 04:29:47 PM PDT 24
Finished Apr 28 04:29:48 PM PDT 24
Peak memory 206720 kb
Host smart-a72c5718-3503-4ef4-8c5e-acc010b8a9e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681111715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3681111715
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3390380080
Short name T181
Test name
Test status
Simulation time 12047202 ps
CPU time 0.88 seconds
Started Apr 28 04:29:43 PM PDT 24
Finished Apr 28 04:29:44 PM PDT 24
Peak memory 215232 kb
Host smart-b8cd4cf5-1046-42cd-8172-178328303742
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390380080 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3390380080
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_err.1433985849
Short name T176
Test name
Test status
Simulation time 61952323 ps
CPU time 0.99 seconds
Started Apr 28 04:29:43 PM PDT 24
Finished Apr 28 04:29:44 PM PDT 24
Peak memory 223720 kb
Host smart-9a897147-b78c-404d-a621-f230f5465227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433985849 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1433985849
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1440271914
Short name T540
Test name
Test status
Simulation time 25954942 ps
CPU time 1.3 seconds
Started Apr 28 04:29:48 PM PDT 24
Finished Apr 28 04:29:50 PM PDT 24
Peak memory 217132 kb
Host smart-10feb599-116b-42ce-9870-75dd21d9bb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440271914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1440271914
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2232137666
Short name T417
Test name
Test status
Simulation time 23378146 ps
CPU time 1.25 seconds
Started Apr 28 04:29:48 PM PDT 24
Finished Apr 28 04:29:50 PM PDT 24
Peak memory 223832 kb
Host smart-cfbf9b83-795f-41e0-b192-52efc843e617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232137666 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2232137666
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2873780138
Short name T297
Test name
Test status
Simulation time 63191165 ps
CPU time 0.89 seconds
Started Apr 28 04:29:39 PM PDT 24
Finished Apr 28 04:29:41 PM PDT 24
Peak memory 215232 kb
Host smart-5ce2bec0-0ed0-4e08-8ce0-4d45d3ad7fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873780138 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2873780138
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.386190515
Short name T513
Test name
Test status
Simulation time 107959695 ps
CPU time 1.22 seconds
Started Apr 28 04:29:38 PM PDT 24
Finished Apr 28 04:29:39 PM PDT 24
Peak memory 206992 kb
Host smart-eac073d2-ecec-4e0b-8cf3-360b71a29d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386190515 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.386190515
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3447348337
Short name T425
Test name
Test status
Simulation time 93377097891 ps
CPU time 417.03 seconds
Started Apr 28 04:29:48 PM PDT 24
Finished Apr 28 04:36:46 PM PDT 24
Peak memory 218424 kb
Host smart-49df727a-50b9-4253-a3dd-096d70ce5ec0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447348337 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3447348337
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2088583305
Short name T147
Test name
Test status
Simulation time 82199388 ps
CPU time 1.25 seconds
Started Apr 28 04:29:49 PM PDT 24
Finished Apr 28 04:29:51 PM PDT 24
Peak memory 215464 kb
Host smart-ce99e2da-3e71-4092-a9ea-38ddf7083df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088583305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2088583305
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2274912356
Short name T809
Test name
Test status
Simulation time 27864488 ps
CPU time 1.26 seconds
Started Apr 28 04:29:48 PM PDT 24
Finished Apr 28 04:29:50 PM PDT 24
Peak memory 206464 kb
Host smart-43261801-c546-4625-9697-fcbbf763c4e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274912356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2274912356
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3531473416
Short name T187
Test name
Test status
Simulation time 40293472 ps
CPU time 0.94 seconds
Started Apr 28 04:29:43 PM PDT 24
Finished Apr 28 04:29:45 PM PDT 24
Peak memory 216104 kb
Host smart-600e1698-d06e-4b33-a9be-9155e73886b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531473416 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3531473416
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2140099485
Short name T111
Test name
Test status
Simulation time 146864716 ps
CPU time 1.04 seconds
Started Apr 28 04:29:42 PM PDT 24
Finished Apr 28 04:29:43 PM PDT 24
Peak memory 219260 kb
Host smart-80877f95-620c-4ebc-a2bf-da9a79594702
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140099485 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2140099485
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3032733267
Short name T133
Test name
Test status
Simulation time 78166497 ps
CPU time 1.07 seconds
Started Apr 28 04:29:46 PM PDT 24
Finished Apr 28 04:29:47 PM PDT 24
Peak memory 223740 kb
Host smart-f0924380-c756-4653-b541-42065c26ecd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032733267 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3032733267
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1528066024
Short name T244
Test name
Test status
Simulation time 94978883 ps
CPU time 1.44 seconds
Started Apr 28 04:29:48 PM PDT 24
Finished Apr 28 04:29:50 PM PDT 24
Peak memory 218284 kb
Host smart-0a8ff0eb-5078-4f44-bbba-80fc3279b762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528066024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1528066024
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.4188857138
Short name T312
Test name
Test status
Simulation time 23172373 ps
CPU time 1.2 seconds
Started Apr 28 04:29:45 PM PDT 24
Finished Apr 28 04:29:46 PM PDT 24
Peak memory 215304 kb
Host smart-93c7ffd9-179d-459f-afb4-e113afe42bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188857138 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.4188857138
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3089323626
Short name T662
Test name
Test status
Simulation time 61437957 ps
CPU time 0.98 seconds
Started Apr 28 04:29:44 PM PDT 24
Finished Apr 28 04:29:45 PM PDT 24
Peak memory 215148 kb
Host smart-3d5bc795-a687-42b1-b68c-1c3798dda066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089323626 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3089323626
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.217255552
Short name T551
Test name
Test status
Simulation time 251335042 ps
CPU time 5.14 seconds
Started Apr 28 04:29:44 PM PDT 24
Finished Apr 28 04:29:50 PM PDT 24
Peak memory 216788 kb
Host smart-79984283-4599-4068-958a-264da5604f52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217255552 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.217255552
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.934707089
Short name T804
Test name
Test status
Simulation time 37827956913 ps
CPU time 917.97 seconds
Started Apr 28 04:29:48 PM PDT 24
Finished Apr 28 04:45:07 PM PDT 24
Peak memory 223448 kb
Host smart-a7221a30-fb1d-44fe-8448-f227a37abbc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934707089 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.934707089
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.571430348
Short name T257
Test name
Test status
Simulation time 83203674 ps
CPU time 1.32 seconds
Started Apr 28 04:29:48 PM PDT 24
Finished Apr 28 04:29:50 PM PDT 24
Peak memory 215460 kb
Host smart-37677219-810b-460a-a4d1-75c5bf0c33a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571430348 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.571430348
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1888309674
Short name T428
Test name
Test status
Simulation time 35105858 ps
CPU time 0.84 seconds
Started Apr 28 04:29:49 PM PDT 24
Finished Apr 28 04:29:51 PM PDT 24
Peak memory 206348 kb
Host smart-d0a4409b-e8fb-49a0-83ae-fa03368036f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888309674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1888309674
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.833232662
Short name T621
Test name
Test status
Simulation time 68484227 ps
CPU time 1.25 seconds
Started Apr 28 04:29:50 PM PDT 24
Finished Apr 28 04:29:52 PM PDT 24
Peak memory 219428 kb
Host smart-bec74dde-0ae0-4230-8e53-1570a2672157
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833232662 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.833232662
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2631443779
Short name T141
Test name
Test status
Simulation time 35651587 ps
CPU time 0.92 seconds
Started Apr 28 04:29:43 PM PDT 24
Finished Apr 28 04:29:44 PM PDT 24
Peak memory 218112 kb
Host smart-bde0f0e1-2e6e-4ec5-8fec-0e3a381a74f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631443779 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2631443779
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1391172581
Short name T477
Test name
Test status
Simulation time 54329339 ps
CPU time 1.36 seconds
Started Apr 28 04:29:43 PM PDT 24
Finished Apr 28 04:29:45 PM PDT 24
Peak memory 219548 kb
Host smart-43e90af9-e2ff-4f9d-b851-c276e81e8904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391172581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1391172581
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3591321784
Short name T669
Test name
Test status
Simulation time 46125775 ps
CPU time 0.87 seconds
Started Apr 28 04:29:45 PM PDT 24
Finished Apr 28 04:29:46 PM PDT 24
Peak memory 215392 kb
Host smart-668ff002-79a5-4c16-be4b-6bf8b601994f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591321784 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3591321784
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3251467598
Short name T620
Test name
Test status
Simulation time 191776200 ps
CPU time 0.99 seconds
Started Apr 28 04:29:42 PM PDT 24
Finished Apr 28 04:29:43 PM PDT 24
Peak memory 215080 kb
Host smart-b8628982-8620-47bd-89ca-f1a80ade7f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251467598 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3251467598
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2423007782
Short name T505
Test name
Test status
Simulation time 23481420 ps
CPU time 1.13 seconds
Started Apr 28 04:29:42 PM PDT 24
Finished Apr 28 04:29:43 PM PDT 24
Peak memory 215176 kb
Host smart-5d107e10-3949-4944-8eaf-c8f8a8b8d3e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423007782 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2423007782
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1756868867
Short name T192
Test name
Test status
Simulation time 13746806374 ps
CPU time 316.19 seconds
Started Apr 28 04:29:44 PM PDT 24
Finished Apr 28 04:35:01 PM PDT 24
Peak memory 217788 kb
Host smart-d5eadc92-66b5-4075-b915-a7b259836d9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756868867 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1756868867
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3258864988
Short name T677
Test name
Test status
Simulation time 82511568 ps
CPU time 1.28 seconds
Started Apr 28 04:29:48 PM PDT 24
Finished Apr 28 04:29:50 PM PDT 24
Peak memory 215572 kb
Host smart-012420d6-0716-4205-9011-dc7bb817fb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258864988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3258864988
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3962736334
Short name T814
Test name
Test status
Simulation time 47713220 ps
CPU time 0.91 seconds
Started Apr 28 04:29:47 PM PDT 24
Finished Apr 28 04:29:49 PM PDT 24
Peak memory 206364 kb
Host smart-01c68aab-4122-47d3-ab8a-07942167156e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962736334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3962736334
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1182674467
Short name T139
Test name
Test status
Simulation time 29704326 ps
CPU time 0.93 seconds
Started Apr 28 04:29:47 PM PDT 24
Finished Apr 28 04:29:49 PM PDT 24
Peak memory 216256 kb
Host smart-bfc5a59d-f40f-4eab-94f5-3093511f1419
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182674467 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1182674467
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3827042181
Short name T105
Test name
Test status
Simulation time 75824051 ps
CPU time 1.39 seconds
Started Apr 28 04:29:46 PM PDT 24
Finished Apr 28 04:29:48 PM PDT 24
Peak memory 216768 kb
Host smart-4a0c5feb-faca-4b28-8984-509094b9cde8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827042181 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3827042181
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3857147070
Short name T721
Test name
Test status
Simulation time 60160460 ps
CPU time 0.89 seconds
Started Apr 28 04:29:49 PM PDT 24
Finished Apr 28 04:29:51 PM PDT 24
Peak memory 217920 kb
Host smart-3dc47206-1d72-4f0d-b033-461b499ad0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857147070 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3857147070
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3772386030
Short name T214
Test name
Test status
Simulation time 95814150 ps
CPU time 1.46 seconds
Started Apr 28 04:29:47 PM PDT 24
Finished Apr 28 04:29:49 PM PDT 24
Peak memory 219476 kb
Host smart-f5b663b9-4ecb-458e-8c60-cabf49bc0afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772386030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3772386030
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1602264442
Short name T680
Test name
Test status
Simulation time 26798936 ps
CPU time 1.03 seconds
Started Apr 28 04:29:48 PM PDT 24
Finished Apr 28 04:29:50 PM PDT 24
Peak memory 215392 kb
Host smart-f9fd6753-0185-4aba-9a7f-bd2a1d4fbf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602264442 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1602264442
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.860191820
Short name T314
Test name
Test status
Simulation time 23591566 ps
CPU time 1.05 seconds
Started Apr 28 04:29:46 PM PDT 24
Finished Apr 28 04:29:48 PM PDT 24
Peak memory 215132 kb
Host smart-3db1dd94-9c4b-4c2f-b9ea-f595bce707c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860191820 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.860191820
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3683742045
Short name T584
Test name
Test status
Simulation time 672909711 ps
CPU time 7.53 seconds
Started Apr 28 04:29:48 PM PDT 24
Finished Apr 28 04:29:57 PM PDT 24
Peak memory 217020 kb
Host smart-684ebb49-270a-4b28-bec2-e79ef819f869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683742045 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3683742045
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1196402848
Short name T288
Test name
Test status
Simulation time 38439098163 ps
CPU time 677.51 seconds
Started Apr 28 04:29:48 PM PDT 24
Finished Apr 28 04:41:07 PM PDT 24
Peak memory 217840 kb
Host smart-f1406a3e-eca1-43bb-a2e7-812871e09f73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196402848 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1196402848
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3795364641
Short name T479
Test name
Test status
Simulation time 150694519 ps
CPU time 1.31 seconds
Started Apr 28 04:29:49 PM PDT 24
Finished Apr 28 04:29:51 PM PDT 24
Peak memory 215524 kb
Host smart-7d434c41-7e6a-477e-acdb-ae40e679c679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795364641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3795364641
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3850042701
Short name T572
Test name
Test status
Simulation time 65531208 ps
CPU time 0.95 seconds
Started Apr 28 04:29:53 PM PDT 24
Finished Apr 28 04:29:54 PM PDT 24
Peak memory 206572 kb
Host smart-6f1017c6-c28d-46bb-beb4-a2d26a5f4924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850042701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3850042701
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2128924547
Short name T543
Test name
Test status
Simulation time 15278429 ps
CPU time 0.85 seconds
Started Apr 28 04:29:51 PM PDT 24
Finished Apr 28 04:29:52 PM PDT 24
Peak memory 215720 kb
Host smart-4b01859f-f4a2-4935-a59e-2896b9463921
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128924547 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2128924547
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2308699647
Short name T769
Test name
Test status
Simulation time 30942601 ps
CPU time 1.11 seconds
Started Apr 28 04:29:53 PM PDT 24
Finished Apr 28 04:29:54 PM PDT 24
Peak memory 216692 kb
Host smart-65a4cb3f-ea18-4a97-abf5-225b0244842d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308699647 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2308699647
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.125588699
Short name T123
Test name
Test status
Simulation time 22424440 ps
CPU time 1.09 seconds
Started Apr 28 04:29:50 PM PDT 24
Finished Apr 28 04:29:51 PM PDT 24
Peak memory 223924 kb
Host smart-f5c316c3-f7d7-4c85-af72-7eda6d13ad11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125588699 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.125588699
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1898459583
Short name T81
Test name
Test status
Simulation time 124397612 ps
CPU time 2.91 seconds
Started Apr 28 04:29:47 PM PDT 24
Finished Apr 28 04:29:51 PM PDT 24
Peak memory 218880 kb
Host smart-62ee142f-d3da-42c3-a446-d1b9a8f83a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898459583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1898459583
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2400434556
Short name T32
Test name
Test status
Simulation time 27068383 ps
CPU time 0.9 seconds
Started Apr 28 04:29:53 PM PDT 24
Finished Apr 28 04:29:54 PM PDT 24
Peak memory 215552 kb
Host smart-89ee77d6-dddc-47d8-a151-9fb9da21a6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400434556 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2400434556
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2450296536
Short name T388
Test name
Test status
Simulation time 42049781 ps
CPU time 0.98 seconds
Started Apr 28 04:29:46 PM PDT 24
Finished Apr 28 04:29:47 PM PDT 24
Peak memory 215188 kb
Host smart-ed97aaee-8d92-4c80-95d9-0aeb37de3e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450296536 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2450296536
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3699004960
Short name T788
Test name
Test status
Simulation time 74502506 ps
CPU time 2.24 seconds
Started Apr 28 04:29:48 PM PDT 24
Finished Apr 28 04:29:51 PM PDT 24
Peak memory 217968 kb
Host smart-4b29b6e1-2dae-45f5-9090-509c88a1e794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699004960 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3699004960
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1304945647
Short name T197
Test name
Test status
Simulation time 29310218871 ps
CPU time 368.62 seconds
Started Apr 28 04:29:47 PM PDT 24
Finished Apr 28 04:35:57 PM PDT 24
Peak memory 218320 kb
Host smart-faed6faa-0d7f-409b-a734-d4340a61c97b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304945647 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1304945647
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.945205245
Short name T259
Test name
Test status
Simulation time 94448851 ps
CPU time 1.4 seconds
Started Apr 28 04:29:49 PM PDT 24
Finished Apr 28 04:29:51 PM PDT 24
Peak memory 215548 kb
Host smart-63a43fdd-7277-4409-b6d3-bd894432fea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945205245 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.945205245
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1010881139
Short name T687
Test name
Test status
Simulation time 21988898 ps
CPU time 0.9 seconds
Started Apr 28 04:29:58 PM PDT 24
Finished Apr 28 04:30:00 PM PDT 24
Peak memory 215072 kb
Host smart-69cf372a-a4cf-4244-943f-f6d2d3e783af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010881139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1010881139
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3255811793
Short name T753
Test name
Test status
Simulation time 53552436 ps
CPU time 0.89 seconds
Started Apr 28 04:29:51 PM PDT 24
Finished Apr 28 04:29:52 PM PDT 24
Peak memory 216144 kb
Host smart-2fc60b6c-cde5-42ad-8e82-3c4dbc57df22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255811793 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3255811793
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.571503100
Short name T173
Test name
Test status
Simulation time 60366609 ps
CPU time 1.19 seconds
Started Apr 28 04:29:52 PM PDT 24
Finished Apr 28 04:29:53 PM PDT 24
Peak memory 219392 kb
Host smart-491777de-bd8c-4e61-87ac-d501a1b13085
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571503100 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.571503100
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3501253213
Short name T4
Test name
Test status
Simulation time 34047203 ps
CPU time 1.22 seconds
Started Apr 28 04:29:51 PM PDT 24
Finished Apr 28 04:29:53 PM PDT 24
Peak memory 223884 kb
Host smart-f262e519-6c48-4ba3-ac65-c928c2369eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501253213 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3501253213
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2321510122
Short name T451
Test name
Test status
Simulation time 53497827 ps
CPU time 1.39 seconds
Started Apr 28 04:29:50 PM PDT 24
Finished Apr 28 04:29:52 PM PDT 24
Peak memory 218316 kb
Host smart-480794a1-a931-4979-90df-5cdf8b3128a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321510122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2321510122
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.906943631
Short name T610
Test name
Test status
Simulation time 22325826 ps
CPU time 1.22 seconds
Started Apr 28 04:29:53 PM PDT 24
Finished Apr 28 04:29:55 PM PDT 24
Peak memory 223892 kb
Host smart-662e667d-0c97-4c0c-8525-80c5ee4927e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906943631 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.906943631
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.991764289
Short name T629
Test name
Test status
Simulation time 30596687 ps
CPU time 0.95 seconds
Started Apr 28 04:29:55 PM PDT 24
Finished Apr 28 04:29:56 PM PDT 24
Peak memory 215172 kb
Host smart-68eb236d-b303-4b9a-846a-5ebee5a22f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991764289 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.991764289
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2908262830
Short name T749
Test name
Test status
Simulation time 48690141 ps
CPU time 1.51 seconds
Started Apr 28 04:29:50 PM PDT 24
Finished Apr 28 04:29:52 PM PDT 24
Peak memory 206944 kb
Host smart-4cdb9335-9be4-4125-8166-96842147e59a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908262830 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2908262830
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2329370813
Short name T196
Test name
Test status
Simulation time 98115018998 ps
CPU time 2351.94 seconds
Started Apr 28 04:29:50 PM PDT 24
Finished Apr 28 05:09:03 PM PDT 24
Peak memory 227172 kb
Host smart-a2363a12-957a-420a-91bc-83172857df9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329370813 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2329370813
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3078908534
Short name T255
Test name
Test status
Simulation time 52464894 ps
CPU time 1.24 seconds
Started Apr 28 04:27:57 PM PDT 24
Finished Apr 28 04:27:59 PM PDT 24
Peak memory 215540 kb
Host smart-bb4fc42e-fbfd-4593-a4f1-e72993879131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078908534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3078908534
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.690185126
Short name T510
Test name
Test status
Simulation time 16660650 ps
CPU time 1.01 seconds
Started Apr 28 04:27:52 PM PDT 24
Finished Apr 28 04:27:53 PM PDT 24
Peak memory 206476 kb
Host smart-4ef6d41c-38bf-4eb4-9fbb-b299be72f7bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690185126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.690185126
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2251868110
Short name T735
Test name
Test status
Simulation time 35267857 ps
CPU time 1.19 seconds
Started Apr 28 04:27:52 PM PDT 24
Finished Apr 28 04:27:54 PM PDT 24
Peak memory 216732 kb
Host smart-fd4b12be-fad3-46af-a55c-fdbb26786a78
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251868110 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2251868110
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3882301938
Short name T656
Test name
Test status
Simulation time 54237106 ps
CPU time 1.06 seconds
Started Apr 28 04:27:53 PM PDT 24
Finished Apr 28 04:27:54 PM PDT 24
Peak memory 219664 kb
Host smart-5d9d1dff-6cfd-434e-b1cd-a9d1ed378e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882301938 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3882301938
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.75886081
Short name T466
Test name
Test status
Simulation time 37318940 ps
CPU time 1.79 seconds
Started Apr 28 04:27:52 PM PDT 24
Finished Apr 28 04:27:54 PM PDT 24
Peak memory 217908 kb
Host smart-a630244e-96cd-4576-a7fa-8ce29f5ed5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75886081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.75886081
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_smoke.3966430433
Short name T462
Test name
Test status
Simulation time 29736518 ps
CPU time 0.96 seconds
Started Apr 28 04:27:49 PM PDT 24
Finished Apr 28 04:27:50 PM PDT 24
Peak memory 215128 kb
Host smart-900fdf7b-f805-4a0f-ba69-c6d8a1152745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966430433 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3966430433
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1124089650
Short name T723
Test name
Test status
Simulation time 547651392 ps
CPU time 3.43 seconds
Started Apr 28 04:27:52 PM PDT 24
Finished Apr 28 04:27:56 PM PDT 24
Peak memory 219320 kb
Host smart-dddaf2e2-82f7-4efa-b59f-8d896a8ff0ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124089650 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1124089650
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/50.edn_err.1467951810
Short name T559
Test name
Test status
Simulation time 19129949 ps
CPU time 1.16 seconds
Started Apr 28 04:29:57 PM PDT 24
Finished Apr 28 04:29:58 PM PDT 24
Peak memory 218304 kb
Host smart-019847fc-8116-464a-9612-f46c34c56356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467951810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1467951810
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1599266031
Short name T674
Test name
Test status
Simulation time 218988764 ps
CPU time 3.54 seconds
Started Apr 28 04:29:56 PM PDT 24
Finished Apr 28 04:30:00 PM PDT 24
Peak memory 219316 kb
Host smart-107d088c-9d82-43fb-b0c2-b034adc6ac3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599266031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1599266031
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.112392652
Short name T124
Test name
Test status
Simulation time 42532031 ps
CPU time 1.29 seconds
Started Apr 28 04:29:59 PM PDT 24
Finished Apr 28 04:30:02 PM PDT 24
Peak memory 225456 kb
Host smart-cc128f9a-01db-4d20-905f-255632b12af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112392652 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.112392652
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3941759691
Short name T727
Test name
Test status
Simulation time 52951861 ps
CPU time 1.77 seconds
Started Apr 28 04:29:58 PM PDT 24
Finished Apr 28 04:30:01 PM PDT 24
Peak memory 218144 kb
Host smart-18052708-c8b2-437e-a750-5537bed96e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941759691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3941759691
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.3631894562
Short name T8
Test name
Test status
Simulation time 23635982 ps
CPU time 1.36 seconds
Started Apr 28 04:29:54 PM PDT 24
Finished Apr 28 04:29:56 PM PDT 24
Peak memory 223920 kb
Host smart-f84613f6-3cb3-43ab-8470-b926254429ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631894562 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3631894562
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.531897767
Short name T397
Test name
Test status
Simulation time 294648862 ps
CPU time 3.52 seconds
Started Apr 28 04:29:55 PM PDT 24
Finished Apr 28 04:29:59 PM PDT 24
Peak memory 219560 kb
Host smart-d1d03e28-80fd-41f3-ad3f-e385f648aeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531897767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.531897767
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.3086600781
Short name T759
Test name
Test status
Simulation time 27003455 ps
CPU time 0.97 seconds
Started Apr 28 04:29:55 PM PDT 24
Finished Apr 28 04:29:56 PM PDT 24
Peak memory 218344 kb
Host smart-9a825e20-5e4c-4cb6-8008-99d3e14e9b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086600781 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3086600781
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.93732183
Short name T319
Test name
Test status
Simulation time 30795210 ps
CPU time 1.29 seconds
Started Apr 28 04:29:56 PM PDT 24
Finished Apr 28 04:29:58 PM PDT 24
Peak memory 219524 kb
Host smart-e53d7cc8-a459-40ae-9660-92be3a4afc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93732183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.93732183
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.3085502293
Short name T171
Test name
Test status
Simulation time 20371313 ps
CPU time 1.13 seconds
Started Apr 28 04:29:58 PM PDT 24
Finished Apr 28 04:30:00 PM PDT 24
Peak memory 219532 kb
Host smart-572587d9-fb7c-4ea3-b445-ffd741fb1327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085502293 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3085502293
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.691254823
Short name T373
Test name
Test status
Simulation time 257723677 ps
CPU time 1.06 seconds
Started Apr 28 04:29:56 PM PDT 24
Finished Apr 28 04:29:57 PM PDT 24
Peak memory 216772 kb
Host smart-b3221d9b-91c7-4def-9a02-e44f28f2bea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691254823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.691254823
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.4259661073
Short name T119
Test name
Test status
Simulation time 24325227 ps
CPU time 1.2 seconds
Started Apr 28 04:29:57 PM PDT 24
Finished Apr 28 04:29:58 PM PDT 24
Peak memory 229492 kb
Host smart-cb5c2022-0de2-444d-af97-6769d1975777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259661073 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.4259661073
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2670618847
Short name T282
Test name
Test status
Simulation time 61079798 ps
CPU time 2.37 seconds
Started Apr 28 04:29:57 PM PDT 24
Finished Apr 28 04:30:00 PM PDT 24
Peak memory 219812 kb
Host smart-fd806645-b4a2-4cd1-8b06-c6ffe9f3697f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670618847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2670618847
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.496136645
Short name T7
Test name
Test status
Simulation time 20512766 ps
CPU time 1.12 seconds
Started Apr 28 04:29:58 PM PDT 24
Finished Apr 28 04:30:00 PM PDT 24
Peak memory 219500 kb
Host smart-42c5f845-fd41-4304-bb24-e83858a3af01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496136645 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.496136645
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3977226059
Short name T434
Test name
Test status
Simulation time 113883196 ps
CPU time 1.04 seconds
Started Apr 28 04:29:58 PM PDT 24
Finished Apr 28 04:30:00 PM PDT 24
Peak memory 218796 kb
Host smart-e67d119b-cfdb-4410-9b63-05d871400df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977226059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3977226059
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2660048837
Short name T167
Test name
Test status
Simulation time 83215662 ps
CPU time 1.39 seconds
Started Apr 28 04:29:55 PM PDT 24
Finished Apr 28 04:29:56 PM PDT 24
Peak memory 225464 kb
Host smart-83d83cb1-33ca-4a2d-b7c2-a0037eaa75a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660048837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2660048837
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2998473393
Short name T522
Test name
Test status
Simulation time 49969143 ps
CPU time 1.25 seconds
Started Apr 28 04:29:57 PM PDT 24
Finished Apr 28 04:29:59 PM PDT 24
Peak memory 217080 kb
Host smart-432dbc01-a5ec-442c-a7c7-9f6bc1498e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998473393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2998473393
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2629145909
Short name T764
Test name
Test status
Simulation time 18522346 ps
CPU time 1.03 seconds
Started Apr 28 04:29:59 PM PDT 24
Finished Apr 28 04:30:00 PM PDT 24
Peak memory 218104 kb
Host smart-3baa5d50-a300-45ef-a5b8-aa22a9b02ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629145909 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2629145909
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3535644634
Short name T406
Test name
Test status
Simulation time 63072203 ps
CPU time 1.31 seconds
Started Apr 28 04:29:55 PM PDT 24
Finished Apr 28 04:29:57 PM PDT 24
Peak memory 218276 kb
Host smart-2f1dfa01-53ee-49ea-ad1f-e7558f6be462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535644634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3535644634
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.2986185009
Short name T127
Test name
Test status
Simulation time 24766754 ps
CPU time 1.21 seconds
Started Apr 28 04:30:01 PM PDT 24
Finished Apr 28 04:30:02 PM PDT 24
Peak memory 223872 kb
Host smart-827b69af-eea4-41e8-ad29-7d35416eca39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986185009 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2986185009
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2763524378
Short name T208
Test name
Test status
Simulation time 49166277 ps
CPU time 1.53 seconds
Started Apr 28 04:30:00 PM PDT 24
Finished Apr 28 04:30:02 PM PDT 24
Peak memory 218312 kb
Host smart-5a4c91c1-6df0-4808-9620-94499c9dd57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763524378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2763524378
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2922527477
Short name T151
Test name
Test status
Simulation time 109690673 ps
CPU time 1.37 seconds
Started Apr 28 04:27:57 PM PDT 24
Finished Apr 28 04:27:59 PM PDT 24
Peak memory 215580 kb
Host smart-bbb6280b-088a-43f3-9c69-61519062522b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922527477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2922527477
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1664901297
Short name T565
Test name
Test status
Simulation time 49368820 ps
CPU time 0.99 seconds
Started Apr 28 04:27:55 PM PDT 24
Finished Apr 28 04:27:56 PM PDT 24
Peak memory 206548 kb
Host smart-533f15ec-1ff0-4409-8bf2-aa7de3e78f3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664901297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1664901297
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2406450259
Short name T162
Test name
Test status
Simulation time 25629900 ps
CPU time 0.88 seconds
Started Apr 28 04:27:57 PM PDT 24
Finished Apr 28 04:27:58 PM PDT 24
Peak memory 216084 kb
Host smart-a09cd27e-8a28-419b-8d90-ffb3ed70cb82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406450259 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2406450259
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1227061882
Short name T471
Test name
Test status
Simulation time 114608415 ps
CPU time 1.14 seconds
Started Apr 28 04:27:56 PM PDT 24
Finished Apr 28 04:27:58 PM PDT 24
Peak memory 218124 kb
Host smart-722258ce-42ef-43f9-b954-efe92eb552f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227061882 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1227061882
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.158013021
Short name T170
Test name
Test status
Simulation time 68907227 ps
CPU time 1.1 seconds
Started Apr 28 04:27:56 PM PDT 24
Finished Apr 28 04:27:58 PM PDT 24
Peak memory 219728 kb
Host smart-91c3dc9e-e56e-44f1-bd46-1da7cbb3b4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158013021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.158013021
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1328930652
Short name T496
Test name
Test status
Simulation time 62694112 ps
CPU time 1.48 seconds
Started Apr 28 04:27:56 PM PDT 24
Finished Apr 28 04:27:58 PM PDT 24
Peak memory 218284 kb
Host smart-c454912c-157d-4b87-ac44-68416b3b11a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328930652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1328930652
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.4016355758
Short name T449
Test name
Test status
Simulation time 21420732 ps
CPU time 1.12 seconds
Started Apr 28 04:27:56 PM PDT 24
Finished Apr 28 04:27:58 PM PDT 24
Peak memory 215408 kb
Host smart-cb6e1df4-6d1b-4163-9e2a-5bc5996831c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016355758 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.4016355758
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1668767284
Short name T827
Test name
Test status
Simulation time 56178315 ps
CPU time 0.95 seconds
Started Apr 28 04:27:57 PM PDT 24
Finished Apr 28 04:27:58 PM PDT 24
Peak memory 206928 kb
Host smart-dbb0b4ce-8b5e-4bc7-947b-12f6c68befa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668767284 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1668767284
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1111026698
Short name T542
Test name
Test status
Simulation time 136324716 ps
CPU time 0.92 seconds
Started Apr 28 04:27:58 PM PDT 24
Finished Apr 28 04:27:59 PM PDT 24
Peak memory 215148 kb
Host smart-7a1fdddd-4ee7-4bec-b459-4bed7dbd7234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111026698 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1111026698
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2765122883
Short name T470
Test name
Test status
Simulation time 85792656 ps
CPU time 1.06 seconds
Started Apr 28 04:27:56 PM PDT 24
Finished Apr 28 04:27:57 PM PDT 24
Peak memory 206192 kb
Host smart-f9ef7a63-e3a8-42c4-ae6b-558f953a1b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765122883 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2765122883
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1447493768
Short name T750
Test name
Test status
Simulation time 224989905670 ps
CPU time 743.13 seconds
Started Apr 28 04:27:56 PM PDT 24
Finished Apr 28 04:40:19 PM PDT 24
Peak memory 220432 kb
Host smart-153bda30-480e-42fe-b6ed-f95c465cb7c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447493768 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1447493768
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.849655472
Short name T777
Test name
Test status
Simulation time 39200736 ps
CPU time 1.01 seconds
Started Apr 28 04:29:59 PM PDT 24
Finished Apr 28 04:30:01 PM PDT 24
Peak memory 219592 kb
Host smart-92515f54-d2e2-4ae2-b1e7-95e7ecaba7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849655472 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.849655472
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1504449076
Short name T478
Test name
Test status
Simulation time 65542775 ps
CPU time 2.53 seconds
Started Apr 28 04:30:01 PM PDT 24
Finished Apr 28 04:30:04 PM PDT 24
Peak memory 217100 kb
Host smart-f0630eaf-f346-4f33-b3c0-efa7e7b5f862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504449076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1504449076
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.1779247005
Short name T57
Test name
Test status
Simulation time 27684651 ps
CPU time 0.99 seconds
Started Apr 28 04:29:58 PM PDT 24
Finished Apr 28 04:29:59 PM PDT 24
Peak memory 223656 kb
Host smart-3e7c6a98-2554-4d11-a3e6-7eb67f460626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779247005 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1779247005
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2949612993
Short name T317
Test name
Test status
Simulation time 48242314 ps
CPU time 1.29 seconds
Started Apr 28 04:30:00 PM PDT 24
Finished Apr 28 04:30:02 PM PDT 24
Peak memory 218120 kb
Host smart-c0615876-9c7f-465a-ab3f-ff57577c6d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949612993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2949612993
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.2762244448
Short name T612
Test name
Test status
Simulation time 126809120 ps
CPU time 0.97 seconds
Started Apr 28 04:30:00 PM PDT 24
Finished Apr 28 04:30:02 PM PDT 24
Peak memory 218148 kb
Host smart-b7854a17-e776-4a44-bebe-b7e856d535bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762244448 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2762244448
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2657828141
Short name T289
Test name
Test status
Simulation time 49877733 ps
CPU time 1.95 seconds
Started Apr 28 04:29:59 PM PDT 24
Finished Apr 28 04:30:01 PM PDT 24
Peak memory 218232 kb
Host smart-3bf1429e-a8de-42d6-a82a-bd37a99cfe8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657828141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2657828141
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.405852321
Short name T787
Test name
Test status
Simulation time 24265356 ps
CPU time 1.36 seconds
Started Apr 28 04:29:59 PM PDT 24
Finished Apr 28 04:30:01 PM PDT 24
Peak memory 223972 kb
Host smart-1927e9f3-f4eb-4f9a-a46e-77d33fc3a0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405852321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.405852321
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1834547661
Short name T682
Test name
Test status
Simulation time 144471176 ps
CPU time 1.7 seconds
Started Apr 28 04:29:58 PM PDT 24
Finished Apr 28 04:30:01 PM PDT 24
Peak memory 218516 kb
Host smart-7e608a7b-d2f2-43e1-a666-d2c3e7e90e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834547661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1834547661
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.4024563313
Short name T125
Test name
Test status
Simulation time 29888273 ps
CPU time 0.89 seconds
Started Apr 28 04:30:00 PM PDT 24
Finished Apr 28 04:30:02 PM PDT 24
Peak memory 218152 kb
Host smart-f02c3e58-66ac-4bac-97e6-aa316cf490a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024563313 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.4024563313
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1317490719
Short name T296
Test name
Test status
Simulation time 193202529 ps
CPU time 3.79 seconds
Started Apr 28 04:29:59 PM PDT 24
Finished Apr 28 04:30:03 PM PDT 24
Peak memory 219820 kb
Host smart-70fe2496-b7f3-470f-b4af-e7e957377474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317490719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1317490719
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.2898791103
Short name T115
Test name
Test status
Simulation time 46879546 ps
CPU time 1.48 seconds
Started Apr 28 04:29:59 PM PDT 24
Finished Apr 28 04:30:01 PM PDT 24
Peak memory 229532 kb
Host smart-e2d3ea54-d7eb-4062-9e02-c98465688753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898791103 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2898791103
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3873367181
Short name T281
Test name
Test status
Simulation time 52217382 ps
CPU time 1.36 seconds
Started Apr 28 04:30:00 PM PDT 24
Finished Apr 28 04:30:02 PM PDT 24
Peak memory 218172 kb
Host smart-9056dcf5-7cba-4c11-a0a3-c58a703f47de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873367181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3873367181
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.3417952889
Short name T445
Test name
Test status
Simulation time 18142426 ps
CPU time 1.17 seconds
Started Apr 28 04:30:01 PM PDT 24
Finished Apr 28 04:30:02 PM PDT 24
Peak memory 215276 kb
Host smart-ea40d3ee-b68b-47b9-ad31-9b78ac999a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417952889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3417952889
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.4228049480
Short name T538
Test name
Test status
Simulation time 71370552 ps
CPU time 1.45 seconds
Started Apr 28 04:30:01 PM PDT 24
Finished Apr 28 04:30:03 PM PDT 24
Peak memory 219156 kb
Host smart-98110b88-a25d-47a6-a9e0-17d4658115b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228049480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.4228049480
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.1541264121
Short name T103
Test name
Test status
Simulation time 52609717 ps
CPU time 1.5 seconds
Started Apr 28 04:30:04 PM PDT 24
Finished Apr 28 04:30:05 PM PDT 24
Peak memory 234240 kb
Host smart-0e086423-091b-4601-a710-e65d56dbc8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541264121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1541264121
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1196814512
Short name T398
Test name
Test status
Simulation time 78616031 ps
CPU time 1.45 seconds
Started Apr 28 04:30:05 PM PDT 24
Finished Apr 28 04:30:07 PM PDT 24
Peak memory 217956 kb
Host smart-90cff9a2-7046-40c4-ba91-b32d44251910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196814512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1196814512
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.2218957804
Short name T56
Test name
Test status
Simulation time 79386295 ps
CPU time 1.32 seconds
Started Apr 28 04:30:06 PM PDT 24
Finished Apr 28 04:30:08 PM PDT 24
Peak memory 225532 kb
Host smart-fae433a1-6c63-4940-93a8-4234d5308d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218957804 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2218957804
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.119905009
Short name T515
Test name
Test status
Simulation time 34631228 ps
CPU time 1.37 seconds
Started Apr 28 04:30:07 PM PDT 24
Finished Apr 28 04:30:09 PM PDT 24
Peak memory 216748 kb
Host smart-2dd0e6fb-789d-412b-a68d-368a0efbe026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119905009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.119905009
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.1839999194
Short name T646
Test name
Test status
Simulation time 75725082 ps
CPU time 1.08 seconds
Started Apr 28 04:30:04 PM PDT 24
Finished Apr 28 04:30:05 PM PDT 24
Peak memory 219508 kb
Host smart-daf7c2f8-e13f-433f-81e3-4171c84c4854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839999194 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1839999194
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.375808424
Short name T2
Test name
Test status
Simulation time 60600933 ps
CPU time 1.23 seconds
Started Apr 28 04:30:05 PM PDT 24
Finished Apr 28 04:30:07 PM PDT 24
Peak memory 219764 kb
Host smart-3e8e7c1d-9547-493b-bb1b-ba215f01e2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375808424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.375808424
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert_test.616486855
Short name T482
Test name
Test status
Simulation time 41066594 ps
CPU time 0.94 seconds
Started Apr 28 04:28:02 PM PDT 24
Finished Apr 28 04:28:03 PM PDT 24
Peak memory 214592 kb
Host smart-d45f5bc2-2142-4eca-a287-f2e97f6c2440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616486855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.616486855
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2579313395
Short name T299
Test name
Test status
Simulation time 43854634 ps
CPU time 0.92 seconds
Started Apr 28 04:28:00 PM PDT 24
Finished Apr 28 04:28:02 PM PDT 24
Peak memory 215764 kb
Host smart-bbc76b45-7687-479a-acff-97ccfb164456
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579313395 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2579313395
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.962374178
Short name T508
Test name
Test status
Simulation time 80393261 ps
CPU time 1.11 seconds
Started Apr 28 04:28:01 PM PDT 24
Finished Apr 28 04:28:02 PM PDT 24
Peak memory 219304 kb
Host smart-5b6553e8-2695-409b-b7c8-02ac38ae97ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962374178 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.962374178
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3356640025
Short name T120
Test name
Test status
Simulation time 25272842 ps
CPU time 1.25 seconds
Started Apr 28 04:28:05 PM PDT 24
Finished Apr 28 04:28:07 PM PDT 24
Peak memory 220320 kb
Host smart-2b3e867f-ed70-4058-9027-79cfb83be245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356640025 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3356640025
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1708323636
Short name T279
Test name
Test status
Simulation time 76368981 ps
CPU time 1.27 seconds
Started Apr 28 04:28:01 PM PDT 24
Finished Apr 28 04:28:02 PM PDT 24
Peak memory 216780 kb
Host smart-eb97ba84-d45b-4b4c-a6ab-8513c4fa0529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708323636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1708323636
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.321582422
Short name T824
Test name
Test status
Simulation time 22147443 ps
CPU time 1.17 seconds
Started Apr 28 04:28:08 PM PDT 24
Finished Apr 28 04:28:10 PM PDT 24
Peak memory 215424 kb
Host smart-dc04d8ee-5ea4-48d6-bee3-e55aa26a12b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321582422 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.321582422
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2081059183
Short name T694
Test name
Test status
Simulation time 16550403 ps
CPU time 1.02 seconds
Started Apr 28 04:28:02 PM PDT 24
Finished Apr 28 04:28:03 PM PDT 24
Peak memory 206964 kb
Host smart-c70fb541-5a4a-47a3-a944-494cfc667b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081059183 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2081059183
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.349194715
Short name T844
Test name
Test status
Simulation time 16848160 ps
CPU time 1.02 seconds
Started Apr 28 04:27:57 PM PDT 24
Finished Apr 28 04:27:58 PM PDT 24
Peak memory 215212 kb
Host smart-316ae916-6959-44da-b0b0-7e12ff648711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349194715 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.349194715
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.574052824
Short name T468
Test name
Test status
Simulation time 1659413305 ps
CPU time 4.14 seconds
Started Apr 28 04:28:08 PM PDT 24
Finished Apr 28 04:28:12 PM PDT 24
Peak memory 215236 kb
Host smart-62611ba0-3a75-4531-839d-b9068ee8d298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574052824 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.574052824
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.66737068
Short name T189
Test name
Test status
Simulation time 546791575011 ps
CPU time 1302.93 seconds
Started Apr 28 04:28:08 PM PDT 24
Finished Apr 28 04:49:52 PM PDT 24
Peak memory 222848 kb
Host smart-cb21a780-af08-4471-a9e4-1b8921d6f13d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66737068 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.66737068
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.3319783784
Short name T549
Test name
Test status
Simulation time 23128102 ps
CPU time 1.1 seconds
Started Apr 28 04:30:05 PM PDT 24
Finished Apr 28 04:30:06 PM PDT 24
Peak memory 218428 kb
Host smart-feb49657-7dd1-49f1-a3b2-9c2576d582cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319783784 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3319783784
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2234859516
Short name T598
Test name
Test status
Simulation time 38934689 ps
CPU time 1.31 seconds
Started Apr 28 04:30:04 PM PDT 24
Finished Apr 28 04:30:06 PM PDT 24
Peak memory 218364 kb
Host smart-a8be5464-14bd-4a63-8f00-7732cdccafdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234859516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2234859516
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.1997985555
Short name T121
Test name
Test status
Simulation time 27046907 ps
CPU time 1.23 seconds
Started Apr 28 04:30:06 PM PDT 24
Finished Apr 28 04:30:08 PM PDT 24
Peak memory 220312 kb
Host smart-4c3a0f51-ecd0-4718-ad1b-ac4a33c30cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997985555 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1997985555
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1764862287
Short name T615
Test name
Test status
Simulation time 81992554 ps
CPU time 1.19 seconds
Started Apr 28 04:30:04 PM PDT 24
Finished Apr 28 04:30:06 PM PDT 24
Peak memory 217060 kb
Host smart-6326168f-abfe-4289-a6aa-c07e2c83e690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764862287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1764862287
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.1527958176
Short name T168
Test name
Test status
Simulation time 19952165 ps
CPU time 1.27 seconds
Started Apr 28 04:30:03 PM PDT 24
Finished Apr 28 04:30:05 PM PDT 24
Peak memory 224000 kb
Host smart-9c130df3-c51e-42eb-bd95-d7d8a6c2bbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527958176 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1527958176
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.907523430
Short name T748
Test name
Test status
Simulation time 29566430 ps
CPU time 1.35 seconds
Started Apr 28 04:30:08 PM PDT 24
Finished Apr 28 04:30:10 PM PDT 24
Peak memory 217328 kb
Host smart-f9e9f9a5-b4a7-4005-8974-26c2fb5a965b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907523430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.907523430
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_genbits.4172522830
Short name T728
Test name
Test status
Simulation time 99144185 ps
CPU time 1.64 seconds
Started Apr 28 04:30:04 PM PDT 24
Finished Apr 28 04:30:06 PM PDT 24
Peak memory 217968 kb
Host smart-c68bb457-1447-4bef-a3e6-a65fa7969e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172522830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.4172522830
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.3276525657
Short name T128
Test name
Test status
Simulation time 24481914 ps
CPU time 1.06 seconds
Started Apr 28 04:30:03 PM PDT 24
Finished Apr 28 04:30:05 PM PDT 24
Peak memory 218464 kb
Host smart-964f6121-8064-42ac-939b-b6800eb3acca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276525657 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3276525657
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.469038248
Short name T303
Test name
Test status
Simulation time 103572182 ps
CPU time 1.1 seconds
Started Apr 28 04:30:03 PM PDT 24
Finished Apr 28 04:30:04 PM PDT 24
Peak memory 216740 kb
Host smart-acca763a-3210-4bb4-9405-9210001e3a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469038248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.469038248
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.3536448254
Short name T785
Test name
Test status
Simulation time 77027204 ps
CPU time 1.11 seconds
Started Apr 28 04:30:04 PM PDT 24
Finished Apr 28 04:30:06 PM PDT 24
Peak memory 219708 kb
Host smart-cf3141fa-d9f4-4051-8663-9f59878481b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536448254 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3536448254
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.986369958
Short name T803
Test name
Test status
Simulation time 39781218 ps
CPU time 1.59 seconds
Started Apr 28 04:30:04 PM PDT 24
Finished Apr 28 04:30:06 PM PDT 24
Peak memory 217120 kb
Host smart-a5c05d6d-3768-47d6-a010-0f8376a09d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986369958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.986369958
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.375147868
Short name T712
Test name
Test status
Simulation time 34090685 ps
CPU time 0.92 seconds
Started Apr 28 04:30:03 PM PDT 24
Finished Apr 28 04:30:04 PM PDT 24
Peak memory 218164 kb
Host smart-034d931e-7e7d-403d-8200-3381d19e2652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375147868 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.375147868
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2023091370
Short name T465
Test name
Test status
Simulation time 150584096 ps
CPU time 1.53 seconds
Started Apr 28 04:30:03 PM PDT 24
Finished Apr 28 04:30:05 PM PDT 24
Peak memory 218344 kb
Host smart-0df75940-c3cb-4ac2-93bf-570e7100b402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023091370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2023091370
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.2225348444
Short name T389
Test name
Test status
Simulation time 32965757 ps
CPU time 0.91 seconds
Started Apr 28 04:30:07 PM PDT 24
Finished Apr 28 04:30:09 PM PDT 24
Peak memory 217944 kb
Host smart-015b0883-403a-4c52-833e-8aec65f23116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225348444 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2225348444
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2641306627
Short name T270
Test name
Test status
Simulation time 28265696 ps
CPU time 1.4 seconds
Started Apr 28 04:30:03 PM PDT 24
Finished Apr 28 04:30:05 PM PDT 24
Peak memory 217040 kb
Host smart-867407fd-17d6-4896-a434-1185d0a462d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641306627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2641306627
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.1337341445
Short name T108
Test name
Test status
Simulation time 62958910 ps
CPU time 0.99 seconds
Started Apr 28 04:30:04 PM PDT 24
Finished Apr 28 04:30:06 PM PDT 24
Peak memory 219284 kb
Host smart-dbebbcdb-eb69-48ea-8fcc-881d67043a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337341445 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1337341445
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3001518645
Short name T744
Test name
Test status
Simulation time 143210254 ps
CPU time 3.13 seconds
Started Apr 28 04:30:07 PM PDT 24
Finished Apr 28 04:30:11 PM PDT 24
Peak memory 218140 kb
Host smart-515cc45b-abcf-4d3a-af75-217e9d214f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001518645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3001518645
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.2465936032
Short name T72
Test name
Test status
Simulation time 26785673 ps
CPU time 0.9 seconds
Started Apr 28 04:30:07 PM PDT 24
Finished Apr 28 04:30:09 PM PDT 24
Peak memory 218048 kb
Host smart-e9c9c103-02f9-4f22-90b4-78cd34c75a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465936032 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2465936032
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.208486514
Short name T709
Test name
Test status
Simulation time 39222336 ps
CPU time 1.5 seconds
Started Apr 28 04:30:06 PM PDT 24
Finished Apr 28 04:30:08 PM PDT 24
Peak memory 218172 kb
Host smart-9ab79a04-7d6a-4d8c-8036-8359402bb6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208486514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.208486514
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3409851278
Short name T697
Test name
Test status
Simulation time 28431653 ps
CPU time 1.39 seconds
Started Apr 28 04:28:05 PM PDT 24
Finished Apr 28 04:28:07 PM PDT 24
Peak memory 215576 kb
Host smart-30b8dd93-8b5b-470d-9918-f251f9b1b038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409851278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3409851278
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.4121056249
Short name T447
Test name
Test status
Simulation time 27632449 ps
CPU time 0.82 seconds
Started Apr 28 04:28:05 PM PDT 24
Finished Apr 28 04:28:06 PM PDT 24
Peak memory 206232 kb
Host smart-ac538c48-e2d6-410d-8303-12721409b58d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121056249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.4121056249
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.958897721
Short name T626
Test name
Test status
Simulation time 12906081 ps
CPU time 0.97 seconds
Started Apr 28 04:28:07 PM PDT 24
Finished Apr 28 04:28:09 PM PDT 24
Peak memory 215980 kb
Host smart-e604d01f-e837-4867-abdb-d44551ef7e3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958897721 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.958897721
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3828072414
Short name T792
Test name
Test status
Simulation time 22223976 ps
CPU time 1.15 seconds
Started Apr 28 04:28:01 PM PDT 24
Finished Apr 28 04:28:03 PM PDT 24
Peak memory 217904 kb
Host smart-918bba97-0c58-4b96-8c8f-ac23acfa8337
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828072414 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3828072414
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3163057601
Short name T811
Test name
Test status
Simulation time 25548348 ps
CPU time 1.3 seconds
Started Apr 28 04:28:01 PM PDT 24
Finished Apr 28 04:28:03 PM PDT 24
Peak memory 220392 kb
Host smart-e85d4ad6-f1df-4f6e-b874-eb388a648340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163057601 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3163057601
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1193459605
Short name T843
Test name
Test status
Simulation time 38345746 ps
CPU time 1.78 seconds
Started Apr 28 04:28:01 PM PDT 24
Finished Apr 28 04:28:04 PM PDT 24
Peak memory 217056 kb
Host smart-518d3d16-175c-4d3f-b4d7-900b97e0fd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193459605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1193459605
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.4129701749
Short name T823
Test name
Test status
Simulation time 31457887 ps
CPU time 0.93 seconds
Started Apr 28 04:28:00 PM PDT 24
Finished Apr 28 04:28:01 PM PDT 24
Peak memory 215256 kb
Host smart-bfd01752-15e6-493c-afe0-dfcbc9319677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129701749 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.4129701749
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.2988542757
Short name T256
Test name
Test status
Simulation time 32151681 ps
CPU time 0.94 seconds
Started Apr 28 04:28:07 PM PDT 24
Finished Apr 28 04:28:09 PM PDT 24
Peak memory 206948 kb
Host smart-243473e1-d51a-4fa2-932e-75a11dd8d13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988542757 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2988542757
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1858852099
Short name T533
Test name
Test status
Simulation time 28209317 ps
CPU time 0.98 seconds
Started Apr 28 04:28:01 PM PDT 24
Finished Apr 28 04:28:02 PM PDT 24
Peak memory 215136 kb
Host smart-4749ed43-a8fa-4907-bb5a-f2d3ab07a2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858852099 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1858852099
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.448284424
Short name T713
Test name
Test status
Simulation time 548177935 ps
CPU time 3.57 seconds
Started Apr 28 04:28:01 PM PDT 24
Finished Apr 28 04:28:05 PM PDT 24
Peak memory 215188 kb
Host smart-4e5e0fef-3e82-45b9-9e12-32e73ebcb77c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448284424 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.448284424
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.237866046
Short name T326
Test name
Test status
Simulation time 325202136407 ps
CPU time 2235.59 seconds
Started Apr 28 04:28:07 PM PDT 24
Finished Apr 28 05:05:23 PM PDT 24
Peak memory 229964 kb
Host smart-80fd9b0f-9fdc-43cf-a100-837579c274b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237866046 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.237866046
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.471476855
Short name T140
Test name
Test status
Simulation time 31572210 ps
CPU time 0.96 seconds
Started Apr 28 04:30:03 PM PDT 24
Finished Apr 28 04:30:04 PM PDT 24
Peak memory 218072 kb
Host smart-f90323c6-bc13-4d68-8c27-1ef31fd3eca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471476855 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.471476855
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.548138836
Short name T467
Test name
Test status
Simulation time 171216982 ps
CPU time 2.18 seconds
Started Apr 28 04:30:07 PM PDT 24
Finished Apr 28 04:30:10 PM PDT 24
Peak memory 219800 kb
Host smart-4fa86980-52d3-4d9e-88d0-adcf4770b5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548138836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.548138836
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.2795744980
Short name T211
Test name
Test status
Simulation time 42688051 ps
CPU time 1.15 seconds
Started Apr 28 04:30:09 PM PDT 24
Finished Apr 28 04:30:10 PM PDT 24
Peak memory 219468 kb
Host smart-d51d150d-f99d-465f-a72b-15a2a0b6506b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795744980 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2795744980
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2202343667
Short name T537
Test name
Test status
Simulation time 39001298 ps
CPU time 1.31 seconds
Started Apr 28 04:30:09 PM PDT 24
Finished Apr 28 04:30:11 PM PDT 24
Peak memory 215204 kb
Host smart-079055da-ab2c-4082-acbe-0b8b7ea09716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202343667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2202343667
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.1791547151
Short name T301
Test name
Test status
Simulation time 19539451 ps
CPU time 1.05 seconds
Started Apr 28 04:30:08 PM PDT 24
Finished Apr 28 04:30:09 PM PDT 24
Peak memory 218244 kb
Host smart-caa93b4a-81a1-461b-8742-9efd33e84ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791547151 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1791547151
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1042635775
Short name T42
Test name
Test status
Simulation time 145101286 ps
CPU time 1.78 seconds
Started Apr 28 04:30:08 PM PDT 24
Finished Apr 28 04:30:10 PM PDT 24
Peak memory 218516 kb
Host smart-f174deb5-8c30-4812-a36f-32520fc6aff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042635775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1042635775
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.2626974626
Short name T137
Test name
Test status
Simulation time 21485951 ps
CPU time 0.96 seconds
Started Apr 28 04:30:08 PM PDT 24
Finished Apr 28 04:30:10 PM PDT 24
Peak memory 218384 kb
Host smart-6e92c4cb-b2c8-4452-9476-f73ebdee912d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626974626 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2626974626
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.795672248
Short name T613
Test name
Test status
Simulation time 65274741 ps
CPU time 1.15 seconds
Started Apr 28 04:30:08 PM PDT 24
Finished Apr 28 04:30:10 PM PDT 24
Peak memory 217108 kb
Host smart-121d2527-fca0-4de6-89ab-203af7c95757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795672248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.795672248
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.1801033433
Short name T595
Test name
Test status
Simulation time 20205148 ps
CPU time 1.13 seconds
Started Apr 28 04:30:10 PM PDT 24
Finished Apr 28 04:30:11 PM PDT 24
Peak memory 218244 kb
Host smart-d93ba6ed-9cbe-4b40-972e-9d2f515706fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801033433 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1801033433
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2038539523
Short name T689
Test name
Test status
Simulation time 25961121 ps
CPU time 1.23 seconds
Started Apr 28 04:30:09 PM PDT 24
Finished Apr 28 04:30:11 PM PDT 24
Peak memory 218208 kb
Host smart-0a648a57-8ac2-441a-b742-e88e1e96f701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038539523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2038539523
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.2923823734
Short name T581
Test name
Test status
Simulation time 20195928 ps
CPU time 1.26 seconds
Started Apr 28 04:30:10 PM PDT 24
Finished Apr 28 04:30:12 PM PDT 24
Peak memory 223916 kb
Host smart-2144f868-9b0f-45c5-ad4f-9f17c89a781f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923823734 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2923823734
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3810587407
Short name T205
Test name
Test status
Simulation time 39901728 ps
CPU time 1.17 seconds
Started Apr 28 04:30:08 PM PDT 24
Finished Apr 28 04:30:10 PM PDT 24
Peak memory 218316 kb
Host smart-0d6ba5fb-95ab-43ef-be85-3971ac24ba46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810587407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3810587407
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1138584609
Short name T762
Test name
Test status
Simulation time 35378308 ps
CPU time 1.25 seconds
Started Apr 28 04:30:08 PM PDT 24
Finished Apr 28 04:30:10 PM PDT 24
Peak memory 223920 kb
Host smart-0b258363-6e81-4fb1-8580-c26dcfd62eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138584609 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1138584609
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.390284703
Short name T450
Test name
Test status
Simulation time 43194817 ps
CPU time 1.16 seconds
Started Apr 28 04:30:08 PM PDT 24
Finished Apr 28 04:30:09 PM PDT 24
Peak memory 217044 kb
Host smart-787575f8-b22b-466a-b717-f036cc17f51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390284703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.390284703
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.567039875
Short name T782
Test name
Test status
Simulation time 36074538 ps
CPU time 0.88 seconds
Started Apr 28 04:30:08 PM PDT 24
Finished Apr 28 04:30:09 PM PDT 24
Peak memory 217800 kb
Host smart-55b56571-f14b-4e16-a3bb-71fa701ca4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567039875 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.567039875
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.447577215
Short name T752
Test name
Test status
Simulation time 118909212 ps
CPU time 1.41 seconds
Started Apr 28 04:30:09 PM PDT 24
Finished Apr 28 04:30:11 PM PDT 24
Peak memory 218780 kb
Host smart-dc45a614-ae0a-4b36-b8f6-09ea8b180c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447577215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.447577215
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.2402267432
Short name T95
Test name
Test status
Simulation time 26018718 ps
CPU time 1.26 seconds
Started Apr 28 04:30:08 PM PDT 24
Finished Apr 28 04:30:10 PM PDT 24
Peak memory 220412 kb
Host smart-9aceecd8-3d53-442e-b9c1-3d99896ebe5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402267432 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2402267432
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1750333359
Short name T560
Test name
Test status
Simulation time 56973799 ps
CPU time 1.59 seconds
Started Apr 28 04:30:08 PM PDT 24
Finished Apr 28 04:30:11 PM PDT 24
Peak memory 217108 kb
Host smart-87812c1a-1d70-4586-974a-3dc6feec9317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750333359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1750333359
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.508903301
Short name T634
Test name
Test status
Simulation time 30481480 ps
CPU time 1.08 seconds
Started Apr 28 04:30:11 PM PDT 24
Finished Apr 28 04:30:12 PM PDT 24
Peak memory 219724 kb
Host smart-2b97ca30-1f68-46e1-a213-440375d78723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508903301 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.508903301
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2008722512
Short name T793
Test name
Test status
Simulation time 33677739 ps
CPU time 1.35 seconds
Started Apr 28 04:30:09 PM PDT 24
Finished Apr 28 04:30:11 PM PDT 24
Peak memory 218128 kb
Host smart-f3c19f1e-80c7-460f-beaf-b06a8a0a0926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008722512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2008722512
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1114500057
Short name T260
Test name
Test status
Simulation time 101317765 ps
CPU time 1.19 seconds
Started Apr 28 04:28:05 PM PDT 24
Finished Apr 28 04:28:07 PM PDT 24
Peak memory 215492 kb
Host smart-8f644af9-26b4-43ce-bd77-ad1abdf12bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114500057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1114500057
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2644709310
Short name T410
Test name
Test status
Simulation time 103041270 ps
CPU time 0.88 seconds
Started Apr 28 04:28:07 PM PDT 24
Finished Apr 28 04:28:08 PM PDT 24
Peak memory 215108 kb
Host smart-5e2d0efa-3685-4f0a-bcc0-081cdb978ec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644709310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2644709310
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.899792822
Short name T671
Test name
Test status
Simulation time 17866819 ps
CPU time 0.9 seconds
Started Apr 28 04:28:09 PM PDT 24
Finished Apr 28 04:28:10 PM PDT 24
Peak memory 215260 kb
Host smart-61b1e0d4-055d-4036-aa07-330f13312b66
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899792822 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.899792822
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3833091214
Short name T794
Test name
Test status
Simulation time 18010471 ps
CPU time 1.05 seconds
Started Apr 28 04:28:06 PM PDT 24
Finished Apr 28 04:28:08 PM PDT 24
Peak memory 217984 kb
Host smart-c4d95cd9-90fc-4ecb-b1f7-25a6292f66fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833091214 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3833091214
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.982928271
Short name T763
Test name
Test status
Simulation time 27978920 ps
CPU time 0.88 seconds
Started Apr 28 04:28:06 PM PDT 24
Finished Apr 28 04:28:07 PM PDT 24
Peak memory 218028 kb
Host smart-d1c6adfa-5804-4008-b745-1b3dd6022b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982928271 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.982928271
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1058105470
Short name T593
Test name
Test status
Simulation time 43491837 ps
CPU time 1.86 seconds
Started Apr 28 04:28:08 PM PDT 24
Finished Apr 28 04:28:10 PM PDT 24
Peak memory 218112 kb
Host smart-04748e83-dc16-45cb-a0d9-6a042020e873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058105470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1058105470
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2773998915
Short name T528
Test name
Test status
Simulation time 23572978 ps
CPU time 0.99 seconds
Started Apr 28 04:28:08 PM PDT 24
Finished Apr 28 04:28:09 PM PDT 24
Peak memory 215932 kb
Host smart-0eec0d36-a495-4101-9589-40533392666b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773998915 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2773998915
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.723975352
Short name T264
Test name
Test status
Simulation time 52707676 ps
CPU time 0.96 seconds
Started Apr 28 04:28:08 PM PDT 24
Finished Apr 28 04:28:10 PM PDT 24
Peak memory 206956 kb
Host smart-efa8f428-aa80-45b3-8915-3f040a2db06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723975352 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.723975352
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2677556615
Short name T379
Test name
Test status
Simulation time 24332213 ps
CPU time 1 seconds
Started Apr 28 04:28:08 PM PDT 24
Finished Apr 28 04:28:10 PM PDT 24
Peak memory 215188 kb
Host smart-61939212-634b-474c-8e4e-c9dc8cd6e153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677556615 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2677556615
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.553785873
Short name T160
Test name
Test status
Simulation time 294205515 ps
CPU time 2.43 seconds
Started Apr 28 04:28:07 PM PDT 24
Finished Apr 28 04:28:10 PM PDT 24
Peak memory 216792 kb
Host smart-c6534f9d-4d44-4410-b4c9-768c1ad1fdf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553785873 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.553785873
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2589303419
Short name T67
Test name
Test status
Simulation time 53462873102 ps
CPU time 342.36 seconds
Started Apr 28 04:28:05 PM PDT 24
Finished Apr 28 04:33:48 PM PDT 24
Peak memory 218332 kb
Host smart-f3769d67-357f-4a9b-b227-9fa083182173
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589303419 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2589303419
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.135348711
Short name T348
Test name
Test status
Simulation time 22492023 ps
CPU time 1.12 seconds
Started Apr 28 04:30:11 PM PDT 24
Finished Apr 28 04:30:12 PM PDT 24
Peak memory 219728 kb
Host smart-2e7c2d02-0067-430e-bffa-8f70d83f95e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135348711 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.135348711
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/91.edn_err.100929455
Short name T754
Test name
Test status
Simulation time 21930040 ps
CPU time 0.98 seconds
Started Apr 28 04:30:13 PM PDT 24
Finished Apr 28 04:30:14 PM PDT 24
Peak memory 218236 kb
Host smart-6a7f903b-5921-43ad-870c-99993a73d534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100929455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.100929455
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2231866483
Short name T473
Test name
Test status
Simulation time 206798333 ps
CPU time 1.19 seconds
Started Apr 28 04:30:11 PM PDT 24
Finished Apr 28 04:30:13 PM PDT 24
Peak memory 217024 kb
Host smart-6979b47a-18ad-49a4-b7a8-a9896a58745d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231866483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2231866483
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.1919959753
Short name T436
Test name
Test status
Simulation time 45377293 ps
CPU time 1.2 seconds
Started Apr 28 04:30:15 PM PDT 24
Finished Apr 28 04:30:17 PM PDT 24
Peak memory 219712 kb
Host smart-0b2fbafa-8129-488d-8eff-e22c3eba2265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919959753 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1919959753
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2394861578
Short name T278
Test name
Test status
Simulation time 34830967 ps
CPU time 1.47 seconds
Started Apr 28 04:30:11 PM PDT 24
Finished Apr 28 04:30:13 PM PDT 24
Peak memory 217068 kb
Host smart-f419b303-b996-470e-a88c-9dd5ef9c12ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394861578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2394861578
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.3482306241
Short name T98
Test name
Test status
Simulation time 22723560 ps
CPU time 1.17 seconds
Started Apr 28 04:30:12 PM PDT 24
Finished Apr 28 04:30:14 PM PDT 24
Peak memory 219444 kb
Host smart-17e11e12-1afb-43ba-a508-c4ce988b101b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482306241 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3482306241
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2246438673
Short name T456
Test name
Test status
Simulation time 305435249 ps
CPU time 3.27 seconds
Started Apr 28 04:30:13 PM PDT 24
Finished Apr 28 04:30:17 PM PDT 24
Peak memory 217044 kb
Host smart-e3e71ef6-0be4-4bc5-bc5d-48fe3b22f081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246438673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2246438673
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.2415194035
Short name T655
Test name
Test status
Simulation time 35699388 ps
CPU time 0.99 seconds
Started Apr 28 04:30:12 PM PDT 24
Finished Apr 28 04:30:14 PM PDT 24
Peak memory 223680 kb
Host smart-ea4316ef-f854-4bf7-ad56-97904da2197c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415194035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2415194035
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3270647604
Short name T290
Test name
Test status
Simulation time 95100039 ps
CPU time 1.25 seconds
Started Apr 28 04:30:13 PM PDT 24
Finished Apr 28 04:30:14 PM PDT 24
Peak memory 218384 kb
Host smart-4800bcef-d24c-486b-b40d-97e430d2ff41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270647604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3270647604
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.198249516
Short name T575
Test name
Test status
Simulation time 42101165 ps
CPU time 0.87 seconds
Started Apr 28 04:30:17 PM PDT 24
Finished Apr 28 04:30:18 PM PDT 24
Peak memory 217784 kb
Host smart-bd70d066-3185-44af-8c03-1c5df2ee885b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198249516 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.198249516
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2764670873
Short name T390
Test name
Test status
Simulation time 69834119 ps
CPU time 1.09 seconds
Started Apr 28 04:30:15 PM PDT 24
Finished Apr 28 04:30:17 PM PDT 24
Peak memory 216980 kb
Host smart-1f227ae9-7392-4b83-a455-a293b2cfb8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764670873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2764670873
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3328205864
Short name T639
Test name
Test status
Simulation time 19067476 ps
CPU time 1.21 seconds
Started Apr 28 04:30:16 PM PDT 24
Finished Apr 28 04:30:18 PM PDT 24
Peak memory 218004 kb
Host smart-5f708081-e2fb-4e04-af23-215ae6f146fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328205864 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3328205864
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.956889225
Short name T43
Test name
Test status
Simulation time 116628977 ps
CPU time 2.51 seconds
Started Apr 28 04:30:16 PM PDT 24
Finished Apr 28 04:30:19 PM PDT 24
Peak memory 219148 kb
Host smart-0117e9a1-6c1a-4693-b225-706ac7b41394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956889225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.956889225
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.1517566585
Short name T836
Test name
Test status
Simulation time 25617166 ps
CPU time 1.24 seconds
Started Apr 28 04:30:17 PM PDT 24
Finished Apr 28 04:30:19 PM PDT 24
Peak memory 218360 kb
Host smart-040a43dd-37ec-4fec-9ded-e34c7fa4b6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517566585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1517566585
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2668944504
Short name T817
Test name
Test status
Simulation time 86708745 ps
CPU time 1.35 seconds
Started Apr 28 04:30:19 PM PDT 24
Finished Apr 28 04:30:21 PM PDT 24
Peak memory 218724 kb
Host smart-ac1e1a90-a707-4fdd-b2c7-df29a9c33a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668944504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2668944504
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1724771406
Short name T129
Test name
Test status
Simulation time 19047168 ps
CPU time 1.07 seconds
Started Apr 28 04:30:15 PM PDT 24
Finished Apr 28 04:30:17 PM PDT 24
Peak memory 218356 kb
Host smart-fe4dbde9-4a0c-4599-af24-5e5cce6317e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724771406 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1724771406
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1226659511
Short name T568
Test name
Test status
Simulation time 65816386 ps
CPU time 1.75 seconds
Started Apr 28 04:30:18 PM PDT 24
Finished Apr 28 04:30:20 PM PDT 24
Peak memory 216968 kb
Host smart-7bab1b8b-3564-47b8-a4f2-de3c3c3a6b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226659511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1226659511
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.3007922892
Short name T109
Test name
Test status
Simulation time 51991662 ps
CPU time 1.17 seconds
Started Apr 28 04:30:15 PM PDT 24
Finished Apr 28 04:30:16 PM PDT 24
Peak memory 229500 kb
Host smart-83d68d1e-8dea-46af-807f-ba7a87c6be31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007922892 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3007922892
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1608796024
Short name T404
Test name
Test status
Simulation time 153250117 ps
CPU time 1.23 seconds
Started Apr 28 04:30:19 PM PDT 24
Finished Apr 28 04:30:20 PM PDT 24
Peak memory 216928 kb
Host smart-44e81a9a-b31b-4a6f-9177-a6031df03322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608796024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1608796024
Directory /workspace/99.edn_genbits/latest
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