Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.33 98.24 93.76 97.06 82.08 96.76 99.77 92.64


Total test records in report: 977
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T789 /workspace/coverage/default/221.edn_genbits.1771042867 Apr 30 02:44:53 PM PDT 24 Apr 30 02:44:55 PM PDT 24 57773410 ps
T790 /workspace/coverage/default/268.edn_genbits.1992411313 Apr 30 02:44:57 PM PDT 24 Apr 30 02:44:59 PM PDT 24 40160220 ps
T268 /workspace/coverage/default/5.edn_regwen.3182539463 Apr 30 02:43:06 PM PDT 24 Apr 30 02:43:08 PM PDT 24 19231803 ps
T791 /workspace/coverage/default/57.edn_genbits.2394020143 Apr 30 02:44:12 PM PDT 24 Apr 30 02:44:14 PM PDT 24 89767084 ps
T182 /workspace/coverage/default/9.edn_disable.2111680493 Apr 30 02:43:12 PM PDT 24 Apr 30 02:43:14 PM PDT 24 16064901 ps
T792 /workspace/coverage/default/6.edn_intr.3754329823 Apr 30 02:43:03 PM PDT 24 Apr 30 02:43:05 PM PDT 24 28400734 ps
T793 /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1318989462 Apr 30 02:43:17 PM PDT 24 Apr 30 03:08:16 PM PDT 24 56932750138 ps
T794 /workspace/coverage/default/4.edn_genbits.1363163431 Apr 30 02:43:01 PM PDT 24 Apr 30 02:43:03 PM PDT 24 31259089 ps
T795 /workspace/coverage/default/195.edn_genbits.2344140931 Apr 30 02:44:52 PM PDT 24 Apr 30 02:44:54 PM PDT 24 74720369 ps
T796 /workspace/coverage/default/99.edn_genbits.3920219452 Apr 30 02:44:31 PM PDT 24 Apr 30 02:44:34 PM PDT 24 90713960 ps
T797 /workspace/coverage/default/52.edn_err.2455332247 Apr 30 02:44:17 PM PDT 24 Apr 30 02:44:18 PM PDT 24 26931957 ps
T798 /workspace/coverage/default/41.edn_disable_auto_req_mode.2641917980 Apr 30 02:44:07 PM PDT 24 Apr 30 02:44:09 PM PDT 24 34985393 ps
T799 /workspace/coverage/default/17.edn_alert.339212919 Apr 30 02:43:27 PM PDT 24 Apr 30 02:43:29 PM PDT 24 28911990 ps
T800 /workspace/coverage/default/30.edn_stress_all.2272288668 Apr 30 02:43:57 PM PDT 24 Apr 30 02:44:03 PM PDT 24 244694613 ps
T801 /workspace/coverage/default/21.edn_stress_all.620242048 Apr 30 02:43:35 PM PDT 24 Apr 30 02:43:39 PM PDT 24 112485058 ps
T802 /workspace/coverage/default/34.edn_disable_auto_req_mode.3028190921 Apr 30 02:43:47 PM PDT 24 Apr 30 02:43:48 PM PDT 24 67322623 ps
T194 /workspace/coverage/default/40.edn_alert.366796322 Apr 30 02:43:57 PM PDT 24 Apr 30 02:44:00 PM PDT 24 69288155 ps
T803 /workspace/coverage/default/100.edn_genbits.3850885779 Apr 30 02:44:39 PM PDT 24 Apr 30 02:44:41 PM PDT 24 91786538 ps
T804 /workspace/coverage/default/33.edn_genbits.2833577855 Apr 30 02:43:46 PM PDT 24 Apr 30 02:43:48 PM PDT 24 49351656 ps
T805 /workspace/coverage/default/220.edn_genbits.2969301611 Apr 30 02:44:46 PM PDT 24 Apr 30 02:44:48 PM PDT 24 56862753 ps
T806 /workspace/coverage/default/20.edn_genbits.3817795796 Apr 30 02:43:28 PM PDT 24 Apr 30 02:43:30 PM PDT 24 52069691 ps
T807 /workspace/coverage/default/80.edn_genbits.861729929 Apr 30 02:44:20 PM PDT 24 Apr 30 02:44:22 PM PDT 24 89212562 ps
T808 /workspace/coverage/default/157.edn_genbits.3448529931 Apr 30 02:44:50 PM PDT 24 Apr 30 02:44:53 PM PDT 24 63340557 ps
T179 /workspace/coverage/default/45.edn_disable.4185681896 Apr 30 02:44:02 PM PDT 24 Apr 30 02:44:04 PM PDT 24 33183167 ps
T809 /workspace/coverage/default/30.edn_genbits.3978557757 Apr 30 02:43:49 PM PDT 24 Apr 30 02:43:51 PM PDT 24 84613837 ps
T810 /workspace/coverage/default/77.edn_err.913105928 Apr 30 02:44:26 PM PDT 24 Apr 30 02:44:28 PM PDT 24 19323645 ps
T811 /workspace/coverage/default/8.edn_err.2822582678 Apr 30 02:43:12 PM PDT 24 Apr 30 02:43:14 PM PDT 24 31353360 ps
T812 /workspace/coverage/default/147.edn_genbits.183244441 Apr 30 02:44:45 PM PDT 24 Apr 30 02:44:48 PM PDT 24 49719905 ps
T813 /workspace/coverage/default/92.edn_genbits.1637971054 Apr 30 02:44:29 PM PDT 24 Apr 30 02:44:31 PM PDT 24 104988764 ps
T814 /workspace/coverage/default/36.edn_genbits.928233070 Apr 30 02:43:57 PM PDT 24 Apr 30 02:43:59 PM PDT 24 91631853 ps
T815 /workspace/coverage/default/243.edn_genbits.231835085 Apr 30 02:44:57 PM PDT 24 Apr 30 02:45:02 PM PDT 24 267123391 ps
T816 /workspace/coverage/default/44.edn_intr.872803506 Apr 30 02:44:08 PM PDT 24 Apr 30 02:44:10 PM PDT 24 66020255 ps
T817 /workspace/coverage/default/25.edn_stress_all.2406254286 Apr 30 02:43:40 PM PDT 24 Apr 30 02:43:45 PM PDT 24 853883595 ps
T818 /workspace/coverage/default/242.edn_genbits.4139508062 Apr 30 02:44:57 PM PDT 24 Apr 30 02:44:58 PM PDT 24 50517896 ps
T819 /workspace/coverage/default/12.edn_genbits.208239702 Apr 30 02:43:17 PM PDT 24 Apr 30 02:43:19 PM PDT 24 61831071 ps
T820 /workspace/coverage/default/37.edn_genbits.1744410716 Apr 30 02:44:00 PM PDT 24 Apr 30 02:44:03 PM PDT 24 34980312 ps
T821 /workspace/coverage/default/14.edn_intr.224015562 Apr 30 02:43:19 PM PDT 24 Apr 30 02:43:21 PM PDT 24 19658209 ps
T67 /workspace/coverage/default/1.edn_sec_cm.3174392937 Apr 30 02:42:53 PM PDT 24 Apr 30 02:43:02 PM PDT 24 1901494973 ps
T822 /workspace/coverage/default/37.edn_alert.4273901494 Apr 30 02:44:04 PM PDT 24 Apr 30 02:44:06 PM PDT 24 43965987 ps
T823 /workspace/coverage/default/40.edn_smoke.3991804209 Apr 30 02:43:51 PM PDT 24 Apr 30 02:43:52 PM PDT 24 166590171 ps
T824 /workspace/coverage/default/31.edn_smoke.413659997 Apr 30 02:43:39 PM PDT 24 Apr 30 02:43:41 PM PDT 24 15917276 ps
T825 /workspace/coverage/default/15.edn_alert_test.1588576192 Apr 30 02:43:24 PM PDT 24 Apr 30 02:43:25 PM PDT 24 65609287 ps
T826 /workspace/coverage/default/144.edn_genbits.345670863 Apr 30 02:44:47 PM PDT 24 Apr 30 02:44:51 PM PDT 24 90783098 ps
T827 /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1665276229 Apr 30 02:43:31 PM PDT 24 Apr 30 03:03:06 PM PDT 24 101481995264 ps
T828 /workspace/coverage/default/24.edn_genbits.3374225385 Apr 30 02:43:32 PM PDT 24 Apr 30 02:43:35 PM PDT 24 123614623 ps
T829 /workspace/coverage/default/150.edn_genbits.2089899742 Apr 30 02:44:50 PM PDT 24 Apr 30 02:44:52 PM PDT 24 38888192 ps
T830 /workspace/coverage/default/177.edn_genbits.3209297125 Apr 30 02:44:46 PM PDT 24 Apr 30 02:44:49 PM PDT 24 103962646 ps
T831 /workspace/coverage/default/69.edn_genbits.1934919169 Apr 30 02:44:24 PM PDT 24 Apr 30 02:44:26 PM PDT 24 218140881 ps
T195 /workspace/coverage/default/35.edn_alert.1945955152 Apr 30 02:43:58 PM PDT 24 Apr 30 02:44:01 PM PDT 24 98461247 ps
T832 /workspace/coverage/default/5.edn_alert.300636629 Apr 30 02:43:03 PM PDT 24 Apr 30 02:43:06 PM PDT 24 84581366 ps
T833 /workspace/coverage/default/1.edn_err.649595813 Apr 30 02:42:55 PM PDT 24 Apr 30 02:42:57 PM PDT 24 37920207 ps
T834 /workspace/coverage/default/39.edn_intr.2023280707 Apr 30 02:43:54 PM PDT 24 Apr 30 02:43:56 PM PDT 24 87306545 ps
T835 /workspace/coverage/default/9.edn_smoke.744240069 Apr 30 02:43:11 PM PDT 24 Apr 30 02:43:13 PM PDT 24 27415783 ps
T836 /workspace/coverage/default/41.edn_genbits.2874983056 Apr 30 02:43:57 PM PDT 24 Apr 30 02:44:00 PM PDT 24 44802855 ps
T837 /workspace/coverage/default/106.edn_genbits.1677062243 Apr 30 02:44:28 PM PDT 24 Apr 30 02:44:30 PM PDT 24 54927875 ps
T838 /workspace/coverage/default/10.edn_smoke.3183158670 Apr 30 02:43:14 PM PDT 24 Apr 30 02:43:16 PM PDT 24 25947967 ps
T839 /workspace/coverage/default/11.edn_intr.176244544 Apr 30 02:43:20 PM PDT 24 Apr 30 02:43:22 PM PDT 24 27872948 ps
T840 /workspace/coverage/default/40.edn_disable_auto_req_mode.4116622115 Apr 30 02:43:56 PM PDT 24 Apr 30 02:43:58 PM PDT 24 47822324 ps
T841 /workspace/coverage/default/40.edn_genbits.1422848558 Apr 30 02:43:54 PM PDT 24 Apr 30 02:43:56 PM PDT 24 56992175 ps
T842 /workspace/coverage/default/28.edn_alert_test.2221858284 Apr 30 02:43:52 PM PDT 24 Apr 30 02:43:54 PM PDT 24 41662267 ps
T843 /workspace/coverage/default/8.edn_alert_test.1771935144 Apr 30 02:43:09 PM PDT 24 Apr 30 02:43:10 PM PDT 24 58687613 ps
T844 /workspace/coverage/default/34.edn_err.2140803271 Apr 30 02:43:45 PM PDT 24 Apr 30 02:43:47 PM PDT 24 47337806 ps
T237 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3259034694 Apr 30 02:25:55 PM PDT 24 Apr 30 02:26:00 PM PDT 24 1931211417 ps
T230 /workspace/coverage/cover_reg_top/17.edn_csr_rw.580594603 Apr 30 02:26:44 PM PDT 24 Apr 30 02:26:46 PM PDT 24 19954306 ps
T845 /workspace/coverage/cover_reg_top/35.edn_intr_test.1935684193 Apr 30 02:27:01 PM PDT 24 Apr 30 02:27:03 PM PDT 24 130335171 ps
T846 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.550210687 Apr 30 02:26:04 PM PDT 24 Apr 30 02:26:06 PM PDT 24 26208419 ps
T238 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3115517906 Apr 30 02:25:52 PM PDT 24 Apr 30 02:25:55 PM PDT 24 91781282 ps
T847 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1518750769 Apr 30 02:25:46 PM PDT 24 Apr 30 02:25:48 PM PDT 24 18975561 ps
T213 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.214187077 Apr 30 02:25:54 PM PDT 24 Apr 30 02:25:56 PM PDT 24 15284460 ps
T848 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2917978712 Apr 30 02:25:56 PM PDT 24 Apr 30 02:26:03 PM PDT 24 1522413397 ps
T849 /workspace/coverage/cover_reg_top/14.edn_intr_test.842335576 Apr 30 02:26:27 PM PDT 24 Apr 30 02:26:28 PM PDT 24 40471621 ps
T239 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3909357553 Apr 30 02:26:14 PM PDT 24 Apr 30 02:26:16 PM PDT 24 166314283 ps
T231 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3074162256 Apr 30 02:26:19 PM PDT 24 Apr 30 02:26:21 PM PDT 24 79667735 ps
T850 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.364082524 Apr 30 02:26:34 PM PDT 24 Apr 30 02:26:36 PM PDT 24 101604333 ps
T851 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1022520117 Apr 30 02:25:59 PM PDT 24 Apr 30 02:26:02 PM PDT 24 54801961 ps
T852 /workspace/coverage/cover_reg_top/48.edn_intr_test.2244455235 Apr 30 02:27:10 PM PDT 24 Apr 30 02:27:12 PM PDT 24 13527093 ps
T232 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1555287850 Apr 30 02:26:18 PM PDT 24 Apr 30 02:26:20 PM PDT 24 51272358 ps
T853 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.4184307995 Apr 30 02:26:46 PM PDT 24 Apr 30 02:26:48 PM PDT 24 50289303 ps
T854 /workspace/coverage/cover_reg_top/13.edn_intr_test.1628458039 Apr 30 02:26:30 PM PDT 24 Apr 30 02:26:32 PM PDT 24 127065656 ps
T855 /workspace/coverage/cover_reg_top/41.edn_intr_test.2298970603 Apr 30 02:27:03 PM PDT 24 Apr 30 02:27:04 PM PDT 24 19801464 ps
T856 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2963277827 Apr 30 02:25:52 PM PDT 24 Apr 30 02:25:56 PM PDT 24 120625160 ps
T250 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.874875818 Apr 30 02:25:37 PM PDT 24 Apr 30 02:25:39 PM PDT 24 72295022 ps
T857 /workspace/coverage/cover_reg_top/11.edn_intr_test.1021817295 Apr 30 02:26:18 PM PDT 24 Apr 30 02:26:19 PM PDT 24 14659857 ps
T233 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.664399308 Apr 30 02:25:59 PM PDT 24 Apr 30 02:26:02 PM PDT 24 69073553 ps
T247 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1328749205 Apr 30 02:26:23 PM PDT 24 Apr 30 02:26:26 PM PDT 24 117823740 ps
T214 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2602648874 Apr 30 02:26:34 PM PDT 24 Apr 30 02:26:36 PM PDT 24 107301704 ps
T858 /workspace/coverage/cover_reg_top/9.edn_intr_test.1881722491 Apr 30 02:26:18 PM PDT 24 Apr 30 02:26:19 PM PDT 24 13528302 ps
T859 /workspace/coverage/cover_reg_top/43.edn_intr_test.2089946654 Apr 30 02:27:05 PM PDT 24 Apr 30 02:27:07 PM PDT 24 16196273 ps
T860 /workspace/coverage/cover_reg_top/4.edn_intr_test.2412825944 Apr 30 02:25:58 PM PDT 24 Apr 30 02:25:59 PM PDT 24 38067989 ps
T248 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3014570429 Apr 30 02:26:38 PM PDT 24 Apr 30 02:26:42 PM PDT 24 95265013 ps
T234 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.4004581958 Apr 30 02:26:12 PM PDT 24 Apr 30 02:26:14 PM PDT 24 31069764 ps
T215 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2350187315 Apr 30 02:26:12 PM PDT 24 Apr 30 02:26:14 PM PDT 24 15969902 ps
T861 /workspace/coverage/cover_reg_top/39.edn_intr_test.3391429362 Apr 30 02:27:05 PM PDT 24 Apr 30 02:27:06 PM PDT 24 16191495 ps
T862 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3084306037 Apr 30 02:25:51 PM PDT 24 Apr 30 02:25:53 PM PDT 24 67132060 ps
T863 /workspace/coverage/cover_reg_top/30.edn_intr_test.3201823121 Apr 30 02:27:00 PM PDT 24 Apr 30 02:27:02 PM PDT 24 37364924 ps
T864 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2098432829 Apr 30 02:26:14 PM PDT 24 Apr 30 02:26:21 PM PDT 24 351907792 ps
T865 /workspace/coverage/cover_reg_top/26.edn_intr_test.3850958542 Apr 30 02:26:57 PM PDT 24 Apr 30 02:26:58 PM PDT 24 14903577 ps
T236 /workspace/coverage/cover_reg_top/0.edn_csr_rw.602101778 Apr 30 02:25:40 PM PDT 24 Apr 30 02:25:41 PM PDT 24 23803342 ps
T216 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3717052054 Apr 30 02:26:07 PM PDT 24 Apr 30 02:26:09 PM PDT 24 33420621 ps
T866 /workspace/coverage/cover_reg_top/5.edn_intr_test.291781403 Apr 30 02:25:58 PM PDT 24 Apr 30 02:26:00 PM PDT 24 40034695 ps
T867 /workspace/coverage/cover_reg_top/17.edn_intr_test.721571149 Apr 30 02:26:43 PM PDT 24 Apr 30 02:26:45 PM PDT 24 15266621 ps
T868 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.345829081 Apr 30 02:25:52 PM PDT 24 Apr 30 02:25:54 PM PDT 24 27891873 ps
T869 /workspace/coverage/cover_reg_top/18.edn_intr_test.779481817 Apr 30 02:26:44 PM PDT 24 Apr 30 02:26:45 PM PDT 24 13003767 ps
T870 /workspace/coverage/cover_reg_top/24.edn_intr_test.2174102453 Apr 30 02:26:54 PM PDT 24 Apr 30 02:26:56 PM PDT 24 14351184 ps
T249 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1354061199 Apr 30 02:26:12 PM PDT 24 Apr 30 02:26:14 PM PDT 24 175898317 ps
T217 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2413982277 Apr 30 02:25:37 PM PDT 24 Apr 30 02:25:39 PM PDT 24 25283972 ps
T218 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2663832146 Apr 30 02:25:51 PM PDT 24 Apr 30 02:25:53 PM PDT 24 62584914 ps
T871 /workspace/coverage/cover_reg_top/6.edn_csr_rw.259778515 Apr 30 02:26:05 PM PDT 24 Apr 30 02:26:07 PM PDT 24 50053810 ps
T872 /workspace/coverage/cover_reg_top/21.edn_intr_test.3201134532 Apr 30 02:26:53 PM PDT 24 Apr 30 02:26:55 PM PDT 24 13034908 ps
T873 /workspace/coverage/cover_reg_top/16.edn_intr_test.107405581 Apr 30 02:26:35 PM PDT 24 Apr 30 02:26:36 PM PDT 24 28531260 ps
T874 /workspace/coverage/cover_reg_top/2.edn_intr_test.527270955 Apr 30 02:25:55 PM PDT 24 Apr 30 02:25:57 PM PDT 24 11381347 ps
T875 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2787774249 Apr 30 02:25:45 PM PDT 24 Apr 30 02:25:49 PM PDT 24 537887873 ps
T219 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3338166716 Apr 30 02:26:27 PM PDT 24 Apr 30 02:26:29 PM PDT 24 25213207 ps
T876 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1159475947 Apr 30 02:26:20 PM PDT 24 Apr 30 02:26:22 PM PDT 24 31190793 ps
T877 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3680328 Apr 30 02:26:44 PM PDT 24 Apr 30 02:26:49 PM PDT 24 298084380 ps
T878 /workspace/coverage/cover_reg_top/36.edn_intr_test.2091634919 Apr 30 02:27:00 PM PDT 24 Apr 30 02:27:02 PM PDT 24 53774483 ps
T220 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.325814375 Apr 30 02:25:53 PM PDT 24 Apr 30 02:25:55 PM PDT 24 25598083 ps
T221 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3392154305 Apr 30 02:25:45 PM PDT 24 Apr 30 02:25:47 PM PDT 24 54981443 ps
T879 /workspace/coverage/cover_reg_top/15.edn_csr_rw.257275059 Apr 30 02:26:34 PM PDT 24 Apr 30 02:26:36 PM PDT 24 24379358 ps
T880 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3373541503 Apr 30 02:26:14 PM PDT 24 Apr 30 02:26:16 PM PDT 24 21414004 ps
T881 /workspace/coverage/cover_reg_top/42.edn_intr_test.1845719548 Apr 30 02:27:05 PM PDT 24 Apr 30 02:27:06 PM PDT 24 24578558 ps
T882 /workspace/coverage/cover_reg_top/7.edn_tl_errors.787312461 Apr 30 02:26:08 PM PDT 24 Apr 30 02:26:10 PM PDT 24 26082707 ps
T883 /workspace/coverage/cover_reg_top/12.edn_intr_test.4153166105 Apr 30 02:26:19 PM PDT 24 Apr 30 02:26:20 PM PDT 24 71213380 ps
T235 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3631686951 Apr 30 02:26:53 PM PDT 24 Apr 30 02:26:55 PM PDT 24 40965136 ps
T222 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2704575251 Apr 30 02:26:01 PM PDT 24 Apr 30 02:26:03 PM PDT 24 88841614 ps
T884 /workspace/coverage/cover_reg_top/0.edn_intr_test.1569598010 Apr 30 02:25:38 PM PDT 24 Apr 30 02:25:40 PM PDT 24 41708861 ps
T885 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2129547413 Apr 30 02:25:44 PM PDT 24 Apr 30 02:25:46 PM PDT 24 64791482 ps
T886 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2388392305 Apr 30 02:26:07 PM PDT 24 Apr 30 02:26:09 PM PDT 24 22086869 ps
T887 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1067574782 Apr 30 02:26:34 PM PDT 24 Apr 30 02:26:36 PM PDT 24 16085361 ps
T888 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.69644632 Apr 30 02:26:20 PM PDT 24 Apr 30 02:26:22 PM PDT 24 22973534 ps
T889 /workspace/coverage/cover_reg_top/0.edn_tl_errors.360739558 Apr 30 02:25:40 PM PDT 24 Apr 30 02:25:45 PM PDT 24 142535800 ps
T890 /workspace/coverage/cover_reg_top/33.edn_intr_test.317030518 Apr 30 02:27:02 PM PDT 24 Apr 30 02:27:03 PM PDT 24 93537926 ps
T891 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.918335484 Apr 30 02:25:58 PM PDT 24 Apr 30 02:26:00 PM PDT 24 73494104 ps
T892 /workspace/coverage/cover_reg_top/10.edn_intr_test.2093563309 Apr 30 02:26:12 PM PDT 24 Apr 30 02:26:14 PM PDT 24 35172943 ps
T893 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2716560165 Apr 30 02:26:31 PM PDT 24 Apr 30 02:26:33 PM PDT 24 17615885 ps
T894 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3411880197 Apr 30 02:25:50 PM PDT 24 Apr 30 02:25:52 PM PDT 24 110446297 ps
T223 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2305062476 Apr 30 02:25:45 PM PDT 24 Apr 30 02:25:47 PM PDT 24 19346890 ps
T895 /workspace/coverage/cover_reg_top/2.edn_tl_errors.337950452 Apr 30 02:25:56 PM PDT 24 Apr 30 02:26:00 PM PDT 24 73137994 ps
T896 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1269436864 Apr 30 02:26:45 PM PDT 24 Apr 30 02:26:48 PM PDT 24 137746134 ps
T897 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2593031640 Apr 30 02:26:55 PM PDT 24 Apr 30 02:26:57 PM PDT 24 23487326 ps
T224 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1636967280 Apr 30 02:26:05 PM PDT 24 Apr 30 02:26:07 PM PDT 24 34984044 ps
T898 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2114000775 Apr 30 02:26:29 PM PDT 24 Apr 30 02:26:31 PM PDT 24 19254717 ps
T899 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.360582590 Apr 30 02:26:29 PM PDT 24 Apr 30 02:26:31 PM PDT 24 109614805 ps
T900 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3675050780 Apr 30 02:25:45 PM PDT 24 Apr 30 02:25:46 PM PDT 24 28709379 ps
T901 /workspace/coverage/cover_reg_top/32.edn_intr_test.2605941897 Apr 30 02:27:01 PM PDT 24 Apr 30 02:27:03 PM PDT 24 12465379 ps
T902 /workspace/coverage/cover_reg_top/20.edn_intr_test.3481928754 Apr 30 02:26:54 PM PDT 24 Apr 30 02:26:55 PM PDT 24 10531391 ps
T903 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1116183788 Apr 30 02:26:34 PM PDT 24 Apr 30 02:26:37 PM PDT 24 41270697 ps
T904 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1831417422 Apr 30 02:26:08 PM PDT 24 Apr 30 02:26:10 PM PDT 24 101609948 ps
T905 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2380671626 Apr 30 02:25:51 PM PDT 24 Apr 30 02:25:54 PM PDT 24 36821487 ps
T251 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.869107062 Apr 30 02:26:34 PM PDT 24 Apr 30 02:26:38 PM PDT 24 148216989 ps
T225 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2471957887 Apr 30 02:25:52 PM PDT 24 Apr 30 02:25:54 PM PDT 24 35729171 ps
T906 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2609591582 Apr 30 02:26:45 PM PDT 24 Apr 30 02:26:47 PM PDT 24 23676533 ps
T907 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.429405048 Apr 30 02:26:07 PM PDT 24 Apr 30 02:26:10 PM PDT 24 52416375 ps
T908 /workspace/coverage/cover_reg_top/15.edn_intr_test.3648460732 Apr 30 02:26:34 PM PDT 24 Apr 30 02:26:36 PM PDT 24 15362022 ps
T909 /workspace/coverage/cover_reg_top/3.edn_intr_test.2633691338 Apr 30 02:25:55 PM PDT 24 Apr 30 02:25:57 PM PDT 24 16975061 ps
T910 /workspace/coverage/cover_reg_top/40.edn_intr_test.2300818576 Apr 30 02:27:05 PM PDT 24 Apr 30 02:27:06 PM PDT 24 15014398 ps
T911 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3802574952 Apr 30 02:26:35 PM PDT 24 Apr 30 02:26:39 PM PDT 24 84018877 ps
T912 /workspace/coverage/cover_reg_top/5.edn_csr_rw.315809654 Apr 30 02:26:00 PM PDT 24 Apr 30 02:26:02 PM PDT 24 45741658 ps
T913 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1050705395 Apr 30 02:26:44 PM PDT 24 Apr 30 02:26:46 PM PDT 24 69446614 ps
T914 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2942706783 Apr 30 02:26:12 PM PDT 24 Apr 30 02:26:16 PM PDT 24 270780277 ps
T915 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.649165102 Apr 30 02:26:20 PM PDT 24 Apr 30 02:26:22 PM PDT 24 18928680 ps
T916 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1145146879 Apr 30 02:26:19 PM PDT 24 Apr 30 02:26:21 PM PDT 24 13057206 ps
T228 /workspace/coverage/cover_reg_top/18.edn_csr_rw.403249578 Apr 30 02:26:45 PM PDT 24 Apr 30 02:26:47 PM PDT 24 16930557 ps
T917 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.481405012 Apr 30 02:26:28 PM PDT 24 Apr 30 02:26:30 PM PDT 24 62174598 ps
T918 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3627732510 Apr 30 02:26:44 PM PDT 24 Apr 30 02:26:46 PM PDT 24 74891932 ps
T919 /workspace/coverage/cover_reg_top/46.edn_intr_test.1285945884 Apr 30 02:27:10 PM PDT 24 Apr 30 02:27:12 PM PDT 24 44104920 ps
T920 /workspace/coverage/cover_reg_top/6.edn_intr_test.425446853 Apr 30 02:26:00 PM PDT 24 Apr 30 02:26:02 PM PDT 24 175253082 ps
T921 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1353058596 Apr 30 02:26:28 PM PDT 24 Apr 30 02:26:29 PM PDT 24 74472195 ps
T922 /workspace/coverage/cover_reg_top/29.edn_intr_test.4043968156 Apr 30 02:27:02 PM PDT 24 Apr 30 02:27:04 PM PDT 24 24645096 ps
T923 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.112020594 Apr 30 02:26:06 PM PDT 24 Apr 30 02:26:08 PM PDT 24 73429621 ps
T924 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2248676088 Apr 30 02:26:28 PM PDT 24 Apr 30 02:26:33 PM PDT 24 218957354 ps
T925 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3268005930 Apr 30 02:25:47 PM PDT 24 Apr 30 02:25:48 PM PDT 24 71707057 ps
T926 /workspace/coverage/cover_reg_top/27.edn_intr_test.2905981438 Apr 30 02:26:57 PM PDT 24 Apr 30 02:26:59 PM PDT 24 24409934 ps
T927 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1173300305 Apr 30 02:26:00 PM PDT 24 Apr 30 02:26:02 PM PDT 24 51857452 ps
T928 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2646224944 Apr 30 02:25:45 PM PDT 24 Apr 30 02:25:48 PM PDT 24 34672644 ps
T929 /workspace/coverage/cover_reg_top/7.edn_intr_test.420405475 Apr 30 02:26:05 PM PDT 24 Apr 30 02:26:07 PM PDT 24 27414717 ps
T930 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1312845791 Apr 30 02:25:52 PM PDT 24 Apr 30 02:25:54 PM PDT 24 27951337 ps
T931 /workspace/coverage/cover_reg_top/19.edn_intr_test.2258231431 Apr 30 02:26:54 PM PDT 24 Apr 30 02:26:56 PM PDT 24 14224811 ps
T932 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2596949854 Apr 30 02:25:54 PM PDT 24 Apr 30 02:25:58 PM PDT 24 359965765 ps
T933 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1423385910 Apr 30 02:26:07 PM PDT 24 Apr 30 02:26:09 PM PDT 24 20996228 ps
T934 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.147056724 Apr 30 02:25:37 PM PDT 24 Apr 30 02:25:39 PM PDT 24 75109859 ps
T935 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1741905921 Apr 30 02:26:35 PM PDT 24 Apr 30 02:26:37 PM PDT 24 12103098 ps
T936 /workspace/coverage/cover_reg_top/4.edn_tl_errors.235692492 Apr 30 02:25:52 PM PDT 24 Apr 30 02:25:55 PM PDT 24 82711655 ps
T226 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2104842740 Apr 30 02:26:11 PM PDT 24 Apr 30 02:26:13 PM PDT 24 113435436 ps
T937 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1180638610 Apr 30 02:25:52 PM PDT 24 Apr 30 02:25:54 PM PDT 24 20197827 ps
T938 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3120052060 Apr 30 02:26:28 PM PDT 24 Apr 30 02:26:30 PM PDT 24 16452395 ps
T939 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1164580711 Apr 30 02:26:38 PM PDT 24 Apr 30 02:26:42 PM PDT 24 71979024 ps
T940 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3664404237 Apr 30 02:26:55 PM PDT 24 Apr 30 02:26:57 PM PDT 24 101255623 ps
T941 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.7911607 Apr 30 02:25:52 PM PDT 24 Apr 30 02:25:54 PM PDT 24 27282836 ps
T227 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2220709524 Apr 30 02:25:52 PM PDT 24 Apr 30 02:25:54 PM PDT 24 17038299 ps
T942 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1706091787 Apr 30 02:25:47 PM PDT 24 Apr 30 02:25:50 PM PDT 24 220467602 ps
T943 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2887893563 Apr 30 02:26:17 PM PDT 24 Apr 30 02:26:19 PM PDT 24 255998264 ps
T944 /workspace/coverage/cover_reg_top/1.edn_intr_test.2264363551 Apr 30 02:25:44 PM PDT 24 Apr 30 02:25:46 PM PDT 24 14609562 ps
T945 /workspace/coverage/cover_reg_top/23.edn_intr_test.1842635196 Apr 30 02:26:57 PM PDT 24 Apr 30 02:26:59 PM PDT 24 28429661 ps
T946 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.201968081 Apr 30 02:25:45 PM PDT 24 Apr 30 02:25:47 PM PDT 24 45546530 ps
T947 /workspace/coverage/cover_reg_top/44.edn_intr_test.416196216 Apr 30 02:27:05 PM PDT 24 Apr 30 02:27:07 PM PDT 24 46519702 ps
T948 /workspace/coverage/cover_reg_top/47.edn_intr_test.3638291829 Apr 30 02:27:09 PM PDT 24 Apr 30 02:27:11 PM PDT 24 72354607 ps
T949 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3764791926 Apr 30 02:26:34 PM PDT 24 Apr 30 02:26:37 PM PDT 24 57562260 ps
T229 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2284850048 Apr 30 02:25:58 PM PDT 24 Apr 30 02:26:00 PM PDT 24 47620950 ps
T950 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2713401859 Apr 30 02:26:06 PM PDT 24 Apr 30 02:26:08 PM PDT 24 138766857 ps
T951 /workspace/coverage/cover_reg_top/49.edn_intr_test.1117907560 Apr 30 02:27:09 PM PDT 24 Apr 30 02:27:11 PM PDT 24 22059413 ps
T952 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.877570592 Apr 30 02:25:51 PM PDT 24 Apr 30 02:25:54 PM PDT 24 148753856 ps
T953 /workspace/coverage/cover_reg_top/8.edn_intr_test.1835108843 Apr 30 02:26:05 PM PDT 24 Apr 30 02:26:07 PM PDT 24 97529255 ps
T954 /workspace/coverage/cover_reg_top/19.edn_tl_errors.184492787 Apr 30 02:26:45 PM PDT 24 Apr 30 02:26:50 PM PDT 24 117410702 ps
T955 /workspace/coverage/cover_reg_top/34.edn_intr_test.1333303660 Apr 30 02:27:04 PM PDT 24 Apr 30 02:27:06 PM PDT 24 22687509 ps
T956 /workspace/coverage/cover_reg_top/37.edn_intr_test.612560906 Apr 30 02:27:03 PM PDT 24 Apr 30 02:27:04 PM PDT 24 36973800 ps
T957 /workspace/coverage/cover_reg_top/8.edn_tl_errors.4153689673 Apr 30 02:26:05 PM PDT 24 Apr 30 02:26:08 PM PDT 24 80823910 ps
T958 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2250741542 Apr 30 02:26:12 PM PDT 24 Apr 30 02:26:13 PM PDT 24 21947517 ps
T959 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2237090189 Apr 30 02:26:20 PM PDT 24 Apr 30 02:26:23 PM PDT 24 72822005 ps
T960 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3516552054 Apr 30 02:26:20 PM PDT 24 Apr 30 02:26:23 PM PDT 24 275483836 ps
T961 /workspace/coverage/cover_reg_top/45.edn_intr_test.997745671 Apr 30 02:27:11 PM PDT 24 Apr 30 02:27:12 PM PDT 24 13912764 ps
T962 /workspace/coverage/cover_reg_top/31.edn_intr_test.1012311001 Apr 30 02:26:59 PM PDT 24 Apr 30 02:27:01 PM PDT 24 13885966 ps
T963 /workspace/coverage/cover_reg_top/28.edn_intr_test.2270615162 Apr 30 02:26:56 PM PDT 24 Apr 30 02:26:58 PM PDT 24 31628073 ps
T964 /workspace/coverage/cover_reg_top/13.edn_tl_errors.4451299 Apr 30 02:26:24 PM PDT 24 Apr 30 02:26:26 PM PDT 24 207238008 ps
T965 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2877236815 Apr 30 02:25:58 PM PDT 24 Apr 30 02:26:01 PM PDT 24 118771038 ps
T966 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2839909555 Apr 30 02:25:59 PM PDT 24 Apr 30 02:26:02 PM PDT 24 450961020 ps
T967 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3771325912 Apr 30 02:25:59 PM PDT 24 Apr 30 02:26:01 PM PDT 24 15523573 ps
T968 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.640632335 Apr 30 02:26:00 PM PDT 24 Apr 30 02:26:05 PM PDT 24 571741169 ps
T969 /workspace/coverage/cover_reg_top/9.edn_tl_errors.4161594632 Apr 30 02:26:13 PM PDT 24 Apr 30 02:26:18 PM PDT 24 1741599469 ps
T970 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2908030131 Apr 30 02:26:30 PM PDT 24 Apr 30 02:26:32 PM PDT 24 46164823 ps
T971 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2979151481 Apr 30 02:26:42 PM PDT 24 Apr 30 02:26:45 PM PDT 24 85604658 ps
T972 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3930772991 Apr 30 02:25:58 PM PDT 24 Apr 30 02:26:00 PM PDT 24 551015591 ps
T973 /workspace/coverage/cover_reg_top/38.edn_intr_test.127672409 Apr 30 02:27:03 PM PDT 24 Apr 30 02:27:04 PM PDT 24 14779111 ps
T974 /workspace/coverage/cover_reg_top/6.edn_tl_errors.671504473 Apr 30 02:25:58 PM PDT 24 Apr 30 02:26:02 PM PDT 24 99583002 ps
T975 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2476413363 Apr 30 02:26:21 PM PDT 24 Apr 30 02:26:23 PM PDT 24 44233759 ps
T976 /workspace/coverage/cover_reg_top/25.edn_intr_test.3886799365 Apr 30 02:26:56 PM PDT 24 Apr 30 02:26:57 PM PDT 24 15982228 ps
T977 /workspace/coverage/cover_reg_top/22.edn_intr_test.3959866201 Apr 30 02:26:54 PM PDT 24 Apr 30 02:26:56 PM PDT 24 55652365 ps

Test location /workspace/coverage/default/110.edn_genbits.1814435282
Short name T2
Test name
Test status
Simulation time 43615429 ps
CPU time 1.73 seconds
Started Apr 30 02:44:35 PM PDT 24
Finished Apr 30 02:44:37 PM PDT 24
Peak memory 218212 kb
Host smart-159f79ec-5e5b-4f66-b0e5-078a8c0c692a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814435282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1814435282
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1975996212
Short name T40
Test name
Test status
Simulation time 121080824094 ps
CPU time 1645.23 seconds
Started Apr 30 02:42:55 PM PDT 24
Finished Apr 30 03:10:22 PM PDT 24
Peak memory 226492 kb
Host smart-08b9882e-718f-4701-a8c1-e37413f75f29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975996212 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1975996212
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.282567371
Short name T8
Test name
Test status
Simulation time 29225703 ps
CPU time 0.98 seconds
Started Apr 30 02:43:16 PM PDT 24
Finished Apr 30 02:43:18 PM PDT 24
Peak memory 217728 kb
Host smart-a5ebc30f-00f6-47c1-a92d-8d362925ca9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282567371 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.282567371
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3750073178
Short name T17
Test name
Test status
Simulation time 1840415842 ps
CPU time 7.92 seconds
Started Apr 30 02:43:08 PM PDT 24
Finished Apr 30 02:43:16 PM PDT 24
Peak memory 237380 kb
Host smart-c7a66ef0-e130-4535-8b44-73868d183b05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750073178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3750073178
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/94.edn_genbits.3489203279
Short name T46
Test name
Test status
Simulation time 48701820 ps
CPU time 1.78 seconds
Started Apr 30 02:44:27 PM PDT 24
Finished Apr 30 02:44:30 PM PDT 24
Peak memory 218272 kb
Host smart-fddf3ae5-5c62-4f5d-82ad-dcf131df2cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489203279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3489203279
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.730798411
Short name T14
Test name
Test status
Simulation time 31209969 ps
CPU time 0.96 seconds
Started Apr 30 02:44:14 PM PDT 24
Finished Apr 30 02:44:15 PM PDT 24
Peak memory 232044 kb
Host smart-fd1b965d-9fec-4652-95d8-da3643f4d320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730798411 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.730798411
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/15.edn_alert.787883021
Short name T31
Test name
Test status
Simulation time 79725487 ps
CPU time 1.24 seconds
Started Apr 30 02:43:33 PM PDT 24
Finished Apr 30 02:43:34 PM PDT 24
Peak memory 215548 kb
Host smart-2bbeb0c2-9b48-4233-a0e3-a60c69d4d1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787883021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.787883021
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/224.edn_genbits.60189946
Short name T20
Test name
Test status
Simulation time 77850371 ps
CPU time 1.2 seconds
Started Apr 30 02:44:47 PM PDT 24
Finished Apr 30 02:44:49 PM PDT 24
Peak memory 219488 kb
Host smart-5ca6bbbe-d034-454c-8359-c80f34025ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60189946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.60189946
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert.2074651893
Short name T157
Test name
Test status
Simulation time 175043237 ps
CPU time 1.21 seconds
Started Apr 30 02:42:57 PM PDT 24
Finished Apr 30 02:42:59 PM PDT 24
Peak memory 215556 kb
Host smart-2818d198-39d8-4e7f-99f1-9aa0db1eb1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074651893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2074651893
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.4276007296
Short name T42
Test name
Test status
Simulation time 19650032231 ps
CPU time 127.49 seconds
Started Apr 30 02:43:32 PM PDT 24
Finished Apr 30 02:45:40 PM PDT 24
Peak memory 216340 kb
Host smart-8fae246a-5eac-4329-a361-1ff9233ef896
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276007296 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.4276007296
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.edn_regwen.819373337
Short name T706
Test name
Test status
Simulation time 40161720 ps
CPU time 0.95 seconds
Started Apr 30 02:42:57 PM PDT 24
Finished Apr 30 02:42:59 PM PDT 24
Peak memory 206888 kb
Host smart-19fe8973-ea3a-4e41-a1a3-658a42923934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819373337 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.819373337
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/20.edn_disable.3938373922
Short name T1
Test name
Test status
Simulation time 31486505 ps
CPU time 0.85 seconds
Started Apr 30 02:43:33 PM PDT 24
Finished Apr 30 02:43:34 PM PDT 24
Peak memory 216144 kb
Host smart-f511049e-b66a-4841-ac65-2556b2ad0fed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938373922 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3938373922
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3717052054
Short name T216
Test name
Test status
Simulation time 33420621 ps
CPU time 0.87 seconds
Started Apr 30 02:26:07 PM PDT 24
Finished Apr 30 02:26:09 PM PDT 24
Peak memory 206088 kb
Host smart-ce4003a7-aeff-4730-be78-501990edc242
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717052054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3717052054
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1328749205
Short name T247
Test name
Test status
Simulation time 117823740 ps
CPU time 2.25 seconds
Started Apr 30 02:26:23 PM PDT 24
Finished Apr 30 02:26:26 PM PDT 24
Peak memory 206344 kb
Host smart-9a8e827f-ffcf-4fdb-8649-af890192994d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328749205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1328749205
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/default/36.edn_alert.905544676
Short name T733
Test name
Test status
Simulation time 124916479 ps
CPU time 1.26 seconds
Started Apr 30 02:43:50 PM PDT 24
Finished Apr 30 02:43:52 PM PDT 24
Peak memory 215536 kb
Host smart-fb9bf32b-7789-47bc-8945-30d658b0c6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905544676 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.905544676
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/33.edn_disable.219074668
Short name T138
Test name
Test status
Simulation time 60282608 ps
CPU time 0.85 seconds
Started Apr 30 02:43:55 PM PDT 24
Finished Apr 30 02:43:56 PM PDT 24
Peak memory 215980 kb
Host smart-a2dbbcee-50df-4fc6-b6e0-dfeb06adc277
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219074668 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.219074668
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2651555988
Short name T107
Test name
Test status
Simulation time 35254602 ps
CPU time 1.09 seconds
Started Apr 30 02:44:02 PM PDT 24
Finished Apr 30 02:44:04 PM PDT 24
Peak memory 216740 kb
Host smart-69329522-058e-4bef-9ff4-155c56fa21b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651555988 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2651555988
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_alert.649002297
Short name T146
Test name
Test status
Simulation time 27613741 ps
CPU time 1.25 seconds
Started Apr 30 02:42:58 PM PDT 24
Finished Apr 30 02:43:00 PM PDT 24
Peak memory 215548 kb
Host smart-f7de9ac9-a1b4-4e85-bf7e-24a48718eb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649002297 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.649002297
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1310873982
Short name T127
Test name
Test status
Simulation time 47471551 ps
CPU time 1.15 seconds
Started Apr 30 02:42:55 PM PDT 24
Finished Apr 30 02:42:57 PM PDT 24
Peak memory 216728 kb
Host smart-ae0aa5bc-c7bf-4368-832a-eacaa153b4f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310873982 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1310873982
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_disable.3659850658
Short name T154
Test name
Test status
Simulation time 15184444 ps
CPU time 0.92 seconds
Started Apr 30 02:43:30 PM PDT 24
Finished Apr 30 02:43:31 PM PDT 24
Peak memory 215636 kb
Host smart-88fb0961-dcc6-4f90-abe8-7071581f630e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659850658 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3659850658
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable.3974989782
Short name T25
Test name
Test status
Simulation time 10756173 ps
CPU time 0.88 seconds
Started Apr 30 02:43:40 PM PDT 24
Finished Apr 30 02:43:42 PM PDT 24
Peak memory 216056 kb
Host smart-378485cb-1e76-4cd6-abdc-c49304673bdd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974989782 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3974989782
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3063306217
Short name T120
Test name
Test status
Simulation time 107114125 ps
CPU time 1.1 seconds
Started Apr 30 02:43:41 PM PDT 24
Finished Apr 30 02:43:43 PM PDT 24
Peak memory 215376 kb
Host smart-7e484e99-4c7f-44f3-97ee-0a70acc83798
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063306217 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3063306217
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/134.edn_genbits.2128884758
Short name T290
Test name
Test status
Simulation time 37011101 ps
CPU time 1.17 seconds
Started Apr 30 02:44:47 PM PDT 24
Finished Apr 30 02:44:49 PM PDT 24
Peak memory 219460 kb
Host smart-39e2653b-bc92-4b6d-aec4-11e693a6269b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128884758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2128884758
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2168594697
Short name T3
Test name
Test status
Simulation time 25157884 ps
CPU time 0.87 seconds
Started Apr 30 02:43:40 PM PDT 24
Finished Apr 30 02:43:42 PM PDT 24
Peak memory 215644 kb
Host smart-daff0ffe-0b9f-4716-906f-28ff8e9dd954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168594697 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2168594697
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/26.edn_alert.1559092569
Short name T158
Test name
Test status
Simulation time 85116311 ps
CPU time 1.18 seconds
Started Apr 30 02:43:45 PM PDT 24
Finished Apr 30 02:43:46 PM PDT 24
Peak memory 215496 kb
Host smart-28f98f61-0333-404d-a589-5ffa610e648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559092569 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1559092569
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/4.edn_disable.4184171269
Short name T26
Test name
Test status
Simulation time 13280647 ps
CPU time 0.87 seconds
Started Apr 30 02:43:01 PM PDT 24
Finished Apr 30 02:43:03 PM PDT 24
Peak memory 216036 kb
Host smart-1f72304a-6b25-414c-af51-575a40f18079
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184171269 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.4184171269
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2840753863
Short name T97
Test name
Test status
Simulation time 128082506 ps
CPU time 1.39 seconds
Started Apr 30 02:42:59 PM PDT 24
Finished Apr 30 02:43:01 PM PDT 24
Peak memory 217072 kb
Host smart-13ebb2a3-427b-4b7f-8f4b-5f39bfc5e240
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840753863 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2840753863
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/288.edn_genbits.3099732228
Short name T272
Test name
Test status
Simulation time 292271701 ps
CPU time 1.68 seconds
Started Apr 30 02:45:02 PM PDT 24
Finished Apr 30 02:45:04 PM PDT 24
Peak memory 218680 kb
Host smart-38931aec-0326-4914-9a81-c37c7fd03e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099732228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3099732228
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_disable.1773897154
Short name T192
Test name
Test status
Simulation time 16825321 ps
CPU time 0.86 seconds
Started Apr 30 02:43:19 PM PDT 24
Finished Apr 30 02:43:20 PM PDT 24
Peak memory 215288 kb
Host smart-87fae9cf-0b13-458a-93fb-6fda0887426c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773897154 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1773897154
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable.2964485791
Short name T156
Test name
Test status
Simulation time 20199226 ps
CPU time 0.91 seconds
Started Apr 30 02:44:03 PM PDT 24
Finished Apr 30 02:44:04 PM PDT 24
Peak memory 215988 kb
Host smart-8759fc6b-8cb6-41bd-95d7-b539c72122c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964485791 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2964485791
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/11.edn_intr.176244544
Short name T839
Test name
Test status
Simulation time 27872948 ps
CPU time 0.95 seconds
Started Apr 30 02:43:20 PM PDT 24
Finished Apr 30 02:43:22 PM PDT 24
Peak memory 215772 kb
Host smart-89b1e79e-a023-4fff-842d-73405ce333b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176244544 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.176244544
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_disable.733606964
Short name T149
Test name
Test status
Simulation time 55439174 ps
CPU time 0.85 seconds
Started Apr 30 02:43:18 PM PDT 24
Finished Apr 30 02:43:20 PM PDT 24
Peak memory 216144 kb
Host smart-d24a281b-3282-4ca5-9b5a-a5f3d80602d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733606964 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.733606964
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1261587444
Short name T112
Test name
Test status
Simulation time 24567082 ps
CPU time 1.08 seconds
Started Apr 30 02:43:41 PM PDT 24
Finished Apr 30 02:43:43 PM PDT 24
Peak memory 216776 kb
Host smart-0979df72-6382-4f8c-bbe0-a0b8668eafe0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261587444 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1261587444
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_disable.1166498677
Short name T172
Test name
Test status
Simulation time 78470579 ps
CPU time 0.8 seconds
Started Apr 30 02:44:05 PM PDT 24
Finished Apr 30 02:44:07 PM PDT 24
Peak memory 216184 kb
Host smart-88bc93c4-90db-4f3f-bf41-ad32bca7c71a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166498677 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1166498677
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable.2111680493
Short name T182
Test name
Test status
Simulation time 16064901 ps
CPU time 0.87 seconds
Started Apr 30 02:43:12 PM PDT 24
Finished Apr 30 02:43:14 PM PDT 24
Peak memory 216052 kb
Host smart-c7de2e31-3764-4a84-a7fe-0d362e075f9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111680493 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2111680493
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/35.edn_alert.1945955152
Short name T195
Test name
Test status
Simulation time 98461247 ps
CPU time 1.27 seconds
Started Apr 30 02:43:58 PM PDT 24
Finished Apr 30 02:44:01 PM PDT 24
Peak memory 215440 kb
Host smart-e74a2fd9-d97e-4a62-9b54-8a69aa55bf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945955152 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1945955152
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/64.edn_genbits.2189810439
Short name T10
Test name
Test status
Simulation time 66570764 ps
CPU time 1.31 seconds
Started Apr 30 02:44:17 PM PDT 24
Finished Apr 30 02:44:18 PM PDT 24
Peak memory 219396 kb
Host smart-591a19f1-bed8-4fe1-be01-4fd9d9911d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189810439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2189810439
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.3665178761
Short name T313
Test name
Test status
Simulation time 22480639 ps
CPU time 1.07 seconds
Started Apr 30 02:43:17 PM PDT 24
Finished Apr 30 02:43:19 PM PDT 24
Peak memory 206572 kb
Host smart-f51a362b-17a3-473b-a62b-0e095355bf0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665178761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3665178761
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_regwen.229328617
Short name T258
Test name
Test status
Simulation time 26677188 ps
CPU time 0.95 seconds
Started Apr 30 02:43:04 PM PDT 24
Finished Apr 30 02:43:06 PM PDT 24
Peak memory 207000 kb
Host smart-bb4f83f5-2f55-47b7-8802-ea45ae2289d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229328617 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.229328617
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/217.edn_genbits.1953344
Short name T53
Test name
Test status
Simulation time 93361590 ps
CPU time 1.23 seconds
Started Apr 30 02:44:56 PM PDT 24
Finished Apr 30 02:44:58 PM PDT 24
Peak memory 216868 kb
Host smart-e2a726e8-3ede-4e15-91fd-feba2c79ca04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1953344
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_err.1750746755
Short name T122
Test name
Test status
Simulation time 27307274 ps
CPU time 1.27 seconds
Started Apr 30 02:44:12 PM PDT 24
Finished Apr 30 02:44:14 PM PDT 24
Peak memory 220468 kb
Host smart-0bce4289-e1cd-466b-a1d1-a28d8c86fd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750746755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1750746755
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/111.edn_genbits.2181362024
Short name T275
Test name
Test status
Simulation time 52256556 ps
CPU time 1.16 seconds
Started Apr 30 02:44:34 PM PDT 24
Finished Apr 30 02:44:35 PM PDT 24
Peak memory 218384 kb
Host smart-4e1cf40e-c970-4564-ae79-af211bc86339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181362024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2181362024
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_regwen.1290385849
Short name T262
Test name
Test status
Simulation time 56615647 ps
CPU time 0.97 seconds
Started Apr 30 02:43:08 PM PDT 24
Finished Apr 30 02:43:09 PM PDT 24
Peak memory 206756 kb
Host smart-023c614b-14d3-49ea-98ff-4dca0b0905ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290385849 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1290385849
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/84.edn_genbits.3240394345
Short name T336
Test name
Test status
Simulation time 35187727 ps
CPU time 1.27 seconds
Started Apr 30 02:44:23 PM PDT 24
Finished Apr 30 02:44:25 PM PDT 24
Peak memory 216772 kb
Host smart-40f08e50-151a-4cbc-a16f-4b663ed4b73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240394345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3240394345
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.728571924
Short name T94
Test name
Test status
Simulation time 23318504 ps
CPU time 1.04 seconds
Started Apr 30 02:42:55 PM PDT 24
Finished Apr 30 02:42:57 PM PDT 24
Peak memory 215644 kb
Host smart-cc57f9f3-be32-4862-bcdb-2541d2a80c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728571924 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.728571924
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2704575251
Short name T222
Test name
Test status
Simulation time 88841614 ps
CPU time 1.2 seconds
Started Apr 30 02:26:01 PM PDT 24
Finished Apr 30 02:26:03 PM PDT 24
Peak memory 206320 kb
Host smart-d302feff-2096-4dff-8331-705c9a58b082
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704575251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2704575251
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/default/13.edn_err.980322679
Short name T174
Test name
Test status
Simulation time 22586333 ps
CPU time 1.14 seconds
Started Apr 30 02:43:20 PM PDT 24
Finished Apr 30 02:43:22 PM PDT 24
Peak memory 218180 kb
Host smart-cc67c288-28d6-476d-9666-4b4ef43d93ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980322679 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.980322679
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3909357553
Short name T239
Test name
Test status
Simulation time 166314283 ps
CPU time 1.52 seconds
Started Apr 30 02:26:14 PM PDT 24
Finished Apr 30 02:26:16 PM PDT 24
Peak memory 206592 kb
Host smart-17f70c77-463b-4bd2-a30d-3d5a1a2f388e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909357553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3909357553
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_regwen.3636994966
Short name T28
Test name
Test status
Simulation time 145017258 ps
CPU time 0.94 seconds
Started Apr 30 02:42:55 PM PDT 24
Finished Apr 30 02:42:57 PM PDT 24
Peak memory 206956 kb
Host smart-347198ec-fcd9-48b1-bc71-b348ae34a9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636994966 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3636994966
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/107.edn_genbits.3602058798
Short name T595
Test name
Test status
Simulation time 357870683 ps
CPU time 4.44 seconds
Started Apr 30 02:44:29 PM PDT 24
Finished Apr 30 02:44:34 PM PDT 24
Peak memory 218268 kb
Host smart-a8568d77-4a2d-4ea0-b7df-a16c2fbae477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602058798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3602058798
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_stress_all.4062124134
Short name T444
Test name
Test status
Simulation time 215905817 ps
CPU time 3.03 seconds
Started Apr 30 02:43:11 PM PDT 24
Finished Apr 30 02:43:16 PM PDT 24
Peak memory 216976 kb
Host smart-aaa2f88c-07b7-495b-8e45-955833f8cf74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062124134 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.4062124134
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/122.edn_genbits.1323880605
Short name T301
Test name
Test status
Simulation time 27373509 ps
CPU time 1.16 seconds
Started Apr 30 02:44:40 PM PDT 24
Finished Apr 30 02:44:41 PM PDT 24
Peak memory 219496 kb
Host smart-f5fafe4e-c7a2-4145-8ca0-17d75b57c33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323880605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1323880605
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.2290624991
Short name T298
Test name
Test status
Simulation time 197942023 ps
CPU time 1.2 seconds
Started Apr 30 02:44:32 PM PDT 24
Finished Apr 30 02:44:34 PM PDT 24
Peak memory 216812 kb
Host smart-f67f11ce-0a5c-4a64-bd32-6e04e8f58fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290624991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2290624991
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.902012053
Short name T288
Test name
Test status
Simulation time 65958305 ps
CPU time 1.69 seconds
Started Apr 30 02:44:43 PM PDT 24
Finished Apr 30 02:44:46 PM PDT 24
Peak memory 218356 kb
Host smart-a8b18467-963f-4d38-b7b8-214e9c181920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902012053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.902012053
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.3262687413
Short name T294
Test name
Test status
Simulation time 95286010 ps
CPU time 1.31 seconds
Started Apr 30 02:44:43 PM PDT 24
Finished Apr 30 02:44:45 PM PDT 24
Peak memory 218548 kb
Host smart-ba925146-07bb-4829-ae8c-a31ef283b9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262687413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3262687413
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_genbits.2994221969
Short name T280
Test name
Test status
Simulation time 42726400 ps
CPU time 1.31 seconds
Started Apr 30 02:43:33 PM PDT 24
Finished Apr 30 02:43:35 PM PDT 24
Peak memory 217124 kb
Host smart-a8a3966f-5dee-4333-9a3d-e19e864b6a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994221969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2994221969
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_stress_all.3586608985
Short name T438
Test name
Test status
Simulation time 500596585 ps
CPU time 5.33 seconds
Started Apr 30 02:43:28 PM PDT 24
Finished Apr 30 02:43:34 PM PDT 24
Peak memory 218292 kb
Host smart-b5dbec1f-ecf4-4114-9b88-01bc56617536
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586608985 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3586608985
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/178.edn_genbits.2370596898
Short name T283
Test name
Test status
Simulation time 59406471 ps
CPU time 1.47 seconds
Started Apr 30 02:44:43 PM PDT 24
Finished Apr 30 02:44:46 PM PDT 24
Peak memory 218252 kb
Host smart-04024179-a514-4a0e-a432-990ab8f9b90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370596898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2370596898
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.634265744
Short name T48
Test name
Test status
Simulation time 86824416 ps
CPU time 1.15 seconds
Started Apr 30 02:44:46 PM PDT 24
Finished Apr 30 02:44:48 PM PDT 24
Peak memory 218028 kb
Host smart-17a11f9a-746c-46a5-84e3-6519217ad4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634265744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.634265744
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2650643332
Short name T300
Test name
Test status
Simulation time 92296506 ps
CPU time 1.52 seconds
Started Apr 30 02:44:52 PM PDT 24
Finished Apr 30 02:44:54 PM PDT 24
Peak memory 218288 kb
Host smart-7da682d8-7683-4a24-bd36-3e7ce5167fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650643332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2650643332
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_alert.2342212059
Short name T264
Test name
Test status
Simulation time 29197465 ps
CPU time 1.32 seconds
Started Apr 30 02:44:12 PM PDT 24
Finished Apr 30 02:44:14 PM PDT 24
Peak memory 215548 kb
Host smart-a8a8dde3-27c2-4484-a4d2-810a25090dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342212059 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2342212059
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/16.edn_intr.1532965553
Short name T35
Test name
Test status
Simulation time 23083829 ps
CPU time 0.91 seconds
Started Apr 30 02:43:25 PM PDT 24
Finished Apr 30 02:43:26 PM PDT 24
Peak memory 215580 kb
Host smart-057275c3-057c-4821-8dce-c9993357e665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532965553 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1532965553
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/265.edn_genbits.3337298670
Short name T304
Test name
Test status
Simulation time 69493862 ps
CPU time 1.48 seconds
Started Apr 30 02:44:54 PM PDT 24
Finished Apr 30 02:44:56 PM PDT 24
Peak memory 219736 kb
Host smart-03b72801-4244-4206-a888-2c69c21d75c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337298670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3337298670
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.2344140931
Short name T795
Test name
Test status
Simulation time 74720369 ps
CPU time 1.55 seconds
Started Apr 30 02:44:52 PM PDT 24
Finished Apr 30 02:44:54 PM PDT 24
Peak memory 219884 kb
Host smart-cf0a831a-b980-4166-bef6-caf90830050b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344140931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2344140931
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3268005930
Short name T925
Test name
Test status
Simulation time 71707057 ps
CPU time 1.22 seconds
Started Apr 30 02:25:47 PM PDT 24
Finished Apr 30 02:25:48 PM PDT 24
Peak memory 206324 kb
Host smart-7e1fd640-666c-4df4-9a8e-dabf9e1590d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268005930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3268005930
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.147056724
Short name T934
Test name
Test status
Simulation time 75109859 ps
CPU time 2.02 seconds
Started Apr 30 02:25:37 PM PDT 24
Finished Apr 30 02:25:39 PM PDT 24
Peak memory 206268 kb
Host smart-11394d9b-0d65-498b-8b70-b5ce90349593
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147056724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.147056724
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2413982277
Short name T217
Test name
Test status
Simulation time 25283972 ps
CPU time 0.87 seconds
Started Apr 30 02:25:37 PM PDT 24
Finished Apr 30 02:25:39 PM PDT 24
Peak memory 206348 kb
Host smart-27a89b08-81c6-408e-bef3-5988d58e49ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413982277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2413982277
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1518750769
Short name T847
Test name
Test status
Simulation time 18975561 ps
CPU time 1.14 seconds
Started Apr 30 02:25:46 PM PDT 24
Finished Apr 30 02:25:48 PM PDT 24
Peak memory 214624 kb
Host smart-aff9b594-333a-4c45-9761-dc88373a0626
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518750769 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1518750769
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.602101778
Short name T236
Test name
Test status
Simulation time 23803342 ps
CPU time 0.92 seconds
Started Apr 30 02:25:40 PM PDT 24
Finished Apr 30 02:25:41 PM PDT 24
Peak memory 206356 kb
Host smart-b94bff42-fc45-4408-88e5-3f513c81f0bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602101778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.602101778
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1569598010
Short name T884
Test name
Test status
Simulation time 41708861 ps
CPU time 0.85 seconds
Started Apr 30 02:25:38 PM PDT 24
Finished Apr 30 02:25:40 PM PDT 24
Peak memory 206172 kb
Host smart-59172cac-cfb9-42b3-bebe-50b02c262529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569598010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1569598010
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.201968081
Short name T946
Test name
Test status
Simulation time 45546530 ps
CPU time 1.03 seconds
Started Apr 30 02:25:45 PM PDT 24
Finished Apr 30 02:25:47 PM PDT 24
Peak memory 206424 kb
Host smart-d1938230-78a7-4e27-8121-3887f9873b19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201968081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.201968081
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.360739558
Short name T889
Test name
Test status
Simulation time 142535800 ps
CPU time 4.98 seconds
Started Apr 30 02:25:40 PM PDT 24
Finished Apr 30 02:25:45 PM PDT 24
Peak memory 222736 kb
Host smart-bb80bfc8-2887-4d2b-a4dc-9e4ae71e3d50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360739558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.360739558
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.874875818
Short name T250
Test name
Test status
Simulation time 72295022 ps
CPU time 2.03 seconds
Started Apr 30 02:25:37 PM PDT 24
Finished Apr 30 02:25:39 PM PDT 24
Peak memory 206224 kb
Host smart-3cbaa33b-f78d-4d3b-876e-464f9d60132b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874875818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.874875818
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2646224944
Short name T928
Test name
Test status
Simulation time 34672644 ps
CPU time 1.47 seconds
Started Apr 30 02:25:45 PM PDT 24
Finished Apr 30 02:25:48 PM PDT 24
Peak memory 206312 kb
Host smart-9c75a76d-a31c-4450-b95f-d2ee32fc5b58
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646224944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2646224944
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2787774249
Short name T875
Test name
Test status
Simulation time 537887873 ps
CPU time 3.68 seconds
Started Apr 30 02:25:45 PM PDT 24
Finished Apr 30 02:25:49 PM PDT 24
Peak memory 206300 kb
Host smart-761a0206-387f-4d0e-8a5e-05ac76fdbbec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787774249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2787774249
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3675050780
Short name T900
Test name
Test status
Simulation time 28709379 ps
CPU time 1.15 seconds
Started Apr 30 02:25:45 PM PDT 24
Finished Apr 30 02:25:46 PM PDT 24
Peak memory 206332 kb
Host smart-0eabef6c-8547-47ec-b660-de8930afbd51
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675050780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3675050780
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3411880197
Short name T894
Test name
Test status
Simulation time 110446297 ps
CPU time 1.31 seconds
Started Apr 30 02:25:50 PM PDT 24
Finished Apr 30 02:25:52 PM PDT 24
Peak memory 214660 kb
Host smart-13936218-7e6e-40c9-a1c9-6c1f6bcc8654
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411880197 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3411880197
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2305062476
Short name T223
Test name
Test status
Simulation time 19346890 ps
CPU time 0.83 seconds
Started Apr 30 02:25:45 PM PDT 24
Finished Apr 30 02:25:47 PM PDT 24
Peak memory 206140 kb
Host smart-2d0e07e3-7548-44a5-811c-11803c3c22d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305062476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2305062476
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2264363551
Short name T944
Test name
Test status
Simulation time 14609562 ps
CPU time 0.94 seconds
Started Apr 30 02:25:44 PM PDT 24
Finished Apr 30 02:25:46 PM PDT 24
Peak memory 206188 kb
Host smart-7de2ebc4-4666-407e-a0c8-5de5d856591a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264363551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2264363551
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3392154305
Short name T221
Test name
Test status
Simulation time 54981443 ps
CPU time 1.05 seconds
Started Apr 30 02:25:45 PM PDT 24
Finished Apr 30 02:25:47 PM PDT 24
Peak memory 206328 kb
Host smart-a877ff51-8cec-42b9-8185-8f235d4f918b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392154305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3392154305
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1706091787
Short name T942
Test name
Test status
Simulation time 220467602 ps
CPU time 2.62 seconds
Started Apr 30 02:25:47 PM PDT 24
Finished Apr 30 02:25:50 PM PDT 24
Peak memory 214536 kb
Host smart-fe7f4963-b082-4079-bbe9-2cb6fe0b383c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706091787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1706091787
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2129547413
Short name T885
Test name
Test status
Simulation time 64791482 ps
CPU time 1.66 seconds
Started Apr 30 02:25:44 PM PDT 24
Finished Apr 30 02:25:46 PM PDT 24
Peak memory 206312 kb
Host smart-42044b13-e497-466c-976c-d09b909d7943
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129547413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2129547413
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3373541503
Short name T880
Test name
Test status
Simulation time 21414004 ps
CPU time 1.1 seconds
Started Apr 30 02:26:14 PM PDT 24
Finished Apr 30 02:26:16 PM PDT 24
Peak memory 216184 kb
Host smart-659bc1f4-ce11-4c44-a94b-7746f9d614e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373541503 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3373541503
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2350187315
Short name T215
Test name
Test status
Simulation time 15969902 ps
CPU time 0.99 seconds
Started Apr 30 02:26:12 PM PDT 24
Finished Apr 30 02:26:14 PM PDT 24
Peak memory 206288 kb
Host smart-e49a5368-b6e5-46b0-9533-947063b8a45c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350187315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2350187315
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2093563309
Short name T892
Test name
Test status
Simulation time 35172943 ps
CPU time 0.83 seconds
Started Apr 30 02:26:12 PM PDT 24
Finished Apr 30 02:26:14 PM PDT 24
Peak memory 206180 kb
Host smart-725081c4-2bda-405c-80b6-70792d251cea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093563309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2093563309
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1555287850
Short name T232
Test name
Test status
Simulation time 51272358 ps
CPU time 1.51 seconds
Started Apr 30 02:26:18 PM PDT 24
Finished Apr 30 02:26:20 PM PDT 24
Peak memory 206376 kb
Host smart-a5ba5770-4f87-4e20-be91-3df93072e51d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555287850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1555287850
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2887893563
Short name T943
Test name
Test status
Simulation time 255998264 ps
CPU time 1.89 seconds
Started Apr 30 02:26:17 PM PDT 24
Finished Apr 30 02:26:19 PM PDT 24
Peak memory 214488 kb
Host smart-23d2c574-b115-422b-a0b3-dd731031e916
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887893563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2887893563
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2098432829
Short name T864
Test name
Test status
Simulation time 351907792 ps
CPU time 6.31 seconds
Started Apr 30 02:26:14 PM PDT 24
Finished Apr 30 02:26:21 PM PDT 24
Peak memory 206352 kb
Host smart-9c8eceed-d212-4a48-a13e-fda4424c1a0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098432829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2098432829
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.649165102
Short name T915
Test name
Test status
Simulation time 18928680 ps
CPU time 1.06 seconds
Started Apr 30 02:26:20 PM PDT 24
Finished Apr 30 02:26:22 PM PDT 24
Peak memory 206420 kb
Host smart-704b1c25-66c9-4404-9bbf-281d8c988058
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649165102 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.649165102
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3074162256
Short name T231
Test name
Test status
Simulation time 79667735 ps
CPU time 0.81 seconds
Started Apr 30 02:26:19 PM PDT 24
Finished Apr 30 02:26:21 PM PDT 24
Peak memory 206088 kb
Host smart-4811402d-7340-48f3-8274-70f1379e088c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074162256 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3074162256
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1021817295
Short name T857
Test name
Test status
Simulation time 14659857 ps
CPU time 0.94 seconds
Started Apr 30 02:26:18 PM PDT 24
Finished Apr 30 02:26:19 PM PDT 24
Peak memory 206152 kb
Host smart-19c15fee-173f-4b28-858a-caf10628c160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021817295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1021817295
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.69644632
Short name T888
Test name
Test status
Simulation time 22973534 ps
CPU time 1.15 seconds
Started Apr 30 02:26:20 PM PDT 24
Finished Apr 30 02:26:22 PM PDT 24
Peak memory 206360 kb
Host smart-4015fbed-eb6e-4023-b203-4eab505ad765
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69644632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_out
standing.69644632
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2942706783
Short name T914
Test name
Test status
Simulation time 270780277 ps
CPU time 3.23 seconds
Started Apr 30 02:26:12 PM PDT 24
Finished Apr 30 02:26:16 PM PDT 24
Peak memory 214468 kb
Host smart-f41c286b-2378-4067-a538-a8126f7d1bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942706783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2942706783
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1159475947
Short name T876
Test name
Test status
Simulation time 31190793 ps
CPU time 2.03 seconds
Started Apr 30 02:26:20 PM PDT 24
Finished Apr 30 02:26:22 PM PDT 24
Peak memory 214640 kb
Host smart-4b3f121a-3a64-4386-87f5-c3e8e93a0df3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159475947 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1159475947
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1145146879
Short name T916
Test name
Test status
Simulation time 13057206 ps
CPU time 0.91 seconds
Started Apr 30 02:26:19 PM PDT 24
Finished Apr 30 02:26:21 PM PDT 24
Peak memory 206260 kb
Host smart-5a098020-3c5b-4905-8513-4e85509970ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145146879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1145146879
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.4153166105
Short name T883
Test name
Test status
Simulation time 71213380 ps
CPU time 0.83 seconds
Started Apr 30 02:26:19 PM PDT 24
Finished Apr 30 02:26:20 PM PDT 24
Peak memory 206224 kb
Host smart-c2372a61-7be0-4b36-bd3a-6bc62d44d646
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153166105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.4153166105
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2476413363
Short name T975
Test name
Test status
Simulation time 44233759 ps
CPU time 1.14 seconds
Started Apr 30 02:26:21 PM PDT 24
Finished Apr 30 02:26:23 PM PDT 24
Peak memory 206412 kb
Host smart-1e0f9440-c79d-4886-b37c-c427ca8092e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476413363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2476413363
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3516552054
Short name T960
Test name
Test status
Simulation time 275483836 ps
CPU time 2.37 seconds
Started Apr 30 02:26:20 PM PDT 24
Finished Apr 30 02:26:23 PM PDT 24
Peak memory 218456 kb
Host smart-969f3dca-e2fe-4928-8fb6-d939cc39121c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516552054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3516552054
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3120052060
Short name T938
Test name
Test status
Simulation time 16452395 ps
CPU time 1.03 seconds
Started Apr 30 02:26:28 PM PDT 24
Finished Apr 30 02:26:30 PM PDT 24
Peak memory 206340 kb
Host smart-58e2560a-5818-4256-b656-f0063c33a685
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120052060 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3120052060
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3338166716
Short name T219
Test name
Test status
Simulation time 25213207 ps
CPU time 0.93 seconds
Started Apr 30 02:26:27 PM PDT 24
Finished Apr 30 02:26:29 PM PDT 24
Peak memory 206304 kb
Host smart-8ce8c108-75ad-405a-bc4c-89797292b782
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338166716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3338166716
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1628458039
Short name T854
Test name
Test status
Simulation time 127065656 ps
CPU time 0.74 seconds
Started Apr 30 02:26:30 PM PDT 24
Finished Apr 30 02:26:32 PM PDT 24
Peak memory 205976 kb
Host smart-366ada3d-57c5-4bd9-8099-cf62fa96daba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628458039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1628458039
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2114000775
Short name T898
Test name
Test status
Simulation time 19254717 ps
CPU time 1.04 seconds
Started Apr 30 02:26:29 PM PDT 24
Finished Apr 30 02:26:31 PM PDT 24
Peak memory 206264 kb
Host smart-c31d38b7-436d-442c-a565-23dbab8fa944
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114000775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2114000775
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.4451299
Short name T964
Test name
Test status
Simulation time 207238008 ps
CPU time 1.54 seconds
Started Apr 30 02:26:24 PM PDT 24
Finished Apr 30 02:26:26 PM PDT 24
Peak memory 214496 kb
Host smart-f65fd6e3-5c24-40e1-9456-8d08b5a7b05b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4451299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.4451299
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2237090189
Short name T959
Test name
Test status
Simulation time 72822005 ps
CPU time 1.65 seconds
Started Apr 30 02:26:20 PM PDT 24
Finished Apr 30 02:26:23 PM PDT 24
Peak memory 206368 kb
Host smart-b1be0f1e-37eb-4f23-b96e-f074d0907528
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237090189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2237090189
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2908030131
Short name T970
Test name
Test status
Simulation time 46164823 ps
CPU time 1.22 seconds
Started Apr 30 02:26:30 PM PDT 24
Finished Apr 30 02:26:32 PM PDT 24
Peak memory 217328 kb
Host smart-14179a8a-b82f-49b6-91a7-4b6125feec3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908030131 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2908030131
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1353058596
Short name T921
Test name
Test status
Simulation time 74472195 ps
CPU time 0.86 seconds
Started Apr 30 02:26:28 PM PDT 24
Finished Apr 30 02:26:29 PM PDT 24
Peak memory 206120 kb
Host smart-f603d3e1-3429-4ee7-8f7c-54552931ba66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353058596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1353058596
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.842335576
Short name T849
Test name
Test status
Simulation time 40471621 ps
CPU time 0.83 seconds
Started Apr 30 02:26:27 PM PDT 24
Finished Apr 30 02:26:28 PM PDT 24
Peak memory 206000 kb
Host smart-d7df173a-f1c3-4045-a558-2d0b0ef0f4f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842335576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.842335576
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.481405012
Short name T917
Test name
Test status
Simulation time 62174598 ps
CPU time 1.38 seconds
Started Apr 30 02:26:28 PM PDT 24
Finished Apr 30 02:26:30 PM PDT 24
Peak memory 206348 kb
Host smart-5b74fa51-bf36-44e7-af05-64b93ee9ea7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481405012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.481405012
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2716560165
Short name T893
Test name
Test status
Simulation time 17615885 ps
CPU time 1.43 seconds
Started Apr 30 02:26:31 PM PDT 24
Finished Apr 30 02:26:33 PM PDT 24
Peak memory 214604 kb
Host smart-218dc7c0-f082-4ea4-9fdf-a05e681c0587
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716560165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2716560165
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.360582590
Short name T899
Test name
Test status
Simulation time 109614805 ps
CPU time 1.55 seconds
Started Apr 30 02:26:29 PM PDT 24
Finished Apr 30 02:26:31 PM PDT 24
Peak memory 206464 kb
Host smart-2648a7e5-e1a0-45fb-940f-84e1840eea10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360582590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.360582590
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1116183788
Short name T903
Test name
Test status
Simulation time 41270697 ps
CPU time 1.49 seconds
Started Apr 30 02:26:34 PM PDT 24
Finished Apr 30 02:26:37 PM PDT 24
Peak memory 214576 kb
Host smart-b646aa16-42be-452f-a097-c6327fad91d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116183788 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1116183788
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.257275059
Short name T879
Test name
Test status
Simulation time 24379358 ps
CPU time 0.9 seconds
Started Apr 30 02:26:34 PM PDT 24
Finished Apr 30 02:26:36 PM PDT 24
Peak memory 206256 kb
Host smart-c27a38ba-3419-4276-bcbd-19ad7045d97b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257275059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.257275059
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3648460732
Short name T908
Test name
Test status
Simulation time 15362022 ps
CPU time 0.87 seconds
Started Apr 30 02:26:34 PM PDT 24
Finished Apr 30 02:26:36 PM PDT 24
Peak memory 206204 kb
Host smart-d239915d-5fb6-42db-a252-9b7e7d621341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648460732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3648460732
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1067574782
Short name T887
Test name
Test status
Simulation time 16085361 ps
CPU time 1.03 seconds
Started Apr 30 02:26:34 PM PDT 24
Finished Apr 30 02:26:36 PM PDT 24
Peak memory 206408 kb
Host smart-4a91a587-e8dc-4d61-8b16-a8aba75b815f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067574782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1067574782
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2248676088
Short name T924
Test name
Test status
Simulation time 218957354 ps
CPU time 4.31 seconds
Started Apr 30 02:26:28 PM PDT 24
Finished Apr 30 02:26:33 PM PDT 24
Peak memory 214660 kb
Host smart-6244eb65-bbff-4623-afd3-01750d6ff7fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248676088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2248676088
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3014570429
Short name T248
Test name
Test status
Simulation time 95265013 ps
CPU time 2.55 seconds
Started Apr 30 02:26:38 PM PDT 24
Finished Apr 30 02:26:42 PM PDT 24
Peak memory 206616 kb
Host smart-327ad465-d534-4edd-a754-f08ecfc8a85e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014570429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3014570429
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3764791926
Short name T949
Test name
Test status
Simulation time 57562260 ps
CPU time 1.47 seconds
Started Apr 30 02:26:34 PM PDT 24
Finished Apr 30 02:26:37 PM PDT 24
Peak memory 218180 kb
Host smart-4160b99c-52bb-41f5-a852-469d83b19474
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764791926 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3764791926
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1741905921
Short name T935
Test name
Test status
Simulation time 12103098 ps
CPU time 0.85 seconds
Started Apr 30 02:26:35 PM PDT 24
Finished Apr 30 02:26:37 PM PDT 24
Peak memory 206356 kb
Host smart-c5b468b8-be4b-400e-b1aa-87adb0f95e68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741905921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1741905921
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.107405581
Short name T873
Test name
Test status
Simulation time 28531260 ps
CPU time 0.88 seconds
Started Apr 30 02:26:35 PM PDT 24
Finished Apr 30 02:26:36 PM PDT 24
Peak memory 206140 kb
Host smart-89209bba-2c01-4d3e-84fd-3e4ac4889952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107405581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.107405581
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2602648874
Short name T214
Test name
Test status
Simulation time 107301704 ps
CPU time 1.06 seconds
Started Apr 30 02:26:34 PM PDT 24
Finished Apr 30 02:26:36 PM PDT 24
Peak memory 206276 kb
Host smart-2a0f00e9-77cf-485f-9799-d731d85c997f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602648874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2602648874
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3802574952
Short name T911
Test name
Test status
Simulation time 84018877 ps
CPU time 2.86 seconds
Started Apr 30 02:26:35 PM PDT 24
Finished Apr 30 02:26:39 PM PDT 24
Peak memory 214564 kb
Host smart-efaf2909-6870-4dd3-a804-b049a48eeed3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802574952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3802574952
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.364082524
Short name T850
Test name
Test status
Simulation time 101604333 ps
CPU time 1.83 seconds
Started Apr 30 02:26:34 PM PDT 24
Finished Apr 30 02:26:36 PM PDT 24
Peak memory 214516 kb
Host smart-1095d485-65b4-430f-8cbd-3a9db2423ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364082524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.364082524
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.4184307995
Short name T853
Test name
Test status
Simulation time 50289303 ps
CPU time 1.71 seconds
Started Apr 30 02:26:46 PM PDT 24
Finished Apr 30 02:26:48 PM PDT 24
Peak memory 214640 kb
Host smart-517e9e81-1818-4338-a024-efba8dd1aae5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184307995 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.4184307995
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.580594603
Short name T230
Test name
Test status
Simulation time 19954306 ps
CPU time 0.92 seconds
Started Apr 30 02:26:44 PM PDT 24
Finished Apr 30 02:26:46 PM PDT 24
Peak memory 206272 kb
Host smart-122e093e-e286-4a20-8227-f2c4099cb129
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580594603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.580594603
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.721571149
Short name T867
Test name
Test status
Simulation time 15266621 ps
CPU time 0.91 seconds
Started Apr 30 02:26:43 PM PDT 24
Finished Apr 30 02:26:45 PM PDT 24
Peak memory 206164 kb
Host smart-bd0df1ce-897b-4095-8189-01a10f668002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721571149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.721571149
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1050705395
Short name T913
Test name
Test status
Simulation time 69446614 ps
CPU time 1.06 seconds
Started Apr 30 02:26:44 PM PDT 24
Finished Apr 30 02:26:46 PM PDT 24
Peak memory 206436 kb
Host smart-bced9f44-97e8-4937-bf7a-23410acbb574
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050705395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1050705395
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1164580711
Short name T939
Test name
Test status
Simulation time 71979024 ps
CPU time 2.81 seconds
Started Apr 30 02:26:38 PM PDT 24
Finished Apr 30 02:26:42 PM PDT 24
Peak memory 214576 kb
Host smart-67d57fd1-1547-42fb-ac14-a283d4330a9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164580711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1164580711
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.869107062
Short name T251
Test name
Test status
Simulation time 148216989 ps
CPU time 3.37 seconds
Started Apr 30 02:26:34 PM PDT 24
Finished Apr 30 02:26:38 PM PDT 24
Peak memory 214488 kb
Host smart-5b8ba33e-d939-43b6-a76c-41d15c368552
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869107062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.869107062
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2609591582
Short name T906
Test name
Test status
Simulation time 23676533 ps
CPU time 1.48 seconds
Started Apr 30 02:26:45 PM PDT 24
Finished Apr 30 02:26:47 PM PDT 24
Peak memory 214584 kb
Host smart-dee24d2a-ed30-4fd6-ad00-adea7db081d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609591582 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2609591582
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.403249578
Short name T228
Test name
Test status
Simulation time 16930557 ps
CPU time 0.97 seconds
Started Apr 30 02:26:45 PM PDT 24
Finished Apr 30 02:26:47 PM PDT 24
Peak memory 206352 kb
Host smart-9a8b181c-db52-4dd9-9332-4c4bac156d19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403249578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.403249578
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.779481817
Short name T869
Test name
Test status
Simulation time 13003767 ps
CPU time 0.87 seconds
Started Apr 30 02:26:44 PM PDT 24
Finished Apr 30 02:26:45 PM PDT 24
Peak memory 206236 kb
Host smart-07a6267c-b91d-47ff-be12-87a0750ba06a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779481817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.779481817
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3627732510
Short name T918
Test name
Test status
Simulation time 74891932 ps
CPU time 1 seconds
Started Apr 30 02:26:44 PM PDT 24
Finished Apr 30 02:26:46 PM PDT 24
Peak memory 206336 kb
Host smart-45f02ac8-452c-4a18-8639-ea24ee3237d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627732510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3627732510
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1269436864
Short name T896
Test name
Test status
Simulation time 137746134 ps
CPU time 2.6 seconds
Started Apr 30 02:26:45 PM PDT 24
Finished Apr 30 02:26:48 PM PDT 24
Peak memory 214576 kb
Host smart-70f9835e-1f42-48f5-a878-9debc0a158cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269436864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1269436864
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3680328
Short name T877
Test name
Test status
Simulation time 298084380 ps
CPU time 5.1 seconds
Started Apr 30 02:26:44 PM PDT 24
Finished Apr 30 02:26:49 PM PDT 24
Peak memory 206528 kb
Host smart-79bb899b-972b-46d9-9fe1-d3c100379fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3680328
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3664404237
Short name T940
Test name
Test status
Simulation time 101255623 ps
CPU time 1.7 seconds
Started Apr 30 02:26:55 PM PDT 24
Finished Apr 30 02:26:57 PM PDT 24
Peak memory 214492 kb
Host smart-e3dba887-818c-4a3e-92a8-8365db48867b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664404237 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3664404237
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2593031640
Short name T897
Test name
Test status
Simulation time 23487326 ps
CPU time 0.83 seconds
Started Apr 30 02:26:55 PM PDT 24
Finished Apr 30 02:26:57 PM PDT 24
Peak memory 206072 kb
Host smart-65225c0d-a8db-45f5-942f-dfb1b91608ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593031640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2593031640
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2258231431
Short name T931
Test name
Test status
Simulation time 14224811 ps
CPU time 0.88 seconds
Started Apr 30 02:26:54 PM PDT 24
Finished Apr 30 02:26:56 PM PDT 24
Peak memory 206224 kb
Host smart-5f2b10c2-51d0-4358-b79c-23fe528ec53c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258231431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2258231431
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3631686951
Short name T235
Test name
Test status
Simulation time 40965136 ps
CPU time 1.13 seconds
Started Apr 30 02:26:53 PM PDT 24
Finished Apr 30 02:26:55 PM PDT 24
Peak memory 206348 kb
Host smart-b013ff7e-f868-444d-ad24-992f70cf4429
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631686951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3631686951
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.184492787
Short name T954
Test name
Test status
Simulation time 117410702 ps
CPU time 4.19 seconds
Started Apr 30 02:26:45 PM PDT 24
Finished Apr 30 02:26:50 PM PDT 24
Peak memory 214564 kb
Host smart-83e253aa-aa3c-4de8-8a63-27c5031f7961
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184492787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.184492787
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2979151481
Short name T971
Test name
Test status
Simulation time 85604658 ps
CPU time 1.69 seconds
Started Apr 30 02:26:42 PM PDT 24
Finished Apr 30 02:26:45 PM PDT 24
Peak memory 206356 kb
Host smart-c32ab1e0-4d0b-454d-9f69-206cc21b8230
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979151481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2979151481
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.325814375
Short name T220
Test name
Test status
Simulation time 25598083 ps
CPU time 1.19 seconds
Started Apr 30 02:25:53 PM PDT 24
Finished Apr 30 02:25:55 PM PDT 24
Peak memory 206344 kb
Host smart-b411a6dc-f4b6-4482-b172-1c7eac09c8e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325814375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.325814375
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2596949854
Short name T932
Test name
Test status
Simulation time 359965765 ps
CPU time 3.15 seconds
Started Apr 30 02:25:54 PM PDT 24
Finished Apr 30 02:25:58 PM PDT 24
Peak memory 206348 kb
Host smart-1a3e293a-93d0-46a3-8d3b-31070095b587
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596949854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2596949854
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1312845791
Short name T930
Test name
Test status
Simulation time 27951337 ps
CPU time 0.96 seconds
Started Apr 30 02:25:52 PM PDT 24
Finished Apr 30 02:25:54 PM PDT 24
Peak memory 206244 kb
Host smart-c835b384-9c28-4e15-8bd0-f6e293a65228
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312845791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1312845791
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1180638610
Short name T937
Test name
Test status
Simulation time 20197827 ps
CPU time 1.24 seconds
Started Apr 30 02:25:52 PM PDT 24
Finished Apr 30 02:25:54 PM PDT 24
Peak memory 214636 kb
Host smart-fa7291ce-3b9b-4cf1-87f2-5429426302f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180638610 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1180638610
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2220709524
Short name T227
Test name
Test status
Simulation time 17038299 ps
CPU time 1.05 seconds
Started Apr 30 02:25:52 PM PDT 24
Finished Apr 30 02:25:54 PM PDT 24
Peak memory 206276 kb
Host smart-4e28fdc9-17d3-44ca-a933-16168dbcc0a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220709524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2220709524
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.527270955
Short name T874
Test name
Test status
Simulation time 11381347 ps
CPU time 0.84 seconds
Started Apr 30 02:25:55 PM PDT 24
Finished Apr 30 02:25:57 PM PDT 24
Peak memory 206188 kb
Host smart-214caa9d-59d2-4c29-85a3-fcb8bbcbbac3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527270955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.527270955
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.7911607
Short name T941
Test name
Test status
Simulation time 27282836 ps
CPU time 1.01 seconds
Started Apr 30 02:25:52 PM PDT 24
Finished Apr 30 02:25:54 PM PDT 24
Peak memory 206300 kb
Host smart-35d8d76b-2f5d-403b-a1c8-c73a61d779f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7911607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outst
anding.7911607
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.337950452
Short name T895
Test name
Test status
Simulation time 73137994 ps
CPU time 2.69 seconds
Started Apr 30 02:25:56 PM PDT 24
Finished Apr 30 02:26:00 PM PDT 24
Peak memory 214472 kb
Host smart-d3875d56-9b4b-4357-8f58-911636a27085
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337950452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.337950452
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3259034694
Short name T237
Test name
Test status
Simulation time 1931211417 ps
CPU time 3.87 seconds
Started Apr 30 02:25:55 PM PDT 24
Finished Apr 30 02:26:00 PM PDT 24
Peak memory 206656 kb
Host smart-03dca81c-30e8-4895-b317-2118e54d2e58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259034694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3259034694
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3481928754
Short name T902
Test name
Test status
Simulation time 10531391 ps
CPU time 0.82 seconds
Started Apr 30 02:26:54 PM PDT 24
Finished Apr 30 02:26:55 PM PDT 24
Peak memory 205936 kb
Host smart-fee92d39-cfd1-48ed-97d5-cdc2de2d2e3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481928754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3481928754
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3201134532
Short name T872
Test name
Test status
Simulation time 13034908 ps
CPU time 0.86 seconds
Started Apr 30 02:26:53 PM PDT 24
Finished Apr 30 02:26:55 PM PDT 24
Peak memory 206180 kb
Host smart-d43a6c39-2f0c-4bad-b97c-518e917c5ed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201134532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3201134532
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3959866201
Short name T977
Test name
Test status
Simulation time 55652365 ps
CPU time 0.9 seconds
Started Apr 30 02:26:54 PM PDT 24
Finished Apr 30 02:26:56 PM PDT 24
Peak memory 206132 kb
Host smart-bb5b5098-13dc-4162-9cfd-4ac9422e7f94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959866201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3959866201
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1842635196
Short name T945
Test name
Test status
Simulation time 28429661 ps
CPU time 0.76 seconds
Started Apr 30 02:26:57 PM PDT 24
Finished Apr 30 02:26:59 PM PDT 24
Peak memory 205952 kb
Host smart-a42b68e9-2ee8-456a-b485-b9c8c43f3307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842635196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1842635196
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2174102453
Short name T870
Test name
Test status
Simulation time 14351184 ps
CPU time 0.84 seconds
Started Apr 30 02:26:54 PM PDT 24
Finished Apr 30 02:26:56 PM PDT 24
Peak memory 206224 kb
Host smart-d05b11dd-8d45-4173-a2a2-abbad254a2bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174102453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2174102453
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3886799365
Short name T976
Test name
Test status
Simulation time 15982228 ps
CPU time 0.89 seconds
Started Apr 30 02:26:56 PM PDT 24
Finished Apr 30 02:26:57 PM PDT 24
Peak memory 206196 kb
Host smart-8ba74023-295c-43c9-a264-cf6192a77a98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886799365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3886799365
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3850958542
Short name T865
Test name
Test status
Simulation time 14903577 ps
CPU time 0.94 seconds
Started Apr 30 02:26:57 PM PDT 24
Finished Apr 30 02:26:58 PM PDT 24
Peak memory 206328 kb
Host smart-3efcc7ed-11a6-4c22-93b3-8e214bad4443
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850958542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3850958542
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2905981438
Short name T926
Test name
Test status
Simulation time 24409934 ps
CPU time 0.91 seconds
Started Apr 30 02:26:57 PM PDT 24
Finished Apr 30 02:26:59 PM PDT 24
Peak memory 206144 kb
Host smart-5fabef4b-1e8b-4bde-8278-312c84c34978
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905981438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2905981438
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2270615162
Short name T963
Test name
Test status
Simulation time 31628073 ps
CPU time 0.89 seconds
Started Apr 30 02:26:56 PM PDT 24
Finished Apr 30 02:26:58 PM PDT 24
Peak memory 206244 kb
Host smart-ac4a052c-f0c1-43a0-9e98-ab5528ad7048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270615162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2270615162
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.4043968156
Short name T922
Test name
Test status
Simulation time 24645096 ps
CPU time 0.96 seconds
Started Apr 30 02:27:02 PM PDT 24
Finished Apr 30 02:27:04 PM PDT 24
Peak memory 206180 kb
Host smart-45162786-c09c-463e-93a5-0bebfdf7b7ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043968156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.4043968156
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2663832146
Short name T218
Test name
Test status
Simulation time 62584914 ps
CPU time 1.21 seconds
Started Apr 30 02:25:51 PM PDT 24
Finished Apr 30 02:25:53 PM PDT 24
Peak memory 206356 kb
Host smart-751181b2-3639-4f29-90d2-2a9206718b7d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663832146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2663832146
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2963277827
Short name T856
Test name
Test status
Simulation time 120625160 ps
CPU time 3.4 seconds
Started Apr 30 02:25:52 PM PDT 24
Finished Apr 30 02:25:56 PM PDT 24
Peak memory 206248 kb
Host smart-9de26287-bc66-44ac-bd1d-d89077affdf3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963277827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2963277827
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.345829081
Short name T868
Test name
Test status
Simulation time 27891873 ps
CPU time 0.99 seconds
Started Apr 30 02:25:52 PM PDT 24
Finished Apr 30 02:25:54 PM PDT 24
Peak memory 206256 kb
Host smart-29ee4718-edfa-43e4-bbad-ad30d2ab4e64
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345829081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.345829081
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3084306037
Short name T862
Test name
Test status
Simulation time 67132060 ps
CPU time 1.1 seconds
Started Apr 30 02:25:51 PM PDT 24
Finished Apr 30 02:25:53 PM PDT 24
Peak memory 216204 kb
Host smart-89f9a439-65ac-4c93-9019-bce023b10636
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084306037 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3084306037
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2471957887
Short name T225
Test name
Test status
Simulation time 35729171 ps
CPU time 0.85 seconds
Started Apr 30 02:25:52 PM PDT 24
Finished Apr 30 02:25:54 PM PDT 24
Peak memory 206288 kb
Host smart-63e50922-8b71-46d8-8944-13a002d5eaea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471957887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2471957887
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2633691338
Short name T909
Test name
Test status
Simulation time 16975061 ps
CPU time 0.99 seconds
Started Apr 30 02:25:55 PM PDT 24
Finished Apr 30 02:25:57 PM PDT 24
Peak memory 206396 kb
Host smart-51c83f3e-66ba-4dad-8af6-b0600efb5d04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633691338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2633691338
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.214187077
Short name T213
Test name
Test status
Simulation time 15284460 ps
CPU time 1.05 seconds
Started Apr 30 02:25:54 PM PDT 24
Finished Apr 30 02:25:56 PM PDT 24
Peak memory 206372 kb
Host smart-af1704b4-855e-450f-b9fc-93fc93966894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214187077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.214187077
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2380671626
Short name T905
Test name
Test status
Simulation time 36821487 ps
CPU time 2.5 seconds
Started Apr 30 02:25:51 PM PDT 24
Finished Apr 30 02:25:54 PM PDT 24
Peak memory 218668 kb
Host smart-abe075a8-ae90-4bb2-9450-97730ccfceb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380671626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2380671626
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3115517906
Short name T238
Test name
Test status
Simulation time 91781282 ps
CPU time 1.61 seconds
Started Apr 30 02:25:52 PM PDT 24
Finished Apr 30 02:25:55 PM PDT 24
Peak memory 214584 kb
Host smart-9bf56b92-4a3f-4fa2-b265-17dbc58c69a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115517906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3115517906
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3201823121
Short name T863
Test name
Test status
Simulation time 37364924 ps
CPU time 0.83 seconds
Started Apr 30 02:27:00 PM PDT 24
Finished Apr 30 02:27:02 PM PDT 24
Peak memory 205928 kb
Host smart-5f7165d2-eeb2-4965-9ee7-7bf2e1259b46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201823121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3201823121
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1012311001
Short name T962
Test name
Test status
Simulation time 13885966 ps
CPU time 0.87 seconds
Started Apr 30 02:26:59 PM PDT 24
Finished Apr 30 02:27:01 PM PDT 24
Peak memory 206208 kb
Host smart-7b0973db-7029-4d04-a99a-ec61dce3dcbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012311001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1012311001
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2605941897
Short name T901
Test name
Test status
Simulation time 12465379 ps
CPU time 0.84 seconds
Started Apr 30 02:27:01 PM PDT 24
Finished Apr 30 02:27:03 PM PDT 24
Peak memory 206140 kb
Host smart-e72a20b7-7ba3-4e1e-9890-7bee35ab840c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605941897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2605941897
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.317030518
Short name T890
Test name
Test status
Simulation time 93537926 ps
CPU time 0.85 seconds
Started Apr 30 02:27:02 PM PDT 24
Finished Apr 30 02:27:03 PM PDT 24
Peak memory 205980 kb
Host smart-e727a242-8403-48a3-9a05-af07048f86e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317030518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.317030518
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1333303660
Short name T955
Test name
Test status
Simulation time 22687509 ps
CPU time 0.86 seconds
Started Apr 30 02:27:04 PM PDT 24
Finished Apr 30 02:27:06 PM PDT 24
Peak memory 206396 kb
Host smart-6aa440bf-2529-4cf3-bba9-8e01a52de9b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333303660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1333303660
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1935684193
Short name T845
Test name
Test status
Simulation time 130335171 ps
CPU time 0.88 seconds
Started Apr 30 02:27:01 PM PDT 24
Finished Apr 30 02:27:03 PM PDT 24
Peak memory 206220 kb
Host smart-d8f72438-848c-4eac-8bcb-f5fd64dc9301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935684193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1935684193
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2091634919
Short name T878
Test name
Test status
Simulation time 53774483 ps
CPU time 0.92 seconds
Started Apr 30 02:27:00 PM PDT 24
Finished Apr 30 02:27:02 PM PDT 24
Peak memory 206204 kb
Host smart-d3b93a05-6bd2-4f91-ba05-e37c9066f708
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091634919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2091634919
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.612560906
Short name T956
Test name
Test status
Simulation time 36973800 ps
CPU time 0.86 seconds
Started Apr 30 02:27:03 PM PDT 24
Finished Apr 30 02:27:04 PM PDT 24
Peak memory 206172 kb
Host smart-7c688e4f-a48a-4474-8425-204880b91edc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612560906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.612560906
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.127672409
Short name T973
Test name
Test status
Simulation time 14779111 ps
CPU time 0.94 seconds
Started Apr 30 02:27:03 PM PDT 24
Finished Apr 30 02:27:04 PM PDT 24
Peak memory 206216 kb
Host smart-4605f6b2-7b1b-4ad2-bd14-43eb09f354e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127672409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.127672409
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3391429362
Short name T861
Test name
Test status
Simulation time 16191495 ps
CPU time 0.81 seconds
Started Apr 30 02:27:05 PM PDT 24
Finished Apr 30 02:27:06 PM PDT 24
Peak memory 206156 kb
Host smart-dd18cfe0-bcaa-4993-81e7-7fefc9cd1f27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391429362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3391429362
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.640632335
Short name T968
Test name
Test status
Simulation time 571741169 ps
CPU time 3.73 seconds
Started Apr 30 02:26:00 PM PDT 24
Finished Apr 30 02:26:05 PM PDT 24
Peak memory 206356 kb
Host smart-679bf8c9-e4bc-4d35-872b-72835112ff08
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640632335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.640632335
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3771325912
Short name T967
Test name
Test status
Simulation time 15523573 ps
CPU time 0.91 seconds
Started Apr 30 02:25:59 PM PDT 24
Finished Apr 30 02:26:01 PM PDT 24
Peak memory 206256 kb
Host smart-64257801-d767-462c-8f01-11077d45f2da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771325912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3771325912
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2877236815
Short name T965
Test name
Test status
Simulation time 118771038 ps
CPU time 1.51 seconds
Started Apr 30 02:25:58 PM PDT 24
Finished Apr 30 02:26:01 PM PDT 24
Peak memory 214668 kb
Host smart-e4aa1107-1f46-4a41-bb91-742655895407
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877236815 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2877236815
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2284850048
Short name T229
Test name
Test status
Simulation time 47620950 ps
CPU time 0.86 seconds
Started Apr 30 02:25:58 PM PDT 24
Finished Apr 30 02:26:00 PM PDT 24
Peak memory 206200 kb
Host smart-1cb62cbd-264d-40ed-a69c-17ef32e6b6d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284850048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2284850048
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2412825944
Short name T860
Test name
Test status
Simulation time 38067989 ps
CPU time 0.81 seconds
Started Apr 30 02:25:58 PM PDT 24
Finished Apr 30 02:25:59 PM PDT 24
Peak memory 206016 kb
Host smart-ff2ac035-9284-4cd0-bdde-087fafbbf449
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412825944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2412825944
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.664399308
Short name T233
Test name
Test status
Simulation time 69073553 ps
CPU time 1.01 seconds
Started Apr 30 02:25:59 PM PDT 24
Finished Apr 30 02:26:02 PM PDT 24
Peak memory 206328 kb
Host smart-c7b36c4b-17ac-4548-8ea2-375ac6a107d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664399308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.664399308
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.235692492
Short name T936
Test name
Test status
Simulation time 82711655 ps
CPU time 2.1 seconds
Started Apr 30 02:25:52 PM PDT 24
Finished Apr 30 02:25:55 PM PDT 24
Peak memory 214576 kb
Host smart-2efe5529-4cc6-4d4f-9e58-f3ddca59d7a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235692492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.235692492
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.877570592
Short name T952
Test name
Test status
Simulation time 148753856 ps
CPU time 2.32 seconds
Started Apr 30 02:25:51 PM PDT 24
Finished Apr 30 02:25:54 PM PDT 24
Peak memory 214504 kb
Host smart-a46acbb8-03a8-43b8-9a76-477ae1c1aa49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877570592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.877570592
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2300818576
Short name T910
Test name
Test status
Simulation time 15014398 ps
CPU time 0.87 seconds
Started Apr 30 02:27:05 PM PDT 24
Finished Apr 30 02:27:06 PM PDT 24
Peak memory 206156 kb
Host smart-30d5b93a-741e-453b-9f20-0f2cd3d64538
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300818576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2300818576
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2298970603
Short name T855
Test name
Test status
Simulation time 19801464 ps
CPU time 0.88 seconds
Started Apr 30 02:27:03 PM PDT 24
Finished Apr 30 02:27:04 PM PDT 24
Peak memory 206204 kb
Host smart-63432937-5d1a-462c-8907-a766f0fd30fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298970603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2298970603
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1845719548
Short name T881
Test name
Test status
Simulation time 24578558 ps
CPU time 0.9 seconds
Started Apr 30 02:27:05 PM PDT 24
Finished Apr 30 02:27:06 PM PDT 24
Peak memory 206152 kb
Host smart-64f44118-8c8a-4db3-901a-24e57f2965a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845719548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1845719548
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2089946654
Short name T859
Test name
Test status
Simulation time 16196273 ps
CPU time 0.9 seconds
Started Apr 30 02:27:05 PM PDT 24
Finished Apr 30 02:27:07 PM PDT 24
Peak memory 206152 kb
Host smart-bebceb96-f52f-46e5-82d8-173770816b1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089946654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2089946654
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.416196216
Short name T947
Test name
Test status
Simulation time 46519702 ps
CPU time 0.9 seconds
Started Apr 30 02:27:05 PM PDT 24
Finished Apr 30 02:27:07 PM PDT 24
Peak memory 206168 kb
Host smart-7b1a44c7-1392-4350-b079-8a60e0fdc44d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416196216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.416196216
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.997745671
Short name T961
Test name
Test status
Simulation time 13912764 ps
CPU time 0.87 seconds
Started Apr 30 02:27:11 PM PDT 24
Finished Apr 30 02:27:12 PM PDT 24
Peak memory 206220 kb
Host smart-e4a8f469-3b09-418e-97f5-ef4bed69e9b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997745671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.997745671
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1285945884
Short name T919
Test name
Test status
Simulation time 44104920 ps
CPU time 0.81 seconds
Started Apr 30 02:27:10 PM PDT 24
Finished Apr 30 02:27:12 PM PDT 24
Peak memory 205980 kb
Host smart-8fd51e24-a42b-4e6c-8c94-10c44428dbaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285945884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1285945884
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3638291829
Short name T948
Test name
Test status
Simulation time 72354607 ps
CPU time 0.77 seconds
Started Apr 30 02:27:09 PM PDT 24
Finished Apr 30 02:27:11 PM PDT 24
Peak memory 206056 kb
Host smart-373bee2d-d5b8-4a52-b8af-e5c7fa377777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638291829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3638291829
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2244455235
Short name T852
Test name
Test status
Simulation time 13527093 ps
CPU time 0.9 seconds
Started Apr 30 02:27:10 PM PDT 24
Finished Apr 30 02:27:12 PM PDT 24
Peak memory 206192 kb
Host smart-66aa8279-e345-4fe1-994b-7e8b2975efb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244455235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2244455235
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1117907560
Short name T951
Test name
Test status
Simulation time 22059413 ps
CPU time 0.88 seconds
Started Apr 30 02:27:09 PM PDT 24
Finished Apr 30 02:27:11 PM PDT 24
Peak memory 206184 kb
Host smart-faf4a974-1229-4092-8f67-44f71a1c3a9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117907560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1117907560
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1173300305
Short name T927
Test name
Test status
Simulation time 51857452 ps
CPU time 1.41 seconds
Started Apr 30 02:26:00 PM PDT 24
Finished Apr 30 02:26:02 PM PDT 24
Peak memory 214624 kb
Host smart-7ea5fb91-07b0-4514-99b4-5dd2d133b4a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173300305 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1173300305
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.315809654
Short name T912
Test name
Test status
Simulation time 45741658 ps
CPU time 0.81 seconds
Started Apr 30 02:26:00 PM PDT 24
Finished Apr 30 02:26:02 PM PDT 24
Peak memory 206328 kb
Host smart-ff071fca-257f-4179-9d15-9c66d19cf233
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315809654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.315809654
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.291781403
Short name T866
Test name
Test status
Simulation time 40034695 ps
CPU time 0.81 seconds
Started Apr 30 02:25:58 PM PDT 24
Finished Apr 30 02:26:00 PM PDT 24
Peak memory 206168 kb
Host smart-37f69966-2e45-41d1-825e-e829a9cb6f5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291781403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.291781403
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2839909555
Short name T966
Test name
Test status
Simulation time 450961020 ps
CPU time 1.39 seconds
Started Apr 30 02:25:59 PM PDT 24
Finished Apr 30 02:26:02 PM PDT 24
Peak memory 206144 kb
Host smart-a2bd4c4d-c378-4fbc-bd61-28800b41e2d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839909555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2839909555
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2917978712
Short name T848
Test name
Test status
Simulation time 1522413397 ps
CPU time 5.93 seconds
Started Apr 30 02:25:56 PM PDT 24
Finished Apr 30 02:26:03 PM PDT 24
Peak memory 214576 kb
Host smart-90463413-5be5-4779-87f3-9db3f0e713de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917978712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2917978712
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3930772991
Short name T972
Test name
Test status
Simulation time 551015591 ps
CPU time 1.63 seconds
Started Apr 30 02:25:58 PM PDT 24
Finished Apr 30 02:26:00 PM PDT 24
Peak memory 206452 kb
Host smart-17d205c7-47dc-4793-b345-6294c30b11e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930772991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3930772991
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.550210687
Short name T846
Test name
Test status
Simulation time 26208419 ps
CPU time 1.28 seconds
Started Apr 30 02:26:04 PM PDT 24
Finished Apr 30 02:26:06 PM PDT 24
Peak memory 214672 kb
Host smart-62bc6fac-0e50-4ca6-9c9d-332ecad7c25f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550210687 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.550210687
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.259778515
Short name T871
Test name
Test status
Simulation time 50053810 ps
CPU time 0.94 seconds
Started Apr 30 02:26:05 PM PDT 24
Finished Apr 30 02:26:07 PM PDT 24
Peak memory 206352 kb
Host smart-df761dd2-6baa-40c3-b154-28787d31f9b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259778515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.259778515
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.425446853
Short name T920
Test name
Test status
Simulation time 175253082 ps
CPU time 0.89 seconds
Started Apr 30 02:26:00 PM PDT 24
Finished Apr 30 02:26:02 PM PDT 24
Peak memory 206212 kb
Host smart-e8470639-6195-4e72-8efc-01a91e558021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425446853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.425446853
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.918335484
Short name T891
Test name
Test status
Simulation time 73494104 ps
CPU time 0.99 seconds
Started Apr 30 02:25:58 PM PDT 24
Finished Apr 30 02:26:00 PM PDT 24
Peak memory 206320 kb
Host smart-3ac2dc95-ac9a-428a-b0a3-91e340ca20fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918335484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.918335484
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.671504473
Short name T974
Test name
Test status
Simulation time 99583002 ps
CPU time 2.14 seconds
Started Apr 30 02:25:58 PM PDT 24
Finished Apr 30 02:26:02 PM PDT 24
Peak memory 214460 kb
Host smart-788195a8-3f52-47f0-8962-52e00b1c7660
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671504473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.671504473
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1022520117
Short name T851
Test name
Test status
Simulation time 54801961 ps
CPU time 1.86 seconds
Started Apr 30 02:25:59 PM PDT 24
Finished Apr 30 02:26:02 PM PDT 24
Peak memory 206580 kb
Host smart-7e36090d-8a36-4c54-b550-ba812774270d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022520117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1022520117
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.429405048
Short name T907
Test name
Test status
Simulation time 52416375 ps
CPU time 2.03 seconds
Started Apr 30 02:26:07 PM PDT 24
Finished Apr 30 02:26:10 PM PDT 24
Peak memory 214580 kb
Host smart-2a1c0454-9e9a-47f0-bb55-2d425e9fc2ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429405048 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.429405048
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.420405475
Short name T929
Test name
Test status
Simulation time 27414717 ps
CPU time 0.92 seconds
Started Apr 30 02:26:05 PM PDT 24
Finished Apr 30 02:26:07 PM PDT 24
Peak memory 206184 kb
Host smart-3592c52c-accc-4e8d-b5d3-711f523990e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420405475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.420405475
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2388392305
Short name T886
Test name
Test status
Simulation time 22086869 ps
CPU time 0.95 seconds
Started Apr 30 02:26:07 PM PDT 24
Finished Apr 30 02:26:09 PM PDT 24
Peak memory 206316 kb
Host smart-c13a5c51-173a-48b8-97d8-94c7e70c5789
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388392305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2388392305
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.787312461
Short name T882
Test name
Test status
Simulation time 26082707 ps
CPU time 1.76 seconds
Started Apr 30 02:26:08 PM PDT 24
Finished Apr 30 02:26:10 PM PDT 24
Peak memory 214768 kb
Host smart-506f93f9-0107-4f1e-9b73-50188a6c1bb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787312461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.787312461
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2713401859
Short name T950
Test name
Test status
Simulation time 138766857 ps
CPU time 1.55 seconds
Started Apr 30 02:26:06 PM PDT 24
Finished Apr 30 02:26:08 PM PDT 24
Peak memory 206400 kb
Host smart-76df495c-ffca-4c98-a2f7-092f63392a38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713401859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2713401859
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1423385910
Short name T933
Test name
Test status
Simulation time 20996228 ps
CPU time 0.97 seconds
Started Apr 30 02:26:07 PM PDT 24
Finished Apr 30 02:26:09 PM PDT 24
Peak memory 206308 kb
Host smart-ca6a135c-f3a5-4c52-87dc-44edf10e016c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423385910 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1423385910
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1636967280
Short name T224
Test name
Test status
Simulation time 34984044 ps
CPU time 0.89 seconds
Started Apr 30 02:26:05 PM PDT 24
Finished Apr 30 02:26:07 PM PDT 24
Peak memory 206372 kb
Host smart-a12edf11-5236-48bd-98ba-2273e76b742f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636967280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1636967280
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1835108843
Short name T953
Test name
Test status
Simulation time 97529255 ps
CPU time 0.92 seconds
Started Apr 30 02:26:05 PM PDT 24
Finished Apr 30 02:26:07 PM PDT 24
Peak memory 206096 kb
Host smart-5ee15839-a61a-4c68-a212-ff1d120ac4c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835108843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1835108843
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.112020594
Short name T923
Test name
Test status
Simulation time 73429621 ps
CPU time 1.06 seconds
Started Apr 30 02:26:06 PM PDT 24
Finished Apr 30 02:26:08 PM PDT 24
Peak memory 206392 kb
Host smart-89533fe4-bbc5-44e9-86d0-b513715e8463
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112020594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_out
standing.112020594
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.4153689673
Short name T957
Test name
Test status
Simulation time 80823910 ps
CPU time 2.9 seconds
Started Apr 30 02:26:05 PM PDT 24
Finished Apr 30 02:26:08 PM PDT 24
Peak memory 214556 kb
Host smart-67483e54-3fe7-4d0a-9d8d-16e5055be6b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153689673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.4153689673
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1831417422
Short name T904
Test name
Test status
Simulation time 101609948 ps
CPU time 1.8 seconds
Started Apr 30 02:26:08 PM PDT 24
Finished Apr 30 02:26:10 PM PDT 24
Peak memory 206544 kb
Host smart-7ebc560a-0d1c-49db-b19c-bf9ee9eba6ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831417422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1831417422
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2250741542
Short name T958
Test name
Test status
Simulation time 21947517 ps
CPU time 1.44 seconds
Started Apr 30 02:26:12 PM PDT 24
Finished Apr 30 02:26:13 PM PDT 24
Peak memory 214660 kb
Host smart-fd61e3be-01eb-4cc9-b28b-6d7682f19d35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250741542 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2250741542
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2104842740
Short name T226
Test name
Test status
Simulation time 113435436 ps
CPU time 0.82 seconds
Started Apr 30 02:26:11 PM PDT 24
Finished Apr 30 02:26:13 PM PDT 24
Peak memory 206008 kb
Host smart-a11c37af-b6ff-4aec-a746-40a33b557178
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104842740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2104842740
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1881722491
Short name T858
Test name
Test status
Simulation time 13528302 ps
CPU time 0.89 seconds
Started Apr 30 02:26:18 PM PDT 24
Finished Apr 30 02:26:19 PM PDT 24
Peak memory 206152 kb
Host smart-68bc32ae-b180-42ff-87b0-9fd91ac6e2c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881722491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1881722491
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.4004581958
Short name T234
Test name
Test status
Simulation time 31069764 ps
CPU time 1.39 seconds
Started Apr 30 02:26:12 PM PDT 24
Finished Apr 30 02:26:14 PM PDT 24
Peak memory 206344 kb
Host smart-c4e22113-9148-44dd-8703-407d9e2feba7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004581958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.4004581958
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.4161594632
Short name T969
Test name
Test status
Simulation time 1741599469 ps
CPU time 4.63 seconds
Started Apr 30 02:26:13 PM PDT 24
Finished Apr 30 02:26:18 PM PDT 24
Peak memory 214724 kb
Host smart-33d6150f-b2d4-4b7e-88b5-e8f1252f2ba3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161594632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.4161594632
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1354061199
Short name T249
Test name
Test status
Simulation time 175898317 ps
CPU time 1.5 seconds
Started Apr 30 02:26:12 PM PDT 24
Finished Apr 30 02:26:14 PM PDT 24
Peak memory 214444 kb
Host smart-bda09bbf-7410-4257-8bdb-a34535979dd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354061199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1354061199
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.3936543309
Short name T332
Test name
Test status
Simulation time 22285784 ps
CPU time 0.85 seconds
Started Apr 30 02:42:57 PM PDT 24
Finished Apr 30 02:42:59 PM PDT 24
Peak memory 206760 kb
Host smart-784cc269-64f5-4170-88f3-8db3c1c5948a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936543309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3936543309
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.2549831092
Short name T186
Test name
Test status
Simulation time 13792963 ps
CPU time 0.95 seconds
Started Apr 30 02:42:57 PM PDT 24
Finished Apr 30 02:42:59 PM PDT 24
Peak memory 216468 kb
Host smart-0dc48814-3306-41d1-82e2-16e6bf66cda3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549831092 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2549831092
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.320812491
Short name T430
Test name
Test status
Simulation time 28908825 ps
CPU time 0.97 seconds
Started Apr 30 02:42:53 PM PDT 24
Finished Apr 30 02:42:55 PM PDT 24
Peak memory 218464 kb
Host smart-aca04b68-ef4c-41d7-91a1-0e9d3d279d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320812491 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.320812491
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.831581324
Short name T245
Test name
Test status
Simulation time 44913164 ps
CPU time 1.57 seconds
Started Apr 30 02:42:58 PM PDT 24
Finished Apr 30 02:43:01 PM PDT 24
Peak memory 216956 kb
Host smart-dface869-c6b8-4af2-b504-16e8fdc16c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831581324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.831581324
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1363417856
Short name T19
Test name
Test status
Simulation time 268489512 ps
CPU time 4.73 seconds
Started Apr 30 02:42:56 PM PDT 24
Finished Apr 30 02:43:02 PM PDT 24
Peak memory 238988 kb
Host smart-dccac237-4c13-4fc4-bf97-dae5c228afc3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363417856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1363417856
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2931077495
Short name T638
Test name
Test status
Simulation time 24103944 ps
CPU time 0.93 seconds
Started Apr 30 02:42:55 PM PDT 24
Finished Apr 30 02:42:57 PM PDT 24
Peak memory 215096 kb
Host smart-a7c0b4b8-5b51-4304-af81-78ff157c04bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931077495 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2931077495
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2825892758
Short name T747
Test name
Test status
Simulation time 76188864 ps
CPU time 1.41 seconds
Started Apr 30 02:42:57 PM PDT 24
Finished Apr 30 02:42:59 PM PDT 24
Peak memory 215184 kb
Host smart-a29c9164-f093-4d94-94c4-87af1baec26e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825892758 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2825892758
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2605095099
Short name T423
Test name
Test status
Simulation time 74412799319 ps
CPU time 933.9 seconds
Started Apr 30 02:43:08 PM PDT 24
Finished Apr 30 02:58:42 PM PDT 24
Peak memory 220960 kb
Host smart-59a4eba4-6122-44b8-863b-4344ee7b7c8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605095099 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2605095099
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.446285520
Short name T750
Test name
Test status
Simulation time 148947206 ps
CPU time 1.26 seconds
Started Apr 30 02:43:01 PM PDT 24
Finished Apr 30 02:43:04 PM PDT 24
Peak memory 215576 kb
Host smart-ff0b7f5b-61f9-4766-a86f-2f6c822322b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446285520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.446285520
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.2840322718
Short name T456
Test name
Test status
Simulation time 44865114 ps
CPU time 0.9 seconds
Started Apr 30 02:42:56 PM PDT 24
Finished Apr 30 02:42:58 PM PDT 24
Peak memory 206400 kb
Host smart-1adc2fe2-7714-4fc0-ad15-0b5ca2e14536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840322718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2840322718
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.194115465
Short name T759
Test name
Test status
Simulation time 40595085 ps
CPU time 0.89 seconds
Started Apr 30 02:42:58 PM PDT 24
Finished Apr 30 02:43:00 PM PDT 24
Peak memory 216148 kb
Host smart-a435ac30-241c-4699-a7b1-f59f5ed1eb18
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194115465 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.194115465
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.649595813
Short name T833
Test name
Test status
Simulation time 37920207 ps
CPU time 0.95 seconds
Started Apr 30 02:42:55 PM PDT 24
Finished Apr 30 02:42:57 PM PDT 24
Peak memory 218472 kb
Host smart-e7500341-b888-46b1-8e79-70965f8989ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649595813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.649595813
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2100945033
Short name T655
Test name
Test status
Simulation time 142139928 ps
CPU time 1.33 seconds
Started Apr 30 02:42:55 PM PDT 24
Finished Apr 30 02:42:57 PM PDT 24
Peak memory 218300 kb
Host smart-3bef7b24-62f3-4485-8584-e15001744329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100945033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2100945033
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3812209739
Short name T460
Test name
Test status
Simulation time 25341664 ps
CPU time 0.96 seconds
Started Apr 30 02:42:56 PM PDT 24
Finished Apr 30 02:42:58 PM PDT 24
Peak memory 215352 kb
Host smart-507adb64-6bd5-4764-bfd0-c02776269f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812209739 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3812209739
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.4196455103
Short name T254
Test name
Test status
Simulation time 50958275 ps
CPU time 0.94 seconds
Started Apr 30 02:43:01 PM PDT 24
Finished Apr 30 02:43:03 PM PDT 24
Peak memory 206896 kb
Host smart-1b0c8bcb-00c4-4c4c-bd04-63121232d102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196455103 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.4196455103
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3174392937
Short name T67
Test name
Test status
Simulation time 1901494973 ps
CPU time 8.51 seconds
Started Apr 30 02:42:53 PM PDT 24
Finished Apr 30 02:43:02 PM PDT 24
Peak memory 236992 kb
Host smart-13018b0b-3794-482b-8eff-eb3b2877532b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174392937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3174392937
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2198903046
Short name T521
Test name
Test status
Simulation time 30748889 ps
CPU time 1 seconds
Started Apr 30 02:42:58 PM PDT 24
Finished Apr 30 02:43:00 PM PDT 24
Peak memory 215172 kb
Host smart-fce3e540-4568-4e22-8a0b-06abf2fb8d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198903046 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2198903046
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.4106654520
Short name T761
Test name
Test status
Simulation time 934558344 ps
CPU time 4.53 seconds
Started Apr 30 02:42:55 PM PDT 24
Finished Apr 30 02:43:01 PM PDT 24
Peak memory 216968 kb
Host smart-fdd5cf2a-3f7a-4127-ad64-e2dc0ada8633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106654520 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.4106654520
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3011036276
Short name T640
Test name
Test status
Simulation time 18690791629 ps
CPU time 487.87 seconds
Started Apr 30 02:42:56 PM PDT 24
Finished Apr 30 02:51:05 PM PDT 24
Peak memory 217304 kb
Host smart-45c8ed89-3655-4b61-9a60-a21ad31868ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011036276 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3011036276
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.2764166142
Short name T267
Test name
Test status
Simulation time 26843983 ps
CPU time 1.28 seconds
Started Apr 30 02:43:14 PM PDT 24
Finished Apr 30 02:43:16 PM PDT 24
Peak memory 215480 kb
Host smart-4b65198c-3155-42f0-bcb3-a5f33461f6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764166142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2764166142
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.41371571
Short name T75
Test name
Test status
Simulation time 17125136 ps
CPU time 0.96 seconds
Started Apr 30 02:43:11 PM PDT 24
Finished Apr 30 02:43:13 PM PDT 24
Peak memory 206548 kb
Host smart-f08a02fc-21d1-4d5e-a23f-e01ef6464e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41371571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.41371571
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.473478319
Short name T133
Test name
Test status
Simulation time 87215147 ps
CPU time 0.82 seconds
Started Apr 30 02:43:14 PM PDT 24
Finished Apr 30 02:43:16 PM PDT 24
Peak memory 215228 kb
Host smart-8ad35cbb-0dce-448c-ab4c-d92bc329d7e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473478319 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.473478319
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.221797297
Short name T119
Test name
Test status
Simulation time 62119625 ps
CPU time 1.09 seconds
Started Apr 30 02:43:10 PM PDT 24
Finished Apr 30 02:43:11 PM PDT 24
Peak memory 218040 kb
Host smart-1c52f945-d3bb-4a14-8a6a-002c095a5145
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221797297 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.221797297
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.2116984018
Short name T190
Test name
Test status
Simulation time 28365657 ps
CPU time 1.3 seconds
Started Apr 30 02:43:09 PM PDT 24
Finished Apr 30 02:43:11 PM PDT 24
Peak memory 233508 kb
Host smart-6cb8e002-cad7-4adc-bf8e-f71652b9d0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116984018 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2116984018
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.699216491
Short name T52
Test name
Test status
Simulation time 54551660 ps
CPU time 1.52 seconds
Started Apr 30 02:43:09 PM PDT 24
Finished Apr 30 02:43:11 PM PDT 24
Peak memory 216848 kb
Host smart-fdfe305b-c640-4a60-9274-e21674c9f511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699216491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.699216491
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.2120378704
Short name T579
Test name
Test status
Simulation time 22914173 ps
CPU time 1.18 seconds
Started Apr 30 02:43:10 PM PDT 24
Finished Apr 30 02:43:12 PM PDT 24
Peak memory 223848 kb
Host smart-a2ba6d38-0068-4cf5-9ccd-8db3dd83b369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120378704 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2120378704
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3183158670
Short name T838
Test name
Test status
Simulation time 25947967 ps
CPU time 0.92 seconds
Started Apr 30 02:43:14 PM PDT 24
Finished Apr 30 02:43:16 PM PDT 24
Peak memory 215092 kb
Host smart-da575c0e-0f30-4b1b-824e-c9dfded3209c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183158670 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3183158670
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1974716533
Short name T552
Test name
Test status
Simulation time 530613169 ps
CPU time 2.76 seconds
Started Apr 30 02:43:10 PM PDT 24
Finished Apr 30 02:43:14 PM PDT 24
Peak memory 216840 kb
Host smart-cb23b816-cefa-4057-a38e-496c35347b28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974716533 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1974716533
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3029917414
Short name T518
Test name
Test status
Simulation time 39873483161 ps
CPU time 123.46 seconds
Started Apr 30 02:43:09 PM PDT 24
Finished Apr 30 02:45:13 PM PDT 24
Peak memory 218384 kb
Host smart-6adf2fb3-e4e8-478c-925e-2be850c53997
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029917414 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3029917414
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.3850885779
Short name T803
Test name
Test status
Simulation time 91786538 ps
CPU time 1.37 seconds
Started Apr 30 02:44:39 PM PDT 24
Finished Apr 30 02:44:41 PM PDT 24
Peak memory 218144 kb
Host smart-37fa05b2-9fc3-4a7f-8b7d-bc62b4624164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850885779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3850885779
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.2580291986
Short name T624
Test name
Test status
Simulation time 206752983 ps
CPU time 1.23 seconds
Started Apr 30 02:44:28 PM PDT 24
Finished Apr 30 02:44:30 PM PDT 24
Peak memory 216896 kb
Host smart-c8224688-8c23-45c1-9366-52ed9869f4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580291986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2580291986
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.1007413279
Short name T350
Test name
Test status
Simulation time 58210582 ps
CPU time 2.04 seconds
Started Apr 30 02:44:29 PM PDT 24
Finished Apr 30 02:44:32 PM PDT 24
Peak memory 218184 kb
Host smart-0852f100-9083-49d1-9cd7-ffd4a05cfc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007413279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1007413279
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3413965054
Short name T687
Test name
Test status
Simulation time 45943865 ps
CPU time 1.52 seconds
Started Apr 30 02:44:29 PM PDT 24
Finished Apr 30 02:44:32 PM PDT 24
Peak memory 218076 kb
Host smart-546160a7-3d25-4648-8dbf-400afe3aa106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413965054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3413965054
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1899181439
Short name T87
Test name
Test status
Simulation time 136078693 ps
CPU time 1.37 seconds
Started Apr 30 02:44:29 PM PDT 24
Finished Apr 30 02:44:31 PM PDT 24
Peak memory 218204 kb
Host smart-6a7c08fc-c163-49ff-83e0-37ed9b20ebf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899181439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1899181439
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.2464332158
Short name T50
Test name
Test status
Simulation time 46068811 ps
CPU time 1.2 seconds
Started Apr 30 02:44:37 PM PDT 24
Finished Apr 30 02:44:39 PM PDT 24
Peak memory 216916 kb
Host smart-c2d0152c-ccca-42bb-a1da-34c9d8e373e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464332158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2464332158
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1677062243
Short name T837
Test name
Test status
Simulation time 54927875 ps
CPU time 1.35 seconds
Started Apr 30 02:44:28 PM PDT 24
Finished Apr 30 02:44:30 PM PDT 24
Peak memory 219552 kb
Host smart-bebe6d39-b52f-4fa9-b882-ae5c488199bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677062243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1677062243
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2963359364
Short name T522
Test name
Test status
Simulation time 45940308 ps
CPU time 1.52 seconds
Started Apr 30 02:44:35 PM PDT 24
Finished Apr 30 02:44:37 PM PDT 24
Peak memory 218896 kb
Host smart-220bdbb9-096f-4ebd-84be-fd3c087bceaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963359364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2963359364
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.56126266
Short name T675
Test name
Test status
Simulation time 66930908 ps
CPU time 1.68 seconds
Started Apr 30 02:44:27 PM PDT 24
Finished Apr 30 02:44:30 PM PDT 24
Peak memory 218472 kb
Host smart-177f3262-e13e-41c9-a852-a3f8b7e90d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56126266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.56126266
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.559139521
Short name T523
Test name
Test status
Simulation time 41915970 ps
CPU time 1.16 seconds
Started Apr 30 02:43:23 PM PDT 24
Finished Apr 30 02:43:25 PM PDT 24
Peak memory 215508 kb
Host smart-0a2e32d9-47c0-4135-85c8-ea0b0a09cb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559139521 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.559139521
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.557642764
Short name T766
Test name
Test status
Simulation time 28681147 ps
CPU time 0.93 seconds
Started Apr 30 02:43:17 PM PDT 24
Finished Apr 30 02:43:19 PM PDT 24
Peak memory 214784 kb
Host smart-a96a2c9b-951d-4077-be00-4846bc0c2eb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557642764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.557642764
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3379504438
Short name T742
Test name
Test status
Simulation time 69280001 ps
CPU time 1.08 seconds
Started Apr 30 02:43:21 PM PDT 24
Finished Apr 30 02:43:23 PM PDT 24
Peak memory 216684 kb
Host smart-f78aee8f-ec89-4ad7-b3e0-9b4d7924fcfd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379504438 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3379504438
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.2918746945
Short name T744
Test name
Test status
Simulation time 27337247 ps
CPU time 1.2 seconds
Started Apr 30 02:43:19 PM PDT 24
Finished Apr 30 02:43:21 PM PDT 24
Peak memory 220316 kb
Host smart-55bc2db6-9b84-40b0-bc77-4bc905afe847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918746945 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2918746945
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2841464517
Short name T594
Test name
Test status
Simulation time 118013185 ps
CPU time 2.09 seconds
Started Apr 30 02:43:07 PM PDT 24
Finished Apr 30 02:43:10 PM PDT 24
Peak memory 218284 kb
Host smart-852ba9b1-5945-4821-be1f-29ed3035127a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841464517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2841464517
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.1011628474
Short name T314
Test name
Test status
Simulation time 16522337 ps
CPU time 0.98 seconds
Started Apr 30 02:43:12 PM PDT 24
Finished Apr 30 02:43:15 PM PDT 24
Peak memory 215156 kb
Host smart-f13ab0d2-db10-49fb-a111-3b9496e93ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011628474 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1011628474
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2800924731
Short name T79
Test name
Test status
Simulation time 25871428707 ps
CPU time 566.72 seconds
Started Apr 30 02:43:17 PM PDT 24
Finished Apr 30 02:52:45 PM PDT 24
Peak memory 218236 kb
Host smart-0663d7b6-b41f-4df9-a872-7f1f8903ea7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800924731 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2800924731
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.edn_genbits.3784045065
Short name T558
Test name
Test status
Simulation time 133484301 ps
CPU time 2.14 seconds
Started Apr 30 02:44:41 PM PDT 24
Finished Apr 30 02:44:44 PM PDT 24
Peak memory 219760 kb
Host smart-110dccf4-85be-4979-a527-17e003b7e169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784045065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3784045065
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.590298737
Short name T748
Test name
Test status
Simulation time 86446024 ps
CPU time 1.16 seconds
Started Apr 30 02:44:43 PM PDT 24
Finished Apr 30 02:44:45 PM PDT 24
Peak memory 216776 kb
Host smart-e94d9549-a5ff-4db7-856c-4245e78e9235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590298737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.590298737
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.1869307642
Short name T516
Test name
Test status
Simulation time 124138710 ps
CPU time 1.23 seconds
Started Apr 30 02:44:38 PM PDT 24
Finished Apr 30 02:44:40 PM PDT 24
Peak memory 216928 kb
Host smart-89cd3665-87da-4e2a-9bdc-01fbb7996921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869307642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1869307642
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.2432042644
Short name T360
Test name
Test status
Simulation time 91303616 ps
CPU time 1.13 seconds
Started Apr 30 02:44:42 PM PDT 24
Finished Apr 30 02:44:44 PM PDT 24
Peak memory 216868 kb
Host smart-95679333-e8cc-4c6b-81cf-9b08d0b22243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432042644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2432042644
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.4181032902
Short name T487
Test name
Test status
Simulation time 67098578 ps
CPU time 1.09 seconds
Started Apr 30 02:44:48 PM PDT 24
Finished Apr 30 02:44:50 PM PDT 24
Peak memory 216984 kb
Host smart-b16fb70a-3fc9-4fec-9857-9dcd8397e370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181032902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.4181032902
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.146016487
Short name T329
Test name
Test status
Simulation time 142679418 ps
CPU time 2.06 seconds
Started Apr 30 02:44:46 PM PDT 24
Finished Apr 30 02:44:49 PM PDT 24
Peak memory 217304 kb
Host smart-fdf45e4c-f8a1-4a1f-9aa7-2163cafe5648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146016487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.146016487
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.2676141291
Short name T602
Test name
Test status
Simulation time 33334028 ps
CPU time 1.36 seconds
Started Apr 30 02:44:47 PM PDT 24
Finished Apr 30 02:44:50 PM PDT 24
Peak memory 216900 kb
Host smart-224ccb3f-6fd8-4590-9d24-4df3da080308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676141291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2676141291
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.217673490
Short name T782
Test name
Test status
Simulation time 353507638 ps
CPU time 3.79 seconds
Started Apr 30 02:44:34 PM PDT 24
Finished Apr 30 02:44:38 PM PDT 24
Peak memory 218412 kb
Host smart-e4d1ea5b-80f7-41e6-a904-b3a123a7bf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217673490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.217673490
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.4063153606
Short name T241
Test name
Test status
Simulation time 50462447 ps
CPU time 1.25 seconds
Started Apr 30 02:43:23 PM PDT 24
Finished Apr 30 02:43:25 PM PDT 24
Peak memory 215512 kb
Host smart-2423cf64-fea9-46a6-9734-917df91b70cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063153606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.4063153606
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_err.813851565
Short name T387
Test name
Test status
Simulation time 18898237 ps
CPU time 1.04 seconds
Started Apr 30 02:43:18 PM PDT 24
Finished Apr 30 02:43:20 PM PDT 24
Peak memory 218076 kb
Host smart-ec9578ca-93f8-4935-ab44-48f707c40765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813851565 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.813851565
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.208239702
Short name T819
Test name
Test status
Simulation time 61831071 ps
CPU time 1.34 seconds
Started Apr 30 02:43:17 PM PDT 24
Finished Apr 30 02:43:19 PM PDT 24
Peak memory 216964 kb
Host smart-2005760a-05f9-4424-9798-68b13d489ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208239702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.208239702
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.2487826466
Short name T667
Test name
Test status
Simulation time 21711186 ps
CPU time 1.32 seconds
Started Apr 30 02:43:19 PM PDT 24
Finished Apr 30 02:43:21 PM PDT 24
Peak memory 223916 kb
Host smart-83194b3a-1dbe-47cf-aaa8-6deb1b0447ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487826466 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2487826466
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.3013914861
Short name T80
Test name
Test status
Simulation time 18341995 ps
CPU time 1.04 seconds
Started Apr 30 02:43:22 PM PDT 24
Finished Apr 30 02:43:23 PM PDT 24
Peak memory 215108 kb
Host smart-d2d2fbfe-cb58-4e34-9351-793c0a298af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013914861 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3013914861
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2376449667
Short name T494
Test name
Test status
Simulation time 4084033099 ps
CPU time 4.96 seconds
Started Apr 30 02:43:18 PM PDT 24
Finished Apr 30 02:43:24 PM PDT 24
Peak memory 217056 kb
Host smart-197f102c-2e4a-43f1-b91e-4fad3a70a2ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376449667 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2376449667
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1318989462
Short name T793
Test name
Test status
Simulation time 56932750138 ps
CPU time 1498.45 seconds
Started Apr 30 02:43:17 PM PDT 24
Finished Apr 30 03:08:16 PM PDT 24
Peak memory 223884 kb
Host smart-84b64d7d-6676-4404-891e-5e09b41370d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318989462 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1318989462
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.66017623
Short name T295
Test name
Test status
Simulation time 850118726 ps
CPU time 5.29 seconds
Started Apr 30 02:44:41 PM PDT 24
Finished Apr 30 02:44:46 PM PDT 24
Peak memory 219536 kb
Host smart-bffa60c5-f639-4d71-a210-26964f56ce64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66017623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.66017623
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.645658401
Short name T710
Test name
Test status
Simulation time 49893150 ps
CPU time 1.84 seconds
Started Apr 30 02:44:51 PM PDT 24
Finished Apr 30 02:44:54 PM PDT 24
Peak memory 218080 kb
Host smart-43585149-3aad-458a-afc8-556b6f6de591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645658401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.645658401
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2048902396
Short name T729
Test name
Test status
Simulation time 30463306 ps
CPU time 1.18 seconds
Started Apr 30 02:44:49 PM PDT 24
Finished Apr 30 02:44:51 PM PDT 24
Peak memory 216940 kb
Host smart-0b1ec5a5-2341-40b8-9462-d84e93ebf7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048902396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2048902396
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.1508617487
Short name T520
Test name
Test status
Simulation time 30620748 ps
CPU time 1.19 seconds
Started Apr 30 02:44:54 PM PDT 24
Finished Apr 30 02:44:56 PM PDT 24
Peak memory 218144 kb
Host smart-ba486345-2581-48d1-98d9-05899ecf594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508617487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1508617487
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.1812502722
Short name T13
Test name
Test status
Simulation time 52840553 ps
CPU time 1.26 seconds
Started Apr 30 02:44:48 PM PDT 24
Finished Apr 30 02:44:50 PM PDT 24
Peak memory 219420 kb
Host smart-87b65f39-bdba-4a6b-8023-b065455ff9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812502722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1812502722
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3507407499
Short name T302
Test name
Test status
Simulation time 68329648 ps
CPU time 1.17 seconds
Started Apr 30 02:44:45 PM PDT 24
Finished Apr 30 02:44:47 PM PDT 24
Peak memory 215160 kb
Host smart-707426be-dd9a-45b8-ba30-18ffe4194574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507407499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3507407499
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.2064813756
Short name T613
Test name
Test status
Simulation time 49373923 ps
CPU time 1.32 seconds
Started Apr 30 02:44:43 PM PDT 24
Finished Apr 30 02:44:45 PM PDT 24
Peak memory 216852 kb
Host smart-e4a70246-b08d-459b-9acd-e1fea48dd95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064813756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2064813756
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2245656919
Short name T307
Test name
Test status
Simulation time 985504222 ps
CPU time 7.12 seconds
Started Apr 30 02:44:37 PM PDT 24
Finished Apr 30 02:44:45 PM PDT 24
Peak memory 218192 kb
Host smart-838a3f9d-6b9b-4f57-976d-2cde58bd5cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245656919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2245656919
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2567175867
Short name T723
Test name
Test status
Simulation time 77297777 ps
CPU time 1.17 seconds
Started Apr 30 02:43:17 PM PDT 24
Finished Apr 30 02:43:19 PM PDT 24
Peak memory 215524 kb
Host smart-f9e52a2c-298a-4252-90de-a5697fccb0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567175867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2567175867
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3657649602
Short name T580
Test name
Test status
Simulation time 33592749 ps
CPU time 0.83 seconds
Started Apr 30 02:43:18 PM PDT 24
Finished Apr 30 02:43:19 PM PDT 24
Peak memory 206344 kb
Host smart-498cf31c-e857-44c1-9e61-afb0787b9b92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657649602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3657649602
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3684723777
Short name T578
Test name
Test status
Simulation time 13750624 ps
CPU time 0.91 seconds
Started Apr 30 02:43:18 PM PDT 24
Finished Apr 30 02:43:19 PM PDT 24
Peak memory 216340 kb
Host smart-cca08f64-97ad-4af4-97b4-dbb0445e5fd3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684723777 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3684723777
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.373050956
Short name T537
Test name
Test status
Simulation time 38796773 ps
CPU time 1.31 seconds
Started Apr 30 02:43:20 PM PDT 24
Finished Apr 30 02:43:21 PM PDT 24
Peak memory 216732 kb
Host smart-a602f71a-2268-46dc-960e-7e7bca914cd5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373050956 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.373050956
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_genbits.4045201901
Short name T273
Test name
Test status
Simulation time 51680278 ps
CPU time 1.6 seconds
Started Apr 30 02:43:23 PM PDT 24
Finished Apr 30 02:43:26 PM PDT 24
Peak memory 218044 kb
Host smart-1129c2a4-5d5b-4188-828c-f60e9c88aa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045201901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.4045201901
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2182058020
Short name T477
Test name
Test status
Simulation time 36086836 ps
CPU time 1.01 seconds
Started Apr 30 02:43:18 PM PDT 24
Finished Apr 30 02:43:20 PM PDT 24
Peak memory 223728 kb
Host smart-b0f9cd93-9844-4f3f-a7b3-783676847f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182058020 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2182058020
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.3304747574
Short name T345
Test name
Test status
Simulation time 27912012 ps
CPU time 0.94 seconds
Started Apr 30 02:43:21 PM PDT 24
Finished Apr 30 02:43:23 PM PDT 24
Peak memory 215092 kb
Host smart-f2931739-c226-45ed-80da-6e6c0be704c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304747574 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3304747574
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.59572584
Short name T695
Test name
Test status
Simulation time 84267682 ps
CPU time 1.31 seconds
Started Apr 30 02:43:19 PM PDT 24
Finished Apr 30 02:43:21 PM PDT 24
Peak memory 217856 kb
Host smart-ba7ec13c-2fad-4a35-8b86-690591395dc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59572584 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.59572584
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.964905206
Short name T201
Test name
Test status
Simulation time 40892242041 ps
CPU time 539.35 seconds
Started Apr 30 02:43:20 PM PDT 24
Finished Apr 30 02:52:20 PM PDT 24
Peak memory 217512 kb
Host smart-16c7855a-19eb-451b-9553-d17cc825956c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964905206 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.964905206
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.2236680471
Short name T770
Test name
Test status
Simulation time 104833121 ps
CPU time 1.1 seconds
Started Apr 30 02:44:54 PM PDT 24
Finished Apr 30 02:44:56 PM PDT 24
Peak memory 216784 kb
Host smart-8beb3f2e-64b1-43c0-9c7c-1af2b7308ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236680471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2236680471
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.957172754
Short name T462
Test name
Test status
Simulation time 57692795 ps
CPU time 1.28 seconds
Started Apr 30 02:44:35 PM PDT 24
Finished Apr 30 02:44:37 PM PDT 24
Peak memory 218320 kb
Host smart-417f5aab-6f3a-48a3-9ff3-7697f27f34ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957172754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.957172754
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.2500086528
Short name T342
Test name
Test status
Simulation time 117633537 ps
CPU time 1.21 seconds
Started Apr 30 02:44:47 PM PDT 24
Finished Apr 30 02:44:49 PM PDT 24
Peak memory 216904 kb
Host smart-5862e6e8-71ae-447f-afd4-59495962d539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500086528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2500086528
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.1379581528
Short name T662
Test name
Test status
Simulation time 36747713 ps
CPU time 1.39 seconds
Started Apr 30 02:44:49 PM PDT 24
Finished Apr 30 02:44:51 PM PDT 24
Peak memory 216960 kb
Host smart-ba6f3ec8-5deb-41c8-8871-06ccdc5b4ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379581528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1379581528
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.3778608557
Short name T550
Test name
Test status
Simulation time 65166412 ps
CPU time 1.46 seconds
Started Apr 30 02:44:48 PM PDT 24
Finished Apr 30 02:44:51 PM PDT 24
Peak memory 218468 kb
Host smart-6fd3df10-c5a4-4400-9581-5516b2d21ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778608557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3778608557
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.3477100546
Short name T784
Test name
Test status
Simulation time 59972345 ps
CPU time 1.3 seconds
Started Apr 30 02:44:50 PM PDT 24
Finished Apr 30 02:44:52 PM PDT 24
Peak memory 219336 kb
Host smart-6a57a586-8af7-4518-90a0-89e49862ce67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477100546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3477100546
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.538517799
Short name T403
Test name
Test status
Simulation time 81921161 ps
CPU time 2.88 seconds
Started Apr 30 02:44:48 PM PDT 24
Finished Apr 30 02:44:52 PM PDT 24
Peak memory 219628 kb
Host smart-9cd8f1e9-082c-4f55-aabf-b2635b201a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538517799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.538517799
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.299613333
Short name T322
Test name
Test status
Simulation time 96378853 ps
CPU time 1.43 seconds
Started Apr 30 02:44:35 PM PDT 24
Finished Apr 30 02:44:37 PM PDT 24
Peak memory 218408 kb
Host smart-e8a36c42-1a7d-4f0b-826d-d2b0702ab39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299613333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.299613333
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3580677422
Short name T265
Test name
Test status
Simulation time 48706631 ps
CPU time 1.23 seconds
Started Apr 30 02:43:20 PM PDT 24
Finished Apr 30 02:43:22 PM PDT 24
Peak memory 215536 kb
Host smart-d696801c-8d03-4eec-9386-b9e6e7a1e304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580677422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3580677422
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.2105019331
Short name T565
Test name
Test status
Simulation time 55612672 ps
CPU time 0.82 seconds
Started Apr 30 02:43:22 PM PDT 24
Finished Apr 30 02:43:23 PM PDT 24
Peak memory 206264 kb
Host smart-0f464859-fbc6-40a8-8fc8-9b7c1f856848
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105019331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2105019331
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.2330620700
Short name T651
Test name
Test status
Simulation time 14085055 ps
CPU time 0.92 seconds
Started Apr 30 02:43:20 PM PDT 24
Finished Apr 30 02:43:22 PM PDT 24
Peak memory 216268 kb
Host smart-21fdd234-3ff9-48a5-a339-fd955a0e206e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330620700 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2330620700
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3922258457
Short name T634
Test name
Test status
Simulation time 138239212 ps
CPU time 1.03 seconds
Started Apr 30 02:43:20 PM PDT 24
Finished Apr 30 02:43:22 PM PDT 24
Peak memory 217800 kb
Host smart-682a7524-8cda-421e-b00d-3f90f6d424be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922258457 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3922258457
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3527563617
Short name T64
Test name
Test status
Simulation time 46635081 ps
CPU time 0.87 seconds
Started Apr 30 02:43:23 PM PDT 24
Finished Apr 30 02:43:25 PM PDT 24
Peak memory 218120 kb
Host smart-f0ee511a-8c94-4ad7-a0f1-f0019bb4f32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527563617 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3527563617
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3957532060
Short name T414
Test name
Test status
Simulation time 41361766 ps
CPU time 1.29 seconds
Started Apr 30 02:43:18 PM PDT 24
Finished Apr 30 02:43:20 PM PDT 24
Peak memory 218368 kb
Host smart-166de6f2-dffa-40c7-9a95-60d70a9bc174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957532060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3957532060
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.224015562
Short name T821
Test name
Test status
Simulation time 19658209 ps
CPU time 1.12 seconds
Started Apr 30 02:43:19 PM PDT 24
Finished Apr 30 02:43:21 PM PDT 24
Peak memory 215912 kb
Host smart-749fae29-bf7d-495b-bfce-7c34eb6f9133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224015562 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.224015562
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.1248275811
Short name T378
Test name
Test status
Simulation time 16668076 ps
CPU time 0.97 seconds
Started Apr 30 02:43:18 PM PDT 24
Finished Apr 30 02:43:20 PM PDT 24
Peak memory 215136 kb
Host smart-ba2ef349-1f14-4bfa-b6be-16e5f635f3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248275811 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1248275811
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2277093356
Short name T726
Test name
Test status
Simulation time 55477928 ps
CPU time 1.68 seconds
Started Apr 30 02:43:22 PM PDT 24
Finished Apr 30 02:43:24 PM PDT 24
Peak memory 215040 kb
Host smart-0a851864-c646-47d7-981b-f7a88f0ac608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277093356 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2277093356
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1200600300
Short name T209
Test name
Test status
Simulation time 21122541518 ps
CPU time 353.01 seconds
Started Apr 30 02:43:19 PM PDT 24
Finished Apr 30 02:49:13 PM PDT 24
Peak memory 217908 kb
Host smart-c1ecd695-f6be-42e6-a42c-34eda73162c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200600300 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1200600300
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.3596264666
Short name T311
Test name
Test status
Simulation time 29682786 ps
CPU time 1.37 seconds
Started Apr 30 02:44:39 PM PDT 24
Finished Apr 30 02:44:41 PM PDT 24
Peak memory 218192 kb
Host smart-e419a527-06b0-4546-8320-fb9cd0ff2c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596264666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3596264666
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.3518080206
Short name T587
Test name
Test status
Simulation time 281688961 ps
CPU time 1.42 seconds
Started Apr 30 02:44:33 PM PDT 24
Finished Apr 30 02:44:34 PM PDT 24
Peak memory 219688 kb
Host smart-80484294-172f-4e44-8c78-6be76cba9d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518080206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3518080206
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.62644983
Short name T682
Test name
Test status
Simulation time 89310946 ps
CPU time 1.83 seconds
Started Apr 30 02:44:48 PM PDT 24
Finished Apr 30 02:44:51 PM PDT 24
Peak memory 218464 kb
Host smart-9cabb846-9918-433d-b1e3-1c32b7df4189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62644983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.62644983
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.1513210639
Short name T491
Test name
Test status
Simulation time 61470297 ps
CPU time 2.45 seconds
Started Apr 30 02:44:49 PM PDT 24
Finished Apr 30 02:44:52 PM PDT 24
Peak memory 218192 kb
Host smart-24be90d6-7215-4f4b-92e5-8ce70f4a3539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513210639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1513210639
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.345670863
Short name T826
Test name
Test status
Simulation time 90783098 ps
CPU time 2.16 seconds
Started Apr 30 02:44:47 PM PDT 24
Finished Apr 30 02:44:51 PM PDT 24
Peak memory 219452 kb
Host smart-d526132a-da47-46d9-bd4f-ec785dc74211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345670863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.345670863
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.4017705099
Short name T549
Test name
Test status
Simulation time 48849068 ps
CPU time 1.47 seconds
Started Apr 30 02:44:52 PM PDT 24
Finished Apr 30 02:44:54 PM PDT 24
Peak memory 216760 kb
Host smart-814b13bc-078f-4e27-bd46-e97dfe94bbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017705099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.4017705099
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.4256842434
Short name T749
Test name
Test status
Simulation time 78467971 ps
CPU time 2.61 seconds
Started Apr 30 02:44:53 PM PDT 24
Finished Apr 30 02:44:56 PM PDT 24
Peak memory 219356 kb
Host smart-8a8f8a44-1280-47e7-a6d6-1506669b309d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256842434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.4256842434
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.183244441
Short name T812
Test name
Test status
Simulation time 49719905 ps
CPU time 1.52 seconds
Started Apr 30 02:44:45 PM PDT 24
Finished Apr 30 02:44:48 PM PDT 24
Peak memory 216796 kb
Host smart-0c88cbdc-d72f-42df-9ac2-3d492f9a1d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183244441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.183244441
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.659427184
Short name T11
Test name
Test status
Simulation time 39497341 ps
CPU time 1.5 seconds
Started Apr 30 02:44:45 PM PDT 24
Finished Apr 30 02:44:47 PM PDT 24
Peak memory 219344 kb
Host smart-b13aa10c-0c2f-4fa2-8c30-70460ea84b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659427184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.659427184
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.2781387466
Short name T47
Test name
Test status
Simulation time 121247662 ps
CPU time 1.3 seconds
Started Apr 30 02:44:44 PM PDT 24
Finished Apr 30 02:44:46 PM PDT 24
Peak memory 218416 kb
Host smart-030b8db7-5502-4aa2-9abb-119175077abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781387466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2781387466
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.1588576192
Short name T825
Test name
Test status
Simulation time 65609287 ps
CPU time 0.96 seconds
Started Apr 30 02:43:24 PM PDT 24
Finished Apr 30 02:43:25 PM PDT 24
Peak memory 206532 kb
Host smart-ec247435-4124-48c1-a36b-a65dbd069810
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588576192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1588576192
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1157531720
Short name T758
Test name
Test status
Simulation time 12162443 ps
CPU time 0.88 seconds
Started Apr 30 02:43:27 PM PDT 24
Finished Apr 30 02:43:29 PM PDT 24
Peak memory 207264 kb
Host smart-698d8535-1ab0-4fee-ae6b-7f5499daafe2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157531720 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1157531720
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3639396325
Short name T178
Test name
Test status
Simulation time 72255049 ps
CPU time 1.27 seconds
Started Apr 30 02:43:31 PM PDT 24
Finished Apr 30 02:43:33 PM PDT 24
Peak memory 216660 kb
Host smart-aacf632c-ea63-415e-a3c4-4f7feda6d44c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639396325 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3639396325
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.3972891423
Short name T177
Test name
Test status
Simulation time 19971276 ps
CPU time 1.08 seconds
Started Apr 30 02:43:26 PM PDT 24
Finished Apr 30 02:43:27 PM PDT 24
Peak memory 218380 kb
Host smart-7161dba2-1120-4e0d-8a27-dbad609734ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972891423 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3972891423
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1479250856
Short name T617
Test name
Test status
Simulation time 50338806 ps
CPU time 1.32 seconds
Started Apr 30 02:43:22 PM PDT 24
Finished Apr 30 02:43:24 PM PDT 24
Peak memory 217036 kb
Host smart-dbab8368-3539-4d9a-9871-60d57d4bbf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479250856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1479250856
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.3779480720
Short name T464
Test name
Test status
Simulation time 23907309 ps
CPU time 1.2 seconds
Started Apr 30 02:43:34 PM PDT 24
Finished Apr 30 02:43:35 PM PDT 24
Peak memory 223828 kb
Host smart-e29e3f1d-90e4-4897-9585-5f742a9c5bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779480720 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3779480720
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.186824267
Short name T500
Test name
Test status
Simulation time 14667141 ps
CPU time 0.97 seconds
Started Apr 30 02:43:18 PM PDT 24
Finished Apr 30 02:43:20 PM PDT 24
Peak memory 215092 kb
Host smart-e260b8ab-7267-4429-94cd-e9465c45fc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186824267 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.186824267
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.648906013
Short name T323
Test name
Test status
Simulation time 826634848 ps
CPU time 5.24 seconds
Started Apr 30 02:43:21 PM PDT 24
Finished Apr 30 02:43:27 PM PDT 24
Peak memory 220024 kb
Host smart-d98e4cbf-1137-4a7d-a022-23ca50af8f29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648906013 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.648906013
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1085218415
Short name T361
Test name
Test status
Simulation time 195297075332 ps
CPU time 1283.2 seconds
Started Apr 30 02:43:20 PM PDT 24
Finished Apr 30 03:04:44 PM PDT 24
Peak memory 224696 kb
Host smart-700d95a4-d8cb-462a-8425-60d43e40e599
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085218415 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1085218415
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.2089899742
Short name T829
Test name
Test status
Simulation time 38888192 ps
CPU time 1.61 seconds
Started Apr 30 02:44:50 PM PDT 24
Finished Apr 30 02:44:52 PM PDT 24
Peak memory 215120 kb
Host smart-576ec5cb-9a4d-4d70-8898-87dd0ba6c1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089899742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2089899742
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.1063722277
Short name T289
Test name
Test status
Simulation time 37587796 ps
CPU time 1.45 seconds
Started Apr 30 02:44:50 PM PDT 24
Finished Apr 30 02:44:52 PM PDT 24
Peak memory 218144 kb
Host smart-ae4f2835-018e-4dea-9ffd-64cdff628e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063722277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1063722277
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.1527731267
Short name T355
Test name
Test status
Simulation time 51711630 ps
CPU time 1.5 seconds
Started Apr 30 02:44:45 PM PDT 24
Finished Apr 30 02:44:48 PM PDT 24
Peak memory 218564 kb
Host smart-b9027df5-75a7-4091-8851-a6480dd67bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527731267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1527731267
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.257764069
Short name T441
Test name
Test status
Simulation time 48841239 ps
CPU time 1.28 seconds
Started Apr 30 02:44:44 PM PDT 24
Finished Apr 30 02:44:46 PM PDT 24
Peak memory 217972 kb
Host smart-a1b7a3c7-a57e-4c8c-adbc-41760b8e654c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257764069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.257764069
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.1869092996
Short name T530
Test name
Test status
Simulation time 38443533 ps
CPU time 1.49 seconds
Started Apr 30 02:44:54 PM PDT 24
Finished Apr 30 02:44:56 PM PDT 24
Peak memory 216900 kb
Host smart-c461a254-47b8-4303-ac3c-a19033263c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869092996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1869092996
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.4177749930
Short name T774
Test name
Test status
Simulation time 112568954 ps
CPU time 1.21 seconds
Started Apr 30 02:44:46 PM PDT 24
Finished Apr 30 02:44:48 PM PDT 24
Peak memory 219348 kb
Host smart-fbc80f33-0578-448f-9cf5-323240176faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177749930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.4177749930
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.2753138797
Short name T563
Test name
Test status
Simulation time 72219872 ps
CPU time 1.58 seconds
Started Apr 30 02:44:51 PM PDT 24
Finished Apr 30 02:44:53 PM PDT 24
Peak memory 218356 kb
Host smart-f9fdd6dc-6feb-443b-b51e-c91610b7ef13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753138797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2753138797
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.3448529931
Short name T808
Test name
Test status
Simulation time 63340557 ps
CPU time 2.3 seconds
Started Apr 30 02:44:50 PM PDT 24
Finished Apr 30 02:44:53 PM PDT 24
Peak memory 219688 kb
Host smart-03969ce7-8f50-4dd1-ae1e-a3db607425d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448529931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3448529931
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.3320428874
Short name T566
Test name
Test status
Simulation time 32820238 ps
CPU time 1.3 seconds
Started Apr 30 02:44:45 PM PDT 24
Finished Apr 30 02:44:48 PM PDT 24
Peak memory 218240 kb
Host smart-7d84dbe3-6fb8-473a-b466-bd392cfcac34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320428874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3320428874
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.546435896
Short name T485
Test name
Test status
Simulation time 48555711 ps
CPU time 1.59 seconds
Started Apr 30 02:44:47 PM PDT 24
Finished Apr 30 02:44:50 PM PDT 24
Peak memory 216836 kb
Host smart-2389fe4d-a0a9-4cef-aaca-638bac9a0018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546435896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.546435896
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.768173330
Short name T166
Test name
Test status
Simulation time 123470064 ps
CPU time 1.26 seconds
Started Apr 30 02:43:24 PM PDT 24
Finished Apr 30 02:43:26 PM PDT 24
Peak memory 215516 kb
Host smart-e7d3397d-dad5-48fb-8d20-a34c2ad48079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768173330 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.768173330
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.702926383
Short name T377
Test name
Test status
Simulation time 42217085 ps
CPU time 0.85 seconds
Started Apr 30 02:43:28 PM PDT 24
Finished Apr 30 02:43:30 PM PDT 24
Peak memory 206724 kb
Host smart-25517781-826c-4e89-b875-21ab08b76dae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702926383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.702926383
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.1843128589
Short name T92
Test name
Test status
Simulation time 11884575 ps
CPU time 0.89 seconds
Started Apr 30 02:43:27 PM PDT 24
Finished Apr 30 02:43:29 PM PDT 24
Peak memory 216044 kb
Host smart-b2b76be6-b97a-4999-9058-91985c0be2a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843128589 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1843128589
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.42183604
Short name T574
Test name
Test status
Simulation time 85136186 ps
CPU time 1.06 seconds
Started Apr 30 02:43:26 PM PDT 24
Finished Apr 30 02:43:28 PM PDT 24
Peak memory 216840 kb
Host smart-9150bf3e-c097-4048-9f1c-791897dfb034
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42183604 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_dis
able_auto_req_mode.42183604
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.196248791
Short name T380
Test name
Test status
Simulation time 29996222 ps
CPU time 0.88 seconds
Started Apr 30 02:43:29 PM PDT 24
Finished Apr 30 02:43:30 PM PDT 24
Peak memory 217852 kb
Host smart-c41461e6-7907-4212-8a04-28b1c2edc378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196248791 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.196248791
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2771716635
Short name T396
Test name
Test status
Simulation time 103997260 ps
CPU time 1.47 seconds
Started Apr 30 02:43:34 PM PDT 24
Finished Apr 30 02:43:37 PM PDT 24
Peak memory 218388 kb
Host smart-d7648546-201d-46b3-878b-b1676677dd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771716635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2771716635
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_smoke.323729712
Short name T24
Test name
Test status
Simulation time 24442456 ps
CPU time 0.99 seconds
Started Apr 30 02:43:26 PM PDT 24
Finished Apr 30 02:43:27 PM PDT 24
Peak memory 215160 kb
Host smart-a61905b9-70f8-4dbb-acec-9edac98e3dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323729712 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.323729712
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3948437029
Short name T698
Test name
Test status
Simulation time 231647506 ps
CPU time 4.77 seconds
Started Apr 30 02:43:35 PM PDT 24
Finished Apr 30 02:43:41 PM PDT 24
Peak memory 215180 kb
Host smart-2b599fc1-c1c1-4d99-88fb-8ab4e7d6b447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948437029 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3948437029
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1022218205
Short name T203
Test name
Test status
Simulation time 33125170128 ps
CPU time 766.28 seconds
Started Apr 30 02:43:24 PM PDT 24
Finished Apr 30 02:56:11 PM PDT 24
Peak memory 218172 kb
Host smart-28438e6b-9775-4eea-b83c-78150de70ded
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022218205 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1022218205
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.830500753
Short name T665
Test name
Test status
Simulation time 99392186 ps
CPU time 2.36 seconds
Started Apr 30 02:44:42 PM PDT 24
Finished Apr 30 02:44:45 PM PDT 24
Peak memory 218172 kb
Host smart-e367857b-a1c9-45d4-b63c-06aeabb81aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830500753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.830500753
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.3813616991
Short name T389
Test name
Test status
Simulation time 62273799 ps
CPU time 0.98 seconds
Started Apr 30 02:44:46 PM PDT 24
Finished Apr 30 02:44:48 PM PDT 24
Peak memory 216800 kb
Host smart-839f8169-7bd4-4517-aa29-b67fc6caa56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813616991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3813616991
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.861756189
Short name T724
Test name
Test status
Simulation time 35443411 ps
CPU time 1.29 seconds
Started Apr 30 02:44:48 PM PDT 24
Finished Apr 30 02:44:50 PM PDT 24
Peak memory 216792 kb
Host smart-6a1c2fb7-69ed-4c7b-a26a-8eb9b9cde872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861756189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.861756189
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.4101472081
Short name T407
Test name
Test status
Simulation time 37371238 ps
CPU time 1.82 seconds
Started Apr 30 02:44:48 PM PDT 24
Finished Apr 30 02:44:50 PM PDT 24
Peak memory 218116 kb
Host smart-9ee97909-f7de-4c2e-87ad-fead7fb8a008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101472081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.4101472081
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.474754143
Short name T296
Test name
Test status
Simulation time 315539463 ps
CPU time 1.25 seconds
Started Apr 30 02:44:40 PM PDT 24
Finished Apr 30 02:44:41 PM PDT 24
Peak memory 216856 kb
Host smart-620014bc-31a7-44b5-b6d0-6619dd0ca40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474754143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.474754143
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.8152
Short name T308
Test name
Test status
Simulation time 62380800 ps
CPU time 2.1 seconds
Started Apr 30 02:44:47 PM PDT 24
Finished Apr 30 02:44:50 PM PDT 24
Peak memory 217024 kb
Host smart-681df867-ea7c-4d3d-9994-c91153fd0688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.8152
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.2805513743
Short name T274
Test name
Test status
Simulation time 42839760 ps
CPU time 1.48 seconds
Started Apr 30 02:44:43 PM PDT 24
Finished Apr 30 02:44:46 PM PDT 24
Peak memory 218720 kb
Host smart-545ab516-9188-4fa9-928b-7de2a2da5b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805513743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2805513743
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.3606379576
Short name T369
Test name
Test status
Simulation time 56397050 ps
CPU time 1.67 seconds
Started Apr 30 02:44:53 PM PDT 24
Finished Apr 30 02:44:56 PM PDT 24
Peak memory 217852 kb
Host smart-8a816a89-4539-4e91-852a-8348e6bc602f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606379576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3606379576
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.2338670428
Short name T309
Test name
Test status
Simulation time 96736621 ps
CPU time 1.28 seconds
Started Apr 30 02:44:45 PM PDT 24
Finished Apr 30 02:44:48 PM PDT 24
Peak memory 218896 kb
Host smart-119bc641-ffc9-47b1-8ed3-fa05539821dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338670428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2338670428
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.339212919
Short name T799
Test name
Test status
Simulation time 28911990 ps
CPU time 1.25 seconds
Started Apr 30 02:43:27 PM PDT 24
Finished Apr 30 02:43:29 PM PDT 24
Peak memory 215456 kb
Host smart-98a0c62e-2671-4771-b950-475a38968a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339212919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.339212919
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2785566245
Short name T316
Test name
Test status
Simulation time 40441263 ps
CPU time 0.85 seconds
Started Apr 30 02:43:25 PM PDT 24
Finished Apr 30 02:43:27 PM PDT 24
Peak memory 206496 kb
Host smart-de77089f-f6d9-4133-9d9c-6876189ecd02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785566245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2785566245
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.693227004
Short name T188
Test name
Test status
Simulation time 176702254 ps
CPU time 0.85 seconds
Started Apr 30 02:43:29 PM PDT 24
Finished Apr 30 02:43:31 PM PDT 24
Peak memory 216052 kb
Host smart-764a43ab-087e-4f33-a5b0-5a4c497a8982
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693227004 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.693227004
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2349492210
Short name T730
Test name
Test status
Simulation time 30835632 ps
CPU time 1.01 seconds
Started Apr 30 02:43:28 PM PDT 24
Finished Apr 30 02:43:29 PM PDT 24
Peak memory 218052 kb
Host smart-e607ec1e-3e36-4bf7-9991-6f86d2837ae6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349492210 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2349492210
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.2090644619
Short name T115
Test name
Test status
Simulation time 23610895 ps
CPU time 1.22 seconds
Started Apr 30 02:43:26 PM PDT 24
Finished Apr 30 02:43:28 PM PDT 24
Peak memory 219700 kb
Host smart-872f2e5f-c93b-4cc3-b935-27ddffb90f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090644619 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2090644619
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_intr.3007993053
Short name T605
Test name
Test status
Simulation time 26957402 ps
CPU time 0.92 seconds
Started Apr 30 02:43:27 PM PDT 24
Finished Apr 30 02:43:29 PM PDT 24
Peak memory 215440 kb
Host smart-13c32f69-1120-4677-9bb0-ba692c19034b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007993053 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3007993053
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.785508672
Short name T515
Test name
Test status
Simulation time 14769640 ps
CPU time 0.94 seconds
Started Apr 30 02:43:25 PM PDT 24
Finished Apr 30 02:43:26 PM PDT 24
Peak memory 206940 kb
Host smart-904b9eca-f8a1-4a29-8fbe-00b6a45066ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785508672 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.785508672
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2449418875
Short name T635
Test name
Test status
Simulation time 140076312361 ps
CPU time 992.74 seconds
Started Apr 30 02:43:27 PM PDT 24
Finished Apr 30 03:00:01 PM PDT 24
Peak memory 223320 kb
Host smart-612bde89-e0a7-4c7e-9e39-e3366729eb67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449418875 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2449418875
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.2946950489
Short name T357
Test name
Test status
Simulation time 41079675 ps
CPU time 1.47 seconds
Started Apr 30 02:44:44 PM PDT 24
Finished Apr 30 02:44:46 PM PDT 24
Peak memory 217080 kb
Host smart-d247b675-30de-4a20-9ce7-5016623d4a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946950489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2946950489
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.2116020816
Short name T519
Test name
Test status
Simulation time 59436858 ps
CPU time 1.03 seconds
Started Apr 30 02:44:43 PM PDT 24
Finished Apr 30 02:44:45 PM PDT 24
Peak memory 216752 kb
Host smart-91b5c06b-f411-45c5-bc64-88c2405ec09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116020816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2116020816
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.3058724973
Short name T486
Test name
Test status
Simulation time 141467969 ps
CPU time 1.36 seconds
Started Apr 30 02:44:47 PM PDT 24
Finished Apr 30 02:44:50 PM PDT 24
Peak memory 218308 kb
Host smart-8779a700-e25d-46c7-af13-def2a8a203fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058724973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3058724973
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.514341193
Short name T82
Test name
Test status
Simulation time 28369857 ps
CPU time 1.27 seconds
Started Apr 30 02:44:48 PM PDT 24
Finished Apr 30 02:44:50 PM PDT 24
Peak memory 216844 kb
Host smart-2c77594b-e2db-471e-9005-02ca2354b876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514341193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.514341193
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.909834153
Short name T410
Test name
Test status
Simulation time 37329433 ps
CPU time 1.35 seconds
Started Apr 30 02:44:46 PM PDT 24
Finished Apr 30 02:44:48 PM PDT 24
Peak memory 218124 kb
Host smart-48647a77-50eb-4ebe-a1b9-6b33815337c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909834153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.909834153
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.3787293177
Short name T362
Test name
Test status
Simulation time 87645859 ps
CPU time 1.17 seconds
Started Apr 30 02:44:44 PM PDT 24
Finished Apr 30 02:44:46 PM PDT 24
Peak memory 216932 kb
Host smart-735a17aa-422c-41bc-a74f-445efd6a49e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787293177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3787293177
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.1231138156
Short name T55
Test name
Test status
Simulation time 98346413 ps
CPU time 1.16 seconds
Started Apr 30 02:44:47 PM PDT 24
Finished Apr 30 02:44:49 PM PDT 24
Peak memory 216892 kb
Host smart-0344605c-86c2-4628-b36d-cedfbf45522c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231138156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1231138156
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.3209297125
Short name T830
Test name
Test status
Simulation time 103962646 ps
CPU time 1.52 seconds
Started Apr 30 02:44:46 PM PDT 24
Finished Apr 30 02:44:49 PM PDT 24
Peak memory 218308 kb
Host smart-cb90b5db-9d70-4304-bf35-13b9c4ff72c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209297125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3209297125
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.905593779
Short name T718
Test name
Test status
Simulation time 44915170 ps
CPU time 1.28 seconds
Started Apr 30 02:44:45 PM PDT 24
Finished Apr 30 02:44:47 PM PDT 24
Peak memory 216888 kb
Host smart-22e48b43-0902-4433-a822-abeffcc8ad7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905593779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.905593779
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.851322275
Short name T71
Test name
Test status
Simulation time 47358075 ps
CPU time 1.18 seconds
Started Apr 30 02:43:25 PM PDT 24
Finished Apr 30 02:43:27 PM PDT 24
Peak memory 215532 kb
Host smart-0c426d1e-1cec-4a2b-ae2c-0ec4d79e1bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851322275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.851322275
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1227765729
Short name T327
Test name
Test status
Simulation time 17277281 ps
CPU time 0.84 seconds
Started Apr 30 02:43:29 PM PDT 24
Finished Apr 30 02:43:30 PM PDT 24
Peak memory 206492 kb
Host smart-2617ca08-e070-4c39-a87f-8475a3b43219
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227765729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1227765729
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1566428296
Short name T643
Test name
Test status
Simulation time 21916843 ps
CPU time 0.88 seconds
Started Apr 30 02:43:26 PM PDT 24
Finished Apr 30 02:43:27 PM PDT 24
Peak memory 215756 kb
Host smart-d3d44457-c011-4a0a-8425-23ccfc3e77c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566428296 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1566428296
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.2843471005
Short name T109
Test name
Test status
Simulation time 24775285 ps
CPU time 1.01 seconds
Started Apr 30 02:43:27 PM PDT 24
Finished Apr 30 02:43:28 PM PDT 24
Peak memory 219284 kb
Host smart-b62641b5-d06c-4e8d-a0e2-0ac822a73d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843471005 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2843471005
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3639834919
Short name T292
Test name
Test status
Simulation time 85850081 ps
CPU time 2.81 seconds
Started Apr 30 02:43:29 PM PDT 24
Finished Apr 30 02:43:32 PM PDT 24
Peak memory 218192 kb
Host smart-1b14056d-1ffd-46bc-861d-b76175697834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639834919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3639834919
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.703538600
Short name T34
Test name
Test status
Simulation time 24553885 ps
CPU time 0.92 seconds
Started Apr 30 02:43:26 PM PDT 24
Finished Apr 30 02:43:27 PM PDT 24
Peak memory 215708 kb
Host smart-5b653390-3d0a-47ca-9f1f-df3beb63f6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703538600 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.703538600
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.579987053
Short name T555
Test name
Test status
Simulation time 16652607 ps
CPU time 0.95 seconds
Started Apr 30 02:43:26 PM PDT 24
Finished Apr 30 02:43:27 PM PDT 24
Peak memory 206988 kb
Host smart-d5f3da91-97eb-43b4-8af8-e76414537df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579987053 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.579987053
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3759334130
Short name T598
Test name
Test status
Simulation time 383730025 ps
CPU time 3.98 seconds
Started Apr 30 02:43:27 PM PDT 24
Finished Apr 30 02:43:32 PM PDT 24
Peak memory 219596 kb
Host smart-d8845296-a491-42f9-b741-30e865b988c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759334130 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3759334130
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1165909556
Short name T571
Test name
Test status
Simulation time 56920111529 ps
CPU time 1227.98 seconds
Started Apr 30 02:43:27 PM PDT 24
Finished Apr 30 03:03:56 PM PDT 24
Peak memory 222532 kb
Host smart-35fb7bb8-ce38-469a-b437-7917819268b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165909556 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1165909556
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.2524233916
Short name T286
Test name
Test status
Simulation time 54808480 ps
CPU time 1.07 seconds
Started Apr 30 02:44:45 PM PDT 24
Finished Apr 30 02:44:47 PM PDT 24
Peak memory 219584 kb
Host smart-f60dcfa3-7347-47ac-8483-a990f96681ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524233916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2524233916
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.2669174489
Short name T320
Test name
Test status
Simulation time 45436629 ps
CPU time 0.95 seconds
Started Apr 30 02:44:47 PM PDT 24
Finished Apr 30 02:44:49 PM PDT 24
Peak memory 216712 kb
Host smart-f44e99da-683a-42b8-803b-c23d21dfc5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669174489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2669174489
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.493695080
Short name T547
Test name
Test status
Simulation time 107701098 ps
CPU time 1.07 seconds
Started Apr 30 02:44:48 PM PDT 24
Finished Apr 30 02:44:50 PM PDT 24
Peak memory 217024 kb
Host smart-c7fccb62-1478-42f5-a1bd-500ff2e44189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493695080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.493695080
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.4167880099
Short name T664
Test name
Test status
Simulation time 67571425 ps
CPU time 1.85 seconds
Started Apr 30 02:44:43 PM PDT 24
Finished Apr 30 02:44:45 PM PDT 24
Peak memory 218112 kb
Host smart-333380c3-7de6-4690-9ddc-f2875674477a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167880099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.4167880099
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.724332790
Short name T54
Test name
Test status
Simulation time 69546301 ps
CPU time 1.41 seconds
Started Apr 30 02:44:50 PM PDT 24
Finished Apr 30 02:44:52 PM PDT 24
Peak memory 218216 kb
Host smart-4e620b62-c624-4a46-846f-900e5b9379d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724332790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.724332790
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.2041701104
Short name T413
Test name
Test status
Simulation time 847781226 ps
CPU time 6.14 seconds
Started Apr 30 02:44:48 PM PDT 24
Finished Apr 30 02:44:55 PM PDT 24
Peak memory 217120 kb
Host smart-dd6c902c-ad97-4882-b227-1d57f93034dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041701104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2041701104
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.4233824412
Short name T752
Test name
Test status
Simulation time 123197422 ps
CPU time 1.19 seconds
Started Apr 30 02:44:48 PM PDT 24
Finished Apr 30 02:44:50 PM PDT 24
Peak memory 216688 kb
Host smart-9351c942-f382-4227-b42f-b624a0fe89df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233824412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.4233824412
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.3803141009
Short name T760
Test name
Test status
Simulation time 44750089 ps
CPU time 1.49 seconds
Started Apr 30 02:44:49 PM PDT 24
Finished Apr 30 02:44:52 PM PDT 24
Peak memory 218088 kb
Host smart-53e1a694-17b9-4075-9e41-82616d2e8dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803141009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3803141009
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1508206382
Short name T89
Test name
Test status
Simulation time 90442333 ps
CPU time 1.25 seconds
Started Apr 30 02:44:45 PM PDT 24
Finished Apr 30 02:44:48 PM PDT 24
Peak memory 216724 kb
Host smart-0d949ffa-6fe9-42e4-89a7-46be76f56755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508206382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1508206382
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.2068388087
Short name T471
Test name
Test status
Simulation time 36167708 ps
CPU time 1.13 seconds
Started Apr 30 02:44:50 PM PDT 24
Finished Apr 30 02:44:51 PM PDT 24
Peak memory 216676 kb
Host smart-bb033665-f0e1-449e-93b6-14d44d79714a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068388087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2068388087
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3616642162
Short name T263
Test name
Test status
Simulation time 48080305 ps
CPU time 1.22 seconds
Started Apr 30 02:43:31 PM PDT 24
Finished Apr 30 02:43:33 PM PDT 24
Peak memory 215520 kb
Host smart-0a850fe0-0ebd-440b-a134-922571cc33d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616642162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3616642162
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.766562058
Short name T331
Test name
Test status
Simulation time 42228574 ps
CPU time 0.99 seconds
Started Apr 30 02:43:26 PM PDT 24
Finished Apr 30 02:43:28 PM PDT 24
Peak memory 214780 kb
Host smart-5da7d656-fdeb-4b97-be61-c6ee99a1cc06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766562058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.766562058
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1519488281
Short name T577
Test name
Test status
Simulation time 36418038 ps
CPU time 0.92 seconds
Started Apr 30 02:43:29 PM PDT 24
Finished Apr 30 02:43:31 PM PDT 24
Peak memory 215988 kb
Host smart-bc31ad2f-abf6-4811-a023-fc22dd1c8673
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519488281 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1519488281
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.4241299907
Short name T108
Test name
Test status
Simulation time 61908926 ps
CPU time 1.25 seconds
Started Apr 30 02:43:26 PM PDT 24
Finished Apr 30 02:43:28 PM PDT 24
Peak memory 216728 kb
Host smart-cc244e6d-1aa3-4733-93d8-f9efaa3a08c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241299907 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.4241299907
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2639299629
Short name T586
Test name
Test status
Simulation time 34726624 ps
CPU time 1.06 seconds
Started Apr 30 02:43:26 PM PDT 24
Finished Apr 30 02:43:28 PM PDT 24
Peak memory 215356 kb
Host smart-9f457fef-1016-4e58-b2a6-2311ca12544c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639299629 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2639299629
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.737816405
Short name T85
Test name
Test status
Simulation time 55356193 ps
CPU time 1.13 seconds
Started Apr 30 02:43:27 PM PDT 24
Finished Apr 30 02:43:29 PM PDT 24
Peak memory 216896 kb
Host smart-6bcd0f76-ff21-43ec-b3f2-b4d73d0950fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737816405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.737816405
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.787778910
Short name T58
Test name
Test status
Simulation time 23208859 ps
CPU time 1.15 seconds
Started Apr 30 02:43:31 PM PDT 24
Finished Apr 30 02:43:32 PM PDT 24
Peak memory 223944 kb
Host smart-1dd3b1d9-8d57-4fc6-bf59-76c4874b004f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787778910 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.787778910
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1715816859
Short name T501
Test name
Test status
Simulation time 110190332 ps
CPU time 0.98 seconds
Started Apr 30 02:43:25 PM PDT 24
Finished Apr 30 02:43:26 PM PDT 24
Peak memory 215184 kb
Host smart-11cc692b-ccea-484f-be0d-e6bcd5cb6187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715816859 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1715816859
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2494297379
Short name T210
Test name
Test status
Simulation time 65804434 ps
CPU time 1.23 seconds
Started Apr 30 02:43:27 PM PDT 24
Finished Apr 30 02:43:29 PM PDT 24
Peak memory 215012 kb
Host smart-44ccac52-3ac9-4a81-b6fb-cb427dbc7f3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494297379 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2494297379
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/190.edn_genbits.2554478690
Short name T376
Test name
Test status
Simulation time 33694405 ps
CPU time 1.27 seconds
Started Apr 30 02:44:43 PM PDT 24
Finished Apr 30 02:44:45 PM PDT 24
Peak memory 218116 kb
Host smart-3e3d190f-f44c-45ee-8973-caa668f21f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554478690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2554478690
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.1285381295
Short name T270
Test name
Test status
Simulation time 232599037 ps
CPU time 1.2 seconds
Started Apr 30 02:44:46 PM PDT 24
Finished Apr 30 02:44:48 PM PDT 24
Peak memory 216788 kb
Host smart-43b5e11f-7cf6-4fcc-83a5-743213645332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285381295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1285381295
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.3902336785
Short name T780
Test name
Test status
Simulation time 49434752 ps
CPU time 1.59 seconds
Started Apr 30 02:44:48 PM PDT 24
Finished Apr 30 02:44:51 PM PDT 24
Peak memory 217004 kb
Host smart-ee9844e7-d1d9-4b31-8947-1b285d79fcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902336785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3902336785
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.2279840120
Short name T511
Test name
Test status
Simulation time 96271817 ps
CPU time 1.83 seconds
Started Apr 30 02:44:45 PM PDT 24
Finished Apr 30 02:44:48 PM PDT 24
Peak memory 219696 kb
Host smart-eb3423d7-ecee-4635-8372-708faaa41517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279840120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2279840120
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.629151308
Short name T560
Test name
Test status
Simulation time 296947025 ps
CPU time 1.04 seconds
Started Apr 30 02:44:48 PM PDT 24
Finished Apr 30 02:44:50 PM PDT 24
Peak memory 217052 kb
Host smart-fd368ce1-5f6b-45a7-84b3-b0753395a678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629151308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.629151308
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.2834538177
Short name T544
Test name
Test status
Simulation time 84755467 ps
CPU time 1.41 seconds
Started Apr 30 02:44:47 PM PDT 24
Finished Apr 30 02:44:49 PM PDT 24
Peak memory 218464 kb
Host smart-935ebf2b-9129-46d2-8870-55a1d08aecb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834538177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2834538177
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.3279730092
Short name T398
Test name
Test status
Simulation time 89855712 ps
CPU time 1.37 seconds
Started Apr 30 02:44:43 PM PDT 24
Finished Apr 30 02:44:45 PM PDT 24
Peak memory 218560 kb
Host smart-b6247129-2244-4127-aa03-3eb9d0ceab57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279730092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3279730092
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.1086072071
Short name T660
Test name
Test status
Simulation time 47235292 ps
CPU time 1.57 seconds
Started Apr 30 02:44:44 PM PDT 24
Finished Apr 30 02:44:46 PM PDT 24
Peak memory 217860 kb
Host smart-b168edbf-ddec-4281-963e-32166b9213ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086072071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1086072071
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert_test.1261891433
Short name T318
Test name
Test status
Simulation time 142489771 ps
CPU time 0.94 seconds
Started Apr 30 02:43:01 PM PDT 24
Finished Apr 30 02:43:03 PM PDT 24
Peak memory 206548 kb
Host smart-7ffa4490-f5c3-41e4-8246-c441784c7251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261891433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1261891433
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3942270927
Short name T183
Test name
Test status
Simulation time 27154033 ps
CPU time 0.86 seconds
Started Apr 30 02:42:57 PM PDT 24
Finished Apr 30 02:42:59 PM PDT 24
Peak memory 216092 kb
Host smart-5879868c-6ca5-45b2-87a3-31b15a729422
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942270927 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3942270927
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2478932911
Short name T118
Test name
Test status
Simulation time 57211738 ps
CPU time 1.22 seconds
Started Apr 30 02:42:57 PM PDT 24
Finished Apr 30 02:42:59 PM PDT 24
Peak memory 219492 kb
Host smart-9a6882ac-47c7-49b5-90ef-ade91671ca06
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478932911 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2478932911
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1059064350
Short name T129
Test name
Test status
Simulation time 55811630 ps
CPU time 0.91 seconds
Started Apr 30 02:42:58 PM PDT 24
Finished Apr 30 02:43:00 PM PDT 24
Peak memory 219288 kb
Host smart-7699f3a5-6dd0-4ec6-8e2a-36bcab06df43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059064350 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1059064350
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.2524249942
Short name T83
Test name
Test status
Simulation time 69369585 ps
CPU time 1.15 seconds
Started Apr 30 02:43:01 PM PDT 24
Finished Apr 30 02:43:03 PM PDT 24
Peak memory 218408 kb
Host smart-7e936a88-95be-4643-9a44-eb76432b5a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524249942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2524249942
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3561641415
Short name T381
Test name
Test status
Simulation time 26465542 ps
CPU time 1.08 seconds
Started Apr 30 02:42:54 PM PDT 24
Finished Apr 30 02:42:56 PM PDT 24
Peak memory 223876 kb
Host smart-437f3546-fb0d-4f0a-b121-25bea7fa7c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561641415 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3561641415
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2295946515
Short name T260
Test name
Test status
Simulation time 20928684 ps
CPU time 0.93 seconds
Started Apr 30 02:42:57 PM PDT 24
Finished Apr 30 02:42:59 PM PDT 24
Peak memory 206968 kb
Host smart-8c6ea0fe-391a-459d-93dc-f7c14ec860ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295946515 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2295946515
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1965914543
Short name T66
Test name
Test status
Simulation time 461167710 ps
CPU time 7.37 seconds
Started Apr 30 02:42:55 PM PDT 24
Finished Apr 30 02:43:04 PM PDT 24
Peak memory 236184 kb
Host smart-220e94fd-e3ef-4b71-b24a-6c184acab963
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965914543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1965914543
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.653877864
Short name T333
Test name
Test status
Simulation time 17191835 ps
CPU time 1.03 seconds
Started Apr 30 02:42:57 PM PDT 24
Finished Apr 30 02:42:59 PM PDT 24
Peak memory 215112 kb
Host smart-cc6a9f2e-fe7a-40be-8f55-ee64ffa1cfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653877864 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.653877864
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3673103639
Short name T735
Test name
Test status
Simulation time 168239663 ps
CPU time 3.81 seconds
Started Apr 30 02:43:00 PM PDT 24
Finished Apr 30 02:43:04 PM PDT 24
Peak memory 217076 kb
Host smart-9455c4dd-ca43-48c8-add6-ac954c9b12ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673103639 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3673103639
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1075847151
Short name T451
Test name
Test status
Simulation time 29477248326 ps
CPU time 793.15 seconds
Started Apr 30 02:42:54 PM PDT 24
Finished Apr 30 02:56:08 PM PDT 24
Peak memory 221036 kb
Host smart-22b463c8-3773-4174-a172-a50d9a467e61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075847151 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1075847151
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.4019513582
Short name T721
Test name
Test status
Simulation time 22358767 ps
CPU time 1.15 seconds
Started Apr 30 02:43:25 PM PDT 24
Finished Apr 30 02:43:27 PM PDT 24
Peak memory 215516 kb
Host smart-077202e0-c00d-4a97-b3f3-33da7c0d9a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019513582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.4019513582
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2057170347
Short name T616
Test name
Test status
Simulation time 43678973 ps
CPU time 0.81 seconds
Started Apr 30 02:43:37 PM PDT 24
Finished Apr 30 02:43:38 PM PDT 24
Peak memory 206252 kb
Host smart-d42bcc8f-bf1c-4aef-ba1f-283762f2528a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057170347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2057170347
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2290464279
Short name T603
Test name
Test status
Simulation time 114675102 ps
CPU time 1.13 seconds
Started Apr 30 02:43:44 PM PDT 24
Finished Apr 30 02:43:46 PM PDT 24
Peak memory 216708 kb
Host smart-a2582fa1-c2e4-4442-bbe0-b5f12b6aec88
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290464279 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2290464279
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2127446875
Short name T180
Test name
Test status
Simulation time 39077279 ps
CPU time 1.18 seconds
Started Apr 30 02:43:33 PM PDT 24
Finished Apr 30 02:43:35 PM PDT 24
Peak memory 219420 kb
Host smart-6178bb72-33d0-4c06-8701-5058f052798d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127446875 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2127446875
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3817795796
Short name T806
Test name
Test status
Simulation time 52069691 ps
CPU time 1.24 seconds
Started Apr 30 02:43:28 PM PDT 24
Finished Apr 30 02:43:30 PM PDT 24
Peak memory 219496 kb
Host smart-41adc50e-69ec-458a-9ba9-da88f15109a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817795796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3817795796
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.2019047776
Short name T368
Test name
Test status
Simulation time 37195094 ps
CPU time 0.84 seconds
Started Apr 30 02:43:26 PM PDT 24
Finished Apr 30 02:43:27 PM PDT 24
Peak memory 215216 kb
Host smart-b4833b4f-4fea-4a92-a06d-eead71cace4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019047776 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2019047776
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.297265208
Short name T65
Test name
Test status
Simulation time 16456265 ps
CPU time 0.95 seconds
Started Apr 30 02:43:47 PM PDT 24
Finished Apr 30 02:43:49 PM PDT 24
Peak memory 215188 kb
Host smart-da459ee4-6004-4b2f-a126-a1a0bedb4527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297265208 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.297265208
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2843575649
Short name T374
Test name
Test status
Simulation time 1204495818 ps
CPU time 2.17 seconds
Started Apr 30 02:43:25 PM PDT 24
Finished Apr 30 02:43:27 PM PDT 24
Peak memory 219348 kb
Host smart-c7b42b80-a69d-4771-96df-211843f67aa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843575649 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2843575649
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2812709690
Short name T676
Test name
Test status
Simulation time 773071083070 ps
CPU time 1668.17 seconds
Started Apr 30 02:43:29 PM PDT 24
Finished Apr 30 03:11:18 PM PDT 24
Peak memory 236624 kb
Host smart-fa85b673-2017-4c7c-a42e-25e0f05448cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812709690 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2812709690
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.408701723
Short name T425
Test name
Test status
Simulation time 170554761 ps
CPU time 1.27 seconds
Started Apr 30 02:44:57 PM PDT 24
Finished Apr 30 02:44:59 PM PDT 24
Peak memory 216908 kb
Host smart-acd5769e-6b2b-46e0-a1ef-97d2df3f6afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408701723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.408701723
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2054140626
Short name T709
Test name
Test status
Simulation time 32656431 ps
CPU time 1.37 seconds
Started Apr 30 02:44:45 PM PDT 24
Finished Apr 30 02:44:47 PM PDT 24
Peak memory 219432 kb
Host smart-98edfa5c-f0a7-4581-afa4-be24a8890baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054140626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2054140626
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.4169031072
Short name T701
Test name
Test status
Simulation time 68980268 ps
CPU time 1.13 seconds
Started Apr 30 02:44:49 PM PDT 24
Finished Apr 30 02:44:51 PM PDT 24
Peak memory 217048 kb
Host smart-fcd0bccb-c746-4a82-812e-5dcccb902c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169031072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.4169031072
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1903222897
Short name T344
Test name
Test status
Simulation time 41282940 ps
CPU time 1.91 seconds
Started Apr 30 02:44:54 PM PDT 24
Finished Apr 30 02:44:57 PM PDT 24
Peak memory 218012 kb
Host smart-81c5a08a-5937-45ed-bf01-2558736639c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903222897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1903222897
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3714355164
Short name T509
Test name
Test status
Simulation time 44067339 ps
CPU time 1.7 seconds
Started Apr 30 02:44:46 PM PDT 24
Finished Apr 30 02:44:49 PM PDT 24
Peak memory 217908 kb
Host smart-aac8437d-6346-4240-b7b6-84ecd2e67d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714355164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3714355164
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3277488302
Short name T371
Test name
Test status
Simulation time 62284779 ps
CPU time 1.36 seconds
Started Apr 30 02:44:51 PM PDT 24
Finished Apr 30 02:44:53 PM PDT 24
Peak memory 219312 kb
Host smart-b974dbef-0c16-42f2-8a7a-0dd21e372acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277488302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3277488302
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.870694903
Short name T363
Test name
Test status
Simulation time 43277928 ps
CPU time 1.85 seconds
Started Apr 30 02:44:53 PM PDT 24
Finished Apr 30 02:44:56 PM PDT 24
Peak memory 217964 kb
Host smart-3fb41527-f73e-4027-9db3-c59cd6885cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870694903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.870694903
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.4258344198
Short name T12
Test name
Test status
Simulation time 44979725 ps
CPU time 1.83 seconds
Started Apr 30 02:44:53 PM PDT 24
Finished Apr 30 02:44:56 PM PDT 24
Peak memory 219404 kb
Host smart-c3839743-13e6-42d0-b03a-54308cb3c767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258344198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.4258344198
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.761519219
Short name T91
Test name
Test status
Simulation time 28386022 ps
CPU time 1.19 seconds
Started Apr 30 02:44:56 PM PDT 24
Finished Apr 30 02:44:58 PM PDT 24
Peak memory 218116 kb
Host smart-20612a66-37e7-4673-baf7-2bab079258de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761519219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.761519219
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.698267772
Short name T510
Test name
Test status
Simulation time 52224752 ps
CPU time 1.26 seconds
Started Apr 30 02:44:58 PM PDT 24
Finished Apr 30 02:45:00 PM PDT 24
Peak memory 219536 kb
Host smart-002cc6cd-fc21-4d63-9c9c-9de22c5a980b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698267772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.698267772
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.452452779
Short name T148
Test name
Test status
Simulation time 28070701 ps
CPU time 1.25 seconds
Started Apr 30 02:43:37 PM PDT 24
Finished Apr 30 02:43:39 PM PDT 24
Peak memory 215596 kb
Host smart-217c5671-3785-4d08-ab76-6bd3e1dfb40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452452779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.452452779
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3267758762
Short name T783
Test name
Test status
Simulation time 19967038 ps
CPU time 0.99 seconds
Started Apr 30 02:43:43 PM PDT 24
Finished Apr 30 02:43:45 PM PDT 24
Peak memory 206492 kb
Host smart-61ee9ba3-4678-4dd5-a8d7-2fc8330a25e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267758762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3267758762
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.4012603704
Short name T589
Test name
Test status
Simulation time 33949601 ps
CPU time 1.14 seconds
Started Apr 30 02:43:30 PM PDT 24
Finished Apr 30 02:43:31 PM PDT 24
Peak memory 216484 kb
Host smart-660235ee-a9a8-4aeb-a5d7-ba00d7c24980
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012603704 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.4012603704
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.1253905961
Short name T144
Test name
Test status
Simulation time 20522624 ps
CPU time 0.99 seconds
Started Apr 30 02:43:30 PM PDT 24
Finished Apr 30 02:43:32 PM PDT 24
Peak memory 218204 kb
Host smart-4b70a959-5ef7-4327-94f8-ff5daf2287eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253905961 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1253905961
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.814433101
Short name T601
Test name
Test status
Simulation time 18824879 ps
CPU time 1.08 seconds
Started Apr 30 02:43:34 PM PDT 24
Finished Apr 30 02:43:35 PM PDT 24
Peak memory 216996 kb
Host smart-7d08e5e8-13c4-4136-8330-c678c7464d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814433101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.814433101
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2034665931
Short name T4
Test name
Test status
Simulation time 28537759 ps
CPU time 0.93 seconds
Started Apr 30 02:43:34 PM PDT 24
Finished Apr 30 02:43:36 PM PDT 24
Peak memory 215492 kb
Host smart-c0d135b4-76bd-4f45-8699-50bd25b85a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034665931 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2034665931
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.4205316973
Short name T526
Test name
Test status
Simulation time 55569740 ps
CPU time 0.97 seconds
Started Apr 30 02:43:33 PM PDT 24
Finished Apr 30 02:43:34 PM PDT 24
Peak memory 215120 kb
Host smart-5487af76-367e-4a52-8d36-6d59b326ee2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205316973 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.4205316973
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.620242048
Short name T801
Test name
Test status
Simulation time 112485058 ps
CPU time 2.66 seconds
Started Apr 30 02:43:35 PM PDT 24
Finished Apr 30 02:43:39 PM PDT 24
Peak memory 215072 kb
Host smart-c7af6d99-01f4-43b5-bebe-d4ed48b37b5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620242048 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.620242048
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.502941460
Short name T424
Test name
Test status
Simulation time 843378259810 ps
CPU time 2111.68 seconds
Started Apr 30 02:43:35 PM PDT 24
Finished Apr 30 03:18:47 PM PDT 24
Peak memory 229084 kb
Host smart-4b45e045-da6b-4692-84d9-77a7fa5eaa02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502941460 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.502941460
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.591431611
Short name T769
Test name
Test status
Simulation time 51773176 ps
CPU time 1.31 seconds
Started Apr 30 02:44:54 PM PDT 24
Finished Apr 30 02:44:57 PM PDT 24
Peak memory 217920 kb
Host smart-d1ae02fa-d8e2-4118-b7a3-d925a13fd4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591431611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.591431611
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.637097560
Short name T457
Test name
Test status
Simulation time 104514607 ps
CPU time 1.28 seconds
Started Apr 30 02:44:44 PM PDT 24
Finished Apr 30 02:44:47 PM PDT 24
Peak memory 218252 kb
Host smart-0995d878-26c9-4b38-9cb6-f3d74bcce267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637097560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.637097560
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2464639475
Short name T776
Test name
Test status
Simulation time 68677148 ps
CPU time 2.53 seconds
Started Apr 30 02:44:44 PM PDT 24
Finished Apr 30 02:44:48 PM PDT 24
Peak memory 219792 kb
Host smart-7367499e-faa0-4860-ae6a-7db6f6defadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464639475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2464639475
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3638703442
Short name T697
Test name
Test status
Simulation time 165738387 ps
CPU time 2.63 seconds
Started Apr 30 02:45:00 PM PDT 24
Finished Apr 30 02:45:03 PM PDT 24
Peak memory 219108 kb
Host smart-4feab187-88e0-4406-949b-37b03d1b422f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638703442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3638703442
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1704322891
Short name T388
Test name
Test status
Simulation time 57073723 ps
CPU time 1.35 seconds
Started Apr 30 02:44:45 PM PDT 24
Finished Apr 30 02:44:47 PM PDT 24
Peak memory 217936 kb
Host smart-56831a69-1435-4dea-80c4-1a8c0af27a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704322891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1704322891
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.475856910
Short name T453
Test name
Test status
Simulation time 101927324 ps
CPU time 1.49 seconds
Started Apr 30 02:44:53 PM PDT 24
Finished Apr 30 02:44:55 PM PDT 24
Peak memory 218428 kb
Host smart-3ddc157e-369d-4729-8e52-83751c05d231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475856910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.475856910
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.517893865
Short name T395
Test name
Test status
Simulation time 41238490 ps
CPU time 1.1 seconds
Started Apr 30 02:44:54 PM PDT 24
Finished Apr 30 02:44:56 PM PDT 24
Peak memory 219428 kb
Host smart-c8d3ceb5-e41f-47ef-8d34-e27ab735f440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517893865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.517893865
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1089736925
Short name T328
Test name
Test status
Simulation time 39780248 ps
CPU time 1.32 seconds
Started Apr 30 02:44:48 PM PDT 24
Finished Apr 30 02:44:50 PM PDT 24
Peak memory 218200 kb
Host smart-28b4b07b-0ac0-4702-8187-3d3436e9b089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089736925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1089736925
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1806181132
Short name T408
Test name
Test status
Simulation time 64245273 ps
CPU time 1.24 seconds
Started Apr 30 02:44:52 PM PDT 24
Finished Apr 30 02:44:54 PM PDT 24
Peak memory 218740 kb
Host smart-c6a8120b-5322-4f05-b62e-a8ca1abc2aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806181132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1806181132
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3661331752
Short name T648
Test name
Test status
Simulation time 57615071 ps
CPU time 1.2 seconds
Started Apr 30 02:43:34 PM PDT 24
Finished Apr 30 02:43:36 PM PDT 24
Peak memory 215568 kb
Host smart-ef32282f-cd81-49e6-9d42-6f20be9a5f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661331752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3661331752
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.415143134
Short name T568
Test name
Test status
Simulation time 91103162 ps
CPU time 2.08 seconds
Started Apr 30 02:43:41 PM PDT 24
Finished Apr 30 02:43:44 PM PDT 24
Peak memory 206652 kb
Host smart-7f4a5e7a-978c-4d25-8756-688b591d68f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415143134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.415143134
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3601957176
Short name T772
Test name
Test status
Simulation time 11344780 ps
CPU time 0.88 seconds
Started Apr 30 02:43:35 PM PDT 24
Finished Apr 30 02:43:37 PM PDT 24
Peak memory 216156 kb
Host smart-30fe2707-a0cb-450e-ba1e-74dbf623aafe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601957176 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3601957176
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2893003876
Short name T390
Test name
Test status
Simulation time 45779217 ps
CPU time 1.34 seconds
Started Apr 30 02:43:33 PM PDT 24
Finished Apr 30 02:43:35 PM PDT 24
Peak memory 218196 kb
Host smart-49942650-3496-4e1b-bbb4-8630fbf518a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893003876 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2893003876
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.4042493048
Short name T132
Test name
Test status
Simulation time 33764485 ps
CPU time 0.99 seconds
Started Apr 30 02:43:42 PM PDT 24
Finished Apr 30 02:43:43 PM PDT 24
Peak memory 223888 kb
Host smart-5a4ad691-79dd-4e91-a9e8-812fa1b1d249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042493048 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.4042493048
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3999564354
Short name T610
Test name
Test status
Simulation time 36584105 ps
CPU time 1.56 seconds
Started Apr 30 02:43:38 PM PDT 24
Finished Apr 30 02:43:40 PM PDT 24
Peak memory 216768 kb
Host smart-67b50b74-22a1-4fa4-a727-7e7b2f2fcc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999564354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3999564354
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2200812101
Short name T335
Test name
Test status
Simulation time 22797818 ps
CPU time 1.14 seconds
Started Apr 30 02:43:33 PM PDT 24
Finished Apr 30 02:43:35 PM PDT 24
Peak memory 215356 kb
Host smart-504cb634-6340-441c-bc0c-7c147989f5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200812101 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2200812101
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.961254179
Short name T353
Test name
Test status
Simulation time 25115860 ps
CPU time 0.91 seconds
Started Apr 30 02:43:34 PM PDT 24
Finished Apr 30 02:43:35 PM PDT 24
Peak memory 215076 kb
Host smart-431bf033-5969-46cd-aeb1-56676dffc231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961254179 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.961254179
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2750625342
Short name T427
Test name
Test status
Simulation time 299823358 ps
CPU time 5.26 seconds
Started Apr 30 02:43:37 PM PDT 24
Finished Apr 30 02:43:43 PM PDT 24
Peak memory 219796 kb
Host smart-6af2d55e-e96a-4814-a33e-bdf5e75f4113
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750625342 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2750625342
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.976442168
Short name T282
Test name
Test status
Simulation time 85901256849 ps
CPU time 1044.02 seconds
Started Apr 30 02:43:32 PM PDT 24
Finished Apr 30 03:00:56 PM PDT 24
Peak memory 221284 kb
Host smart-04fe2cff-32f8-4a57-88f4-6af523081aea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976442168 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.976442168
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2969301611
Short name T805
Test name
Test status
Simulation time 56862753 ps
CPU time 1.29 seconds
Started Apr 30 02:44:46 PM PDT 24
Finished Apr 30 02:44:48 PM PDT 24
Peak memory 216844 kb
Host smart-fd6e7dcb-d0c2-4453-ad46-4bd456ceb595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969301611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2969301611
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1771042867
Short name T789
Test name
Test status
Simulation time 57773410 ps
CPU time 1 seconds
Started Apr 30 02:44:53 PM PDT 24
Finished Apr 30 02:44:55 PM PDT 24
Peak memory 216848 kb
Host smart-a7440792-304b-4e4c-ac0d-63d05d125811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771042867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1771042867
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1324506517
Short name T702
Test name
Test status
Simulation time 54922935 ps
CPU time 1.32 seconds
Started Apr 30 02:44:45 PM PDT 24
Finished Apr 30 02:44:48 PM PDT 24
Peak memory 218532 kb
Host smart-ade906e5-b2fd-4e98-bbe0-a8d1b0b87fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324506517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1324506517
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2085360054
Short name T690
Test name
Test status
Simulation time 61777040 ps
CPU time 1.23 seconds
Started Apr 30 02:44:58 PM PDT 24
Finished Apr 30 02:45:00 PM PDT 24
Peak memory 216884 kb
Host smart-1f5ad69e-793a-4ff2-bb2b-7a0bdf286114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085360054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2085360054
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2965322962
Short name T633
Test name
Test status
Simulation time 87170233 ps
CPU time 1.08 seconds
Started Apr 30 02:44:46 PM PDT 24
Finished Apr 30 02:44:49 PM PDT 24
Peak memory 216748 kb
Host smart-f51bf163-d559-46a5-83b5-aaec416e9198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965322962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2965322962
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1989592781
Short name T778
Test name
Test status
Simulation time 35488849 ps
CPU time 1.33 seconds
Started Apr 30 02:44:56 PM PDT 24
Finished Apr 30 02:44:58 PM PDT 24
Peak memory 217996 kb
Host smart-bf4ea750-d159-4022-b586-c98b76f2e0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989592781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1989592781
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1884238690
Short name T437
Test name
Test status
Simulation time 86134612 ps
CPU time 1.11 seconds
Started Apr 30 02:44:56 PM PDT 24
Finished Apr 30 02:44:57 PM PDT 24
Peak memory 216692 kb
Host smart-3d1973e5-0bad-4fba-b626-9295b6f98fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884238690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1884238690
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2910564541
Short name T583
Test name
Test status
Simulation time 40348263 ps
CPU time 1.54 seconds
Started Apr 30 02:44:50 PM PDT 24
Finished Apr 30 02:44:52 PM PDT 24
Peak memory 216784 kb
Host smart-5a303359-572c-496c-9876-bc564796ba65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910564541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2910564541
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3594826301
Short name T746
Test name
Test status
Simulation time 691364473 ps
CPU time 4.39 seconds
Started Apr 30 02:44:51 PM PDT 24
Finished Apr 30 02:44:56 PM PDT 24
Peak memory 219516 kb
Host smart-631b1bb0-5ea1-468d-b5e0-47aee121a29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594826301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3594826301
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.407623469
Short name T753
Test name
Test status
Simulation time 90926850 ps
CPU time 1.22 seconds
Started Apr 30 02:43:41 PM PDT 24
Finished Apr 30 02:43:43 PM PDT 24
Peak memory 215560 kb
Host smart-38f7dbaf-f93e-4320-a222-19c3275460d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407623469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.407623469
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1015053564
Short name T341
Test name
Test status
Simulation time 18234184 ps
CPU time 0.83 seconds
Started Apr 30 02:43:31 PM PDT 24
Finished Apr 30 02:43:33 PM PDT 24
Peak memory 206820 kb
Host smart-ebb56013-98c8-40b2-ab06-da07f796a35c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015053564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1015053564
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.786926270
Short name T686
Test name
Test status
Simulation time 22423371 ps
CPU time 0.8 seconds
Started Apr 30 02:43:32 PM PDT 24
Finished Apr 30 02:43:33 PM PDT 24
Peak memory 216020 kb
Host smart-0d365746-480a-4401-8135-110bd2b0c9be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786926270 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.786926270
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.960866711
Short name T124
Test name
Test status
Simulation time 25500517 ps
CPU time 1.22 seconds
Started Apr 30 02:43:31 PM PDT 24
Finished Apr 30 02:43:33 PM PDT 24
Peak memory 220352 kb
Host smart-a3a1364c-49e7-422f-a63e-abc9f3c68a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960866711 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.960866711
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3230039624
Short name T582
Test name
Test status
Simulation time 45738402 ps
CPU time 1.22 seconds
Started Apr 30 02:43:44 PM PDT 24
Finished Apr 30 02:43:46 PM PDT 24
Peak memory 217028 kb
Host smart-9ef03e51-2eec-4632-9f6a-9b5134ddcaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230039624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3230039624
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3150638938
Short name T505
Test name
Test status
Simulation time 30211093 ps
CPU time 0.89 seconds
Started Apr 30 02:43:36 PM PDT 24
Finished Apr 30 02:43:37 PM PDT 24
Peak memory 215508 kb
Host smart-80072e1f-1213-4a91-92e9-c9afcfdf0757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150638938 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3150638938
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3758177345
Short name T349
Test name
Test status
Simulation time 16020961 ps
CPU time 0.97 seconds
Started Apr 30 02:43:34 PM PDT 24
Finished Apr 30 02:43:36 PM PDT 24
Peak memory 215164 kb
Host smart-b64d9f0f-91a5-44c9-a8a2-bfa0036c7c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758177345 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3758177345
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3987409381
Short name T628
Test name
Test status
Simulation time 1985688085 ps
CPU time 4.46 seconds
Started Apr 30 02:43:37 PM PDT 24
Finished Apr 30 02:43:42 PM PDT 24
Peak memory 216880 kb
Host smart-a7cecc88-4844-4d29-a04b-dd5cf55d3b49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987409381 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3987409381
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2030358430
Short name T506
Test name
Test status
Simulation time 88261305808 ps
CPU time 832.61 seconds
Started Apr 30 02:43:36 PM PDT 24
Finished Apr 30 02:57:29 PM PDT 24
Peak memory 221572 kb
Host smart-54c54c97-4b70-4bb4-a3c1-17258b103662
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030358430 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2030358430
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2535008958
Short name T731
Test name
Test status
Simulation time 36906028 ps
CPU time 1.28 seconds
Started Apr 30 02:44:57 PM PDT 24
Finished Apr 30 02:44:59 PM PDT 24
Peak memory 217920 kb
Host smart-27f4f0ad-101d-418f-93c7-16f030ec7481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535008958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2535008958
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3005995331
Short name T763
Test name
Test status
Simulation time 171563045 ps
CPU time 2.3 seconds
Started Apr 30 02:44:54 PM PDT 24
Finished Apr 30 02:44:57 PM PDT 24
Peak memory 219724 kb
Host smart-fbe322c8-fcd8-4aef-9a11-f2fdf31962d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005995331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3005995331
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3685622915
Short name T540
Test name
Test status
Simulation time 101806418 ps
CPU time 1.04 seconds
Started Apr 30 02:44:45 PM PDT 24
Finished Apr 30 02:44:47 PM PDT 24
Peak memory 216852 kb
Host smart-9672d6dd-ee72-4b8b-9964-c12dfbbd8aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685622915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3685622915
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.720771901
Short name T402
Test name
Test status
Simulation time 28417131 ps
CPU time 1.24 seconds
Started Apr 30 02:44:57 PM PDT 24
Finished Apr 30 02:44:59 PM PDT 24
Peak memory 216732 kb
Host smart-fc356c7d-1f4c-477e-bfb7-463770823dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720771901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.720771901
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3343483900
Short name T615
Test name
Test status
Simulation time 39433424 ps
CPU time 1.26 seconds
Started Apr 30 02:44:54 PM PDT 24
Finished Apr 30 02:44:57 PM PDT 24
Peak memory 216980 kb
Host smart-c8020b50-7b31-4d7d-b941-9951af303886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343483900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3343483900
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.821194738
Short name T768
Test name
Test status
Simulation time 60712985 ps
CPU time 1.27 seconds
Started Apr 30 02:44:51 PM PDT 24
Finished Apr 30 02:44:53 PM PDT 24
Peak memory 218056 kb
Host smart-43c5d845-12e4-4e94-ae18-340313240b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821194738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.821194738
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.814775574
Short name T281
Test name
Test status
Simulation time 32062322 ps
CPU time 1.29 seconds
Started Apr 30 02:44:58 PM PDT 24
Finished Apr 30 02:45:00 PM PDT 24
Peak memory 218092 kb
Host smart-d50b8893-b6d2-4444-9e94-27a9c85e08b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814775574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.814775574
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2761526476
Short name T688
Test name
Test status
Simulation time 35910935 ps
CPU time 1.41 seconds
Started Apr 30 02:45:00 PM PDT 24
Finished Apr 30 02:45:02 PM PDT 24
Peak memory 218224 kb
Host smart-fa4c02cb-fc65-4d18-b39e-e77fb77c44ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761526476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2761526476
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1733794859
Short name T493
Test name
Test status
Simulation time 2199347299 ps
CPU time 73.2 seconds
Started Apr 30 02:45:04 PM PDT 24
Finished Apr 30 02:46:17 PM PDT 24
Peak memory 218620 kb
Host smart-25bc2541-1bef-494b-8f79-b15b669c7305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733794859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1733794859
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.4222821966
Short name T346
Test name
Test status
Simulation time 76539501 ps
CPU time 1.43 seconds
Started Apr 30 02:44:59 PM PDT 24
Finished Apr 30 02:45:02 PM PDT 24
Peak memory 218280 kb
Host smart-0453c8d3-f278-4f61-9689-6c0596fa3309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222821966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.4222821966
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.871003623
Short name T147
Test name
Test status
Simulation time 52232995 ps
CPU time 1.19 seconds
Started Apr 30 02:43:47 PM PDT 24
Finished Apr 30 02:43:49 PM PDT 24
Peak memory 215556 kb
Host smart-65523aba-6c92-4347-8a1d-12d2f102832b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871003623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.871003623
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.916036960
Short name T508
Test name
Test status
Simulation time 42154991 ps
CPU time 1.31 seconds
Started Apr 30 02:43:33 PM PDT 24
Finished Apr 30 02:43:35 PM PDT 24
Peak memory 206744 kb
Host smart-96cac82c-ba71-441c-8624-78e10ba5392d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916036960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.916036960
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.357740259
Short name T499
Test name
Test status
Simulation time 11448188 ps
CPU time 0.84 seconds
Started Apr 30 02:43:36 PM PDT 24
Finished Apr 30 02:43:38 PM PDT 24
Peak memory 215248 kb
Host smart-604e7ede-cb00-466d-bdbe-9853a20c8674
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357740259 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.357740259
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.54301046
Short name T671
Test name
Test status
Simulation time 86461905 ps
CPU time 1.09 seconds
Started Apr 30 02:43:35 PM PDT 24
Finished Apr 30 02:43:37 PM PDT 24
Peak memory 216584 kb
Host smart-06624217-d763-4e17-952f-f2bb6039dde4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54301046 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_dis
able_auto_req_mode.54301046
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.568179265
Short name T553
Test name
Test status
Simulation time 78907727 ps
CPU time 0.9 seconds
Started Apr 30 02:43:33 PM PDT 24
Finished Apr 30 02:43:35 PM PDT 24
Peak memory 218252 kb
Host smart-ec4ba738-cc7b-49a9-bb34-a43acb00f380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568179265 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.568179265
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3374225385
Short name T828
Test name
Test status
Simulation time 123614623 ps
CPU time 2.74 seconds
Started Apr 30 02:43:32 PM PDT 24
Finished Apr 30 02:43:35 PM PDT 24
Peak memory 219692 kb
Host smart-1ac49f6f-7a21-4e43-97dc-50f9efef1d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374225385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3374225385
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_smoke.3901305396
Short name T659
Test name
Test status
Simulation time 15488039 ps
CPU time 0.96 seconds
Started Apr 30 02:43:34 PM PDT 24
Finished Apr 30 02:43:36 PM PDT 24
Peak memory 215184 kb
Host smart-fa90c082-bb62-440a-8794-7f70bfbdaecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901305396 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3901305396
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.237752939
Short name T385
Test name
Test status
Simulation time 911063379 ps
CPU time 3.63 seconds
Started Apr 30 02:43:29 PM PDT 24
Finished Apr 30 02:43:33 PM PDT 24
Peak memory 216632 kb
Host smart-aecf93be-96ae-4871-a17f-cc27299572ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237752939 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.237752939
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.242312281
Short name T573
Test name
Test status
Simulation time 120848943295 ps
CPU time 771.84 seconds
Started Apr 30 02:43:35 PM PDT 24
Finished Apr 30 02:56:27 PM PDT 24
Peak memory 222136 kb
Host smart-ba06bc78-b014-44ed-8e23-0a1607f4a338
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242312281 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.242312281
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3932182011
Short name T293
Test name
Test status
Simulation time 43275234 ps
CPU time 1.44 seconds
Started Apr 30 02:45:01 PM PDT 24
Finished Apr 30 02:45:03 PM PDT 24
Peak memory 215184 kb
Host smart-a2398342-1d3c-44f5-9348-af6b07f5c21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932182011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3932182011
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.4139508062
Short name T818
Test name
Test status
Simulation time 50517896 ps
CPU time 1.45 seconds
Started Apr 30 02:44:57 PM PDT 24
Finished Apr 30 02:44:58 PM PDT 24
Peak memory 218372 kb
Host smart-aaeda631-9d8f-4584-81db-28473de76053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139508062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.4139508062
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.231835085
Short name T815
Test name
Test status
Simulation time 267123391 ps
CPU time 3.43 seconds
Started Apr 30 02:44:57 PM PDT 24
Finished Apr 30 02:45:02 PM PDT 24
Peak memory 217340 kb
Host smart-0417cab0-61c0-4de3-8d4a-d9604b399fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231835085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.231835085
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1985523985
Short name T781
Test name
Test status
Simulation time 53789581 ps
CPU time 1.39 seconds
Started Apr 30 02:44:53 PM PDT 24
Finished Apr 30 02:44:56 PM PDT 24
Peak memory 218144 kb
Host smart-810a4285-48d7-4fc6-a59d-7074ef107499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985523985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1985523985
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1377482421
Short name T291
Test name
Test status
Simulation time 328029807 ps
CPU time 4.48 seconds
Started Apr 30 02:44:56 PM PDT 24
Finished Apr 30 02:45:01 PM PDT 24
Peak memory 219688 kb
Host smart-26d22f9d-8f16-47b1-9149-85d0316a2ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377482421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1377482421
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1308208611
Short name T502
Test name
Test status
Simulation time 59238733 ps
CPU time 1.16 seconds
Started Apr 30 02:44:59 PM PDT 24
Finished Apr 30 02:45:00 PM PDT 24
Peak memory 216896 kb
Host smart-76ebe1d7-ebb6-47a7-970f-cdd1fbac4bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308208611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1308208611
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.4100185685
Short name T535
Test name
Test status
Simulation time 72743843 ps
CPU time 0.95 seconds
Started Apr 30 02:44:55 PM PDT 24
Finished Apr 30 02:44:57 PM PDT 24
Peak memory 216912 kb
Host smart-fe1da8fe-b403-4a08-9e93-86dd23ecd6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100185685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.4100185685
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1957230661
Short name T70
Test name
Test status
Simulation time 66908475 ps
CPU time 1.16 seconds
Started Apr 30 02:45:02 PM PDT 24
Finished Apr 30 02:45:04 PM PDT 24
Peak memory 218492 kb
Host smart-38b2e796-44c4-42f2-8361-0bc60ea4a37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957230661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1957230661
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.406994985
Short name T445
Test name
Test status
Simulation time 70278768 ps
CPU time 2.46 seconds
Started Apr 30 02:45:02 PM PDT 24
Finished Apr 30 02:45:05 PM PDT 24
Peak memory 218692 kb
Host smart-0758b13b-7962-4e16-9d07-e3a701f18e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406994985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.406994985
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2351918
Short name T703
Test name
Test status
Simulation time 40287620 ps
CPU time 1.17 seconds
Started Apr 30 02:43:29 PM PDT 24
Finished Apr 30 02:43:31 PM PDT 24
Peak memory 215512 kb
Host smart-d941ac43-706e-491e-bf72-39d6fd7dfc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2351918
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.4033972601
Short name T319
Test name
Test status
Simulation time 17314671 ps
CPU time 0.93 seconds
Started Apr 30 02:43:44 PM PDT 24
Finished Apr 30 02:43:45 PM PDT 24
Peak memory 206484 kb
Host smart-bdff3e9c-b0f7-4666-bb34-88f5f33011cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033972601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.4033972601
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2519563122
Short name T197
Test name
Test status
Simulation time 14288825 ps
CPU time 0.93 seconds
Started Apr 30 02:43:41 PM PDT 24
Finished Apr 30 02:43:42 PM PDT 24
Peak memory 216200 kb
Host smart-888907a6-29ba-47c7-b114-56dc46b539f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519563122 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2519563122
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.3231023938
Short name T139
Test name
Test status
Simulation time 35673963 ps
CPU time 0.87 seconds
Started Apr 30 02:43:35 PM PDT 24
Finished Apr 30 02:43:37 PM PDT 24
Peak memory 218208 kb
Host smart-636438fd-0965-4392-a592-fe85674d39dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231023938 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3231023938
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3678477533
Short name T543
Test name
Test status
Simulation time 157758953 ps
CPU time 1.19 seconds
Started Apr 30 02:43:32 PM PDT 24
Finished Apr 30 02:43:34 PM PDT 24
Peak memory 216848 kb
Host smart-531e98db-8079-43b5-bcef-2de9920b592d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678477533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3678477533
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2011345621
Short name T401
Test name
Test status
Simulation time 41412594 ps
CPU time 0.83 seconds
Started Apr 30 02:43:40 PM PDT 24
Finished Apr 30 02:43:42 PM PDT 24
Peak memory 215452 kb
Host smart-1105e67d-2557-46d3-8bb1-e7bf775819bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011345621 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2011345621
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1039354375
Short name T542
Test name
Test status
Simulation time 42704645 ps
CPU time 0.89 seconds
Started Apr 30 02:43:42 PM PDT 24
Finished Apr 30 02:43:44 PM PDT 24
Peak memory 215176 kb
Host smart-5d644ed1-d759-48e7-922b-fa72c1807d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039354375 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1039354375
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2406254286
Short name T817
Test name
Test status
Simulation time 853883595 ps
CPU time 4.69 seconds
Started Apr 30 02:43:40 PM PDT 24
Finished Apr 30 02:43:45 PM PDT 24
Peak memory 215120 kb
Host smart-ffb5adf1-a892-4753-a410-988f9bc6f2e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406254286 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2406254286
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.103619614
Short name T739
Test name
Test status
Simulation time 61491395325 ps
CPU time 654.41 seconds
Started Apr 30 02:43:29 PM PDT 24
Finished Apr 30 02:54:25 PM PDT 24
Peak memory 217956 kb
Host smart-43e825ba-d3d4-44a7-8ebd-617a29c37991
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103619614 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.103619614
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.115605041
Short name T669
Test name
Test status
Simulation time 30177134 ps
CPU time 1.31 seconds
Started Apr 30 02:44:58 PM PDT 24
Finished Apr 30 02:45:00 PM PDT 24
Peak memory 219304 kb
Host smart-5465b59d-e8b6-489e-acd2-fb5f78321996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115605041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.115605041
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1583716284
Short name T472
Test name
Test status
Simulation time 39220827 ps
CPU time 1.34 seconds
Started Apr 30 02:44:53 PM PDT 24
Finished Apr 30 02:44:55 PM PDT 24
Peak memory 218168 kb
Host smart-563c0a2c-b614-429c-8f72-6c00cf9baea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583716284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1583716284
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.281248475
Short name T434
Test name
Test status
Simulation time 54331381 ps
CPU time 1.26 seconds
Started Apr 30 02:44:58 PM PDT 24
Finished Apr 30 02:45:00 PM PDT 24
Peak memory 218252 kb
Host smart-6c11bdc3-cbce-49e1-8637-d282adc3fa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281248475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.281248475
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.836502223
Short name T73
Test name
Test status
Simulation time 75874538 ps
CPU time 1.31 seconds
Started Apr 30 02:45:00 PM PDT 24
Finished Apr 30 02:45:02 PM PDT 24
Peak memory 218316 kb
Host smart-ae775283-4c86-446e-9290-bb145f291e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836502223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.836502223
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2085465320
Short name T707
Test name
Test status
Simulation time 51687858 ps
CPU time 1.7 seconds
Started Apr 30 02:44:52 PM PDT 24
Finished Apr 30 02:44:55 PM PDT 24
Peak memory 218228 kb
Host smart-cbbfbd54-9259-4465-b61e-1443e77142ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085465320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2085465320
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2915371487
Short name T504
Test name
Test status
Simulation time 57582214 ps
CPU time 0.99 seconds
Started Apr 30 02:44:58 PM PDT 24
Finished Apr 30 02:45:00 PM PDT 24
Peak memory 216944 kb
Host smart-f2d856e1-d8b3-43ed-ba22-8c99fb00d555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915371487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2915371487
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3610696951
Short name T287
Test name
Test status
Simulation time 123424512 ps
CPU time 0.99 seconds
Started Apr 30 02:45:01 PM PDT 24
Finished Apr 30 02:45:02 PM PDT 24
Peak memory 216804 kb
Host smart-75b28439-1b51-4f5b-8450-7eac2cca1f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610696951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3610696951
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.529938452
Short name T484
Test name
Test status
Simulation time 88135322 ps
CPU time 1.48 seconds
Started Apr 30 02:45:02 PM PDT 24
Finished Apr 30 02:45:04 PM PDT 24
Peak memory 216996 kb
Host smart-620311e2-8de4-482c-8da0-a7c3bd794ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529938452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.529938452
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3359418980
Short name T525
Test name
Test status
Simulation time 29247234 ps
CPU time 1.23 seconds
Started Apr 30 02:44:54 PM PDT 24
Finished Apr 30 02:44:56 PM PDT 24
Peak memory 216972 kb
Host smart-399d1048-1bd5-4667-8038-34df7cd7b6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359418980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3359418980
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1110318150
Short name T513
Test name
Test status
Simulation time 53905680 ps
CPU time 1.22 seconds
Started Apr 30 02:44:59 PM PDT 24
Finished Apr 30 02:45:01 PM PDT 24
Peak memory 216916 kb
Host smart-faab2c21-661e-4109-bb25-c63b5523eebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110318150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1110318150
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert_test.4047247549
Short name T394
Test name
Test status
Simulation time 32185549 ps
CPU time 1.15 seconds
Started Apr 30 02:43:38 PM PDT 24
Finished Apr 30 02:43:40 PM PDT 24
Peak memory 206628 kb
Host smart-56891d11-7ef3-4d86-bb5c-a832cebe42e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047247549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.4047247549
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.264405945
Short name T650
Test name
Test status
Simulation time 81245805 ps
CPU time 0.84 seconds
Started Apr 30 02:43:54 PM PDT 24
Finished Apr 30 02:43:56 PM PDT 24
Peak memory 216076 kb
Host smart-7b1ff331-bf04-415f-b780-6974b1b58b3e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264405945 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.264405945
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1154505025
Short name T125
Test name
Test status
Simulation time 95200421 ps
CPU time 1.09 seconds
Started Apr 30 02:43:36 PM PDT 24
Finished Apr 30 02:43:38 PM PDT 24
Peak memory 216680 kb
Host smart-7845d07a-be55-47f2-a678-d46a19173ca1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154505025 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1154505025
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2053032725
Short name T412
Test name
Test status
Simulation time 22243626 ps
CPU time 0.92 seconds
Started Apr 30 02:43:42 PM PDT 24
Finished Apr 30 02:43:43 PM PDT 24
Peak memory 217892 kb
Host smart-f17f6d34-74d9-40ce-bc49-1cf7d4c9d094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053032725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2053032725
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3285390858
Short name T244
Test name
Test status
Simulation time 65556680 ps
CPU time 1.31 seconds
Started Apr 30 02:43:34 PM PDT 24
Finished Apr 30 02:43:36 PM PDT 24
Peak memory 216792 kb
Host smart-f93d6c6c-52ee-47fa-975f-d15cdbbf6900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285390858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3285390858
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3219720253
Short name T16
Test name
Test status
Simulation time 42812901 ps
CPU time 0.98 seconds
Started Apr 30 02:43:33 PM PDT 24
Finished Apr 30 02:43:35 PM PDT 24
Peak memory 223852 kb
Host smart-6e8bc5d4-eddd-4336-9dc0-d5e0851c3542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219720253 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3219720253
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3374480912
Short name T620
Test name
Test status
Simulation time 17377764 ps
CPU time 1.01 seconds
Started Apr 30 02:43:38 PM PDT 24
Finished Apr 30 02:43:40 PM PDT 24
Peak memory 215140 kb
Host smart-badcf58d-cb3e-4583-b0d0-506898cf51cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374480912 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3374480912
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3583115238
Short name T330
Test name
Test status
Simulation time 153027326 ps
CPU time 1.47 seconds
Started Apr 30 02:43:35 PM PDT 24
Finished Apr 30 02:43:37 PM PDT 24
Peak memory 216832 kb
Host smart-2c087a97-4849-4fe3-9bdc-4b7fc984b004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583115238 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3583115238
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1665276229
Short name T827
Test name
Test status
Simulation time 101481995264 ps
CPU time 1174.65 seconds
Started Apr 30 02:43:31 PM PDT 24
Finished Apr 30 03:03:06 PM PDT 24
Peak memory 221928 kb
Host smart-d7e4ef25-9bcd-467d-9c82-c17eb1a4b3b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665276229 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1665276229
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3414094328
Short name T597
Test name
Test status
Simulation time 90254115 ps
CPU time 1.19 seconds
Started Apr 30 02:44:58 PM PDT 24
Finished Apr 30 02:45:00 PM PDT 24
Peak memory 216996 kb
Host smart-1f45ca7d-a59f-4d88-b3d8-2157146fbdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414094328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3414094328
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3264212128
Short name T375
Test name
Test status
Simulation time 116376255 ps
CPU time 1.25 seconds
Started Apr 30 02:45:00 PM PDT 24
Finished Apr 30 02:45:03 PM PDT 24
Peak memory 216900 kb
Host smart-bea844a4-06fe-429c-8b53-92e8298bc9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264212128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3264212128
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.134634765
Short name T599
Test name
Test status
Simulation time 107843881 ps
CPU time 1.7 seconds
Started Apr 30 02:45:01 PM PDT 24
Finished Apr 30 02:45:04 PM PDT 24
Peak memory 218208 kb
Host smart-51a6c420-b44e-42db-b42d-bdeeb500aa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134634765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.134634765
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1060290408
Short name T279
Test name
Test status
Simulation time 62308324 ps
CPU time 1.12 seconds
Started Apr 30 02:44:58 PM PDT 24
Finished Apr 30 02:45:00 PM PDT 24
Peak memory 219432 kb
Host smart-8e13317e-3a17-41af-b7b7-01527bab9b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060290408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1060290408
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3413200736
Short name T642
Test name
Test status
Simulation time 31746629 ps
CPU time 1.5 seconds
Started Apr 30 02:44:58 PM PDT 24
Finished Apr 30 02:45:00 PM PDT 24
Peak memory 216996 kb
Host smart-46f3e74a-30da-42f1-b0ee-da837b5d1664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413200736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3413200736
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1152439796
Short name T497
Test name
Test status
Simulation time 51711583 ps
CPU time 1.7 seconds
Started Apr 30 02:45:02 PM PDT 24
Finished Apr 30 02:45:05 PM PDT 24
Peak memory 218524 kb
Host smart-2c2d4d93-ae85-4545-ade8-e933d8e48e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152439796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1152439796
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1726332269
Short name T305
Test name
Test status
Simulation time 40028852 ps
CPU time 1.14 seconds
Started Apr 30 02:44:58 PM PDT 24
Finished Apr 30 02:45:00 PM PDT 24
Peak memory 216824 kb
Host smart-d10ec26c-c313-4809-9865-a5a22c9db331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726332269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1726332269
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1992411313
Short name T790
Test name
Test status
Simulation time 40160220 ps
CPU time 1.24 seconds
Started Apr 30 02:44:57 PM PDT 24
Finished Apr 30 02:44:59 PM PDT 24
Peak memory 216864 kb
Host smart-baaea8f6-74cd-4fb7-a7df-665180d6c0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992411313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1992411313
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.623410513
Short name T576
Test name
Test status
Simulation time 71756364 ps
CPU time 1.07 seconds
Started Apr 30 02:44:59 PM PDT 24
Finished Apr 30 02:45:01 PM PDT 24
Peak memory 217088 kb
Host smart-ac912c4d-5d7e-4c41-80df-9680fdaf83f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623410513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.623410513
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.254880768
Short name T652
Test name
Test status
Simulation time 22364137 ps
CPU time 1.19 seconds
Started Apr 30 02:43:38 PM PDT 24
Finished Apr 30 02:43:40 PM PDT 24
Peak memory 215548 kb
Host smart-b645ca86-6003-4915-9918-e8b853b49337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254880768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.254880768
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1107285277
Short name T531
Test name
Test status
Simulation time 44128569 ps
CPU time 1.35 seconds
Started Apr 30 02:43:42 PM PDT 24
Finished Apr 30 02:43:44 PM PDT 24
Peak memory 206632 kb
Host smart-c527fbdf-de62-4e48-a426-76eadfdbd418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107285277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1107285277
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1979664199
Short name T106
Test name
Test status
Simulation time 65620928 ps
CPU time 1.35 seconds
Started Apr 30 02:43:38 PM PDT 24
Finished Apr 30 02:43:40 PM PDT 24
Peak memory 216720 kb
Host smart-3dc86dfb-05f8-48f5-b104-c6249cf669ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979664199 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1979664199
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1462783161
Short name T137
Test name
Test status
Simulation time 21123175 ps
CPU time 1.1 seconds
Started Apr 30 02:43:56 PM PDT 24
Finished Apr 30 02:43:58 PM PDT 24
Peak memory 218280 kb
Host smart-85fe48f4-b5ba-4bd0-9688-6f2c46851024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462783161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1462783161
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1275897989
Short name T674
Test name
Test status
Simulation time 129352684 ps
CPU time 2.86 seconds
Started Apr 30 02:43:39 PM PDT 24
Finished Apr 30 02:43:43 PM PDT 24
Peak memory 218360 kb
Host smart-bac0e008-1126-450c-9e2e-bb588608b58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275897989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1275897989
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1214179557
Short name T621
Test name
Test status
Simulation time 44306248 ps
CPU time 1 seconds
Started Apr 30 02:43:39 PM PDT 24
Finished Apr 30 02:43:40 PM PDT 24
Peak memory 223732 kb
Host smart-f8dde3ca-45cd-4be9-957e-afaad0287130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214179557 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1214179557
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.845904589
Short name T439
Test name
Test status
Simulation time 28348811 ps
CPU time 0.91 seconds
Started Apr 30 02:43:54 PM PDT 24
Finished Apr 30 02:43:56 PM PDT 24
Peak memory 215100 kb
Host smart-200466f7-45da-4825-a56b-a529d80f3fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845904589 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.845904589
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1045467374
Short name T725
Test name
Test status
Simulation time 270724386 ps
CPU time 3.17 seconds
Started Apr 30 02:43:41 PM PDT 24
Finished Apr 30 02:43:45 PM PDT 24
Peak memory 215164 kb
Host smart-bce50d8c-559c-44b9-98b5-f3fb8991aff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045467374 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1045467374
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1094821941
Short name T538
Test name
Test status
Simulation time 71986927812 ps
CPU time 934.8 seconds
Started Apr 30 02:43:37 PM PDT 24
Finished Apr 30 02:59:12 PM PDT 24
Peak memory 220892 kb
Host smart-4fe83caa-ccdf-403f-b815-b5dc8aea2e27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094821941 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1094821941
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1169174806
Short name T653
Test name
Test status
Simulation time 54897648 ps
CPU time 1.34 seconds
Started Apr 30 02:44:57 PM PDT 24
Finished Apr 30 02:44:59 PM PDT 24
Peak memory 218256 kb
Host smart-d4a54d0b-6d23-4545-9c91-135983f45211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169174806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1169174806
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2661573917
Short name T409
Test name
Test status
Simulation time 38526980 ps
CPU time 1.64 seconds
Started Apr 30 02:44:59 PM PDT 24
Finished Apr 30 02:45:01 PM PDT 24
Peak memory 218076 kb
Host smart-74d6c100-99ba-41ff-b512-a17222f8440c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661573917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2661573917
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1827604228
Short name T257
Test name
Test status
Simulation time 49461017 ps
CPU time 1.4 seconds
Started Apr 30 02:44:59 PM PDT 24
Finished Apr 30 02:45:01 PM PDT 24
Peak memory 217172 kb
Host smart-3aba31d1-374c-4a5e-a556-96c6f9bcc988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827604228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1827604228
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2044261717
Short name T467
Test name
Test status
Simulation time 80204065 ps
CPU time 1.08 seconds
Started Apr 30 02:45:02 PM PDT 24
Finished Apr 30 02:45:04 PM PDT 24
Peak memory 216880 kb
Host smart-a40e68e2-617f-4ced-bee7-8777139ce511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044261717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2044261717
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1683575056
Short name T449
Test name
Test status
Simulation time 60098208 ps
CPU time 1.17 seconds
Started Apr 30 02:45:02 PM PDT 24
Finished Apr 30 02:45:04 PM PDT 24
Peak memory 216748 kb
Host smart-0926884f-07ed-4b93-8df1-4cdbedcf6dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683575056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1683575056
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2532898482
Short name T49
Test name
Test status
Simulation time 45810874 ps
CPU time 1.2 seconds
Started Apr 30 02:44:59 PM PDT 24
Finished Apr 30 02:45:02 PM PDT 24
Peak memory 216728 kb
Host smart-51e0b8e5-2c80-4cd5-99eb-8acdfc123152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532898482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2532898482
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3382333540
Short name T421
Test name
Test status
Simulation time 34728204 ps
CPU time 1.19 seconds
Started Apr 30 02:44:58 PM PDT 24
Finished Apr 30 02:45:00 PM PDT 24
Peak memory 219500 kb
Host smart-6d854b27-638c-4f90-b46e-216a41bfd964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382333540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3382333540
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.174800142
Short name T86
Test name
Test status
Simulation time 51010537 ps
CPU time 1.24 seconds
Started Apr 30 02:45:02 PM PDT 24
Finished Apr 30 02:45:04 PM PDT 24
Peak memory 217032 kb
Host smart-0be080cd-e817-4ea0-b58b-f639872ee86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174800142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.174800142
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3735164275
Short name T432
Test name
Test status
Simulation time 69388318 ps
CPU time 1.1 seconds
Started Apr 30 02:45:00 PM PDT 24
Finished Apr 30 02:45:02 PM PDT 24
Peak memory 216808 kb
Host smart-94496ea3-a8f5-4717-bdf9-85923d943380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735164275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3735164275
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3766189312
Short name T646
Test name
Test status
Simulation time 86317910 ps
CPU time 1.13 seconds
Started Apr 30 02:44:58 PM PDT 24
Finished Apr 30 02:45:00 PM PDT 24
Peak memory 218328 kb
Host smart-55aeb147-b955-44d7-b5fb-2f2f8bd3a006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766189312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3766189312
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1593530882
Short name T95
Test name
Test status
Simulation time 28593885 ps
CPU time 1.29 seconds
Started Apr 30 02:43:54 PM PDT 24
Finished Apr 30 02:43:56 PM PDT 24
Peak memory 215612 kb
Host smart-6f7eb738-332d-4d70-b91f-e98f9101b8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593530882 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1593530882
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2221858284
Short name T842
Test name
Test status
Simulation time 41662267 ps
CPU time 0.83 seconds
Started Apr 30 02:43:52 PM PDT 24
Finished Apr 30 02:43:54 PM PDT 24
Peak memory 206504 kb
Host smart-774d4b3d-5948-4a52-b711-1cbbc40d8931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221858284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2221858284
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2166020429
Short name T570
Test name
Test status
Simulation time 22299219 ps
CPU time 0.87 seconds
Started Apr 30 02:43:39 PM PDT 24
Finished Apr 30 02:43:40 PM PDT 24
Peak memory 216112 kb
Host smart-a26d9fef-4eb7-4935-9013-c840e8e3ee8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166020429 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2166020429
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3058879598
Short name T175
Test name
Test status
Simulation time 245122126 ps
CPU time 1.2 seconds
Started Apr 30 02:43:58 PM PDT 24
Finished Apr 30 02:44:01 PM PDT 24
Peak memory 219272 kb
Host smart-900ab76a-64d1-4452-959e-148cdd43fe05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058879598 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3058879598
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.570619122
Short name T63
Test name
Test status
Simulation time 21104148 ps
CPU time 1.03 seconds
Started Apr 30 02:43:47 PM PDT 24
Finished Apr 30 02:43:49 PM PDT 24
Peak memory 223836 kb
Host smart-fb740e86-5917-4b6c-8c89-2e5b7abfbc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570619122 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.570619122
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2897254544
Short name T43
Test name
Test status
Simulation time 37453647 ps
CPU time 1.5 seconds
Started Apr 30 02:43:43 PM PDT 24
Finished Apr 30 02:43:45 PM PDT 24
Peak memory 218356 kb
Host smart-cc2eb717-5960-4762-982f-2395e0a47f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897254544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2897254544
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2422894421
Short name T36
Test name
Test status
Simulation time 20876396 ps
CPU time 1.08 seconds
Started Apr 30 02:43:46 PM PDT 24
Finished Apr 30 02:43:48 PM PDT 24
Peak memory 215664 kb
Host smart-92967df1-167d-4b50-a899-bf54bec735cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422894421 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2422894421
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3579821674
Short name T431
Test name
Test status
Simulation time 187605313 ps
CPU time 0.9 seconds
Started Apr 30 02:43:37 PM PDT 24
Finished Apr 30 02:43:39 PM PDT 24
Peak memory 215144 kb
Host smart-7372d7f4-45fb-449b-ab16-77e2ef48857a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579821674 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3579821674
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1019815823
Short name T533
Test name
Test status
Simulation time 95177384 ps
CPU time 2.41 seconds
Started Apr 30 02:43:46 PM PDT 24
Finished Apr 30 02:43:49 PM PDT 24
Peak memory 216732 kb
Host smart-93a880a1-193b-494e-867f-98923a8534f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019815823 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1019815823
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.692985739
Short name T541
Test name
Test status
Simulation time 58863904324 ps
CPU time 770.13 seconds
Started Apr 30 02:43:52 PM PDT 24
Finished Apr 30 02:56:43 PM PDT 24
Peak memory 218748 kb
Host smart-7fda0983-1559-4de0-a684-441e59ac7c1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692985739 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.692985739
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.27665517
Short name T593
Test name
Test status
Simulation time 334286581 ps
CPU time 1.21 seconds
Started Apr 30 02:45:02 PM PDT 24
Finished Apr 30 02:45:04 PM PDT 24
Peak memory 216728 kb
Host smart-3567782e-7cba-459a-a19c-ee1f944b1d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27665517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.27665517
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1811697881
Short name T548
Test name
Test status
Simulation time 204898484 ps
CPU time 1.18 seconds
Started Apr 30 02:45:05 PM PDT 24
Finished Apr 30 02:45:07 PM PDT 24
Peak memory 219664 kb
Host smart-a4a4b419-be0c-4f62-95fc-09ed9e9841a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811697881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1811697881
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.76740793
Short name T461
Test name
Test status
Simulation time 55713018 ps
CPU time 1.35 seconds
Started Apr 30 02:44:58 PM PDT 24
Finished Apr 30 02:45:00 PM PDT 24
Peak memory 219088 kb
Host smart-0ba1e1bf-1a02-49da-9f7a-5af4478d3d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76740793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.76740793
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.4078321265
Short name T240
Test name
Test status
Simulation time 49799620 ps
CPU time 1.5 seconds
Started Apr 30 02:45:00 PM PDT 24
Finished Apr 30 02:45:02 PM PDT 24
Peak memory 218120 kb
Host smart-7d0ae3c8-6e75-4baf-b4c4-1439f8d1d8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078321265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.4078321265
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2661764528
Short name T442
Test name
Test status
Simulation time 109841354 ps
CPU time 1.41 seconds
Started Apr 30 02:44:58 PM PDT 24
Finished Apr 30 02:45:00 PM PDT 24
Peak memory 215228 kb
Host smart-5fb265d2-c137-4d35-8827-c1de26ba311e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661764528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2661764528
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3121850545
Short name T517
Test name
Test status
Simulation time 37181628 ps
CPU time 1.41 seconds
Started Apr 30 02:45:00 PM PDT 24
Finished Apr 30 02:45:03 PM PDT 24
Peak memory 217248 kb
Host smart-f78d6cd3-758c-4624-8142-032a26b5ed77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121850545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3121850545
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3784060820
Short name T69
Test name
Test status
Simulation time 71946142 ps
CPU time 1.7 seconds
Started Apr 30 02:44:59 PM PDT 24
Finished Apr 30 02:45:01 PM PDT 24
Peak memory 218260 kb
Host smart-9b048deb-d465-471c-aea3-5938bd710f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784060820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3784060820
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2270464129
Short name T743
Test name
Test status
Simulation time 49973536 ps
CPU time 1.42 seconds
Started Apr 30 02:44:58 PM PDT 24
Finished Apr 30 02:45:00 PM PDT 24
Peak memory 217952 kb
Host smart-b4dfdbc9-a413-4cee-a8c2-c5751688771c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270464129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2270464129
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3676618540
Short name T326
Test name
Test status
Simulation time 56161725 ps
CPU time 1.25 seconds
Started Apr 30 02:45:00 PM PDT 24
Finished Apr 30 02:45:02 PM PDT 24
Peak memory 216800 kb
Host smart-9996008a-856c-4c13-b22b-dbfcbf377c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676618540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3676618540
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.3590140300
Short name T169
Test name
Test status
Simulation time 87405027 ps
CPU time 1.21 seconds
Started Apr 30 02:43:53 PM PDT 24
Finished Apr 30 02:43:55 PM PDT 24
Peak memory 215568 kb
Host smart-867690b8-844b-4b1e-b47e-079936425838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590140300 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3590140300
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.628731311
Short name T56
Test name
Test status
Simulation time 160604312 ps
CPU time 0.95 seconds
Started Apr 30 02:43:58 PM PDT 24
Finished Apr 30 02:44:00 PM PDT 24
Peak memory 214824 kb
Host smart-11d6d48c-b96a-4d54-99f9-9bb18ab5bbbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628731311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.628731311
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2295826626
Short name T45
Test name
Test status
Simulation time 11792264 ps
CPU time 0.88 seconds
Started Apr 30 02:43:46 PM PDT 24
Finished Apr 30 02:43:47 PM PDT 24
Peak memory 215960 kb
Host smart-c5c48340-a6e4-48ea-9098-8cb5bb45ae9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295826626 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2295826626
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.94874415
Short name T788
Test name
Test status
Simulation time 62772721 ps
CPU time 1.18 seconds
Started Apr 30 02:43:46 PM PDT 24
Finished Apr 30 02:43:48 PM PDT 24
Peak memory 216680 kb
Host smart-0a9a5e7d-d61a-4a7c-8695-6e2846333a05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94874415 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_dis
able_auto_req_mode.94874415
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.4016803200
Short name T105
Test name
Test status
Simulation time 23509954 ps
CPU time 1.11 seconds
Started Apr 30 02:43:37 PM PDT 24
Finished Apr 30 02:43:39 PM PDT 24
Peak memory 219576 kb
Host smart-43ac9a69-5860-4aa7-9a9a-7535418acab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016803200 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.4016803200
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.726262823
Short name T777
Test name
Test status
Simulation time 65517279 ps
CPU time 1.56 seconds
Started Apr 30 02:43:42 PM PDT 24
Finished Apr 30 02:43:44 PM PDT 24
Peak memory 218076 kb
Host smart-b7a339c7-e496-41df-a41b-578e2b85e7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726262823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.726262823
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3970791252
Short name T551
Test name
Test status
Simulation time 21905373 ps
CPU time 1.08 seconds
Started Apr 30 02:43:39 PM PDT 24
Finished Apr 30 02:43:41 PM PDT 24
Peak memory 215604 kb
Host smart-262dfad6-29f8-441c-a845-4cf5a51eb4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970791252 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3970791252
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.676075371
Short name T351
Test name
Test status
Simulation time 31604608 ps
CPU time 0.97 seconds
Started Apr 30 02:43:37 PM PDT 24
Finished Apr 30 02:43:38 PM PDT 24
Peak memory 215144 kb
Host smart-88340caf-5753-40e9-9c12-ce47d7daa6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676075371 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.676075371
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1349351533
Short name T604
Test name
Test status
Simulation time 54905279 ps
CPU time 1.21 seconds
Started Apr 30 02:43:44 PM PDT 24
Finished Apr 30 02:43:46 PM PDT 24
Peak memory 216820 kb
Host smart-7d6988d6-48ad-4634-9c14-3bb87aebbd2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349351533 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1349351533
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1368171193
Short name T205
Test name
Test status
Simulation time 227277485967 ps
CPU time 1668.66 seconds
Started Apr 30 02:43:37 PM PDT 24
Finished Apr 30 03:11:26 PM PDT 24
Peak memory 222636 kb
Host smart-500de3aa-1bea-41c3-b41b-22ebaf81c521
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368171193 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1368171193
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.4132351077
Short name T246
Test name
Test status
Simulation time 44295685 ps
CPU time 1.18 seconds
Started Apr 30 02:45:05 PM PDT 24
Finished Apr 30 02:45:07 PM PDT 24
Peak memory 217912 kb
Host smart-a0188fd1-2cbb-47d2-a77c-4436b9c5e658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132351077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.4132351077
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3621247032
Short name T417
Test name
Test status
Simulation time 57461116 ps
CPU time 1.37 seconds
Started Apr 30 02:44:59 PM PDT 24
Finished Apr 30 02:45:02 PM PDT 24
Peak memory 218056 kb
Host smart-b495025b-62da-497b-84dd-e2bb71d220bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621247032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3621247032
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3047752894
Short name T243
Test name
Test status
Simulation time 74561025 ps
CPU time 1.28 seconds
Started Apr 30 02:44:58 PM PDT 24
Finished Apr 30 02:45:00 PM PDT 24
Peak memory 215168 kb
Host smart-5c4d7dc2-91e6-453f-8510-124ade3b29a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047752894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3047752894
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.711488451
Short name T712
Test name
Test status
Simulation time 57996917 ps
CPU time 1.32 seconds
Started Apr 30 02:44:59 PM PDT 24
Finished Apr 30 02:45:02 PM PDT 24
Peak memory 218284 kb
Host smart-bce72397-bb6b-4620-9743-fbb346ebcbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711488451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.711488451
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1366129971
Short name T765
Test name
Test status
Simulation time 84095909 ps
CPU time 1.17 seconds
Started Apr 30 02:45:02 PM PDT 24
Finished Apr 30 02:45:04 PM PDT 24
Peak memory 217268 kb
Host smart-bb06a24e-b25d-4a4a-9267-f0bcd22a6571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366129971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1366129971
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3089654280
Short name T585
Test name
Test status
Simulation time 83760866 ps
CPU time 1.51 seconds
Started Apr 30 02:45:02 PM PDT 24
Finished Apr 30 02:45:04 PM PDT 24
Peak memory 218232 kb
Host smart-e6148e7c-29ff-4120-ad61-b23d6b81932b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089654280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3089654280
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2469561208
Short name T476
Test name
Test status
Simulation time 50299821 ps
CPU time 1.49 seconds
Started Apr 30 02:45:00 PM PDT 24
Finished Apr 30 02:45:02 PM PDT 24
Peak memory 218288 kb
Host smart-4bbc091c-cefa-46cb-bb3e-0bbcc498f21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469561208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2469561208
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.846683441
Short name T299
Test name
Test status
Simulation time 55285134 ps
CPU time 1.71 seconds
Started Apr 30 02:45:04 PM PDT 24
Finished Apr 30 02:45:07 PM PDT 24
Peak memory 218244 kb
Host smart-9aec2f7b-2c87-4861-91db-f1d1844f6947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846683441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.846683441
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.417710898
Short name T630
Test name
Test status
Simulation time 38428537 ps
CPU time 1.51 seconds
Started Apr 30 02:45:02 PM PDT 24
Finished Apr 30 02:45:04 PM PDT 24
Peak memory 217976 kb
Host smart-f5517b7b-5eda-4db1-b754-38f5420176e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417710898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.417710898
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1385882898
Short name T459
Test name
Test status
Simulation time 52190474 ps
CPU time 1.58 seconds
Started Apr 30 02:45:01 PM PDT 24
Finished Apr 30 02:45:03 PM PDT 24
Peak memory 217892 kb
Host smart-990a7d49-c60b-4628-91fd-24a731630d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385882898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1385882898
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3109478306
Short name T252
Test name
Test status
Simulation time 109501271 ps
CPU time 1.33 seconds
Started Apr 30 02:42:54 PM PDT 24
Finished Apr 30 02:42:56 PM PDT 24
Peak memory 215552 kb
Host smart-4a22311b-85e7-44c1-8b6e-d3d464fd32de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109478306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3109478306
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3150307550
Short name T366
Test name
Test status
Simulation time 155572825 ps
CPU time 0.93 seconds
Started Apr 30 02:43:07 PM PDT 24
Finished Apr 30 02:43:09 PM PDT 24
Peak memory 214664 kb
Host smart-ac597899-3318-425a-b2e8-97e03d967ec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150307550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3150307550
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2452980073
Short name T632
Test name
Test status
Simulation time 14116147 ps
CPU time 0.91 seconds
Started Apr 30 02:42:56 PM PDT 24
Finished Apr 30 02:42:58 PM PDT 24
Peak memory 216344 kb
Host smart-125d874c-7545-4019-a423-d595fe0c22ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452980073 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2452980073
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3820460663
Short name T113
Test name
Test status
Simulation time 56185325 ps
CPU time 1.23 seconds
Started Apr 30 02:42:57 PM PDT 24
Finished Apr 30 02:42:59 PM PDT 24
Peak memory 216704 kb
Host smart-ac0225ae-9b1c-4388-a6d6-14e489c52576
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820460663 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3820460663
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2775073795
Short name T637
Test name
Test status
Simulation time 31003795 ps
CPU time 1.3 seconds
Started Apr 30 02:43:00 PM PDT 24
Finished Apr 30 02:43:02 PM PDT 24
Peak memory 218892 kb
Host smart-be1e4d08-53a9-4db1-a901-ee0ec5c23b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775073795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2775073795
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2130903635
Short name T492
Test name
Test status
Simulation time 49602771 ps
CPU time 1.27 seconds
Started Apr 30 02:42:58 PM PDT 24
Finished Apr 30 02:43:00 PM PDT 24
Peak memory 218148 kb
Host smart-dc882c83-59ad-4956-b24f-fd00d1c1ee83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130903635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2130903635
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2327300100
Short name T468
Test name
Test status
Simulation time 21888869 ps
CPU time 1.18 seconds
Started Apr 30 02:42:58 PM PDT 24
Finished Apr 30 02:43:01 PM PDT 24
Peak memory 223828 kb
Host smart-55cc4a72-908f-4bcf-992f-a52584dd6959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327300100 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2327300100
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_smoke.525092961
Short name T704
Test name
Test status
Simulation time 56137708 ps
CPU time 0.97 seconds
Started Apr 30 02:43:01 PM PDT 24
Finished Apr 30 02:43:03 PM PDT 24
Peak memory 215200 kb
Host smart-8415b1ba-fdd8-4361-9682-11273c57fea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525092961 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.525092961
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2316030369
Short name T534
Test name
Test status
Simulation time 765779991 ps
CPU time 4.29 seconds
Started Apr 30 02:43:00 PM PDT 24
Finished Apr 30 02:43:05 PM PDT 24
Peak memory 219432 kb
Host smart-649ccaa2-2994-47f4-953b-4fa85c582fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316030369 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2316030369
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_alert.142173922
Short name T32
Test name
Test status
Simulation time 27464510 ps
CPU time 1.25 seconds
Started Apr 30 02:43:46 PM PDT 24
Finished Apr 30 02:43:48 PM PDT 24
Peak memory 215492 kb
Host smart-ddfea269-250d-48c5-a7e1-60111ea28cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142173922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.142173922
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2059847443
Short name T556
Test name
Test status
Simulation time 44231247 ps
CPU time 1.05 seconds
Started Apr 30 02:43:39 PM PDT 24
Finished Apr 30 02:43:41 PM PDT 24
Peak memory 214816 kb
Host smart-9067897f-06fe-4f58-a08c-d12e86679e58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059847443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2059847443
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.4181070775
Short name T564
Test name
Test status
Simulation time 43538500 ps
CPU time 0.89 seconds
Started Apr 30 02:43:46 PM PDT 24
Finished Apr 30 02:43:47 PM PDT 24
Peak memory 215216 kb
Host smart-e72ddf8d-edce-4211-b87b-035810ba9d32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181070775 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.4181070775
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3430685074
Short name T592
Test name
Test status
Simulation time 73361537 ps
CPU time 1.02 seconds
Started Apr 30 02:43:58 PM PDT 24
Finished Apr 30 02:44:01 PM PDT 24
Peak memory 216668 kb
Host smart-bf4a353f-0c86-4b90-88db-85fecf37feb6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430685074 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3430685074
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.724314372
Short name T185
Test name
Test status
Simulation time 34886938 ps
CPU time 0.97 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:43:59 PM PDT 24
Peak memory 219560 kb
Host smart-7d71159e-4a5e-4099-82e1-ada95a8c2b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724314372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.724314372
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3978557757
Short name T809
Test name
Test status
Simulation time 84613837 ps
CPU time 1.23 seconds
Started Apr 30 02:43:49 PM PDT 24
Finished Apr 30 02:43:51 PM PDT 24
Peak memory 218248 kb
Host smart-65ad1309-6bce-4fb9-a64b-ef65afde0f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978557757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3978557757
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2590261514
Short name T514
Test name
Test status
Simulation time 57059154 ps
CPU time 0.94 seconds
Started Apr 30 02:43:56 PM PDT 24
Finished Apr 30 02:43:58 PM PDT 24
Peak memory 215108 kb
Host smart-1bcfde05-8dfa-4055-84c7-405fd2c99461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590261514 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2590261514
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.4061261641
Short name T719
Test name
Test status
Simulation time 27379920 ps
CPU time 0.99 seconds
Started Apr 30 02:43:48 PM PDT 24
Finished Apr 30 02:43:50 PM PDT 24
Peak memory 215184 kb
Host smart-dc4af9ed-773a-436b-b7fb-224c0e9f3743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061261641 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.4061261641
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2272288668
Short name T800
Test name
Test status
Simulation time 244694613 ps
CPU time 4.26 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:44:03 PM PDT 24
Peak memory 216640 kb
Host smart-5dee73d7-7093-4fb2-8eb8-35a6cd6e2156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272288668 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2272288668
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2216434077
Short name T165
Test name
Test status
Simulation time 49170276398 ps
CPU time 648.51 seconds
Started Apr 30 02:43:37 PM PDT 24
Finished Apr 30 02:54:26 PM PDT 24
Peak memory 218988 kb
Host smart-a768d49b-7ad5-4fd3-8677-e44c271c8eeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216434077 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2216434077
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3940875932
Short name T475
Test name
Test status
Simulation time 100005174 ps
CPU time 1.28 seconds
Started Apr 30 02:43:48 PM PDT 24
Finished Apr 30 02:43:50 PM PDT 24
Peak memory 215556 kb
Host smart-6ccfa8c4-5972-43c4-a2df-7fdf48c51d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940875932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3940875932
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3566059827
Short name T447
Test name
Test status
Simulation time 77738766 ps
CPU time 0.97 seconds
Started Apr 30 02:43:43 PM PDT 24
Finished Apr 30 02:43:45 PM PDT 24
Peak memory 215028 kb
Host smart-d1463587-fa56-4c8d-a26c-4d01dc4adf0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566059827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3566059827
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.743704744
Short name T705
Test name
Test status
Simulation time 14460832 ps
CPU time 0.97 seconds
Started Apr 30 02:43:47 PM PDT 24
Finished Apr 30 02:43:48 PM PDT 24
Peak memory 215384 kb
Host smart-3db7bf27-5652-4ae7-966a-8ae6945603de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743704744 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.743704744
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2282299451
Short name T126
Test name
Test status
Simulation time 51899798 ps
CPU time 1.12 seconds
Started Apr 30 02:44:00 PM PDT 24
Finished Apr 30 02:44:02 PM PDT 24
Peak memory 216904 kb
Host smart-cc5b1a0f-ee26-4060-95da-86aba3446881
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282299451 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2282299451
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.894682874
Short name T7
Test name
Test status
Simulation time 25830596 ps
CPU time 1.32 seconds
Started Apr 30 02:43:38 PM PDT 24
Finished Apr 30 02:43:40 PM PDT 24
Peak memory 223900 kb
Host smart-bb038998-8e48-416c-9a3b-20bc77fb9601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894682874 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.894682874
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3793605101
Short name T751
Test name
Test status
Simulation time 53634239 ps
CPU time 1.35 seconds
Started Apr 30 02:43:42 PM PDT 24
Finished Apr 30 02:43:44 PM PDT 24
Peak memory 215232 kb
Host smart-5bffb423-ce70-4daa-9a86-504822ae9fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793605101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3793605101
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1534269830
Short name T779
Test name
Test status
Simulation time 22185537 ps
CPU time 1.11 seconds
Started Apr 30 02:43:35 PM PDT 24
Finished Apr 30 02:43:37 PM PDT 24
Peak memory 215348 kb
Host smart-154137c1-c9f2-4a63-958b-7c407d34da4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534269830 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1534269830
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.413659997
Short name T824
Test name
Test status
Simulation time 15917276 ps
CPU time 0.97 seconds
Started Apr 30 02:43:39 PM PDT 24
Finished Apr 30 02:43:41 PM PDT 24
Peak memory 215088 kb
Host smart-21a8ea96-0429-423f-ad89-a6e24df17fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413659997 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.413659997
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3687562238
Short name T767
Test name
Test status
Simulation time 130901213 ps
CPU time 1.44 seconds
Started Apr 30 02:43:42 PM PDT 24
Finished Apr 30 02:43:44 PM PDT 24
Peak memory 215140 kb
Host smart-1f3b0e37-9c8d-4865-a68a-29f638a1d71b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687562238 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3687562238
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.282168742
Short name T713
Test name
Test status
Simulation time 51973497298 ps
CPU time 1191.85 seconds
Started Apr 30 02:43:54 PM PDT 24
Finished Apr 30 03:03:47 PM PDT 24
Peak memory 220860 kb
Host smart-b86b5b74-6334-4285-a1b2-c4847ee99d69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282168742 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.282168742
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1422456722
Short name T253
Test name
Test status
Simulation time 24679129 ps
CPU time 1.22 seconds
Started Apr 30 02:43:59 PM PDT 24
Finished Apr 30 02:44:01 PM PDT 24
Peak memory 215528 kb
Host smart-97f0340b-e4be-4104-8f6d-4a9be155cff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422456722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1422456722
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3911671843
Short name T448
Test name
Test status
Simulation time 31932154 ps
CPU time 1 seconds
Started Apr 30 02:43:58 PM PDT 24
Finished Apr 30 02:44:00 PM PDT 24
Peak memory 214772 kb
Host smart-cd08b9be-1657-4496-85ca-a8c61a15fb17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911671843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3911671843
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3832355897
Short name T771
Test name
Test status
Simulation time 43587270 ps
CPU time 0.84 seconds
Started Apr 30 02:43:59 PM PDT 24
Finished Apr 30 02:44:01 PM PDT 24
Peak memory 215240 kb
Host smart-b05443b8-7a13-4d17-87c1-622eec3a88ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832355897 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3832355897
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.29864190
Short name T481
Test name
Test status
Simulation time 55716120 ps
CPU time 1.1 seconds
Started Apr 30 02:43:51 PM PDT 24
Finished Apr 30 02:43:53 PM PDT 24
Peak memory 217964 kb
Host smart-6a5865ac-114f-4fbc-b063-f359fa77d395
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29864190 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_dis
able_auto_req_mode.29864190
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.1948594229
Short name T359
Test name
Test status
Simulation time 19015981 ps
CPU time 1.02 seconds
Started Apr 30 02:43:48 PM PDT 24
Finished Apr 30 02:43:49 PM PDT 24
Peak memory 218108 kb
Host smart-5a1f26c3-6eda-43fc-9652-769b8bee2059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948594229 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1948594229
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2015391810
Short name T416
Test name
Test status
Simulation time 30800757 ps
CPU time 1.36 seconds
Started Apr 30 02:43:58 PM PDT 24
Finished Apr 30 02:44:01 PM PDT 24
Peak memory 219364 kb
Host smart-67bde7b0-428c-42f9-9f10-895736aa9ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015391810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2015391810
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2785931882
Short name T343
Test name
Test status
Simulation time 125827448 ps
CPU time 0.89 seconds
Started Apr 30 02:43:45 PM PDT 24
Finished Apr 30 02:43:47 PM PDT 24
Peak memory 215160 kb
Host smart-896d7030-b313-4383-b6b9-359b4e7b1410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785931882 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2785931882
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1452536608
Short name T473
Test name
Test status
Simulation time 16622743 ps
CPU time 1.04 seconds
Started Apr 30 02:43:54 PM PDT 24
Finished Apr 30 02:43:56 PM PDT 24
Peak memory 215208 kb
Host smart-22832faf-0139-41bd-aeb9-65fa113b086e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452536608 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1452536608
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1734183877
Short name T474
Test name
Test status
Simulation time 2234786614 ps
CPU time 4.94 seconds
Started Apr 30 02:43:47 PM PDT 24
Finished Apr 30 02:43:52 PM PDT 24
Peak memory 219620 kb
Host smart-dc663f40-bb8c-40ca-a8e3-eac1c792b23e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734183877 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1734183877
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.588636033
Short name T428
Test name
Test status
Simulation time 439213750388 ps
CPU time 1473.77 seconds
Started Apr 30 02:43:45 PM PDT 24
Finished Apr 30 03:08:20 PM PDT 24
Peak memory 223680 kb
Host smart-659af723-6558-41f3-b205-1bce7ba1236d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588636033 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.588636033
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.4183234312
Short name T88
Test name
Test status
Simulation time 59259122 ps
CPU time 1.22 seconds
Started Apr 30 02:43:52 PM PDT 24
Finished Apr 30 02:43:54 PM PDT 24
Peak memory 215548 kb
Host smart-317e6e33-0b24-4770-82b8-0bbe9fcb20f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183234312 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.4183234312
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2360347050
Short name T636
Test name
Test status
Simulation time 105494250 ps
CPU time 0.9 seconds
Started Apr 30 02:43:58 PM PDT 24
Finished Apr 30 02:44:00 PM PDT 24
Peak memory 215112 kb
Host smart-6d0d0966-dce7-483d-b45e-346d624b7a90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360347050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2360347050
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.908002725
Short name T325
Test name
Test status
Simulation time 81766780 ps
CPU time 1.26 seconds
Started Apr 30 02:43:44 PM PDT 24
Finished Apr 30 02:43:46 PM PDT 24
Peak memory 216652 kb
Host smart-3de210bc-55c8-47a6-aed8-dfd173718149
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908002725 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.908002725
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.137650627
Short name T191
Test name
Test status
Simulation time 22703611 ps
CPU time 1.04 seconds
Started Apr 30 02:43:49 PM PDT 24
Finished Apr 30 02:43:51 PM PDT 24
Peak memory 223860 kb
Host smart-a29986ff-cd3b-48ed-a6a8-cd9e71e52b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137650627 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.137650627
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2833577855
Short name T804
Test name
Test status
Simulation time 49351656 ps
CPU time 1.14 seconds
Started Apr 30 02:43:46 PM PDT 24
Finished Apr 30 02:43:48 PM PDT 24
Peak memory 218148 kb
Host smart-99452a88-b7e9-4c05-9ca3-bd0c8e0428dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833577855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2833577855
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3238068970
Short name T170
Test name
Test status
Simulation time 36136728 ps
CPU time 0.83 seconds
Started Apr 30 02:43:46 PM PDT 24
Finished Apr 30 02:43:48 PM PDT 24
Peak memory 215524 kb
Host smart-4a917df8-fd87-49e2-a25e-51d1e279806e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238068970 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3238068970
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3109396187
Short name T443
Test name
Test status
Simulation time 49022304 ps
CPU time 0.93 seconds
Started Apr 30 02:43:46 PM PDT 24
Finished Apr 30 02:43:48 PM PDT 24
Peak memory 215128 kb
Host smart-6e526d8d-f2b1-4133-a76b-8b654e69a76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109396187 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3109396187
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3413871807
Short name T740
Test name
Test status
Simulation time 298835998 ps
CPU time 3.35 seconds
Started Apr 30 02:43:51 PM PDT 24
Finished Apr 30 02:43:55 PM PDT 24
Peak memory 219316 kb
Host smart-2f9d91f8-d76c-440e-834a-ab6133b84ac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413871807 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3413871807
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.730117405
Short name T678
Test name
Test status
Simulation time 57616299749 ps
CPU time 1266.65 seconds
Started Apr 30 02:43:46 PM PDT 24
Finished Apr 30 03:04:54 PM PDT 24
Peak memory 221640 kb
Host smart-70b7daa0-d01f-47f6-b163-f45f8d44952d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730117405 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.730117405
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3318796773
Short name T9
Test name
Test status
Simulation time 37170809 ps
CPU time 1.13 seconds
Started Apr 30 02:43:48 PM PDT 24
Finished Apr 30 02:43:49 PM PDT 24
Peak memory 215544 kb
Host smart-4bd9b45c-d876-480b-af68-d2d40da13216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318796773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3318796773
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2853609851
Short name T356
Test name
Test status
Simulation time 94542169 ps
CPU time 0.95 seconds
Started Apr 30 02:43:56 PM PDT 24
Finished Apr 30 02:43:58 PM PDT 24
Peak memory 206536 kb
Host smart-2acabcbe-ad2a-493e-b3cd-4d39d690ba96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853609851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2853609851
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.303236063
Short name T90
Test name
Test status
Simulation time 11895851 ps
CPU time 0.88 seconds
Started Apr 30 02:44:00 PM PDT 24
Finished Apr 30 02:44:02 PM PDT 24
Peak memory 215944 kb
Host smart-0775d68d-0813-477e-8795-2f331d820c44
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303236063 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.303236063
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3028190921
Short name T802
Test name
Test status
Simulation time 67322623 ps
CPU time 1.03 seconds
Started Apr 30 02:43:47 PM PDT 24
Finished Apr 30 02:43:48 PM PDT 24
Peak memory 217776 kb
Host smart-cd2d6d5e-7586-4390-9da3-263d865c668a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028190921 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3028190921
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2140803271
Short name T844
Test name
Test status
Simulation time 47337806 ps
CPU time 1.27 seconds
Started Apr 30 02:43:45 PM PDT 24
Finished Apr 30 02:43:47 PM PDT 24
Peak memory 225604 kb
Host smart-40a3eb4d-6b24-4d04-90d2-aedcef7db226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140803271 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2140803271
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1567310155
Short name T315
Test name
Test status
Simulation time 33541695 ps
CPU time 1.27 seconds
Started Apr 30 02:43:54 PM PDT 24
Finished Apr 30 02:43:56 PM PDT 24
Peak memory 217912 kb
Host smart-e634aec3-eab7-4866-864b-bb131b1245ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567310155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1567310155
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1970680489
Short name T393
Test name
Test status
Simulation time 25455571 ps
CPU time 1.31 seconds
Started Apr 30 02:43:45 PM PDT 24
Finished Apr 30 02:43:47 PM PDT 24
Peak memory 223880 kb
Host smart-441bb52f-b324-403c-a1e8-8d181cf059d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970680489 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1970680489
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1549471485
Short name T435
Test name
Test status
Simulation time 56961755 ps
CPU time 0.9 seconds
Started Apr 30 02:43:45 PM PDT 24
Finished Apr 30 02:43:46 PM PDT 24
Peak memory 215100 kb
Host smart-64189c9e-ccce-4468-9e79-6480a00f9ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549471485 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1549471485
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2292272167
Short name T211
Test name
Test status
Simulation time 117068629 ps
CPU time 2.74 seconds
Started Apr 30 02:43:56 PM PDT 24
Finished Apr 30 02:43:59 PM PDT 24
Peak memory 216928 kb
Host smart-b49997c5-d90d-456b-a2be-8eb389a7e6d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292272167 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2292272167
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2806327804
Short name T575
Test name
Test status
Simulation time 123082998508 ps
CPU time 1444.92 seconds
Started Apr 30 02:43:54 PM PDT 24
Finished Apr 30 03:08:00 PM PDT 24
Peak memory 222700 kb
Host smart-ab391bab-e241-4ccc-ab3a-5c35d946da10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806327804 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2806327804
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert_test.1223814937
Short name T347
Test name
Test status
Simulation time 18040353 ps
CPU time 0.96 seconds
Started Apr 30 02:43:53 PM PDT 24
Finished Apr 30 02:43:54 PM PDT 24
Peak memory 206424 kb
Host smart-0fe3c9e3-a0bf-4b8b-9cdb-12895425757e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223814937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1223814937
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.791272825
Short name T559
Test name
Test status
Simulation time 26310027 ps
CPU time 0.84 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:44:00 PM PDT 24
Peak memory 216204 kb
Host smart-498961ac-7de3-4800-a3cc-7d71e0ef06c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791272825 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.791272825
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1791809656
Short name T696
Test name
Test status
Simulation time 97363149 ps
CPU time 1.02 seconds
Started Apr 30 02:43:56 PM PDT 24
Finished Apr 30 02:43:58 PM PDT 24
Peak memory 216764 kb
Host smart-9daee5b7-8dc4-47d1-862e-bf04433a8ffe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791809656 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1791809656
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3477267042
Short name T117
Test name
Test status
Simulation time 72691700 ps
CPU time 1.02 seconds
Started Apr 30 02:43:47 PM PDT 24
Finished Apr 30 02:43:48 PM PDT 24
Peak memory 220460 kb
Host smart-ca72ba75-c6e0-490d-b6c4-eac1627a5edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477267042 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3477267042
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.4265294355
Short name T276
Test name
Test status
Simulation time 41411901 ps
CPU time 1.46 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:44:01 PM PDT 24
Peak memory 218000 kb
Host smart-93f8c1e4-0f92-44ae-886a-9ee93f6440f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265294355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.4265294355
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1419145155
Short name T160
Test name
Test status
Simulation time 34421282 ps
CPU time 0.87 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:44:00 PM PDT 24
Peak memory 215304 kb
Host smart-b1ba514a-8a3a-4078-a4b5-b0530eca6183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419145155 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1419145155
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2311046171
Short name T663
Test name
Test status
Simulation time 48403136 ps
CPU time 0.91 seconds
Started Apr 30 02:43:51 PM PDT 24
Finished Apr 30 02:43:53 PM PDT 24
Peak memory 215108 kb
Host smart-23adf6fb-fcac-4fbd-8451-93c8ecb8c08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311046171 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2311046171
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2395000403
Short name T465
Test name
Test status
Simulation time 399388288 ps
CPU time 4.37 seconds
Started Apr 30 02:43:46 PM PDT 24
Finished Apr 30 02:43:51 PM PDT 24
Peak memory 220176 kb
Host smart-4b756bd0-d095-4a3d-959c-0b5770a51973
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395000403 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2395000403
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.704563980
Short name T588
Test name
Test status
Simulation time 365861328816 ps
CPU time 2477.59 seconds
Started Apr 30 02:43:50 PM PDT 24
Finished Apr 30 03:25:09 PM PDT 24
Peak memory 231044 kb
Host smart-4e609e47-6e2c-42a6-98ba-d6d9cef965b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704563980 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.704563980
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert_test.1737249957
Short name T524
Test name
Test status
Simulation time 14764495 ps
CPU time 0.92 seconds
Started Apr 30 02:43:59 PM PDT 24
Finished Apr 30 02:44:01 PM PDT 24
Peak memory 206456 kb
Host smart-012b2fa6-345c-4150-ac88-3ff7e9b0bafa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737249957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1737249957
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1449491876
Short name T711
Test name
Test status
Simulation time 39605770 ps
CPU time 0.89 seconds
Started Apr 30 02:43:58 PM PDT 24
Finished Apr 30 02:44:00 PM PDT 24
Peak memory 215896 kb
Host smart-fe67f9a1-a2be-4249-bb93-48cc51b3319c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449491876 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1449491876
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_err.690522284
Short name T755
Test name
Test status
Simulation time 23487552 ps
CPU time 1.02 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:44:00 PM PDT 24
Peak memory 223880 kb
Host smart-4d9090e1-5436-4259-90c5-5608b6e30ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690522284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.690522284
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.928233070
Short name T814
Test name
Test status
Simulation time 91631853 ps
CPU time 1.2 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:43:59 PM PDT 24
Peak memory 218696 kb
Host smart-0712e586-ba67-4fe8-9126-a3b68ca53df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928233070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.928233070
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1506803630
Short name T37
Test name
Test status
Simulation time 21556780 ps
CPU time 1.08 seconds
Started Apr 30 02:43:54 PM PDT 24
Finished Apr 30 02:43:56 PM PDT 24
Peak memory 215624 kb
Host smart-b17d9780-b53e-429f-bef9-8c903bbaf162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506803630 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1506803630
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1383700763
Short name T596
Test name
Test status
Simulation time 16100743 ps
CPU time 1.02 seconds
Started Apr 30 02:44:01 PM PDT 24
Finished Apr 30 02:44:03 PM PDT 24
Peak memory 215144 kb
Host smart-c6c2f3dc-e3ae-4870-b401-9f0b419554ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383700763 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1383700763
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2968826550
Short name T609
Test name
Test status
Simulation time 580370507 ps
CPU time 3.98 seconds
Started Apr 30 02:44:02 PM PDT 24
Finished Apr 30 02:44:07 PM PDT 24
Peak memory 216844 kb
Host smart-5a7f7bb2-f61e-440a-91a9-ecab2be2e315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968826550 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2968826550
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3748377357
Short name T775
Test name
Test status
Simulation time 67457433828 ps
CPU time 1522.37 seconds
Started Apr 30 02:43:52 PM PDT 24
Finished Apr 30 03:09:16 PM PDT 24
Peak memory 223064 kb
Host smart-288ca789-687a-40b9-bc01-6d85c73574d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748377357 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3748377357
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.4273901494
Short name T822
Test name
Test status
Simulation time 43965987 ps
CPU time 1.12 seconds
Started Apr 30 02:44:04 PM PDT 24
Finished Apr 30 02:44:06 PM PDT 24
Peak memory 215536 kb
Host smart-73676abb-0f39-4d52-9225-406f36b9f573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273901494 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.4273901494
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2863879917
Short name T685
Test name
Test status
Simulation time 18172985 ps
CPU time 0.93 seconds
Started Apr 30 02:43:53 PM PDT 24
Finished Apr 30 02:43:55 PM PDT 24
Peak memory 206544 kb
Host smart-636a6c13-ea0e-4416-95ad-478adb66440e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863879917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2863879917
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2722482829
Short name T134
Test name
Test status
Simulation time 30246544 ps
CPU time 0.86 seconds
Started Apr 30 02:43:53 PM PDT 24
Finished Apr 30 02:43:55 PM PDT 24
Peak memory 215248 kb
Host smart-628c0f29-3cef-4542-99d5-b710613848d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722482829 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2722482829
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3073829812
Short name T189
Test name
Test status
Simulation time 38739670 ps
CPU time 1.32 seconds
Started Apr 30 02:44:01 PM PDT 24
Finished Apr 30 02:44:04 PM PDT 24
Peak memory 216520 kb
Host smart-d477ec97-61aa-49ef-86ef-6e389c78cb79
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073829812 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3073829812
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1945332930
Short name T15
Test name
Test status
Simulation time 21663193 ps
CPU time 1 seconds
Started Apr 30 02:43:50 PM PDT 24
Finished Apr 30 02:43:52 PM PDT 24
Peak memory 223864 kb
Host smart-c1b88892-73c8-4cdc-9a4b-a0ef44859fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945332930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1945332930
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1744410716
Short name T820
Test name
Test status
Simulation time 34980312 ps
CPU time 1.34 seconds
Started Apr 30 02:44:00 PM PDT 24
Finished Apr 30 02:44:03 PM PDT 24
Peak memory 217880 kb
Host smart-48b1d36e-88b0-48fe-9efb-57e962204224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744410716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1744410716
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2030697508
Short name T39
Test name
Test status
Simulation time 21530533 ps
CPU time 1.06 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:43:59 PM PDT 24
Peak memory 215736 kb
Host smart-7fa122b7-7e9e-420f-8341-0ae713b6a334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030697508 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2030697508
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2810728296
Short name T645
Test name
Test status
Simulation time 18165097 ps
CPU time 1.05 seconds
Started Apr 30 02:44:00 PM PDT 24
Finished Apr 30 02:44:02 PM PDT 24
Peak memory 215120 kb
Host smart-42c9ab69-b08c-4f40-9859-2946c800de19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810728296 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2810728296
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3751779152
Short name T74
Test name
Test status
Simulation time 305116635 ps
CPU time 4.13 seconds
Started Apr 30 02:43:53 PM PDT 24
Finished Apr 30 02:43:58 PM PDT 24
Peak memory 216736 kb
Host smart-5a800046-2e6e-468e-949f-1f1e95723513
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751779152 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3751779152
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2915514454
Short name T656
Test name
Test status
Simulation time 38460744715 ps
CPU time 767.71 seconds
Started Apr 30 02:44:03 PM PDT 24
Finished Apr 30 02:56:51 PM PDT 24
Peak memory 218912 kb
Host smart-0d74517c-fa4f-40bf-8071-0561423a4e61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915514454 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2915514454
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3141001641
Short name T242
Test name
Test status
Simulation time 24115542 ps
CPU time 1.28 seconds
Started Apr 30 02:43:56 PM PDT 24
Finished Apr 30 02:43:58 PM PDT 24
Peak memory 215460 kb
Host smart-f82e88e9-6416-4566-a963-73bdc13acdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141001641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3141001641
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3990990633
Short name T77
Test name
Test status
Simulation time 39737144 ps
CPU time 1.01 seconds
Started Apr 30 02:44:01 PM PDT 24
Finished Apr 30 02:44:03 PM PDT 24
Peak memory 214588 kb
Host smart-b0d46dae-5d0b-49ea-a7b7-4c540fabd646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990990633 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3990990633
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.466431106
Short name T612
Test name
Test status
Simulation time 26249910 ps
CPU time 1.15 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:43:59 PM PDT 24
Peak memory 218128 kb
Host smart-1981b816-8ee8-496e-b18e-1925d3f984ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466431106 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.466431106
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3056997925
Short name T103
Test name
Test status
Simulation time 24433312 ps
CPU time 1.04 seconds
Started Apr 30 02:43:56 PM PDT 24
Finished Apr 30 02:43:57 PM PDT 24
Peak memory 219464 kb
Host smart-796aeaff-2de0-4567-a033-c5e265ce340f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056997925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3056997925
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1165553929
Short name T720
Test name
Test status
Simulation time 51777769 ps
CPU time 1.3 seconds
Started Apr 30 02:43:51 PM PDT 24
Finished Apr 30 02:43:53 PM PDT 24
Peak memory 216964 kb
Host smart-1a05626e-0762-4b3b-8428-2c1b524d445e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165553929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1165553929
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3724884407
Short name T33
Test name
Test status
Simulation time 26516417 ps
CPU time 0.91 seconds
Started Apr 30 02:43:52 PM PDT 24
Finished Apr 30 02:43:53 PM PDT 24
Peak memory 215452 kb
Host smart-15793eb5-7f26-46cf-b07b-e6dc91246117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724884407 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3724884407
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.429428906
Short name T429
Test name
Test status
Simulation time 39273833 ps
CPU time 0.93 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:43:59 PM PDT 24
Peak memory 215120 kb
Host smart-98326ef7-afa6-48d3-8b85-46417fc839f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429428906 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.429428906
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2792516430
Short name T545
Test name
Test status
Simulation time 91445579 ps
CPU time 2.19 seconds
Started Apr 30 02:43:51 PM PDT 24
Finished Apr 30 02:43:53 PM PDT 24
Peak memory 216792 kb
Host smart-c318e70c-7e24-4057-add5-35c1530e4a60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792516430 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2792516430
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1446435072
Short name T405
Test name
Test status
Simulation time 53121936550 ps
CPU time 1388.44 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 03:07:06 PM PDT 24
Peak memory 223176 kb
Host smart-42e43a2e-835e-416f-9e90-effb51e1ac1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446435072 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1446435072
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2433464646
Short name T140
Test name
Test status
Simulation time 55944399 ps
CPU time 1.24 seconds
Started Apr 30 02:43:55 PM PDT 24
Finished Apr 30 02:43:57 PM PDT 24
Peak memory 215508 kb
Host smart-f13cb7f9-7495-4455-85b1-88b290eaa272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433464646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2433464646
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2124994516
Short name T625
Test name
Test status
Simulation time 15288842 ps
CPU time 0.96 seconds
Started Apr 30 02:43:58 PM PDT 24
Finished Apr 30 02:44:00 PM PDT 24
Peak memory 215060 kb
Host smart-3531a669-a73f-41f8-bb5b-2552ed310611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124994516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2124994516
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.872012880
Short name T757
Test name
Test status
Simulation time 38494841 ps
CPU time 0.9 seconds
Started Apr 30 02:44:01 PM PDT 24
Finished Apr 30 02:44:03 PM PDT 24
Peak memory 215288 kb
Host smart-93278ffc-a7c8-49b9-b9ed-36688a51d768
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872012880 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.872012880
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.144791457
Short name T21
Test name
Test status
Simulation time 90301142 ps
CPU time 1.13 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:43:59 PM PDT 24
Peak memory 216580 kb
Host smart-824b9a8b-1a57-4d91-9eb2-a3822b498678
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144791457 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.144791457
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.142484240
Short name T507
Test name
Test status
Simulation time 97490191 ps
CPU time 1.35 seconds
Started Apr 30 02:43:58 PM PDT 24
Finished Apr 30 02:44:01 PM PDT 24
Peak memory 225396 kb
Host smart-92800fa5-7a93-4f26-9ced-7f86f9b025d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142484240 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.142484240
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1988699729
Short name T700
Test name
Test status
Simulation time 43521210 ps
CPU time 1.23 seconds
Started Apr 30 02:43:56 PM PDT 24
Finished Apr 30 02:43:58 PM PDT 24
Peak memory 216924 kb
Host smart-b5951e8a-7352-43df-b50f-ca97d5c6e466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988699729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1988699729
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2023280707
Short name T834
Test name
Test status
Simulation time 87306545 ps
CPU time 0.98 seconds
Started Apr 30 02:43:54 PM PDT 24
Finished Apr 30 02:43:56 PM PDT 24
Peak memory 223700 kb
Host smart-17450d49-49d6-4aad-8e7f-20e0dfd41154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023280707 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2023280707
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.957096344
Short name T562
Test name
Test status
Simulation time 15313362 ps
CPU time 0.94 seconds
Started Apr 30 02:43:59 PM PDT 24
Finished Apr 30 02:44:01 PM PDT 24
Peak memory 215132 kb
Host smart-e38299fd-e7eb-45fc-82cf-c714c280df61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957096344 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.957096344
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.756106027
Short name T163
Test name
Test status
Simulation time 768237065 ps
CPU time 4.15 seconds
Started Apr 30 02:43:58 PM PDT 24
Finished Apr 30 02:44:03 PM PDT 24
Peak memory 215172 kb
Host smart-2e313ab2-a3f9-47d3-946e-0296bfcdd8db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756106027 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.756106027
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2820048258
Short name T41
Test name
Test status
Simulation time 98834073196 ps
CPU time 1378.13 seconds
Started Apr 30 02:43:52 PM PDT 24
Finished Apr 30 03:06:51 PM PDT 24
Peak memory 221860 kb
Host smart-ce8b96d9-051a-42b8-abe1-04ae2cd29c8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820048258 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2820048258
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3340942490
Short name T259
Test name
Test status
Simulation time 344775997 ps
CPU time 1.38 seconds
Started Apr 30 02:43:04 PM PDT 24
Finished Apr 30 02:43:07 PM PDT 24
Peak memory 215472 kb
Host smart-4e442d97-3efa-469d-8305-a259ad77e4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340942490 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3340942490
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1347654040
Short name T591
Test name
Test status
Simulation time 21842533 ps
CPU time 0.92 seconds
Started Apr 30 02:43:04 PM PDT 24
Finished Apr 30 02:43:07 PM PDT 24
Peak memory 206580 kb
Host smart-5d2cc969-af71-418b-a7bb-3d05b3dfdbad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347654040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1347654040
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1623090376
Short name T512
Test name
Test status
Simulation time 52329241 ps
CPU time 1.27 seconds
Started Apr 30 02:43:06 PM PDT 24
Finished Apr 30 02:43:09 PM PDT 24
Peak memory 219192 kb
Host smart-6e546ed4-4bb7-4280-ac53-78ad2241122f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623090376 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1623090376
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3303066444
Short name T159
Test name
Test status
Simulation time 28801762 ps
CPU time 0.88 seconds
Started Apr 30 02:43:05 PM PDT 24
Finished Apr 30 02:43:07 PM PDT 24
Peak memory 216536 kb
Host smart-9376bed1-2a72-4a22-987e-bab66d99c6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303066444 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3303066444
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1363163431
Short name T794
Test name
Test status
Simulation time 31259089 ps
CPU time 1.55 seconds
Started Apr 30 02:43:01 PM PDT 24
Finished Apr 30 02:43:03 PM PDT 24
Peak memory 217208 kb
Host smart-7c82f5fc-4ac8-4f07-9723-0e1d99634a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363163431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1363163431
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1440609999
Short name T93
Test name
Test status
Simulation time 21189874 ps
CPU time 1.11 seconds
Started Apr 30 02:42:58 PM PDT 24
Finished Apr 30 02:43:01 PM PDT 24
Peak memory 215696 kb
Host smart-b6ad2713-bdee-4f27-9ca6-ce94349231b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440609999 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1440609999
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1094485308
Short name T18
Test name
Test status
Simulation time 2007734376 ps
CPU time 8.05 seconds
Started Apr 30 02:43:03 PM PDT 24
Finished Apr 30 02:43:12 PM PDT 24
Peak memory 243756 kb
Host smart-51a74c69-a097-4d70-b469-182914a69c84
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094485308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1094485308
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2244745483
Short name T164
Test name
Test status
Simulation time 15643613 ps
CPU time 1 seconds
Started Apr 30 02:43:00 PM PDT 24
Finished Apr 30 02:43:02 PM PDT 24
Peak memory 214376 kb
Host smart-6161073e-19cb-44dd-8e6b-2f36d67c6aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244745483 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2244745483
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3777939647
Short name T450
Test name
Test status
Simulation time 366722979 ps
CPU time 4.08 seconds
Started Apr 30 02:42:57 PM PDT 24
Finished Apr 30 02:43:02 PM PDT 24
Peak memory 215116 kb
Host smart-ac28a22d-18ac-45d4-901f-e74664ba0c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777939647 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3777939647
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.151892996
Short name T469
Test name
Test status
Simulation time 354371634215 ps
CPU time 2872.11 seconds
Started Apr 30 02:42:59 PM PDT 24
Finished Apr 30 03:30:52 PM PDT 24
Peak memory 232860 kb
Host smart-ce5bb2fa-28a9-471a-bd4f-448e7a68aed6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151892996 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.151892996
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.366796322
Short name T194
Test name
Test status
Simulation time 69288155 ps
CPU time 1.21 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:44:00 PM PDT 24
Peak memory 215552 kb
Host smart-2b76d897-166c-4f55-9754-c528d90ff4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366796322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.366796322
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3694064561
Short name T611
Test name
Test status
Simulation time 22135446 ps
CPU time 0.86 seconds
Started Apr 30 02:44:05 PM PDT 24
Finished Apr 30 02:44:06 PM PDT 24
Peak memory 206700 kb
Host smart-715f2946-4594-4bd4-ad4a-f36eed310bb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694064561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3694064561
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2420336567
Short name T338
Test name
Test status
Simulation time 21012515 ps
CPU time 0.92 seconds
Started Apr 30 02:44:03 PM PDT 24
Finished Apr 30 02:44:04 PM PDT 24
Peak memory 216252 kb
Host smart-d44fe82f-6fc5-41a6-8e10-257dcccfa40a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420336567 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2420336567
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.4116622115
Short name T840
Test name
Test status
Simulation time 47822324 ps
CPU time 1.23 seconds
Started Apr 30 02:43:56 PM PDT 24
Finished Apr 30 02:43:58 PM PDT 24
Peak memory 218244 kb
Host smart-ed93ba3d-0c82-47d0-864d-2935a9c13a5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116622115 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.4116622115
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3648902504
Short name T623
Test name
Test status
Simulation time 30452296 ps
CPU time 0.9 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:43:59 PM PDT 24
Peak memory 218164 kb
Host smart-017a3142-23f3-4a29-9fa9-3c29276beb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648902504 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3648902504
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1422848558
Short name T841
Test name
Test status
Simulation time 56992175 ps
CPU time 0.96 seconds
Started Apr 30 02:43:54 PM PDT 24
Finished Apr 30 02:43:56 PM PDT 24
Peak memory 216768 kb
Host smart-e357fa7d-5b6f-4128-9e77-03903f517b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422848558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1422848558
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1913273361
Short name T694
Test name
Test status
Simulation time 36225718 ps
CPU time 0.88 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:43:58 PM PDT 24
Peak memory 215580 kb
Host smart-e0de2f7a-b4b7-4433-bfdd-a63c2f161665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913273361 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1913273361
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3991804209
Short name T823
Test name
Test status
Simulation time 166590171 ps
CPU time 0.98 seconds
Started Apr 30 02:43:51 PM PDT 24
Finished Apr 30 02:43:52 PM PDT 24
Peak memory 215144 kb
Host smart-ae1381d6-f9bc-427f-b3bf-c15760962549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991804209 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3991804209
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.882853544
Short name T647
Test name
Test status
Simulation time 305540007 ps
CPU time 5.1 seconds
Started Apr 30 02:43:59 PM PDT 24
Finished Apr 30 02:44:05 PM PDT 24
Peak memory 215180 kb
Host smart-b42ff247-339e-416a-bc97-d9a26714a936
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882853544 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.882853544
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1567437757
Short name T600
Test name
Test status
Simulation time 6744063291 ps
CPU time 80.49 seconds
Started Apr 30 02:44:04 PM PDT 24
Finished Apr 30 02:45:25 PM PDT 24
Peak memory 218076 kb
Host smart-5cc78d65-b6af-4b7e-8a76-d60579381e7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567437757 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1567437757
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.529680063
Short name T590
Test name
Test status
Simulation time 27287913 ps
CPU time 1.19 seconds
Started Apr 30 02:44:05 PM PDT 24
Finished Apr 30 02:44:07 PM PDT 24
Peak memory 215496 kb
Host smart-8fd356b3-6eab-4c0b-9ef1-22c0aaa1c8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529680063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.529680063
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.4017752246
Short name T386
Test name
Test status
Simulation time 52195220 ps
CPU time 0.93 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:44:00 PM PDT 24
Peak memory 214684 kb
Host smart-20528685-750b-4fd0-a724-d2839cb0b905
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017752246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.4017752246
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1677994669
Short name T155
Test name
Test status
Simulation time 32256583 ps
CPU time 0.78 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:44:00 PM PDT 24
Peak memory 216188 kb
Host smart-b3b643fc-3590-452f-bc0a-7d6deb15c830
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677994669 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1677994669
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2641917980
Short name T798
Test name
Test status
Simulation time 34985393 ps
CPU time 1.29 seconds
Started Apr 30 02:44:07 PM PDT 24
Finished Apr 30 02:44:09 PM PDT 24
Peak memory 216664 kb
Host smart-ed9f7f01-e630-4876-8c6e-d1133d3e4fc2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641917980 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2641917980
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3106523571
Short name T143
Test name
Test status
Simulation time 33199734 ps
CPU time 1.33 seconds
Started Apr 30 02:44:01 PM PDT 24
Finished Apr 30 02:44:03 PM PDT 24
Peak memory 215428 kb
Host smart-9c27ac0b-fdff-4a11-9028-62702951354d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106523571 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3106523571
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2874983056
Short name T836
Test name
Test status
Simulation time 44802855 ps
CPU time 1.27 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:44:00 PM PDT 24
Peak memory 216764 kb
Host smart-d7415a63-9eb3-42a4-b664-337c7c604b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874983056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2874983056
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1855368875
Short name T161
Test name
Test status
Simulation time 24536223 ps
CPU time 1.01 seconds
Started Apr 30 02:43:59 PM PDT 24
Finished Apr 30 02:44:02 PM PDT 24
Peak memory 215828 kb
Host smart-ae584a7a-aa42-47b8-9c48-afbf9fa96cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855368875 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1855368875
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1981608592
Short name T419
Test name
Test status
Simulation time 15449043 ps
CPU time 0.99 seconds
Started Apr 30 02:43:58 PM PDT 24
Finished Apr 30 02:44:00 PM PDT 24
Peak memory 215124 kb
Host smart-9276aa90-a15c-40bc-9050-1a020190c3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981608592 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1981608592
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3935112471
Short name T78
Test name
Test status
Simulation time 109992603 ps
CPU time 2.58 seconds
Started Apr 30 02:44:01 PM PDT 24
Finished Apr 30 02:44:05 PM PDT 24
Peak memory 216712 kb
Host smart-bd9cfd74-72c9-4c5b-8cf0-7b2b6e803605
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935112471 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3935112471
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3056971101
Short name T72
Test name
Test status
Simulation time 58725429653 ps
CPU time 770.44 seconds
Started Apr 30 02:44:06 PM PDT 24
Finished Apr 30 02:56:57 PM PDT 24
Peak memory 218800 kb
Host smart-1d5b1e57-028a-433f-ab17-6317b6036967
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056971101 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3056971101
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3654000335
Short name T199
Test name
Test status
Simulation time 23605200 ps
CPU time 1.18 seconds
Started Apr 30 02:43:56 PM PDT 24
Finished Apr 30 02:43:58 PM PDT 24
Peak memory 215576 kb
Host smart-710057a2-9fa8-44bb-81a6-66275ab1cd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654000335 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3654000335
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2619192677
Short name T458
Test name
Test status
Simulation time 15955021 ps
CPU time 0.92 seconds
Started Apr 30 02:44:02 PM PDT 24
Finished Apr 30 02:44:04 PM PDT 24
Peak memory 214636 kb
Host smart-35c6d809-bcc8-4bbc-a605-ae1268e8cb7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619192677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2619192677
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1565009411
Short name T198
Test name
Test status
Simulation time 67216453 ps
CPU time 0.85 seconds
Started Apr 30 02:44:00 PM PDT 24
Finished Apr 30 02:44:02 PM PDT 24
Peak memory 216224 kb
Host smart-3ba83c26-518b-4c30-8aa1-54247e4a721c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565009411 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1565009411
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3793640303
Short name T658
Test name
Test status
Simulation time 95785503 ps
CPU time 1.05 seconds
Started Apr 30 02:44:05 PM PDT 24
Finished Apr 30 02:44:06 PM PDT 24
Peak memory 217908 kb
Host smart-10f9ec82-8912-4d97-9b19-ea9e3a681268
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793640303 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3793640303
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.236801530
Short name T128
Test name
Test status
Simulation time 28796266 ps
CPU time 1.28 seconds
Started Apr 30 02:44:05 PM PDT 24
Finished Apr 30 02:44:07 PM PDT 24
Peak memory 217268 kb
Host smart-e14c71b1-30e3-4a10-8121-fec8f4edbc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236801530 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.236801530
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2717824662
Short name T454
Test name
Test status
Simulation time 114280079 ps
CPU time 1.58 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:44:00 PM PDT 24
Peak memory 219756 kb
Host smart-af5193af-63a8-4eff-ab08-c2b62a3982a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717824662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2717824662
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3998351072
Short name T98
Test name
Test status
Simulation time 34160042 ps
CPU time 0.88 seconds
Started Apr 30 02:44:05 PM PDT 24
Finished Apr 30 02:44:07 PM PDT 24
Peak memory 215680 kb
Host smart-5ddb7830-74a7-47cc-86a2-13d227ca4204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998351072 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3998351072
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.125412285
Short name T773
Test name
Test status
Simulation time 50720858 ps
CPU time 0.95 seconds
Started Apr 30 02:44:03 PM PDT 24
Finished Apr 30 02:44:04 PM PDT 24
Peak memory 215140 kb
Host smart-7c7507f8-7129-4484-843f-9a35c116b3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125412285 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.125412285
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.578575943
Short name T483
Test name
Test status
Simulation time 125126637 ps
CPU time 2.77 seconds
Started Apr 30 02:43:57 PM PDT 24
Finished Apr 30 02:44:02 PM PDT 24
Peak memory 216780 kb
Host smart-3cea5719-cc0f-4b31-a51d-41531cc2bcce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578575943 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.578575943
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.755097820
Short name T204
Test name
Test status
Simulation time 6963698829 ps
CPU time 80.87 seconds
Started Apr 30 02:44:03 PM PDT 24
Finished Apr 30 02:45:24 PM PDT 24
Peak memory 217816 kb
Host smart-955c5086-9205-464d-89b1-850e45fd0f51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755097820 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.755097820
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.3367297877
Short name T168
Test name
Test status
Simulation time 70704083 ps
CPU time 1.16 seconds
Started Apr 30 02:44:03 PM PDT 24
Finished Apr 30 02:44:05 PM PDT 24
Peak memory 215556 kb
Host smart-eb5ae102-b108-4028-915e-c493a739dce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367297877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3367297877
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1772559370
Short name T348
Test name
Test status
Simulation time 264968736 ps
CPU time 0.94 seconds
Started Apr 30 02:44:04 PM PDT 24
Finished Apr 30 02:44:06 PM PDT 24
Peak memory 215096 kb
Host smart-52774762-8222-4381-ae6a-369416f85d11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772559370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1772559370
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3754890430
Short name T51
Test name
Test status
Simulation time 13448127 ps
CPU time 0.9 seconds
Started Apr 30 02:44:06 PM PDT 24
Finished Apr 30 02:44:07 PM PDT 24
Peak memory 216248 kb
Host smart-ea621717-7f1f-49aa-aa15-df2915da4a5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754890430 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3754890430
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_err.3382005309
Short name T104
Test name
Test status
Simulation time 33487276 ps
CPU time 1.01 seconds
Started Apr 30 02:44:08 PM PDT 24
Finished Apr 30 02:44:09 PM PDT 24
Peak memory 229532 kb
Host smart-57d31500-0873-4a56-b3d0-600b84ee2a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382005309 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3382005309
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2286870235
Short name T572
Test name
Test status
Simulation time 82241236 ps
CPU time 1.15 seconds
Started Apr 30 02:44:04 PM PDT 24
Finished Apr 30 02:44:06 PM PDT 24
Peak memory 216676 kb
Host smart-3d5657bd-7bcf-46a3-a116-d54460cc82c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286870235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2286870235
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2860086357
Short name T370
Test name
Test status
Simulation time 29734232 ps
CPU time 0.94 seconds
Started Apr 30 02:44:04 PM PDT 24
Finished Apr 30 02:44:05 PM PDT 24
Peak memory 215272 kb
Host smart-4d51afc3-68f2-4b1d-a302-4ca8580a7c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860086357 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2860086357
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3420222756
Short name T732
Test name
Test status
Simulation time 17830580 ps
CPU time 1.01 seconds
Started Apr 30 02:44:12 PM PDT 24
Finished Apr 30 02:44:13 PM PDT 24
Peak memory 215180 kb
Host smart-573dcb1a-1d90-46b0-8da5-f82f4076cdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420222756 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3420222756
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3401726595
Short name T340
Test name
Test status
Simulation time 147235934 ps
CPU time 3.29 seconds
Started Apr 30 02:44:06 PM PDT 24
Finished Apr 30 02:44:10 PM PDT 24
Peak memory 216688 kb
Host smart-eb201ea4-8bff-4d49-b825-2061fc9271c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401726595 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3401726595
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1966130490
Short name T627
Test name
Test status
Simulation time 48026419576 ps
CPU time 1230.59 seconds
Started Apr 30 02:44:06 PM PDT 24
Finished Apr 30 03:04:37 PM PDT 24
Peak memory 223660 kb
Host smart-0c8ffd95-7d26-4526-bd14-6d68fa896c06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966130490 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1966130490
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.497216039
Short name T171
Test name
Test status
Simulation time 88066561 ps
CPU time 1.34 seconds
Started Apr 30 02:44:08 PM PDT 24
Finished Apr 30 02:44:09 PM PDT 24
Peak memory 215520 kb
Host smart-f0adcff0-3550-48b7-abca-3686d38d911e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497216039 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.497216039
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.871315396
Short name T57
Test name
Test status
Simulation time 11665133 ps
CPU time 0.88 seconds
Started Apr 30 02:44:07 PM PDT 24
Finished Apr 30 02:44:08 PM PDT 24
Peak memory 206356 kb
Host smart-23a2e487-f767-4c7f-afa6-01ced84ed9d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871315396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.871315396
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.4014809852
Short name T23
Test name
Test status
Simulation time 67258826 ps
CPU time 1.01 seconds
Started Apr 30 02:44:03 PM PDT 24
Finished Apr 30 02:44:05 PM PDT 24
Peak memory 217724 kb
Host smart-6787cbf2-ea78-4100-a33e-ec16e76d954d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014809852 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.4014809852
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3955932660
Short name T785
Test name
Test status
Simulation time 19114213 ps
CPU time 1.15 seconds
Started Apr 30 02:44:06 PM PDT 24
Finished Apr 30 02:44:08 PM PDT 24
Peak memory 223928 kb
Host smart-a4dd95d9-9389-4efa-a311-be53cf4daed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955932660 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3955932660
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.4099674281
Short name T440
Test name
Test status
Simulation time 47221521 ps
CPU time 1.28 seconds
Started Apr 30 02:44:02 PM PDT 24
Finished Apr 30 02:44:04 PM PDT 24
Peak memory 218232 kb
Host smart-e6d9c0a9-78d4-41cb-9b53-95a96af32e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099674281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.4099674281
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.872803506
Short name T816
Test name
Test status
Simulation time 66020255 ps
CPU time 0.97 seconds
Started Apr 30 02:44:08 PM PDT 24
Finished Apr 30 02:44:10 PM PDT 24
Peak memory 223928 kb
Host smart-1c47ba2e-b50d-45e7-9472-f8c70e1e2eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872803506 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.872803506
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.4172861527
Short name T786
Test name
Test status
Simulation time 94843090 ps
CPU time 0.93 seconds
Started Apr 30 02:44:03 PM PDT 24
Finished Apr 30 02:44:05 PM PDT 24
Peak memory 215112 kb
Host smart-b3f49755-ded5-49c7-9c67-8129adc1ce1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172861527 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.4172861527
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.682049245
Short name T339
Test name
Test status
Simulation time 586390967 ps
CPU time 3.18 seconds
Started Apr 30 02:44:04 PM PDT 24
Finished Apr 30 02:44:08 PM PDT 24
Peak memory 217016 kb
Host smart-8ca562bb-f79b-4afe-bec5-9695d573edd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682049245 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.682049245
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.4006889206
Short name T208
Test name
Test status
Simulation time 350131098748 ps
CPU time 1903.9 seconds
Started Apr 30 02:44:02 PM PDT 24
Finished Apr 30 03:15:47 PM PDT 24
Peak memory 225912 kb
Host smart-e4bce857-d7e6-448a-a0c8-e2cb23d9d484
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006889206 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.4006889206
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2278698424
Short name T142
Test name
Test status
Simulation time 28428650 ps
CPU time 1.21 seconds
Started Apr 30 02:44:11 PM PDT 24
Finished Apr 30 02:44:13 PM PDT 24
Peak memory 215564 kb
Host smart-a6a2a840-2830-4a41-8af0-af2e9e378c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278698424 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2278698424
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3665968165
Short name T312
Test name
Test status
Simulation time 39040043 ps
CPU time 0.91 seconds
Started Apr 30 02:44:13 PM PDT 24
Finished Apr 30 02:44:15 PM PDT 24
Peak memory 215100 kb
Host smart-2b1ed231-9dea-42f5-a0bf-0d2ce004e4f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665968165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3665968165
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.4185681896
Short name T179
Test name
Test status
Simulation time 33183167 ps
CPU time 0.88 seconds
Started Apr 30 02:44:02 PM PDT 24
Finished Apr 30 02:44:04 PM PDT 24
Peak memory 216068 kb
Host smart-9990dff4-95b8-4ed7-b132-0b622be0764e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185681896 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.4185681896
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3523662279
Short name T255
Test name
Test status
Simulation time 23155780 ps
CPU time 1.01 seconds
Started Apr 30 02:44:07 PM PDT 24
Finished Apr 30 02:44:09 PM PDT 24
Peak memory 216872 kb
Host smart-d0678ab1-d99b-476f-a483-3ae5c117d8e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523662279 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3523662279
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2884992654
Short name T478
Test name
Test status
Simulation time 18862775 ps
CPU time 1.03 seconds
Started Apr 30 02:44:04 PM PDT 24
Finished Apr 30 02:44:06 PM PDT 24
Peak memory 218072 kb
Host smart-fda33ade-9878-4ddd-9624-aa3a9a3ccbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884992654 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2884992654
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1335639669
Short name T285
Test name
Test status
Simulation time 53099357 ps
CPU time 1.62 seconds
Started Apr 30 02:44:02 PM PDT 24
Finished Apr 30 02:44:04 PM PDT 24
Peak memory 218188 kb
Host smart-fcee47ae-5254-4869-b8b8-103fe497ac6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335639669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1335639669
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3409258332
Short name T99
Test name
Test status
Simulation time 26468915 ps
CPU time 0.87 seconds
Started Apr 30 02:44:10 PM PDT 24
Finished Apr 30 02:44:11 PM PDT 24
Peak memory 215620 kb
Host smart-b9c05bbd-0e81-4d30-b0e0-8fd6bddde1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409258332 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3409258332
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3883895741
Short name T745
Test name
Test status
Simulation time 21615977 ps
CPU time 0.93 seconds
Started Apr 30 02:44:04 PM PDT 24
Finished Apr 30 02:44:05 PM PDT 24
Peak memory 215124 kb
Host smart-852d705f-888e-4231-b18d-4d1eb2e82917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883895741 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3883895741
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2244461527
Short name T532
Test name
Test status
Simulation time 91040707 ps
CPU time 2.25 seconds
Started Apr 30 02:44:01 PM PDT 24
Finished Apr 30 02:44:04 PM PDT 24
Peak memory 217888 kb
Host smart-4dba7815-101a-46b6-b8ac-a4d40b2f9766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244461527 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2244461527
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2284089612
Short name T764
Test name
Test status
Simulation time 205815154683 ps
CPU time 547.79 seconds
Started Apr 30 02:44:05 PM PDT 24
Finished Apr 30 02:53:14 PM PDT 24
Peak memory 220048 kb
Host smart-2e8456a5-55e8-4eda-84b6-888587b79964
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284089612 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2284089612
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1981702174
Short name T167
Test name
Test status
Simulation time 41727678 ps
CPU time 1.18 seconds
Started Apr 30 02:44:09 PM PDT 24
Finished Apr 30 02:44:10 PM PDT 24
Peak memory 215444 kb
Host smart-bc454061-42bb-485b-9d18-b74ed9bc1cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981702174 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1981702174
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4225217711
Short name T422
Test name
Test status
Simulation time 51136684 ps
CPU time 0.94 seconds
Started Apr 30 02:44:11 PM PDT 24
Finished Apr 30 02:44:13 PM PDT 24
Peak memory 206448 kb
Host smart-9f0c35ed-a4ea-4c58-af00-4973c45e0522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225217711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4225217711
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3313808967
Short name T352
Test name
Test status
Simulation time 10812840 ps
CPU time 0.91 seconds
Started Apr 30 02:44:11 PM PDT 24
Finished Apr 30 02:44:12 PM PDT 24
Peak memory 215756 kb
Host smart-7bcbb960-9ee3-4712-81e2-7b2721206cd0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313808967 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3313808967
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2843554724
Short name T717
Test name
Test status
Simulation time 38267441 ps
CPU time 1.21 seconds
Started Apr 30 02:44:09 PM PDT 24
Finished Apr 30 02:44:11 PM PDT 24
Peak memory 217876 kb
Host smart-6f53b944-075d-41a0-b9e7-67e250b7aab5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843554724 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2843554724
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3482590307
Short name T102
Test name
Test status
Simulation time 30449593 ps
CPU time 1.17 seconds
Started Apr 30 02:44:11 PM PDT 24
Finished Apr 30 02:44:13 PM PDT 24
Peak memory 219556 kb
Host smart-39df41b9-51b6-4cf7-9077-6cc8eb21e057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482590307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3482590307
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.4092021868
Short name T392
Test name
Test status
Simulation time 30843634 ps
CPU time 1.29 seconds
Started Apr 30 02:44:12 PM PDT 24
Finished Apr 30 02:44:14 PM PDT 24
Peak memory 217052 kb
Host smart-205fe584-39d0-4b32-9647-ca57880a48f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092021868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.4092021868
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3731442866
Short name T162
Test name
Test status
Simulation time 28417191 ps
CPU time 0.95 seconds
Started Apr 30 02:44:11 PM PDT 24
Finished Apr 30 02:44:13 PM PDT 24
Peak memory 215544 kb
Host smart-a4ef4dbb-1642-4396-8e10-cabae9c98276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731442866 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3731442866
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3110688859
Short name T629
Test name
Test status
Simulation time 20224021 ps
CPU time 0.97 seconds
Started Apr 30 02:44:10 PM PDT 24
Finished Apr 30 02:44:11 PM PDT 24
Peak memory 215096 kb
Host smart-220e1ca3-70b4-40cd-a1a3-b0941411a90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110688859 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3110688859
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1430399094
Short name T317
Test name
Test status
Simulation time 285983368 ps
CPU time 2.17 seconds
Started Apr 30 02:44:09 PM PDT 24
Finished Apr 30 02:44:12 PM PDT 24
Peak memory 216780 kb
Host smart-779be134-3947-4098-b6d8-0c8276f124ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430399094 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1430399094
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3575460561
Short name T207
Test name
Test status
Simulation time 37540892458 ps
CPU time 840.52 seconds
Started Apr 30 02:44:11 PM PDT 24
Finished Apr 30 02:58:12 PM PDT 24
Peak memory 218156 kb
Host smart-3429eb67-6658-4674-a3a6-75a688736828
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575460561 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3575460561
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2212739151
Short name T756
Test name
Test status
Simulation time 41385436 ps
CPU time 1.21 seconds
Started Apr 30 02:44:09 PM PDT 24
Finished Apr 30 02:44:11 PM PDT 24
Peak memory 215516 kb
Host smart-3c2140f5-d4b0-498d-839a-bb5af21d4fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212739151 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2212739151
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2495797676
Short name T708
Test name
Test status
Simulation time 180445555 ps
CPU time 0.86 seconds
Started Apr 30 02:44:09 PM PDT 24
Finished Apr 30 02:44:10 PM PDT 24
Peak memory 214544 kb
Host smart-c012e026-15c2-4920-ab3e-db69ed5ffc8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495797676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2495797676
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2277715707
Short name T187
Test name
Test status
Simulation time 27377998 ps
CPU time 0.8 seconds
Started Apr 30 02:44:08 PM PDT 24
Finished Apr 30 02:44:09 PM PDT 24
Peak memory 216044 kb
Host smart-0b9b7ff0-54ec-4c03-9c20-c836da768eec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277715707 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2277715707
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1527643740
Short name T661
Test name
Test status
Simulation time 90113001 ps
CPU time 1.08 seconds
Started Apr 30 02:44:09 PM PDT 24
Finished Apr 30 02:44:11 PM PDT 24
Peak memory 216684 kb
Host smart-64c31ddc-de2e-403c-b3f3-e7f80538bc8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527643740 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1527643740
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.654516802
Short name T668
Test name
Test status
Simulation time 32157982 ps
CPU time 0.88 seconds
Started Apr 30 02:44:09 PM PDT 24
Finished Apr 30 02:44:11 PM PDT 24
Peak memory 218116 kb
Host smart-8145be6e-33fa-41cc-97c1-cc1c24bb46ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654516802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.654516802
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1741406367
Short name T684
Test name
Test status
Simulation time 62265200 ps
CPU time 1.06 seconds
Started Apr 30 02:44:10 PM PDT 24
Finished Apr 30 02:44:12 PM PDT 24
Peak memory 216784 kb
Host smart-4168ebf4-3f11-4411-8094-539159cac715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741406367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1741406367
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2769532632
Short name T38
Test name
Test status
Simulation time 20464721 ps
CPU time 1.07 seconds
Started Apr 30 02:44:11 PM PDT 24
Finished Apr 30 02:44:13 PM PDT 24
Peak memory 215884 kb
Host smart-848343ca-f09e-4d29-b3e1-4f031a9de684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769532632 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2769532632
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2891002831
Short name T455
Test name
Test status
Simulation time 23255734 ps
CPU time 1.04 seconds
Started Apr 30 02:44:08 PM PDT 24
Finished Apr 30 02:44:09 PM PDT 24
Peak memory 215164 kb
Host smart-f9030479-5c2f-40b6-be19-6687fa8ab015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891002831 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2891002831
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1445481203
Short name T715
Test name
Test status
Simulation time 123572644 ps
CPU time 1.98 seconds
Started Apr 30 02:44:13 PM PDT 24
Finished Apr 30 02:44:16 PM PDT 24
Peak memory 216876 kb
Host smart-6a9bdce5-b518-41ab-a6cf-36a21fce6beb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445481203 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1445481203
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2537046073
Short name T200
Test name
Test status
Simulation time 88886712243 ps
CPU time 1920.9 seconds
Started Apr 30 02:44:09 PM PDT 24
Finished Apr 30 03:16:11 PM PDT 24
Peak memory 225524 kb
Host smart-eb545079-1672-4a52-8186-8ca00b4e5b96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537046073 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2537046073
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert_test.456108371
Short name T383
Test name
Test status
Simulation time 23256765 ps
CPU time 1.13 seconds
Started Apr 30 02:44:11 PM PDT 24
Finished Apr 30 02:44:13 PM PDT 24
Peak memory 214816 kb
Host smart-2233b2ee-227f-47bb-a2cf-aa3c2daec45c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456108371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.456108371
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.479653963
Short name T150
Test name
Test status
Simulation time 34702297 ps
CPU time 0.81 seconds
Started Apr 30 02:44:14 PM PDT 24
Finished Apr 30 02:44:15 PM PDT 24
Peak memory 216056 kb
Host smart-3c747591-a012-40ad-a88f-02b555467314
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479653963 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.479653963
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1266009064
Short name T436
Test name
Test status
Simulation time 38767607 ps
CPU time 1.26 seconds
Started Apr 30 02:44:08 PM PDT 24
Finished Apr 30 02:44:10 PM PDT 24
Peak memory 216808 kb
Host smart-0a668c2e-0b1d-49f3-8156-0fba721f8070
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266009064 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1266009064
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_genbits.2933936781
Short name T372
Test name
Test status
Simulation time 32618520 ps
CPU time 1.24 seconds
Started Apr 30 02:44:11 PM PDT 24
Finished Apr 30 02:44:13 PM PDT 24
Peak memory 216756 kb
Host smart-f396eea6-73cd-4dda-9c51-a0088743e25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933936781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2933936781
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3212175771
Short name T488
Test name
Test status
Simulation time 24164897 ps
CPU time 0.95 seconds
Started Apr 30 02:44:09 PM PDT 24
Finished Apr 30 02:44:11 PM PDT 24
Peak memory 215412 kb
Host smart-61483257-8321-4f54-80bf-65345837a62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212175771 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3212175771
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2109797290
Short name T382
Test name
Test status
Simulation time 37920488 ps
CPU time 0.91 seconds
Started Apr 30 02:44:07 PM PDT 24
Finished Apr 30 02:44:08 PM PDT 24
Peak memory 215184 kb
Host smart-81e959e8-72bd-42c2-8ccd-bd5e8c6c0584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109797290 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2109797290
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2844548564
Short name T692
Test name
Test status
Simulation time 95435099 ps
CPU time 2.22 seconds
Started Apr 30 02:44:07 PM PDT 24
Finished Apr 30 02:44:10 PM PDT 24
Peak memory 215192 kb
Host smart-772b0624-d7da-4ba3-9ede-6a4c72e3e1fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844548564 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2844548564
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1683828999
Short name T619
Test name
Test status
Simulation time 195222869699 ps
CPU time 517.19 seconds
Started Apr 30 02:44:09 PM PDT 24
Finished Apr 30 02:52:47 PM PDT 24
Peak memory 219436 kb
Host smart-4dda5405-4e67-4baf-984d-910663460445
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683828999 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1683828999
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2534515822
Short name T141
Test name
Test status
Simulation time 26449241 ps
CPU time 1.24 seconds
Started Apr 30 02:44:11 PM PDT 24
Finished Apr 30 02:44:13 PM PDT 24
Peak memory 215472 kb
Host smart-bce3b2a0-fb84-4657-b8e2-30df02fea46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534515822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2534515822
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.45188275
Short name T426
Test name
Test status
Simulation time 20444881 ps
CPU time 1.01 seconds
Started Apr 30 02:44:16 PM PDT 24
Finished Apr 30 02:44:18 PM PDT 24
Peak memory 206500 kb
Host smart-dd27a6c9-de29-4ebe-bcda-b293a09726b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45188275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.45188275
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2068341946
Short name T193
Test name
Test status
Simulation time 27691122 ps
CPU time 0.83 seconds
Started Apr 30 02:44:18 PM PDT 24
Finished Apr 30 02:44:19 PM PDT 24
Peak memory 215204 kb
Host smart-662d27a7-56e8-4d97-9ff2-bf73b71c9d78
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068341946 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2068341946
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.903356186
Short name T130
Test name
Test status
Simulation time 41723473 ps
CPU time 1.05 seconds
Started Apr 30 02:44:17 PM PDT 24
Finished Apr 30 02:44:18 PM PDT 24
Peak memory 216564 kb
Host smart-6a15d693-2087-42b9-910c-398d6a7f77d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903356186 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.903356186
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.53377292
Short name T379
Test name
Test status
Simulation time 18768027 ps
CPU time 1.15 seconds
Started Apr 30 02:44:08 PM PDT 24
Finished Apr 30 02:44:10 PM PDT 24
Peak memory 223876 kb
Host smart-48e04d4b-836f-4d05-a0f6-0c70ab4dac16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53377292 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.53377292
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2877042903
Short name T334
Test name
Test status
Simulation time 264011852 ps
CPU time 3.35 seconds
Started Apr 30 02:44:10 PM PDT 24
Finished Apr 30 02:44:14 PM PDT 24
Peak memory 219884 kb
Host smart-b07ec0f8-a862-4cfa-a997-81129370f724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877042903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2877042903
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1084339511
Short name T722
Test name
Test status
Simulation time 23055669 ps
CPU time 1.13 seconds
Started Apr 30 02:44:07 PM PDT 24
Finished Apr 30 02:44:09 PM PDT 24
Peak memory 215472 kb
Host smart-2847f49d-486c-4781-bd83-a4b8616be612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084339511 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1084339511
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1266658620
Short name T584
Test name
Test status
Simulation time 17583588 ps
CPU time 1 seconds
Started Apr 30 02:44:08 PM PDT 24
Finished Apr 30 02:44:10 PM PDT 24
Peak memory 215136 kb
Host smart-616c1e8f-c648-4bc8-b0b0-153bf3ee1b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266658620 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1266658620
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1265176624
Short name T754
Test name
Test status
Simulation time 355155997 ps
CPU time 6.92 seconds
Started Apr 30 02:44:09 PM PDT 24
Finished Apr 30 02:44:16 PM PDT 24
Peak memory 220088 kb
Host smart-cc52328c-31a8-40e3-af47-6118e7b77779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265176624 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1265176624
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.116843647
Short name T202
Test name
Test status
Simulation time 78635738916 ps
CPU time 1932.32 seconds
Started Apr 30 02:44:10 PM PDT 24
Finished Apr 30 03:16:24 PM PDT 24
Peak memory 229016 kb
Host smart-77c3ecc2-4a4e-4417-aa65-d437015edd67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116843647 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.116843647
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.300636629
Short name T832
Test name
Test status
Simulation time 84581366 ps
CPU time 1.3 seconds
Started Apr 30 02:43:03 PM PDT 24
Finished Apr 30 02:43:06 PM PDT 24
Peak memory 215540 kb
Host smart-531bbcf2-9053-49f4-ae63-d2d6af7d822c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300636629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.300636629
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2302676924
Short name T787
Test name
Test status
Simulation time 36474779 ps
CPU time 1.02 seconds
Started Apr 30 02:43:02 PM PDT 24
Finished Apr 30 02:43:05 PM PDT 24
Peak memory 206568 kb
Host smart-e32ee29d-11ff-4a64-8baa-211db90c2fb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302676924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2302676924
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3258639684
Short name T184
Test name
Test status
Simulation time 130662063 ps
CPU time 0.88 seconds
Started Apr 30 02:43:01 PM PDT 24
Finished Apr 30 02:43:03 PM PDT 24
Peak memory 215988 kb
Host smart-98bf3f4d-e7fb-4440-a2ad-73cb81daa1df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258639684 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3258639684
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1044408269
Short name T400
Test name
Test status
Simulation time 43984849 ps
CPU time 1.25 seconds
Started Apr 30 02:43:04 PM PDT 24
Finished Apr 30 02:43:07 PM PDT 24
Peak memory 216592 kb
Host smart-51f45149-5c61-4a4e-9eae-f610e5314213
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044408269 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1044408269
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.24772695
Short name T61
Test name
Test status
Simulation time 36009427 ps
CPU time 0.96 seconds
Started Apr 30 02:43:02 PM PDT 24
Finished Apr 30 02:43:04 PM PDT 24
Peak memory 223688 kb
Host smart-7b80b15b-bb2b-4deb-8f7f-0c87affb50a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24772695 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.24772695
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1010522955
Short name T561
Test name
Test status
Simulation time 74994975 ps
CPU time 2.26 seconds
Started Apr 30 02:43:01 PM PDT 24
Finished Apr 30 02:43:04 PM PDT 24
Peak memory 218436 kb
Host smart-5bf90e74-4e77-457b-b501-91f9375f715c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010522955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1010522955
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1338619696
Short name T641
Test name
Test status
Simulation time 40788675 ps
CPU time 0.93 seconds
Started Apr 30 02:43:02 PM PDT 24
Finished Apr 30 02:43:04 PM PDT 24
Peak memory 215356 kb
Host smart-d91bca43-66c1-4564-8138-a832b59743b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338619696 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1338619696
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3182539463
Short name T268
Test name
Test status
Simulation time 19231803 ps
CPU time 1.09 seconds
Started Apr 30 02:43:06 PM PDT 24
Finished Apr 30 02:43:08 PM PDT 24
Peak memory 206940 kb
Host smart-a63983a6-268c-4958-b352-2cb548abaf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182539463 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3182539463
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.546416945
Short name T614
Test name
Test status
Simulation time 46022440 ps
CPU time 0.89 seconds
Started Apr 30 02:43:03 PM PDT 24
Finished Apr 30 02:43:05 PM PDT 24
Peak memory 215108 kb
Host smart-b124e8bd-35d4-45bf-9cc9-f27146510573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546416945 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.546416945
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2899836019
Short name T212
Test name
Test status
Simulation time 35533231 ps
CPU time 1.3 seconds
Started Apr 30 02:43:05 PM PDT 24
Finished Apr 30 02:43:08 PM PDT 24
Peak memory 215104 kb
Host smart-ac53fb9a-04b5-4e1c-a3c9-ab7337558905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899836019 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2899836019
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1505878930
Short name T657
Test name
Test status
Simulation time 122869679115 ps
CPU time 2373.82 seconds
Started Apr 30 02:43:04 PM PDT 24
Finished Apr 30 03:22:40 PM PDT 24
Peak memory 227848 kb
Host smart-95489cf5-90d4-4ad8-a38d-5901a2ad810c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505878930 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1505878930
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.728784451
Short name T176
Test name
Test status
Simulation time 23843072 ps
CPU time 1.3 seconds
Started Apr 30 02:44:17 PM PDT 24
Finished Apr 30 02:44:19 PM PDT 24
Peak memory 223900 kb
Host smart-feff1f72-4528-4427-b9ba-60f0841fb262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728784451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.728784451
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1997280853
Short name T27
Test name
Test status
Simulation time 37448231 ps
CPU time 1.33 seconds
Started Apr 30 02:44:19 PM PDT 24
Finished Apr 30 02:44:21 PM PDT 24
Peak memory 216916 kb
Host smart-962a9621-4949-40b6-ba03-c3d57379d5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997280853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1997280853
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.613726116
Short name T173
Test name
Test status
Simulation time 60254893 ps
CPU time 1.04 seconds
Started Apr 30 02:44:14 PM PDT 24
Finished Apr 30 02:44:16 PM PDT 24
Peak memory 218556 kb
Host smart-4302d910-6c0f-4fae-8e1d-1a8aa44b102c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613726116 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.613726116
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1401385283
Short name T364
Test name
Test status
Simulation time 79338219 ps
CPU time 2.54 seconds
Started Apr 30 02:44:11 PM PDT 24
Finished Apr 30 02:44:14 PM PDT 24
Peak memory 218172 kb
Host smart-b5d69f5b-25d6-4b4b-9249-2b223b1293b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401385283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1401385283
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.2455332247
Short name T797
Test name
Test status
Simulation time 26931957 ps
CPU time 0.86 seconds
Started Apr 30 02:44:17 PM PDT 24
Finished Apr 30 02:44:18 PM PDT 24
Peak memory 217960 kb
Host smart-b34371e9-7c4e-4dab-935e-489378941134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455332247 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2455332247
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2157939704
Short name T480
Test name
Test status
Simulation time 55466554 ps
CPU time 1.7 seconds
Started Apr 30 02:44:14 PM PDT 24
Finished Apr 30 02:44:16 PM PDT 24
Peak memory 217972 kb
Host smart-8d705192-d2f6-4077-b94a-790147f96bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157939704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2157939704
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.3037076189
Short name T181
Test name
Test status
Simulation time 27445584 ps
CPU time 1.07 seconds
Started Apr 30 02:44:18 PM PDT 24
Finished Apr 30 02:44:19 PM PDT 24
Peak memory 219744 kb
Host smart-9263fd11-5ce1-44ef-97d3-753b51df2a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037076189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3037076189
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1763661208
Short name T76
Test name
Test status
Simulation time 77864735 ps
CPU time 1.08 seconds
Started Apr 30 02:44:16 PM PDT 24
Finished Apr 30 02:44:18 PM PDT 24
Peak memory 216744 kb
Host smart-d7a46b83-7319-4e4c-b75e-7100b7436908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763661208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1763661208
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_genbits.2819328806
Short name T608
Test name
Test status
Simulation time 53042177 ps
CPU time 1.15 seconds
Started Apr 30 02:44:12 PM PDT 24
Finished Apr 30 02:44:14 PM PDT 24
Peak memory 216800 kb
Host smart-a0fc851b-252a-4e2a-adfe-68dc89428cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819328806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2819328806
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.1506716505
Short name T131
Test name
Test status
Simulation time 19174450 ps
CPU time 1.15 seconds
Started Apr 30 02:44:19 PM PDT 24
Finished Apr 30 02:44:20 PM PDT 24
Peak memory 223324 kb
Host smart-646dd43b-5448-4229-9a20-f3209f9eb3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506716505 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1506716505
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3004928620
Short name T310
Test name
Test status
Simulation time 18154874 ps
CPU time 1.15 seconds
Started Apr 30 02:44:12 PM PDT 24
Finished Apr 30 02:44:14 PM PDT 24
Peak memory 219460 kb
Host smart-50d63e8c-7836-4332-aa3a-dd3477e2cc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004928620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3004928620
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.705284140
Short name T411
Test name
Test status
Simulation time 29704329 ps
CPU time 1.03 seconds
Started Apr 30 02:44:13 PM PDT 24
Finished Apr 30 02:44:15 PM PDT 24
Peak memory 219672 kb
Host smart-fbe49b98-8111-44d8-964f-5499fe39c272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705284140 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.705284140
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1557995837
Short name T528
Test name
Test status
Simulation time 57103079 ps
CPU time 1.25 seconds
Started Apr 30 02:44:17 PM PDT 24
Finished Apr 30 02:44:18 PM PDT 24
Peak memory 218072 kb
Host smart-7d7a893d-f4b0-4c89-81c1-52757f425cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557995837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1557995837
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.3265475627
Short name T100
Test name
Test status
Simulation time 67230822 ps
CPU time 1.15 seconds
Started Apr 30 02:44:16 PM PDT 24
Finished Apr 30 02:44:18 PM PDT 24
Peak memory 229516 kb
Host smart-6d09e1f9-8d72-4d22-ae28-672994170f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265475627 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3265475627
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2394020143
Short name T791
Test name
Test status
Simulation time 89767084 ps
CPU time 1.15 seconds
Started Apr 30 02:44:12 PM PDT 24
Finished Apr 30 02:44:14 PM PDT 24
Peak memory 216924 kb
Host smart-d3553a16-08f6-4558-8dc2-e308aacc1d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394020143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2394020143
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.205613524
Short name T489
Test name
Test status
Simulation time 21464810 ps
CPU time 1.16 seconds
Started Apr 30 02:44:16 PM PDT 24
Finished Apr 30 02:44:18 PM PDT 24
Peak memory 218108 kb
Host smart-cea7a050-ab59-49e8-af6e-0f7abcb50052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205613524 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.205613524
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2353082047
Short name T358
Test name
Test status
Simulation time 92193389 ps
CPU time 2.96 seconds
Started Apr 30 02:44:18 PM PDT 24
Finished Apr 30 02:44:21 PM PDT 24
Peak memory 217064 kb
Host smart-ec781ce4-9a5c-492a-8e22-ac4f4aa2645a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353082047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2353082047
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.3555886973
Short name T415
Test name
Test status
Simulation time 20650643 ps
CPU time 1.14 seconds
Started Apr 30 02:44:16 PM PDT 24
Finished Apr 30 02:44:17 PM PDT 24
Peak memory 223500 kb
Host smart-96b8f0ed-0729-4b39-a7bb-a069b0f25061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555886973 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3555886973
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3327967206
Short name T691
Test name
Test status
Simulation time 29850404 ps
CPU time 1.31 seconds
Started Apr 30 02:44:20 PM PDT 24
Finished Apr 30 02:44:22 PM PDT 24
Peak memory 218124 kb
Host smart-de42b614-d76f-4cab-8546-758c7cce58d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327967206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3327967206
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3845088012
Short name T463
Test name
Test status
Simulation time 32450294 ps
CPU time 1.38 seconds
Started Apr 30 02:43:04 PM PDT 24
Finished Apr 30 02:43:07 PM PDT 24
Peak memory 215552 kb
Host smart-0415dc72-7da4-477a-a0f0-b76a93f025be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845088012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3845088012
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1341749985
Short name T567
Test name
Test status
Simulation time 71285958 ps
CPU time 0.89 seconds
Started Apr 30 02:43:04 PM PDT 24
Finished Apr 30 02:43:07 PM PDT 24
Peak memory 214752 kb
Host smart-7d7fc120-f1c4-453e-aabf-dbde41f0fda4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341749985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1341749985
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2898958346
Short name T673
Test name
Test status
Simulation time 10424240 ps
CPU time 0.86 seconds
Started Apr 30 02:43:03 PM PDT 24
Finished Apr 30 02:43:05 PM PDT 24
Peak memory 215200 kb
Host smart-73a2bd71-393f-4496-be2a-83e576ac13af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898958346 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2898958346
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2890762744
Short name T256
Test name
Test status
Simulation time 35502380 ps
CPU time 1.19 seconds
Started Apr 30 02:43:08 PM PDT 24
Finished Apr 30 02:43:10 PM PDT 24
Peak memory 217972 kb
Host smart-2135feea-202f-483a-b144-ef246ffe28ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890762744 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2890762744
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1200037791
Short name T62
Test name
Test status
Simulation time 43674098 ps
CPU time 1.06 seconds
Started Apr 30 02:43:08 PM PDT 24
Finished Apr 30 02:43:09 PM PDT 24
Peak memory 229412 kb
Host smart-c1f892f2-1337-4681-a365-8750600b3d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200037791 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1200037791
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1459692082
Short name T672
Test name
Test status
Simulation time 272065185 ps
CPU time 1.65 seconds
Started Apr 30 02:43:07 PM PDT 24
Finished Apr 30 02:43:09 PM PDT 24
Peak memory 218604 kb
Host smart-c3d2e6d6-3018-4c11-a3d1-6142ec64f240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459692082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1459692082
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3754329823
Short name T792
Test name
Test status
Simulation time 28400734 ps
CPU time 0.94 seconds
Started Apr 30 02:43:03 PM PDT 24
Finished Apr 30 02:43:05 PM PDT 24
Peak memory 215404 kb
Host smart-33859a16-3f49-4059-91df-c347a65bb103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754329823 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3754329823
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.3488014113
Short name T626
Test name
Test status
Simulation time 17590696 ps
CPU time 1.04 seconds
Started Apr 30 02:43:04 PM PDT 24
Finished Apr 30 02:43:06 PM PDT 24
Peak memory 215132 kb
Host smart-f5515ee3-29cc-4ff5-af46-066244c4c372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488014113 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3488014113
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3369273628
Short name T714
Test name
Test status
Simulation time 272897463 ps
CPU time 3.56 seconds
Started Apr 30 02:43:03 PM PDT 24
Finished Apr 30 02:43:08 PM PDT 24
Peak memory 219852 kb
Host smart-c2b1c37a-e051-46d4-93ba-a5e0ebbe500f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369273628 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3369273628
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2706045664
Short name T666
Test name
Test status
Simulation time 43300196385 ps
CPU time 1153.74 seconds
Started Apr 30 02:43:02 PM PDT 24
Finished Apr 30 03:02:17 PM PDT 24
Peak memory 221388 kb
Host smart-a4afcd0b-4b90-4d8d-9a4e-7f135a858b0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706045664 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2706045664
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.418509905
Short name T96
Test name
Test status
Simulation time 36841913 ps
CPU time 1.4 seconds
Started Apr 30 02:44:14 PM PDT 24
Finished Apr 30 02:44:16 PM PDT 24
Peak memory 219520 kb
Host smart-5bb3f61a-bceb-4024-bb26-38a33a936fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418509905 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.418509905
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1718467712
Short name T727
Test name
Test status
Simulation time 40368953 ps
CPU time 1.55 seconds
Started Apr 30 02:44:17 PM PDT 24
Finished Apr 30 02:44:19 PM PDT 24
Peak memory 215112 kb
Host smart-e94cd88b-9ae0-4737-a650-e624731db636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718467712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1718467712
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.3363659981
Short name T111
Test name
Test status
Simulation time 38605828 ps
CPU time 1.17 seconds
Started Apr 30 02:44:16 PM PDT 24
Finished Apr 30 02:44:17 PM PDT 24
Peak memory 229316 kb
Host smart-02f214cd-d0b0-4918-975f-27b2c8431ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363659981 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3363659981
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2452581230
Short name T606
Test name
Test status
Simulation time 34270640 ps
CPU time 1.44 seconds
Started Apr 30 02:44:13 PM PDT 24
Finished Apr 30 02:44:15 PM PDT 24
Peak memory 218120 kb
Host smart-e6ab4470-8469-4bda-8b39-d43ce9851943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452581230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2452581230
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.1732389655
Short name T631
Test name
Test status
Simulation time 87848313 ps
CPU time 1.14 seconds
Started Apr 30 02:44:13 PM PDT 24
Finished Apr 30 02:44:15 PM PDT 24
Peak memory 224876 kb
Host smart-78975302-f8bc-4e74-8ca3-d733a4e2371f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732389655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1732389655
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3096410511
Short name T762
Test name
Test status
Simulation time 49553320 ps
CPU time 1.37 seconds
Started Apr 30 02:44:12 PM PDT 24
Finished Apr 30 02:44:14 PM PDT 24
Peak memory 218144 kb
Host smart-5270c923-2510-4171-9367-840bd3f3004e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096410511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3096410511
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.675903433
Short name T404
Test name
Test status
Simulation time 31419430 ps
CPU time 0.93 seconds
Started Apr 30 02:44:19 PM PDT 24
Finished Apr 30 02:44:20 PM PDT 24
Peak memory 217704 kb
Host smart-b51c7125-cf56-416a-810c-d1bd0659e5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675903433 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.675903433
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3278386211
Short name T677
Test name
Test status
Simulation time 89905145 ps
CPU time 1.1 seconds
Started Apr 30 02:44:22 PM PDT 24
Finished Apr 30 02:44:23 PM PDT 24
Peak memory 216824 kb
Host smart-5f145aba-86a3-48b4-a631-b4b14484d15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278386211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3278386211
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.2909875801
Short name T365
Test name
Test status
Simulation time 27049100 ps
CPU time 0.87 seconds
Started Apr 30 02:44:17 PM PDT 24
Finished Apr 30 02:44:18 PM PDT 24
Peak memory 218024 kb
Host smart-71e78806-3afb-4ef4-a4a7-fa0f21f266d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909875801 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2909875801
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/65.edn_err.746739411
Short name T114
Test name
Test status
Simulation time 25529322 ps
CPU time 1.38 seconds
Started Apr 30 02:44:12 PM PDT 24
Finished Apr 30 02:44:14 PM PDT 24
Peak memory 229596 kb
Host smart-0aa4dda4-eda6-4c62-b90c-b1eedb6f134f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746739411 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.746739411
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1530857623
Short name T418
Test name
Test status
Simulation time 44042131 ps
CPU time 1.16 seconds
Started Apr 30 02:44:16 PM PDT 24
Finished Apr 30 02:44:17 PM PDT 24
Peak memory 216620 kb
Host smart-8621073c-be59-49f2-bdab-beefeec73ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530857623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1530857623
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.747862578
Short name T153
Test name
Test status
Simulation time 20224233 ps
CPU time 1.1 seconds
Started Apr 30 02:44:21 PM PDT 24
Finished Apr 30 02:44:23 PM PDT 24
Peak memory 223796 kb
Host smart-f1037b1c-2bfd-421d-8ac8-2213bf117fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747862578 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.747862578
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.4052479982
Short name T490
Test name
Test status
Simulation time 85869285 ps
CPU time 1.23 seconds
Started Apr 30 02:44:15 PM PDT 24
Finished Apr 30 02:44:16 PM PDT 24
Peak memory 218372 kb
Host smart-adcf96ae-e3b6-4798-ad23-0f68a35bf369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052479982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.4052479982
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.3013422341
Short name T110
Test name
Test status
Simulation time 38564131 ps
CPU time 1.16 seconds
Started Apr 30 02:44:24 PM PDT 24
Finished Apr 30 02:44:25 PM PDT 24
Peak memory 217240 kb
Host smart-10fb8585-1c9c-4525-b3f3-248150f8774f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013422341 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3013422341
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3509905525
Short name T699
Test name
Test status
Simulation time 48209851 ps
CPU time 1.58 seconds
Started Apr 30 02:44:15 PM PDT 24
Finished Apr 30 02:44:17 PM PDT 24
Peak memory 217992 kb
Host smart-31763cfb-b511-4380-b8f0-abd9202d1e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509905525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3509905525
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.4137854152
Short name T384
Test name
Test status
Simulation time 24628557 ps
CPU time 1.05 seconds
Started Apr 30 02:44:28 PM PDT 24
Finished Apr 30 02:44:29 PM PDT 24
Peak memory 223892 kb
Host smart-22f1b228-7d19-4b37-ba80-8cb22bb8b61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137854152 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.4137854152
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.605788171
Short name T324
Test name
Test status
Simulation time 106445260 ps
CPU time 1.6 seconds
Started Apr 30 02:44:23 PM PDT 24
Finished Apr 30 02:44:25 PM PDT 24
Peak memory 218088 kb
Host smart-fcbafcf7-c877-40c3-ab7a-2afab0be6746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605788171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.605788171
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.128315228
Short name T136
Test name
Test status
Simulation time 27275604 ps
CPU time 0.88 seconds
Started Apr 30 02:44:26 PM PDT 24
Finished Apr 30 02:44:27 PM PDT 24
Peak memory 218256 kb
Host smart-442531eb-7e83-42ad-be2f-b2c8207217a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128315228 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.128315228
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1934919169
Short name T831
Test name
Test status
Simulation time 218140881 ps
CPU time 1.66 seconds
Started Apr 30 02:44:24 PM PDT 24
Finished Apr 30 02:44:26 PM PDT 24
Peak memory 218512 kb
Host smart-4819700a-4e57-4b10-8fac-49d1a2605f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934919169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1934919169
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1333518450
Short name T266
Test name
Test status
Simulation time 106498938 ps
CPU time 1.37 seconds
Started Apr 30 02:43:03 PM PDT 24
Finished Apr 30 02:43:06 PM PDT 24
Peak memory 215560 kb
Host smart-81cf73f3-1b9c-420c-ba54-0692e9f92512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333518450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1333518450
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.922212127
Short name T337
Test name
Test status
Simulation time 47290975 ps
CPU time 0.9 seconds
Started Apr 30 02:43:06 PM PDT 24
Finished Apr 30 02:43:08 PM PDT 24
Peak memory 214680 kb
Host smart-8d4082d8-6628-4fb4-bb9f-82bf9cc2c639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922212127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.922212127
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3107673303
Short name T557
Test name
Test status
Simulation time 20703394 ps
CPU time 0.96 seconds
Started Apr 30 02:43:02 PM PDT 24
Finished Apr 30 02:43:05 PM PDT 24
Peak memory 215396 kb
Host smart-0fff146d-a7b6-4019-8088-abebd1a01760
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107673303 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3107673303
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2785657099
Short name T679
Test name
Test status
Simulation time 151673298 ps
CPU time 1.08 seconds
Started Apr 30 02:43:07 PM PDT 24
Finished Apr 30 02:43:09 PM PDT 24
Peak memory 216664 kb
Host smart-5a91ce2c-cb53-43c5-bec8-1792781f119f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785657099 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2785657099
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3298463718
Short name T59
Test name
Test status
Simulation time 29265551 ps
CPU time 1.38 seconds
Started Apr 30 02:43:02 PM PDT 24
Finished Apr 30 02:43:05 PM PDT 24
Peak memory 225424 kb
Host smart-bf9422d7-bfed-4dbc-b412-e7c332c5736a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298463718 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3298463718
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3791102744
Short name T680
Test name
Test status
Simulation time 52431235 ps
CPU time 1.36 seconds
Started Apr 30 02:43:06 PM PDT 24
Finished Apr 30 02:43:08 PM PDT 24
Peak memory 218244 kb
Host smart-a79533c8-ee10-499c-ba06-ac2ddff03f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791102744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3791102744
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3075555736
Short name T433
Test name
Test status
Simulation time 25763269 ps
CPU time 1.1 seconds
Started Apr 30 02:43:08 PM PDT 24
Finished Apr 30 02:43:09 PM PDT 24
Peak memory 223836 kb
Host smart-618ce85f-c83c-4690-8952-29c2e5cf33ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075555736 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3075555736
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.4201662392
Short name T261
Test name
Test status
Simulation time 46107816 ps
CPU time 0.97 seconds
Started Apr 30 02:43:05 PM PDT 24
Finished Apr 30 02:43:07 PM PDT 24
Peak memory 205632 kb
Host smart-21fe3e90-8d56-4683-ad33-e16e039702f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201662392 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.4201662392
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.86569460
Short name T482
Test name
Test status
Simulation time 18393089 ps
CPU time 1.03 seconds
Started Apr 30 02:43:03 PM PDT 24
Finished Apr 30 02:43:06 PM PDT 24
Peak memory 207000 kb
Host smart-bc93258e-6bfa-4126-b593-c66db2444421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86569460 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.86569460
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2320292214
Short name T716
Test name
Test status
Simulation time 156975525 ps
CPU time 2.67 seconds
Started Apr 30 02:43:03 PM PDT 24
Finished Apr 30 02:43:07 PM PDT 24
Peak memory 217004 kb
Host smart-2ee52e10-4ee5-4e73-8d14-0b6ff8782bd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320292214 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2320292214
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1031531466
Short name T470
Test name
Test status
Simulation time 112793454434 ps
CPU time 1034.09 seconds
Started Apr 30 02:43:03 PM PDT 24
Finished Apr 30 03:00:18 PM PDT 24
Peak memory 223456 kb
Host smart-f796f93f-d14b-415a-9be9-421c12a94614
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031531466 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1031531466
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.706117756
Short name T6
Test name
Test status
Simulation time 84302138 ps
CPU time 1.02 seconds
Started Apr 30 02:44:29 PM PDT 24
Finished Apr 30 02:44:31 PM PDT 24
Peak memory 220548 kb
Host smart-ad9b0b77-0b76-49a9-96ba-718718cb2093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706117756 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.706117756
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.889849706
Short name T446
Test name
Test status
Simulation time 47303532 ps
CPU time 1.61 seconds
Started Apr 30 02:44:28 PM PDT 24
Finished Apr 30 02:44:30 PM PDT 24
Peak memory 215140 kb
Host smart-7283e102-2043-44bd-ad7b-8bc70803e81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889849706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.889849706
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.3933540423
Short name T607
Test name
Test status
Simulation time 27321902 ps
CPU time 1.13 seconds
Started Apr 30 02:44:27 PM PDT 24
Finished Apr 30 02:44:28 PM PDT 24
Peak memory 218236 kb
Host smart-d4b640c6-429d-4086-8285-196e6e03102b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933540423 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3933540423
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.969621190
Short name T354
Test name
Test status
Simulation time 56653967 ps
CPU time 1.03 seconds
Started Apr 30 02:44:27 PM PDT 24
Finished Apr 30 02:44:29 PM PDT 24
Peak memory 216904 kb
Host smart-ba32b7dd-98b7-425c-b9bf-3fc3d5602bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969621190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.969621190
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.1076303677
Short name T683
Test name
Test status
Simulation time 20393466 ps
CPU time 1.05 seconds
Started Apr 30 02:44:22 PM PDT 24
Finished Apr 30 02:44:24 PM PDT 24
Peak memory 218384 kb
Host smart-d89db9b5-5843-46c8-b337-cc2de1eb3b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076303677 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1076303677
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2068203940
Short name T373
Test name
Test status
Simulation time 50840814 ps
CPU time 1.78 seconds
Started Apr 30 02:44:21 PM PDT 24
Finished Apr 30 02:44:23 PM PDT 24
Peak memory 218180 kb
Host smart-b6fcd541-b252-4150-9559-2b03c3ba2f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068203940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2068203940
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.2563915419
Short name T101
Test name
Test status
Simulation time 22082409 ps
CPU time 1.18 seconds
Started Apr 30 02:44:20 PM PDT 24
Finished Apr 30 02:44:22 PM PDT 24
Peak memory 219376 kb
Host smart-ac91a8cd-354a-4b16-ae36-bf204ee28f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563915419 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2563915419
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1414517854
Short name T554
Test name
Test status
Simulation time 54506658 ps
CPU time 1.31 seconds
Started Apr 30 02:44:27 PM PDT 24
Finished Apr 30 02:44:29 PM PDT 24
Peak memory 216812 kb
Host smart-182c92ea-5430-4c13-9332-5da4a5d09622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414517854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1414517854
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.1231470832
Short name T121
Test name
Test status
Simulation time 26894085 ps
CPU time 0.96 seconds
Started Apr 30 02:44:23 PM PDT 24
Finished Apr 30 02:44:25 PM PDT 24
Peak memory 218464 kb
Host smart-3f565941-be2d-418e-a2ff-9cc8adbceff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231470832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1231470832
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3845422657
Short name T539
Test name
Test status
Simulation time 33879030 ps
CPU time 1.18 seconds
Started Apr 30 02:44:23 PM PDT 24
Finished Apr 30 02:44:24 PM PDT 24
Peak memory 218208 kb
Host smart-de462449-5b89-4cc4-b2cb-adc3c8ed26f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845422657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3845422657
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.2237946075
Short name T618
Test name
Test status
Simulation time 22678731 ps
CPU time 0.93 seconds
Started Apr 30 02:44:30 PM PDT 24
Finished Apr 30 02:44:32 PM PDT 24
Peak memory 218140 kb
Host smart-1239c511-9665-4dc2-99ec-c1457c4b2a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237946075 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2237946075
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3819027573
Short name T22
Test name
Test status
Simulation time 257023558 ps
CPU time 3.15 seconds
Started Apr 30 02:44:21 PM PDT 24
Finished Apr 30 02:44:24 PM PDT 24
Peak memory 219296 kb
Host smart-644c94b0-8a1b-452d-8dbd-176fc196ee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819027573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3819027573
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.128835453
Short name T498
Test name
Test status
Simulation time 30018809 ps
CPU time 1.35 seconds
Started Apr 30 02:44:22 PM PDT 24
Finished Apr 30 02:44:23 PM PDT 24
Peak memory 225448 kb
Host smart-97de0601-bc6a-40d0-8bb3-5acb4b6385d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128835453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.128835453
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.4036960818
Short name T693
Test name
Test status
Simulation time 32248070 ps
CPU time 1.29 seconds
Started Apr 30 02:44:20 PM PDT 24
Finished Apr 30 02:44:21 PM PDT 24
Peak memory 215096 kb
Host smart-a3075d19-8ad1-4ab8-9781-b414866378e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036960818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.4036960818
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.913105928
Short name T810
Test name
Test status
Simulation time 19323645 ps
CPU time 1.14 seconds
Started Apr 30 02:44:26 PM PDT 24
Finished Apr 30 02:44:28 PM PDT 24
Peak memory 223940 kb
Host smart-94c31d1a-8c8f-4867-b65e-2c960437c6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913105928 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.913105928
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.525487864
Short name T399
Test name
Test status
Simulation time 40559886 ps
CPU time 1.45 seconds
Started Apr 30 02:44:19 PM PDT 24
Finished Apr 30 02:44:21 PM PDT 24
Peak memory 216888 kb
Host smart-9ef19d80-cac1-486d-bc7f-5d2db368e705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525487864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.525487864
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.2942144091
Short name T152
Test name
Test status
Simulation time 19450330 ps
CPU time 1.05 seconds
Started Apr 30 02:44:25 PM PDT 24
Finished Apr 30 02:44:26 PM PDT 24
Peak memory 218428 kb
Host smart-8bb15cbf-ea13-45dd-9cb8-65524cee4a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942144091 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2942144091
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3005479071
Short name T277
Test name
Test status
Simulation time 149181694 ps
CPU time 1.67 seconds
Started Apr 30 02:44:27 PM PDT 24
Finished Apr 30 02:44:30 PM PDT 24
Peak memory 218584 kb
Host smart-ee93b861-711d-4988-b964-050eb6ff6acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005479071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3005479071
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.2411312270
Short name T406
Test name
Test status
Simulation time 28996614 ps
CPU time 1.3 seconds
Started Apr 30 02:44:27 PM PDT 24
Finished Apr 30 02:44:29 PM PDT 24
Peak memory 219408 kb
Host smart-d7e2959c-aa3d-4276-a066-c1e808e839a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411312270 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2411312270
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1381910823
Short name T84
Test name
Test status
Simulation time 56112801 ps
CPU time 1.37 seconds
Started Apr 30 02:44:28 PM PDT 24
Finished Apr 30 02:44:31 PM PDT 24
Peak memory 216796 kb
Host smart-3d647dc9-9f27-4706-9feb-4779baef0327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381910823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1381910823
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3522000542
Short name T269
Test name
Test status
Simulation time 39727246 ps
CPU time 1.21 seconds
Started Apr 30 02:43:13 PM PDT 24
Finished Apr 30 02:43:15 PM PDT 24
Peak memory 215528 kb
Host smart-e14ff7d8-da3b-4fe1-91c1-49b1924a6f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522000542 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3522000542
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1771935144
Short name T843
Test name
Test status
Simulation time 58687613 ps
CPU time 0.92 seconds
Started Apr 30 02:43:09 PM PDT 24
Finished Apr 30 02:43:10 PM PDT 24
Peak memory 214716 kb
Host smart-a2361fae-3dc8-4fcd-a50f-431c4253663e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771935144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1771935144
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1359975472
Short name T527
Test name
Test status
Simulation time 16011199 ps
CPU time 0.91 seconds
Started Apr 30 02:43:10 PM PDT 24
Finished Apr 30 02:43:12 PM PDT 24
Peak memory 215924 kb
Host smart-010bf3ee-513f-43d2-b472-ed77d44f1cd0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359975472 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1359975472
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.4211801969
Short name T734
Test name
Test status
Simulation time 58354513 ps
CPU time 1.09 seconds
Started Apr 30 02:43:11 PM PDT 24
Finished Apr 30 02:43:13 PM PDT 24
Peak memory 218932 kb
Host smart-af096e6a-7970-4aa9-af63-9cd6a73b41f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211801969 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.4211801969
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2822582678
Short name T811
Test name
Test status
Simulation time 31353360 ps
CPU time 1.07 seconds
Started Apr 30 02:43:12 PM PDT 24
Finished Apr 30 02:43:14 PM PDT 24
Peak memory 218428 kb
Host smart-98523a1f-9241-443d-af08-45c5fa2cdbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822582678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2822582678
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3614612932
Short name T741
Test name
Test status
Simulation time 126044896 ps
CPU time 1.72 seconds
Started Apr 30 02:43:03 PM PDT 24
Finished Apr 30 02:43:06 PM PDT 24
Peak memory 219932 kb
Host smart-4de5d6ea-4fb6-46f1-abc6-77f9b1c9f53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614612932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3614612932
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.4077527026
Short name T81
Test name
Test status
Simulation time 32746447 ps
CPU time 0.96 seconds
Started Apr 30 02:43:12 PM PDT 24
Finished Apr 30 02:43:14 PM PDT 24
Peak memory 215384 kb
Host smart-6a211c05-d91b-4ee9-821b-9ff264b1500d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077527026 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.4077527026
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.2059020969
Short name T30
Test name
Test status
Simulation time 153128178 ps
CPU time 0.95 seconds
Started Apr 30 02:43:08 PM PDT 24
Finished Apr 30 02:43:09 PM PDT 24
Peak memory 206884 kb
Host smart-cdf77a60-17f8-4157-b777-9d2d8ca219e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059020969 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2059020969
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1227139240
Short name T649
Test name
Test status
Simulation time 24861381 ps
CPU time 0.93 seconds
Started Apr 30 02:43:02 PM PDT 24
Finished Apr 30 02:43:04 PM PDT 24
Peak memory 215096 kb
Host smart-1e424e1f-a1cb-444b-801b-fe844d88e3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227139240 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1227139240
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3710636651
Short name T654
Test name
Test status
Simulation time 26717223 ps
CPU time 1.14 seconds
Started Apr 30 02:43:02 PM PDT 24
Finished Apr 30 02:43:05 PM PDT 24
Peak memory 218816 kb
Host smart-31c6c1b2-247a-454c-a719-aff0c9e54ba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710636651 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3710636651
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3238900608
Short name T689
Test name
Test status
Simulation time 32269565452 ps
CPU time 726.94 seconds
Started Apr 30 02:43:14 PM PDT 24
Finished Apr 30 02:55:22 PM PDT 24
Peak memory 217984 kb
Host smart-0c01e95d-71ed-4f06-8c23-5c1dcce1ed0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238900608 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3238900608
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.4003626673
Short name T145
Test name
Test status
Simulation time 61141085 ps
CPU time 1.08 seconds
Started Apr 30 02:44:24 PM PDT 24
Finished Apr 30 02:44:26 PM PDT 24
Peak memory 219512 kb
Host smart-6885eef5-8295-4dbe-b269-d25bbcd70b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003626673 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.4003626673
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.861729929
Short name T807
Test name
Test status
Simulation time 89212562 ps
CPU time 1 seconds
Started Apr 30 02:44:20 PM PDT 24
Finished Apr 30 02:44:22 PM PDT 24
Peak memory 217024 kb
Host smart-30aca0e7-f99d-43ac-a213-cd7e7ada9849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861729929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.861729929
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.1479771937
Short name T116
Test name
Test status
Simulation time 44527139 ps
CPU time 0.98 seconds
Started Apr 30 02:44:24 PM PDT 24
Finished Apr 30 02:44:25 PM PDT 24
Peak memory 219504 kb
Host smart-888d7774-ebcd-41dd-b6cd-0643e7bab4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479771937 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1479771937
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3495511546
Short name T391
Test name
Test status
Simulation time 97327650 ps
CPU time 1.24 seconds
Started Apr 30 02:44:20 PM PDT 24
Finished Apr 30 02:44:21 PM PDT 24
Peak memory 217192 kb
Host smart-044b4d98-32a8-4ede-a9d2-b2958a0a8739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495511546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3495511546
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.2552344374
Short name T495
Test name
Test status
Simulation time 28260164 ps
CPU time 0.89 seconds
Started Apr 30 02:44:28 PM PDT 24
Finished Apr 30 02:44:30 PM PDT 24
Peak memory 217944 kb
Host smart-6c5a81ee-ac3c-4411-bfe7-9a1166474034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552344374 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2552344374
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2294276221
Short name T44
Test name
Test status
Simulation time 54754359 ps
CPU time 1.7 seconds
Started Apr 30 02:44:25 PM PDT 24
Finished Apr 30 02:44:27 PM PDT 24
Peak memory 217012 kb
Host smart-7ce49479-0df7-4c2c-a07b-24d4335fbc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294276221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2294276221
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.3318535742
Short name T60
Test name
Test status
Simulation time 23208475 ps
CPU time 1.08 seconds
Started Apr 30 02:44:27 PM PDT 24
Finished Apr 30 02:44:29 PM PDT 24
Peak memory 223876 kb
Host smart-455da124-bc04-4f56-8dfe-36568768af1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318535742 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3318535742
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3308357339
Short name T546
Test name
Test status
Simulation time 32523433 ps
CPU time 1.03 seconds
Started Apr 30 02:44:21 PM PDT 24
Finished Apr 30 02:44:22 PM PDT 24
Peak memory 216772 kb
Host smart-eaff8a53-fa57-4457-85c3-9c24049ad6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308357339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3308357339
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.3204160326
Short name T420
Test name
Test status
Simulation time 69641501 ps
CPU time 1.17 seconds
Started Apr 30 02:44:47 PM PDT 24
Finished Apr 30 02:44:49 PM PDT 24
Peak memory 225544 kb
Host smart-2b00d7b6-e973-4470-8466-6a56450bf112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204160326 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3204160326
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/85.edn_err.4294513337
Short name T123
Test name
Test status
Simulation time 46714898 ps
CPU time 1.12 seconds
Started Apr 30 02:44:30 PM PDT 24
Finished Apr 30 02:44:32 PM PDT 24
Peak memory 229516 kb
Host smart-22a4a110-15db-49c0-a293-fa1d5edd5eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294513337 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.4294513337
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1916973788
Short name T670
Test name
Test status
Simulation time 50608945 ps
CPU time 1.67 seconds
Started Apr 30 02:44:26 PM PDT 24
Finished Apr 30 02:44:28 PM PDT 24
Peak memory 216952 kb
Host smart-5e6a9409-a374-4152-abbe-ed17ae091d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916973788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1916973788
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.2951342995
Short name T622
Test name
Test status
Simulation time 57433028 ps
CPU time 1.12 seconds
Started Apr 30 02:44:48 PM PDT 24
Finished Apr 30 02:44:50 PM PDT 24
Peak memory 232008 kb
Host smart-2f5693d3-1c08-4ec0-851a-c985bd586b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951342995 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2951342995
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1588472211
Short name T303
Test name
Test status
Simulation time 29418254 ps
CPU time 1.28 seconds
Started Apr 30 02:44:28 PM PDT 24
Finished Apr 30 02:44:30 PM PDT 24
Peak memory 219448 kb
Host smart-2081f039-204c-42fe-9a91-54f2bddf4ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588472211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1588472211
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.2786962859
Short name T135
Test name
Test status
Simulation time 43798077 ps
CPU time 1.3 seconds
Started Apr 30 02:44:28 PM PDT 24
Finished Apr 30 02:44:30 PM PDT 24
Peak memory 224756 kb
Host smart-53476ddc-1ac4-4f7a-9a08-27ff2696b6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786962859 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2786962859
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.4202111082
Short name T306
Test name
Test status
Simulation time 41736391 ps
CPU time 1.72 seconds
Started Apr 30 02:44:28 PM PDT 24
Finished Apr 30 02:44:31 PM PDT 24
Peak memory 217104 kb
Host smart-966044c1-0089-46cd-b26f-6aabdedee95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202111082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.4202111082
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.3138585113
Short name T151
Test name
Test status
Simulation time 18334829 ps
CPU time 1.16 seconds
Started Apr 30 02:44:27 PM PDT 24
Finished Apr 30 02:44:29 PM PDT 24
Peak memory 223940 kb
Host smart-4707d787-5798-4e09-9a05-c9070344492b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138585113 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3138585113
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1380888041
Short name T284
Test name
Test status
Simulation time 37492350 ps
CPU time 1.29 seconds
Started Apr 30 02:44:27 PM PDT 24
Finished Apr 30 02:44:29 PM PDT 24
Peak memory 218368 kb
Host smart-5572e2ae-0dd2-4b0c-ab72-317541615f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380888041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1380888041
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.2416635009
Short name T737
Test name
Test status
Simulation time 33203375 ps
CPU time 1.03 seconds
Started Apr 30 02:44:27 PM PDT 24
Finished Apr 30 02:44:28 PM PDT 24
Peak memory 232336 kb
Host smart-7973061e-67cc-4953-9229-e69683cb33ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416635009 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2416635009
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2741615205
Short name T278
Test name
Test status
Simulation time 31436314 ps
CPU time 1.29 seconds
Started Apr 30 02:44:47 PM PDT 24
Finished Apr 30 02:44:49 PM PDT 24
Peak memory 219440 kb
Host smart-e1e4cfbe-e2f1-4d7e-b7bb-41179ed14ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741615205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2741615205
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1294789359
Short name T196
Test name
Test status
Simulation time 41436903 ps
CPU time 1.08 seconds
Started Apr 30 02:43:12 PM PDT 24
Finished Apr 30 02:43:14 PM PDT 24
Peak memory 215484 kb
Host smart-dcab6da9-2c07-4741-b818-de93530fa603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294789359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1294789359
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.322404666
Short name T644
Test name
Test status
Simulation time 125145344 ps
CPU time 0.9 seconds
Started Apr 30 02:43:11 PM PDT 24
Finished Apr 30 02:43:12 PM PDT 24
Peak memory 214736 kb
Host smart-e57cc751-ad8f-4df1-a38a-17c6f8854407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322404666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.322404666
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_err.3296021620
Short name T681
Test name
Test status
Simulation time 18232944 ps
CPU time 1.08 seconds
Started Apr 30 02:43:10 PM PDT 24
Finished Apr 30 02:43:12 PM PDT 24
Peak memory 218388 kb
Host smart-b32fe23a-a52f-4098-b0f9-84ec7687a74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296021620 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3296021620
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.4057233534
Short name T736
Test name
Test status
Simulation time 44781209 ps
CPU time 1.14 seconds
Started Apr 30 02:43:11 PM PDT 24
Finished Apr 30 02:43:13 PM PDT 24
Peak memory 218012 kb
Host smart-80de9cd3-7860-4db5-b9c2-cc0626ed0c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057233534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.4057233534
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3298535280
Short name T479
Test name
Test status
Simulation time 31706247 ps
CPU time 0.9 seconds
Started Apr 30 02:43:12 PM PDT 24
Finished Apr 30 02:43:14 PM PDT 24
Peak memory 215240 kb
Host smart-2ad24d8d-7ee7-443e-95ea-068c8b7a6c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298535280 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3298535280
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2714499317
Short name T29
Test name
Test status
Simulation time 46475090 ps
CPU time 0.93 seconds
Started Apr 30 02:43:12 PM PDT 24
Finished Apr 30 02:43:14 PM PDT 24
Peak memory 206912 kb
Host smart-5cd9ddd5-38a5-4a68-8c13-72a25b8b5ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714499317 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2714499317
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.744240069
Short name T835
Test name
Test status
Simulation time 27415783 ps
CPU time 0.96 seconds
Started Apr 30 02:43:11 PM PDT 24
Finished Apr 30 02:43:13 PM PDT 24
Peak memory 215140 kb
Host smart-63ac7911-3e8a-4bb4-a7f9-f9b06602f032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744240069 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.744240069
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1774557601
Short name T321
Test name
Test status
Simulation time 302213393 ps
CPU time 6.07 seconds
Started Apr 30 02:43:12 PM PDT 24
Finished Apr 30 02:43:19 PM PDT 24
Peak memory 216944 kb
Host smart-ba157259-6344-41c7-a45f-7576c4e82822
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774557601 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1774557601
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3752504273
Short name T206
Test name
Test status
Simulation time 132449200051 ps
CPU time 1511.63 seconds
Started Apr 30 02:43:11 PM PDT 24
Finished Apr 30 03:08:24 PM PDT 24
Peak memory 224140 kb
Host smart-f237378c-99b4-4b75-a3f3-ab47d83b4852
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752504273 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3752504273
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.829879362
Short name T5
Test name
Test status
Simulation time 161347177 ps
CPU time 0.95 seconds
Started Apr 30 02:44:37 PM PDT 24
Finished Apr 30 02:44:38 PM PDT 24
Peak memory 218184 kb
Host smart-369d8a6e-fd23-4469-a6c3-7e74f7554f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829879362 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.829879362
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3528736088
Short name T271
Test name
Test status
Simulation time 104068460 ps
CPU time 1.28 seconds
Started Apr 30 02:44:28 PM PDT 24
Finished Apr 30 02:44:30 PM PDT 24
Peak memory 218524 kb
Host smart-a0d358c2-743d-4ce7-b042-7c5992757a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528736088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3528736088
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.2896943100
Short name T503
Test name
Test status
Simulation time 24205273 ps
CPU time 1.21 seconds
Started Apr 30 02:44:26 PM PDT 24
Finished Apr 30 02:44:28 PM PDT 24
Peak memory 218524 kb
Host smart-e533d5ac-05de-46e8-a8ad-cedb051f7660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896943100 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2896943100
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1887895208
Short name T297
Test name
Test status
Simulation time 43040086 ps
CPU time 1.16 seconds
Started Apr 30 02:44:30 PM PDT 24
Finished Apr 30 02:44:32 PM PDT 24
Peak memory 217024 kb
Host smart-d1a62c2b-8ceb-4a42-9c3e-2c0c41e6cd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887895208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1887895208
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.179020951
Short name T466
Test name
Test status
Simulation time 68707283 ps
CPU time 1.11 seconds
Started Apr 30 02:44:27 PM PDT 24
Finished Apr 30 02:44:29 PM PDT 24
Peak memory 219456 kb
Host smart-3ba7309d-78e9-4ab6-8e2c-8f793f077744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179020951 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.179020951
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1637971054
Short name T813
Test name
Test status
Simulation time 104988764 ps
CPU time 1.54 seconds
Started Apr 30 02:44:29 PM PDT 24
Finished Apr 30 02:44:31 PM PDT 24
Peak memory 218108 kb
Host smart-343352f0-ce15-46d1-8b24-6b948864b976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637971054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1637971054
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.991282334
Short name T529
Test name
Test status
Simulation time 21094277 ps
CPU time 1.12 seconds
Started Apr 30 02:44:31 PM PDT 24
Finished Apr 30 02:44:33 PM PDT 24
Peak memory 218480 kb
Host smart-f8a451d2-c627-4187-9d27-3e6aac98dbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991282334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.991282334
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.444642967
Short name T496
Test name
Test status
Simulation time 40871596 ps
CPU time 1.09 seconds
Started Apr 30 02:44:27 PM PDT 24
Finished Apr 30 02:44:28 PM PDT 24
Peak memory 216812 kb
Host smart-4eca0296-029b-408b-8959-82da622dbcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444642967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.444642967
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.327777665
Short name T68
Test name
Test status
Simulation time 27688537 ps
CPU time 1.24 seconds
Started Apr 30 02:44:43 PM PDT 24
Finished Apr 30 02:44:45 PM PDT 24
Peak memory 217264 kb
Host smart-f8ec96f3-fead-4454-b916-91145d48cc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327777665 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.327777665
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/95.edn_err.4285139882
Short name T367
Test name
Test status
Simulation time 71318336 ps
CPU time 1.06 seconds
Started Apr 30 02:44:35 PM PDT 24
Finished Apr 30 02:44:37 PM PDT 24
Peak memory 219324 kb
Host smart-7917701a-f3b6-4b08-b3e5-35198d399c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285139882 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.4285139882
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.881450883
Short name T639
Test name
Test status
Simulation time 162345850 ps
CPU time 0.99 seconds
Started Apr 30 02:44:27 PM PDT 24
Finished Apr 30 02:44:29 PM PDT 24
Peak memory 216808 kb
Host smart-76df3924-9fe6-4b5b-8289-2ad60e9f3e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881450883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.881450883
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.620921132
Short name T536
Test name
Test status
Simulation time 26838257 ps
CPU time 1.23 seconds
Started Apr 30 02:44:33 PM PDT 24
Finished Apr 30 02:44:34 PM PDT 24
Peak memory 220348 kb
Host smart-b16c0ba6-5cd4-4c82-86ff-b4825df8a405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620921132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.620921132
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2709665027
Short name T738
Test name
Test status
Simulation time 90754536 ps
CPU time 1.46 seconds
Started Apr 30 02:44:30 PM PDT 24
Finished Apr 30 02:44:32 PM PDT 24
Peak memory 218072 kb
Host smart-b83c7466-56c1-4d74-9a70-306fc69a9910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709665027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2709665027
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.3012160635
Short name T581
Test name
Test status
Simulation time 31140569 ps
CPU time 0.86 seconds
Started Apr 30 02:44:35 PM PDT 24
Finished Apr 30 02:44:37 PM PDT 24
Peak memory 218008 kb
Host smart-6d525b85-dd99-4e4c-b84e-39d1ae1550c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012160635 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3012160635
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2148368099
Short name T397
Test name
Test status
Simulation time 81619831 ps
CPU time 1.33 seconds
Started Apr 30 02:44:35 PM PDT 24
Finished Apr 30 02:44:37 PM PDT 24
Peak memory 216748 kb
Host smart-0c4f10b1-2134-43f7-a5be-b82b085719ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148368099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2148368099
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1093425272
Short name T452
Test name
Test status
Simulation time 32805021 ps
CPU time 0.99 seconds
Started Apr 30 02:44:29 PM PDT 24
Finished Apr 30 02:44:31 PM PDT 24
Peak memory 218232 kb
Host smart-78d48978-6e12-4528-ab03-e28c37e110ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093425272 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1093425272
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3015157778
Short name T728
Test name
Test status
Simulation time 46401814 ps
CPU time 1.46 seconds
Started Apr 30 02:44:32 PM PDT 24
Finished Apr 30 02:44:34 PM PDT 24
Peak memory 219404 kb
Host smart-88b9025e-c7ee-431a-b7a9-0b00b7dba148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015157778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3015157778
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.2070540622
Short name T569
Test name
Test status
Simulation time 30352004 ps
CPU time 1.17 seconds
Started Apr 30 02:44:33 PM PDT 24
Finished Apr 30 02:44:35 PM PDT 24
Peak memory 219560 kb
Host smart-e92a5bf9-09c4-4df6-be57-363fdbd1997b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070540622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2070540622
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3920219452
Short name T796
Test name
Test status
Simulation time 90713960 ps
CPU time 2.98 seconds
Started Apr 30 02:44:31 PM PDT 24
Finished Apr 30 02:44:34 PM PDT 24
Peak memory 219536 kb
Host smart-974ac058-e029-4950-b253-4949b3ff0a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920219452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3920219452
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%