Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.30 98.24 93.76 97.02 82.08 96.76 99.77 92.47


Total test records in report: 976
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T792 /workspace/coverage/default/97.edn_err.316592263 May 05 01:54:26 PM PDT 24 May 05 01:54:28 PM PDT 24 21205436 ps
T793 /workspace/coverage/default/155.edn_genbits.4178317031 May 05 01:54:38 PM PDT 24 May 05 01:54:40 PM PDT 24 59881784 ps
T794 /workspace/coverage/default/27.edn_disable.1067475536 May 05 01:53:38 PM PDT 24 May 05 01:53:39 PM PDT 24 22406573 ps
T795 /workspace/coverage/default/79.edn_genbits.2119779706 May 05 01:54:23 PM PDT 24 May 05 01:54:26 PM PDT 24 298943771 ps
T796 /workspace/coverage/default/0.edn_disable_auto_req_mode.3445553481 May 05 01:52:31 PM PDT 24 May 05 01:52:32 PM PDT 24 50942430 ps
T797 /workspace/coverage/default/40.edn_smoke.782296552 May 05 01:53:57 PM PDT 24 May 05 01:53:58 PM PDT 24 28361941 ps
T798 /workspace/coverage/default/48.edn_err.2740371272 May 05 01:54:20 PM PDT 24 May 05 01:54:21 PM PDT 24 21164100 ps
T799 /workspace/coverage/default/35.edn_stress_all.3782700642 May 05 01:53:51 PM PDT 24 May 05 01:53:55 PM PDT 24 2075439530 ps
T800 /workspace/coverage/default/13.edn_genbits.1756420492 May 05 01:53:12 PM PDT 24 May 05 01:53:14 PM PDT 24 106585277 ps
T801 /workspace/coverage/default/127.edn_genbits.749146028 May 05 01:54:34 PM PDT 24 May 05 01:54:36 PM PDT 24 122931145 ps
T802 /workspace/coverage/default/48.edn_stress_all.3877394622 May 05 01:54:08 PM PDT 24 May 05 01:54:11 PM PDT 24 96368133 ps
T803 /workspace/coverage/default/14.edn_alert.3991231618 May 05 01:53:12 PM PDT 24 May 05 01:53:14 PM PDT 24 26799204 ps
T171 /workspace/coverage/default/37.edn_disable_auto_req_mode.390037828 May 05 01:53:53 PM PDT 24 May 05 01:53:55 PM PDT 24 38932300 ps
T804 /workspace/coverage/default/53.edn_err.4098901200 May 05 01:54:20 PM PDT 24 May 05 01:54:21 PM PDT 24 34287743 ps
T805 /workspace/coverage/default/74.edn_err.2427968288 May 05 01:54:23 PM PDT 24 May 05 01:54:24 PM PDT 24 21588563 ps
T806 /workspace/coverage/default/43.edn_disable.1834270342 May 05 01:54:03 PM PDT 24 May 05 01:54:05 PM PDT 24 12138023 ps
T807 /workspace/coverage/default/46.edn_intr.2133503349 May 05 01:54:06 PM PDT 24 May 05 01:54:08 PM PDT 24 22178883 ps
T808 /workspace/coverage/default/44.edn_err.3102649465 May 05 01:54:00 PM PDT 24 May 05 01:54:02 PM PDT 24 18298392 ps
T809 /workspace/coverage/default/31.edn_disable_auto_req_mode.3274356312 May 05 01:53:45 PM PDT 24 May 05 01:53:47 PM PDT 24 20195981 ps
T172 /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2100296463 May 05 01:52:42 PM PDT 24 May 05 02:19:27 PM PDT 24 59372261854 ps
T810 /workspace/coverage/default/2.edn_smoke.3635157454 May 05 01:52:38 PM PDT 24 May 05 01:52:40 PM PDT 24 167627259 ps
T811 /workspace/coverage/default/49.edn_err.2068853065 May 05 01:54:12 PM PDT 24 May 05 01:54:13 PM PDT 24 31749198 ps
T812 /workspace/coverage/default/32.edn_err.2310829412 May 05 01:53:46 PM PDT 24 May 05 01:53:48 PM PDT 24 43302618 ps
T813 /workspace/coverage/default/42.edn_disable_auto_req_mode.690575177 May 05 01:53:58 PM PDT 24 May 05 01:54:00 PM PDT 24 63313878 ps
T814 /workspace/coverage/default/2.edn_disable.3806260117 May 05 01:52:35 PM PDT 24 May 05 01:52:36 PM PDT 24 16805599 ps
T815 /workspace/coverage/default/41.edn_disable.4126356296 May 05 01:53:57 PM PDT 24 May 05 01:53:59 PM PDT 24 16958516 ps
T816 /workspace/coverage/default/269.edn_genbits.2168110902 May 05 01:54:55 PM PDT 24 May 05 01:54:57 PM PDT 24 85168804 ps
T817 /workspace/coverage/default/259.edn_genbits.98595937 May 05 01:54:49 PM PDT 24 May 05 01:54:51 PM PDT 24 89759564 ps
T818 /workspace/coverage/default/51.edn_err.3432756140 May 05 01:54:18 PM PDT 24 May 05 01:54:20 PM PDT 24 29495048 ps
T819 /workspace/coverage/default/26.edn_intr.2547615404 May 05 01:53:30 PM PDT 24 May 05 01:53:31 PM PDT 24 24028707 ps
T820 /workspace/coverage/default/254.edn_genbits.3898410835 May 05 01:54:48 PM PDT 24 May 05 01:54:50 PM PDT 24 55766091 ps
T821 /workspace/coverage/default/28.edn_stress_all.2641635312 May 05 01:53:38 PM PDT 24 May 05 01:53:42 PM PDT 24 524652865 ps
T822 /workspace/coverage/default/22.edn_intr.1093814314 May 05 01:53:26 PM PDT 24 May 05 01:53:27 PM PDT 24 31665025 ps
T175 /workspace/coverage/default/49.edn_disable.3873758585 May 05 01:54:13 PM PDT 24 May 05 01:54:15 PM PDT 24 22751554 ps
T823 /workspace/coverage/default/18.edn_alert.229755667 May 05 01:53:17 PM PDT 24 May 05 01:53:19 PM PDT 24 79176128 ps
T284 /workspace/coverage/default/122.edn_genbits.1878890882 May 05 01:54:34 PM PDT 24 May 05 01:54:36 PM PDT 24 98699987 ps
T116 /workspace/coverage/default/73.edn_err.1678056596 May 05 01:54:24 PM PDT 24 May 05 01:54:26 PM PDT 24 25005819 ps
T824 /workspace/coverage/default/47.edn_err.2801837355 May 05 01:54:13 PM PDT 24 May 05 01:54:15 PM PDT 24 46393474 ps
T825 /workspace/coverage/default/33.edn_alert_test.3822360705 May 05 01:53:51 PM PDT 24 May 05 01:53:52 PM PDT 24 20646375 ps
T826 /workspace/coverage/default/268.edn_genbits.1415121986 May 05 01:54:52 PM PDT 24 May 05 01:54:54 PM PDT 24 27972903 ps
T827 /workspace/coverage/default/11.edn_intr.3046874290 May 05 01:53:12 PM PDT 24 May 05 01:53:13 PM PDT 24 77803107 ps
T828 /workspace/coverage/default/20.edn_genbits.2580788345 May 05 01:53:19 PM PDT 24 May 05 01:53:21 PM PDT 24 42490339 ps
T829 /workspace/coverage/default/18.edn_alert_test.241553371 May 05 01:53:17 PM PDT 24 May 05 01:53:18 PM PDT 24 19996495 ps
T830 /workspace/coverage/default/17.edn_alert_test.3222786157 May 05 01:53:18 PM PDT 24 May 05 01:53:19 PM PDT 24 31828760 ps
T831 /workspace/coverage/default/37.edn_alert_test.467097026 May 05 01:53:53 PM PDT 24 May 05 01:53:55 PM PDT 24 33993030 ps
T832 /workspace/coverage/default/10.edn_disable.1756274820 May 05 01:53:04 PM PDT 24 May 05 01:53:05 PM PDT 24 12856492 ps
T833 /workspace/coverage/default/23.edn_stress_all.144826294 May 05 01:53:27 PM PDT 24 May 05 01:53:32 PM PDT 24 339286126 ps
T834 /workspace/coverage/default/220.edn_genbits.1743242847 May 05 01:54:46 PM PDT 24 May 05 01:54:48 PM PDT 24 54326823 ps
T835 /workspace/coverage/default/49.edn_alert_test.2949653258 May 05 01:54:13 PM PDT 24 May 05 01:54:15 PM PDT 24 56180351 ps
T836 /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1367642444 May 05 01:53:58 PM PDT 24 May 05 02:08:04 PM PDT 24 32006081650 ps
T837 /workspace/coverage/default/28.edn_err.3956867152 May 05 01:53:36 PM PDT 24 May 05 01:53:38 PM PDT 24 26119635 ps
T838 /workspace/coverage/default/66.edn_genbits.4088474336 May 05 01:54:20 PM PDT 24 May 05 01:54:22 PM PDT 24 39007201 ps
T839 /workspace/coverage/default/5.edn_err.3025686855 May 05 01:52:49 PM PDT 24 May 05 01:52:50 PM PDT 24 19647825 ps
T840 /workspace/coverage/default/78.edn_err.3717983005 May 05 01:54:22 PM PDT 24 May 05 01:54:24 PM PDT 24 22788133 ps
T841 /workspace/coverage/default/53.edn_genbits.448449861 May 05 01:54:15 PM PDT 24 May 05 01:54:17 PM PDT 24 54292730 ps
T842 /workspace/coverage/default/69.edn_genbits.1423367801 May 05 01:54:16 PM PDT 24 May 05 01:54:18 PM PDT 24 38215145 ps
T843 /workspace/coverage/default/49.edn_stress_all.2660972019 May 05 01:54:12 PM PDT 24 May 05 01:54:13 PM PDT 24 67951840 ps
T844 /workspace/coverage/default/161.edn_genbits.4129609538 May 05 01:54:39 PM PDT 24 May 05 01:54:41 PM PDT 24 83566254 ps
T845 /workspace/coverage/default/34.edn_genbits.2799285635 May 05 01:53:46 PM PDT 24 May 05 01:53:48 PM PDT 24 36174659 ps
T118 /workspace/coverage/default/77.edn_err.2373374013 May 05 01:54:22 PM PDT 24 May 05 01:54:23 PM PDT 24 170019595 ps
T846 /workspace/coverage/default/27.edn_stress_all.3817764088 May 05 01:53:30 PM PDT 24 May 05 01:53:34 PM PDT 24 1814841978 ps
T216 /workspace/coverage/cover_reg_top/10.edn_csr_rw.4091116749 May 05 02:28:23 PM PDT 24 May 05 02:28:25 PM PDT 24 13020282 ps
T205 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2232103294 May 05 02:27:59 PM PDT 24 May 05 02:28:00 PM PDT 24 63376541 ps
T217 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2326254402 May 05 02:28:15 PM PDT 24 May 05 02:28:16 PM PDT 24 24581359 ps
T241 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1056931872 May 05 02:28:44 PM PDT 24 May 05 02:28:46 PM PDT 24 80058113 ps
T847 /workspace/coverage/cover_reg_top/12.edn_intr_test.565110589 May 05 02:28:33 PM PDT 24 May 05 02:28:34 PM PDT 24 49987658 ps
T848 /workspace/coverage/cover_reg_top/5.edn_intr_test.2090483259 May 05 02:28:00 PM PDT 24 May 05 02:28:01 PM PDT 24 39127251 ps
T208 /workspace/coverage/cover_reg_top/2.edn_tl_errors.2120047836 May 05 02:27:29 PM PDT 24 May 05 02:27:31 PM PDT 24 84816974 ps
T849 /workspace/coverage/cover_reg_top/27.edn_intr_test.2338540586 May 05 02:29:11 PM PDT 24 May 05 02:29:13 PM PDT 24 16719320 ps
T242 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1443559513 May 05 02:28:50 PM PDT 24 May 05 02:28:53 PM PDT 24 345549301 ps
T234 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1139198041 May 05 02:27:34 PM PDT 24 May 05 02:27:36 PM PDT 24 13080583 ps
T850 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1844854899 May 05 02:29:03 PM PDT 24 May 05 02:29:04 PM PDT 24 73576790 ps
T218 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2526010567 May 05 02:27:41 PM PDT 24 May 05 02:27:42 PM PDT 24 35672269 ps
T851 /workspace/coverage/cover_reg_top/12.edn_tl_errors.714119113 May 05 02:28:33 PM PDT 24 May 05 02:28:35 PM PDT 24 46147449 ps
T852 /workspace/coverage/cover_reg_top/34.edn_intr_test.2967648268 May 05 02:29:14 PM PDT 24 May 05 02:29:15 PM PDT 24 11706795 ps
T853 /workspace/coverage/cover_reg_top/24.edn_intr_test.3409347048 May 05 02:29:09 PM PDT 24 May 05 02:29:10 PM PDT 24 68573665 ps
T854 /workspace/coverage/cover_reg_top/40.edn_intr_test.3405726524 May 05 02:29:20 PM PDT 24 May 05 02:29:21 PM PDT 24 34243207 ps
T855 /workspace/coverage/cover_reg_top/10.edn_intr_test.1738494748 May 05 02:28:26 PM PDT 24 May 05 02:28:27 PM PDT 24 79698383 ps
T856 /workspace/coverage/cover_reg_top/10.edn_tl_errors.4280465011 May 05 02:28:18 PM PDT 24 May 05 02:28:21 PM PDT 24 46719090 ps
T857 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3420085260 May 05 02:27:17 PM PDT 24 May 05 02:27:22 PM PDT 24 507605560 ps
T858 /workspace/coverage/cover_reg_top/38.edn_intr_test.3529911770 May 05 02:29:18 PM PDT 24 May 05 02:29:20 PM PDT 24 15822119 ps
T219 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.4148008440 May 05 02:27:00 PM PDT 24 May 05 02:27:07 PM PDT 24 4929674051 ps
T238 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3267130727 May 05 02:27:49 PM PDT 24 May 05 02:27:51 PM PDT 24 19407763 ps
T859 /workspace/coverage/cover_reg_top/7.edn_intr_test.4171961847 May 05 02:28:12 PM PDT 24 May 05 02:28:13 PM PDT 24 16633862 ps
T860 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.4079601709 May 05 02:28:34 PM PDT 24 May 05 02:28:35 PM PDT 24 23277489 ps
T861 /workspace/coverage/cover_reg_top/19.edn_intr_test.554453366 May 05 02:28:55 PM PDT 24 May 05 02:28:56 PM PDT 24 11345375 ps
T862 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1695524847 May 05 02:28:46 PM PDT 24 May 05 02:28:48 PM PDT 24 58732827 ps
T863 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3443560078 May 05 02:28:13 PM PDT 24 May 05 02:28:16 PM PDT 24 38227647 ps
T864 /workspace/coverage/cover_reg_top/21.edn_intr_test.3496284105 May 05 02:29:00 PM PDT 24 May 05 02:29:01 PM PDT 24 41286544 ps
T235 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3008493143 May 05 02:28:33 PM PDT 24 May 05 02:28:34 PM PDT 24 190690521 ps
T243 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.609258410 May 05 02:26:52 PM PDT 24 May 05 02:26:54 PM PDT 24 159981706 ps
T865 /workspace/coverage/cover_reg_top/47.edn_intr_test.2160768291 May 05 02:29:26 PM PDT 24 May 05 02:29:28 PM PDT 24 40966679 ps
T239 /workspace/coverage/cover_reg_top/5.edn_csr_rw.102869809 May 05 02:28:06 PM PDT 24 May 05 02:28:07 PM PDT 24 52321324 ps
T236 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.296823472 May 05 02:28:43 PM PDT 24 May 05 02:28:45 PM PDT 24 105801249 ps
T240 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3888005084 May 05 02:28:14 PM PDT 24 May 05 02:28:15 PM PDT 24 40273251 ps
T866 /workspace/coverage/cover_reg_top/22.edn_intr_test.77760727 May 05 02:29:02 PM PDT 24 May 05 02:29:04 PM PDT 24 55629378 ps
T867 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3781848272 May 05 02:28:18 PM PDT 24 May 05 02:28:20 PM PDT 24 74213344 ps
T252 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2152443571 May 05 02:27:38 PM PDT 24 May 05 02:27:41 PM PDT 24 114792601 ps
T237 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2439530338 May 05 02:28:10 PM PDT 24 May 05 02:28:12 PM PDT 24 23705946 ps
T868 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3426309488 May 05 02:27:37 PM PDT 24 May 05 02:27:41 PM PDT 24 376197784 ps
T869 /workspace/coverage/cover_reg_top/37.edn_intr_test.4181905704 May 05 02:29:18 PM PDT 24 May 05 02:29:19 PM PDT 24 128495880 ps
T256 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.307934216 May 05 02:28:18 PM PDT 24 May 05 02:28:21 PM PDT 24 99212725 ps
T870 /workspace/coverage/cover_reg_top/41.edn_intr_test.1733914288 May 05 02:29:19 PM PDT 24 May 05 02:29:20 PM PDT 24 19533935 ps
T871 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1933594544 May 05 02:27:59 PM PDT 24 May 05 02:28:00 PM PDT 24 29422410 ps
T872 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2229882149 May 05 02:27:09 PM PDT 24 May 05 02:27:11 PM PDT 24 21570855 ps
T873 /workspace/coverage/cover_reg_top/18.edn_intr_test.541080595 May 05 02:28:51 PM PDT 24 May 05 02:28:52 PM PDT 24 45898261 ps
T874 /workspace/coverage/cover_reg_top/48.edn_intr_test.1185366016 May 05 02:29:22 PM PDT 24 May 05 02:29:24 PM PDT 24 11712274 ps
T875 /workspace/coverage/cover_reg_top/9.edn_csr_rw.939283022 May 05 02:28:18 PM PDT 24 May 05 02:28:20 PM PDT 24 18394195 ps
T876 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3469345848 May 05 02:27:29 PM PDT 24 May 05 02:27:32 PM PDT 24 73726104 ps
T877 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2634108996 May 05 02:28:26 PM PDT 24 May 05 02:28:29 PM PDT 24 214340346 ps
T220 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2323751822 May 05 02:28:50 PM PDT 24 May 05 02:28:52 PM PDT 24 66163671 ps
T878 /workspace/coverage/cover_reg_top/23.edn_intr_test.742939274 May 05 02:29:02 PM PDT 24 May 05 02:29:03 PM PDT 24 35894232 ps
T879 /workspace/coverage/cover_reg_top/16.edn_intr_test.2113143455 May 05 02:28:50 PM PDT 24 May 05 02:28:52 PM PDT 24 13750301 ps
T221 /workspace/coverage/cover_reg_top/6.edn_csr_rw.427116404 May 05 02:28:06 PM PDT 24 May 05 02:28:07 PM PDT 24 118037948 ps
T222 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2470001767 May 05 02:28:53 PM PDT 24 May 05 02:28:55 PM PDT 24 117654629 ps
T880 /workspace/coverage/cover_reg_top/9.edn_intr_test.2122901312 May 05 02:28:13 PM PDT 24 May 05 02:28:14 PM PDT 24 66377072 ps
T881 /workspace/coverage/cover_reg_top/8.edn_intr_test.922086358 May 05 02:28:13 PM PDT 24 May 05 02:28:14 PM PDT 24 13236009 ps
T882 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.567626313 May 05 02:28:09 PM PDT 24 May 05 02:28:10 PM PDT 24 47433853 ps
T883 /workspace/coverage/cover_reg_top/33.edn_intr_test.1769671066 May 05 02:29:14 PM PDT 24 May 05 02:29:15 PM PDT 24 15574062 ps
T884 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1105866699 May 05 02:27:46 PM PDT 24 May 05 02:27:47 PM PDT 24 40231948 ps
T885 /workspace/coverage/cover_reg_top/44.edn_intr_test.874315232 May 05 02:29:17 PM PDT 24 May 05 02:29:18 PM PDT 24 12294716 ps
T886 /workspace/coverage/cover_reg_top/15.edn_intr_test.3124059073 May 05 02:28:48 PM PDT 24 May 05 02:28:50 PM PDT 24 19171341 ps
T887 /workspace/coverage/cover_reg_top/0.edn_intr_test.1570282204 May 05 02:27:02 PM PDT 24 May 05 02:27:03 PM PDT 24 35781869 ps
T888 /workspace/coverage/cover_reg_top/36.edn_intr_test.3362288022 May 05 02:29:11 PM PDT 24 May 05 02:29:13 PM PDT 24 15973891 ps
T889 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2063797225 May 05 02:28:43 PM PDT 24 May 05 02:28:47 PM PDT 24 94197733 ps
T890 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3472883074 May 05 02:28:51 PM PDT 24 May 05 02:28:53 PM PDT 24 17825191 ps
T223 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3943729488 May 05 02:27:05 PM PDT 24 May 05 02:27:07 PM PDT 24 159699956 ps
T224 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.13944154 May 05 02:28:19 PM PDT 24 May 05 02:28:21 PM PDT 24 170505364 ps
T225 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.411992631 May 05 02:27:38 PM PDT 24 May 05 02:27:40 PM PDT 24 30554184 ps
T891 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3722155816 May 05 02:28:05 PM PDT 24 May 05 02:28:09 PM PDT 24 114501996 ps
T892 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4031151293 May 05 02:28:46 PM PDT 24 May 05 02:28:50 PM PDT 24 148857408 ps
T893 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2023410857 May 05 02:27:55 PM PDT 24 May 05 02:27:59 PM PDT 24 349061553 ps
T894 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2443698353 May 05 02:28:05 PM PDT 24 May 05 02:28:07 PM PDT 24 247624648 ps
T895 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2052152616 May 05 02:27:36 PM PDT 24 May 05 02:27:39 PM PDT 24 35147648 ps
T226 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2614601499 May 05 02:27:01 PM PDT 24 May 05 02:27:02 PM PDT 24 24442236 ps
T896 /workspace/coverage/cover_reg_top/20.edn_intr_test.3805485987 May 05 02:29:04 PM PDT 24 May 05 02:29:05 PM PDT 24 140165554 ps
T897 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3407942090 May 05 02:27:25 PM PDT 24 May 05 02:27:26 PM PDT 24 167361900 ps
T227 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3576268969 May 05 02:27:01 PM PDT 24 May 05 02:27:02 PM PDT 24 41654140 ps
T898 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2305192604 May 05 02:28:42 PM PDT 24 May 05 02:28:44 PM PDT 24 52142395 ps
T899 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3350142805 May 05 02:28:09 PM PDT 24 May 05 02:28:10 PM PDT 24 67865944 ps
T900 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.902109062 May 05 02:28:06 PM PDT 24 May 05 02:28:12 PM PDT 24 329732279 ps
T253 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1198213268 May 05 02:27:33 PM PDT 24 May 05 02:27:35 PM PDT 24 48218825 ps
T901 /workspace/coverage/cover_reg_top/25.edn_intr_test.4075402258 May 05 02:29:08 PM PDT 24 May 05 02:29:09 PM PDT 24 12053742 ps
T902 /workspace/coverage/cover_reg_top/42.edn_intr_test.3985650680 May 05 02:29:18 PM PDT 24 May 05 02:29:20 PM PDT 24 126518472 ps
T903 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3267315724 May 05 02:28:53 PM PDT 24 May 05 02:28:54 PM PDT 24 14436008 ps
T228 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3118273373 May 05 02:28:50 PM PDT 24 May 05 02:28:52 PM PDT 24 104548047 ps
T904 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3035176304 May 05 02:27:36 PM PDT 24 May 05 02:27:38 PM PDT 24 30849056 ps
T905 /workspace/coverage/cover_reg_top/11.edn_csr_rw.208433100 May 05 02:28:27 PM PDT 24 May 05 02:28:28 PM PDT 24 21728475 ps
T906 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4248858840 May 05 02:28:45 PM PDT 24 May 05 02:28:48 PM PDT 24 58708915 ps
T907 /workspace/coverage/cover_reg_top/3.edn_intr_test.1630885846 May 05 02:27:36 PM PDT 24 May 05 02:27:38 PM PDT 24 56804023 ps
T908 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1436259907 May 05 02:27:38 PM PDT 24 May 05 02:27:40 PM PDT 24 23141577 ps
T909 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2873001222 May 05 02:28:47 PM PDT 24 May 05 02:28:48 PM PDT 24 21446390 ps
T910 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4096249827 May 05 02:28:24 PM PDT 24 May 05 02:28:25 PM PDT 24 210495281 ps
T911 /workspace/coverage/cover_reg_top/1.edn_csr_rw.1147739409 May 05 02:27:29 PM PDT 24 May 05 02:27:31 PM PDT 24 57178381 ps
T912 /workspace/coverage/cover_reg_top/14.edn_intr_test.4156214196 May 05 02:28:42 PM PDT 24 May 05 02:28:43 PM PDT 24 66883721 ps
T229 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1167783134 May 05 02:28:49 PM PDT 24 May 05 02:28:51 PM PDT 24 18884446 ps
T913 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2384784627 May 05 02:28:47 PM PDT 24 May 05 02:28:49 PM PDT 24 18699163 ps
T914 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3535843171 May 05 02:27:11 PM PDT 24 May 05 02:27:12 PM PDT 24 106140667 ps
T915 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.49202041 May 05 02:28:37 PM PDT 24 May 05 02:28:39 PM PDT 24 19084967 ps
T916 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2996873591 May 05 02:27:41 PM PDT 24 May 05 02:27:43 PM PDT 24 35236539 ps
T917 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1678874401 May 05 02:28:03 PM PDT 24 May 05 02:28:05 PM PDT 24 88584620 ps
T254 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2635133918 May 05 02:28:00 PM PDT 24 May 05 02:28:03 PM PDT 24 330409808 ps
T918 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3498909267 May 05 02:27:41 PM PDT 24 May 05 02:27:43 PM PDT 24 29519961 ps
T919 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3740306808 May 05 02:26:52 PM PDT 24 May 05 02:26:54 PM PDT 24 108506618 ps
T920 /workspace/coverage/cover_reg_top/12.edn_csr_rw.170005089 May 05 02:28:34 PM PDT 24 May 05 02:28:35 PM PDT 24 13818294 ps
T921 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1496912269 May 05 02:29:01 PM PDT 24 May 05 02:29:02 PM PDT 24 16063924 ps
T922 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1785821215 May 05 02:28:54 PM PDT 24 May 05 02:28:56 PM PDT 24 311471568 ps
T923 /workspace/coverage/cover_reg_top/45.edn_intr_test.3577484683 May 05 02:29:17 PM PDT 24 May 05 02:29:19 PM PDT 24 31896587 ps
T924 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3351342442 May 05 02:28:55 PM PDT 24 May 05 02:28:57 PM PDT 24 154141140 ps
T925 /workspace/coverage/cover_reg_top/26.edn_intr_test.4176584741 May 05 02:29:09 PM PDT 24 May 05 02:29:10 PM PDT 24 23566214 ps
T926 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.544677401 May 05 02:27:46 PM PDT 24 May 05 02:27:48 PM PDT 24 54667808 ps
T927 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2792943433 May 05 02:27:45 PM PDT 24 May 05 02:27:48 PM PDT 24 328371687 ps
T928 /workspace/coverage/cover_reg_top/2.edn_intr_test.1498135238 May 05 02:27:33 PM PDT 24 May 05 02:27:34 PM PDT 24 24815313 ps
T929 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3973502044 May 05 02:29:01 PM PDT 24 May 05 02:29:02 PM PDT 24 40336930 ps
T930 /workspace/coverage/cover_reg_top/32.edn_intr_test.4008175459 May 05 02:29:15 PM PDT 24 May 05 02:29:16 PM PDT 24 35436840 ps
T931 /workspace/coverage/cover_reg_top/29.edn_intr_test.3293697924 May 05 02:29:09 PM PDT 24 May 05 02:29:11 PM PDT 24 10871578 ps
T932 /workspace/coverage/cover_reg_top/31.edn_intr_test.3944834433 May 05 02:29:08 PM PDT 24 May 05 02:29:09 PM PDT 24 17324998 ps
T933 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.219434232 May 05 02:27:58 PM PDT 24 May 05 02:28:00 PM PDT 24 150201481 ps
T934 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2233958076 May 05 02:28:14 PM PDT 24 May 05 02:28:16 PM PDT 24 195058389 ps
T935 /workspace/coverage/cover_reg_top/4.edn_intr_test.4185164166 May 05 02:27:50 PM PDT 24 May 05 02:27:51 PM PDT 24 22023327 ps
T936 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.806407519 May 05 02:28:15 PM PDT 24 May 05 02:28:16 PM PDT 24 138534703 ps
T230 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1081610158 May 05 02:27:34 PM PDT 24 May 05 02:27:36 PM PDT 24 14748891 ps
T937 /workspace/coverage/cover_reg_top/6.edn_intr_test.2256628287 May 05 02:28:04 PM PDT 24 May 05 02:28:05 PM PDT 24 40099938 ps
T938 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3864390602 May 05 02:28:37 PM PDT 24 May 05 02:28:39 PM PDT 24 52664557 ps
T939 /workspace/coverage/cover_reg_top/28.edn_intr_test.716964403 May 05 02:29:09 PM PDT 24 May 05 02:29:11 PM PDT 24 14791967 ps
T940 /workspace/coverage/cover_reg_top/7.edn_csr_rw.305900364 May 05 02:28:10 PM PDT 24 May 05 02:28:11 PM PDT 24 53096709 ps
T941 /workspace/coverage/cover_reg_top/30.edn_intr_test.2958065727 May 05 02:29:09 PM PDT 24 May 05 02:29:11 PM PDT 24 17881595 ps
T942 /workspace/coverage/cover_reg_top/46.edn_intr_test.3016043111 May 05 02:29:23 PM PDT 24 May 05 02:29:25 PM PDT 24 16624905 ps
T943 /workspace/coverage/cover_reg_top/8.edn_tl_errors.2166018103 May 05 02:28:10 PM PDT 24 May 05 02:28:12 PM PDT 24 33423471 ps
T944 /workspace/coverage/cover_reg_top/17.edn_intr_test.3647652731 May 05 02:28:53 PM PDT 24 May 05 02:28:54 PM PDT 24 38722569 ps
T945 /workspace/coverage/cover_reg_top/13.edn_intr_test.4096125981 May 05 02:28:35 PM PDT 24 May 05 02:28:37 PM PDT 24 28844134 ps
T946 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.624373303 May 05 02:27:41 PM PDT 24 May 05 02:27:45 PM PDT 24 216974751 ps
T947 /workspace/coverage/cover_reg_top/7.edn_tl_errors.861954123 May 05 02:28:09 PM PDT 24 May 05 02:28:13 PM PDT 24 183156262 ps
T948 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3892142533 May 05 02:28:13 PM PDT 24 May 05 02:28:15 PM PDT 24 35191551 ps
T949 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1962584259 May 05 02:28:36 PM PDT 24 May 05 02:28:38 PM PDT 24 30443931 ps
T950 /workspace/coverage/cover_reg_top/1.edn_intr_test.3661271230 May 05 02:27:21 PM PDT 24 May 05 02:27:23 PM PDT 24 73129033 ps
T231 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1978189666 May 05 02:28:43 PM PDT 24 May 05 02:28:45 PM PDT 24 110954043 ps
T951 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1934105562 May 05 02:28:51 PM PDT 24 May 05 02:28:54 PM PDT 24 430142101 ps
T952 /workspace/coverage/cover_reg_top/35.edn_intr_test.2043462824 May 05 02:29:13 PM PDT 24 May 05 02:29:14 PM PDT 24 15377029 ps
T953 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3524037819 May 05 02:28:38 PM PDT 24 May 05 02:28:42 PM PDT 24 404336567 ps
T255 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3628934461 May 05 02:27:21 PM PDT 24 May 05 02:27:23 PM PDT 24 57698695 ps
T954 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.830339160 May 05 02:28:48 PM PDT 24 May 05 02:28:50 PM PDT 24 180193458 ps
T955 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1453908834 May 05 02:27:28 PM PDT 24 May 05 02:27:29 PM PDT 24 93184516 ps
T956 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3655142295 May 05 02:27:27 PM PDT 24 May 05 02:27:29 PM PDT 24 86361715 ps
T957 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2129561618 May 05 02:28:45 PM PDT 24 May 05 02:28:48 PM PDT 24 29531133 ps
T958 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1645996111 May 05 02:28:53 PM PDT 24 May 05 02:28:56 PM PDT 24 48015114 ps
T959 /workspace/coverage/cover_reg_top/39.edn_intr_test.2703311224 May 05 02:29:19 PM PDT 24 May 05 02:29:20 PM PDT 24 19855516 ps
T960 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1872768447 May 05 02:27:47 PM PDT 24 May 05 02:27:49 PM PDT 24 168248046 ps
T961 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1107734180 May 05 02:28:01 PM PDT 24 May 05 02:28:03 PM PDT 24 72320625 ps
T962 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1753594550 May 05 02:28:52 PM PDT 24 May 05 02:28:55 PM PDT 24 35738147 ps
T963 /workspace/coverage/cover_reg_top/49.edn_intr_test.1454079979 May 05 02:29:25 PM PDT 24 May 05 02:29:26 PM PDT 24 24559481 ps
T964 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2751391478 May 05 02:27:32 PM PDT 24 May 05 02:27:34 PM PDT 24 52887021 ps
T965 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.779488801 May 05 02:28:24 PM PDT 24 May 05 02:28:26 PM PDT 24 41748309 ps
T966 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1528035645 May 05 02:28:50 PM PDT 24 May 05 02:28:51 PM PDT 24 35981702 ps
T967 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3860880941 May 05 02:28:43 PM PDT 24 May 05 02:28:45 PM PDT 24 33902768 ps
T968 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2913474648 May 05 02:28:25 PM PDT 24 May 05 02:28:28 PM PDT 24 179683941 ps
T969 /workspace/coverage/cover_reg_top/11.edn_intr_test.88046372 May 05 02:28:24 PM PDT 24 May 05 02:28:26 PM PDT 24 43238256 ps
T970 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3652521905 May 05 02:28:10 PM PDT 24 May 05 02:28:13 PM PDT 24 235904719 ps
T971 /workspace/coverage/cover_reg_top/16.edn_tl_errors.4186950236 May 05 02:28:49 PM PDT 24 May 05 02:28:54 PM PDT 24 191568990 ps
T972 /workspace/coverage/cover_reg_top/17.edn_tl_errors.138393667 May 05 02:28:48 PM PDT 24 May 05 02:28:51 PM PDT 24 59204100 ps
T973 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2318031881 May 05 02:28:45 PM PDT 24 May 05 02:28:46 PM PDT 24 22885798 ps
T233 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.773197019 May 05 02:27:56 PM PDT 24 May 05 02:27:57 PM PDT 24 367797690 ps
T974 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1722572540 May 05 02:28:32 PM PDT 24 May 05 02:28:34 PM PDT 24 42414350 ps
T232 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1421711115 May 05 02:28:42 PM PDT 24 May 05 02:28:44 PM PDT 24 62674810 ps
T975 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3266150917 May 05 02:28:15 PM PDT 24 May 05 02:28:17 PM PDT 24 312415501 ps
T976 /workspace/coverage/cover_reg_top/43.edn_intr_test.4123426401 May 05 02:29:19 PM PDT 24 May 05 02:29:21 PM PDT 24 34668475 ps

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1886378988
Short name T1
Test name
Test status
Simulation time 34093152064 ps
CPU time 174.17 seconds
Started May 05 01:54:05 PM PDT 24
Finished May 05 01:57:00 PM PDT 24
Peak memory 217904 kb
Host smart-f80d1631-5c14-4d43-880c-4a331f08b473
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886378988 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1886378988
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.4142761865
Short name T47
Test name
Test status
Simulation time 45347800 ps
CPU time 1.08 seconds
Started May 05 01:53:48 PM PDT 24
Finished May 05 01:53:49 PM PDT 24
Peak memory 217120 kb
Host smart-1053a4f1-b697-4712-b792-91714c26daee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142761865 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.4142761865
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_alert.744943425
Short name T33
Test name
Test status
Simulation time 61102361 ps
CPU time 1.17 seconds
Started May 05 01:52:35 PM PDT 24
Finished May 05 01:52:37 PM PDT 24
Peak memory 216024 kb
Host smart-09905eae-fe56-4efc-adb0-cc22b4c68cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744943425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.744943425
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/241.edn_genbits.866359324
Short name T53
Test name
Test status
Simulation time 62144969 ps
CPU time 1.59 seconds
Started May 05 01:54:48 PM PDT 24
Finished May 05 01:54:50 PM PDT 24
Peak memory 218744 kb
Host smart-6515f3a7-6b55-42c1-8c92-2e4789fff196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866359324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.866359324
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2131776589
Short name T15
Test name
Test status
Simulation time 1871258267 ps
CPU time 8.16 seconds
Started May 05 01:52:31 PM PDT 24
Finished May 05 01:52:39 PM PDT 24
Peak memory 239116 kb
Host smart-f279eab0-965f-4ab5-b907-e90384c9464d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131776589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2131776589
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/21.edn_intr.2128472845
Short name T40
Test name
Test status
Simulation time 110069171 ps
CPU time 0.88 seconds
Started May 05 01:53:22 PM PDT 24
Finished May 05 01:53:23 PM PDT 24
Peak memory 215948 kb
Host smart-79e31542-2720-47dd-9666-4b471f6bf053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128472845 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2128472845
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/13.edn_disable.1189654001
Short name T89
Test name
Test status
Simulation time 13202553 ps
CPU time 0.91 seconds
Started May 05 01:53:10 PM PDT 24
Finished May 05 01:53:12 PM PDT 24
Peak memory 216788 kb
Host smart-84253ce0-aac2-4d95-a46b-cc36f7f166e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189654001 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1189654001
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/59.edn_genbits.1865154604
Short name T10
Test name
Test status
Simulation time 31376484 ps
CPU time 1.27 seconds
Started May 05 01:54:19 PM PDT 24
Finished May 05 01:54:21 PM PDT 24
Peak memory 219928 kb
Host smart-2c69e674-153f-421d-95cc-5de09ff34972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865154604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1865154604
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.908637765
Short name T59
Test name
Test status
Simulation time 28834271 ps
CPU time 1.28 seconds
Started May 05 01:53:41 PM PDT 24
Finished May 05 01:53:44 PM PDT 24
Peak memory 216040 kb
Host smart-0dc54186-85e9-46c1-a277-4606ff1c259a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908637765 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.908637765
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3988023456
Short name T25
Test name
Test status
Simulation time 89512126 ps
CPU time 1.14 seconds
Started May 05 01:54:48 PM PDT 24
Finished May 05 01:54:50 PM PDT 24
Peak memory 217416 kb
Host smart-e2e644bc-d94d-41de-99e4-c7d88d5502fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988023456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3988023456
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.2252723604
Short name T27
Test name
Test status
Simulation time 53907599 ps
CPU time 0.91 seconds
Started May 05 01:52:26 PM PDT 24
Finished May 05 01:52:28 PM PDT 24
Peak memory 207420 kb
Host smart-62d20931-92ee-488b-8679-63161dda24bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252723604 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2252723604
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_alert.1903593351
Short name T56
Test name
Test status
Simulation time 30139063 ps
CPU time 1.29 seconds
Started May 05 01:52:25 PM PDT 24
Finished May 05 01:52:26 PM PDT 24
Peak memory 216012 kb
Host smart-20837291-cc3d-4eba-a720-c6df64835ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903593351 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1903593351
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.389044492
Short name T195
Test name
Test status
Simulation time 82422677205 ps
CPU time 1042.8 seconds
Started May 05 01:53:12 PM PDT 24
Finished May 05 02:10:36 PM PDT 24
Peak memory 223864 kb
Host smart-9994ad29-f21c-421f-8e73-f3c73ee18713
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389044492 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.389044492
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2635133918
Short name T254
Test name
Test status
Simulation time 330409808 ps
CPU time 2.59 seconds
Started May 05 02:28:00 PM PDT 24
Finished May 05 02:28:03 PM PDT 24
Peak memory 206836 kb
Host smart-194a0fdc-d5bf-42fe-93fe-22669755032e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635133918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2635133918
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.864947075
Short name T124
Test name
Test status
Simulation time 166973647 ps
CPU time 1.16 seconds
Started May 05 01:52:41 PM PDT 24
Finished May 05 01:52:43 PM PDT 24
Peak memory 217216 kb
Host smart-01ee8f97-d3ba-4038-b400-fb547947123a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864947075 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.864947075
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_alert.1605261857
Short name T78
Test name
Test status
Simulation time 37529405 ps
CPU time 1.14 seconds
Started May 05 01:53:49 PM PDT 24
Finished May 05 01:53:51 PM PDT 24
Peak memory 216072 kb
Host smart-e02c95bb-786f-419d-8441-186669751b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605261857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1605261857
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/24.edn_disable.4222844979
Short name T176
Test name
Test status
Simulation time 44806209 ps
CPU time 0.91 seconds
Started May 05 01:53:34 PM PDT 24
Finished May 05 01:53:35 PM PDT 24
Peak memory 216756 kb
Host smart-267d0ad4-31ab-451e-b51e-0a6b550cf943
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222844979 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.4222844979
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable.927496222
Short name T158
Test name
Test status
Simulation time 64770989 ps
CPU time 0.9 seconds
Started May 05 01:53:17 PM PDT 24
Finished May 05 01:53:18 PM PDT 24
Peak memory 216604 kb
Host smart-37433c60-e8f9-4a00-b052-64eab5598dd8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927496222 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.927496222
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable.1560077848
Short name T149
Test name
Test status
Simulation time 20131346 ps
CPU time 0.84 seconds
Started May 05 01:54:03 PM PDT 24
Finished May 05 01:54:04 PM PDT 24
Peak memory 216636 kb
Host smart-9968b675-527e-413e-ad69-d783d09dc327
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560077848 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1560077848
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.4091116749
Short name T216
Test name
Test status
Simulation time 13020282 ps
CPU time 0.82 seconds
Started May 05 02:28:23 PM PDT 24
Finished May 05 02:28:25 PM PDT 24
Peak memory 206476 kb
Host smart-5aaf4b1d-254b-4ccd-8cb9-0854a4f6f4e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091116749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.4091116749
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.4087340176
Short name T19
Test name
Test status
Simulation time 158437820 ps
CPU time 1.06 seconds
Started May 05 01:53:23 PM PDT 24
Finished May 05 01:53:24 PM PDT 24
Peak memory 217284 kb
Host smart-cd6d6ffc-f249-4355-9c24-b946aea30fa5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087340176 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.4087340176
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/52.edn_err.2434091689
Short name T63
Test name
Test status
Simulation time 20471398 ps
CPU time 1.2 seconds
Started May 05 01:54:12 PM PDT 24
Finished May 05 01:54:14 PM PDT 24
Peak memory 224448 kb
Host smart-04c9fd6c-9c5c-4445-bfc3-46eda0ecdd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434091689 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2434091689
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.827457304
Short name T9
Test name
Test status
Simulation time 90381823 ps
CPU time 1.16 seconds
Started May 05 01:53:35 PM PDT 24
Finished May 05 01:53:37 PM PDT 24
Peak memory 219828 kb
Host smart-f74acd06-d8b8-4246-889c-f99262b17f9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827457304 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.827457304
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_intr.2906887464
Short name T38
Test name
Test status
Simulation time 21148576 ps
CPU time 1.08 seconds
Started May 05 01:53:49 PM PDT 24
Finished May 05 01:53:50 PM PDT 24
Peak memory 216264 kb
Host smart-8d92892a-4cb6-4acb-9d69-356c567550ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906887464 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2906887464
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/109.edn_genbits.4179458720
Short name T262
Test name
Test status
Simulation time 47516898 ps
CPU time 1.71 seconds
Started May 05 01:54:32 PM PDT 24
Finished May 05 01:54:34 PM PDT 24
Peak memory 220072 kb
Host smart-7b74dcac-19a1-49ab-9fb8-d9aa77486680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179458720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.4179458720
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3403914744
Short name T39
Test name
Test status
Simulation time 21440295 ps
CPU time 1.09 seconds
Started May 05 01:53:08 PM PDT 24
Finished May 05 01:53:09 PM PDT 24
Peak memory 216272 kb
Host smart-b406d4fe-b87f-4b48-9547-412d6ef3a66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403914744 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3403914744
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/14.edn_disable.925941243
Short name T52
Test name
Test status
Simulation time 16239397 ps
CPU time 0.88 seconds
Started May 05 01:53:14 PM PDT 24
Finished May 05 01:53:15 PM PDT 24
Peak memory 215776 kb
Host smart-383781ec-2674-46cf-9361-5c6422c36e2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925941243 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.925941243
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/33.edn_alert.451360979
Short name T188
Test name
Test status
Simulation time 428129286 ps
CPU time 1.54 seconds
Started May 05 01:53:49 PM PDT 24
Finished May 05 01:53:51 PM PDT 24
Peak memory 216084 kb
Host smart-68bdfe44-0fe3-4430-8d2b-8531e928c81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451360979 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.451360979
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable.3078907097
Short name T101
Test name
Test status
Simulation time 40601169 ps
CPU time 0.84 seconds
Started May 05 01:52:25 PM PDT 24
Finished May 05 01:52:26 PM PDT 24
Peak memory 216596 kb
Host smart-6ea8e9af-dbc2-4a51-ae73-8e2c1b766a30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078907097 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3078907097
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable.3967504529
Short name T174
Test name
Test status
Simulation time 77844854 ps
CPU time 0.88 seconds
Started May 05 01:53:41 PM PDT 24
Finished May 05 01:53:43 PM PDT 24
Peak memory 216584 kb
Host smart-ae5dc617-8c10-4742-8ffb-e32476a7a4ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967504529 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3967504529
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1173040178
Short name T716
Test name
Test status
Simulation time 99722467 ps
CPU time 1.12 seconds
Started May 05 01:52:32 PM PDT 24
Finished May 05 01:52:34 PM PDT 24
Peak memory 219816 kb
Host smart-7db319ba-256f-4541-b9f3-7af79df1e7dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173040178 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1173040178
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_disable.1736866142
Short name T169
Test name
Test status
Simulation time 11009672 ps
CPU time 0.87 seconds
Started May 05 01:53:51 PM PDT 24
Finished May 05 01:53:53 PM PDT 24
Peak memory 216616 kb
Host smart-10ad2407-aa9e-4e63-a109-05641ac246fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736866142 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1736866142
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.390037828
Short name T171
Test name
Test status
Simulation time 38932300 ps
CPU time 1.23 seconds
Started May 05 01:53:53 PM PDT 24
Finished May 05 01:53:55 PM PDT 24
Peak memory 217120 kb
Host smart-6a16357d-da8b-48cb-b504-5035cd38b560
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390037828 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.390037828
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_genbits.1211664937
Short name T268
Test name
Test status
Simulation time 147665472 ps
CPU time 2.25 seconds
Started May 05 01:53:48 PM PDT 24
Finished May 05 01:53:51 PM PDT 24
Peak memory 219928 kb
Host smart-41984fd6-017d-4749-8b7a-e93f40324b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211664937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1211664937
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_regwen.3392129473
Short name T28
Test name
Test status
Simulation time 203981607 ps
CPU time 0.96 seconds
Started May 05 01:52:45 PM PDT 24
Finished May 05 01:52:47 PM PDT 24
Peak memory 207396 kb
Host smart-373999fc-d311-429f-8964-86b35b1ab6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392129473 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3392129473
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_alert_test.2379065387
Short name T22
Test name
Test status
Simulation time 76106165 ps
CPU time 0.86 seconds
Started May 05 01:52:43 PM PDT 24
Finished May 05 01:52:44 PM PDT 24
Peak memory 215004 kb
Host smart-03832015-0c19-47d6-8035-371f14413d9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379065387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2379065387
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/120.edn_genbits.278439391
Short name T49
Test name
Test status
Simulation time 92006012 ps
CPU time 1.18 seconds
Started May 05 01:54:40 PM PDT 24
Finished May 05 01:54:42 PM PDT 24
Peak memory 215616 kb
Host smart-fd29f764-8a53-457a-ab61-e095881e97a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278439391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.278439391
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3943729488
Short name T223
Test name
Test status
Simulation time 159699956 ps
CPU time 1.62 seconds
Started May 05 02:27:05 PM PDT 24
Finished May 05 02:27:07 PM PDT 24
Peak memory 206712 kb
Host smart-620414cb-3d92-45ac-892c-46ab9403dd64
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943729488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3943729488
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/default/124.edn_genbits.1120952103
Short name T20
Test name
Test status
Simulation time 57237777 ps
CPU time 1.2 seconds
Started May 05 01:54:31 PM PDT 24
Finished May 05 01:54:33 PM PDT 24
Peak memory 219268 kb
Host smart-6edfef94-129a-4c98-84c9-1a0b700480f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120952103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1120952103
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_alert.2946724319
Short name T258
Test name
Test status
Simulation time 89182500 ps
CPU time 1.19 seconds
Started May 05 01:53:47 PM PDT 24
Finished May 05 01:53:48 PM PDT 24
Peak memory 216076 kb
Host smart-f2ad1173-3b9a-4089-a2b0-6400979f36e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946724319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2946724319
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/4.edn_regwen.1377284481
Short name T298
Test name
Test status
Simulation time 36878259 ps
CPU time 0.91 seconds
Started May 05 01:52:40 PM PDT 24
Finished May 05 01:52:41 PM PDT 24
Peak memory 207436 kb
Host smart-7ba261fa-48cc-43c9-9728-a1f0bcfdb4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377284481 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1377284481
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/290.edn_genbits.121416129
Short name T31
Test name
Test status
Simulation time 64655743 ps
CPU time 1.51 seconds
Started May 05 01:55:05 PM PDT 24
Finished May 05 01:55:07 PM PDT 24
Peak memory 218872 kb
Host smart-d5d6c998-69eb-4d9d-af77-8098b67655a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121416129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.121416129
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2601455307
Short name T37
Test name
Test status
Simulation time 21847211 ps
CPU time 0.89 seconds
Started May 05 01:53:53 PM PDT 24
Finished May 05 01:53:54 PM PDT 24
Peak memory 216352 kb
Host smart-9083021c-e271-40f3-ac71-08337695d99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601455307 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2601455307
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1325792635
Short name T509
Test name
Test status
Simulation time 42303900785 ps
CPU time 990.18 seconds
Started May 05 01:52:26 PM PDT 24
Finished May 05 02:08:56 PM PDT 24
Peak memory 223964 kb
Host smart-d6cc4a0c-e915-4301-813c-9836d4d223f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325792635 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1325792635
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/107.edn_genbits.2207285481
Short name T670
Test name
Test status
Simulation time 61035596 ps
CPU time 1.33 seconds
Started May 05 01:54:26 PM PDT 24
Finished May 05 01:54:28 PM PDT 24
Peak memory 217352 kb
Host smart-a28e9289-c1fe-47f5-a739-af586fb204fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207285481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2207285481
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1878890882
Short name T284
Test name
Test status
Simulation time 98699987 ps
CPU time 1.52 seconds
Started May 05 01:54:34 PM PDT 24
Finished May 05 01:54:36 PM PDT 24
Peak memory 218784 kb
Host smart-7df8a762-aa7c-480a-b618-cb55c9a2ba79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878890882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1878890882
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.1476006317
Short name T276
Test name
Test status
Simulation time 115489572 ps
CPU time 1.49 seconds
Started May 05 01:54:36 PM PDT 24
Finished May 05 01:54:38 PM PDT 24
Peak memory 218412 kb
Host smart-1e9f1a0a-4795-4821-8414-19b7ce856cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476006317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1476006317
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1718667787
Short name T680
Test name
Test status
Simulation time 42259841 ps
CPU time 1.43 seconds
Started May 05 01:54:35 PM PDT 24
Finished May 05 01:54:37 PM PDT 24
Peak memory 217324 kb
Host smart-d3b7fcd7-94f4-4772-a1e5-221ecb16d382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718667787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1718667787
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2092113528
Short name T725
Test name
Test status
Simulation time 51995438 ps
CPU time 1.87 seconds
Started May 05 01:54:33 PM PDT 24
Finished May 05 01:54:35 PM PDT 24
Peak memory 218696 kb
Host smart-dd296895-e8a9-4a4f-b6c5-a50f98d4e0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092113528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2092113528
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1048367905
Short name T293
Test name
Test status
Simulation time 29918263 ps
CPU time 1.27 seconds
Started May 05 01:53:11 PM PDT 24
Finished May 05 01:53:13 PM PDT 24
Peak memory 216076 kb
Host smart-67020347-9bff-45da-8ffa-92aa8d971ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048367905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1048367905
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.745173364
Short name T419
Test name
Test status
Simulation time 51606425 ps
CPU time 1.25 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:40 PM PDT 24
Peak memory 218600 kb
Host smart-36475f95-a5bb-4ae2-abcf-15bcff914014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745173364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.745173364
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.420886589
Short name T273
Test name
Test status
Simulation time 30286777 ps
CPU time 1.35 seconds
Started May 05 01:54:42 PM PDT 24
Finished May 05 01:54:44 PM PDT 24
Peak memory 217444 kb
Host smart-10acf056-2093-45b9-920d-bfb94cd82a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420886589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.420886589
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/240.edn_genbits.3312472975
Short name T23
Test name
Test status
Simulation time 110736759 ps
CPU time 1.24 seconds
Started May 05 01:54:47 PM PDT 24
Finished May 05 01:54:49 PM PDT 24
Peak memory 218812 kb
Host smart-e84d3085-fd6d-433e-b5d2-f45ec97f1fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312472975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3312472975
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_alert.188980076
Short name T295
Test name
Test status
Simulation time 277843057 ps
CPU time 1.35 seconds
Started May 05 01:53:40 PM PDT 24
Finished May 05 01:53:42 PM PDT 24
Peak memory 216052 kb
Host smart-b6defd94-ce4a-4b16-bd63-0aa4b4205876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188980076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.188980076
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert.938679447
Short name T247
Test name
Test status
Simulation time 80620623 ps
CPU time 1.06 seconds
Started May 05 01:53:59 PM PDT 24
Finished May 05 01:54:01 PM PDT 24
Peak memory 216080 kb
Host smart-015a76a2-576e-4647-9400-5efc8ffd8fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938679447 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.938679447
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/33.edn_intr.3233976734
Short name T107
Test name
Test status
Simulation time 27558740 ps
CPU time 0.99 seconds
Started May 05 01:53:49 PM PDT 24
Finished May 05 01:53:50 PM PDT 24
Peak memory 216304 kb
Host smart-bb444d3b-f664-4efd-9149-683bfcfbcbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233976734 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3233976734
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/12.edn_err.1449999894
Short name T6
Test name
Test status
Simulation time 35354170 ps
CPU time 1.06 seconds
Started May 05 01:53:09 PM PDT 24
Finished May 05 01:53:11 PM PDT 24
Peak memory 230012 kb
Host smart-ef9b1f42-d10e-4a9c-a94e-0af422cd988e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449999894 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1449999894
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2717264704
Short name T653
Test name
Test status
Simulation time 51024835 ps
CPU time 1.32 seconds
Started May 05 01:53:14 PM PDT 24
Finished May 05 01:53:16 PM PDT 24
Peak memory 219016 kb
Host smart-fae3fdfa-cc35-4f80-bab5-cec49df1dd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717264704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2717264704
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.4148008440
Short name T219
Test name
Test status
Simulation time 4929674051 ps
CPU time 7.06 seconds
Started May 05 02:27:00 PM PDT 24
Finished May 05 02:27:07 PM PDT 24
Peak memory 206772 kb
Host smart-ffa75731-fed6-42b6-9a8d-178c75189a4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148008440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.4148008440
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3576268969
Short name T227
Test name
Test status
Simulation time 41654140 ps
CPU time 0.83 seconds
Started May 05 02:27:01 PM PDT 24
Finished May 05 02:27:02 PM PDT 24
Peak memory 206456 kb
Host smart-50e24b23-75d4-419f-a937-7212dfeec04d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576268969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3576268969
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2229882149
Short name T872
Test name
Test status
Simulation time 21570855 ps
CPU time 1.37 seconds
Started May 05 02:27:09 PM PDT 24
Finished May 05 02:27:11 PM PDT 24
Peak memory 215072 kb
Host smart-14f4f3e6-2291-4a3f-8a06-5bb367b7616f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229882149 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2229882149
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2614601499
Short name T226
Test name
Test status
Simulation time 24442236 ps
CPU time 0.91 seconds
Started May 05 02:27:01 PM PDT 24
Finished May 05 02:27:02 PM PDT 24
Peak memory 206736 kb
Host smart-5d308019-9946-41c6-afc2-c68ada1ee61c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614601499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2614601499
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1570282204
Short name T887
Test name
Test status
Simulation time 35781869 ps
CPU time 0.82 seconds
Started May 05 02:27:02 PM PDT 24
Finished May 05 02:27:03 PM PDT 24
Peak memory 206444 kb
Host smart-b4db11c2-de78-483c-aeba-695f8d852f3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570282204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1570282204
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3535843171
Short name T914
Test name
Test status
Simulation time 106140667 ps
CPU time 1.25 seconds
Started May 05 02:27:11 PM PDT 24
Finished May 05 02:27:12 PM PDT 24
Peak memory 206752 kb
Host smart-5be6319d-7e68-480c-ab2f-ee694b0c7eba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535843171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3535843171
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3740306808
Short name T919
Test name
Test status
Simulation time 108506618 ps
CPU time 1.94 seconds
Started May 05 02:26:52 PM PDT 24
Finished May 05 02:26:54 PM PDT 24
Peak memory 214960 kb
Host smart-7dbc8571-8c87-4490-815a-1fa4c1da3636
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740306808 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3740306808
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.609258410
Short name T243
Test name
Test status
Simulation time 159981706 ps
CPU time 1.53 seconds
Started May 05 02:26:52 PM PDT 24
Finished May 05 02:26:54 PM PDT 24
Peak memory 207004 kb
Host smart-7334484e-9702-4035-b19c-e68ccb427773
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609258410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.609258410
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1453908834
Short name T955
Test name
Test status
Simulation time 93184516 ps
CPU time 1.02 seconds
Started May 05 02:27:28 PM PDT 24
Finished May 05 02:27:29 PM PDT 24
Peak memory 206724 kb
Host smart-4cd0d9f0-6077-424a-a230-1cacf2ca2769
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453908834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1453908834
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3469345848
Short name T876
Test name
Test status
Simulation time 73726104 ps
CPU time 2.14 seconds
Started May 05 02:27:29 PM PDT 24
Finished May 05 02:27:32 PM PDT 24
Peak memory 206792 kb
Host smart-9b10dd36-8f88-4515-b297-ebee51b9b255
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469345848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3469345848
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3407942090
Short name T897
Test name
Test status
Simulation time 167361900 ps
CPU time 0.93 seconds
Started May 05 02:27:25 PM PDT 24
Finished May 05 02:27:26 PM PDT 24
Peak memory 206492 kb
Host smart-c37a2519-63ca-479e-b8a8-c0f6de3f0d83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407942090 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3407942090
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3655142295
Short name T956
Test name
Test status
Simulation time 86361715 ps
CPU time 1.26 seconds
Started May 05 02:27:27 PM PDT 24
Finished May 05 02:27:29 PM PDT 24
Peak memory 215000 kb
Host smart-10b292e9-bfd3-4c0b-8f90-a6c4fb972dd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655142295 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3655142295
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1147739409
Short name T911
Test name
Test status
Simulation time 57178381 ps
CPU time 0.93 seconds
Started May 05 02:27:29 PM PDT 24
Finished May 05 02:27:31 PM PDT 24
Peak memory 206624 kb
Host smart-18c17bb8-a58d-4955-977e-bb7bd789df69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147739409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1147739409
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3661271230
Short name T950
Test name
Test status
Simulation time 73129033 ps
CPU time 0.86 seconds
Started May 05 02:27:21 PM PDT 24
Finished May 05 02:27:23 PM PDT 24
Peak memory 206612 kb
Host smart-647e0539-2275-462e-92ac-e9fdafd2fb1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661271230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3661271230
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2751391478
Short name T964
Test name
Test status
Simulation time 52887021 ps
CPU time 1.01 seconds
Started May 05 02:27:32 PM PDT 24
Finished May 05 02:27:34 PM PDT 24
Peak memory 206760 kb
Host smart-a9497f26-fe5e-48df-a809-6cc2daebf37c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751391478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2751391478
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3420085260
Short name T857
Test name
Test status
Simulation time 507605560 ps
CPU time 4.52 seconds
Started May 05 02:27:17 PM PDT 24
Finished May 05 02:27:22 PM PDT 24
Peak memory 214948 kb
Host smart-e286d034-7850-434b-8c82-05ce2ca1f6e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420085260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3420085260
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3628934461
Short name T255
Test name
Test status
Simulation time 57698695 ps
CPU time 1.74 seconds
Started May 05 02:27:21 PM PDT 24
Finished May 05 02:27:23 PM PDT 24
Peak memory 206664 kb
Host smart-9b8d6095-804b-4161-ab02-61f68efce61f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628934461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3628934461
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4096249827
Short name T910
Test name
Test status
Simulation time 210495281 ps
CPU time 1.03 seconds
Started May 05 02:28:24 PM PDT 24
Finished May 05 02:28:25 PM PDT 24
Peak memory 206756 kb
Host smart-a640155a-43e8-43fe-9bff-0275018c4c1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096249827 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.4096249827
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1738494748
Short name T855
Test name
Test status
Simulation time 79698383 ps
CPU time 0.9 seconds
Started May 05 02:28:26 PM PDT 24
Finished May 05 02:28:27 PM PDT 24
Peak memory 206688 kb
Host smart-cfc849d2-de9d-49d1-84ec-67580d859ebb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738494748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1738494748
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.779488801
Short name T965
Test name
Test status
Simulation time 41748309 ps
CPU time 1.58 seconds
Started May 05 02:28:24 PM PDT 24
Finished May 05 02:28:26 PM PDT 24
Peak memory 206748 kb
Host smart-4e510dc7-c4b5-4fc8-8d33-7d8d284c1adf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779488801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.779488801
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.4280465011
Short name T856
Test name
Test status
Simulation time 46719090 ps
CPU time 1.79 seconds
Started May 05 02:28:18 PM PDT 24
Finished May 05 02:28:21 PM PDT 24
Peak memory 215032 kb
Host smart-d36cc333-7511-4e37-8752-2c464d84ee2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280465011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.4280465011
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.307934216
Short name T256
Test name
Test status
Simulation time 99212725 ps
CPU time 1.6 seconds
Started May 05 02:28:18 PM PDT 24
Finished May 05 02:28:21 PM PDT 24
Peak memory 214960 kb
Host smart-2aa458bb-289a-45d9-b69c-885f3efc1c05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307934216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.307934216
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.4079601709
Short name T860
Test name
Test status
Simulation time 23277489 ps
CPU time 1.22 seconds
Started May 05 02:28:34 PM PDT 24
Finished May 05 02:28:35 PM PDT 24
Peak memory 214972 kb
Host smart-51a0aa3e-70a0-4ce3-82ae-4ba2b0dc00e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079601709 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.4079601709
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.208433100
Short name T905
Test name
Test status
Simulation time 21728475 ps
CPU time 0.82 seconds
Started May 05 02:28:27 PM PDT 24
Finished May 05 02:28:28 PM PDT 24
Peak memory 206500 kb
Host smart-01098f88-9f62-4507-b9cb-8c3427277742
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208433100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.208433100
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.88046372
Short name T969
Test name
Test status
Simulation time 43238256 ps
CPU time 0.83 seconds
Started May 05 02:28:24 PM PDT 24
Finished May 05 02:28:26 PM PDT 24
Peak memory 206476 kb
Host smart-183ff2d6-f213-459b-8523-6ba92da7a405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88046372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.88046372
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3008493143
Short name T235
Test name
Test status
Simulation time 190690521 ps
CPU time 1.14 seconds
Started May 05 02:28:33 PM PDT 24
Finished May 05 02:28:34 PM PDT 24
Peak memory 206804 kb
Host smart-16348e72-e434-4494-a150-5fb823b9dc69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008493143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3008493143
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2634108996
Short name T877
Test name
Test status
Simulation time 214340346 ps
CPU time 2.74 seconds
Started May 05 02:28:26 PM PDT 24
Finished May 05 02:28:29 PM PDT 24
Peak memory 214860 kb
Host smart-3bdb3d4a-4be1-4181-b63b-7e5248a99729
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634108996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2634108996
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2913474648
Short name T968
Test name
Test status
Simulation time 179683941 ps
CPU time 2.56 seconds
Started May 05 02:28:25 PM PDT 24
Finished May 05 02:28:28 PM PDT 24
Peak memory 206712 kb
Host smart-8ca20582-c633-4fb9-b3e1-6d33e85b3e8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913474648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2913474648
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1962584259
Short name T949
Test name
Test status
Simulation time 30443931 ps
CPU time 1.32 seconds
Started May 05 02:28:36 PM PDT 24
Finished May 05 02:28:38 PM PDT 24
Peak memory 215000 kb
Host smart-f067c33e-dae9-4b54-8e83-e64c47a0c2b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962584259 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1962584259
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.170005089
Short name T920
Test name
Test status
Simulation time 13818294 ps
CPU time 0.87 seconds
Started May 05 02:28:34 PM PDT 24
Finished May 05 02:28:35 PM PDT 24
Peak memory 206740 kb
Host smart-42d03a16-3a0f-4324-b6d5-a81ac76ca908
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170005089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.170005089
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.565110589
Short name T847
Test name
Test status
Simulation time 49987658 ps
CPU time 0.81 seconds
Started May 05 02:28:33 PM PDT 24
Finished May 05 02:28:34 PM PDT 24
Peak memory 206424 kb
Host smart-cf7904c2-9ea7-4171-9b5f-1c3fbe7c84ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565110589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.565110589
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.49202041
Short name T915
Test name
Test status
Simulation time 19084967 ps
CPU time 1.2 seconds
Started May 05 02:28:37 PM PDT 24
Finished May 05 02:28:39 PM PDT 24
Peak memory 206720 kb
Host smart-25eded2a-0d97-4d7b-941e-1c39721b072e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49202041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_out
standing.49202041
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.714119113
Short name T851
Test name
Test status
Simulation time 46147449 ps
CPU time 1.91 seconds
Started May 05 02:28:33 PM PDT 24
Finished May 05 02:28:35 PM PDT 24
Peak memory 215032 kb
Host smart-1b5c9f39-d5d6-427d-b3e1-4635c5933b2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714119113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.714119113
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1722572540
Short name T974
Test name
Test status
Simulation time 42414350 ps
CPU time 1.63 seconds
Started May 05 02:28:32 PM PDT 24
Finished May 05 02:28:34 PM PDT 24
Peak memory 206848 kb
Host smart-e6a33a89-b1ec-4744-ab3d-4f9674a4b0e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722572540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1722572540
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3860880941
Short name T967
Test name
Test status
Simulation time 33902768 ps
CPU time 2.07 seconds
Started May 05 02:28:43 PM PDT 24
Finished May 05 02:28:45 PM PDT 24
Peak memory 214988 kb
Host smart-516c373e-9066-4345-a244-39c7020a8da5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860880941 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3860880941
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1978189666
Short name T231
Test name
Test status
Simulation time 110954043 ps
CPU time 0.84 seconds
Started May 05 02:28:43 PM PDT 24
Finished May 05 02:28:45 PM PDT 24
Peak memory 206712 kb
Host smart-798c9660-0a2d-471b-8c97-e48d2564f06b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978189666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1978189666
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.4096125981
Short name T945
Test name
Test status
Simulation time 28844134 ps
CPU time 0.86 seconds
Started May 05 02:28:35 PM PDT 24
Finished May 05 02:28:37 PM PDT 24
Peak memory 206640 kb
Host smart-b91106a4-10bc-40b1-a53a-7dc42182208d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096125981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.4096125981
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.296823472
Short name T236
Test name
Test status
Simulation time 105801249 ps
CPU time 1.29 seconds
Started May 05 02:28:43 PM PDT 24
Finished May 05 02:28:45 PM PDT 24
Peak memory 206744 kb
Host smart-c7ae3590-32b5-459e-b763-a7dff9b04f2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296823472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.296823472
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3524037819
Short name T953
Test name
Test status
Simulation time 404336567 ps
CPU time 3.74 seconds
Started May 05 02:28:38 PM PDT 24
Finished May 05 02:28:42 PM PDT 24
Peak memory 214964 kb
Host smart-3b0049c1-c318-4349-8828-717b7da38d55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524037819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3524037819
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3864390602
Short name T938
Test name
Test status
Simulation time 52664557 ps
CPU time 1.69 seconds
Started May 05 02:28:37 PM PDT 24
Finished May 05 02:28:39 PM PDT 24
Peak memory 206744 kb
Host smart-77e79c12-f1db-4794-9403-cb807e95b5d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864390602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3864390602
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2305192604
Short name T898
Test name
Test status
Simulation time 52142395 ps
CPU time 1.01 seconds
Started May 05 02:28:42 PM PDT 24
Finished May 05 02:28:44 PM PDT 24
Peak memory 216584 kb
Host smart-ca0daaed-c67a-4781-9b2d-2bf74f129ab2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305192604 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2305192604
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1421711115
Short name T232
Test name
Test status
Simulation time 62674810 ps
CPU time 0.85 seconds
Started May 05 02:28:42 PM PDT 24
Finished May 05 02:28:44 PM PDT 24
Peak memory 206740 kb
Host smart-11ddceb9-fec0-4af3-a498-ca16b947d58d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421711115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1421711115
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.4156214196
Short name T912
Test name
Test status
Simulation time 66883721 ps
CPU time 0.86 seconds
Started May 05 02:28:42 PM PDT 24
Finished May 05 02:28:43 PM PDT 24
Peak memory 206688 kb
Host smart-a8429a68-10da-4ca9-868b-78d5df27bae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156214196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.4156214196
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2318031881
Short name T973
Test name
Test status
Simulation time 22885798 ps
CPU time 1.1 seconds
Started May 05 02:28:45 PM PDT 24
Finished May 05 02:28:46 PM PDT 24
Peak memory 206756 kb
Host smart-97287c00-6c21-47cc-96c5-60f3f36829f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318031881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2318031881
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2129561618
Short name T957
Test name
Test status
Simulation time 29531133 ps
CPU time 1.94 seconds
Started May 05 02:28:45 PM PDT 24
Finished May 05 02:28:48 PM PDT 24
Peak memory 214948 kb
Host smart-e973c62f-ea17-4321-a749-525e5a532021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129561618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2129561618
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1056931872
Short name T241
Test name
Test status
Simulation time 80058113 ps
CPU time 1.53 seconds
Started May 05 02:28:44 PM PDT 24
Finished May 05 02:28:46 PM PDT 24
Peak memory 214892 kb
Host smart-1750a552-4aaf-4a02-b476-9eddb2e938b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056931872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1056931872
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1695524847
Short name T862
Test name
Test status
Simulation time 58732827 ps
CPU time 1.61 seconds
Started May 05 02:28:46 PM PDT 24
Finished May 05 02:28:48 PM PDT 24
Peak memory 215028 kb
Host smart-f231e716-c767-4434-b17a-764d28cf5bc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695524847 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1695524847
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1167783134
Short name T229
Test name
Test status
Simulation time 18884446 ps
CPU time 0.82 seconds
Started May 05 02:28:49 PM PDT 24
Finished May 05 02:28:51 PM PDT 24
Peak memory 206544 kb
Host smart-5c4daeac-841f-4c78-a03c-420bd17797b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167783134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1167783134
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3124059073
Short name T886
Test name
Test status
Simulation time 19171341 ps
CPU time 0.83 seconds
Started May 05 02:28:48 PM PDT 24
Finished May 05 02:28:50 PM PDT 24
Peak memory 206620 kb
Host smart-936ae8ff-5ded-43a7-8ee3-429b59915667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124059073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3124059073
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.830339160
Short name T954
Test name
Test status
Simulation time 180193458 ps
CPU time 1.01 seconds
Started May 05 02:28:48 PM PDT 24
Finished May 05 02:28:50 PM PDT 24
Peak memory 206764 kb
Host smart-18f50478-329e-42e2-bcf5-80adf92f2bcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830339160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.830339160
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2063797225
Short name T889
Test name
Test status
Simulation time 94197733 ps
CPU time 3.34 seconds
Started May 05 02:28:43 PM PDT 24
Finished May 05 02:28:47 PM PDT 24
Peak memory 214868 kb
Host smart-194ad73d-3520-4dc5-ae91-8df4c665bc1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063797225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2063797225
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4248858840
Short name T906
Test name
Test status
Simulation time 58708915 ps
CPU time 1.79 seconds
Started May 05 02:28:45 PM PDT 24
Finished May 05 02:28:48 PM PDT 24
Peak memory 206748 kb
Host smart-66971485-1761-451f-8783-cf93781e1a8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248858840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.4248858840
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2384784627
Short name T913
Test name
Test status
Simulation time 18699163 ps
CPU time 1.08 seconds
Started May 05 02:28:47 PM PDT 24
Finished May 05 02:28:49 PM PDT 24
Peak memory 215060 kb
Host smart-fd1aad8f-137f-46fd-a273-347c5647b74c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384784627 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2384784627
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3118273373
Short name T228
Test name
Test status
Simulation time 104548047 ps
CPU time 0.94 seconds
Started May 05 02:28:50 PM PDT 24
Finished May 05 02:28:52 PM PDT 24
Peak memory 206744 kb
Host smart-91796538-4c32-4411-b94a-2206366b66be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118273373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3118273373
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2113143455
Short name T879
Test name
Test status
Simulation time 13750301 ps
CPU time 0.88 seconds
Started May 05 02:28:50 PM PDT 24
Finished May 05 02:28:52 PM PDT 24
Peak memory 206620 kb
Host smart-23663c18-8990-4483-95d5-585ff0851cc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113143455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2113143455
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2873001222
Short name T909
Test name
Test status
Simulation time 21446390 ps
CPU time 1.08 seconds
Started May 05 02:28:47 PM PDT 24
Finished May 05 02:28:48 PM PDT 24
Peak memory 206700 kb
Host smart-b1c746f6-947a-4882-84c7-32a8ba3e4eb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873001222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2873001222
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.4186950236
Short name T971
Test name
Test status
Simulation time 191568990 ps
CPU time 3.56 seconds
Started May 05 02:28:49 PM PDT 24
Finished May 05 02:28:54 PM PDT 24
Peak memory 215100 kb
Host smart-1530c92c-721f-493c-b1ed-152017a5b4ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186950236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.4186950236
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4031151293
Short name T892
Test name
Test status
Simulation time 148857408 ps
CPU time 3.2 seconds
Started May 05 02:28:46 PM PDT 24
Finished May 05 02:28:50 PM PDT 24
Peak memory 206824 kb
Host smart-13cdca1a-2f4a-4a6d-b113-34e55910d053
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031151293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.4031151293
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3472883074
Short name T890
Test name
Test status
Simulation time 17825191 ps
CPU time 1.02 seconds
Started May 05 02:28:51 PM PDT 24
Finished May 05 02:28:53 PM PDT 24
Peak memory 206700 kb
Host smart-6b096d37-2c33-4398-95eb-3ae2c264eb6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472883074 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3472883074
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3267315724
Short name T903
Test name
Test status
Simulation time 14436008 ps
CPU time 0.95 seconds
Started May 05 02:28:53 PM PDT 24
Finished May 05 02:28:54 PM PDT 24
Peak memory 206708 kb
Host smart-75df08b0-b5a0-4fc0-9273-2b2a5cca518c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267315724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3267315724
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3647652731
Short name T944
Test name
Test status
Simulation time 38722569 ps
CPU time 0.82 seconds
Started May 05 02:28:53 PM PDT 24
Finished May 05 02:28:54 PM PDT 24
Peak memory 206420 kb
Host smart-f3dcbbfd-690b-41ef-a246-3e47109f9a82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647652731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3647652731
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2323751822
Short name T220
Test name
Test status
Simulation time 66163671 ps
CPU time 1.03 seconds
Started May 05 02:28:50 PM PDT 24
Finished May 05 02:28:52 PM PDT 24
Peak memory 206728 kb
Host smart-c3b6f5ec-5d53-4d39-bb05-816e7c3f16fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323751822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2323751822
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.138393667
Short name T972
Test name
Test status
Simulation time 59204100 ps
CPU time 2.64 seconds
Started May 05 02:28:48 PM PDT 24
Finished May 05 02:28:51 PM PDT 24
Peak memory 214980 kb
Host smart-cf47fb54-5b92-47b1-9dd5-a538f5a99af7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138393667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.138393667
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1934105562
Short name T951
Test name
Test status
Simulation time 430142101 ps
CPU time 2.91 seconds
Started May 05 02:28:51 PM PDT 24
Finished May 05 02:28:54 PM PDT 24
Peak memory 214876 kb
Host smart-9a65168f-5bd5-4607-9700-379538bef752
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934105562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1934105562
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1785821215
Short name T922
Test name
Test status
Simulation time 311471568 ps
CPU time 1.55 seconds
Started May 05 02:28:54 PM PDT 24
Finished May 05 02:28:56 PM PDT 24
Peak memory 214984 kb
Host smart-319044b0-062b-45ae-88c5-d7935e309ea6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785821215 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1785821215
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1528035645
Short name T966
Test name
Test status
Simulation time 35981702 ps
CPU time 0.82 seconds
Started May 05 02:28:50 PM PDT 24
Finished May 05 02:28:51 PM PDT 24
Peak memory 206516 kb
Host smart-9c593377-ccdb-4d32-a939-b403ec429c4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528035645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1528035645
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.541080595
Short name T873
Test name
Test status
Simulation time 45898261 ps
CPU time 0.8 seconds
Started May 05 02:28:51 PM PDT 24
Finished May 05 02:28:52 PM PDT 24
Peak memory 206480 kb
Host smart-ae46c352-e728-4f6d-bc0e-4b5edc58a5a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541080595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.541080595
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2470001767
Short name T222
Test name
Test status
Simulation time 117654629 ps
CPU time 0.92 seconds
Started May 05 02:28:53 PM PDT 24
Finished May 05 02:28:55 PM PDT 24
Peak memory 206728 kb
Host smart-51de401a-a377-4a8b-85bf-100372a47fe0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470001767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2470001767
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1753594550
Short name T962
Test name
Test status
Simulation time 35738147 ps
CPU time 2.15 seconds
Started May 05 02:28:52 PM PDT 24
Finished May 05 02:28:55 PM PDT 24
Peak memory 214936 kb
Host smart-c53fae91-dc06-4268-8998-8e207311463a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753594550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1753594550
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1443559513
Short name T242
Test name
Test status
Simulation time 345549301 ps
CPU time 2.21 seconds
Started May 05 02:28:50 PM PDT 24
Finished May 05 02:28:53 PM PDT 24
Peak memory 206828 kb
Host smart-51937f10-eeac-4e65-9574-6de441c94d99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443559513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1443559513
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1844854899
Short name T850
Test name
Test status
Simulation time 73576790 ps
CPU time 1.01 seconds
Started May 05 02:29:03 PM PDT 24
Finished May 05 02:29:04 PM PDT 24
Peak memory 206748 kb
Host smart-6adda7a4-fc04-4cbd-95ea-dcbe8e7a7407
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844854899 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1844854899
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1496912269
Short name T921
Test name
Test status
Simulation time 16063924 ps
CPU time 1.02 seconds
Started May 05 02:29:01 PM PDT 24
Finished May 05 02:29:02 PM PDT 24
Peak memory 206768 kb
Host smart-750b46cf-d3d8-4f95-b004-b8da525abac1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496912269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1496912269
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.554453366
Short name T861
Test name
Test status
Simulation time 11345375 ps
CPU time 0.83 seconds
Started May 05 02:28:55 PM PDT 24
Finished May 05 02:28:56 PM PDT 24
Peak memory 206660 kb
Host smart-27fb7386-d2b4-4ab5-b24e-d8e6b1429586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554453366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.554453366
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3973502044
Short name T929
Test name
Test status
Simulation time 40336930 ps
CPU time 1.46 seconds
Started May 05 02:29:01 PM PDT 24
Finished May 05 02:29:02 PM PDT 24
Peak memory 206748 kb
Host smart-06d2d273-ef40-4dae-a0a2-415367acca37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973502044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3973502044
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1645996111
Short name T958
Test name
Test status
Simulation time 48015114 ps
CPU time 2.1 seconds
Started May 05 02:28:53 PM PDT 24
Finished May 05 02:28:56 PM PDT 24
Peak memory 214908 kb
Host smart-95af527f-a816-4f51-b9f5-390b397ed757
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645996111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1645996111
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3351342442
Short name T924
Test name
Test status
Simulation time 154141140 ps
CPU time 1.59 seconds
Started May 05 02:28:55 PM PDT 24
Finished May 05 02:28:57 PM PDT 24
Peak memory 206716 kb
Host smart-a611e0c2-3005-44bb-a7d2-e579fb259980
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351342442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3351342442
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.411992631
Short name T225
Test name
Test status
Simulation time 30554184 ps
CPU time 1.22 seconds
Started May 05 02:27:38 PM PDT 24
Finished May 05 02:27:40 PM PDT 24
Peak memory 206776 kb
Host smart-d2bcaa84-92c9-4e32-b840-894a62c0e1c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411992631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.411992631
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2052152616
Short name T895
Test name
Test status
Simulation time 35147648 ps
CPU time 2.01 seconds
Started May 05 02:27:36 PM PDT 24
Finished May 05 02:27:39 PM PDT 24
Peak memory 206736 kb
Host smart-818262b4-43f7-4757-be7e-c29b75c165e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052152616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2052152616
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1081610158
Short name T230
Test name
Test status
Simulation time 14748891 ps
CPU time 0.92 seconds
Started May 05 02:27:34 PM PDT 24
Finished May 05 02:27:36 PM PDT 24
Peak memory 206732 kb
Host smart-5d799821-b941-41e0-a3d4-aedac937ae60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081610158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1081610158
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3035176304
Short name T904
Test name
Test status
Simulation time 30849056 ps
CPU time 1.93 seconds
Started May 05 02:27:36 PM PDT 24
Finished May 05 02:27:38 PM PDT 24
Peak memory 214960 kb
Host smart-4f6242a6-594b-4d9d-b28a-26406e8a9018
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035176304 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3035176304
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1139198041
Short name T234
Test name
Test status
Simulation time 13080583 ps
CPU time 0.89 seconds
Started May 05 02:27:34 PM PDT 24
Finished May 05 02:27:36 PM PDT 24
Peak memory 206732 kb
Host smart-721b9b0d-8be6-45f6-842b-c67a3469d93b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139198041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1139198041
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1498135238
Short name T928
Test name
Test status
Simulation time 24815313 ps
CPU time 0.86 seconds
Started May 05 02:27:33 PM PDT 24
Finished May 05 02:27:34 PM PDT 24
Peak memory 206624 kb
Host smart-183e3eb5-7e9e-47f7-9f89-52a0e2c1faed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498135238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1498135238
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1436259907
Short name T908
Test name
Test status
Simulation time 23141577 ps
CPU time 0.94 seconds
Started May 05 02:27:38 PM PDT 24
Finished May 05 02:27:40 PM PDT 24
Peak memory 206684 kb
Host smart-d3a8ce66-b836-4164-b1c0-103b6492504a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436259907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1436259907
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2120047836
Short name T208
Test name
Test status
Simulation time 84816974 ps
CPU time 2.63 seconds
Started May 05 02:27:29 PM PDT 24
Finished May 05 02:27:31 PM PDT 24
Peak memory 214880 kb
Host smart-3d607a1c-dfc1-4f3b-91c0-d4aa5721cca6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120047836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2120047836
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1198213268
Short name T253
Test name
Test status
Simulation time 48218825 ps
CPU time 1.72 seconds
Started May 05 02:27:33 PM PDT 24
Finished May 05 02:27:35 PM PDT 24
Peak memory 214948 kb
Host smart-6ec7b20f-28d6-4046-922e-82cad3e886b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198213268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1198213268
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3805485987
Short name T896
Test name
Test status
Simulation time 140165554 ps
CPU time 0.83 seconds
Started May 05 02:29:04 PM PDT 24
Finished May 05 02:29:05 PM PDT 24
Peak memory 206480 kb
Host smart-38262281-29d4-4cf5-9778-cafb2302ff51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805485987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3805485987
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3496284105
Short name T864
Test name
Test status
Simulation time 41286544 ps
CPU time 0.86 seconds
Started May 05 02:29:00 PM PDT 24
Finished May 05 02:29:01 PM PDT 24
Peak memory 206468 kb
Host smart-58fe2a5a-7faf-4ee2-805d-79c2fb411532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496284105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3496284105
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.77760727
Short name T866
Test name
Test status
Simulation time 55629378 ps
CPU time 0.9 seconds
Started May 05 02:29:02 PM PDT 24
Finished May 05 02:29:04 PM PDT 24
Peak memory 206444 kb
Host smart-7c3304b7-0bdb-427d-8f2a-6ba9d95a61d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77760727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.77760727
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.742939274
Short name T878
Test name
Test status
Simulation time 35894232 ps
CPU time 0.84 seconds
Started May 05 02:29:02 PM PDT 24
Finished May 05 02:29:03 PM PDT 24
Peak memory 206648 kb
Host smart-ff507b83-6329-4b0e-a437-a4c829e41d5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742939274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.742939274
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3409347048
Short name T853
Test name
Test status
Simulation time 68573665 ps
CPU time 0.87 seconds
Started May 05 02:29:09 PM PDT 24
Finished May 05 02:29:10 PM PDT 24
Peak memory 206592 kb
Host smart-9621ff4b-d4e0-4783-8d19-b7b72a6401ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409347048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3409347048
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.4075402258
Short name T901
Test name
Test status
Simulation time 12053742 ps
CPU time 0.84 seconds
Started May 05 02:29:08 PM PDT 24
Finished May 05 02:29:09 PM PDT 24
Peak memory 206676 kb
Host smart-dc8e3d4b-c609-4db5-a0f9-a55145b3b57a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075402258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.4075402258
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.4176584741
Short name T925
Test name
Test status
Simulation time 23566214 ps
CPU time 0.83 seconds
Started May 05 02:29:09 PM PDT 24
Finished May 05 02:29:10 PM PDT 24
Peak memory 206736 kb
Host smart-c789815f-5079-483c-8554-96b68f2e7bae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176584741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.4176584741
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2338540586
Short name T849
Test name
Test status
Simulation time 16719320 ps
CPU time 0.95 seconds
Started May 05 02:29:11 PM PDT 24
Finished May 05 02:29:13 PM PDT 24
Peak memory 206764 kb
Host smart-2da1689a-b107-4d9e-8d61-59055bd60caf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338540586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2338540586
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.716964403
Short name T939
Test name
Test status
Simulation time 14791967 ps
CPU time 0.9 seconds
Started May 05 02:29:09 PM PDT 24
Finished May 05 02:29:11 PM PDT 24
Peak memory 206648 kb
Host smart-cdc9a2ab-3f7f-42fa-a008-9558c7f905b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716964403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.716964403
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3293697924
Short name T931
Test name
Test status
Simulation time 10871578 ps
CPU time 0.81 seconds
Started May 05 02:29:09 PM PDT 24
Finished May 05 02:29:11 PM PDT 24
Peak memory 206592 kb
Host smart-fee553a3-4519-48b6-b5b5-19c968874dd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293697924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3293697924
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3498909267
Short name T918
Test name
Test status
Simulation time 29519961 ps
CPU time 1.24 seconds
Started May 05 02:27:41 PM PDT 24
Finished May 05 02:27:43 PM PDT 24
Peak memory 206716 kb
Host smart-b95d0fbc-e2dc-4554-91a8-021c74f9bba9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498909267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3498909267
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.624373303
Short name T946
Test name
Test status
Simulation time 216974751 ps
CPU time 2.99 seconds
Started May 05 02:27:41 PM PDT 24
Finished May 05 02:27:45 PM PDT 24
Peak memory 206744 kb
Host smart-fb8a2a23-844e-4ff4-8769-dd496f178139
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624373303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.624373303
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2996873591
Short name T916
Test name
Test status
Simulation time 35236539 ps
CPU time 0.92 seconds
Started May 05 02:27:41 PM PDT 24
Finished May 05 02:27:43 PM PDT 24
Peak memory 206680 kb
Host smart-94b6365b-81d8-4809-85ae-5cbcf22a6dbc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996873591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2996873591
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1105866699
Short name T884
Test name
Test status
Simulation time 40231948 ps
CPU time 1.46 seconds
Started May 05 02:27:46 PM PDT 24
Finished May 05 02:27:47 PM PDT 24
Peak memory 214988 kb
Host smart-4911d1c5-25b2-43ee-8986-1470be38c492
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105866699 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1105866699
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2526010567
Short name T218
Test name
Test status
Simulation time 35672269 ps
CPU time 0.82 seconds
Started May 05 02:27:41 PM PDT 24
Finished May 05 02:27:42 PM PDT 24
Peak memory 206516 kb
Host smart-8586af00-d22c-4b5b-8d3a-c9a3b7cc533f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526010567 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2526010567
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1630885846
Short name T907
Test name
Test status
Simulation time 56804023 ps
CPU time 0.89 seconds
Started May 05 02:27:36 PM PDT 24
Finished May 05 02:27:38 PM PDT 24
Peak memory 206636 kb
Host smart-ce96b6a2-d083-44c9-9320-bb6b91eb613b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630885846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1630885846
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.544677401
Short name T926
Test name
Test status
Simulation time 54667808 ps
CPU time 1.1 seconds
Started May 05 02:27:46 PM PDT 24
Finished May 05 02:27:48 PM PDT 24
Peak memory 206732 kb
Host smart-8d201818-b318-4bc5-8366-71959370b4b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544677401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.544677401
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3426309488
Short name T868
Test name
Test status
Simulation time 376197784 ps
CPU time 3.52 seconds
Started May 05 02:27:37 PM PDT 24
Finished May 05 02:27:41 PM PDT 24
Peak memory 215056 kb
Host smart-0aeb6b41-ae50-4bf5-8ce6-7c1140ef528c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426309488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3426309488
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2152443571
Short name T252
Test name
Test status
Simulation time 114792601 ps
CPU time 1.71 seconds
Started May 05 02:27:38 PM PDT 24
Finished May 05 02:27:41 PM PDT 24
Peak memory 206772 kb
Host smart-977cc780-a797-46b3-8625-d6583e03fc78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152443571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2152443571
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2958065727
Short name T941
Test name
Test status
Simulation time 17881595 ps
CPU time 1.05 seconds
Started May 05 02:29:09 PM PDT 24
Finished May 05 02:29:11 PM PDT 24
Peak memory 206644 kb
Host smart-ef0ed228-89c5-440f-be6b-d482eb400413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958065727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2958065727
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3944834433
Short name T932
Test name
Test status
Simulation time 17324998 ps
CPU time 0.81 seconds
Started May 05 02:29:08 PM PDT 24
Finished May 05 02:29:09 PM PDT 24
Peak memory 206472 kb
Host smart-faa62abc-6a3c-4042-b69e-920a7f95f0fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944834433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3944834433
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.4008175459
Short name T930
Test name
Test status
Simulation time 35436840 ps
CPU time 0.84 seconds
Started May 05 02:29:15 PM PDT 24
Finished May 05 02:29:16 PM PDT 24
Peak memory 206464 kb
Host smart-8c6be2e4-e5fb-4d84-bbae-3454f9b291b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008175459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.4008175459
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1769671066
Short name T883
Test name
Test status
Simulation time 15574062 ps
CPU time 0.88 seconds
Started May 05 02:29:14 PM PDT 24
Finished May 05 02:29:15 PM PDT 24
Peak memory 206644 kb
Host smart-860e2551-f260-4533-b42f-cbe1a06097cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769671066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1769671066
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2967648268
Short name T852
Test name
Test status
Simulation time 11706795 ps
CPU time 0.85 seconds
Started May 05 02:29:14 PM PDT 24
Finished May 05 02:29:15 PM PDT 24
Peak memory 206612 kb
Host smart-b0c819c8-1111-472c-8d3b-1aa99c13eae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967648268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2967648268
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2043462824
Short name T952
Test name
Test status
Simulation time 15377029 ps
CPU time 0.8 seconds
Started May 05 02:29:13 PM PDT 24
Finished May 05 02:29:14 PM PDT 24
Peak memory 206404 kb
Host smart-b8d81cc1-7beb-419f-9294-b49810740d99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043462824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2043462824
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3362288022
Short name T888
Test name
Test status
Simulation time 15973891 ps
CPU time 0.82 seconds
Started May 05 02:29:11 PM PDT 24
Finished May 05 02:29:13 PM PDT 24
Peak memory 206612 kb
Host smart-d1499556-59c4-45e2-a8fb-485b1d1ac4df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362288022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3362288022
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.4181905704
Short name T869
Test name
Test status
Simulation time 128495880 ps
CPU time 0.75 seconds
Started May 05 02:29:18 PM PDT 24
Finished May 05 02:29:19 PM PDT 24
Peak memory 206392 kb
Host smart-fa8baba8-99a8-4452-bd79-531c96c0bcfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181905704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.4181905704
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3529911770
Short name T858
Test name
Test status
Simulation time 15822119 ps
CPU time 0.9 seconds
Started May 05 02:29:18 PM PDT 24
Finished May 05 02:29:20 PM PDT 24
Peak memory 206664 kb
Host smart-a16f3d9a-c26d-4363-b6df-ffd0e0ea6e5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529911770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3529911770
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2703311224
Short name T959
Test name
Test status
Simulation time 19855516 ps
CPU time 0.86 seconds
Started May 05 02:29:19 PM PDT 24
Finished May 05 02:29:20 PM PDT 24
Peak memory 206668 kb
Host smart-6deb1eee-0d7b-48b3-8374-b94bdc8f6a76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703311224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2703311224
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.773197019
Short name T233
Test name
Test status
Simulation time 367797690 ps
CPU time 1.51 seconds
Started May 05 02:27:56 PM PDT 24
Finished May 05 02:27:57 PM PDT 24
Peak memory 206792 kb
Host smart-63d85b04-8787-4363-8cdd-22242d52411a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773197019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.773197019
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2023410857
Short name T893
Test name
Test status
Simulation time 349061553 ps
CPU time 3.13 seconds
Started May 05 02:27:55 PM PDT 24
Finished May 05 02:27:59 PM PDT 24
Peak memory 206788 kb
Host smart-87b00d8a-2fbc-4967-a408-217db0006ff5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023410857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2023410857
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3267130727
Short name T238
Test name
Test status
Simulation time 19407763 ps
CPU time 0.88 seconds
Started May 05 02:27:49 PM PDT 24
Finished May 05 02:27:51 PM PDT 24
Peak memory 206704 kb
Host smart-8f4c3de2-d395-4d04-9e47-a9f97ec8c69e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267130727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3267130727
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2232103294
Short name T205
Test name
Test status
Simulation time 63376541 ps
CPU time 1.04 seconds
Started May 05 02:27:59 PM PDT 24
Finished May 05 02:28:00 PM PDT 24
Peak memory 214956 kb
Host smart-631d2771-dfca-44e3-afc4-48f0b0cda13c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232103294 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2232103294
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1933594544
Short name T871
Test name
Test status
Simulation time 29422410 ps
CPU time 0.86 seconds
Started May 05 02:27:59 PM PDT 24
Finished May 05 02:28:00 PM PDT 24
Peak memory 206672 kb
Host smart-9147f8ec-bc57-41d2-afaf-326dbbfa92cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933594544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1933594544
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.4185164166
Short name T935
Test name
Test status
Simulation time 22023327 ps
CPU time 0.87 seconds
Started May 05 02:27:50 PM PDT 24
Finished May 05 02:27:51 PM PDT 24
Peak memory 206688 kb
Host smart-a3941681-5ab6-43a6-b6f9-7faacfdffa4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185164166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.4185164166
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.219434232
Short name T933
Test name
Test status
Simulation time 150201481 ps
CPU time 1.6 seconds
Started May 05 02:27:58 PM PDT 24
Finished May 05 02:28:00 PM PDT 24
Peak memory 206704 kb
Host smart-a5ab7e5e-8dc3-418f-a2f3-f95398225d78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219434232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.219434232
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2792943433
Short name T927
Test name
Test status
Simulation time 328371687 ps
CPU time 2.49 seconds
Started May 05 02:27:45 PM PDT 24
Finished May 05 02:27:48 PM PDT 24
Peak memory 215000 kb
Host smart-10ce8bdb-c274-4f24-a48d-e61139210207
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792943433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2792943433
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1872768447
Short name T960
Test name
Test status
Simulation time 168248046 ps
CPU time 1.59 seconds
Started May 05 02:27:47 PM PDT 24
Finished May 05 02:27:49 PM PDT 24
Peak memory 206748 kb
Host smart-35b168b6-8b98-42d3-8167-151740f6003c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872768447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1872768447
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3405726524
Short name T854
Test name
Test status
Simulation time 34243207 ps
CPU time 0.83 seconds
Started May 05 02:29:20 PM PDT 24
Finished May 05 02:29:21 PM PDT 24
Peak memory 206436 kb
Host smart-8fd8f1e4-5007-4475-b612-25eb5e61d054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405726524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3405726524
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1733914288
Short name T870
Test name
Test status
Simulation time 19533935 ps
CPU time 0.77 seconds
Started May 05 02:29:19 PM PDT 24
Finished May 05 02:29:20 PM PDT 24
Peak memory 206396 kb
Host smart-56a94d0b-72e3-4c05-8dfb-b11bb2a84d10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733914288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1733914288
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3985650680
Short name T902
Test name
Test status
Simulation time 126518472 ps
CPU time 0.85 seconds
Started May 05 02:29:18 PM PDT 24
Finished May 05 02:29:20 PM PDT 24
Peak memory 206468 kb
Host smart-cecb0d98-db09-43f3-89fd-d51074fa7a33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985650680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3985650680
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.4123426401
Short name T976
Test name
Test status
Simulation time 34668475 ps
CPU time 0.95 seconds
Started May 05 02:29:19 PM PDT 24
Finished May 05 02:29:21 PM PDT 24
Peak memory 206600 kb
Host smart-f5a9fc1e-788e-410e-a3c1-3db8a0bb4075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123426401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.4123426401
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.874315232
Short name T885
Test name
Test status
Simulation time 12294716 ps
CPU time 0.8 seconds
Started May 05 02:29:17 PM PDT 24
Finished May 05 02:29:18 PM PDT 24
Peak memory 206680 kb
Host smart-95f368fe-a325-44a9-8e36-cdb1d5a463a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874315232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.874315232
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3577484683
Short name T923
Test name
Test status
Simulation time 31896587 ps
CPU time 0.79 seconds
Started May 05 02:29:17 PM PDT 24
Finished May 05 02:29:19 PM PDT 24
Peak memory 206476 kb
Host smart-8088a358-d059-46e8-85a6-68c92c2c0f42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577484683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3577484683
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3016043111
Short name T942
Test name
Test status
Simulation time 16624905 ps
CPU time 0.9 seconds
Started May 05 02:29:23 PM PDT 24
Finished May 05 02:29:25 PM PDT 24
Peak memory 206652 kb
Host smart-611f5e4b-2685-4aba-b0cc-1ac4b95acc2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016043111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3016043111
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2160768291
Short name T865
Test name
Test status
Simulation time 40966679 ps
CPU time 0.92 seconds
Started May 05 02:29:26 PM PDT 24
Finished May 05 02:29:28 PM PDT 24
Peak memory 206632 kb
Host smart-dd3ec2ef-6a06-4ac4-990b-cb99d03add7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160768291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2160768291
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1185366016
Short name T874
Test name
Test status
Simulation time 11712274 ps
CPU time 0.9 seconds
Started May 05 02:29:22 PM PDT 24
Finished May 05 02:29:24 PM PDT 24
Peak memory 206624 kb
Host smart-788eff0a-21c8-4cb1-9302-a55e1902f45d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185366016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1185366016
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1454079979
Short name T963
Test name
Test status
Simulation time 24559481 ps
CPU time 0.9 seconds
Started May 05 02:29:25 PM PDT 24
Finished May 05 02:29:26 PM PDT 24
Peak memory 206620 kb
Host smart-eaacd606-39f5-4091-ba20-3633780faae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454079979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1454079979
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1678874401
Short name T917
Test name
Test status
Simulation time 88584620 ps
CPU time 1.22 seconds
Started May 05 02:28:03 PM PDT 24
Finished May 05 02:28:05 PM PDT 24
Peak memory 214980 kb
Host smart-87a469bc-b49f-4cea-8c1a-d1fb0ce658e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678874401 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1678874401
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.102869809
Short name T239
Test name
Test status
Simulation time 52321324 ps
CPU time 0.89 seconds
Started May 05 02:28:06 PM PDT 24
Finished May 05 02:28:07 PM PDT 24
Peak memory 206720 kb
Host smart-32d92bc5-5a91-4be9-9f58-c2cc60b96a8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102869809 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.102869809
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2090483259
Short name T848
Test name
Test status
Simulation time 39127251 ps
CPU time 0.81 seconds
Started May 05 02:28:00 PM PDT 24
Finished May 05 02:28:01 PM PDT 24
Peak memory 206428 kb
Host smart-5c1d03cd-4ef0-4fb5-8bbc-836f034243f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090483259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2090483259
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2443698353
Short name T894
Test name
Test status
Simulation time 247624648 ps
CPU time 1.3 seconds
Started May 05 02:28:05 PM PDT 24
Finished May 05 02:28:07 PM PDT 24
Peak memory 206732 kb
Host smart-cce5141a-e325-480e-936f-4d6c36d56683
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443698353 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2443698353
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1107734180
Short name T961
Test name
Test status
Simulation time 72320625 ps
CPU time 1.78 seconds
Started May 05 02:28:01 PM PDT 24
Finished May 05 02:28:03 PM PDT 24
Peak memory 214948 kb
Host smart-9ed3a4bc-69d0-4748-8952-e49ca4d91919
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107734180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1107734180
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.567626313
Short name T882
Test name
Test status
Simulation time 47433853 ps
CPU time 0.98 seconds
Started May 05 02:28:09 PM PDT 24
Finished May 05 02:28:10 PM PDT 24
Peak memory 206816 kb
Host smart-2f519a29-37d2-4f9a-b9bb-6231fd61f4da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567626313 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.567626313
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.427116404
Short name T221
Test name
Test status
Simulation time 118037948 ps
CPU time 0.9 seconds
Started May 05 02:28:06 PM PDT 24
Finished May 05 02:28:07 PM PDT 24
Peak memory 206708 kb
Host smart-e035203d-3297-49a8-9db9-cf644cc4fcbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427116404 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.427116404
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2256628287
Short name T937
Test name
Test status
Simulation time 40099938 ps
CPU time 0.85 seconds
Started May 05 02:28:04 PM PDT 24
Finished May 05 02:28:05 PM PDT 24
Peak memory 206720 kb
Host smart-99ffb884-629d-4663-a502-9e6e8941b76e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256628287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2256628287
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2439530338
Short name T237
Test name
Test status
Simulation time 23705946 ps
CPU time 0.93 seconds
Started May 05 02:28:10 PM PDT 24
Finished May 05 02:28:12 PM PDT 24
Peak memory 206744 kb
Host smart-7e1a424a-ee43-4cba-83ad-4d62ce93a1e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439530338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2439530338
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3722155816
Short name T891
Test name
Test status
Simulation time 114501996 ps
CPU time 3.85 seconds
Started May 05 02:28:05 PM PDT 24
Finished May 05 02:28:09 PM PDT 24
Peak memory 214980 kb
Host smart-0989f364-1184-48e6-9833-94e3fea8b80a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722155816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3722155816
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.902109062
Short name T900
Test name
Test status
Simulation time 329732279 ps
CPU time 5.98 seconds
Started May 05 02:28:06 PM PDT 24
Finished May 05 02:28:12 PM PDT 24
Peak memory 206960 kb
Host smart-4a28193c-c564-42bc-a5b4-36087858d6ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902109062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.902109062
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3350142805
Short name T899
Test name
Test status
Simulation time 67865944 ps
CPU time 1.23 seconds
Started May 05 02:28:09 PM PDT 24
Finished May 05 02:28:10 PM PDT 24
Peak memory 214972 kb
Host smart-1f851d0f-04df-4d2d-933e-b5fd341726e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350142805 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3350142805
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.305900364
Short name T940
Test name
Test status
Simulation time 53096709 ps
CPU time 0.93 seconds
Started May 05 02:28:10 PM PDT 24
Finished May 05 02:28:11 PM PDT 24
Peak memory 206688 kb
Host smart-b047cdd9-967e-497b-87ba-47202d2356fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305900364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.305900364
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.4171961847
Short name T859
Test name
Test status
Simulation time 16633862 ps
CPU time 0.83 seconds
Started May 05 02:28:12 PM PDT 24
Finished May 05 02:28:13 PM PDT 24
Peak memory 206448 kb
Host smart-9d08c594-2c86-4e4b-b0bf-213415530b3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171961847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.4171961847
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3892142533
Short name T948
Test name
Test status
Simulation time 35191551 ps
CPU time 1.16 seconds
Started May 05 02:28:13 PM PDT 24
Finished May 05 02:28:15 PM PDT 24
Peak memory 206728 kb
Host smart-c57648db-bad3-434c-af5c-c3f2ddaf2e2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892142533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3892142533
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.861954123
Short name T947
Test name
Test status
Simulation time 183156262 ps
CPU time 3.56 seconds
Started May 05 02:28:09 PM PDT 24
Finished May 05 02:28:13 PM PDT 24
Peak memory 215072 kb
Host smart-eb0a434e-3a0d-407c-88b0-88251e07fc51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861954123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.861954123
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3652521905
Short name T970
Test name
Test status
Simulation time 235904719 ps
CPU time 2.13 seconds
Started May 05 02:28:10 PM PDT 24
Finished May 05 02:28:13 PM PDT 24
Peak memory 206748 kb
Host smart-1585d0a3-6265-403d-8d2e-dbe1168df5ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652521905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3652521905
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.806407519
Short name T936
Test name
Test status
Simulation time 138534703 ps
CPU time 1.34 seconds
Started May 05 02:28:15 PM PDT 24
Finished May 05 02:28:16 PM PDT 24
Peak memory 214876 kb
Host smart-3fe0428f-83f7-4e68-afde-a18293b12be2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806407519 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.806407519
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3888005084
Short name T240
Test name
Test status
Simulation time 40273251 ps
CPU time 0.87 seconds
Started May 05 02:28:14 PM PDT 24
Finished May 05 02:28:15 PM PDT 24
Peak memory 206464 kb
Host smart-17ca7977-7406-4ea5-a5f9-469ba1441182
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888005084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3888005084
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.922086358
Short name T881
Test name
Test status
Simulation time 13236009 ps
CPU time 0.86 seconds
Started May 05 02:28:13 PM PDT 24
Finished May 05 02:28:14 PM PDT 24
Peak memory 206632 kb
Host smart-321d5b0d-6e65-44ad-818d-f84de3ac6410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922086358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.922086358
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2326254402
Short name T217
Test name
Test status
Simulation time 24581359 ps
CPU time 0.92 seconds
Started May 05 02:28:15 PM PDT 24
Finished May 05 02:28:16 PM PDT 24
Peak memory 206600 kb
Host smart-40f27346-9e2f-448e-ac72-b1e8d3e62b78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326254402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2326254402
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2166018103
Short name T943
Test name
Test status
Simulation time 33423471 ps
CPU time 1.4 seconds
Started May 05 02:28:10 PM PDT 24
Finished May 05 02:28:12 PM PDT 24
Peak memory 214904 kb
Host smart-62d50135-6d88-49f5-a982-b0952eb1b799
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166018103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2166018103
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2233958076
Short name T934
Test name
Test status
Simulation time 195058389 ps
CPU time 1.8 seconds
Started May 05 02:28:14 PM PDT 24
Finished May 05 02:28:16 PM PDT 24
Peak memory 206676 kb
Host smart-333faab9-f78b-4b9c-ad27-994b6f0afa98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233958076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2233958076
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3781848272
Short name T867
Test name
Test status
Simulation time 74213344 ps
CPU time 1.34 seconds
Started May 05 02:28:18 PM PDT 24
Finished May 05 02:28:20 PM PDT 24
Peak memory 223236 kb
Host smart-74edd590-17ab-45ab-80c5-8c13d704b705
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781848272 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3781848272
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.939283022
Short name T875
Test name
Test status
Simulation time 18394195 ps
CPU time 0.82 seconds
Started May 05 02:28:18 PM PDT 24
Finished May 05 02:28:20 PM PDT 24
Peak memory 206520 kb
Host smart-00490948-5b83-468f-8afe-2c80a5a2cea1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939283022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.939283022
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2122901312
Short name T880
Test name
Test status
Simulation time 66377072 ps
CPU time 0.84 seconds
Started May 05 02:28:13 PM PDT 24
Finished May 05 02:28:14 PM PDT 24
Peak memory 206688 kb
Host smart-cb40344d-b1e8-421e-aa97-de64fd2d97c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122901312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2122901312
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.13944154
Short name T224
Test name
Test status
Simulation time 170505364 ps
CPU time 1.39 seconds
Started May 05 02:28:19 PM PDT 24
Finished May 05 02:28:21 PM PDT 24
Peak memory 206788 kb
Host smart-4afef8c1-a5ff-4163-bb55-4a1d6943e3c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13944154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outs
tanding.13944154
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3443560078
Short name T863
Test name
Test status
Simulation time 38227647 ps
CPU time 2.49 seconds
Started May 05 02:28:13 PM PDT 24
Finished May 05 02:28:16 PM PDT 24
Peak memory 214928 kb
Host smart-eb13d8bb-991f-49c9-b518-3e9f6b5e23e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443560078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3443560078
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3266150917
Short name T975
Test name
Test status
Simulation time 312415501 ps
CPU time 2.35 seconds
Started May 05 02:28:15 PM PDT 24
Finished May 05 02:28:17 PM PDT 24
Peak memory 206724 kb
Host smart-d8a68d91-5a04-46ef-b6d5-67c07cad3b28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266150917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3266150917
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.2882553580
Short name T329
Test name
Test status
Simulation time 270487537 ps
CPU time 0.93 seconds
Started May 05 01:52:31 PM PDT 24
Finished May 05 01:52:32 PM PDT 24
Peak memory 206948 kb
Host smart-e7de9ec8-a129-4c11-b575-0819fac525f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882553580 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2882553580
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3445553481
Short name T796
Test name
Test status
Simulation time 50942430 ps
CPU time 1.07 seconds
Started May 05 01:52:31 PM PDT 24
Finished May 05 01:52:32 PM PDT 24
Peak memory 218660 kb
Host smart-dca354df-9e2d-488d-9786-20ca71ae21d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445553481 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3445553481
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.30716358
Short name T144
Test name
Test status
Simulation time 19211588 ps
CPU time 1.05 seconds
Started May 05 01:52:25 PM PDT 24
Finished May 05 01:52:26 PM PDT 24
Peak memory 218896 kb
Host smart-bd404121-89e1-462e-8a1a-e9e8565e3d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30716358 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.30716358
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.133010903
Short name T413
Test name
Test status
Simulation time 56992558 ps
CPU time 1.41 seconds
Started May 05 01:52:26 PM PDT 24
Finished May 05 01:52:28 PM PDT 24
Peak memory 219760 kb
Host smart-d368964c-24a7-47cc-8709-79b7738e814d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133010903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.133010903
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.3526215056
Short name T467
Test name
Test status
Simulation time 37933772 ps
CPU time 0.91 seconds
Started May 05 01:52:27 PM PDT 24
Finished May 05 01:52:28 PM PDT 24
Peak memory 215880 kb
Host smart-887880ed-3d71-44f1-9288-646dc6d49efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526215056 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3526215056
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_smoke.2180953463
Short name T566
Test name
Test status
Simulation time 15760841 ps
CPU time 0.96 seconds
Started May 05 01:52:26 PM PDT 24
Finished May 05 01:52:28 PM PDT 24
Peak memory 215636 kb
Host smart-7ffc508b-8f76-44c0-9109-324e4501e60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180953463 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2180953463
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.758351646
Short name T82
Test name
Test status
Simulation time 231313929 ps
CPU time 1.83 seconds
Started May 05 01:52:25 PM PDT 24
Finished May 05 01:52:27 PM PDT 24
Peak memory 217436 kb
Host smart-abb88498-4055-4769-a0a6-7ddf81cd9772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758351646 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.758351646
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert.2083308939
Short name T641
Test name
Test status
Simulation time 27980041 ps
CPU time 1.23 seconds
Started May 05 01:52:31 PM PDT 24
Finished May 05 01:52:32 PM PDT 24
Peak memory 216040 kb
Host smart-b24289a1-bb5e-4584-b82a-f95448df13f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083308939 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2083308939
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1229694293
Short name T610
Test name
Test status
Simulation time 50766815 ps
CPU time 0.93 seconds
Started May 05 01:52:35 PM PDT 24
Finished May 05 01:52:36 PM PDT 24
Peak memory 206988 kb
Host smart-3f5f96e1-d596-4d97-b6f0-27a2dc965539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229694293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1229694293
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.112873015
Short name T193
Test name
Test status
Simulation time 28915169 ps
CPU time 0.81 seconds
Started May 05 01:52:31 PM PDT 24
Finished May 05 01:52:32 PM PDT 24
Peak memory 216772 kb
Host smart-aa5e05a2-3744-4352-b78e-45288c7090f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112873015 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.112873015
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.2668204807
Short name T714
Test name
Test status
Simulation time 20226241 ps
CPU time 1.07 seconds
Started May 05 01:52:31 PM PDT 24
Finished May 05 01:52:33 PM PDT 24
Peak memory 219228 kb
Host smart-109218e2-b0d3-4e79-8be0-8aafe614f0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668204807 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2668204807
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.4149450303
Short name T444
Test name
Test status
Simulation time 790642511 ps
CPU time 6.74 seconds
Started May 05 01:52:30 PM PDT 24
Finished May 05 01:52:37 PM PDT 24
Peak memory 220116 kb
Host smart-fb1605ee-6011-44d3-8b66-5f12ebbebd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149450303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.4149450303
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3256417766
Short name T42
Test name
Test status
Simulation time 48223412 ps
CPU time 0.87 seconds
Started May 05 01:52:31 PM PDT 24
Finished May 05 01:52:33 PM PDT 24
Peak memory 216088 kb
Host smart-5bd9cbb3-5198-42ba-ad4c-45fe4504cf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256417766 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3256417766
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.2111551259
Short name T294
Test name
Test status
Simulation time 24917325 ps
CPU time 0.96 seconds
Started May 05 01:52:30 PM PDT 24
Finished May 05 01:52:32 PM PDT 24
Peak memory 207444 kb
Host smart-2f5adc80-9f26-4066-994c-3ab5a471b3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111551259 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2111551259
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1382446801
Short name T16
Test name
Test status
Simulation time 860146919 ps
CPU time 4.22 seconds
Started May 05 01:52:32 PM PDT 24
Finished May 05 01:52:36 PM PDT 24
Peak memory 237096 kb
Host smart-56e8033d-3297-4a8f-9264-135e5272f6f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382446801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1382446801
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1915359131
Short name T450
Test name
Test status
Simulation time 52536944 ps
CPU time 0.94 seconds
Started May 05 01:52:31 PM PDT 24
Finished May 05 01:52:32 PM PDT 24
Peak memory 215616 kb
Host smart-26caaca9-5529-42db-ba3b-ea02f9198dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915359131 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1915359131
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3193291543
Short name T170
Test name
Test status
Simulation time 583879802 ps
CPU time 5.99 seconds
Started May 05 01:52:31 PM PDT 24
Finished May 05 01:52:38 PM PDT 24
Peak memory 217472 kb
Host smart-03a0bd76-4e12-4301-8779-65c9ba991c79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193291543 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3193291543
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1732525397
Short name T202
Test name
Test status
Simulation time 233906631467 ps
CPU time 1294.62 seconds
Started May 05 01:52:33 PM PDT 24
Finished May 05 02:14:08 PM PDT 24
Peak memory 224024 kb
Host smart-fd4a37c5-d6d6-4fbd-8a2d-9015117d6a6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732525397 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1732525397
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1633428650
Short name T290
Test name
Test status
Simulation time 28496871 ps
CPU time 1.26 seconds
Started May 05 01:53:01 PM PDT 24
Finished May 05 01:53:03 PM PDT 24
Peak memory 216076 kb
Host smart-5285367c-5009-42f9-a4ae-fc3a34475cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633428650 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1633428650
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.3516899369
Short name T579
Test name
Test status
Simulation time 20894025 ps
CPU time 0.99 seconds
Started May 05 01:53:05 PM PDT 24
Finished May 05 01:53:06 PM PDT 24
Peak memory 207012 kb
Host smart-92efbd67-e938-44f5-ab21-a2bbe77b91ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516899369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3516899369
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.1756274820
Short name T832
Test name
Test status
Simulation time 12856492 ps
CPU time 0.97 seconds
Started May 05 01:53:04 PM PDT 24
Finished May 05 01:53:05 PM PDT 24
Peak memory 215760 kb
Host smart-78fc10a6-8ab4-4b18-9450-bb1b9ef8ad8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756274820 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1756274820
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.745414518
Short name T123
Test name
Test status
Simulation time 23586643 ps
CPU time 1.26 seconds
Started May 05 01:53:02 PM PDT 24
Finished May 05 01:53:04 PM PDT 24
Peak memory 220896 kb
Host smart-ca2b6b6d-7008-4298-9f32-f89e34dd227a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745414518 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.745414518
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3054084103
Short name T665
Test name
Test status
Simulation time 23655528 ps
CPU time 1.18 seconds
Started May 05 01:53:01 PM PDT 24
Finished May 05 01:53:03 PM PDT 24
Peak memory 215680 kb
Host smart-ca1fedf2-7db4-42ab-87e9-2db6c13c62a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054084103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3054084103
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.2521443424
Short name T161
Test name
Test status
Simulation time 21076419 ps
CPU time 1.16 seconds
Started May 05 01:53:03 PM PDT 24
Finished May 05 01:53:05 PM PDT 24
Peak memory 215984 kb
Host smart-a59ed2e6-63f4-4d3b-82fc-582e7e8bba2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521443424 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2521443424
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3320355489
Short name T694
Test name
Test status
Simulation time 93586831 ps
CPU time 0.94 seconds
Started May 05 01:53:01 PM PDT 24
Finished May 05 01:53:02 PM PDT 24
Peak memory 215628 kb
Host smart-2a57a820-7294-43bf-ba59-e1301c82cd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320355489 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3320355489
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3543434600
Short name T709
Test name
Test status
Simulation time 259257060 ps
CPU time 5.39 seconds
Started May 05 01:53:06 PM PDT 24
Finished May 05 01:53:11 PM PDT 24
Peak memory 215628 kb
Host smart-56ed268e-25de-4f2c-8514-459698385dcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543434600 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3543434600
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.984309452
Short name T451
Test name
Test status
Simulation time 82207883078 ps
CPU time 2134.94 seconds
Started May 05 01:53:06 PM PDT 24
Finished May 05 02:28:41 PM PDT 24
Peak memory 230204 kb
Host smart-8a46aa4c-bdbc-43fa-b09b-ead26012d946
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984309452 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.984309452
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.313236747
Short name T535
Test name
Test status
Simulation time 36763104 ps
CPU time 1.37 seconds
Started May 05 01:54:30 PM PDT 24
Finished May 05 01:54:32 PM PDT 24
Peak memory 217192 kb
Host smart-a50e5e7e-cbf1-4147-9ef9-5bf623d54c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313236747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.313236747
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.3402477422
Short name T493
Test name
Test status
Simulation time 121549229 ps
CPU time 1.37 seconds
Started May 05 01:54:29 PM PDT 24
Finished May 05 01:54:31 PM PDT 24
Peak memory 218384 kb
Host smart-bffdf73a-0e1f-4254-9a97-50c03fc80283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402477422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3402477422
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.3940739637
Short name T392
Test name
Test status
Simulation time 100889259 ps
CPU time 1.26 seconds
Started May 05 01:54:28 PM PDT 24
Finished May 05 01:54:30 PM PDT 24
Peak memory 219312 kb
Host smart-63106a46-025c-4c2a-ad4a-fc1ccbaa1957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940739637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3940739637
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.1927256204
Short name T426
Test name
Test status
Simulation time 93680075 ps
CPU time 1.11 seconds
Started May 05 01:54:30 PM PDT 24
Finished May 05 01:54:32 PM PDT 24
Peak memory 217336 kb
Host smart-4893e00b-0277-45e3-aede-b27f25bccc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927256204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1927256204
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.2540923563
Short name T633
Test name
Test status
Simulation time 2318283087 ps
CPU time 66.77 seconds
Started May 05 01:54:29 PM PDT 24
Finished May 05 01:55:36 PM PDT 24
Peak memory 220616 kb
Host smart-b3d963cf-5fe3-4c49-aadc-90357b477123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540923563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2540923563
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.2497666084
Short name T398
Test name
Test status
Simulation time 102864244 ps
CPU time 1.25 seconds
Started May 05 01:54:35 PM PDT 24
Finished May 05 01:54:37 PM PDT 24
Peak memory 217420 kb
Host smart-75fc9031-7192-4027-8144-ede586d7f9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497666084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2497666084
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.965408668
Short name T615
Test name
Test status
Simulation time 42324617 ps
CPU time 1.9 seconds
Started May 05 01:54:27 PM PDT 24
Finished May 05 01:54:29 PM PDT 24
Peak memory 218520 kb
Host smart-5214172f-52e1-4957-b92e-49ee45ef599e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965408668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.965408668
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.4124813990
Short name T96
Test name
Test status
Simulation time 39251373 ps
CPU time 1.33 seconds
Started May 05 01:54:25 PM PDT 24
Finished May 05 01:54:27 PM PDT 24
Peak memory 218380 kb
Host smart-fe9efa4d-415e-46d5-88ee-f6436e4558b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124813990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.4124813990
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1219579458
Short name T140
Test name
Test status
Simulation time 28818337 ps
CPU time 1.31 seconds
Started May 05 01:53:07 PM PDT 24
Finished May 05 01:53:09 PM PDT 24
Peak memory 216068 kb
Host smart-547336fa-cb9d-45f9-aa33-bf35246c8d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219579458 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1219579458
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.1169185960
Short name T385
Test name
Test status
Simulation time 25709548 ps
CPU time 0.93 seconds
Started May 05 01:53:06 PM PDT 24
Finished May 05 01:53:07 PM PDT 24
Peak memory 207008 kb
Host smart-02b6482c-1faf-4d8b-902b-c38ca8dcea0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169185960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1169185960
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3900908428
Short name T184
Test name
Test status
Simulation time 16411678 ps
CPU time 0.82 seconds
Started May 05 01:53:09 PM PDT 24
Finished May 05 01:53:10 PM PDT 24
Peak memory 216536 kb
Host smart-47aa478e-43ef-4a45-9aed-a49d124241f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900908428 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3900908428
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2616711720
Short name T126
Test name
Test status
Simulation time 36220512 ps
CPU time 1.23 seconds
Started May 05 01:53:08 PM PDT 24
Finished May 05 01:53:10 PM PDT 24
Peak memory 217304 kb
Host smart-4b2c2b1d-c277-4ce3-8dce-9de152fe35be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616711720 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2616711720
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1558769055
Short name T751
Test name
Test status
Simulation time 33557187 ps
CPU time 0.92 seconds
Started May 05 01:53:08 PM PDT 24
Finished May 05 01:53:09 PM PDT 24
Peak memory 218984 kb
Host smart-00726970-0eb1-41cb-9c00-65f335e1b352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558769055 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1558769055
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1839945765
Short name T302
Test name
Test status
Simulation time 103497044 ps
CPU time 1.31 seconds
Started May 05 01:53:05 PM PDT 24
Finished May 05 01:53:07 PM PDT 24
Peak memory 219924 kb
Host smart-af0bb5f1-29b7-487a-9a19-4e2873188a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839945765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1839945765
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.3046874290
Short name T827
Test name
Test status
Simulation time 77803107 ps
CPU time 0.89 seconds
Started May 05 01:53:12 PM PDT 24
Finished May 05 01:53:13 PM PDT 24
Peak memory 224100 kb
Host smart-92465216-0871-4827-b834-99f26c585332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046874290 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3046874290
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.4110493177
Short name T372
Test name
Test status
Simulation time 40939965 ps
CPU time 0.9 seconds
Started May 05 01:53:07 PM PDT 24
Finished May 05 01:53:08 PM PDT 24
Peak memory 215604 kb
Host smart-f01c7cb0-7125-4ec1-88f7-e32dc68b445a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110493177 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.4110493177
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.273025466
Short name T79
Test name
Test status
Simulation time 343767251 ps
CPU time 4.88 seconds
Started May 05 01:53:09 PM PDT 24
Finished May 05 01:53:15 PM PDT 24
Peak memory 217072 kb
Host smart-35fef287-47b2-4dcf-810f-bad64cf6ce35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273025466 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.273025466
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2635157070
Short name T386
Test name
Test status
Simulation time 1274726493045 ps
CPU time 2294.63 seconds
Started May 05 01:53:10 PM PDT 24
Finished May 05 02:31:25 PM PDT 24
Peak memory 226212 kb
Host smart-94be9ad8-785d-4c7c-bb83-1b2e868535d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635157070 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2635157070
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.2953636800
Short name T630
Test name
Test status
Simulation time 37364597 ps
CPU time 1.2 seconds
Started May 05 01:54:31 PM PDT 24
Finished May 05 01:54:33 PM PDT 24
Peak memory 218420 kb
Host smart-7e1ae05a-f088-4254-a563-e67f1e3d4dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953636800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2953636800
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.1251849615
Short name T103
Test name
Test status
Simulation time 75945854 ps
CPU time 1.24 seconds
Started May 05 01:54:27 PM PDT 24
Finished May 05 01:54:29 PM PDT 24
Peak memory 217352 kb
Host smart-5c31120e-2bb7-4d0a-ba47-5afe3f2973eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251849615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1251849615
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1221518717
Short name T445
Test name
Test status
Simulation time 47617564 ps
CPU time 1.43 seconds
Started May 05 01:54:29 PM PDT 24
Finished May 05 01:54:31 PM PDT 24
Peak memory 218604 kb
Host smart-0c1ac2de-00f5-44fe-99a4-f56c7c8d7f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221518717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1221518717
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.2504765350
Short name T758
Test name
Test status
Simulation time 148113255 ps
CPU time 2.7 seconds
Started May 05 01:54:29 PM PDT 24
Finished May 05 01:54:32 PM PDT 24
Peak memory 220132 kb
Host smart-796d43e2-87db-47db-b865-7722c8604f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504765350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2504765350
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.1234633489
Short name T698
Test name
Test status
Simulation time 48879392 ps
CPU time 1.8 seconds
Started May 05 01:54:28 PM PDT 24
Finished May 05 01:54:30 PM PDT 24
Peak memory 218564 kb
Host smart-f886e966-5873-4b32-8d63-352233b47e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234633489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1234633489
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.3338452252
Short name T206
Test name
Test status
Simulation time 30173740 ps
CPU time 1.24 seconds
Started May 05 01:54:29 PM PDT 24
Finished May 05 01:54:31 PM PDT 24
Peak memory 215620 kb
Host smart-cc0ffd33-ffb4-4b02-8eb7-399eb52d5073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338452252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3338452252
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.4270192720
Short name T332
Test name
Test status
Simulation time 32038679 ps
CPU time 1.42 seconds
Started May 05 01:54:29 PM PDT 24
Finished May 05 01:54:31 PM PDT 24
Peak memory 218444 kb
Host smart-ecde9795-9748-4f5d-927b-a15b4cb1ee8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270192720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.4270192720
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.3113072421
Short name T720
Test name
Test status
Simulation time 134500376 ps
CPU time 2.89 seconds
Started May 05 01:54:32 PM PDT 24
Finished May 05 01:54:35 PM PDT 24
Peak memory 220332 kb
Host smart-08250ed7-3cbf-45df-84d2-7102dbb85923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113072421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3113072421
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.95727676
Short name T395
Test name
Test status
Simulation time 110528173 ps
CPU time 1.27 seconds
Started May 05 01:54:34 PM PDT 24
Finished May 05 01:54:36 PM PDT 24
Peak memory 217200 kb
Host smart-04258ce9-3dac-4e6e-bf60-3afc6640e257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95727676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.95727676
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.4191782962
Short name T24
Test name
Test status
Simulation time 43793486 ps
CPU time 1.48 seconds
Started May 05 01:54:33 PM PDT 24
Finished May 05 01:54:35 PM PDT 24
Peak memory 218468 kb
Host smart-0bd01420-53f9-461a-8ea9-6f2ac1e4f9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191782962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.4191782962
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.3339799066
Short name T686
Test name
Test status
Simulation time 190964529 ps
CPU time 1.29 seconds
Started May 05 01:53:06 PM PDT 24
Finished May 05 01:53:08 PM PDT 24
Peak memory 216024 kb
Host smart-b4cc4086-6c94-4486-97cd-afb49356a40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339799066 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3339799066
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.536420614
Short name T746
Test name
Test status
Simulation time 81390260 ps
CPU time 0.88 seconds
Started May 05 01:53:11 PM PDT 24
Finished May 05 01:53:12 PM PDT 24
Peak memory 206764 kb
Host smart-996bc0f4-2654-4c2b-8f77-3897d9be2955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536420614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.536420614
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2841614684
Short name T148
Test name
Test status
Simulation time 56728228 ps
CPU time 0.84 seconds
Started May 05 01:53:09 PM PDT 24
Finished May 05 01:53:11 PM PDT 24
Peak memory 216604 kb
Host smart-6f36f423-15b5-42f7-92b5-8de61158dd23
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841614684 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2841614684
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_genbits.2304861794
Short name T378
Test name
Test status
Simulation time 122138559 ps
CPU time 1.42 seconds
Started May 05 01:53:05 PM PDT 24
Finished May 05 01:53:07 PM PDT 24
Peak memory 217320 kb
Host smart-9ff2f3d3-24cf-4059-810e-2307d882462e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304861794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2304861794
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.89649669
Short name T683
Test name
Test status
Simulation time 49270022 ps
CPU time 0.91 seconds
Started May 05 01:53:10 PM PDT 24
Finished May 05 01:53:11 PM PDT 24
Peak memory 215628 kb
Host smart-558aa8ec-0b2a-423e-b731-491926743be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89649669 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.89649669
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3644383057
Short name T764
Test name
Test status
Simulation time 129367795 ps
CPU time 1.8 seconds
Started May 05 01:53:09 PM PDT 24
Finished May 05 01:53:11 PM PDT 24
Peak memory 217404 kb
Host smart-8f793b7d-5d96-4859-8955-649fa4256592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644383057 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3644383057
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1985682988
Short name T440
Test name
Test status
Simulation time 6766873290 ps
CPU time 175.57 seconds
Started May 05 01:53:10 PM PDT 24
Finished May 05 01:56:06 PM PDT 24
Peak memory 218376 kb
Host smart-ab8140e1-5237-4962-a169-a259035bb996
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985682988 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1985682988
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.edn_genbits.44605478
Short name T557
Test name
Test status
Simulation time 70229553 ps
CPU time 2.5 seconds
Started May 05 01:54:33 PM PDT 24
Finished May 05 01:54:36 PM PDT 24
Peak memory 218676 kb
Host smart-4b7f762d-d10f-4fec-8053-204aecf34a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44605478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.44605478
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.1478583809
Short name T12
Test name
Test status
Simulation time 41980777 ps
CPU time 1.11 seconds
Started May 05 01:54:36 PM PDT 24
Finished May 05 01:54:37 PM PDT 24
Peak memory 220024 kb
Host smart-abde443e-68be-43d1-9702-aa165c16177c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478583809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1478583809
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.749146028
Short name T801
Test name
Test status
Simulation time 122931145 ps
CPU time 1.41 seconds
Started May 05 01:54:34 PM PDT 24
Finished May 05 01:54:36 PM PDT 24
Peak memory 219216 kb
Host smart-b7e0e6e9-dc4a-4e69-a9ca-80fe1df4b0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749146028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.749146028
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.3763999088
Short name T463
Test name
Test status
Simulation time 255896238 ps
CPU time 1.71 seconds
Started May 05 01:54:32 PM PDT 24
Finished May 05 01:54:34 PM PDT 24
Peak memory 218632 kb
Host smart-23b6b95f-7f1c-4712-9182-51bc132062a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763999088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3763999088
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2087991816
Short name T574
Test name
Test status
Simulation time 55438925 ps
CPU time 1.97 seconds
Started May 05 01:54:31 PM PDT 24
Finished May 05 01:54:33 PM PDT 24
Peak memory 220092 kb
Host smart-baec3a3f-3180-4746-a487-6b1cba72a05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087991816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2087991816
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1464537699
Short name T629
Test name
Test status
Simulation time 42733578 ps
CPU time 1.24 seconds
Started May 05 01:53:10 PM PDT 24
Finished May 05 01:53:12 PM PDT 24
Peak memory 216076 kb
Host smart-0b216a7d-a659-40d6-8299-2fe72f8bd878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464537699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1464537699
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.66414463
Short name T650
Test name
Test status
Simulation time 28766978 ps
CPU time 1.14 seconds
Started May 05 01:53:12 PM PDT 24
Finished May 05 01:53:14 PM PDT 24
Peak memory 207016 kb
Host smart-dc1702b0-6b2d-4778-9ec5-7783f67b294c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66414463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.66414463
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.550255563
Short name T360
Test name
Test status
Simulation time 40551672 ps
CPU time 1.32 seconds
Started May 05 01:53:08 PM PDT 24
Finished May 05 01:53:10 PM PDT 24
Peak memory 218696 kb
Host smart-1006ca9b-bcb6-46d5-9833-97ab5c0a8f4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550255563 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.550255563
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1306291076
Short name T141
Test name
Test status
Simulation time 30586718 ps
CPU time 1.23 seconds
Started May 05 01:53:09 PM PDT 24
Finished May 05 01:53:10 PM PDT 24
Peak memory 220072 kb
Host smart-80737e90-fd6f-475d-913d-7c5452d0df6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306291076 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1306291076
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1756420492
Short name T800
Test name
Test status
Simulation time 106585277 ps
CPU time 1.38 seconds
Started May 05 01:53:12 PM PDT 24
Finished May 05 01:53:14 PM PDT 24
Peak memory 220072 kb
Host smart-bc4c9279-de1d-425c-9c57-7fea1f0ad414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756420492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1756420492
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3091812327
Short name T485
Test name
Test status
Simulation time 31950767 ps
CPU time 0.86 seconds
Started May 05 01:53:12 PM PDT 24
Finished May 05 01:53:13 PM PDT 24
Peak memory 215960 kb
Host smart-183f4da9-9250-44ed-a559-b85ee4338ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091812327 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3091812327
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2330355919
Short name T519
Test name
Test status
Simulation time 40299876 ps
CPU time 0.88 seconds
Started May 05 01:53:09 PM PDT 24
Finished May 05 01:53:10 PM PDT 24
Peak memory 215528 kb
Host smart-9b72eec4-fdf1-4d7b-b1b8-06db30a69b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330355919 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2330355919
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.4160339410
Short name T287
Test name
Test status
Simulation time 305855208 ps
CPU time 3.64 seconds
Started May 05 01:53:07 PM PDT 24
Finished May 05 01:53:11 PM PDT 24
Peak memory 219960 kb
Host smart-4a28c52f-2fb3-44c4-801c-044b7cda4492
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160339410 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.4160339410
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2141951884
Short name T402
Test name
Test status
Simulation time 105001154295 ps
CPU time 1173.17 seconds
Started May 05 01:53:11 PM PDT 24
Finished May 05 02:12:45 PM PDT 24
Peak memory 224544 kb
Host smart-3931d350-c668-4499-b6f6-9dacb5d70ccb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141951884 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2141951884
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1519447890
Short name T406
Test name
Test status
Simulation time 40040913 ps
CPU time 1.39 seconds
Started May 05 01:54:35 PM PDT 24
Finished May 05 01:54:37 PM PDT 24
Peak memory 215604 kb
Host smart-c9104666-3256-4f63-aa64-b09c2a3dd2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519447890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1519447890
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.2002238482
Short name T741
Test name
Test status
Simulation time 95360077 ps
CPU time 1.21 seconds
Started May 05 01:54:32 PM PDT 24
Finished May 05 01:54:34 PM PDT 24
Peak memory 217316 kb
Host smart-bd6c3a2a-1485-4fee-ae1c-3a985c33fca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002238482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2002238482
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.3875208434
Short name T573
Test name
Test status
Simulation time 100227862 ps
CPU time 1.24 seconds
Started May 05 01:54:33 PM PDT 24
Finished May 05 01:54:34 PM PDT 24
Peak memory 217304 kb
Host smart-bda54a0e-fa0f-49bd-90a4-1f6741eca40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875208434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3875208434
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.2310050645
Short name T369
Test name
Test status
Simulation time 67823585 ps
CPU time 2.29 seconds
Started May 05 01:54:31 PM PDT 24
Finished May 05 01:54:34 PM PDT 24
Peak memory 215540 kb
Host smart-d5f364aa-03cd-4e7d-b961-9ff328ace498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310050645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2310050645
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3801724551
Short name T91
Test name
Test status
Simulation time 34144240 ps
CPU time 1.63 seconds
Started May 05 01:54:31 PM PDT 24
Finished May 05 01:54:34 PM PDT 24
Peak memory 218520 kb
Host smart-827ca924-16db-4966-8417-39b08811bbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801724551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3801724551
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.1403529040
Short name T51
Test name
Test status
Simulation time 77994373 ps
CPU time 1.14 seconds
Started May 05 01:54:33 PM PDT 24
Finished May 05 01:54:34 PM PDT 24
Peak memory 218836 kb
Host smart-5756a8d5-d795-442e-bde8-883008029461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403529040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1403529040
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.1788989690
Short name T729
Test name
Test status
Simulation time 39223918 ps
CPU time 1.42 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:39 PM PDT 24
Peak memory 218568 kb
Host smart-6ef7fcf3-c9ff-47a7-9b3b-3b862cc819dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788989690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1788989690
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.329538080
Short name T282
Test name
Test status
Simulation time 116074246 ps
CPU time 1.66 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:40 PM PDT 24
Peak memory 219072 kb
Host smart-c93e201b-bde8-4e60-924f-ab3877488bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329538080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.329538080
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.3015584959
Short name T510
Test name
Test status
Simulation time 45473185 ps
CPU time 1.58 seconds
Started May 05 01:54:36 PM PDT 24
Finished May 05 01:54:38 PM PDT 24
Peak memory 218228 kb
Host smart-62b7c1e4-c3dc-49ee-81af-5d122d13c1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015584959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3015584959
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3991231618
Short name T803
Test name
Test status
Simulation time 26799204 ps
CPU time 1.33 seconds
Started May 05 01:53:12 PM PDT 24
Finished May 05 01:53:14 PM PDT 24
Peak memory 216044 kb
Host smart-8281d074-9617-4bb2-9739-df6170173249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991231618 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3991231618
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3516485274
Short name T61
Test name
Test status
Simulation time 56690345 ps
CPU time 0.95 seconds
Started May 05 01:53:12 PM PDT 24
Finished May 05 01:53:14 PM PDT 24
Peak memory 206996 kb
Host smart-a321bba7-029b-4f92-bdff-731c542f6cc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516485274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3516485274
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3542535016
Short name T502
Test name
Test status
Simulation time 34171960 ps
CPU time 1.19 seconds
Started May 05 01:53:14 PM PDT 24
Finished May 05 01:53:15 PM PDT 24
Peak memory 218516 kb
Host smart-a7f66e87-dda2-45ba-9a75-ecda40bf91ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542535016 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3542535016
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.4270151668
Short name T115
Test name
Test status
Simulation time 20329636 ps
CPU time 1.25 seconds
Started May 05 01:53:11 PM PDT 24
Finished May 05 01:53:13 PM PDT 24
Peak memory 230096 kb
Host smart-942f4037-2902-4023-9325-975b7e36623e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270151668 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.4270151668
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1085247634
Short name T617
Test name
Test status
Simulation time 31640604 ps
CPU time 1.36 seconds
Started May 05 01:53:11 PM PDT 24
Finished May 05 01:53:13 PM PDT 24
Peak memory 219892 kb
Host smart-4c1314cf-d678-42f4-81b4-38be7b635480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085247634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1085247634
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.599106555
Short name T357
Test name
Test status
Simulation time 50766761 ps
CPU time 0.88 seconds
Started May 05 01:53:13 PM PDT 24
Finished May 05 01:53:14 PM PDT 24
Peak memory 215796 kb
Host smart-221343e7-eda3-411e-ae76-b1826d06128f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599106555 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.599106555
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.254142870
Short name T415
Test name
Test status
Simulation time 50801255 ps
CPU time 0.96 seconds
Started May 05 01:53:14 PM PDT 24
Finished May 05 01:53:16 PM PDT 24
Peak memory 215616 kb
Host smart-e78913a0-a88c-49b0-8be5-edca6093dedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254142870 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.254142870
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3961661925
Short name T583
Test name
Test status
Simulation time 1045097280 ps
CPU time 5.97 seconds
Started May 05 01:53:13 PM PDT 24
Finished May 05 01:53:19 PM PDT 24
Peak memory 217404 kb
Host smart-19beb32d-3f5e-4944-96d3-9893e9b7f18c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961661925 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3961661925
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/140.edn_genbits.3168775430
Short name T422
Test name
Test status
Simulation time 24381075 ps
CPU time 1.16 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:40 PM PDT 24
Peak memory 219900 kb
Host smart-afa26791-26c7-44ba-8e45-0e87475d3789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168775430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3168775430
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.3723995291
Short name T522
Test name
Test status
Simulation time 61027985 ps
CPU time 2.09 seconds
Started May 05 01:54:39 PM PDT 24
Finished May 05 01:54:41 PM PDT 24
Peak memory 218684 kb
Host smart-6d27d937-8972-4bde-9491-ee9fc2d74307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723995291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3723995291
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.2336459551
Short name T412
Test name
Test status
Simulation time 50789035 ps
CPU time 1.87 seconds
Started May 05 01:54:31 PM PDT 24
Finished May 05 01:54:34 PM PDT 24
Peak memory 218596 kb
Host smart-216484f0-2a4f-483b-92f7-8173fb022c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336459551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2336459551
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.3276626175
Short name T264
Test name
Test status
Simulation time 42008601 ps
CPU time 1.04 seconds
Started May 05 01:54:39 PM PDT 24
Finished May 05 01:54:40 PM PDT 24
Peak memory 217268 kb
Host smart-bb36958b-5474-4dea-a153-90ffc5b900f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276626175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3276626175
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1493525925
Short name T655
Test name
Test status
Simulation time 75075332 ps
CPU time 0.96 seconds
Started May 05 01:54:36 PM PDT 24
Finished May 05 01:54:38 PM PDT 24
Peak memory 217440 kb
Host smart-619fd9d8-4d12-47d4-882a-16f3f2e90755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493525925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1493525925
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.3228483125
Short name T405
Test name
Test status
Simulation time 264323270 ps
CPU time 1.2 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:40 PM PDT 24
Peak memory 215616 kb
Host smart-7dd024f8-8a84-4077-bea8-4bc2855a5c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228483125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3228483125
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.4282071864
Short name T713
Test name
Test status
Simulation time 36682345 ps
CPU time 1.49 seconds
Started May 05 01:54:35 PM PDT 24
Finished May 05 01:54:37 PM PDT 24
Peak memory 217348 kb
Host smart-d37c1ed4-50af-4f4c-9ec6-17d536ccd942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282071864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.4282071864
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.314361158
Short name T749
Test name
Test status
Simulation time 529302029 ps
CPU time 4.7 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:44 PM PDT 24
Peak memory 218872 kb
Host smart-47989eb7-c79e-4c16-ae67-66e8e5bfd734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314361158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.314361158
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.3306968353
Short name T761
Test name
Test status
Simulation time 493779936 ps
CPU time 5.51 seconds
Started May 05 01:54:36 PM PDT 24
Finished May 05 01:54:42 PM PDT 24
Peak memory 218380 kb
Host smart-caa75169-c66e-41ff-a80e-648a3999cc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306968353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3306968353
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.2957600476
Short name T563
Test name
Test status
Simulation time 40405608 ps
CPU time 1.23 seconds
Started May 05 01:54:33 PM PDT 24
Finished May 05 01:54:35 PM PDT 24
Peak memory 219892 kb
Host smart-d57f7c69-3c63-4564-b3de-0d3ce53bdd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957600476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2957600476
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.2602220003
Short name T325
Test name
Test status
Simulation time 52520902 ps
CPU time 0.82 seconds
Started May 05 01:53:12 PM PDT 24
Finished May 05 01:53:13 PM PDT 24
Peak memory 206748 kb
Host smart-71ea5099-8061-44c0-bb68-c175005f1731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602220003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2602220003
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3099026875
Short name T46
Test name
Test status
Simulation time 11085424 ps
CPU time 0.92 seconds
Started May 05 01:53:14 PM PDT 24
Finished May 05 01:53:16 PM PDT 24
Peak memory 207540 kb
Host smart-38b134be-3efc-4d3e-9134-e142afb1c4df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099026875 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3099026875
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.90176183
Short name T310
Test name
Test status
Simulation time 44219947 ps
CPU time 1.4 seconds
Started May 05 01:53:16 PM PDT 24
Finished May 05 01:53:18 PM PDT 24
Peak memory 217124 kb
Host smart-5a1595f9-bd84-4643-aab7-cc66df7eeafa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90176183 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_dis
able_auto_req_mode.90176183
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.673220908
Short name T404
Test name
Test status
Simulation time 19668420 ps
CPU time 1.09 seconds
Started May 05 01:53:13 PM PDT 24
Finished May 05 01:53:15 PM PDT 24
Peak memory 219032 kb
Host smart-f27380ae-28f9-4a25-8a04-a92a2f4ea78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673220908 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.673220908
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1788428438
Short name T411
Test name
Test status
Simulation time 45420474 ps
CPU time 1.57 seconds
Started May 05 01:53:11 PM PDT 24
Finished May 05 01:53:13 PM PDT 24
Peak memory 217396 kb
Host smart-8e5ef0a1-6d33-4285-a88d-9224b8b19661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788428438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1788428438
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.3691902214
Short name T168
Test name
Test status
Simulation time 21667691 ps
CPU time 1.07 seconds
Started May 05 01:53:15 PM PDT 24
Finished May 05 01:53:16 PM PDT 24
Peak memory 216240 kb
Host smart-e9264483-4028-4db0-a53c-eb7b4e568626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691902214 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3691902214
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1277872346
Short name T382
Test name
Test status
Simulation time 21818234 ps
CPU time 0.99 seconds
Started May 05 01:53:15 PM PDT 24
Finished May 05 01:53:16 PM PDT 24
Peak memory 215600 kb
Host smart-a7f4cbff-4046-4096-b649-708eb9c40224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277872346 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1277872346
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3666532305
Short name T83
Test name
Test status
Simulation time 149997045 ps
CPU time 3.36 seconds
Started May 05 01:53:13 PM PDT 24
Finished May 05 01:53:17 PM PDT 24
Peak memory 218596 kb
Host smart-fa26f384-cde8-438f-aba3-90618401f254
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666532305 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3666532305
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.4205003140
Short name T669
Test name
Test status
Simulation time 424457611905 ps
CPU time 3012.14 seconds
Started May 05 01:53:16 PM PDT 24
Finished May 05 02:43:29 PM PDT 24
Peak memory 234820 kb
Host smart-f178e84d-842e-4190-bae5-a10b2205fdef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205003140 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.4205003140
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.3721213486
Short name T711
Test name
Test status
Simulation time 56857811 ps
CPU time 1.51 seconds
Started May 05 01:54:32 PM PDT 24
Finished May 05 01:54:34 PM PDT 24
Peak memory 217488 kb
Host smart-c16c5f97-ad64-4ac9-b9d2-41112b4fcf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721213486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3721213486
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.373735495
Short name T331
Test name
Test status
Simulation time 81680377 ps
CPU time 1.08 seconds
Started May 05 01:54:33 PM PDT 24
Finished May 05 01:54:34 PM PDT 24
Peak memory 217384 kb
Host smart-55c9bcb1-f5ba-4edb-b8ac-999caf813003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373735495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.373735495
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.1662480745
Short name T321
Test name
Test status
Simulation time 97730140 ps
CPU time 1.16 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:40 PM PDT 24
Peak memory 217420 kb
Host smart-8a62a764-d385-4436-9767-dc5125e6c6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662480745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1662480745
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.4165997324
Short name T266
Test name
Test status
Simulation time 39820686 ps
CPU time 1.2 seconds
Started May 05 01:54:37 PM PDT 24
Finished May 05 01:54:39 PM PDT 24
Peak memory 218552 kb
Host smart-aab662a5-3599-42b4-8f97-b7d2adfa88ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165997324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.4165997324
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.1133730237
Short name T482
Test name
Test status
Simulation time 86247149 ps
CPU time 1.58 seconds
Started May 05 01:54:37 PM PDT 24
Finished May 05 01:54:39 PM PDT 24
Peak memory 218608 kb
Host smart-0ef8d530-a298-452e-85f1-b026876d9d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133730237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1133730237
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.4178317031
Short name T793
Test name
Test status
Simulation time 59881784 ps
CPU time 1.71 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:40 PM PDT 24
Peak memory 218868 kb
Host smart-9e5dde3e-48d5-4a25-b5b1-4125d9a3f3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178317031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.4178317031
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.1807766612
Short name T560
Test name
Test status
Simulation time 64989123 ps
CPU time 1.05 seconds
Started May 05 01:54:36 PM PDT 24
Finished May 05 01:54:38 PM PDT 24
Peak memory 217376 kb
Host smart-477f4933-2a14-44eb-901b-63c74ec4dc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807766612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1807766612
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.2065813821
Short name T550
Test name
Test status
Simulation time 28967402 ps
CPU time 1.38 seconds
Started May 05 01:54:39 PM PDT 24
Finished May 05 01:54:41 PM PDT 24
Peak memory 220088 kb
Host smart-b1b0fc6a-59bf-429c-a003-d485ba85d101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065813821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2065813821
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.1759814397
Short name T754
Test name
Test status
Simulation time 91973473 ps
CPU time 1.21 seconds
Started May 05 01:54:37 PM PDT 24
Finished May 05 01:54:39 PM PDT 24
Peak memory 217312 kb
Host smart-2cfb9492-0890-4a09-a81e-a436474a0f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759814397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1759814397
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.2016172410
Short name T350
Test name
Test status
Simulation time 39764806 ps
CPU time 1.37 seconds
Started May 05 01:54:32 PM PDT 24
Finished May 05 01:54:34 PM PDT 24
Peak memory 217652 kb
Host smart-5a98d727-d448-43d1-a166-3322f8e55060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016172410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2016172410
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1022447049
Short name T735
Test name
Test status
Simulation time 202187959 ps
CPU time 1.34 seconds
Started May 05 01:53:13 PM PDT 24
Finished May 05 01:53:15 PM PDT 24
Peak memory 216068 kb
Host smart-b16c0d0f-8e2b-4657-bbb5-166f3228714b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022447049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1022447049
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1499768354
Short name T708
Test name
Test status
Simulation time 21573684 ps
CPU time 0.87 seconds
Started May 05 01:53:12 PM PDT 24
Finished May 05 01:53:14 PM PDT 24
Peak memory 215148 kb
Host smart-5363f5bf-ffc7-4b39-87cf-3f43729acd31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499768354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1499768354
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2966215484
Short name T138
Test name
Test status
Simulation time 33521703 ps
CPU time 0.93 seconds
Started May 05 01:53:16 PM PDT 24
Finished May 05 01:53:17 PM PDT 24
Peak memory 216608 kb
Host smart-73aff1df-422d-45d7-8b68-eeef0fe814c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966215484 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2966215484
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3952937107
Short name T765
Test name
Test status
Simulation time 391328716 ps
CPU time 1.14 seconds
Started May 05 01:53:11 PM PDT 24
Finished May 05 01:53:13 PM PDT 24
Peak memory 219816 kb
Host smart-57079370-b036-4a7c-898b-82eeee89d297
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952937107 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3952937107
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1153294527
Short name T581
Test name
Test status
Simulation time 30205192 ps
CPU time 0.87 seconds
Started May 05 01:53:14 PM PDT 24
Finished May 05 01:53:15 PM PDT 24
Peak memory 218504 kb
Host smart-dd3b7bbc-7e98-4da2-a019-77e36b9f53bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153294527 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1153294527
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2972868436
Short name T301
Test name
Test status
Simulation time 52165388 ps
CPU time 1.86 seconds
Started May 05 01:53:16 PM PDT 24
Finished May 05 01:53:18 PM PDT 24
Peak memory 220188 kb
Host smart-090a7ccf-4f34-4b5e-871c-1ce320fc349b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972868436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2972868436
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3041243844
Short name T312
Test name
Test status
Simulation time 24922478 ps
CPU time 0.96 seconds
Started May 05 01:53:15 PM PDT 24
Finished May 05 01:53:16 PM PDT 24
Peak memory 215948 kb
Host smart-64d60321-b1dd-48e8-97bb-efd719c2c9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041243844 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3041243844
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1685933717
Short name T474
Test name
Test status
Simulation time 28909830 ps
CPU time 0.95 seconds
Started May 05 01:53:11 PM PDT 24
Finished May 05 01:53:13 PM PDT 24
Peak memory 215628 kb
Host smart-70f356a8-0e41-4df5-944d-3e639d2d4615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685933717 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1685933717
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1000281686
Short name T734
Test name
Test status
Simulation time 149423235 ps
CPU time 1.9 seconds
Started May 05 01:53:11 PM PDT 24
Finished May 05 01:53:14 PM PDT 24
Peak memory 217436 kb
Host smart-818246b7-5253-4542-97e0-340164eaad21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000281686 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1000281686
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2946191312
Short name T336
Test name
Test status
Simulation time 261483856285 ps
CPU time 1543.99 seconds
Started May 05 01:53:12 PM PDT 24
Finished May 05 02:18:57 PM PDT 24
Peak memory 225728 kb
Host smart-ab2ce434-c491-4750-befa-31e6fae38b64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946191312 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2946191312
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.2692179621
Short name T434
Test name
Test status
Simulation time 40864059 ps
CPU time 1.49 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:41 PM PDT 24
Peak memory 218584 kb
Host smart-ef0ea0de-dfd5-4cc1-9bb1-9545507db1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692179621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2692179621
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.4129609538
Short name T844
Test name
Test status
Simulation time 83566254 ps
CPU time 1.2 seconds
Started May 05 01:54:39 PM PDT 24
Finished May 05 01:54:41 PM PDT 24
Peak memory 217420 kb
Host smart-b4fa7e11-5f23-469b-b896-8973032d662c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129609538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.4129609538
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.1096005408
Short name T681
Test name
Test status
Simulation time 53114957 ps
CPU time 1.63 seconds
Started May 05 01:54:40 PM PDT 24
Finished May 05 01:54:43 PM PDT 24
Peak memory 217252 kb
Host smart-2ce0c115-b4df-4b11-830f-5dc13ab1de38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096005408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1096005408
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2047492373
Short name T55
Test name
Test status
Simulation time 82263981 ps
CPU time 1.74 seconds
Started May 05 01:54:37 PM PDT 24
Finished May 05 01:54:40 PM PDT 24
Peak memory 218696 kb
Host smart-999ad16c-916d-4ae0-9b39-8df06e28f707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047492373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2047492373
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.3067563257
Short name T250
Test name
Test status
Simulation time 170025825 ps
CPU time 1.3 seconds
Started May 05 01:54:37 PM PDT 24
Finished May 05 01:54:39 PM PDT 24
Peak memory 218712 kb
Host smart-41e2e4a6-1f07-40ca-add8-6c84b494a23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067563257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3067563257
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.1785319442
Short name T561
Test name
Test status
Simulation time 55624447 ps
CPU time 2.01 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:41 PM PDT 24
Peak memory 218380 kb
Host smart-a9d2d4b7-8460-467a-a3b8-9015f9352c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785319442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1785319442
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.3108332603
Short name T439
Test name
Test status
Simulation time 31939462 ps
CPU time 1.31 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:40 PM PDT 24
Peak memory 218484 kb
Host smart-f2b3fc49-4acf-4ca9-9627-8ac17a3b2ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108332603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3108332603
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.2906198571
Short name T160
Test name
Test status
Simulation time 27608968 ps
CPU time 1.24 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:39 PM PDT 24
Peak memory 218564 kb
Host smart-764bfaaa-50b9-4450-89f5-dc230ae30b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906198571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2906198571
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.3299911522
Short name T379
Test name
Test status
Simulation time 55157941 ps
CPU time 1.24 seconds
Started May 05 01:54:41 PM PDT 24
Finished May 05 01:54:43 PM PDT 24
Peak memory 219944 kb
Host smart-bde351e0-f7b9-4723-95d0-339ae4a1e193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299911522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3299911522
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2999712087
Short name T93
Test name
Test status
Simulation time 43082741 ps
CPU time 1.15 seconds
Started May 05 01:53:12 PM PDT 24
Finished May 05 01:53:13 PM PDT 24
Peak memory 216028 kb
Host smart-40f93a24-bacf-47df-a6cb-67af894e2f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999712087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2999712087
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3222786157
Short name T830
Test name
Test status
Simulation time 31828760 ps
CPU time 0.93 seconds
Started May 05 01:53:18 PM PDT 24
Finished May 05 01:53:19 PM PDT 24
Peak memory 206932 kb
Host smart-9111b90e-fff2-40fb-bf61-1d59e1f81c3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222786157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3222786157
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.2323306741
Short name T349
Test name
Test status
Simulation time 39659468 ps
CPU time 0.89 seconds
Started May 05 01:53:12 PM PDT 24
Finished May 05 01:53:13 PM PDT 24
Peak memory 216188 kb
Host smart-e6dc8d77-6c41-4afe-a0fa-4bd6897eb818
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323306741 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2323306741
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3941668267
Short name T112
Test name
Test status
Simulation time 44821561 ps
CPU time 1.43 seconds
Started May 05 01:53:13 PM PDT 24
Finished May 05 01:53:15 PM PDT 24
Peak memory 217280 kb
Host smart-96494dc0-2e20-42d3-8a79-9ca46a6d5f33
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941668267 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3941668267
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1442706457
Short name T186
Test name
Test status
Simulation time 44789338 ps
CPU time 1.15 seconds
Started May 05 01:53:11 PM PDT 24
Finished May 05 01:53:13 PM PDT 24
Peak memory 220284 kb
Host smart-e36f7180-c160-4012-9d8e-d36833df2fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442706457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1442706457
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_intr.3445292797
Short name T470
Test name
Test status
Simulation time 47101264 ps
CPU time 0.84 seconds
Started May 05 01:53:16 PM PDT 24
Finished May 05 01:53:17 PM PDT 24
Peak memory 215624 kb
Host smart-d9639f0a-554f-412a-9874-1aa07a39da3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445292797 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3445292797
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2795439509
Short name T452
Test name
Test status
Simulation time 26047978 ps
CPU time 0.97 seconds
Started May 05 01:53:12 PM PDT 24
Finished May 05 01:53:13 PM PDT 24
Peak memory 215628 kb
Host smart-48f58907-5759-4c4a-885c-4739073143f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795439509 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2795439509
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3745559479
Short name T67
Test name
Test status
Simulation time 344044407 ps
CPU time 6.57 seconds
Started May 05 01:53:11 PM PDT 24
Finished May 05 01:53:19 PM PDT 24
Peak memory 220156 kb
Host smart-39d854a5-7084-41b8-b5ef-d0588af629eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745559479 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3745559479
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.348576962
Short name T427
Test name
Test status
Simulation time 39687912512 ps
CPU time 528.72 seconds
Started May 05 01:53:13 PM PDT 24
Finished May 05 02:02:03 PM PDT 24
Peak memory 223984 kb
Host smart-ba621d13-02e2-424a-85af-f555be28704d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348576962 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.348576962
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.2271352564
Short name T260
Test name
Test status
Simulation time 66850711 ps
CPU time 1.21 seconds
Started May 05 01:54:36 PM PDT 24
Finished May 05 01:54:38 PM PDT 24
Peak memory 218816 kb
Host smart-a6273556-d488-4ed0-b6f0-95a1c564c95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271352564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2271352564
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.2899424825
Short name T772
Test name
Test status
Simulation time 67293133 ps
CPU time 1.07 seconds
Started May 05 01:54:40 PM PDT 24
Finished May 05 01:54:42 PM PDT 24
Peak memory 219024 kb
Host smart-d0b43907-b7f7-493c-98cc-b8a83ef892e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899424825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2899424825
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.670798743
Short name T340
Test name
Test status
Simulation time 43067876 ps
CPU time 1.48 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:40 PM PDT 24
Peak memory 218268 kb
Host smart-0ab82562-5984-4363-80d0-0caed24041bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670798743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.670798743
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.1416932787
Short name T50
Test name
Test status
Simulation time 139254058 ps
CPU time 1.17 seconds
Started May 05 01:54:39 PM PDT 24
Finished May 05 01:54:41 PM PDT 24
Peak memory 217272 kb
Host smart-04bfb059-3db0-4759-b3a4-0dc0694e7808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416932787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1416932787
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.3307532039
Short name T279
Test name
Test status
Simulation time 81238735 ps
CPU time 2.86 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:41 PM PDT 24
Peak memory 220032 kb
Host smart-f9348486-f65e-4368-adfb-bf777ad3bfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307532039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3307532039
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.793581415
Short name T601
Test name
Test status
Simulation time 50028744 ps
CPU time 1.17 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:39 PM PDT 24
Peak memory 217324 kb
Host smart-679999be-58f8-48ab-9385-aa242a4ad491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793581415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.793581415
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.1390091423
Short name T500
Test name
Test status
Simulation time 30930211 ps
CPU time 1.35 seconds
Started May 05 01:54:36 PM PDT 24
Finished May 05 01:54:38 PM PDT 24
Peak memory 218380 kb
Host smart-884eca91-052e-455e-8f99-8f303c0e823c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390091423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1390091423
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2533815796
Short name T446
Test name
Test status
Simulation time 34320036 ps
CPU time 1.39 seconds
Started May 05 01:54:42 PM PDT 24
Finished May 05 01:54:44 PM PDT 24
Peak memory 217800 kb
Host smart-9d6b7d0e-9ac8-49b4-ad80-978285bc1172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533815796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2533815796
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.122004568
Short name T685
Test name
Test status
Simulation time 91715141 ps
CPU time 1.68 seconds
Started May 05 01:54:40 PM PDT 24
Finished May 05 01:54:43 PM PDT 24
Peak memory 219168 kb
Host smart-219364fd-ac49-4499-89c7-d477fd44123a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122004568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.122004568
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.2012195934
Short name T704
Test name
Test status
Simulation time 69540870 ps
CPU time 1 seconds
Started May 05 01:54:37 PM PDT 24
Finished May 05 01:54:38 PM PDT 24
Peak memory 217284 kb
Host smart-af4f79fc-2400-43f1-8318-676ac318d33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012195934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2012195934
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.229755667
Short name T823
Test name
Test status
Simulation time 79176128 ps
CPU time 1.1 seconds
Started May 05 01:53:17 PM PDT 24
Finished May 05 01:53:19 PM PDT 24
Peak memory 216052 kb
Host smart-34f6aee8-687e-40ff-80a3-e2f93a0e0a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229755667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.229755667
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.241553371
Short name T829
Test name
Test status
Simulation time 19996495 ps
CPU time 0.98 seconds
Started May 05 01:53:17 PM PDT 24
Finished May 05 01:53:18 PM PDT 24
Peak memory 206916 kb
Host smart-35216589-166e-4f44-8d76-26c88842b776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241553371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.241553371
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2185262307
Short name T30
Test name
Test status
Simulation time 36598016 ps
CPU time 0.81 seconds
Started May 05 01:53:18 PM PDT 24
Finished May 05 01:53:19 PM PDT 24
Peak memory 216372 kb
Host smart-ddc0fb7c-0527-45e2-85fe-34aa8e0ab2f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185262307 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2185262307
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3234803355
Short name T638
Test name
Test status
Simulation time 29580355 ps
CPU time 1.19 seconds
Started May 05 01:53:17 PM PDT 24
Finished May 05 01:53:18 PM PDT 24
Peak memory 217352 kb
Host smart-05e8e537-62bd-4763-bbfe-914307d6ae39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234803355 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3234803355
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.784788755
Short name T131
Test name
Test status
Simulation time 22055176 ps
CPU time 1.02 seconds
Started May 05 01:53:19 PM PDT 24
Finished May 05 01:53:21 PM PDT 24
Peak memory 224440 kb
Host smart-59104b58-49b3-4ae4-a519-3d4eaf2983ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784788755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.784788755
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2781642704
Short name T374
Test name
Test status
Simulation time 45708111 ps
CPU time 1.58 seconds
Started May 05 01:53:18 PM PDT 24
Finished May 05 01:53:20 PM PDT 24
Peak memory 218524 kb
Host smart-f93a8e43-be2a-4dfc-b065-3de30b78cf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781642704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2781642704
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1744626308
Short name T526
Test name
Test status
Simulation time 77659012 ps
CPU time 0.84 seconds
Started May 05 01:53:18 PM PDT 24
Finished May 05 01:53:19 PM PDT 24
Peak memory 215772 kb
Host smart-2d6ad9dc-d281-45f5-ac43-9b7a39488e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744626308 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1744626308
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.28747888
Short name T516
Test name
Test status
Simulation time 38345242 ps
CPU time 0.91 seconds
Started May 05 01:53:17 PM PDT 24
Finished May 05 01:53:19 PM PDT 24
Peak memory 215620 kb
Host smart-d526b991-feac-47a5-8718-13882f6f66d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28747888 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.28747888
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.309100782
Short name T210
Test name
Test status
Simulation time 1270539937 ps
CPU time 5.13 seconds
Started May 05 01:53:20 PM PDT 24
Finished May 05 01:53:25 PM PDT 24
Peak memory 217140 kb
Host smart-5208789e-6a0a-4e94-b5f8-7c9bd302cffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309100782 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.309100782
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1063350560
Short name T679
Test name
Test status
Simulation time 12809641375 ps
CPU time 334.65 seconds
Started May 05 01:53:18 PM PDT 24
Finished May 05 01:58:53 PM PDT 24
Peak memory 218340 kb
Host smart-1535b502-33c8-4e92-a861-92c63ef8ec87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063350560 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1063350560
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.4261434272
Short name T506
Test name
Test status
Simulation time 58280575 ps
CPU time 1.09 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:40 PM PDT 24
Peak memory 217472 kb
Host smart-3071b650-2da2-44a8-b2f1-5f9c28392378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261434272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.4261434272
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.2613081994
Short name T473
Test name
Test status
Simulation time 46447157 ps
CPU time 1.04 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:40 PM PDT 24
Peak memory 217280 kb
Host smart-3d3329e5-d10a-4add-8509-a2e09b6a36e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613081994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2613081994
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.2317612042
Short name T652
Test name
Test status
Simulation time 28718171 ps
CPU time 1.25 seconds
Started May 05 01:54:40 PM PDT 24
Finished May 05 01:54:42 PM PDT 24
Peak memory 217748 kb
Host smart-99a5c447-188f-4552-80fb-ae853d1367e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317612042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2317612042
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.3840466690
Short name T786
Test name
Test status
Simulation time 76061906 ps
CPU time 1.11 seconds
Started May 05 01:54:40 PM PDT 24
Finished May 05 01:54:42 PM PDT 24
Peak memory 215616 kb
Host smart-20621bed-1e86-493a-b0f8-5a853f83c5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840466690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3840466690
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.1072135196
Short name T518
Test name
Test status
Simulation time 106799930 ps
CPU time 2.67 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:42 PM PDT 24
Peak memory 220264 kb
Host smart-b98de9ae-d3a6-4850-95cb-7181bbfb3dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072135196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1072135196
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.236185535
Short name T308
Test name
Test status
Simulation time 55170521 ps
CPU time 1.24 seconds
Started May 05 01:54:37 PM PDT 24
Finished May 05 01:54:38 PM PDT 24
Peak memory 217424 kb
Host smart-044f4ec8-5f13-4b10-930a-65895fe7fc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236185535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.236185535
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.667242228
Short name T586
Test name
Test status
Simulation time 67831039 ps
CPU time 1.2 seconds
Started May 05 01:54:40 PM PDT 24
Finished May 05 01:54:42 PM PDT 24
Peak memory 217416 kb
Host smart-4df25970-0f41-4ca4-aa09-f84a7b86871d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667242228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.667242228
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.1549413387
Short name T458
Test name
Test status
Simulation time 148937247 ps
CPU time 1.05 seconds
Started May 05 01:54:38 PM PDT 24
Finished May 05 01:54:40 PM PDT 24
Peak memory 217204 kb
Host smart-b1cd574c-5742-486b-b0ff-af487a8676e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549413387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1549413387
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.2794026882
Short name T527
Test name
Test status
Simulation time 312643728 ps
CPU time 1.84 seconds
Started May 05 01:54:41 PM PDT 24
Finished May 05 01:54:43 PM PDT 24
Peak memory 218924 kb
Host smart-419c3bba-9485-4388-b7d4-3c778dbd933c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794026882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2794026882
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1302300747
Short name T649
Test name
Test status
Simulation time 31675773 ps
CPU time 1.32 seconds
Started May 05 01:53:19 PM PDT 24
Finished May 05 01:53:21 PM PDT 24
Peak memory 216076 kb
Host smart-f669c36c-5317-4b36-b038-64622294a7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302300747 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1302300747
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3153817187
Short name T327
Test name
Test status
Simulation time 40555558 ps
CPU time 0.84 seconds
Started May 05 01:53:17 PM PDT 24
Finished May 05 01:53:18 PM PDT 24
Peak memory 215556 kb
Host smart-88da5c6f-5f6f-4643-abca-d56ea1064fa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153817187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3153817187
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.4050698237
Short name T76
Test name
Test status
Simulation time 87068886 ps
CPU time 1.11 seconds
Started May 05 01:53:18 PM PDT 24
Finished May 05 01:53:20 PM PDT 24
Peak memory 218712 kb
Host smart-3baf6297-0a75-4e6b-a381-4ad346c12374
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050698237 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.4050698237
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.732842676
Short name T737
Test name
Test status
Simulation time 49686535 ps
CPU time 0.98 seconds
Started May 05 01:53:16 PM PDT 24
Finished May 05 01:53:17 PM PDT 24
Peak memory 218880 kb
Host smart-f418dbc1-02e7-4390-a698-548d552c3ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732842676 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.732842676
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1315454300
Short name T757
Test name
Test status
Simulation time 39566466 ps
CPU time 1.35 seconds
Started May 05 01:53:18 PM PDT 24
Finished May 05 01:53:20 PM PDT 24
Peak memory 217352 kb
Host smart-0ae44008-6c30-4201-a5a5-ef7202f392af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315454300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1315454300
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.923128988
Short name T700
Test name
Test status
Simulation time 24663164 ps
CPU time 0.94 seconds
Started May 05 01:53:20 PM PDT 24
Finished May 05 01:53:21 PM PDT 24
Peak memory 216328 kb
Host smart-68241659-495d-46ee-bf70-3eb052f9747e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923128988 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.923128988
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.48029535
Short name T603
Test name
Test status
Simulation time 27038136 ps
CPU time 0.88 seconds
Started May 05 01:53:15 PM PDT 24
Finished May 05 01:53:16 PM PDT 24
Peak memory 215560 kb
Host smart-e9835acd-94ce-4933-9316-bfe7b90bac20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48029535 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.48029535
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1233235518
Short name T730
Test name
Test status
Simulation time 172938000 ps
CPU time 3.93 seconds
Started May 05 01:53:19 PM PDT 24
Finished May 05 01:53:23 PM PDT 24
Peak memory 217264 kb
Host smart-437e270f-d052-40e7-8c0b-5218f04537a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233235518 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1233235518
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2919926761
Short name T441
Test name
Test status
Simulation time 174078732142 ps
CPU time 1036.22 seconds
Started May 05 01:53:17 PM PDT 24
Finished May 05 02:10:34 PM PDT 24
Peak memory 224044 kb
Host smart-4f15d2b6-4b69-4120-810e-1cf56c04940d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919926761 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2919926761
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.735727797
Short name T403
Test name
Test status
Simulation time 108797067 ps
CPU time 2.66 seconds
Started May 05 01:54:39 PM PDT 24
Finished May 05 01:54:42 PM PDT 24
Peak memory 217732 kb
Host smart-6c0355ad-773a-4729-a0a7-36210c64e405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735727797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.735727797
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.535273386
Short name T388
Test name
Test status
Simulation time 27384615 ps
CPU time 1.32 seconds
Started May 05 01:54:39 PM PDT 24
Finished May 05 01:54:41 PM PDT 24
Peak memory 218528 kb
Host smart-49f693d2-75c3-4382-a349-23e2e78f027e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535273386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.535273386
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.67916884
Short name T303
Test name
Test status
Simulation time 235686303 ps
CPU time 2.45 seconds
Started May 05 01:54:49 PM PDT 24
Finished May 05 01:54:52 PM PDT 24
Peak memory 217484 kb
Host smart-d0418ad4-318b-44fc-ac6e-33445e8674d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67916884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.67916884
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3227815565
Short name T363
Test name
Test status
Simulation time 52846488 ps
CPU time 1.61 seconds
Started May 05 01:54:44 PM PDT 24
Finished May 05 01:54:47 PM PDT 24
Peak memory 218560 kb
Host smart-233092ff-56cb-426d-b3b8-b80e9a2ff7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227815565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3227815565
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.1730747819
Short name T692
Test name
Test status
Simulation time 59975987 ps
CPU time 1.5 seconds
Started May 05 01:54:45 PM PDT 24
Finished May 05 01:54:47 PM PDT 24
Peak memory 220072 kb
Host smart-4bdf938f-a49d-4d02-ac42-c88ccc6a1599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730747819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1730747819
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.3007725222
Short name T575
Test name
Test status
Simulation time 61561074 ps
CPU time 1.09 seconds
Started May 05 01:54:45 PM PDT 24
Finished May 05 01:54:47 PM PDT 24
Peak memory 219788 kb
Host smart-11c2fa38-e06d-44c6-90de-cce74a8df55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007725222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3007725222
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.1881888885
Short name T420
Test name
Test status
Simulation time 304882706 ps
CPU time 2.69 seconds
Started May 05 01:54:44 PM PDT 24
Finished May 05 01:54:47 PM PDT 24
Peak memory 220340 kb
Host smart-3580d7c0-a9e0-4d0f-a87b-f1330bcfe779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881888885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1881888885
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.3918086947
Short name T562
Test name
Test status
Simulation time 51419211 ps
CPU time 2.06 seconds
Started May 05 01:54:44 PM PDT 24
Finished May 05 01:54:47 PM PDT 24
Peak memory 218580 kb
Host smart-7402a0f4-63ce-4f2d-b236-f7a2df3ffec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918086947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3918086947
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.3513657016
Short name T270
Test name
Test status
Simulation time 88823775 ps
CPU time 1.65 seconds
Started May 05 01:54:42 PM PDT 24
Finished May 05 01:54:44 PM PDT 24
Peak memory 220412 kb
Host smart-f63059fd-42b7-44d0-90da-03033356f1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513657016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3513657016
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert_test.3824335752
Short name T699
Test name
Test status
Simulation time 26286473 ps
CPU time 0.89 seconds
Started May 05 01:52:37 PM PDT 24
Finished May 05 01:52:38 PM PDT 24
Peak memory 206988 kb
Host smart-2d01ab32-739b-4a9b-8215-f2c832f21a3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824335752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3824335752
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3806260117
Short name T814
Test name
Test status
Simulation time 16805599 ps
CPU time 0.84 seconds
Started May 05 01:52:35 PM PDT 24
Finished May 05 01:52:36 PM PDT 24
Peak memory 216568 kb
Host smart-66cca37c-4e8e-4181-991e-3b60dd7a39a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806260117 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3806260117
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3344132798
Short name T578
Test name
Test status
Simulation time 386152406 ps
CPU time 1.12 seconds
Started May 05 01:52:35 PM PDT 24
Finished May 05 01:52:36 PM PDT 24
Peak memory 217264 kb
Host smart-a3e9f76a-61c4-4c6e-93a7-8b12047a9546
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344132798 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3344132798
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.4044513492
Short name T309
Test name
Test status
Simulation time 28838806 ps
CPU time 0.83 seconds
Started May 05 01:52:34 PM PDT 24
Finished May 05 01:52:36 PM PDT 24
Peak memory 218304 kb
Host smart-6f974975-b68d-4624-a748-5a321793291d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044513492 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.4044513492
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.4027640874
Short name T469
Test name
Test status
Simulation time 57098442 ps
CPU time 1.61 seconds
Started May 05 01:52:39 PM PDT 24
Finished May 05 01:52:41 PM PDT 24
Peak memory 218640 kb
Host smart-a9d0c57e-17ac-4d74-81f7-da4933e2bde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027640874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.4027640874
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3082021842
Short name T494
Test name
Test status
Simulation time 45062699 ps
CPU time 0.88 seconds
Started May 05 01:52:37 PM PDT 24
Finished May 05 01:52:38 PM PDT 24
Peak memory 215656 kb
Host smart-b4259755-1367-4d66-b4c1-26e5200d2d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082021842 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3082021842
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3137755201
Short name T530
Test name
Test status
Simulation time 32048861 ps
CPU time 0.93 seconds
Started May 05 01:52:34 PM PDT 24
Finished May 05 01:52:36 PM PDT 24
Peak memory 207388 kb
Host smart-935ba3b6-9030-4da9-bb29-412145cbd2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137755201 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3137755201
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.420040070
Short name T71
Test name
Test status
Simulation time 2749493194 ps
CPU time 4.45 seconds
Started May 05 01:52:37 PM PDT 24
Finished May 05 01:52:42 PM PDT 24
Peak memory 237164 kb
Host smart-dd124839-fa13-4fba-8c2e-4d0516db07aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420040070 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.420040070
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3635157454
Short name T810
Test name
Test status
Simulation time 167627259 ps
CPU time 0.91 seconds
Started May 05 01:52:38 PM PDT 24
Finished May 05 01:52:40 PM PDT 24
Peak memory 215580 kb
Host smart-5c9b6ca0-a53f-47d3-8217-1503a6dfd489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635157454 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3635157454
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2661687628
Short name T569
Test name
Test status
Simulation time 269655862 ps
CPU time 4.73 seconds
Started May 05 01:52:37 PM PDT 24
Finished May 05 01:52:42 PM PDT 24
Peak memory 218364 kb
Host smart-604fb407-3455-4b8b-8311-91375a8c2443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661687628 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2661687628
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2253422468
Short name T597
Test name
Test status
Simulation time 47992557798 ps
CPU time 296.6 seconds
Started May 05 01:52:39 PM PDT 24
Finished May 05 01:57:36 PM PDT 24
Peak memory 217736 kb
Host smart-2c5f15e7-aead-4785-aaa1-046ab0621cf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253422468 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2253422468
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2016082893
Short name T57
Test name
Test status
Simulation time 26753545 ps
CPU time 1.28 seconds
Started May 05 01:53:20 PM PDT 24
Finished May 05 01:53:21 PM PDT 24
Peak memory 216080 kb
Host smart-3add6438-ef1c-41b6-b2cd-cc8e8cf4a837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016082893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2016082893
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.929001207
Short name T543
Test name
Test status
Simulation time 50418246 ps
CPU time 0.9 seconds
Started May 05 01:53:20 PM PDT 24
Finished May 05 01:53:21 PM PDT 24
Peak memory 206948 kb
Host smart-33a68d4b-a877-4a03-a2ec-9c8964da5ca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929001207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.929001207
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1128037189
Short name T662
Test name
Test status
Simulation time 26886287 ps
CPU time 0.89 seconds
Started May 05 01:53:23 PM PDT 24
Finished May 05 01:53:24 PM PDT 24
Peak memory 216236 kb
Host smart-0d47ad52-006f-4a6f-9b1e-6260c90a1f62
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128037189 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1128037189
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.2405878894
Short name T136
Test name
Test status
Simulation time 21997823 ps
CPU time 1.06 seconds
Started May 05 01:53:17 PM PDT 24
Finished May 05 01:53:19 PM PDT 24
Peak memory 224432 kb
Host smart-43bfb600-bf98-4861-abc6-f5366b4f72a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405878894 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2405878894
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2580788345
Short name T828
Test name
Test status
Simulation time 42490339 ps
CPU time 1.15 seconds
Started May 05 01:53:19 PM PDT 24
Finished May 05 01:53:21 PM PDT 24
Peak memory 220132 kb
Host smart-e05a4c83-6582-4b8d-bdb8-5470a86967d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580788345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2580788345
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1829511367
Short name T104
Test name
Test status
Simulation time 37168695 ps
CPU time 0.85 seconds
Started May 05 01:53:18 PM PDT 24
Finished May 05 01:53:19 PM PDT 24
Peak memory 216016 kb
Host smart-31040dca-2aee-4da5-89d9-e2b16a849223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829511367 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1829511367
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2469555932
Short name T381
Test name
Test status
Simulation time 17695323 ps
CPU time 1.01 seconds
Started May 05 01:53:19 PM PDT 24
Finished May 05 01:53:20 PM PDT 24
Peak memory 215592 kb
Host smart-ffdc6f47-8d77-46a3-a63f-2da1a90b9a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469555932 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2469555932
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3855278800
Short name T756
Test name
Test status
Simulation time 796614593 ps
CPU time 3.64 seconds
Started May 05 01:53:18 PM PDT 24
Finished May 05 01:53:22 PM PDT 24
Peak memory 217304 kb
Host smart-fa99f0c5-6c47-4076-8e27-d266e8d54f73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855278800 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3855278800
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3332195648
Short name T396
Test name
Test status
Simulation time 129810452148 ps
CPU time 231.34 seconds
Started May 05 01:53:20 PM PDT 24
Finished May 05 01:57:11 PM PDT 24
Peak memory 222064 kb
Host smart-95b2e0b7-d30e-44dd-ae57-d49b7c846643
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332195648 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3332195648
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3243602670
Short name T580
Test name
Test status
Simulation time 33229801 ps
CPU time 1.12 seconds
Started May 05 01:54:46 PM PDT 24
Finished May 05 01:54:47 PM PDT 24
Peak memory 218540 kb
Host smart-6c5062db-6c32-469f-8b47-cb2286d34226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243602670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3243602670
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2003433001
Short name T604
Test name
Test status
Simulation time 48428208 ps
CPU time 1.78 seconds
Started May 05 01:54:44 PM PDT 24
Finished May 05 01:54:46 PM PDT 24
Peak memory 218644 kb
Host smart-7b8bdf51-ea8c-4415-8f74-8a0afb326e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003433001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2003433001
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.481465181
Short name T608
Test name
Test status
Simulation time 53427202 ps
CPU time 1.74 seconds
Started May 05 01:54:42 PM PDT 24
Finished May 05 01:54:44 PM PDT 24
Peak memory 218444 kb
Host smart-a4535380-c85b-47d2-9d02-ccbdafb624bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481465181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.481465181
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.162742410
Short name T466
Test name
Test status
Simulation time 55358286 ps
CPU time 1.21 seconds
Started May 05 01:54:42 PM PDT 24
Finished May 05 01:54:44 PM PDT 24
Peak memory 217284 kb
Host smart-e25aac98-f8ab-47e3-8de9-81536e41c42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162742410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.162742410
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3459364958
Short name T475
Test name
Test status
Simulation time 44032234 ps
CPU time 1.49 seconds
Started May 05 01:54:42 PM PDT 24
Finished May 05 01:54:44 PM PDT 24
Peak memory 218468 kb
Host smart-35f78019-92a3-4bd8-bd14-6beb16e13ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459364958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3459364958
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3837783463
Short name T215
Test name
Test status
Simulation time 183280037 ps
CPU time 2.79 seconds
Started May 05 01:54:45 PM PDT 24
Finished May 05 01:54:48 PM PDT 24
Peak memory 217520 kb
Host smart-454a3708-5074-4d4b-8645-83ed128168ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837783463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3837783463
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3261990630
Short name T536
Test name
Test status
Simulation time 110727663 ps
CPU time 1.09 seconds
Started May 05 01:54:46 PM PDT 24
Finished May 05 01:54:48 PM PDT 24
Peak memory 217484 kb
Host smart-e5d80ebf-be49-4e35-9f02-7bf9646dd337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261990630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3261990630
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2268244990
Short name T551
Test name
Test status
Simulation time 87673932 ps
CPU time 1.42 seconds
Started May 05 01:54:42 PM PDT 24
Finished May 05 01:54:44 PM PDT 24
Peak memory 219012 kb
Host smart-8b47ad5a-a7bb-4204-8370-b283960843e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268244990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2268244990
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2888998114
Short name T486
Test name
Test status
Simulation time 51850197 ps
CPU time 2.06 seconds
Started May 05 01:54:42 PM PDT 24
Finished May 05 01:54:45 PM PDT 24
Peak memory 218628 kb
Host smart-942e701f-648b-4a0c-a20a-1f8a4ed67562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888998114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2888998114
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2049669630
Short name T278
Test name
Test status
Simulation time 47779330 ps
CPU time 1.61 seconds
Started May 05 01:54:47 PM PDT 24
Finished May 05 01:54:49 PM PDT 24
Peak memory 218776 kb
Host smart-b178b421-cd52-4d4e-aa6f-8db2b0ae8e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049669630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2049669630
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2341020812
Short name T165
Test name
Test status
Simulation time 31123534 ps
CPU time 1.32 seconds
Started May 05 01:53:23 PM PDT 24
Finished May 05 01:53:25 PM PDT 24
Peak memory 216016 kb
Host smart-76abfb5c-ccb6-4931-ad97-7a298164c3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341020812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2341020812
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3258392753
Short name T707
Test name
Test status
Simulation time 16141993 ps
CPU time 0.93 seconds
Started May 05 01:53:26 PM PDT 24
Finished May 05 01:53:27 PM PDT 24
Peak memory 206968 kb
Host smart-2e95875b-aaf8-4874-840d-f2a141a52124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258392753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3258392753
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1891760069
Short name T552
Test name
Test status
Simulation time 17131374 ps
CPU time 0.87 seconds
Started May 05 01:53:22 PM PDT 24
Finished May 05 01:53:23 PM PDT 24
Peak memory 216404 kb
Host smart-2aaeb704-eb50-43f4-9139-6e1af179a311
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891760069 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1891760069
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2509223786
Short name T348
Test name
Test status
Simulation time 28130233 ps
CPU time 1.04 seconds
Started May 05 01:53:24 PM PDT 24
Finished May 05 01:53:25 PM PDT 24
Peak memory 217092 kb
Host smart-e4fcfcf8-70a3-418f-858d-f0122cd726e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509223786 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2509223786
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.2205217555
Short name T478
Test name
Test status
Simulation time 18913574 ps
CPU time 1.02 seconds
Started May 05 01:53:22 PM PDT 24
Finished May 05 01:53:23 PM PDT 24
Peak memory 218612 kb
Host smart-17375288-8753-44ec-b46f-49bf8ab8ab9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205217555 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2205217555
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2969697293
Short name T400
Test name
Test status
Simulation time 44480307 ps
CPU time 1.51 seconds
Started May 05 01:53:23 PM PDT 24
Finished May 05 01:53:25 PM PDT 24
Peak memory 218560 kb
Host smart-e08ea142-2f41-4ff1-8b25-ba80e39a116a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969697293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2969697293
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_smoke.2038823540
Short name T315
Test name
Test status
Simulation time 30489051 ps
CPU time 0.91 seconds
Started May 05 01:53:22 PM PDT 24
Finished May 05 01:53:23 PM PDT 24
Peak memory 215604 kb
Host smart-877ece1a-bef3-40de-9a39-b0f5fe50ed55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038823540 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2038823540
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2799742669
Short name T334
Test name
Test status
Simulation time 563423434 ps
CPU time 5.75 seconds
Started May 05 01:53:21 PM PDT 24
Finished May 05 01:53:27 PM PDT 24
Peak memory 215668 kb
Host smart-6c978c7f-074f-4888-aaca-3e8afebce460
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799742669 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2799742669
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.424189680
Short name T74
Test name
Test status
Simulation time 16431663798 ps
CPU time 385.78 seconds
Started May 05 01:53:24 PM PDT 24
Finished May 05 01:59:50 PM PDT 24
Peak memory 224024 kb
Host smart-17f47bcb-1171-43bb-a465-7b786fdb6399
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424189680 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.424189680
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2862710182
Short name T696
Test name
Test status
Simulation time 37518477 ps
CPU time 0.9 seconds
Started May 05 01:54:45 PM PDT 24
Finished May 05 01:54:47 PM PDT 24
Peak memory 217480 kb
Host smart-38a6083f-4798-4085-9b02-5d02f9fdf127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862710182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2862710182
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2121619
Short name T314
Test name
Test status
Simulation time 46379373 ps
CPU time 1.53 seconds
Started May 05 01:54:41 PM PDT 24
Finished May 05 01:54:43 PM PDT 24
Peak memory 218336 kb
Host smart-7f55a8fb-0b1a-4d03-98a0-7f74b97a4578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2121619
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3290010931
Short name T763
Test name
Test status
Simulation time 311075273 ps
CPU time 3.73 seconds
Started May 05 01:54:43 PM PDT 24
Finished May 05 01:54:47 PM PDT 24
Peak memory 219408 kb
Host smart-0ca9a6d9-05bc-4392-b0be-bccf8294b935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290010931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3290010931
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.4249685589
Short name T105
Test name
Test status
Simulation time 86411615 ps
CPU time 2.89 seconds
Started May 05 01:54:43 PM PDT 24
Finished May 05 01:54:46 PM PDT 24
Peak memory 220112 kb
Host smart-2dd2bebd-31fd-433f-92c1-015b42d562aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249685589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.4249685589
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2803039279
Short name T425
Test name
Test status
Simulation time 83729810 ps
CPU time 1.12 seconds
Started May 05 01:54:43 PM PDT 24
Finished May 05 01:54:44 PM PDT 24
Peak memory 217460 kb
Host smart-b8cf6d3c-7f1b-40ea-b522-040fd84b2894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803039279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2803039279
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.883777016
Short name T460
Test name
Test status
Simulation time 59643316 ps
CPU time 1.06 seconds
Started May 05 01:54:47 PM PDT 24
Finished May 05 01:54:49 PM PDT 24
Peak memory 217284 kb
Host smart-aa475e09-3389-4d85-b2a4-fb0dab06a347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883777016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.883777016
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.156211892
Short name T274
Test name
Test status
Simulation time 72204341 ps
CPU time 1.73 seconds
Started May 05 01:54:43 PM PDT 24
Finished May 05 01:54:45 PM PDT 24
Peak memory 217496 kb
Host smart-b14111fd-fc6f-46bf-a35f-06deda4d4647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156211892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.156211892
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2717833391
Short name T249
Test name
Test status
Simulation time 88700905 ps
CPU time 1.2 seconds
Started May 05 01:54:47 PM PDT 24
Finished May 05 01:54:49 PM PDT 24
Peak memory 220104 kb
Host smart-843a2866-26b1-4383-a749-ac6723de3d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717833391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2717833391
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1237180650
Short name T727
Test name
Test status
Simulation time 38887228 ps
CPU time 1.14 seconds
Started May 05 01:54:42 PM PDT 24
Finished May 05 01:54:44 PM PDT 24
Peak memory 219872 kb
Host smart-12482ade-6649-4a96-8232-e5c5fd19b397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237180650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1237180650
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1801568068
Short name T72
Test name
Test status
Simulation time 9564632295 ps
CPU time 95.73 seconds
Started May 05 01:54:44 PM PDT 24
Finished May 05 01:56:20 PM PDT 24
Peak memory 220460 kb
Host smart-ee93718e-7020-4c86-915c-1bb15508a5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801568068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1801568068
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2463693916
Short name T438
Test name
Test status
Simulation time 82867472 ps
CPU time 1.24 seconds
Started May 05 01:53:22 PM PDT 24
Finished May 05 01:53:24 PM PDT 24
Peak memory 216052 kb
Host smart-cca280f4-499c-4aef-b775-73122b3012e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463693916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2463693916
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.126942647
Short name T313
Test name
Test status
Simulation time 182229770 ps
CPU time 0.94 seconds
Started May 05 01:53:27 PM PDT 24
Finished May 05 01:53:28 PM PDT 24
Peak memory 215540 kb
Host smart-adbb5cfd-cf8b-4ea0-9d88-4eddf32e9ad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126942647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.126942647
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3308484763
Short name T590
Test name
Test status
Simulation time 42714902 ps
CPU time 0.85 seconds
Started May 05 01:53:26 PM PDT 24
Finished May 05 01:53:28 PM PDT 24
Peak memory 215776 kb
Host smart-ea3a594e-6b15-4a49-9373-82e269ecf366
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308484763 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3308484763
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2175629836
Short name T86
Test name
Test status
Simulation time 32020212 ps
CPU time 1.24 seconds
Started May 05 01:53:28 PM PDT 24
Finished May 05 01:53:30 PM PDT 24
Peak memory 217076 kb
Host smart-91f9132c-ecce-45cd-b7b1-192b93346ec8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175629836 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2175629836
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.638037940
Short name T127
Test name
Test status
Simulation time 21418100 ps
CPU time 1.09 seconds
Started May 05 01:53:27 PM PDT 24
Finished May 05 01:53:29 PM PDT 24
Peak memory 219924 kb
Host smart-d272dc66-651d-47c1-97e7-b9996955e307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638037940 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.638037940
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3915410494
Short name T664
Test name
Test status
Simulation time 54100333 ps
CPU time 0.95 seconds
Started May 05 01:53:21 PM PDT 24
Finished May 05 01:53:23 PM PDT 24
Peak memory 217316 kb
Host smart-dee7af04-872e-4074-8ffe-124041f524eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915410494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3915410494
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1093814314
Short name T822
Test name
Test status
Simulation time 31665025 ps
CPU time 0.83 seconds
Started May 05 01:53:26 PM PDT 24
Finished May 05 01:53:27 PM PDT 24
Peak memory 215760 kb
Host smart-401d2874-d6db-4b50-934d-eb4b69b0a610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093814314 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1093814314
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3222381352
Short name T346
Test name
Test status
Simulation time 130543164 ps
CPU time 1.01 seconds
Started May 05 01:53:24 PM PDT 24
Finished May 05 01:53:25 PM PDT 24
Peak memory 215620 kb
Host smart-9a76a9c2-90ed-46e1-a14f-e1a9167cf5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222381352 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3222381352
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1425431616
Short name T459
Test name
Test status
Simulation time 80910563 ps
CPU time 2.06 seconds
Started May 05 01:53:21 PM PDT 24
Finished May 05 01:53:23 PM PDT 24
Peak memory 215636 kb
Host smart-e6088404-48a7-4a0f-8aa4-038e4b28d599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425431616 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1425431616
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2964146464
Short name T68
Test name
Test status
Simulation time 49946304481 ps
CPU time 639.75 seconds
Started May 05 01:53:24 PM PDT 24
Finished May 05 02:04:04 PM PDT 24
Peak memory 218684 kb
Host smart-6c6aed6f-c481-4b87-af30-c49ea62a1353
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964146464 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2964146464
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1743242847
Short name T834
Test name
Test status
Simulation time 54326823 ps
CPU time 2.29 seconds
Started May 05 01:54:46 PM PDT 24
Finished May 05 01:54:48 PM PDT 24
Peak memory 217784 kb
Host smart-47759155-a3e4-42e8-8ed1-43afbc539b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743242847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1743242847
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1517671858
Short name T435
Test name
Test status
Simulation time 37452129 ps
CPU time 1.31 seconds
Started May 05 01:54:47 PM PDT 24
Finished May 05 01:54:49 PM PDT 24
Peak memory 218564 kb
Host smart-c936b176-5d5c-462b-9974-d99c40524fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517671858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1517671858
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.219574059
Short name T724
Test name
Test status
Simulation time 130058291 ps
CPU time 1.7 seconds
Started May 05 01:54:48 PM PDT 24
Finished May 05 01:54:50 PM PDT 24
Peak memory 219936 kb
Host smart-b66ccfcc-baad-4a0f-a9c0-72a2ddc0b059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219574059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.219574059
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1022546949
Short name T612
Test name
Test status
Simulation time 88454923 ps
CPU time 1.47 seconds
Started May 05 01:54:43 PM PDT 24
Finished May 05 01:54:45 PM PDT 24
Peak memory 218852 kb
Host smart-cdff7736-1a7e-413b-aca0-2e8d9698805a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022546949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1022546949
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1577172781
Short name T399
Test name
Test status
Simulation time 164129540 ps
CPU time 1.64 seconds
Started May 05 01:54:43 PM PDT 24
Finished May 05 01:54:45 PM PDT 24
Peak memory 219156 kb
Host smart-a0239047-f3e3-4f9e-8034-7d3264ec2a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577172781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1577172781
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3952613076
Short name T555
Test name
Test status
Simulation time 58883747 ps
CPU time 1.27 seconds
Started May 05 01:54:45 PM PDT 24
Finished May 05 01:54:47 PM PDT 24
Peak memory 218940 kb
Host smart-4c332c84-8f08-4393-baab-0ac9b09f79c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952613076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3952613076
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2084796814
Short name T503
Test name
Test status
Simulation time 45262633 ps
CPU time 1.28 seconds
Started May 05 01:54:45 PM PDT 24
Finished May 05 01:54:47 PM PDT 24
Peak memory 218956 kb
Host smart-517bce46-de31-475c-a967-07af303fe558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084796814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2084796814
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1378312388
Short name T277
Test name
Test status
Simulation time 40916068 ps
CPU time 1.72 seconds
Started May 05 01:54:48 PM PDT 24
Finished May 05 01:54:50 PM PDT 24
Peak memory 218556 kb
Host smart-4116108a-f29a-4ec0-aa17-cd0db027ae93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378312388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1378312388
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2896964115
Short name T541
Test name
Test status
Simulation time 45622650 ps
CPU time 1.52 seconds
Started May 05 01:54:46 PM PDT 24
Finished May 05 01:54:48 PM PDT 24
Peak memory 215792 kb
Host smart-15c747c1-7c47-43dc-9994-b33f04773167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896964115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2896964115
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.4239310137
Short name T337
Test name
Test status
Simulation time 33643927 ps
CPU time 1.43 seconds
Started May 05 01:54:45 PM PDT 24
Finished May 05 01:54:47 PM PDT 24
Peak memory 219920 kb
Host smart-b8df3498-059f-4b8c-bf21-aa186832008c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239310137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.4239310137
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.99313618
Short name T167
Test name
Test status
Simulation time 23278866 ps
CPU time 1.24 seconds
Started May 05 01:53:27 PM PDT 24
Finished May 05 01:53:29 PM PDT 24
Peak memory 216020 kb
Host smart-e9008932-614c-4bbf-86da-140475fc3b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99313618 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.99313618
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3335303570
Short name T345
Test name
Test status
Simulation time 20803477 ps
CPU time 0.89 seconds
Started May 05 01:53:27 PM PDT 24
Finished May 05 01:53:29 PM PDT 24
Peak memory 215080 kb
Host smart-53df3e23-058b-4266-932b-190192cfaea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335303570 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3335303570
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3962570131
Short name T152
Test name
Test status
Simulation time 42447208 ps
CPU time 0.89 seconds
Started May 05 01:53:27 PM PDT 24
Finished May 05 01:53:28 PM PDT 24
Peak memory 216780 kb
Host smart-a9387b77-3a03-4f85-ac03-cbaa0e68ca81
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962570131 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3962570131
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3535667948
Short name T322
Test name
Test status
Simulation time 41077552 ps
CPU time 1.24 seconds
Started May 05 01:53:33 PM PDT 24
Finished May 05 01:53:35 PM PDT 24
Peak memory 218532 kb
Host smart-3c05ec38-a9d3-46b2-9457-3c4e05df9b49
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535667948 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3535667948
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.2480744668
Short name T135
Test name
Test status
Simulation time 85514211 ps
CPU time 0.82 seconds
Started May 05 01:53:28 PM PDT 24
Finished May 05 01:53:29 PM PDT 24
Peak memory 218552 kb
Host smart-a79c1a9c-b699-4e03-8c54-2f7905ac4f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480744668 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2480744668
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.793001651
Short name T771
Test name
Test status
Simulation time 256633568 ps
CPU time 3.39 seconds
Started May 05 01:53:34 PM PDT 24
Finished May 05 01:53:38 PM PDT 24
Peak memory 218668 kb
Host smart-a92dfd14-9032-42ab-b898-8f5c55e084da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793001651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.793001651
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1102884208
Short name T35
Test name
Test status
Simulation time 22699588 ps
CPU time 0.92 seconds
Started May 05 01:53:29 PM PDT 24
Finished May 05 01:53:30 PM PDT 24
Peak memory 216196 kb
Host smart-7818e7d8-1303-453b-b56b-ae836bfb1046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102884208 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1102884208
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3811623013
Short name T637
Test name
Test status
Simulation time 19134778 ps
CPU time 1 seconds
Started May 05 01:53:27 PM PDT 24
Finished May 05 01:53:29 PM PDT 24
Peak memory 215636 kb
Host smart-b796d6c2-173c-4f91-b2ed-f7887639b09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811623013 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3811623013
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.144826294
Short name T833
Test name
Test status
Simulation time 339286126 ps
CPU time 4.1 seconds
Started May 05 01:53:27 PM PDT 24
Finished May 05 01:53:32 PM PDT 24
Peak memory 215628 kb
Host smart-933080f7-510b-43b9-9058-405248671169
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144826294 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.144826294
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.4048077732
Short name T657
Test name
Test status
Simulation time 172619428164 ps
CPU time 1169.08 seconds
Started May 05 01:53:26 PM PDT 24
Finished May 05 02:12:56 PM PDT 24
Peak memory 224740 kb
Host smart-e0760c5f-e46b-42cc-afd0-d87d745b77ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048077732 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.4048077732
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.4113324239
Short name T87
Test name
Test status
Simulation time 72333384 ps
CPU time 1.19 seconds
Started May 05 01:54:46 PM PDT 24
Finished May 05 01:54:47 PM PDT 24
Peak memory 217420 kb
Host smart-0d967130-4ed2-462d-a13c-60d74b4496e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113324239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.4113324239
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1363190645
Short name T456
Test name
Test status
Simulation time 315082166 ps
CPU time 1.11 seconds
Started May 05 01:54:46 PM PDT 24
Finished May 05 01:54:48 PM PDT 24
Peak memory 217404 kb
Host smart-8564fa71-44e8-4bd3-a3a0-bc9f474c4b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363190645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1363190645
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2607306450
Short name T571
Test name
Test status
Simulation time 46225975 ps
CPU time 1.2 seconds
Started May 05 01:54:42 PM PDT 24
Finished May 05 01:54:44 PM PDT 24
Peak memory 218924 kb
Host smart-b550c9df-6cda-4555-a8ca-9ac995954445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607306450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2607306450
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3092806154
Short name T744
Test name
Test status
Simulation time 147005111 ps
CPU time 3.28 seconds
Started May 05 01:54:44 PM PDT 24
Finished May 05 01:54:48 PM PDT 24
Peak memory 219140 kb
Host smart-9c64a43b-ac28-461f-8224-be6d7a546023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092806154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3092806154
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.378202518
Short name T591
Test name
Test status
Simulation time 49217301 ps
CPU time 1.31 seconds
Started May 05 01:54:50 PM PDT 24
Finished May 05 01:54:51 PM PDT 24
Peak memory 217304 kb
Host smart-cb1d3909-e0a8-433b-b465-973b84fe0c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378202518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.378202518
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3252679062
Short name T732
Test name
Test status
Simulation time 145779889 ps
CPU time 1.56 seconds
Started May 05 01:54:51 PM PDT 24
Finished May 05 01:54:53 PM PDT 24
Peak memory 219996 kb
Host smart-bef47a41-e482-4012-9a98-ee4e3c526577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252679062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3252679062
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3491889943
Short name T487
Test name
Test status
Simulation time 75343297 ps
CPU time 1.5 seconds
Started May 05 01:54:48 PM PDT 24
Finished May 05 01:54:50 PM PDT 24
Peak memory 218620 kb
Host smart-c340ae90-757b-4dec-94f0-db378f9d7965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491889943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3491889943
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.57540508
Short name T512
Test name
Test status
Simulation time 43168165 ps
CPU time 1.47 seconds
Started May 05 01:54:50 PM PDT 24
Finished May 05 01:54:52 PM PDT 24
Peak memory 219876 kb
Host smart-8c8ad48c-960b-45f7-9d24-605dabcd78f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57540508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.57540508
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3308159260
Short name T263
Test name
Test status
Simulation time 39996892 ps
CPU time 1.47 seconds
Started May 05 01:54:51 PM PDT 24
Finished May 05 01:54:53 PM PDT 24
Peak memory 217356 kb
Host smart-4fe6d722-6882-4f20-9d7d-e3da5e66a853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308159260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3308159260
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2553535916
Short name T553
Test name
Test status
Simulation time 59036777 ps
CPU time 0.95 seconds
Started May 05 01:54:46 PM PDT 24
Finished May 05 01:54:48 PM PDT 24
Peak memory 217164 kb
Host smart-e4817a6c-fa93-44ce-85fc-ca1a25b9d10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553535916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2553535916
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2404673526
Short name T190
Test name
Test status
Simulation time 53865084 ps
CPU time 1.17 seconds
Started May 05 01:53:27 PM PDT 24
Finished May 05 01:53:28 PM PDT 24
Peak memory 216072 kb
Host smart-8615b19f-32e6-4df1-a7de-1793766cbb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404673526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2404673526
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2553931253
Short name T60
Test name
Test status
Simulation time 78998042 ps
CPU time 1.02 seconds
Started May 05 01:53:34 PM PDT 24
Finished May 05 01:53:35 PM PDT 24
Peak memory 207100 kb
Host smart-542a00a9-7114-4ea7-abae-c01155a97d94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553931253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2553931253
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.844114695
Short name T3
Test name
Test status
Simulation time 53908120 ps
CPU time 1.03 seconds
Started May 05 01:53:26 PM PDT 24
Finished May 05 01:53:28 PM PDT 24
Peak memory 217220 kb
Host smart-568eff51-5a95-41fd-b2ae-b46146a6478b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844114695 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.844114695
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2237542696
Short name T130
Test name
Test status
Simulation time 19285487 ps
CPU time 1.08 seconds
Started May 05 01:53:27 PM PDT 24
Finished May 05 01:53:28 PM PDT 24
Peak memory 218936 kb
Host smart-f3cd1b18-9ee6-4b4e-a7ee-e8d165ec6423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237542696 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2237542696
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1523080888
Short name T682
Test name
Test status
Simulation time 32225217 ps
CPU time 1.23 seconds
Started May 05 01:53:32 PM PDT 24
Finished May 05 01:53:33 PM PDT 24
Peak memory 218316 kb
Host smart-5d17b99e-e47a-40d7-8ec8-5d9cc64bf4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523080888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1523080888
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.1742716519
Short name T317
Test name
Test status
Simulation time 72836718 ps
CPU time 0.81 seconds
Started May 05 01:53:32 PM PDT 24
Finished May 05 01:53:33 PM PDT 24
Peak memory 215596 kb
Host smart-e0514680-e70f-425b-92e3-4f40064fbc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742716519 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1742716519
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2163556065
Short name T343
Test name
Test status
Simulation time 59239477 ps
CPU time 0.91 seconds
Started May 05 01:53:28 PM PDT 24
Finished May 05 01:53:29 PM PDT 24
Peak memory 215568 kb
Host smart-8951ce26-8ca3-4616-8061-7b2022666482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163556065 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2163556065
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.4163707331
Short name T666
Test name
Test status
Simulation time 111267665 ps
CPU time 2.65 seconds
Started May 05 01:53:28 PM PDT 24
Finished May 05 01:53:31 PM PDT 24
Peak memory 218448 kb
Host smart-1fcb87d6-174f-4c8c-88fd-6796af603e7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163707331 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.4163707331
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1459143080
Short name T739
Test name
Test status
Simulation time 462616657294 ps
CPU time 2009.28 seconds
Started May 05 01:53:29 PM PDT 24
Finished May 05 02:26:59 PM PDT 24
Peak memory 229416 kb
Host smart-71c11b88-829a-4c1e-98a9-9bc7ee484b55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459143080 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1459143080
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/242.edn_genbits.2246717765
Short name T488
Test name
Test status
Simulation time 122193433 ps
CPU time 1.03 seconds
Started May 05 01:54:48 PM PDT 24
Finished May 05 01:54:50 PM PDT 24
Peak memory 217280 kb
Host smart-396dc458-7180-4e3d-aa57-3aa65af805f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246717765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2246717765
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2842256382
Short name T401
Test name
Test status
Simulation time 125261467 ps
CPU time 0.93 seconds
Started May 05 01:54:45 PM PDT 24
Finished May 05 01:54:47 PM PDT 24
Peak memory 217496 kb
Host smart-bec4acdf-4477-427a-aefb-8a07ff447679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842256382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2842256382
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2516521103
Short name T589
Test name
Test status
Simulation time 279572802 ps
CPU time 1.81 seconds
Started May 05 01:54:48 PM PDT 24
Finished May 05 01:54:51 PM PDT 24
Peak memory 218952 kb
Host smart-8c39bf80-c290-4674-afe8-18dc45823556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516521103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2516521103
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.503216512
Short name T547
Test name
Test status
Simulation time 37787076 ps
CPU time 1.39 seconds
Started May 05 01:54:49 PM PDT 24
Finished May 05 01:54:51 PM PDT 24
Peak memory 217308 kb
Host smart-b05a0499-4355-436a-b248-e030a3922baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503216512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.503216512
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.831836777
Short name T251
Test name
Test status
Simulation time 38809730 ps
CPU time 1.1 seconds
Started May 05 01:54:47 PM PDT 24
Finished May 05 01:54:49 PM PDT 24
Peak memory 217364 kb
Host smart-3917e7f5-cb28-46a5-9b02-1b26ba5be31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831836777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.831836777
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2219801908
Short name T397
Test name
Test status
Simulation time 38532824 ps
CPU time 1.48 seconds
Started May 05 01:54:52 PM PDT 24
Finished May 05 01:54:54 PM PDT 24
Peak memory 218704 kb
Host smart-1798c27e-cef8-4dc6-82ce-2c714bdbe29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219801908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2219801908
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3875874078
Short name T265
Test name
Test status
Simulation time 66661974 ps
CPU time 1.39 seconds
Started May 05 01:54:48 PM PDT 24
Finished May 05 01:54:50 PM PDT 24
Peak memory 217356 kb
Host smart-97fdb647-9c3d-473b-a582-796ced4bf79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875874078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3875874078
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2668320679
Short name T539
Test name
Test status
Simulation time 30550091 ps
CPU time 1.21 seconds
Started May 05 01:54:47 PM PDT 24
Finished May 05 01:54:49 PM PDT 24
Peak memory 217200 kb
Host smart-e1359214-30c7-4a58-abc7-c24ec6dfab7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668320679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2668320679
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3015493772
Short name T722
Test name
Test status
Simulation time 56164450 ps
CPU time 1.38 seconds
Started May 05 01:53:28 PM PDT 24
Finished May 05 01:53:30 PM PDT 24
Peak memory 216020 kb
Host smart-252db302-f6b1-41cc-bc20-22728846d679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015493772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3015493772
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1222241899
Short name T587
Test name
Test status
Simulation time 53736943 ps
CPU time 0.9 seconds
Started May 05 01:53:30 PM PDT 24
Finished May 05 01:53:32 PM PDT 24
Peak memory 206776 kb
Host smart-d6b53b87-5574-414a-b954-07eebe4d95ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222241899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1222241899
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2726203270
Short name T192
Test name
Test status
Simulation time 107944426 ps
CPU time 0.88 seconds
Started May 05 01:53:34 PM PDT 24
Finished May 05 01:53:35 PM PDT 24
Peak memory 215760 kb
Host smart-ff595ce2-cad0-4090-a6a9-1029eaf4254d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726203270 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2726203270
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.20237390
Short name T391
Test name
Test status
Simulation time 34666524 ps
CPU time 1.3 seconds
Started May 05 01:53:30 PM PDT 24
Finished May 05 01:53:32 PM PDT 24
Peak memory 217232 kb
Host smart-1cda131a-66be-41c4-9679-3e8c01386b4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20237390 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_dis
able_auto_req_mode.20237390
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2586944407
Short name T508
Test name
Test status
Simulation time 21529072 ps
CPU time 1.03 seconds
Started May 05 01:53:26 PM PDT 24
Finished May 05 01:53:27 PM PDT 24
Peak memory 224380 kb
Host smart-ef8cb5bc-9f31-42c9-ab03-2bf14c476406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586944407 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2586944407
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3601499040
Short name T567
Test name
Test status
Simulation time 91906534 ps
CPU time 1.33 seconds
Started May 05 01:53:28 PM PDT 24
Finished May 05 01:53:30 PM PDT 24
Peak memory 217272 kb
Host smart-d222ddc9-f19d-4a14-9711-b6e1e96cb40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601499040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3601499040
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.294741753
Short name T36
Test name
Test status
Simulation time 27099808 ps
CPU time 0.89 seconds
Started May 05 01:53:33 PM PDT 24
Finished May 05 01:53:35 PM PDT 24
Peak memory 216112 kb
Host smart-15402a8d-ec04-4006-b982-5335f568aa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294741753 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.294741753
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1303157897
Short name T453
Test name
Test status
Simulation time 15064643 ps
CPU time 1.01 seconds
Started May 05 01:53:28 PM PDT 24
Finished May 05 01:53:30 PM PDT 24
Peak memory 215336 kb
Host smart-e098a46a-9e71-43c8-a5ca-9755ea5d216b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303157897 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1303157897
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1935556583
Short name T639
Test name
Test status
Simulation time 478284509 ps
CPU time 5.81 seconds
Started May 05 01:53:28 PM PDT 24
Finished May 05 01:53:35 PM PDT 24
Peak memory 217140 kb
Host smart-b87d4233-ac90-4b8a-b1de-6a8e7ba83980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935556583 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1935556583
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2507376274
Short name T702
Test name
Test status
Simulation time 199540689159 ps
CPU time 660.47 seconds
Started May 05 01:53:27 PM PDT 24
Finished May 05 02:04:28 PM PDT 24
Peak memory 221084 kb
Host smart-bf7994f6-cb48-40b6-b653-eddd0de0ed5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507376274 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2507376274
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2459383067
Short name T271
Test name
Test status
Simulation time 69950725 ps
CPU time 1.05 seconds
Started May 05 01:54:52 PM PDT 24
Finished May 05 01:54:54 PM PDT 24
Peak memory 217496 kb
Host smart-ce03f82c-3f75-49c9-824c-3d60990766f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459383067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2459383067
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.4229662435
Short name T97
Test name
Test status
Simulation time 165062211 ps
CPU time 1.4 seconds
Started May 05 01:54:49 PM PDT 24
Finished May 05 01:54:51 PM PDT 24
Peak memory 217556 kb
Host smart-2f3c3c82-59a1-4cd7-8411-3987a3c614f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229662435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.4229662435
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1950553818
Short name T26
Test name
Test status
Simulation time 47193479 ps
CPU time 1.61 seconds
Started May 05 01:54:49 PM PDT 24
Finished May 05 01:54:52 PM PDT 24
Peak memory 218424 kb
Host smart-9882bee5-d3b7-4ec3-b833-2c7654977460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950553818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1950553818
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.688325444
Short name T659
Test name
Test status
Simulation time 49088963 ps
CPU time 1.42 seconds
Started May 05 01:54:49 PM PDT 24
Finished May 05 01:54:51 PM PDT 24
Peak memory 218552 kb
Host smart-413529c6-4a2c-477b-9957-5a3fc1f623a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688325444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.688325444
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3898410835
Short name T820
Test name
Test status
Simulation time 55766091 ps
CPU time 1.08 seconds
Started May 05 01:54:48 PM PDT 24
Finished May 05 01:54:50 PM PDT 24
Peak memory 217384 kb
Host smart-bfc300d7-6e0c-492a-83ff-639847d8c9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898410835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3898410835
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1172145342
Short name T407
Test name
Test status
Simulation time 32647447 ps
CPU time 1.33 seconds
Started May 05 01:54:50 PM PDT 24
Finished May 05 01:54:52 PM PDT 24
Peak memory 219748 kb
Host smart-1172ea60-5bd5-4cab-9a40-dcb31a1dfd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172145342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1172145342
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1030744677
Short name T367
Test name
Test status
Simulation time 119298888 ps
CPU time 1.82 seconds
Started May 05 01:54:50 PM PDT 24
Finished May 05 01:54:52 PM PDT 24
Peak memory 219020 kb
Host smart-c5ccf02f-64d3-4596-a2a3-0cc7e9d9937e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030744677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1030744677
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1335706761
Short name T99
Test name
Test status
Simulation time 40858085 ps
CPU time 1.77 seconds
Started May 05 01:54:53 PM PDT 24
Finished May 05 01:54:56 PM PDT 24
Peak memory 220292 kb
Host smart-5511b0ba-73a0-45cd-9b42-08a369171f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335706761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1335706761
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2891967362
Short name T465
Test name
Test status
Simulation time 85047971 ps
CPU time 1.48 seconds
Started May 05 01:54:51 PM PDT 24
Finished May 05 01:54:53 PM PDT 24
Peak memory 218776 kb
Host smart-e5fa2602-0a6d-445d-9de9-11b0cc980a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891967362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2891967362
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.98595937
Short name T817
Test name
Test status
Simulation time 89759564 ps
CPU time 1.36 seconds
Started May 05 01:54:49 PM PDT 24
Finished May 05 01:54:51 PM PDT 24
Peak memory 217600 kb
Host smart-368d7f8b-2b79-4228-8b31-ba44476db98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98595937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.98595937
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2526732178
Short name T142
Test name
Test status
Simulation time 38020680 ps
CPU time 1.09 seconds
Started May 05 01:53:31 PM PDT 24
Finished May 05 01:53:33 PM PDT 24
Peak memory 216056 kb
Host smart-2ce3be35-c011-47c0-8994-6c25078a08c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526732178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2526732178
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3748572297
Short name T423
Test name
Test status
Simulation time 12780896 ps
CPU time 0.86 seconds
Started May 05 01:53:33 PM PDT 24
Finished May 05 01:53:34 PM PDT 24
Peak memory 206972 kb
Host smart-6033362c-4d25-4b20-8dec-c094f03fbb42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748572297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3748572297
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3079445672
Short name T728
Test name
Test status
Simulation time 67971840 ps
CPU time 0.88 seconds
Started May 05 01:53:33 PM PDT 24
Finished May 05 01:53:34 PM PDT 24
Peak memory 216592 kb
Host smart-5bcb5625-e645-467c-a875-6a7f7da253f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079445672 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3079445672
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.3278347355
Short name T429
Test name
Test status
Simulation time 25267065 ps
CPU time 0.98 seconds
Started May 05 01:53:32 PM PDT 24
Finished May 05 01:53:33 PM PDT 24
Peak memory 220240 kb
Host smart-89156941-27a6-4b2c-b4eb-47286cb995a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278347355 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3278347355
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.963777268
Short name T511
Test name
Test status
Simulation time 253569209 ps
CPU time 1.32 seconds
Started May 05 01:53:31 PM PDT 24
Finished May 05 01:53:32 PM PDT 24
Peak memory 217680 kb
Host smart-73ac1d58-acd4-4b6e-944c-2e1133b1663c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963777268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.963777268
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2547615404
Short name T819
Test name
Test status
Simulation time 24028707 ps
CPU time 0.85 seconds
Started May 05 01:53:30 PM PDT 24
Finished May 05 01:53:31 PM PDT 24
Peak memory 216228 kb
Host smart-2a93a9e2-2d88-44e8-a31b-c84d471452b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547615404 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2547615404
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.979786606
Short name T207
Test name
Test status
Simulation time 44990408 ps
CPU time 0.89 seconds
Started May 05 01:53:33 PM PDT 24
Finished May 05 01:53:35 PM PDT 24
Peak memory 207388 kb
Host smart-f16451b9-8876-4901-bbf4-3fdb860d419b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979786606 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.979786606
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3725997800
Short name T209
Test name
Test status
Simulation time 2996238686 ps
CPU time 4.41 seconds
Started May 05 01:53:31 PM PDT 24
Finished May 05 01:53:36 PM PDT 24
Peak memory 215724 kb
Host smart-22081160-5586-4fce-8605-fd4112d105bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725997800 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3725997800
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2007791853
Short name T781
Test name
Test status
Simulation time 733011121196 ps
CPU time 1475.2 seconds
Started May 05 01:53:30 PM PDT 24
Finished May 05 02:18:06 PM PDT 24
Peak memory 224636 kb
Host smart-db0dfa86-e050-48f7-9792-204c07470a54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007791853 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2007791853
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.721584151
Short name T88
Test name
Test status
Simulation time 73464257 ps
CPU time 1.1 seconds
Started May 05 01:54:52 PM PDT 24
Finished May 05 01:54:54 PM PDT 24
Peak memory 217372 kb
Host smart-c48bae8c-a1d8-40db-a2ee-f266b1ed99e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721584151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.721584151
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1258035258
Short name T214
Test name
Test status
Simulation time 76633022 ps
CPU time 1.34 seconds
Started May 05 01:54:50 PM PDT 24
Finished May 05 01:54:52 PM PDT 24
Peak memory 218392 kb
Host smart-fe6de6c5-d427-4496-a874-34d018f740a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258035258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1258035258
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2224938586
Short name T447
Test name
Test status
Simulation time 87491031 ps
CPU time 1.19 seconds
Started May 05 01:54:51 PM PDT 24
Finished May 05 01:54:52 PM PDT 24
Peak memory 217496 kb
Host smart-0c07b909-67eb-4993-8621-04bd04a6dadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224938586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2224938586
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1421229418
Short name T305
Test name
Test status
Simulation time 98695669 ps
CPU time 1.17 seconds
Started May 05 01:54:53 PM PDT 24
Finished May 05 01:54:55 PM PDT 24
Peak memory 217408 kb
Host smart-6d77c62d-3300-4333-89fb-ccc425311fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421229418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1421229418
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2663441014
Short name T358
Test name
Test status
Simulation time 37414791 ps
CPU time 1.1 seconds
Started May 05 01:54:52 PM PDT 24
Finished May 05 01:54:54 PM PDT 24
Peak memory 217396 kb
Host smart-8a525bca-d1b1-4082-b21d-ae53488c9087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663441014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2663441014
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2590454426
Short name T338
Test name
Test status
Simulation time 43171997 ps
CPU time 1.54 seconds
Started May 05 01:54:59 PM PDT 24
Finished May 05 01:55:01 PM PDT 24
Peak memory 218564 kb
Host smart-b19fd8cc-3283-41cf-b57f-30f13770b01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590454426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2590454426
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.4157912583
Short name T272
Test name
Test status
Simulation time 141146009 ps
CPU time 3.12 seconds
Started May 05 01:54:55 PM PDT 24
Finished May 05 01:54:58 PM PDT 24
Peak memory 219460 kb
Host smart-3aceae70-6dc8-40d7-b2eb-9b4de04f9dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157912583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.4157912583
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1711017085
Short name T390
Test name
Test status
Simulation time 56789011 ps
CPU time 1.98 seconds
Started May 05 01:54:53 PM PDT 24
Finished May 05 01:54:55 PM PDT 24
Peak memory 218528 kb
Host smart-c80cd7b4-0815-48f8-8614-b5bb638b0211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711017085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1711017085
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1415121986
Short name T826
Test name
Test status
Simulation time 27972903 ps
CPU time 1.19 seconds
Started May 05 01:54:52 PM PDT 24
Finished May 05 01:54:54 PM PDT 24
Peak memory 215728 kb
Host smart-49ba8052-805d-4521-bcc9-7acc35f215ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415121986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1415121986
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2168110902
Short name T816
Test name
Test status
Simulation time 85168804 ps
CPU time 1.8 seconds
Started May 05 01:54:55 PM PDT 24
Finished May 05 01:54:57 PM PDT 24
Peak memory 220256 kb
Host smart-53b464dc-9d96-443d-95f8-728b5c3c37bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168110902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2168110902
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1359364774
Short name T418
Test name
Test status
Simulation time 28667965 ps
CPU time 1.23 seconds
Started May 05 01:53:39 PM PDT 24
Finished May 05 01:53:40 PM PDT 24
Peak memory 216048 kb
Host smart-671c4aee-99ab-4053-8410-e5f00c4b4b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359364774 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1359364774
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2923026251
Short name T623
Test name
Test status
Simulation time 73856330 ps
CPU time 0.91 seconds
Started May 05 01:53:40 PM PDT 24
Finished May 05 01:53:42 PM PDT 24
Peak memory 215196 kb
Host smart-9681d995-d413-4cb5-911b-1bd737271cba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923026251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2923026251
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1067475536
Short name T794
Test name
Test status
Simulation time 22406573 ps
CPU time 0.94 seconds
Started May 05 01:53:38 PM PDT 24
Finished May 05 01:53:39 PM PDT 24
Peak memory 216576 kb
Host smart-f72dc730-1f98-4413-ba1d-a53d39641f29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067475536 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1067475536
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.2211716337
Short name T504
Test name
Test status
Simulation time 28715060 ps
CPU time 1.33 seconds
Started May 05 01:53:35 PM PDT 24
Finished May 05 01:53:37 PM PDT 24
Peak memory 220132 kb
Host smart-85919c87-bb3b-4612-8fd4-936d4ba7023c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211716337 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2211716337
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2649176623
Short name T269
Test name
Test status
Simulation time 141861940 ps
CPU time 2.19 seconds
Started May 05 01:53:30 PM PDT 24
Finished May 05 01:53:33 PM PDT 24
Peak memory 217580 kb
Host smart-e233d9f2-0dcb-44b0-824b-3ca4edc95b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649176623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2649176623
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1327445252
Short name T538
Test name
Test status
Simulation time 25153224 ps
CPU time 0.93 seconds
Started May 05 01:53:37 PM PDT 24
Finished May 05 01:53:38 PM PDT 24
Peak memory 215968 kb
Host smart-2dc11a08-bab1-4856-aec3-dabbb75973bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327445252 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1327445252
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.501694525
Short name T750
Test name
Test status
Simulation time 46923473 ps
CPU time 0.87 seconds
Started May 05 01:53:33 PM PDT 24
Finished May 05 01:53:34 PM PDT 24
Peak memory 215544 kb
Host smart-245006f5-7659-4553-8bfc-fd4ec939d642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501694525 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.501694525
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3817764088
Short name T846
Test name
Test status
Simulation time 1814841978 ps
CPU time 3.96 seconds
Started May 05 01:53:30 PM PDT 24
Finished May 05 01:53:34 PM PDT 24
Peak memory 216820 kb
Host smart-d8b0ed6f-c10b-4bd0-8f65-e056cb9c874a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817764088 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3817764088
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.400283246
Short name T636
Test name
Test status
Simulation time 113270016649 ps
CPU time 1413.93 seconds
Started May 05 01:53:35 PM PDT 24
Finished May 05 02:17:10 PM PDT 24
Peak memory 225940 kb
Host smart-773aa51c-ec4d-4af7-8bd0-c527cc943010
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400283246 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.400283246
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.4156543689
Short name T449
Test name
Test status
Simulation time 60432688 ps
CPU time 1.01 seconds
Started May 05 01:54:57 PM PDT 24
Finished May 05 01:54:58 PM PDT 24
Peak memory 217372 kb
Host smart-6d5e3eb2-7a44-4fea-bdf7-3be4e50ec1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156543689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.4156543689
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3418906730
Short name T362
Test name
Test status
Simulation time 34616448 ps
CPU time 1.42 seconds
Started May 05 01:54:51 PM PDT 24
Finished May 05 01:54:53 PM PDT 24
Peak memory 218548 kb
Host smart-794c5631-6c91-49b9-97f7-4115f5321d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418906730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3418906730
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1396998849
Short name T95
Test name
Test status
Simulation time 62575789 ps
CPU time 1.39 seconds
Started May 05 01:54:50 PM PDT 24
Finished May 05 01:54:52 PM PDT 24
Peak memory 220292 kb
Host smart-ab3fd243-a788-431c-95ab-9071fa6822da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396998849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1396998849
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3186108284
Short name T8
Test name
Test status
Simulation time 155996251 ps
CPU time 1.07 seconds
Started May 05 01:54:58 PM PDT 24
Finished May 05 01:55:00 PM PDT 24
Peak memory 219596 kb
Host smart-14294529-e9e1-47cd-b39c-ba049002fa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186108284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3186108284
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1882279853
Short name T306
Test name
Test status
Simulation time 96528278 ps
CPU time 1.18 seconds
Started May 05 01:54:51 PM PDT 24
Finished May 05 01:54:53 PM PDT 24
Peak memory 219836 kb
Host smart-203ed5d2-ff51-4b1f-ae73-a80c5436b6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882279853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1882279853
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3239336846
Short name T717
Test name
Test status
Simulation time 33301148 ps
CPU time 1.65 seconds
Started May 05 01:54:56 PM PDT 24
Finished May 05 01:54:58 PM PDT 24
Peak memory 218680 kb
Host smart-c201f9c1-5f17-4065-ab0f-ba5b6915982f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239336846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3239336846
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2886537677
Short name T505
Test name
Test status
Simulation time 79464100 ps
CPU time 1.17 seconds
Started May 05 01:54:54 PM PDT 24
Finished May 05 01:54:56 PM PDT 24
Peak memory 215636 kb
Host smart-9560c7d1-122a-4459-8aba-751801e107fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886537677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2886537677
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3832405533
Short name T736
Test name
Test status
Simulation time 31695249 ps
CPU time 1.32 seconds
Started May 05 01:54:56 PM PDT 24
Finished May 05 01:54:57 PM PDT 24
Peak memory 218548 kb
Host smart-85c1bc39-68ba-47a9-87fa-84dff33ad1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832405533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3832405533
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.4155375491
Short name T745
Test name
Test status
Simulation time 301334358 ps
CPU time 1.22 seconds
Started May 05 01:54:58 PM PDT 24
Finished May 05 01:54:59 PM PDT 24
Peak memory 217360 kb
Host smart-3d6c5334-55e3-4052-b06f-019ffd7ab10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155375491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.4155375491
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3936197617
Short name T492
Test name
Test status
Simulation time 37195127 ps
CPU time 1.3 seconds
Started May 05 01:55:01 PM PDT 24
Finished May 05 01:55:03 PM PDT 24
Peak memory 217276 kb
Host smart-26cd8a2a-0510-4300-8b0b-e1e7d9a09030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936197617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3936197617
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1820123835
Short name T92
Test name
Test status
Simulation time 110478896 ps
CPU time 1.2 seconds
Started May 05 01:53:36 PM PDT 24
Finished May 05 01:53:38 PM PDT 24
Peak memory 216060 kb
Host smart-7ee93702-a33b-44c4-b329-b2427e8fff0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820123835 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1820123835
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1022870565
Short name T80
Test name
Test status
Simulation time 19051912 ps
CPU time 0.85 seconds
Started May 05 01:53:40 PM PDT 24
Finished May 05 01:53:41 PM PDT 24
Peak memory 207244 kb
Host smart-a1523923-b3e0-4f7b-a361-144a4c124746
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022870565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1022870565
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1645600960
Short name T58
Test name
Test status
Simulation time 35859478 ps
CPU time 0.87 seconds
Started May 05 01:53:36 PM PDT 24
Finished May 05 01:53:38 PM PDT 24
Peak memory 216272 kb
Host smart-3978e489-fdbd-429e-9e58-9bd37b945f90
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645600960 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1645600960
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3037289822
Short name T791
Test name
Test status
Simulation time 93480151 ps
CPU time 1.37 seconds
Started May 05 01:53:38 PM PDT 24
Finished May 05 01:53:40 PM PDT 24
Peak memory 218300 kb
Host smart-8cb6621c-9646-48f9-bd1e-31e741e0df71
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037289822 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3037289822
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.3956867152
Short name T837
Test name
Test status
Simulation time 26119635 ps
CPU time 1.31 seconds
Started May 05 01:53:36 PM PDT 24
Finished May 05 01:53:38 PM PDT 24
Peak memory 224380 kb
Host smart-76b0d48b-0f2d-4db0-bd26-f4cc409d2f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956867152 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3956867152
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2822222001
Short name T339
Test name
Test status
Simulation time 37468156 ps
CPU time 1.13 seconds
Started May 05 01:53:37 PM PDT 24
Finished May 05 01:53:39 PM PDT 24
Peak memory 217332 kb
Host smart-96527862-cf67-47bb-b425-48a80f30c26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822222001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2822222001
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3378426625
Short name T753
Test name
Test status
Simulation time 20004743 ps
CPU time 1.1 seconds
Started May 05 01:53:37 PM PDT 24
Finished May 05 01:53:38 PM PDT 24
Peak memory 216268 kb
Host smart-6d3ba776-0711-4cec-9a8b-e1114c0a450d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378426625 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3378426625
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1552265434
Short name T491
Test name
Test status
Simulation time 52978555 ps
CPU time 0.93 seconds
Started May 05 01:53:38 PM PDT 24
Finished May 05 01:53:39 PM PDT 24
Peak memory 215588 kb
Host smart-afedbf4d-79ac-4c84-9f67-b5f75c348df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552265434 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1552265434
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2641635312
Short name T821
Test name
Test status
Simulation time 524652865 ps
CPU time 3.32 seconds
Started May 05 01:53:38 PM PDT 24
Finished May 05 01:53:42 PM PDT 24
Peak memory 217344 kb
Host smart-cfe3f023-4d57-4619-9202-0aaf0e7d0aa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641635312 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2641635312
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1997439167
Short name T2
Test name
Test status
Simulation time 146197641373 ps
CPU time 589.21 seconds
Started May 05 01:53:36 PM PDT 24
Finished May 05 02:03:25 PM PDT 24
Peak memory 219404 kb
Host smart-45962a47-1814-494b-988c-65f494dd60ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997439167 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1997439167
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2397183965
Short name T267
Test name
Test status
Simulation time 27307121 ps
CPU time 1.22 seconds
Started May 05 01:54:53 PM PDT 24
Finished May 05 01:54:55 PM PDT 24
Peak memory 218644 kb
Host smart-a28ad5c7-7c88-4716-b87f-bf4d1299e31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397183965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2397183965
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3432842566
Short name T384
Test name
Test status
Simulation time 4470452364 ps
CPU time 88.44 seconds
Started May 05 01:54:52 PM PDT 24
Finished May 05 01:56:21 PM PDT 24
Peak memory 220608 kb
Host smart-1bc04b79-46f0-4f39-b61e-8d34c1ffb15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432842566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3432842566
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1514304447
Short name T285
Test name
Test status
Simulation time 260013290 ps
CPU time 3.88 seconds
Started May 05 01:54:55 PM PDT 24
Finished May 05 01:54:59 PM PDT 24
Peak memory 217492 kb
Host smart-00a7da9d-ef96-437d-abe8-a5cf43499038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514304447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1514304447
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1731029537
Short name T69
Test name
Test status
Simulation time 52296015 ps
CPU time 1.58 seconds
Started May 05 01:54:51 PM PDT 24
Finished May 05 01:54:53 PM PDT 24
Peak memory 218352 kb
Host smart-340b08d0-aed7-4942-8cf4-383e4f1d9355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731029537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1731029537
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.459442619
Short name T643
Test name
Test status
Simulation time 263649620 ps
CPU time 1.21 seconds
Started May 05 01:54:55 PM PDT 24
Finished May 05 01:54:57 PM PDT 24
Peak memory 217332 kb
Host smart-56a6fb67-b58a-4d53-9327-33dabd24cd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459442619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.459442619
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1847416906
Short name T540
Test name
Test status
Simulation time 30780007 ps
CPU time 1.32 seconds
Started May 05 01:54:52 PM PDT 24
Finished May 05 01:54:54 PM PDT 24
Peak memory 218588 kb
Host smart-00cac02b-f0b1-49e4-8784-5a17f20c51be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847416906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1847416906
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3098628635
Short name T598
Test name
Test status
Simulation time 33933570 ps
CPU time 1.4 seconds
Started May 05 01:54:53 PM PDT 24
Finished May 05 01:54:55 PM PDT 24
Peak memory 217532 kb
Host smart-9573cb1d-7bea-4723-8a7c-a6a0ce35d6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098628635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3098628635
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.4034951849
Short name T718
Test name
Test status
Simulation time 48340608 ps
CPU time 1.25 seconds
Started May 05 01:54:54 PM PDT 24
Finished May 05 01:54:55 PM PDT 24
Peak memory 217404 kb
Host smart-b4b5ad9d-a38d-4291-b576-1c2c292a4672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034951849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.4034951849
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.989622652
Short name T710
Test name
Test status
Simulation time 36226621 ps
CPU time 1.31 seconds
Started May 05 01:54:58 PM PDT 24
Finished May 05 01:54:59 PM PDT 24
Peak memory 219568 kb
Host smart-73540bb6-0ba2-4d76-91b4-7af2ae638892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989622652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.989622652
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1213581706
Short name T780
Test name
Test status
Simulation time 54895127 ps
CPU time 1.21 seconds
Started May 05 01:54:58 PM PDT 24
Finished May 05 01:55:00 PM PDT 24
Peak memory 218368 kb
Host smart-10cdb469-0165-40d0-bdc7-1d86c4ca780d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213581706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1213581706
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert_test.1551056864
Short name T355
Test name
Test status
Simulation time 25650841 ps
CPU time 0.89 seconds
Started May 05 01:53:39 PM PDT 24
Finished May 05 01:53:41 PM PDT 24
Peak memory 206936 kb
Host smart-7217c3d7-2196-4a97-9271-1de368f322aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551056864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1551056864
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2210826774
Short name T147
Test name
Test status
Simulation time 13405088 ps
CPU time 0.92 seconds
Started May 05 01:53:40 PM PDT 24
Finished May 05 01:53:42 PM PDT 24
Peak memory 216944 kb
Host smart-ddf6579c-8b3c-47fc-b986-7317cfaef39b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210826774 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2210826774
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.4275853793
Short name T119
Test name
Test status
Simulation time 50110391 ps
CPU time 1.22 seconds
Started May 05 01:53:40 PM PDT 24
Finished May 05 01:53:42 PM PDT 24
Peak memory 217284 kb
Host smart-7de760ff-9808-4e71-95bb-35474004e841
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275853793 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.4275853793
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1491266585
Short name T64
Test name
Test status
Simulation time 21086994 ps
CPU time 1.27 seconds
Started May 05 01:53:41 PM PDT 24
Finished May 05 01:53:44 PM PDT 24
Peak memory 230008 kb
Host smart-824cec67-bae1-4553-99bb-9286c439584c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491266585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1491266585
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3721035452
Short name T701
Test name
Test status
Simulation time 94978217 ps
CPU time 1.34 seconds
Started May 05 01:53:35 PM PDT 24
Finished May 05 01:53:37 PM PDT 24
Peak memory 219828 kb
Host smart-aae7d827-8c6b-4230-922d-ffe87d1a2d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721035452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3721035452
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.1132098347
Short name T44
Test name
Test status
Simulation time 38314507 ps
CPU time 0.86 seconds
Started May 05 01:53:41 PM PDT 24
Finished May 05 01:53:43 PM PDT 24
Peak memory 216128 kb
Host smart-12ad4900-5842-4023-94bf-d560eec91e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132098347 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1132098347
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.4095977478
Short name T706
Test name
Test status
Simulation time 40847443 ps
CPU time 0.93 seconds
Started May 05 01:53:36 PM PDT 24
Finished May 05 01:53:38 PM PDT 24
Peak memory 215632 kb
Host smart-3db5b782-6034-4855-b9ab-1a7330c1b5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095977478 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.4095977478
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2718604211
Short name T359
Test name
Test status
Simulation time 683405078 ps
CPU time 3.58 seconds
Started May 05 01:53:37 PM PDT 24
Finished May 05 01:53:41 PM PDT 24
Peak memory 217324 kb
Host smart-9f311126-7d99-4fe9-bfb2-bd147bf4d03b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718604211 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2718604211
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2823672259
Short name T198
Test name
Test status
Simulation time 95118738121 ps
CPU time 1248.78 seconds
Started May 05 01:53:37 PM PDT 24
Finished May 05 02:14:26 PM PDT 24
Peak memory 225180 kb
Host smart-b1c7c1ac-55da-465f-9d88-0a6c1c8c1cf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823672259 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2823672259
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/291.edn_genbits.1756605852
Short name T613
Test name
Test status
Simulation time 69232652 ps
CPU time 1.24 seconds
Started May 05 01:54:54 PM PDT 24
Finished May 05 01:54:56 PM PDT 24
Peak memory 215564 kb
Host smart-85cfe942-fc5b-4434-90de-642cddbdca8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756605852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1756605852
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3822337333
Short name T330
Test name
Test status
Simulation time 37880850 ps
CPU time 1.51 seconds
Started May 05 01:55:02 PM PDT 24
Finished May 05 01:55:04 PM PDT 24
Peak memory 218396 kb
Host smart-f85eccb8-d8c1-4674-a701-3479fb00bb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822337333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3822337333
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2523518152
Short name T743
Test name
Test status
Simulation time 28772611 ps
CPU time 1.15 seconds
Started May 05 01:54:53 PM PDT 24
Finished May 05 01:54:54 PM PDT 24
Peak memory 218772 kb
Host smart-c3d0aca0-c0be-47fa-b496-5e5eb64cce19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523518152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2523518152
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3560270075
Short name T644
Test name
Test status
Simulation time 51907669 ps
CPU time 1.68 seconds
Started May 05 01:55:02 PM PDT 24
Finished May 05 01:55:04 PM PDT 24
Peak memory 220116 kb
Host smart-fd3df7c0-38c1-4fbf-b102-17a75c8e5d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560270075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3560270075
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.979558606
Short name T645
Test name
Test status
Simulation time 73860438 ps
CPU time 1.05 seconds
Started May 05 01:54:58 PM PDT 24
Finished May 05 01:55:00 PM PDT 24
Peak memory 217288 kb
Host smart-39e150b0-c32b-4b4a-9028-c5b703027a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979558606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.979558606
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3579978091
Short name T414
Test name
Test status
Simulation time 41237803 ps
CPU time 1.44 seconds
Started May 05 01:55:00 PM PDT 24
Finished May 05 01:55:02 PM PDT 24
Peak memory 217252 kb
Host smart-32028dee-3779-47ad-b3b1-bba5c105a443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579978091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3579978091
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.497719872
Short name T361
Test name
Test status
Simulation time 42418771 ps
CPU time 1.72 seconds
Started May 05 01:54:57 PM PDT 24
Finished May 05 01:54:59 PM PDT 24
Peak memory 218532 kb
Host smart-fbe2fe73-ce78-4f3b-b044-00a529327025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497719872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.497719872
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1639820767
Short name T283
Test name
Test status
Simulation time 72084114 ps
CPU time 1.74 seconds
Started May 05 01:54:55 PM PDT 24
Finished May 05 01:54:57 PM PDT 24
Peak memory 218660 kb
Host smart-35b335f1-ecab-4480-9eb5-815f6e8d54be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639820767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1639820767
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2058025131
Short name T778
Test name
Test status
Simulation time 30568950 ps
CPU time 1.31 seconds
Started May 05 01:54:58 PM PDT 24
Finished May 05 01:55:00 PM PDT 24
Peak memory 218492 kb
Host smart-c1d6642f-03dd-4289-b7eb-0cc233e33629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058025131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2058025131
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2989481880
Short name T257
Test name
Test status
Simulation time 72521523 ps
CPU time 1.15 seconds
Started May 05 01:52:34 PM PDT 24
Finished May 05 01:52:36 PM PDT 24
Peak memory 216032 kb
Host smart-e7c4d574-07c4-4b8a-9a48-ac9fa4b2ceac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989481880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2989481880
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_disable.1404354201
Short name T191
Test name
Test status
Simulation time 11208706 ps
CPU time 0.86 seconds
Started May 05 01:52:42 PM PDT 24
Finished May 05 01:52:44 PM PDT 24
Peak memory 216612 kb
Host smart-9c3df860-53ec-4cba-907c-9b50356abf47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404354201 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1404354201
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_err.3816726491
Short name T477
Test name
Test status
Simulation time 21079985 ps
CPU time 1 seconds
Started May 05 01:52:40 PM PDT 24
Finished May 05 01:52:42 PM PDT 24
Peak memory 224396 kb
Host smart-06b10e9a-e538-49a4-b894-54fbc38c9fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816726491 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3816726491
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2315186430
Short name T790
Test name
Test status
Simulation time 39752414 ps
CPU time 1.44 seconds
Started May 05 01:52:39 PM PDT 24
Finished May 05 01:52:40 PM PDT 24
Peak memory 218580 kb
Host smart-f339bdaa-59a1-4fdf-aa72-54778c86caab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315186430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2315186430
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.352937990
Short name T13
Test name
Test status
Simulation time 27402083 ps
CPU time 1.02 seconds
Started May 05 01:52:39 PM PDT 24
Finished May 05 01:52:40 PM PDT 24
Peak memory 224364 kb
Host smart-0086eb9f-3e7a-40e9-a618-1e6c7e38f7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352937990 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.352937990
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.780576723
Short name T291
Test name
Test status
Simulation time 41832700 ps
CPU time 0.93 seconds
Started May 05 01:52:34 PM PDT 24
Finished May 05 01:52:36 PM PDT 24
Peak memory 207436 kb
Host smart-1d689ef7-ccdc-404f-ab27-e89f60e5be8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780576723 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.780576723
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1714558425
Short name T70
Test name
Test status
Simulation time 1353861695 ps
CPU time 9.4 seconds
Started May 05 01:52:41 PM PDT 24
Finished May 05 01:52:51 PM PDT 24
Peak memory 236764 kb
Host smart-8ed31e77-c5b7-4bd0-8953-e3d04def487e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714558425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1714558425
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2282049533
Short name T461
Test name
Test status
Simulation time 15542335 ps
CPU time 0.94 seconds
Started May 05 01:52:36 PM PDT 24
Finished May 05 01:52:37 PM PDT 24
Peak memory 215616 kb
Host smart-7068a6ff-3f7b-4f26-b45f-f09c851cb101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282049533 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2282049533
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.995780367
Short name T619
Test name
Test status
Simulation time 311454374 ps
CPU time 5.57 seconds
Started May 05 01:52:38 PM PDT 24
Finished May 05 01:52:44 PM PDT 24
Peak memory 217180 kb
Host smart-26b80e62-eb7c-49c0-81f3-7baa7836a2c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995780367 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.995780367
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2240867540
Short name T199
Test name
Test status
Simulation time 35007416919 ps
CPU time 754.67 seconds
Started May 05 01:52:37 PM PDT 24
Finished May 05 02:05:12 PM PDT 24
Peak memory 217708 kb
Host smart-5e90dd51-93da-4ed2-91f7-f5520e4ece9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240867540 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2240867540
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert_test.3731116223
Short name T376
Test name
Test status
Simulation time 48857623 ps
CPU time 0.86 seconds
Started May 05 01:53:43 PM PDT 24
Finished May 05 01:53:44 PM PDT 24
Peak memory 206968 kb
Host smart-8b21c776-060f-43ca-8d15-52cecfb70cce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731116223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3731116223
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2682524361
Short name T549
Test name
Test status
Simulation time 382340870 ps
CPU time 1.18 seconds
Started May 05 01:53:40 PM PDT 24
Finished May 05 01:53:42 PM PDT 24
Peak memory 217160 kb
Host smart-72e1e499-7042-4f0f-bd39-f20a8029b4b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682524361 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2682524361
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.765986313
Short name T515
Test name
Test status
Simulation time 21952026 ps
CPU time 1.03 seconds
Started May 05 01:53:41 PM PDT 24
Finished May 05 01:53:43 PM PDT 24
Peak memory 224440 kb
Host smart-e8d5b406-aae7-4bad-8a0b-e2bb5d676501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765986313 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.765986313
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.4125990263
Short name T595
Test name
Test status
Simulation time 60712366 ps
CPU time 1.39 seconds
Started May 05 01:53:40 PM PDT 24
Finished May 05 01:53:43 PM PDT 24
Peak memory 218732 kb
Host smart-36182afe-f998-4d35-892b-e56fc4c9b8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125990263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.4125990263
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3270253392
Short name T584
Test name
Test status
Simulation time 47780485 ps
CPU time 0.84 seconds
Started May 05 01:53:40 PM PDT 24
Finished May 05 01:53:42 PM PDT 24
Peak memory 215640 kb
Host smart-3347164f-ea85-4e49-946c-f4cb5db08939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270253392 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3270253392
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3400146436
Short name T768
Test name
Test status
Simulation time 20069664 ps
CPU time 1.05 seconds
Started May 05 01:53:41 PM PDT 24
Finished May 05 01:53:43 PM PDT 24
Peak memory 215648 kb
Host smart-60270fcf-03dd-4a3f-b18e-6b95eec29309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400146436 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3400146436
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.166417295
Short name T517
Test name
Test status
Simulation time 471327114 ps
CPU time 4.93 seconds
Started May 05 01:53:45 PM PDT 24
Finished May 05 01:53:50 PM PDT 24
Peak memory 220208 kb
Host smart-9a5ab99d-1941-4074-9c6e-e6cbe2afe2cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166417295 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.166417295
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.372196335
Short name T164
Test name
Test status
Simulation time 295668261051 ps
CPU time 1543.32 seconds
Started May 05 01:53:42 PM PDT 24
Finished May 05 02:19:26 PM PDT 24
Peak memory 224500 kb
Host smart-b2e538e6-7b76-419f-ad63-848ac101c3cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372196335 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.372196335
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1553949945
Short name T139
Test name
Test status
Simulation time 41399696 ps
CPU time 1.16 seconds
Started May 05 01:53:48 PM PDT 24
Finished May 05 01:53:49 PM PDT 24
Peak memory 216052 kb
Host smart-e69b41cf-bd35-41b7-91a2-bb5826502898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553949945 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1553949945
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3987393576
Short name T690
Test name
Test status
Simulation time 43129616 ps
CPU time 0.83 seconds
Started May 05 01:53:51 PM PDT 24
Finished May 05 01:53:53 PM PDT 24
Peak memory 214936 kb
Host smart-20d8b3e4-3921-4619-ab83-7eeb01e4a846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987393576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3987393576
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2198477173
Short name T54
Test name
Test status
Simulation time 14473833 ps
CPU time 0.82 seconds
Started May 05 01:53:54 PM PDT 24
Finished May 05 01:53:56 PM PDT 24
Peak memory 215792 kb
Host smart-8720466f-b4c6-4221-824e-f2bacc6b004d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198477173 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2198477173
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3274356312
Short name T809
Test name
Test status
Simulation time 20195981 ps
CPU time 1.04 seconds
Started May 05 01:53:45 PM PDT 24
Finished May 05 01:53:47 PM PDT 24
Peak memory 218432 kb
Host smart-1e8033b7-22d9-49c4-b089-bd8825537271
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274356312 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3274356312
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3109557801
Short name T179
Test name
Test status
Simulation time 24903387 ps
CPU time 1 seconds
Started May 05 01:53:49 PM PDT 24
Finished May 05 01:53:50 PM PDT 24
Peak memory 219224 kb
Host smart-09928882-6135-456f-b409-fc89223b1495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109557801 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3109557801
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2671063690
Short name T565
Test name
Test status
Simulation time 120977823 ps
CPU time 1.3 seconds
Started May 05 01:53:43 PM PDT 24
Finished May 05 01:53:45 PM PDT 24
Peak memory 219992 kb
Host smart-ceaa3b38-0b94-4af6-b5a6-8b1a1b798bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671063690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2671063690
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3028574997
Short name T697
Test name
Test status
Simulation time 25954728 ps
CPU time 0.96 seconds
Started May 05 01:53:42 PM PDT 24
Finished May 05 01:53:44 PM PDT 24
Peak memory 215976 kb
Host smart-4d30a419-a9ff-41c1-8ab5-fe843a992d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028574997 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3028574997
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2712017737
Short name T534
Test name
Test status
Simulation time 43717121 ps
CPU time 0.95 seconds
Started May 05 01:53:41 PM PDT 24
Finished May 05 01:53:43 PM PDT 24
Peak memory 215636 kb
Host smart-114d46cf-b452-4f17-8704-55561d73cb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712017737 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2712017737
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3353379311
Short name T773
Test name
Test status
Simulation time 406713711 ps
CPU time 7.41 seconds
Started May 05 01:53:43 PM PDT 24
Finished May 05 01:53:51 PM PDT 24
Peak memory 219768 kb
Host smart-bc8af7c1-caa9-499c-a6fe-3fc98d18c7c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353379311 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3353379311
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.642591725
Short name T333
Test name
Test status
Simulation time 51940834472 ps
CPU time 1175.2 seconds
Started May 05 01:53:41 PM PDT 24
Finished May 05 02:13:18 PM PDT 24
Peak memory 220404 kb
Host smart-e8f554f5-6059-4805-ad49-6c8579e5fba2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642591725 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.642591725
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert_test.2600921105
Short name T353
Test name
Test status
Simulation time 20426368 ps
CPU time 0.96 seconds
Started May 05 01:53:49 PM PDT 24
Finished May 05 01:53:51 PM PDT 24
Peak memory 206948 kb
Host smart-801461fe-30dd-44d5-b11b-c2fd8675bd61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600921105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2600921105
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1398597659
Short name T159
Test name
Test status
Simulation time 79909473 ps
CPU time 0.88 seconds
Started May 05 01:53:49 PM PDT 24
Finished May 05 01:53:51 PM PDT 24
Peak memory 216600 kb
Host smart-a46d8c55-3e91-42e0-b103-c75c492d528f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398597659 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1398597659
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2229131679
Short name T544
Test name
Test status
Simulation time 50060916 ps
CPU time 1 seconds
Started May 05 01:53:48 PM PDT 24
Finished May 05 01:53:50 PM PDT 24
Peak memory 219568 kb
Host smart-b8270018-e563-45bd-84ad-9b25e8e131ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229131679 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2229131679
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2310829412
Short name T812
Test name
Test status
Simulation time 43302618 ps
CPU time 0.9 seconds
Started May 05 01:53:46 PM PDT 24
Finished May 05 01:53:48 PM PDT 24
Peak memory 218804 kb
Host smart-67fbbbd8-3c9a-49fc-8b37-259f047f4d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310829412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2310829412
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3898742431
Short name T476
Test name
Test status
Simulation time 41239034 ps
CPU time 1.55 seconds
Started May 05 01:53:49 PM PDT 24
Finished May 05 01:53:52 PM PDT 24
Peak memory 218584 kb
Host smart-4e64858e-b1ad-400b-945d-453d27fdd8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898742431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3898742431
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3783508033
Short name T448
Test name
Test status
Simulation time 39824758 ps
CPU time 0.94 seconds
Started May 05 01:53:50 PM PDT 24
Finished May 05 01:53:51 PM PDT 24
Peak memory 215840 kb
Host smart-05ef6410-3cb8-4110-ba03-15aa74bab7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783508033 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3783508033
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1966780073
Short name T373
Test name
Test status
Simulation time 26701904 ps
CPU time 0.97 seconds
Started May 05 01:53:53 PM PDT 24
Finished May 05 01:53:55 PM PDT 24
Peak memory 215592 kb
Host smart-0153e95b-cee9-41a3-b838-71c3953a3ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966780073 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1966780073
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3999212551
Short name T433
Test name
Test status
Simulation time 270352355 ps
CPU time 5.26 seconds
Started May 05 01:53:51 PM PDT 24
Finished May 05 01:53:57 PM PDT 24
Peak memory 217252 kb
Host smart-1242c2aa-2dc6-40e9-820c-332e9f0d4731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999212551 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3999212551
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.531453934
Short name T767
Test name
Test status
Simulation time 14453837980 ps
CPU time 317.18 seconds
Started May 05 01:53:50 PM PDT 24
Finished May 05 01:59:08 PM PDT 24
Peak memory 218120 kb
Host smart-5472dd24-384e-4cb4-a892-730ff27398a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531453934 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.531453934
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert_test.3822360705
Short name T825
Test name
Test status
Simulation time 20646375 ps
CPU time 0.76 seconds
Started May 05 01:53:51 PM PDT 24
Finished May 05 01:53:52 PM PDT 24
Peak memory 207132 kb
Host smart-b6ef4820-77be-429c-b73b-f731f84edbc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822360705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3822360705
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3947693930
Short name T479
Test name
Test status
Simulation time 11498499 ps
CPU time 0.83 seconds
Started May 05 01:53:46 PM PDT 24
Finished May 05 01:53:47 PM PDT 24
Peak memory 216732 kb
Host smart-c15f72da-471f-4003-acb4-ca6533ce7779
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947693930 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3947693930
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2284125919
Short name T18
Test name
Test status
Simulation time 33783866 ps
CPU time 1.24 seconds
Started May 05 01:53:48 PM PDT 24
Finished May 05 01:53:50 PM PDT 24
Peak memory 217356 kb
Host smart-9709009d-687e-465b-8394-f77f3fc0b281
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284125919 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2284125919
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.688976429
Short name T156
Test name
Test status
Simulation time 21416417 ps
CPU time 1.12 seconds
Started May 05 01:53:49 PM PDT 24
Finished May 05 01:53:51 PM PDT 24
Peak memory 219024 kb
Host smart-4e80c14b-8c19-4ec0-acd8-12030ee109f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688976429 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.688976429
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3607336645
Short name T646
Test name
Test status
Simulation time 120636952 ps
CPU time 1.16 seconds
Started May 05 01:53:47 PM PDT 24
Finished May 05 01:53:49 PM PDT 24
Peak memory 217452 kb
Host smart-8bed9821-41a7-4071-95d2-878de3228e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607336645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3607336645
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_smoke.500466562
Short name T383
Test name
Test status
Simulation time 25335681 ps
CPU time 0.95 seconds
Started May 05 01:53:50 PM PDT 24
Finished May 05 01:53:52 PM PDT 24
Peak memory 215644 kb
Host smart-1164e127-318c-4c89-8f56-b052c3b5c813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500466562 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.500466562
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3900395759
Short name T602
Test name
Test status
Simulation time 459441682 ps
CPU time 3.78 seconds
Started May 05 01:53:52 PM PDT 24
Finished May 05 01:53:57 PM PDT 24
Peak memory 217268 kb
Host smart-22d17672-46b3-44ea-8c20-86a34fb5f479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900395759 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3900395759
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1511776936
Short name T377
Test name
Test status
Simulation time 8445613760 ps
CPU time 190.29 seconds
Started May 05 01:53:50 PM PDT 24
Finished May 05 01:57:01 PM PDT 24
Peak memory 222000 kb
Host smart-adfb19eb-2491-4662-8663-52c4840b988d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511776936 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1511776936
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2429992944
Short name T34
Test name
Test status
Simulation time 27081799 ps
CPU time 1.19 seconds
Started May 05 01:53:51 PM PDT 24
Finished May 05 01:53:53 PM PDT 24
Peak memory 216056 kb
Host smart-fb6f33f2-857a-4079-9274-f3662d0d2b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429992944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2429992944
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.959964816
Short name T676
Test name
Test status
Simulation time 51952943 ps
CPU time 0.8 seconds
Started May 05 01:53:47 PM PDT 24
Finished May 05 01:53:48 PM PDT 24
Peak memory 215008 kb
Host smart-78762ce6-46eb-426f-8c84-e32a311fe6da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959964816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.959964816
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3322451936
Short name T606
Test name
Test status
Simulation time 16022483 ps
CPU time 0.83 seconds
Started May 05 01:53:55 PM PDT 24
Finished May 05 01:53:57 PM PDT 24
Peak memory 216620 kb
Host smart-7be0843e-c5e7-424d-af34-d3d81300df18
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322451936 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3322451936
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2651279457
Short name T784
Test name
Test status
Simulation time 50767874 ps
CPU time 1.1 seconds
Started May 05 01:53:46 PM PDT 24
Finished May 05 01:53:47 PM PDT 24
Peak memory 219808 kb
Host smart-7a7498ce-69ef-4581-826c-046d24374042
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651279457 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2651279457
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3256864927
Short name T472
Test name
Test status
Simulation time 29156292 ps
CPU time 0.95 seconds
Started May 05 01:53:49 PM PDT 24
Finished May 05 01:53:50 PM PDT 24
Peak memory 224240 kb
Host smart-32025181-aca4-407d-89b4-75dfbf0e3c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256864927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3256864927
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2799285635
Short name T845
Test name
Test status
Simulation time 36174659 ps
CPU time 1.42 seconds
Started May 05 01:53:46 PM PDT 24
Finished May 05 01:53:48 PM PDT 24
Peak memory 219840 kb
Host smart-731dc78a-436a-4956-a1f0-2ca3d35e8930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799285635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2799285635
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_smoke.859261941
Short name T654
Test name
Test status
Simulation time 30265706 ps
CPU time 0.91 seconds
Started May 05 01:53:54 PM PDT 24
Finished May 05 01:53:55 PM PDT 24
Peak memory 215612 kb
Host smart-e5cf09d8-8f5a-4e7d-8230-36f368ba380f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859261941 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.859261941
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3875901219
Short name T375
Test name
Test status
Simulation time 83494801 ps
CPU time 2.21 seconds
Started May 05 01:53:49 PM PDT 24
Finished May 05 01:53:52 PM PDT 24
Peak memory 217204 kb
Host smart-ee757674-5bce-4e60-8a2e-05f5ea20e9d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875901219 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3875901219
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1235433144
Short name T674
Test name
Test status
Simulation time 279013758264 ps
CPU time 1724.5 seconds
Started May 05 01:53:48 PM PDT 24
Finished May 05 02:22:34 PM PDT 24
Peak memory 228116 kb
Host smart-b910af83-24d4-49cb-a4cf-fae4f512b71a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235433144 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1235433144
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert_test.1036231614
Short name T554
Test name
Test status
Simulation time 122167410 ps
CPU time 0.87 seconds
Started May 05 01:53:49 PM PDT 24
Finished May 05 01:53:51 PM PDT 24
Peak memory 206916 kb
Host smart-e9c2b1e5-0594-4677-9dfa-0c3cebb0b5fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036231614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1036231614
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2257178752
Short name T417
Test name
Test status
Simulation time 19599531 ps
CPU time 0.91 seconds
Started May 05 01:53:47 PM PDT 24
Finished May 05 01:53:48 PM PDT 24
Peak memory 216416 kb
Host smart-6f93d076-87c1-44b7-8bc5-758c8cc797d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257178752 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2257178752
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_err.3755363758
Short name T490
Test name
Test status
Simulation time 30949296 ps
CPU time 0.88 seconds
Started May 05 01:53:54 PM PDT 24
Finished May 05 01:53:56 PM PDT 24
Peak memory 219004 kb
Host smart-0f778efd-1bc9-4188-b240-6e2434071623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755363758 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3755363758
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.906077494
Short name T564
Test name
Test status
Simulation time 47029180 ps
CPU time 1.52 seconds
Started May 05 01:53:50 PM PDT 24
Finished May 05 01:53:52 PM PDT 24
Peak memory 217388 kb
Host smart-fae31b85-2eca-4614-ab1d-bdf96b3a3abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906077494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.906077494
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3677962626
Short name T715
Test name
Test status
Simulation time 29979832 ps
CPU time 0.94 seconds
Started May 05 01:53:49 PM PDT 24
Finished May 05 01:53:50 PM PDT 24
Peak memory 216168 kb
Host smart-8f022120-5b65-471b-bffa-b31a19d19dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677962626 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3677962626
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.488358872
Short name T759
Test name
Test status
Simulation time 23267023 ps
CPU time 0.93 seconds
Started May 05 01:53:51 PM PDT 24
Finished May 05 01:53:53 PM PDT 24
Peak memory 215604 kb
Host smart-471833f9-e49e-4667-a6e7-437524d2a886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488358872 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.488358872
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.3782700642
Short name T799
Test name
Test status
Simulation time 2075439530 ps
CPU time 3.17 seconds
Started May 05 01:53:51 PM PDT 24
Finished May 05 01:53:55 PM PDT 24
Peak memory 217140 kb
Host smart-28702517-d4a2-4a40-813a-6c6b1a96216a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782700642 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3782700642
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.611495439
Short name T204
Test name
Test status
Simulation time 318324152611 ps
CPU time 1602.3 seconds
Started May 05 01:53:49 PM PDT 24
Finished May 05 02:20:32 PM PDT 24
Peak memory 224316 kb
Host smart-45ae973d-e6a1-43bd-98a6-402ceafc2d67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611495439 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.611495439
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1605358423
Short name T246
Test name
Test status
Simulation time 27355727 ps
CPU time 1.22 seconds
Started May 05 01:53:53 PM PDT 24
Finished May 05 01:53:55 PM PDT 24
Peak memory 215976 kb
Host smart-1c13b254-6247-4673-b8e8-7a44b00e6a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605358423 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1605358423
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2400727223
Short name T387
Test name
Test status
Simulation time 35018547 ps
CPU time 0.8 seconds
Started May 05 01:53:54 PM PDT 24
Finished May 05 01:53:56 PM PDT 24
Peak memory 207208 kb
Host smart-2af68daf-4d95-46cb-bc21-925307c29ed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400727223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2400727223
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.4146731934
Short name T528
Test name
Test status
Simulation time 72496688 ps
CPU time 1.36 seconds
Started May 05 01:53:56 PM PDT 24
Finished May 05 01:53:57 PM PDT 24
Peak memory 217276 kb
Host smart-f5ab0f84-8d17-4d81-8a05-2ec10cf4cd4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146731934 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.4146731934
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.743760143
Short name T41
Test name
Test status
Simulation time 31164765 ps
CPU time 1.19 seconds
Started May 05 01:53:51 PM PDT 24
Finished May 05 01:53:54 PM PDT 24
Peak memory 220208 kb
Host smart-7c8e3667-6be1-40ae-8737-86f86d3ac40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743760143 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.743760143
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_intr.79433560
Short name T648
Test name
Test status
Simulation time 23543584 ps
CPU time 1.17 seconds
Started May 05 01:53:51 PM PDT 24
Finished May 05 01:53:52 PM PDT 24
Peak memory 215964 kb
Host smart-187a2a49-6b41-40cf-ae1d-c94fd97dfff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79433560 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.79433560
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.208850182
Short name T318
Test name
Test status
Simulation time 47420923 ps
CPU time 0.94 seconds
Started May 05 01:53:50 PM PDT 24
Finished May 05 01:53:51 PM PDT 24
Peak memory 215604 kb
Host smart-7bd9f139-8068-4fc3-ad5a-b2e8932fc016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208850182 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.208850182
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3021716050
Short name T409
Test name
Test status
Simulation time 555956434 ps
CPU time 3.47 seconds
Started May 05 01:53:45 PM PDT 24
Finished May 05 01:53:49 PM PDT 24
Peak memory 215604 kb
Host smart-13c12017-6b69-4c09-ad1b-ee5ea7cc6d1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021716050 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3021716050
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1420761707
Short name T599
Test name
Test status
Simulation time 139422204614 ps
CPU time 1904.45 seconds
Started May 05 01:53:50 PM PDT 24
Finished May 05 02:25:35 PM PDT 24
Peak memory 226660 kb
Host smart-7e236460-4448-4b0f-8967-7b61ff08be3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420761707 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1420761707
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3713888294
Short name T480
Test name
Test status
Simulation time 58260410 ps
CPU time 1.29 seconds
Started May 05 01:53:55 PM PDT 24
Finished May 05 01:53:57 PM PDT 24
Peak memory 216048 kb
Host smart-a553f727-7814-4aae-bab8-28facf78c6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713888294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3713888294
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.467097026
Short name T831
Test name
Test status
Simulation time 33993030 ps
CPU time 0.96 seconds
Started May 05 01:53:53 PM PDT 24
Finished May 05 01:53:55 PM PDT 24
Peak memory 207136 kb
Host smart-4e6711e8-6028-455b-9ebb-328349c00499
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467097026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.467097026
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.4292107172
Short name T677
Test name
Test status
Simulation time 29198148 ps
CPU time 0.8 seconds
Started May 05 01:53:55 PM PDT 24
Finished May 05 01:53:57 PM PDT 24
Peak memory 215776 kb
Host smart-e07cfb07-9048-41d9-a30d-d5f9d4cd47ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292107172 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.4292107172
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_err.1019438822
Short name T365
Test name
Test status
Simulation time 101226341 ps
CPU time 0.89 seconds
Started May 05 01:53:49 PM PDT 24
Finished May 05 01:53:51 PM PDT 24
Peak memory 218784 kb
Host smart-622b549f-2bab-49e4-aac4-f1bddd5a1c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019438822 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1019438822
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3415874882
Short name T410
Test name
Test status
Simulation time 39116989 ps
CPU time 1.31 seconds
Started May 05 01:53:52 PM PDT 24
Finished May 05 01:53:54 PM PDT 24
Peak memory 217264 kb
Host smart-394ac7de-4333-4bbe-8d5b-2cf0984b032c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415874882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3415874882
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.915441273
Short name T108
Test name
Test status
Simulation time 25951956 ps
CPU time 0.97 seconds
Started May 05 01:53:53 PM PDT 24
Finished May 05 01:53:55 PM PDT 24
Peak memory 216220 kb
Host smart-46e07e94-c218-4d3e-8279-2ee8965aedd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915441273 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.915441273
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3023212433
Short name T556
Test name
Test status
Simulation time 104414441 ps
CPU time 0.89 seconds
Started May 05 01:53:51 PM PDT 24
Finished May 05 01:53:53 PM PDT 24
Peak memory 215616 kb
Host smart-2fd3ab26-39bf-49e8-9646-1a219c2d927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023212433 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3023212433
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2764106215
Short name T371
Test name
Test status
Simulation time 272590414 ps
CPU time 2.91 seconds
Started May 05 01:53:52 PM PDT 24
Finished May 05 01:53:56 PM PDT 24
Peak memory 217408 kb
Host smart-24417ef8-5fb1-4b55-9ab6-a42156c081e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764106215 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2764106215
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.655308670
Short name T442
Test name
Test status
Simulation time 22934089999 ps
CPU time 521.89 seconds
Started May 05 01:53:54 PM PDT 24
Finished May 05 02:02:37 PM PDT 24
Peak memory 218720 kb
Host smart-d521c6de-3341-4942-bfa1-52df2014fdb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655308670 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.655308670
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.2589007124
Short name T90
Test name
Test status
Simulation time 170137834 ps
CPU time 1.28 seconds
Started May 05 01:53:55 PM PDT 24
Finished May 05 01:53:57 PM PDT 24
Peak memory 216040 kb
Host smart-17bc8947-7f2c-435a-9863-3a75685742f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589007124 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2589007124
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3332339448
Short name T634
Test name
Test status
Simulation time 30270305 ps
CPU time 0.92 seconds
Started May 05 01:53:50 PM PDT 24
Finished May 05 01:53:52 PM PDT 24
Peak memory 206988 kb
Host smart-7dd84149-f23a-4b0d-bac3-526d91004ae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332339448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3332339448
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2929201811
Short name T194
Test name
Test status
Simulation time 13538825 ps
CPU time 0.88 seconds
Started May 05 01:53:55 PM PDT 24
Finished May 05 01:53:57 PM PDT 24
Peak memory 216804 kb
Host smart-b4b49c2a-ccbf-473c-b8c2-5fe75fa85191
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929201811 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2929201811
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.846017306
Short name T546
Test name
Test status
Simulation time 66891863 ps
CPU time 1.03 seconds
Started May 05 01:53:53 PM PDT 24
Finished May 05 01:53:54 PM PDT 24
Peak memory 218724 kb
Host smart-12f87143-3b77-4b88-b3ac-7b476d265b51
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846017306 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.846017306
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3722234183
Short name T723
Test name
Test status
Simulation time 24826456 ps
CPU time 0.88 seconds
Started May 05 01:53:53 PM PDT 24
Finished May 05 01:53:55 PM PDT 24
Peak memory 215768 kb
Host smart-2e0c22e3-aaca-4820-854e-6e021c6c4804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722234183 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3722234183
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3381104108
Short name T380
Test name
Test status
Simulation time 31955825 ps
CPU time 1.34 seconds
Started May 05 01:53:57 PM PDT 24
Finished May 05 01:53:59 PM PDT 24
Peak memory 217376 kb
Host smart-2f423980-339a-44ac-ba3e-7deb381ee057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381104108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3381104108
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1369960206
Short name T712
Test name
Test status
Simulation time 33889206 ps
CPU time 0.93 seconds
Started May 05 01:53:53 PM PDT 24
Finished May 05 01:53:55 PM PDT 24
Peak memory 215884 kb
Host smart-e7e0f3b5-2e1c-406c-9dcc-d4232b345ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369960206 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1369960206
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.785845951
Short name T621
Test name
Test status
Simulation time 20557976 ps
CPU time 0.94 seconds
Started May 05 01:53:52 PM PDT 24
Finished May 05 01:53:54 PM PDT 24
Peak memory 215100 kb
Host smart-8b44444c-372a-4bd3-846e-a47386b503f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785845951 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.785845951
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.4134245058
Short name T501
Test name
Test status
Simulation time 319774017 ps
CPU time 6.77 seconds
Started May 05 01:53:52 PM PDT 24
Finished May 05 01:53:59 PM PDT 24
Peak memory 217128 kb
Host smart-d922eb1a-613e-44b4-90e0-149dce43200d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134245058 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.4134245058
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2292651458
Short name T200
Test name
Test status
Simulation time 100712589969 ps
CPU time 1037.4 seconds
Started May 05 01:53:51 PM PDT 24
Finished May 05 02:11:09 PM PDT 24
Peak memory 221464 kb
Host smart-06b24737-965a-41ca-8b49-e8e00066186e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292651458 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2292651458
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.4178853216
Short name T577
Test name
Test status
Simulation time 45089121 ps
CPU time 1.19 seconds
Started May 05 01:53:53 PM PDT 24
Finished May 05 01:53:55 PM PDT 24
Peak memory 216020 kb
Host smart-3171ede7-15f0-476f-a6ec-0a8a41f5d5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178853216 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.4178853216
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1185233562
Short name T542
Test name
Test status
Simulation time 17950939 ps
CPU time 0.98 seconds
Started May 05 01:53:51 PM PDT 24
Finished May 05 01:53:52 PM PDT 24
Peak memory 206956 kb
Host smart-eceab9da-edd1-4563-9d3c-88bc5c1fc0c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185233562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1185233562
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1015720412
Short name T432
Test name
Test status
Simulation time 18318641 ps
CPU time 0.84 seconds
Started May 05 01:53:52 PM PDT 24
Finished May 05 01:53:54 PM PDT 24
Peak memory 215784 kb
Host smart-4b2cd06c-06e9-4ee4-9b85-7a3cb8693e6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015720412 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1015720412
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1725003567
Short name T738
Test name
Test status
Simulation time 24794030 ps
CPU time 1.1 seconds
Started May 05 01:53:51 PM PDT 24
Finished May 05 01:53:53 PM PDT 24
Peak memory 218372 kb
Host smart-6928c7d1-697d-47e4-842b-63cef2b0fc2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725003567 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1725003567
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.44796294
Short name T66
Test name
Test status
Simulation time 32205743 ps
CPU time 0.98 seconds
Started May 05 01:53:52 PM PDT 24
Finished May 05 01:53:54 PM PDT 24
Peak memory 224248 kb
Host smart-985e9e57-14b8-49fb-b29a-e628e7921b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44796294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.44796294
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.4013824934
Short name T524
Test name
Test status
Simulation time 40773159 ps
CPU time 1.11 seconds
Started May 05 01:53:52 PM PDT 24
Finished May 05 01:53:54 PM PDT 24
Peak memory 217292 kb
Host smart-d0db3f5f-5f9c-43cf-82cb-78434c506274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013824934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.4013824934
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_smoke.2266301781
Short name T537
Test name
Test status
Simulation time 26663068 ps
CPU time 0.96 seconds
Started May 05 01:53:54 PM PDT 24
Finished May 05 01:53:56 PM PDT 24
Peak memory 215584 kb
Host smart-474c97ff-6f7a-4237-b7a1-64ffeeca47d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266301781 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2266301781
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.598902907
Short name T788
Test name
Test status
Simulation time 346371661 ps
CPU time 5.07 seconds
Started May 05 01:53:52 PM PDT 24
Finished May 05 01:53:58 PM PDT 24
Peak memory 217240 kb
Host smart-a6c96bae-1448-4634-89cb-7a0201766ff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598902907 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.598902907
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3612408677
Short name T281
Test name
Test status
Simulation time 19698856073 ps
CPU time 440.4 seconds
Started May 05 01:54:00 PM PDT 24
Finished May 05 02:01:21 PM PDT 24
Peak memory 223936 kb
Host smart-c335a299-0b6d-4233-aad9-af0771e33af5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612408677 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3612408677
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.4111946587
Short name T288
Test name
Test status
Simulation time 31784367 ps
CPU time 1.35 seconds
Started May 05 01:52:43 PM PDT 24
Finished May 05 01:52:45 PM PDT 24
Peak memory 216048 kb
Host smart-6ffbc0ef-684a-41c8-9fdb-b9906baee62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111946587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.4111946587
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.912578882
Short name T364
Test name
Test status
Simulation time 19774902 ps
CPU time 0.98 seconds
Started May 05 01:52:46 PM PDT 24
Finished May 05 01:52:48 PM PDT 24
Peak memory 215240 kb
Host smart-401d65aa-8e8a-4eb3-93f5-0f5282b0fbd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912578882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.912578882
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3726018363
Short name T177
Test name
Test status
Simulation time 105733663 ps
CPU time 0.81 seconds
Started May 05 01:52:40 PM PDT 24
Finished May 05 01:52:41 PM PDT 24
Peak memory 216528 kb
Host smart-a6a62a17-8c40-4e0f-b7c5-a35a1a43147b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726018363 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3726018363
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.207042843
Short name T632
Test name
Test status
Simulation time 35386835 ps
CPU time 1.16 seconds
Started May 05 01:52:42 PM PDT 24
Finished May 05 01:52:43 PM PDT 24
Peak memory 217112 kb
Host smart-7283831d-a07a-4a8d-88d1-6a735a9d46ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207042843 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.207042843
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.901880863
Short name T110
Test name
Test status
Simulation time 25593671 ps
CPU time 1.22 seconds
Started May 05 01:52:41 PM PDT 24
Finished May 05 01:52:43 PM PDT 24
Peak memory 221000 kb
Host smart-827dcda3-59be-4b4a-bffc-1c9184033b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901880863 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.901880863
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.586944307
Short name T455
Test name
Test status
Simulation time 46964745 ps
CPU time 1.77 seconds
Started May 05 01:52:42 PM PDT 24
Finished May 05 01:52:44 PM PDT 24
Peak memory 218476 kb
Host smart-1df6d048-7b14-4050-b2ae-492ab9516fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586944307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.586944307
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2066062172
Short name T531
Test name
Test status
Simulation time 26477654 ps
CPU time 1.05 seconds
Started May 05 01:52:41 PM PDT 24
Finished May 05 01:52:43 PM PDT 24
Peak memory 224408 kb
Host smart-2a856292-65e2-4632-8087-87288666a033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066062172 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2066062172
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3743646729
Short name T17
Test name
Test status
Simulation time 237341027 ps
CPU time 4.18 seconds
Started May 05 01:52:43 PM PDT 24
Finished May 05 01:52:48 PM PDT 24
Peak memory 235612 kb
Host smart-f2c26e23-9df2-4736-b2e1-28f5e6b18454
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743646729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3743646729
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2051046190
Short name T462
Test name
Test status
Simulation time 30619362 ps
CPU time 0.96 seconds
Started May 05 01:52:41 PM PDT 24
Finished May 05 01:52:42 PM PDT 24
Peak memory 215540 kb
Host smart-94330b5b-c70c-43c5-ba10-f923ba11a50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051046190 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2051046190
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2011439331
Short name T496
Test name
Test status
Simulation time 29875081 ps
CPU time 1.23 seconds
Started May 05 01:52:39 PM PDT 24
Finished May 05 01:52:41 PM PDT 24
Peak memory 215664 kb
Host smart-bd793ce6-ac58-4812-aa3f-3ea4373c96c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011439331 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2011439331
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2100296463
Short name T172
Test name
Test status
Simulation time 59372261854 ps
CPU time 1604.31 seconds
Started May 05 01:52:42 PM PDT 24
Finished May 05 02:19:27 PM PDT 24
Peak memory 225088 kb
Host smart-185c4a41-19db-4b67-b56b-efab8bfb563f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100296463 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2100296463
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.668679885
Short name T143
Test name
Test status
Simulation time 179946898 ps
CPU time 1.25 seconds
Started May 05 01:53:57 PM PDT 24
Finished May 05 01:53:59 PM PDT 24
Peak memory 216040 kb
Host smart-6270b220-e927-4384-96af-3425849988be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668679885 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.668679885
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.817476260
Short name T481
Test name
Test status
Simulation time 42198326 ps
CPU time 0.89 seconds
Started May 05 01:53:57 PM PDT 24
Finished May 05 01:53:59 PM PDT 24
Peak memory 215164 kb
Host smart-3acf9bbb-c94d-48f3-b4c7-b7dc0b3096be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817476260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.817476260
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1024103152
Short name T133
Test name
Test status
Simulation time 65604515 ps
CPU time 0.83 seconds
Started May 05 01:53:54 PM PDT 24
Finished May 05 01:53:56 PM PDT 24
Peak memory 215700 kb
Host smart-802f17a7-8b9a-47a3-905e-59b39b70581e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024103152 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1024103152
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.4054002868
Short name T705
Test name
Test status
Simulation time 27679283 ps
CPU time 1.13 seconds
Started May 05 01:54:00 PM PDT 24
Finished May 05 01:54:01 PM PDT 24
Peak memory 219704 kb
Host smart-f4716902-2d78-4569-b7e3-6dc374dea4fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054002868 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.4054002868
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3101603891
Short name T187
Test name
Test status
Simulation time 19234779 ps
CPU time 1.15 seconds
Started May 05 01:53:57 PM PDT 24
Finished May 05 01:53:59 PM PDT 24
Peak memory 219096 kb
Host smart-df5447a1-410f-4d11-93ef-5b97a1b17e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101603891 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3101603891
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1045421206
Short name T431
Test name
Test status
Simulation time 75468499 ps
CPU time 1.43 seconds
Started May 05 01:53:52 PM PDT 24
Finished May 05 01:53:54 PM PDT 24
Peak memory 218516 kb
Host smart-96eb5bf1-70b7-4110-8cc7-83b674a71797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045421206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1045421206
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1280177878
Short name T389
Test name
Test status
Simulation time 22586919 ps
CPU time 1.12 seconds
Started May 05 01:54:00 PM PDT 24
Finished May 05 01:54:01 PM PDT 24
Peak memory 215972 kb
Host smart-41c4707a-a166-465b-89a6-ce17eaca6a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280177878 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1280177878
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.782296552
Short name T797
Test name
Test status
Simulation time 28361941 ps
CPU time 0.99 seconds
Started May 05 01:53:57 PM PDT 24
Finished May 05 01:53:58 PM PDT 24
Peak memory 215600 kb
Host smart-33740c4e-6f18-4788-a045-d1a32c735df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782296552 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.782296552
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.37178761
Short name T733
Test name
Test status
Simulation time 341359395 ps
CPU time 6.73 seconds
Started May 05 01:53:55 PM PDT 24
Finished May 05 01:54:02 PM PDT 24
Peak memory 215632 kb
Host smart-e79bb4ea-6012-4364-936f-739ff73276be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37178761 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.37178761
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3617489796
Short name T721
Test name
Test status
Simulation time 123423101369 ps
CPU time 2798.15 seconds
Started May 05 01:53:57 PM PDT 24
Finished May 05 02:40:36 PM PDT 24
Peak memory 231052 kb
Host smart-f636f747-1acf-4227-b0d7-69ec655cbc8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617489796 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3617489796
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert_test.3893311110
Short name T689
Test name
Test status
Simulation time 14421990 ps
CPU time 0.84 seconds
Started May 05 01:53:57 PM PDT 24
Finished May 05 01:53:58 PM PDT 24
Peak memory 206936 kb
Host smart-92fe6257-a687-4e5c-bc7b-250883b7658e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893311110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3893311110
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.4126356296
Short name T815
Test name
Test status
Simulation time 16958516 ps
CPU time 0.85 seconds
Started May 05 01:53:57 PM PDT 24
Finished May 05 01:53:59 PM PDT 24
Peak memory 216756 kb
Host smart-b8bc7e5c-f8e7-4b57-a55b-ceb89c23f409
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126356296 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.4126356296
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2416894543
Short name T125
Test name
Test status
Simulation time 37371234 ps
CPU time 1.42 seconds
Started May 05 01:53:55 PM PDT 24
Finished May 05 01:53:57 PM PDT 24
Peak memory 218488 kb
Host smart-4d23f175-29ea-403c-9256-700c41e4192a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416894543 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2416894543
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.1851121502
Short name T180
Test name
Test status
Simulation time 21200791 ps
CPU time 1.02 seconds
Started May 05 01:53:57 PM PDT 24
Finished May 05 01:53:59 PM PDT 24
Peak memory 218892 kb
Host smart-1d59ae54-64ab-4667-be56-43a710d82033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851121502 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1851121502
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1416723652
Short name T627
Test name
Test status
Simulation time 80901463 ps
CPU time 1.15 seconds
Started May 05 01:53:57 PM PDT 24
Finished May 05 01:53:58 PM PDT 24
Peak memory 217432 kb
Host smart-4c114ce2-59d1-4cd2-8fc1-a98605baa76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416723652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1416723652
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2104563161
Short name T529
Test name
Test status
Simulation time 36530572 ps
CPU time 0.94 seconds
Started May 05 01:54:00 PM PDT 24
Finished May 05 01:54:01 PM PDT 24
Peak memory 215776 kb
Host smart-613cc450-7473-4f4b-b070-ee6ddeccb58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104563161 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2104563161
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3287574871
Short name T468
Test name
Test status
Simulation time 52453936 ps
CPU time 0.94 seconds
Started May 05 01:53:58 PM PDT 24
Finished May 05 01:54:00 PM PDT 24
Peak memory 207444 kb
Host smart-81693412-01c1-480f-a8ab-3cbe058b4108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287574871 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3287574871
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1505899916
Short name T770
Test name
Test status
Simulation time 282944025 ps
CPU time 2.08 seconds
Started May 05 01:53:57 PM PDT 24
Finished May 05 01:54:00 PM PDT 24
Peak memory 215756 kb
Host smart-0bbbf75c-067b-465d-8a75-85c8b8ceaf4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505899916 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1505899916
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1367642444
Short name T836
Test name
Test status
Simulation time 32006081650 ps
CPU time 845.35 seconds
Started May 05 01:53:58 PM PDT 24
Finished May 05 02:08:04 PM PDT 24
Peak memory 219028 kb
Host smart-6fee2371-5976-4cc1-9bdb-4aa2d09bf8ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367642444 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1367642444
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1612697155
Short name T777
Test name
Test status
Simulation time 89015293 ps
CPU time 1.18 seconds
Started May 05 01:53:56 PM PDT 24
Finished May 05 01:53:57 PM PDT 24
Peak memory 216036 kb
Host smart-a703d229-a4d3-4a0f-9047-eb8ccb23ade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612697155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1612697155
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3563498813
Short name T471
Test name
Test status
Simulation time 61020230 ps
CPU time 1.11 seconds
Started May 05 01:53:58 PM PDT 24
Finished May 05 01:54:00 PM PDT 24
Peak memory 215320 kb
Host smart-28783335-bf11-4b8a-a5d5-07d3cde68fa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563498813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3563498813
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.548496701
Short name T163
Test name
Test status
Simulation time 62344146 ps
CPU time 0.89 seconds
Started May 05 01:53:56 PM PDT 24
Finished May 05 01:53:57 PM PDT 24
Peak memory 216252 kb
Host smart-8863a0e7-293f-4e7f-8e27-4e9a302e43f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548496701 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.548496701
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.690575177
Short name T813
Test name
Test status
Simulation time 63313878 ps
CPU time 1.29 seconds
Started May 05 01:53:58 PM PDT 24
Finished May 05 01:54:00 PM PDT 24
Peak memory 217340 kb
Host smart-20fa0016-9c98-4141-a3b2-3dc6524dc7f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690575177 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.690575177
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1839215584
Short name T484
Test name
Test status
Simulation time 24421589 ps
CPU time 0.97 seconds
Started May 05 01:53:57 PM PDT 24
Finished May 05 01:53:59 PM PDT 24
Peak memory 218932 kb
Host smart-2fb7e615-4690-4ccf-a7d4-96cdd939ead7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839215584 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1839215584
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1900871702
Short name T75
Test name
Test status
Simulation time 148832657 ps
CPU time 0.99 seconds
Started May 05 01:53:56 PM PDT 24
Finished May 05 01:53:58 PM PDT 24
Peak memory 217272 kb
Host smart-14313623-a30b-4739-82ec-283cb226a835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900871702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1900871702
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2519252089
Short name T106
Test name
Test status
Simulation time 20774659 ps
CPU time 1.1 seconds
Started May 05 01:53:59 PM PDT 24
Finished May 05 01:54:00 PM PDT 24
Peak memory 216292 kb
Host smart-a940d823-a3e5-448c-947f-488cceb084eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519252089 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2519252089
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3843035631
Short name T651
Test name
Test status
Simulation time 50792260 ps
CPU time 0.94 seconds
Started May 05 01:53:57 PM PDT 24
Finished May 05 01:53:58 PM PDT 24
Peak memory 215620 kb
Host smart-93cce3b9-8776-4c50-8716-bdf6f9e49b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843035631 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3843035631
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2157738526
Short name T703
Test name
Test status
Simulation time 937450402 ps
CPU time 1.92 seconds
Started May 05 01:53:58 PM PDT 24
Finished May 05 01:54:01 PM PDT 24
Peak memory 217252 kb
Host smart-d7576302-ddd3-403b-9b3c-24080ae09195
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157738526 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2157738526
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2712481360
Short name T203
Test name
Test status
Simulation time 136832592772 ps
CPU time 406.53 seconds
Started May 05 01:53:56 PM PDT 24
Finished May 05 02:00:44 PM PDT 24
Peak memory 218952 kb
Host smart-ae77f42d-4ca8-4de3-9e3c-0943fe771b36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712481360 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2712481360
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1018707495
Short name T32
Test name
Test status
Simulation time 47344907 ps
CPU time 1.13 seconds
Started May 05 01:54:02 PM PDT 24
Finished May 05 01:54:03 PM PDT 24
Peak memory 216008 kb
Host smart-07fe31d9-67c5-4bf0-94e3-220d8f731ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018707495 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1018707495
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1230319749
Short name T489
Test name
Test status
Simulation time 24805434 ps
CPU time 0.89 seconds
Started May 05 01:54:04 PM PDT 24
Finished May 05 01:54:06 PM PDT 24
Peak memory 206964 kb
Host smart-fdac0797-900e-47de-8757-6b1b1733283d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230319749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1230319749
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1834270342
Short name T806
Test name
Test status
Simulation time 12138023 ps
CPU time 0.96 seconds
Started May 05 01:54:03 PM PDT 24
Finished May 05 01:54:05 PM PDT 24
Peak memory 216756 kb
Host smart-15732df2-dda2-43f0-8256-cfa94ee33e73
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834270342 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1834270342
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.4247846583
Short name T525
Test name
Test status
Simulation time 61123772 ps
CPU time 1.07 seconds
Started May 05 01:54:01 PM PDT 24
Finished May 05 01:54:02 PM PDT 24
Peak memory 218424 kb
Host smart-f051eff3-b28c-457e-913d-2c671e933a89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247846583 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.4247846583
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.502694994
Short name T132
Test name
Test status
Simulation time 29772828 ps
CPU time 0.92 seconds
Started May 05 01:54:07 PM PDT 24
Finished May 05 01:54:08 PM PDT 24
Peak memory 218812 kb
Host smart-ac5e008a-4ea7-4426-a220-911ebaa58740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502694994 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.502694994
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.151820562
Short name T787
Test name
Test status
Simulation time 63423627 ps
CPU time 1.61 seconds
Started May 05 01:54:03 PM PDT 24
Finished May 05 01:54:05 PM PDT 24
Peak memory 218524 kb
Host smart-2218d25d-0691-4b7e-a835-5f37683a3467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151820562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.151820562
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3727119906
Short name T342
Test name
Test status
Simulation time 21390469 ps
CPU time 1.01 seconds
Started May 05 01:54:04 PM PDT 24
Finished May 05 01:54:06 PM PDT 24
Peak memory 215784 kb
Host smart-80c70e50-b530-4137-96a3-b9f4ac4671d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727119906 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3727119906
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2657702367
Short name T532
Test name
Test status
Simulation time 15094011 ps
CPU time 0.98 seconds
Started May 05 01:53:57 PM PDT 24
Finished May 05 01:53:58 PM PDT 24
Peak memory 215616 kb
Host smart-e25f2def-3f35-42dd-944e-bc3227ac1b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657702367 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2657702367
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2090960792
Short name T4
Test name
Test status
Simulation time 1378495435 ps
CPU time 4.8 seconds
Started May 05 01:54:03 PM PDT 24
Finished May 05 01:54:08 PM PDT 24
Peak memory 220288 kb
Host smart-3996100a-2038-4c3e-89e9-6e8b10a0448b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090960792 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2090960792
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.560782058
Short name T351
Test name
Test status
Simulation time 56162475368 ps
CPU time 860.97 seconds
Started May 05 01:54:05 PM PDT 24
Finished May 05 02:08:26 PM PDT 24
Peak memory 223960 kb
Host smart-562ff935-1c13-4fea-a430-16cf889a57cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560782058 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.560782058
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1370278482
Short name T740
Test name
Test status
Simulation time 66551588 ps
CPU time 1.22 seconds
Started May 05 01:54:03 PM PDT 24
Finished May 05 01:54:05 PM PDT 24
Peak memory 216044 kb
Host smart-72624936-b629-4fbf-81d9-9a892c994573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370278482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1370278482
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.199683311
Short name T684
Test name
Test status
Simulation time 53715504 ps
CPU time 0.89 seconds
Started May 05 01:54:03 PM PDT 24
Finished May 05 01:54:05 PM PDT 24
Peak memory 207012 kb
Host smart-3cf922ed-1fee-4f62-bc31-962fdca7bbe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199683311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.199683311
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2954189734
Short name T94
Test name
Test status
Simulation time 47103363 ps
CPU time 1.47 seconds
Started May 05 01:54:03 PM PDT 24
Finished May 05 01:54:05 PM PDT 24
Peak memory 217296 kb
Host smart-c80a1620-84e1-4192-8edd-7f6d68d2547b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954189734 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2954189734
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3102649465
Short name T808
Test name
Test status
Simulation time 18298392 ps
CPU time 1.05 seconds
Started May 05 01:54:00 PM PDT 24
Finished May 05 01:54:02 PM PDT 24
Peak memory 219152 kb
Host smart-dac6a0e5-d75e-4b08-b1dc-1343883e69b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102649465 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3102649465
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2994362715
Short name T424
Test name
Test status
Simulation time 52578822 ps
CPU time 1.02 seconds
Started May 05 01:54:05 PM PDT 24
Finished May 05 01:54:06 PM PDT 24
Peak memory 217568 kb
Host smart-460610ec-674f-4c4d-9f21-971d76f3cfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994362715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2994362715
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1813614534
Short name T593
Test name
Test status
Simulation time 31043645 ps
CPU time 0.94 seconds
Started May 05 01:54:02 PM PDT 24
Finished May 05 01:54:04 PM PDT 24
Peak memory 216060 kb
Host smart-6494e9a5-9b4b-4962-8ba4-1805bbfae2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813614534 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1813614534
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1845498289
Short name T726
Test name
Test status
Simulation time 20747683 ps
CPU time 0.95 seconds
Started May 05 01:54:01 PM PDT 24
Finished May 05 01:54:03 PM PDT 24
Peak memory 215584 kb
Host smart-932889e7-d998-4a29-a457-d1096cf1499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845498289 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1845498289
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.40320954
Short name T212
Test name
Test status
Simulation time 296734086 ps
CPU time 3.24 seconds
Started May 05 01:54:02 PM PDT 24
Finished May 05 01:54:05 PM PDT 24
Peak memory 217232 kb
Host smart-12c4fc33-033b-4c07-a47a-35437ef9a1e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40320954 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.40320954
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3156315144
Short name T45
Test name
Test status
Simulation time 926989216846 ps
CPU time 2653.21 seconds
Started May 05 01:54:04 PM PDT 24
Finished May 05 02:38:18 PM PDT 24
Peak memory 228456 kb
Host smart-51943434-8ffb-415d-b11a-9e57e3427ee0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156315144 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3156315144
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2521799360
Short name T244
Test name
Test status
Simulation time 37414391 ps
CPU time 1.34 seconds
Started May 05 01:54:04 PM PDT 24
Finished May 05 01:54:06 PM PDT 24
Peak memory 216048 kb
Host smart-49b02b3f-0696-4166-bbb2-58c0017d6c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521799360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2521799360
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3619318766
Short name T523
Test name
Test status
Simulation time 53168497 ps
CPU time 0.87 seconds
Started May 05 01:54:09 PM PDT 24
Finished May 05 01:54:10 PM PDT 24
Peak memory 215144 kb
Host smart-26bdd72b-3466-47fa-81f0-a930d78113c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619318766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3619318766
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1885998
Short name T157
Test name
Test status
Simulation time 31088145 ps
CPU time 0.89 seconds
Started May 05 01:54:07 PM PDT 24
Finished May 05 01:54:08 PM PDT 24
Peak memory 216580 kb
Host smart-949af8a2-22c3-48e7-9edc-547913e6861d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885998 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1885998
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1875381450
Short name T128
Test name
Test status
Simulation time 50280756 ps
CPU time 1.51 seconds
Started May 05 01:54:09 PM PDT 24
Finished May 05 01:54:11 PM PDT 24
Peak memory 217248 kb
Host smart-8f7ed2a7-94a0-46a6-9d87-4fb388766e2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875381450 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1875381450
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1521479079
Short name T366
Test name
Test status
Simulation time 47233865 ps
CPU time 1.06 seconds
Started May 05 01:54:05 PM PDT 24
Finished May 05 01:54:07 PM PDT 24
Peak memory 219128 kb
Host smart-62d14c0f-9109-4650-b547-85137adebed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521479079 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1521479079
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1482608793
Short name T642
Test name
Test status
Simulation time 58765433 ps
CPU time 1.25 seconds
Started May 05 01:54:03 PM PDT 24
Finished May 05 01:54:05 PM PDT 24
Peak memory 218912 kb
Host smart-be768ddf-e033-4274-b8ad-e1e5565eaf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482608793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1482608793
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.656688510
Short name T769
Test name
Test status
Simulation time 22166259 ps
CPU time 1.1 seconds
Started May 05 01:54:04 PM PDT 24
Finished May 05 01:54:06 PM PDT 24
Peak memory 215784 kb
Host smart-6e00f4cb-1d78-4826-bc33-9faee32199d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656688510 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.656688510
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3484453450
Short name T85
Test name
Test status
Simulation time 29322755 ps
CPU time 0.99 seconds
Started May 05 01:54:04 PM PDT 24
Finished May 05 01:54:06 PM PDT 24
Peak memory 215696 kb
Host smart-36e27fd3-a7cf-4d38-bff2-79188f9b5829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484453450 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3484453450
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3644742323
Short name T495
Test name
Test status
Simulation time 872468638 ps
CPU time 3.82 seconds
Started May 05 01:54:02 PM PDT 24
Finished May 05 01:54:06 PM PDT 24
Peak memory 217144 kb
Host smart-f3eb72af-1bcf-418c-b66b-d8ea82c52e96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644742323 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3644742323
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.191086370
Short name T454
Test name
Test status
Simulation time 10282774013 ps
CPU time 269.79 seconds
Started May 05 01:54:03 PM PDT 24
Finished May 05 01:58:33 PM PDT 24
Peak memory 219216 kb
Host smart-0f787bfe-14ec-4ade-a4bb-7261265b6ffc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191086370 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.191086370
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3053227503
Short name T370
Test name
Test status
Simulation time 37681231 ps
CPU time 1.28 seconds
Started May 05 01:54:13 PM PDT 24
Finished May 05 01:54:15 PM PDT 24
Peak memory 216044 kb
Host smart-575026f5-4525-425a-a696-b1b4f638e6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053227503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3053227503
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3277748052
Short name T789
Test name
Test status
Simulation time 26630138 ps
CPU time 0.9 seconds
Started May 05 01:54:11 PM PDT 24
Finished May 05 01:54:12 PM PDT 24
Peak memory 206948 kb
Host smart-e25ece66-236a-4071-a2ad-2d039962dd3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277748052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3277748052
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3887015011
Short name T189
Test name
Test status
Simulation time 56066341 ps
CPU time 0.82 seconds
Started May 05 01:54:06 PM PDT 24
Finished May 05 01:54:07 PM PDT 24
Peak memory 215796 kb
Host smart-196038bb-792f-4a96-9b50-08128530d87b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887015011 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3887015011
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3821177399
Short name T129
Test name
Test status
Simulation time 48823997 ps
CPU time 1.09 seconds
Started May 05 01:54:05 PM PDT 24
Finished May 05 01:54:06 PM PDT 24
Peak memory 217332 kb
Host smart-91b18824-9987-4f2c-838a-6d91aac355c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821177399 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3821177399
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3078458640
Short name T146
Test name
Test status
Simulation time 35643616 ps
CPU time 0.88 seconds
Started May 05 01:54:13 PM PDT 24
Finished May 05 01:54:14 PM PDT 24
Peak memory 218720 kb
Host smart-e2fb22a9-6762-45af-bca4-757f278c05bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078458640 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3078458640
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2419718949
Short name T286
Test name
Test status
Simulation time 27558769 ps
CPU time 1.09 seconds
Started May 05 01:54:07 PM PDT 24
Finished May 05 01:54:09 PM PDT 24
Peak memory 217520 kb
Host smart-98ab3e4f-ce37-4a9f-977d-50cccb283035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419718949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2419718949
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.2133503349
Short name T807
Test name
Test status
Simulation time 22178883 ps
CPU time 1.12 seconds
Started May 05 01:54:06 PM PDT 24
Finished May 05 01:54:08 PM PDT 24
Peak memory 216268 kb
Host smart-31fe3ce1-9d39-4cf4-b3e0-d7b27daf0d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133503349 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2133503349
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1815131245
Short name T533
Test name
Test status
Simulation time 16066490 ps
CPU time 1.06 seconds
Started May 05 01:54:05 PM PDT 24
Finished May 05 01:54:07 PM PDT 24
Peak memory 215808 kb
Host smart-58d8bd61-c018-4299-836d-a99f1cb77001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815131245 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1815131245
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3007502998
Short name T394
Test name
Test status
Simulation time 1087047218 ps
CPU time 3.16 seconds
Started May 05 01:54:04 PM PDT 24
Finished May 05 01:54:08 PM PDT 24
Peak memory 215624 kb
Host smart-a344681e-512d-4260-991b-00d47b82f991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007502998 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3007502998
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_alert.4056665105
Short name T166
Test name
Test status
Simulation time 44516746 ps
CPU time 1.26 seconds
Started May 05 01:54:05 PM PDT 24
Finished May 05 01:54:07 PM PDT 24
Peak memory 216060 kb
Host smart-906fee47-6b37-4a4e-b899-4138cc121995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056665105 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.4056665105
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3104316516
Short name T647
Test name
Test status
Simulation time 14260236 ps
CPU time 0.92 seconds
Started May 05 01:54:07 PM PDT 24
Finished May 05 01:54:08 PM PDT 24
Peak memory 206964 kb
Host smart-ec43dc21-4e7d-4ba5-b04f-2096aef78f0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104316516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3104316516
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2083113144
Short name T185
Test name
Test status
Simulation time 17822050 ps
CPU time 0.83 seconds
Started May 05 01:54:08 PM PDT 24
Finished May 05 01:54:09 PM PDT 24
Peak memory 216576 kb
Host smart-73525cc7-116f-4f16-a33e-4b5b8899509e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083113144 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2083113144
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2708437869
Short name T113
Test name
Test status
Simulation time 92034647 ps
CPU time 1.11 seconds
Started May 05 01:54:06 PM PDT 24
Finished May 05 01:54:08 PM PDT 24
Peak memory 217232 kb
Host smart-7363ede8-7141-4c72-9977-5a33ab9e393b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708437869 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2708437869
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2801837355
Short name T824
Test name
Test status
Simulation time 46393474 ps
CPU time 0.99 seconds
Started May 05 01:54:13 PM PDT 24
Finished May 05 01:54:15 PM PDT 24
Peak memory 218956 kb
Host smart-75333a1a-2885-45e8-a6e7-22be1f683730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801837355 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2801837355
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2427010085
Short name T320
Test name
Test status
Simulation time 53259489 ps
CPU time 1.21 seconds
Started May 05 01:54:07 PM PDT 24
Finished May 05 01:54:08 PM PDT 24
Peak memory 217320 kb
Host smart-c377afdb-d894-4d8e-82a0-c76450d51bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427010085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2427010085
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1668663651
Short name T43
Test name
Test status
Simulation time 20640014 ps
CPU time 0.96 seconds
Started May 05 01:54:13 PM PDT 24
Finished May 05 01:54:15 PM PDT 24
Peak memory 216204 kb
Host smart-5df58c11-dd9d-46ca-9a7a-15745501c1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668663651 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1668663651
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2450719022
Short name T752
Test name
Test status
Simulation time 37927177 ps
CPU time 0.93 seconds
Started May 05 01:54:07 PM PDT 24
Finished May 05 01:54:08 PM PDT 24
Peak memory 215524 kb
Host smart-c3b689fb-a858-40d0-b521-ac6690facebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450719022 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2450719022
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1409234928
Short name T576
Test name
Test status
Simulation time 846346902 ps
CPU time 4.53 seconds
Started May 05 01:54:13 PM PDT 24
Finished May 05 01:54:18 PM PDT 24
Peak memory 217212 kb
Host smart-48b26e4e-2a7e-4953-8357-94d282ff232c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409234928 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1409234928
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3285628007
Short name T457
Test name
Test status
Simulation time 24127905784 ps
CPU time 311.07 seconds
Started May 05 01:54:06 PM PDT 24
Finished May 05 01:59:18 PM PDT 24
Peak memory 218260 kb
Host smart-d4c18921-fb04-46de-a5d5-b5a7cbbc4811
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285628007 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3285628007
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1266071115
Short name T296
Test name
Test status
Simulation time 45235976 ps
CPU time 1.18 seconds
Started May 05 01:54:05 PM PDT 24
Finished May 05 01:54:07 PM PDT 24
Peak memory 216032 kb
Host smart-0589e9ca-2c33-452b-9510-15ad5cba65f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266071115 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1266071115
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3887180269
Short name T609
Test name
Test status
Simulation time 13941208 ps
CPU time 0.91 seconds
Started May 05 01:54:14 PM PDT 24
Finished May 05 01:54:16 PM PDT 24
Peak memory 206896 kb
Host smart-c1827f45-b1e3-4948-835b-3ddb632a4df5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887180269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3887180269
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.791089796
Short name T48
Test name
Test status
Simulation time 18215865 ps
CPU time 0.88 seconds
Started May 05 01:54:19 PM PDT 24
Finished May 05 01:54:21 PM PDT 24
Peak memory 216400 kb
Host smart-e72b4e90-48f7-4385-bc77-58df1eb8f9aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791089796 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.791089796
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.365476167
Short name T600
Test name
Test status
Simulation time 114840509 ps
CPU time 1.15 seconds
Started May 05 01:54:14 PM PDT 24
Finished May 05 01:54:16 PM PDT 24
Peak memory 217160 kb
Host smart-d08a854b-0816-4a09-8742-c458c774e5ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365476167 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.365476167
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2740371272
Short name T798
Test name
Test status
Simulation time 21164100 ps
CPU time 1.08 seconds
Started May 05 01:54:20 PM PDT 24
Finished May 05 01:54:21 PM PDT 24
Peak memory 218804 kb
Host smart-32dffb8c-f037-45a8-8efd-7ce51f722de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740371272 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2740371272
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1808943052
Short name T437
Test name
Test status
Simulation time 75122085 ps
CPU time 2.6 seconds
Started May 05 01:54:05 PM PDT 24
Finished May 05 01:54:08 PM PDT 24
Peak memory 219616 kb
Host smart-d8f4b2f5-a5de-4621-a412-076376bff3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808943052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1808943052
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.4279708103
Short name T783
Test name
Test status
Simulation time 28006050 ps
CPU time 1.03 seconds
Started May 05 01:54:09 PM PDT 24
Finished May 05 01:54:10 PM PDT 24
Peak memory 215952 kb
Host smart-6365e294-92d0-414b-88f0-41b7222d063e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279708103 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.4279708103
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1155268149
Short name T693
Test name
Test status
Simulation time 23278013 ps
CPU time 1.02 seconds
Started May 05 01:54:07 PM PDT 24
Finished May 05 01:54:08 PM PDT 24
Peak memory 215612 kb
Host smart-492a7d48-7b7e-40c6-af68-d55f4dd3c3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155268149 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1155268149
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3877394622
Short name T802
Test name
Test status
Simulation time 96368133 ps
CPU time 2.34 seconds
Started May 05 01:54:08 PM PDT 24
Finished May 05 01:54:11 PM PDT 24
Peak memory 215612 kb
Host smart-d0ceb9a2-bf07-4887-894e-104af4a2b32f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877394622 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3877394622
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3052104476
Short name T201
Test name
Test status
Simulation time 668434075583 ps
CPU time 1643.45 seconds
Started May 05 01:54:09 PM PDT 24
Finished May 05 02:21:33 PM PDT 24
Peak memory 224672 kb
Host smart-17cb904e-a296-4a8e-a09d-2a0ddd6e9bc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052104476 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3052104476
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.469639592
Short name T245
Test name
Test status
Simulation time 44029953 ps
CPU time 1.25 seconds
Started May 05 01:54:16 PM PDT 24
Finished May 05 01:54:19 PM PDT 24
Peak memory 216060 kb
Host smart-709d3e94-c665-43d6-ba70-ba1a98b2f4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469639592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.469639592
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2949653258
Short name T835
Test name
Test status
Simulation time 56180351 ps
CPU time 0.93 seconds
Started May 05 01:54:13 PM PDT 24
Finished May 05 01:54:15 PM PDT 24
Peak memory 206976 kb
Host smart-62e11533-51fe-4d84-9b9a-7ec3cbadd5b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949653258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2949653258
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3873758585
Short name T175
Test name
Test status
Simulation time 22751554 ps
CPU time 0.91 seconds
Started May 05 01:54:13 PM PDT 24
Finished May 05 01:54:15 PM PDT 24
Peak memory 216756 kb
Host smart-031ec9be-57b2-4b23-98dc-140028859332
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873758585 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3873758585
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3841968437
Short name T582
Test name
Test status
Simulation time 102621907 ps
CPU time 1.1 seconds
Started May 05 01:54:15 PM PDT 24
Finished May 05 01:54:17 PM PDT 24
Peak memory 217252 kb
Host smart-f67ec34d-e284-41cd-bda3-fe69c2bb9596
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841968437 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3841968437
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2068853065
Short name T811
Test name
Test status
Simulation time 31749198 ps
CPU time 0.95 seconds
Started May 05 01:54:12 PM PDT 24
Finished May 05 01:54:13 PM PDT 24
Peak memory 232916 kb
Host smart-189194f8-d776-4a96-b0d1-5edb8992d38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068853065 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2068853065
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1307255678
Short name T100
Test name
Test status
Simulation time 599682101 ps
CPU time 4.65 seconds
Started May 05 01:54:14 PM PDT 24
Finished May 05 01:54:20 PM PDT 24
Peak memory 220336 kb
Host smart-04c27d96-41c5-4b22-9b62-ef056cb8bdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307255678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1307255678
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1245449542
Short name T559
Test name
Test status
Simulation time 28955874 ps
CPU time 1.01 seconds
Started May 05 01:54:14 PM PDT 24
Finished May 05 01:54:16 PM PDT 24
Peak memory 215792 kb
Host smart-e339f42c-8fcf-4d68-bb48-0665e4051667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245449542 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1245449542
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.487416928
Short name T77
Test name
Test status
Simulation time 51809959 ps
CPU time 0.96 seconds
Started May 05 01:54:20 PM PDT 24
Finished May 05 01:54:21 PM PDT 24
Peak memory 215628 kb
Host smart-175d6661-528d-437f-85f4-60f826ed04a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487416928 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.487416928
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2660972019
Short name T843
Test name
Test status
Simulation time 67951840 ps
CPU time 1.04 seconds
Started May 05 01:54:12 PM PDT 24
Finished May 05 01:54:13 PM PDT 24
Peak memory 207308 kb
Host smart-ef75b826-8e22-4184-a810-0c49abd0a83e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660972019 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2660972019
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1636123071
Short name T507
Test name
Test status
Simulation time 248506565573 ps
CPU time 1675.52 seconds
Started May 05 01:54:13 PM PDT 24
Finished May 05 02:22:09 PM PDT 24
Peak memory 227560 kb
Host smart-393fd147-016e-43c5-8596-6cc747e74371
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636123071 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1636123071
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.2641280998
Short name T668
Test name
Test status
Simulation time 29330815 ps
CPU time 1.15 seconds
Started May 05 01:52:47 PM PDT 24
Finished May 05 01:52:49 PM PDT 24
Peak memory 216076 kb
Host smart-c18c16ea-d8ba-4a34-9f22-bc057906cda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641280998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2641280998
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3301820495
Short name T368
Test name
Test status
Simulation time 115798024 ps
CPU time 0.92 seconds
Started May 05 01:52:48 PM PDT 24
Finished May 05 01:52:49 PM PDT 24
Peak memory 206812 kb
Host smart-6fceb858-994f-44b7-865c-4485841cd29d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301820495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3301820495
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1159200162
Short name T622
Test name
Test status
Simulation time 21573756 ps
CPU time 0.86 seconds
Started May 05 01:52:46 PM PDT 24
Finished May 05 01:52:48 PM PDT 24
Peak memory 216772 kb
Host smart-50e1144c-11d7-4f1d-9364-355c1c61cbad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159200162 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1159200162
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2945737160
Short name T21
Test name
Test status
Simulation time 31688504 ps
CPU time 1.22 seconds
Started May 05 01:52:47 PM PDT 24
Finished May 05 01:52:49 PM PDT 24
Peak memory 217116 kb
Host smart-ffeaf378-e8c3-4296-9991-ffe11ecbe03a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945737160 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2945737160
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3025686855
Short name T839
Test name
Test status
Simulation time 19647825 ps
CPU time 1.05 seconds
Started May 05 01:52:49 PM PDT 24
Finished May 05 01:52:50 PM PDT 24
Peak memory 218948 kb
Host smart-79795a0f-7ea6-4002-95b3-d0116c850b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025686855 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3025686855
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.797978531
Short name T592
Test name
Test status
Simulation time 31288960 ps
CPU time 1.25 seconds
Started May 05 01:52:47 PM PDT 24
Finished May 05 01:52:49 PM PDT 24
Peak memory 217472 kb
Host smart-94b04719-e5f3-4017-9d16-cf28657b4481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797978531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.797978531
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2496506181
Short name T695
Test name
Test status
Simulation time 33396904 ps
CPU time 0.88 seconds
Started May 05 01:52:47 PM PDT 24
Finished May 05 01:52:49 PM PDT 24
Peak memory 215640 kb
Host smart-8097e03d-2849-4658-aadd-64e920518ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496506181 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2496506181
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_smoke.570916093
Short name T672
Test name
Test status
Simulation time 17174234 ps
CPU time 1.01 seconds
Started May 05 01:52:46 PM PDT 24
Finished May 05 01:52:48 PM PDT 24
Peak memory 215548 kb
Host smart-2e007308-32cc-4db1-b6ca-77712a5f0d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570916093 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.570916093
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2509118437
Short name T775
Test name
Test status
Simulation time 343499705 ps
CPU time 6.63 seconds
Started May 05 01:52:46 PM PDT 24
Finished May 05 01:52:53 PM PDT 24
Peak memory 220012 kb
Host smart-27348f6a-d420-420d-99d0-b26bd96e44b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509118437 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2509118437
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.4227132887
Short name T558
Test name
Test status
Simulation time 7485516986 ps
CPU time 192.39 seconds
Started May 05 01:52:46 PM PDT 24
Finished May 05 01:55:58 PM PDT 24
Peak memory 222320 kb
Host smart-91f46a6d-fac6-42d6-a6b2-e8eaf40e2884
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227132887 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.4227132887
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.3501023094
Short name T183
Test name
Test status
Simulation time 46008698 ps
CPU time 0.98 seconds
Started May 05 01:54:12 PM PDT 24
Finished May 05 01:54:14 PM PDT 24
Peak memory 220208 kb
Host smart-aa482d79-cbbc-4d86-b18c-6d4bbddc0684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501023094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3501023094
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1736531931
Short name T785
Test name
Test status
Simulation time 154640042 ps
CPU time 3.39 seconds
Started May 05 01:54:13 PM PDT 24
Finished May 05 01:54:17 PM PDT 24
Peak memory 220140 kb
Host smart-6b82fe20-3982-4bb7-8898-07d8675959f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736531931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1736531931
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.3432756140
Short name T818
Test name
Test status
Simulation time 29495048 ps
CPU time 1.02 seconds
Started May 05 01:54:18 PM PDT 24
Finished May 05 01:54:20 PM PDT 24
Peak memory 224216 kb
Host smart-22cf9c17-1c10-4b0c-8854-68f04399116e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432756140 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3432756140
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.36880643
Short name T421
Test name
Test status
Simulation time 594134458 ps
CPU time 3.57 seconds
Started May 05 01:54:11 PM PDT 24
Finished May 05 01:54:16 PM PDT 24
Peak memory 219844 kb
Host smart-5b05e203-fddc-4def-9aa0-d2ae12aa6050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36880643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.36880643
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_genbits.523732289
Short name T408
Test name
Test status
Simulation time 239705107 ps
CPU time 1.13 seconds
Started May 05 01:54:14 PM PDT 24
Finished May 05 01:54:16 PM PDT 24
Peak memory 217252 kb
Host smart-c514a277-5022-460f-9366-b0f103ca27cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523732289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.523732289
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.4098901200
Short name T804
Test name
Test status
Simulation time 34287743 ps
CPU time 0.87 seconds
Started May 05 01:54:20 PM PDT 24
Finished May 05 01:54:21 PM PDT 24
Peak memory 218776 kb
Host smart-5c524918-a50b-42ad-9593-bd93428dc37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098901200 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.4098901200
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.448449861
Short name T841
Test name
Test status
Simulation time 54292730 ps
CPU time 1.35 seconds
Started May 05 01:54:15 PM PDT 24
Finished May 05 01:54:17 PM PDT 24
Peak memory 218528 kb
Host smart-c46eed18-9a78-4764-8578-9b95807cec45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448449861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.448449861
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.3767319252
Short name T658
Test name
Test status
Simulation time 54848384 ps
CPU time 1.08 seconds
Started May 05 01:54:13 PM PDT 24
Finished May 05 01:54:14 PM PDT 24
Peak memory 220436 kb
Host smart-a183e28c-fac5-4d01-ae88-8ff7813e7ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767319252 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3767319252
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2932873809
Short name T624
Test name
Test status
Simulation time 69221605 ps
CPU time 1.27 seconds
Started May 05 01:54:15 PM PDT 24
Finished May 05 01:54:17 PM PDT 24
Peak memory 217616 kb
Host smart-45f95567-0bdf-405f-b667-365f83ef9ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932873809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2932873809
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.3939893188
Short name T111
Test name
Test status
Simulation time 194472189 ps
CPU time 1 seconds
Started May 05 01:54:12 PM PDT 24
Finished May 05 01:54:14 PM PDT 24
Peak memory 217708 kb
Host smart-40495ad5-a487-4bee-ab45-8c9abb78e197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939893188 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3939893188
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3063658990
Short name T688
Test name
Test status
Simulation time 91495236 ps
CPU time 1.55 seconds
Started May 05 01:54:13 PM PDT 24
Finished May 05 01:54:15 PM PDT 24
Peak memory 219048 kb
Host smart-bd3bfab4-d7c3-4ae1-865f-f1bf2d6a29f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063658990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3063658990
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.1571489266
Short name T182
Test name
Test status
Simulation time 20663063 ps
CPU time 1.15 seconds
Started May 05 01:54:20 PM PDT 24
Finished May 05 01:54:22 PM PDT 24
Peak memory 220284 kb
Host smart-335d4d2c-99fd-459a-ba4e-09f213cbc0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571489266 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1571489266
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2789981549
Short name T614
Test name
Test status
Simulation time 36340308 ps
CPU time 1.49 seconds
Started May 05 01:54:16 PM PDT 24
Finished May 05 01:54:19 PM PDT 24
Peak memory 219928 kb
Host smart-fe103f2f-6e2d-447f-8ec8-a5f612dfd33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789981549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2789981549
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2016873335
Short name T625
Test name
Test status
Simulation time 29763301 ps
CPU time 1.28 seconds
Started May 05 01:54:17 PM PDT 24
Finished May 05 01:54:19 PM PDT 24
Peak memory 220144 kb
Host smart-9140be58-9687-4ad4-a0f9-1f0e2826a583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016873335 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2016873335
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3210566763
Short name T607
Test name
Test status
Simulation time 33094920 ps
CPU time 1.3 seconds
Started May 05 01:54:16 PM PDT 24
Finished May 05 01:54:18 PM PDT 24
Peak memory 220140 kb
Host smart-89c5e21b-2791-48ca-9c50-ba40deae63ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210566763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3210566763
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.748934466
Short name T134
Test name
Test status
Simulation time 20305747 ps
CPU time 1.25 seconds
Started May 05 01:54:18 PM PDT 24
Finished May 05 01:54:20 PM PDT 24
Peak memory 224416 kb
Host smart-8bef3c26-06eb-458f-9128-9fbc130ee934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748934466 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.748934466
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3119718581
Short name T568
Test name
Test status
Simulation time 98615729 ps
CPU time 1.11 seconds
Started May 05 01:54:19 PM PDT 24
Finished May 05 01:54:20 PM PDT 24
Peak memory 217500 kb
Host smart-3eb2d2c5-06cb-4b0c-a49e-56067274bfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119718581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3119718581
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.3234607111
Short name T73
Test name
Test status
Simulation time 20847870 ps
CPU time 1.14 seconds
Started May 05 01:54:17 PM PDT 24
Finished May 05 01:54:19 PM PDT 24
Peak memory 220612 kb
Host smart-9d8bc868-9b30-445d-a59f-f57a83db0f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234607111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3234607111
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/6.edn_alert.82333442
Short name T594
Test name
Test status
Simulation time 44402386 ps
CPU time 1.21 seconds
Started May 05 01:52:50 PM PDT 24
Finished May 05 01:52:52 PM PDT 24
Peak memory 216040 kb
Host smart-a75a86fa-9f4e-43bc-9efe-881377662178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82333442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.82333442
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.633120717
Short name T521
Test name
Test status
Simulation time 64928655 ps
CPU time 0.82 seconds
Started May 05 01:52:51 PM PDT 24
Finished May 05 01:52:52 PM PDT 24
Peak memory 207212 kb
Host smart-47c71f7d-2c5d-4ded-9f32-66e14dbc0947
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633120717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.633120717
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1876098637
Short name T98
Test name
Test status
Simulation time 32287374 ps
CPU time 0.82 seconds
Started May 05 01:52:51 PM PDT 24
Finished May 05 01:52:53 PM PDT 24
Peak memory 216616 kb
Host smart-c75b3c71-b9aa-4f90-942f-fb17cbd27905
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876098637 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1876098637
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_err.3709294977
Short name T513
Test name
Test status
Simulation time 52045334 ps
CPU time 1.02 seconds
Started May 05 01:52:50 PM PDT 24
Finished May 05 01:52:51 PM PDT 24
Peak memory 230000 kb
Host smart-7446e731-0c6f-460d-bc26-1a2280c906b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709294977 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3709294977
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3906334397
Short name T760
Test name
Test status
Simulation time 49349785 ps
CPU time 1.17 seconds
Started May 05 01:52:49 PM PDT 24
Finished May 05 01:52:51 PM PDT 24
Peak memory 217280 kb
Host smart-27289ed2-5587-47bc-8f62-f5f8745ce17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906334397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3906334397
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3392252460
Short name T162
Test name
Test status
Simulation time 21520020 ps
CPU time 0.97 seconds
Started May 05 01:52:51 PM PDT 24
Finished May 05 01:52:53 PM PDT 24
Peak memory 216248 kb
Host smart-58264345-0431-4244-9767-50380d2ad0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392252460 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3392252460
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1720826129
Short name T292
Test name
Test status
Simulation time 35227341 ps
CPU time 0.89 seconds
Started May 05 01:52:46 PM PDT 24
Finished May 05 01:52:47 PM PDT 24
Peak memory 207404 kb
Host smart-ec304128-f108-4517-80b6-ffeb36eb246d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720826129 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1720826129
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3966374200
Short name T605
Test name
Test status
Simulation time 19778638 ps
CPU time 1.05 seconds
Started May 05 01:52:48 PM PDT 24
Finished May 05 01:52:49 PM PDT 24
Peak memory 215624 kb
Host smart-d22c2025-fd6d-4721-b111-1c1922647c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966374200 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3966374200
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3315588610
Short name T548
Test name
Test status
Simulation time 95566525 ps
CPU time 2.38 seconds
Started May 05 01:52:50 PM PDT 24
Finished May 05 01:52:53 PM PDT 24
Peak memory 217428 kb
Host smart-163628b0-9678-4829-b819-396913aab448
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315588610 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3315588610
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.4220709021
Short name T196
Test name
Test status
Simulation time 97557747982 ps
CPU time 755.65 seconds
Started May 05 01:52:50 PM PDT 24
Finished May 05 02:05:27 PM PDT 24
Peak memory 220380 kb
Host smart-7d1c58ab-91a6-4cae-a5cc-e67980361309
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220709021 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.4220709021
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.1579059463
Short name T352
Test name
Test status
Simulation time 27008827 ps
CPU time 0.86 seconds
Started May 05 01:54:17 PM PDT 24
Finished May 05 01:54:19 PM PDT 24
Peak memory 218476 kb
Host smart-a0be5684-9ff9-4ff3-ad50-96c3d0bf28c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579059463 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1579059463
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3128300481
Short name T570
Test name
Test status
Simulation time 45983555 ps
CPU time 1.51 seconds
Started May 05 01:54:19 PM PDT 24
Finished May 05 01:54:22 PM PDT 24
Peak memory 218368 kb
Host smart-7dd4e306-745f-4a70-a73c-d70a2c115fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128300481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3128300481
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.2195763675
Short name T483
Test name
Test status
Simulation time 17799493 ps
CPU time 1.03 seconds
Started May 05 01:54:16 PM PDT 24
Finished May 05 01:54:18 PM PDT 24
Peak memory 218716 kb
Host smart-4d1b58f8-ea4c-4268-a750-216de9502be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195763675 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2195763675
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2105421293
Short name T316
Test name
Test status
Simulation time 33737619 ps
CPU time 1.19 seconds
Started May 05 01:54:19 PM PDT 24
Finished May 05 01:54:21 PM PDT 24
Peak memory 218900 kb
Host smart-a23f741b-244a-4c27-8f18-100ca7f2b1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105421293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2105421293
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.53408241
Short name T114
Test name
Test status
Simulation time 34621689 ps
CPU time 1.09 seconds
Started May 05 01:54:16 PM PDT 24
Finished May 05 01:54:18 PM PDT 24
Peak memory 220824 kb
Host smart-d60e01aa-3dac-46aa-92b8-3a58ab0dd260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53408241 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.53408241
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1376292570
Short name T428
Test name
Test status
Simulation time 57467035 ps
CPU time 1.1 seconds
Started May 05 01:54:18 PM PDT 24
Finished May 05 01:54:20 PM PDT 24
Peak memory 218984 kb
Host smart-57585f4a-a84c-4936-8790-afff1b651916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376292570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1376292570
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.868747772
Short name T154
Test name
Test status
Simulation time 43315171 ps
CPU time 0.96 seconds
Started May 05 01:54:19 PM PDT 24
Finished May 05 01:54:21 PM PDT 24
Peak memory 224240 kb
Host smart-3270935f-5b99-4c65-b6fc-5ca347b31b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868747772 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.868747772
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.802100885
Short name T635
Test name
Test status
Simulation time 29054172 ps
CPU time 1.23 seconds
Started May 05 01:54:18 PM PDT 24
Finished May 05 01:54:20 PM PDT 24
Peak memory 218504 kb
Host smart-3b6d345d-656b-44fb-a521-d74716a62625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802100885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.802100885
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.4234678467
Short name T596
Test name
Test status
Simulation time 20433671 ps
CPU time 1.17 seconds
Started May 05 01:54:18 PM PDT 24
Finished May 05 01:54:20 PM PDT 24
Peak memory 219884 kb
Host smart-e6893c68-8a8a-470e-be3e-794b0ee693e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234678467 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.4234678467
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.346326002
Short name T436
Test name
Test status
Simulation time 74672238 ps
CPU time 1.12 seconds
Started May 05 01:54:15 PM PDT 24
Finished May 05 01:54:17 PM PDT 24
Peak memory 220092 kb
Host smart-2a515686-bc4a-49f4-815b-ce854435fa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346326002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.346326002
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.730941679
Short name T181
Test name
Test status
Simulation time 18258913 ps
CPU time 1.09 seconds
Started May 05 01:54:15 PM PDT 24
Finished May 05 01:54:17 PM PDT 24
Peak memory 218940 kb
Host smart-556c1e88-df00-4e69-a3a8-321821c02a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730941679 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.730941679
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1882070821
Short name T280
Test name
Test status
Simulation time 28456632 ps
CPU time 1.17 seconds
Started May 05 01:54:15 PM PDT 24
Finished May 05 01:54:17 PM PDT 24
Peak memory 219888 kb
Host smart-229122d8-217a-496a-a545-60294b806218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882070821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1882070821
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.1987930677
Short name T5
Test name
Test status
Simulation time 23234484 ps
CPU time 1.15 seconds
Started May 05 01:54:18 PM PDT 24
Finished May 05 01:54:20 PM PDT 24
Peak memory 219084 kb
Host smart-ac48e767-f8d1-4014-8410-4d96f57f71fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987930677 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1987930677
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.4088474336
Short name T838
Test name
Test status
Simulation time 39007201 ps
CPU time 1.28 seconds
Started May 05 01:54:20 PM PDT 24
Finished May 05 01:54:22 PM PDT 24
Peak memory 217344 kb
Host smart-dc7ea14c-c1b9-4e87-bfab-707d79f28f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088474336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.4088474336
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.1281122199
Short name T356
Test name
Test status
Simulation time 55661446 ps
CPU time 0.87 seconds
Started May 05 01:54:17 PM PDT 24
Finished May 05 01:54:19 PM PDT 24
Peak memory 218656 kb
Host smart-7b465a53-d499-4b95-adad-57cf2ac3e63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281122199 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1281122199
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3299767961
Short name T300
Test name
Test status
Simulation time 54497631 ps
CPU time 1.28 seconds
Started May 05 01:54:15 PM PDT 24
Finished May 05 01:54:18 PM PDT 24
Peak memory 218724 kb
Host smart-3e7a0d28-7632-42f0-89ee-d5e15ca777ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299767961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3299767961
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.3899938014
Short name T109
Test name
Test status
Simulation time 33637909 ps
CPU time 0.92 seconds
Started May 05 01:54:17 PM PDT 24
Finished May 05 01:54:19 PM PDT 24
Peak memory 219824 kb
Host smart-cf40ca17-7045-47fa-9e57-5b140f9988ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899938014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3899938014
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1693412806
Short name T328
Test name
Test status
Simulation time 209513016 ps
CPU time 1.11 seconds
Started May 05 01:54:16 PM PDT 24
Finished May 05 01:54:18 PM PDT 24
Peak memory 217376 kb
Host smart-74e3469c-2f9c-4189-971b-51507b9de576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693412806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1693412806
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.377264142
Short name T667
Test name
Test status
Simulation time 21717899 ps
CPU time 1.04 seconds
Started May 05 01:54:19 PM PDT 24
Finished May 05 01:54:21 PM PDT 24
Peak memory 218996 kb
Host smart-a1aa3abf-13bd-4d64-a71d-33035cf38060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377264142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.377264142
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1423367801
Short name T842
Test name
Test status
Simulation time 38215145 ps
CPU time 1.49 seconds
Started May 05 01:54:16 PM PDT 24
Finished May 05 01:54:18 PM PDT 24
Peak memory 218412 kb
Host smart-b3a6d81e-41ff-4182-8df4-3bf260d48ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423367801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1423367801
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2586526255
Short name T259
Test name
Test status
Simulation time 23577151 ps
CPU time 1.25 seconds
Started May 05 01:52:53 PM PDT 24
Finished May 05 01:52:55 PM PDT 24
Peak memory 215976 kb
Host smart-6e228e98-dae3-492c-a20c-8eae9e707d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586526255 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2586526255
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.313833098
Short name T304
Test name
Test status
Simulation time 25665455 ps
CPU time 0.97 seconds
Started May 05 01:52:56 PM PDT 24
Finished May 05 01:52:58 PM PDT 24
Peak memory 207332 kb
Host smart-8acdf1e5-1992-49e0-8502-0e21b15f05ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313833098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.313833098
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3759512141
Short name T173
Test name
Test status
Simulation time 13010666 ps
CPU time 0.94 seconds
Started May 05 01:52:51 PM PDT 24
Finished May 05 01:52:52 PM PDT 24
Peak memory 216000 kb
Host smart-edb32fd7-d70c-4b91-a086-1b834b86563b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759512141 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3759512141
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.188505165
Short name T430
Test name
Test status
Simulation time 47928707 ps
CPU time 1.16 seconds
Started May 05 01:52:54 PM PDT 24
Finished May 05 01:52:56 PM PDT 24
Peak memory 219780 kb
Host smart-4438bb4f-49ce-4bb3-8d3f-49a4e5057124
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188505165 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.188505165
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2152135650
Short name T464
Test name
Test status
Simulation time 19881912 ps
CPU time 0.98 seconds
Started May 05 01:52:51 PM PDT 24
Finished May 05 01:52:52 PM PDT 24
Peak memory 218748 kb
Host smart-2f9c7f42-3574-4abd-a4da-e3cf92140009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152135650 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2152135650
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2658332765
Short name T779
Test name
Test status
Simulation time 33173194 ps
CPU time 1.32 seconds
Started May 05 01:52:51 PM PDT 24
Finished May 05 01:52:53 PM PDT 24
Peak memory 219464 kb
Host smart-b4914f24-74a5-47eb-9ed6-00ff591b29dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658332765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2658332765
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.98477607
Short name T443
Test name
Test status
Simulation time 22183684 ps
CPU time 1.12 seconds
Started May 05 01:52:53 PM PDT 24
Finished May 05 01:52:54 PM PDT 24
Peak memory 215788 kb
Host smart-66fa52f6-017f-4312-9505-7f79206071d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98477607 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.98477607
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2713426290
Short name T29
Test name
Test status
Simulation time 29107694 ps
CPU time 0.94 seconds
Started May 05 01:52:52 PM PDT 24
Finished May 05 01:52:54 PM PDT 24
Peak memory 207408 kb
Host smart-d90747de-7e2d-4367-ba82-dd76f7e4dc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713426290 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2713426290
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.941014542
Short name T416
Test name
Test status
Simulation time 19958111 ps
CPU time 1.02 seconds
Started May 05 01:52:51 PM PDT 24
Finished May 05 01:52:53 PM PDT 24
Peak memory 215620 kb
Host smart-30b1b283-835c-40d9-adf2-0c8702d42e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941014542 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.941014542
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.4127901007
Short name T675
Test name
Test status
Simulation time 376683604 ps
CPU time 3.15 seconds
Started May 05 01:52:51 PM PDT 24
Finished May 05 01:52:55 PM PDT 24
Peak memory 217240 kb
Host smart-e27f9185-ddd6-4761-83b0-cff8f21b226e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127901007 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4127901007
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.768023376
Short name T748
Test name
Test status
Simulation time 71187780102 ps
CPU time 463.57 seconds
Started May 05 01:52:50 PM PDT 24
Finished May 05 02:00:34 PM PDT 24
Peak memory 219468 kb
Host smart-54ee2b83-6221-488d-a868-3d0a4d634d06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768023376 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.768023376
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.955068100
Short name T661
Test name
Test status
Simulation time 36205667 ps
CPU time 1.01 seconds
Started May 05 01:54:16 PM PDT 24
Finished May 05 01:54:18 PM PDT 24
Peak memory 220160 kb
Host smart-a6af3c66-d9fa-41da-8976-7aa5150ef5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955068100 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.955068100
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3270809932
Short name T673
Test name
Test status
Simulation time 137657496 ps
CPU time 1.79 seconds
Started May 05 01:54:17 PM PDT 24
Finished May 05 01:54:20 PM PDT 24
Peak memory 219164 kb
Host smart-75b9a91c-435d-4815-a94d-ce4d2e138cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270809932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3270809932
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.3134292438
Short name T628
Test name
Test status
Simulation time 22393869 ps
CPU time 1.03 seconds
Started May 05 01:54:18 PM PDT 24
Finished May 05 01:54:20 PM PDT 24
Peak memory 224192 kb
Host smart-019c20bf-3f50-496c-aaec-0a1884677610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134292438 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3134292438
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.247568104
Short name T626
Test name
Test status
Simulation time 185576397 ps
CPU time 2.68 seconds
Started May 05 01:54:17 PM PDT 24
Finished May 05 01:54:21 PM PDT 24
Peak memory 220260 kb
Host smart-f34b1453-01ec-473b-97c0-38b8e65a0918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247568104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.247568104
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.3549261162
Short name T150
Test name
Test status
Simulation time 18725387 ps
CPU time 1.11 seconds
Started May 05 01:54:24 PM PDT 24
Finished May 05 01:54:26 PM PDT 24
Peak memory 218824 kb
Host smart-ad7c945c-3669-414e-bb7c-72b353b34d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549261162 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3549261162
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1320755904
Short name T323
Test name
Test status
Simulation time 29910104 ps
CPU time 1.3 seconds
Started May 05 01:54:16 PM PDT 24
Finished May 05 01:54:18 PM PDT 24
Peak memory 219948 kb
Host smart-358b9fe0-8b4d-46a5-8450-9c131ea58a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320755904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1320755904
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.1678056596
Short name T116
Test name
Test status
Simulation time 25005819 ps
CPU time 1.17 seconds
Started May 05 01:54:24 PM PDT 24
Finished May 05 01:54:26 PM PDT 24
Peak memory 230020 kb
Host smart-64cb14d5-3f21-4610-acec-90c237001df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678056596 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1678056596
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.403331833
Short name T102
Test name
Test status
Simulation time 78752622 ps
CPU time 1.81 seconds
Started May 05 01:54:21 PM PDT 24
Finished May 05 01:54:24 PM PDT 24
Peak memory 220092 kb
Host smart-1cf3baf1-c943-453a-a09b-db781a455d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403331833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.403331833
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.2427968288
Short name T805
Test name
Test status
Simulation time 21588563 ps
CPU time 0.93 seconds
Started May 05 01:54:23 PM PDT 24
Finished May 05 01:54:24 PM PDT 24
Peak memory 218708 kb
Host smart-61ff5691-19db-4f8c-9751-fb6d2f6087b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427968288 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2427968288
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.4224030826
Short name T782
Test name
Test status
Simulation time 42187868 ps
CPU time 1.46 seconds
Started May 05 01:54:22 PM PDT 24
Finished May 05 01:54:24 PM PDT 24
Peak memory 217348 kb
Host smart-2c9d6e41-db78-4fc1-9be6-ad65c27151a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224030826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.4224030826
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.1467282121
Short name T122
Test name
Test status
Simulation time 23102871 ps
CPU time 1.22 seconds
Started May 05 01:54:22 PM PDT 24
Finished May 05 01:54:23 PM PDT 24
Peak memory 224412 kb
Host smart-4661c8b7-cbf9-42ff-bfcc-eb2bffc039b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467282121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1467282121
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.108685669
Short name T324
Test name
Test status
Simulation time 34575040 ps
CPU time 1.05 seconds
Started May 05 01:54:21 PM PDT 24
Finished May 05 01:54:22 PM PDT 24
Peak memory 217204 kb
Host smart-5eba4964-060d-44c7-8ba1-c7619def6401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108685669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.108685669
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.4150487290
Short name T151
Test name
Test status
Simulation time 18290834 ps
CPU time 1.13 seconds
Started May 05 01:54:21 PM PDT 24
Finished May 05 01:54:23 PM PDT 24
Peak memory 224444 kb
Host smart-305d13d1-d141-4103-b42d-a0a766770359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150487290 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.4150487290
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1970057348
Short name T776
Test name
Test status
Simulation time 76105480 ps
CPU time 1.01 seconds
Started May 05 01:54:21 PM PDT 24
Finished May 05 01:54:22 PM PDT 24
Peak memory 218392 kb
Host smart-2914f79e-6a43-45eb-a577-345181bca4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970057348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1970057348
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.2373374013
Short name T118
Test name
Test status
Simulation time 170019595 ps
CPU time 1 seconds
Started May 05 01:54:22 PM PDT 24
Finished May 05 01:54:23 PM PDT 24
Peak memory 220184 kb
Host smart-f9727001-3468-466b-99ed-2c616632db42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373374013 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2373374013
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.430494398
Short name T326
Test name
Test status
Simulation time 44876906 ps
CPU time 1.18 seconds
Started May 05 01:54:21 PM PDT 24
Finished May 05 01:54:22 PM PDT 24
Peak memory 217288 kb
Host smart-c4ac051b-4215-48c3-a2c2-36a78b7319d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430494398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.430494398
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.3717983005
Short name T840
Test name
Test status
Simulation time 22788133 ps
CPU time 0.95 seconds
Started May 05 01:54:22 PM PDT 24
Finished May 05 01:54:24 PM PDT 24
Peak memory 218508 kb
Host smart-c20d6d95-2e55-47ea-8c26-f0ce1689467c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717983005 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3717983005
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.4025560983
Short name T498
Test name
Test status
Simulation time 47056104 ps
CPU time 1.16 seconds
Started May 05 01:54:22 PM PDT 24
Finished May 05 01:54:24 PM PDT 24
Peak memory 217408 kb
Host smart-fc02ca05-14a9-4832-a214-8ac77ed89e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025560983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.4025560983
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.235113512
Short name T65
Test name
Test status
Simulation time 63343205 ps
CPU time 1.12 seconds
Started May 05 01:54:22 PM PDT 24
Finished May 05 01:54:24 PM PDT 24
Peak memory 230172 kb
Host smart-45025fa4-e289-4d71-ace8-8098afd192ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235113512 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.235113512
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2119779706
Short name T795
Test name
Test status
Simulation time 298943771 ps
CPU time 3.15 seconds
Started May 05 01:54:23 PM PDT 24
Finished May 05 01:54:26 PM PDT 24
Peak memory 217616 kb
Host smart-5cc9e229-46a0-47da-be81-4b62f89306bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119779706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2119779706
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2619388139
Short name T520
Test name
Test status
Simulation time 168688004 ps
CPU time 1.33 seconds
Started May 05 01:52:56 PM PDT 24
Finished May 05 01:52:57 PM PDT 24
Peak memory 216076 kb
Host smart-ce462698-8d57-401c-9e31-791a3273a90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619388139 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2619388139
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.181058307
Short name T213
Test name
Test status
Simulation time 16696564 ps
CPU time 0.95 seconds
Started May 05 01:52:59 PM PDT 24
Finished May 05 01:53:00 PM PDT 24
Peak memory 206988 kb
Host smart-9d3c5524-4cfe-49df-ae89-bcf3a8610b13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181058307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.181058307
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2609698960
Short name T678
Test name
Test status
Simulation time 21465907 ps
CPU time 0.9 seconds
Started May 05 01:52:57 PM PDT 24
Finished May 05 01:52:58 PM PDT 24
Peak memory 216240 kb
Host smart-3f0aab01-9f25-4f5b-8f78-13c9be65ed46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609698960 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2609698960
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3665514221
Short name T731
Test name
Test status
Simulation time 22392904 ps
CPU time 0.98 seconds
Started May 05 01:52:56 PM PDT 24
Finished May 05 01:52:58 PM PDT 24
Peak memory 218240 kb
Host smart-1ff1747f-95ec-4b5e-a236-e7e5fb2dd435
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665514221 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3665514221
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.4001780091
Short name T84
Test name
Test status
Simulation time 33723045 ps
CPU time 0.91 seconds
Started May 05 01:52:56 PM PDT 24
Finished May 05 01:52:57 PM PDT 24
Peak memory 218540 kb
Host smart-6b5843ba-d124-4878-b01d-6916714c3b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001780091 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.4001780091
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.2589978536
Short name T497
Test name
Test status
Simulation time 114234733 ps
CPU time 1.5 seconds
Started May 05 01:52:55 PM PDT 24
Finished May 05 01:52:57 PM PDT 24
Peak memory 218632 kb
Host smart-2de0459e-2ded-49a2-bf92-584589700723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589978536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2589978536
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.846283727
Short name T774
Test name
Test status
Simulation time 44882229 ps
CPU time 0.97 seconds
Started May 05 01:52:57 PM PDT 24
Finished May 05 01:52:58 PM PDT 24
Peak memory 216284 kb
Host smart-6600310c-191c-4365-910f-a90ef7a8ce1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846283727 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.846283727
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1627955792
Short name T299
Test name
Test status
Simulation time 127190175 ps
CPU time 0.97 seconds
Started May 05 01:52:56 PM PDT 24
Finished May 05 01:52:57 PM PDT 24
Peak memory 207588 kb
Host smart-2f746018-6d3b-4ab0-83de-f72cad9d3384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627955792 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1627955792
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2014427850
Short name T81
Test name
Test status
Simulation time 16249550 ps
CPU time 0.98 seconds
Started May 05 01:52:55 PM PDT 24
Finished May 05 01:52:57 PM PDT 24
Peak memory 215536 kb
Host smart-893d37d6-2be7-457a-9f49-67979fd8303c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014427850 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2014427850
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2386373710
Short name T656
Test name
Test status
Simulation time 427995934 ps
CPU time 6.91 seconds
Started May 05 01:52:56 PM PDT 24
Finished May 05 01:53:04 PM PDT 24
Peak memory 218496 kb
Host smart-bf5268a2-78d5-4051-ba37-a326a73ea5fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386373710 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2386373710
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.809165436
Short name T354
Test name
Test status
Simulation time 179520600349 ps
CPU time 1179.75 seconds
Started May 05 01:52:55 PM PDT 24
Finished May 05 02:12:36 PM PDT 24
Peak memory 224660 kb
Host smart-3161e8be-d841-4a9b-9086-3ed8ccb444b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809165436 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.809165436
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.561947882
Short name T117
Test name
Test status
Simulation time 34275652 ps
CPU time 1.12 seconds
Started May 05 01:54:21 PM PDT 24
Finished May 05 01:54:23 PM PDT 24
Peak memory 221020 kb
Host smart-19fb0791-2816-4bd9-9055-382fee5cdb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561947882 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.561947882
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2000990454
Short name T275
Test name
Test status
Simulation time 91404373 ps
CPU time 1.98 seconds
Started May 05 01:54:23 PM PDT 24
Finished May 05 01:54:26 PM PDT 24
Peak memory 218588 kb
Host smart-d3498aee-434e-47aa-8b56-68942d2e90e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000990454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2000990454
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.3959805796
Short name T121
Test name
Test status
Simulation time 81454461 ps
CPU time 1.05 seconds
Started May 05 01:54:27 PM PDT 24
Finished May 05 01:54:29 PM PDT 24
Peak memory 224516 kb
Host smart-0a85f916-f72f-4a91-8474-d281b94b097c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959805796 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3959805796
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2212780153
Short name T616
Test name
Test status
Simulation time 74753180 ps
CPU time 1.33 seconds
Started May 05 01:54:23 PM PDT 24
Finished May 05 01:54:25 PM PDT 24
Peak memory 218920 kb
Host smart-9b74b657-d0e2-4043-a655-3fc4c183c9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212780153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2212780153
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.1974361412
Short name T120
Test name
Test status
Simulation time 59449185 ps
CPU time 1 seconds
Started May 05 01:54:27 PM PDT 24
Finished May 05 01:54:29 PM PDT 24
Peak memory 219040 kb
Host smart-1854e532-a1ba-4f29-8f4e-aabc2a746b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974361412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1974361412
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2855367150
Short name T663
Test name
Test status
Simulation time 61122677 ps
CPU time 1.88 seconds
Started May 05 01:54:29 PM PDT 24
Finished May 05 01:54:32 PM PDT 24
Peak memory 218508 kb
Host smart-f6e3c165-6b11-473c-853b-228b12662be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855367150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2855367150
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.2753996734
Short name T585
Test name
Test status
Simulation time 33788410 ps
CPU time 0.84 seconds
Started May 05 01:54:34 PM PDT 24
Finished May 05 01:54:35 PM PDT 24
Peak memory 218408 kb
Host smart-3d0dc2b9-78c3-4f20-880c-792443f72b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753996734 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2753996734
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.226497874
Short name T307
Test name
Test status
Simulation time 37984978 ps
CPU time 1.36 seconds
Started May 05 01:54:26 PM PDT 24
Finished May 05 01:54:28 PM PDT 24
Peak memory 217304 kb
Host smart-bfc88e44-c064-4daf-ba93-4de158fd8f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226497874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.226497874
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.2690897594
Short name T14
Test name
Test status
Simulation time 24362645 ps
CPU time 1.02 seconds
Started May 05 01:54:26 PM PDT 24
Finished May 05 01:54:28 PM PDT 24
Peak memory 224392 kb
Host smart-8dc46e28-5317-47e7-830a-8d935c424a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690897594 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2690897594
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2599001685
Short name T631
Test name
Test status
Simulation time 87756147 ps
CPU time 1.28 seconds
Started May 05 01:54:29 PM PDT 24
Finished May 05 01:54:31 PM PDT 24
Peak memory 219868 kb
Host smart-53929c91-4b02-4a14-8a8f-7957c8bf452f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599001685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2599001685
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.2785719789
Short name T671
Test name
Test status
Simulation time 27245375 ps
CPU time 0.86 seconds
Started May 05 01:54:29 PM PDT 24
Finished May 05 01:54:31 PM PDT 24
Peak memory 218476 kb
Host smart-e3370dc4-21b4-4105-8ff5-ff3d2c842058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785719789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2785719789
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1099468329
Short name T660
Test name
Test status
Simulation time 72806026 ps
CPU time 1.19 seconds
Started May 05 01:54:31 PM PDT 24
Finished May 05 01:54:33 PM PDT 24
Peak memory 219788 kb
Host smart-9e0479f8-41b4-410a-a63f-fb21f0a6650f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099468329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1099468329
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.2693242066
Short name T719
Test name
Test status
Simulation time 18887413 ps
CPU time 1.1 seconds
Started May 05 01:54:32 PM PDT 24
Finished May 05 01:54:33 PM PDT 24
Peak memory 218652 kb
Host smart-a615adef-c9dd-46d0-9fc2-d05d5e83232c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693242066 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2693242066
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.4062392876
Short name T311
Test name
Test status
Simulation time 210056999 ps
CPU time 1.16 seconds
Started May 05 01:54:32 PM PDT 24
Finished May 05 01:54:34 PM PDT 24
Peak memory 217572 kb
Host smart-3254254d-1ee1-47b8-a13a-ad6d6b1aa24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062392876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.4062392876
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.2633182696
Short name T742
Test name
Test status
Simulation time 36917409 ps
CPU time 0.9 seconds
Started May 05 01:54:31 PM PDT 24
Finished May 05 01:54:32 PM PDT 24
Peak memory 218716 kb
Host smart-ebaa7141-9f69-40a2-ad32-af07dcd49c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633182696 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2633182696
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2112395010
Short name T11
Test name
Test status
Simulation time 44894422 ps
CPU time 1.51 seconds
Started May 05 01:54:29 PM PDT 24
Finished May 05 01:54:32 PM PDT 24
Peak memory 219992 kb
Host smart-9b871481-067d-40b5-8fb9-c9d920fe178d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112395010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2112395010
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.511406308
Short name T155
Test name
Test status
Simulation time 29312833 ps
CPU time 0.99 seconds
Started May 05 01:54:27 PM PDT 24
Finished May 05 01:54:28 PM PDT 24
Peak memory 224220 kb
Host smart-62dc27ef-64e2-4a1e-9c22-1a68d110f5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511406308 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.511406308
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.4274838861
Short name T618
Test name
Test status
Simulation time 53711952 ps
CPU time 2.18 seconds
Started May 05 01:54:31 PM PDT 24
Finished May 05 01:54:34 PM PDT 24
Peak memory 220272 kb
Host smart-020d42f1-4eb9-42cd-961a-82efc3ed6e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274838861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.4274838861
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.2741631236
Short name T691
Test name
Test status
Simulation time 21724958 ps
CPU time 0.97 seconds
Started May 05 01:54:25 PM PDT 24
Finished May 05 01:54:27 PM PDT 24
Peak memory 224232 kb
Host smart-cb67f40f-5e03-41d9-9be7-c533b8e78282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741631236 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2741631236
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1272195696
Short name T344
Test name
Test status
Simulation time 41945368 ps
CPU time 1.51 seconds
Started May 05 01:54:31 PM PDT 24
Finished May 05 01:54:33 PM PDT 24
Peak memory 218524 kb
Host smart-82870ef6-6c48-4541-b0e4-ca0111783f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272195696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1272195696
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.395728657
Short name T297
Test name
Test status
Simulation time 25308700 ps
CPU time 1.24 seconds
Started May 05 01:53:01 PM PDT 24
Finished May 05 01:53:03 PM PDT 24
Peak memory 216052 kb
Host smart-6f29002b-c597-44d3-b477-74bb74f8fe8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395728657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.395728657
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.3317081597
Short name T687
Test name
Test status
Simulation time 30411338 ps
CPU time 0.92 seconds
Started May 05 01:53:00 PM PDT 24
Finished May 05 01:53:01 PM PDT 24
Peak memory 207024 kb
Host smart-a519786d-efd1-4e2e-af7b-cfb50f1b366b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317081597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3317081597
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.80199481
Short name T153
Test name
Test status
Simulation time 56982881 ps
CPU time 0.85 seconds
Started May 05 01:53:02 PM PDT 24
Finished May 05 01:53:03 PM PDT 24
Peak memory 216608 kb
Host smart-19c2716c-3bef-4932-a9bc-1741613a6bdc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80199481 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.80199481
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1660390805
Short name T335
Test name
Test status
Simulation time 55520708 ps
CPU time 1.13 seconds
Started May 05 01:53:02 PM PDT 24
Finished May 05 01:53:04 PM PDT 24
Peak memory 218404 kb
Host smart-4bd495a7-1833-41cb-8043-dd1d39dd16a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660390805 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1660390805
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3249750940
Short name T137
Test name
Test status
Simulation time 87387059 ps
CPU time 1.12 seconds
Started May 05 01:53:00 PM PDT 24
Finished May 05 01:53:01 PM PDT 24
Peak memory 220352 kb
Host smart-0821a18a-9b4f-4345-8b30-ac08d6be40a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249750940 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3249750940
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1446170604
Short name T499
Test name
Test status
Simulation time 85665507 ps
CPU time 1.13 seconds
Started May 05 01:53:01 PM PDT 24
Finished May 05 01:53:03 PM PDT 24
Peak memory 217308 kb
Host smart-19f125a1-2391-4f22-8dbb-fba5bc90502d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446170604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1446170604
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.870725429
Short name T545
Test name
Test status
Simulation time 37870754 ps
CPU time 1.02 seconds
Started May 05 01:53:02 PM PDT 24
Finished May 05 01:53:04 PM PDT 24
Peak memory 224412 kb
Host smart-6e870cd4-bb62-4302-a242-2d2691793f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870725429 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.870725429
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3164222969
Short name T289
Test name
Test status
Simulation time 28433507 ps
CPU time 0.96 seconds
Started May 05 01:53:06 PM PDT 24
Finished May 05 01:53:07 PM PDT 24
Peak memory 207412 kb
Host smart-69768f7f-362c-49b9-b71e-b5ffc1628649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164222969 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3164222969
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.4196295228
Short name T393
Test name
Test status
Simulation time 17810663 ps
CPU time 1.02 seconds
Started May 05 01:53:06 PM PDT 24
Finished May 05 01:53:08 PM PDT 24
Peak memory 215596 kb
Host smart-a1f310ad-2186-40da-952b-29a12acadaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196295228 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.4196295228
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2672234657
Short name T211
Test name
Test status
Simulation time 157228964 ps
CPU time 1.42 seconds
Started May 05 01:53:03 PM PDT 24
Finished May 05 01:53:05 PM PDT 24
Peak memory 217432 kb
Host smart-916ae320-d4e9-45a3-a61c-4acdec832b19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672234657 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2672234657
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.872651180
Short name T197
Test name
Test status
Simulation time 206085158833 ps
CPU time 2436.74 seconds
Started May 05 01:53:01 PM PDT 24
Finished May 05 02:33:38 PM PDT 24
Peak memory 228680 kb
Host smart-239968ce-0f27-4fde-be4d-79eda545d243
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872651180 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.872651180
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.2490805351
Short name T572
Test name
Test status
Simulation time 53282265 ps
CPU time 1.08 seconds
Started May 05 01:54:26 PM PDT 24
Finished May 05 01:54:27 PM PDT 24
Peak memory 220984 kb
Host smart-c6e914cc-6332-42a1-8e6b-24ef783c3803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490805351 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2490805351
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1031773628
Short name T514
Test name
Test status
Simulation time 49643633 ps
CPU time 1.05 seconds
Started May 05 01:54:28 PM PDT 24
Finished May 05 01:54:30 PM PDT 24
Peak memory 217424 kb
Host smart-6013a4e2-9038-42ba-83ed-fc5d235e19dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031773628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1031773628
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.3339295399
Short name T145
Test name
Test status
Simulation time 40404258 ps
CPU time 0.94 seconds
Started May 05 01:54:35 PM PDT 24
Finished May 05 01:54:36 PM PDT 24
Peak memory 224164 kb
Host smart-d431df8e-7ea5-4704-af2a-da3068dcce53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339295399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3339295399
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3726009738
Short name T766
Test name
Test status
Simulation time 55719585 ps
CPU time 1.27 seconds
Started May 05 01:54:34 PM PDT 24
Finished May 05 01:54:36 PM PDT 24
Peak memory 217232 kb
Host smart-a5b118f9-dfce-4bcc-b26c-ebb35c3c9878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726009738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3726009738
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.70203245
Short name T762
Test name
Test status
Simulation time 17876658 ps
CPU time 1.05 seconds
Started May 05 01:54:29 PM PDT 24
Finished May 05 01:54:30 PM PDT 24
Peak memory 218692 kb
Host smart-78f31e21-4190-4a53-acaf-cd4cac3640da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70203245 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.70203245
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1796220103
Short name T341
Test name
Test status
Simulation time 28644592 ps
CPU time 1.33 seconds
Started May 05 01:54:35 PM PDT 24
Finished May 05 01:54:37 PM PDT 24
Peak memory 218616 kb
Host smart-e765c179-9524-41d4-afce-04fa1bf48415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796220103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1796220103
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.3864108378
Short name T755
Test name
Test status
Simulation time 45182604 ps
CPU time 0.95 seconds
Started May 05 01:54:25 PM PDT 24
Finished May 05 01:54:26 PM PDT 24
Peak memory 224172 kb
Host smart-46e97c80-963e-42c4-904c-0500dc5a14bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864108378 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3864108378
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3229106457
Short name T248
Test name
Test status
Simulation time 53602715 ps
CPU time 1.26 seconds
Started May 05 01:54:31 PM PDT 24
Finished May 05 01:54:33 PM PDT 24
Peak memory 218624 kb
Host smart-c65c8647-aaf3-4b53-a7f3-15c3b1aaac75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229106457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3229106457
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.2098528277
Short name T178
Test name
Test status
Simulation time 18683925 ps
CPU time 1.14 seconds
Started May 05 01:54:29 PM PDT 24
Finished May 05 01:54:31 PM PDT 24
Peak memory 219056 kb
Host smart-ecf5a4f6-c28b-4254-8afe-94fd2ede72b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098528277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2098528277
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1605883885
Short name T620
Test name
Test status
Simulation time 66526688 ps
CPU time 1.37 seconds
Started May 05 01:54:29 PM PDT 24
Finished May 05 01:54:31 PM PDT 24
Peak memory 218420 kb
Host smart-f0e7c136-7606-4966-8a6e-a70371983b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605883885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1605883885
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2777311490
Short name T7
Test name
Test status
Simulation time 37810765 ps
CPU time 1.12 seconds
Started May 05 01:54:26 PM PDT 24
Finished May 05 01:54:28 PM PDT 24
Peak memory 219168 kb
Host smart-9da47d53-1731-49a5-a1f1-4052ef3fcd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777311490 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2777311490
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2642818638
Short name T261
Test name
Test status
Simulation time 67484242 ps
CPU time 1.05 seconds
Started May 05 01:54:34 PM PDT 24
Finished May 05 01:54:36 PM PDT 24
Peak memory 217292 kb
Host smart-7c199017-8fb0-4119-b07a-512721e74ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642818638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2642818638
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.2822052917
Short name T62
Test name
Test status
Simulation time 19106383 ps
CPU time 1.14 seconds
Started May 05 01:54:30 PM PDT 24
Finished May 05 01:54:31 PM PDT 24
Peak memory 233156 kb
Host smart-48b8ddfc-9364-433c-8f80-f67dc5a706ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822052917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2822052917
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3570519837
Short name T747
Test name
Test status
Simulation time 26143066 ps
CPU time 1.3 seconds
Started May 05 01:54:31 PM PDT 24
Finished May 05 01:54:33 PM PDT 24
Peak memory 219768 kb
Host smart-6f4ffc6d-8017-4223-88a7-23054def1be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570519837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3570519837
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.316592263
Short name T792
Test name
Test status
Simulation time 21205436 ps
CPU time 0.99 seconds
Started May 05 01:54:26 PM PDT 24
Finished May 05 01:54:28 PM PDT 24
Peak memory 224412 kb
Host smart-c840cb9f-5c34-4931-bf64-0fb334c192db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316592263 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.316592263
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.159594729
Short name T347
Test name
Test status
Simulation time 134148752 ps
CPU time 1.24 seconds
Started May 05 01:54:27 PM PDT 24
Finished May 05 01:54:29 PM PDT 24
Peak memory 218600 kb
Host smart-9d595ddd-0b33-4845-9c54-c4762e0b12a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159594729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.159594729
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.3845212830
Short name T640
Test name
Test status
Simulation time 30244043 ps
CPU time 0.94 seconds
Started May 05 01:54:26 PM PDT 24
Finished May 05 01:54:27 PM PDT 24
Peak memory 218828 kb
Host smart-c1d28148-ed48-457d-b1e2-3159aa883fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845212830 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3845212830
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.720098400
Short name T319
Test name
Test status
Simulation time 33097451 ps
CPU time 1.3 seconds
Started May 05 01:54:35 PM PDT 24
Finished May 05 01:54:37 PM PDT 24
Peak memory 218424 kb
Host smart-83dd9378-7921-491d-a1a2-62ba436da796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720098400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.720098400
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.4280585289
Short name T588
Test name
Test status
Simulation time 43209876 ps
CPU time 1.17 seconds
Started May 05 01:54:27 PM PDT 24
Finished May 05 01:54:29 PM PDT 24
Peak memory 220056 kb
Host smart-8a932769-b747-46c3-9dff-1b3b1a883823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280585289 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.4280585289
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3742425935
Short name T611
Test name
Test status
Simulation time 65185921 ps
CPU time 1.16 seconds
Started May 05 01:54:27 PM PDT 24
Finished May 05 01:54:28 PM PDT 24
Peak memory 217416 kb
Host smart-fefb557c-cda6-439d-bc08-1f6fc26610f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742425935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3742425935
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%