Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.23 98.24 93.82 97.02 81.50 96.76 99.77 92.47


Total test records in report: 972
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T788 /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1442176701 May 07 03:17:19 PM PDT 24 May 07 03:22:22 PM PDT 24 23130503660 ps
T789 /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1871411279 May 07 03:16:09 PM PDT 24 May 07 03:22:25 PM PDT 24 133167651403 ps
T790 /workspace/coverage/default/45.edn_alert_test.2344615878 May 07 03:17:36 PM PDT 24 May 07 03:17:39 PM PDT 24 19286479 ps
T791 /workspace/coverage/default/77.edn_genbits.3601418973 May 07 03:17:45 PM PDT 24 May 07 03:17:47 PM PDT 24 62113642 ps
T792 /workspace/coverage/default/202.edn_genbits.821453816 May 07 03:18:19 PM PDT 24 May 07 03:18:23 PM PDT 24 93196006 ps
T793 /workspace/coverage/default/214.edn_genbits.4054742303 May 07 03:18:23 PM PDT 24 May 07 03:18:27 PM PDT 24 71076025 ps
T794 /workspace/coverage/default/135.edn_genbits.3355959435 May 07 03:18:12 PM PDT 24 May 07 03:18:15 PM PDT 24 76023585 ps
T795 /workspace/coverage/default/161.edn_genbits.1206376293 May 07 03:18:07 PM PDT 24 May 07 03:18:12 PM PDT 24 274332081 ps
T796 /workspace/coverage/default/119.edn_genbits.2394643364 May 07 03:18:01 PM PDT 24 May 07 03:18:05 PM PDT 24 50907831 ps
T797 /workspace/coverage/default/268.edn_genbits.129595002 May 07 03:18:23 PM PDT 24 May 07 03:18:27 PM PDT 24 40463094 ps
T798 /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2976248440 May 07 03:16:22 PM PDT 24 May 07 03:36:15 PM PDT 24 107886671508 ps
T799 /workspace/coverage/default/87.edn_genbits.2242918530 May 07 03:17:53 PM PDT 24 May 07 03:17:56 PM PDT 24 27507492 ps
T102 /workspace/coverage/default/29.edn_intr.78723157 May 07 03:17:05 PM PDT 24 May 07 03:17:07 PM PDT 24 24481202 ps
T118 /workspace/coverage/default/25.edn_err.288585990 May 07 03:16:57 PM PDT 24 May 07 03:16:59 PM PDT 24 67313886 ps
T800 /workspace/coverage/default/22.edn_alert_test.566859031 May 07 03:16:57 PM PDT 24 May 07 03:16:59 PM PDT 24 16903183 ps
T278 /workspace/coverage/default/14.edn_genbits.3272440884 May 07 03:16:48 PM PDT 24 May 07 03:16:51 PM PDT 24 41095498 ps
T801 /workspace/coverage/default/42.edn_disable.1583575189 May 07 03:17:37 PM PDT 24 May 07 03:17:41 PM PDT 24 17981108 ps
T802 /workspace/coverage/default/165.edn_genbits.422423879 May 07 03:18:14 PM PDT 24 May 07 03:18:17 PM PDT 24 41967161 ps
T803 /workspace/coverage/default/187.edn_genbits.2313111841 May 07 03:18:13 PM PDT 24 May 07 03:18:16 PM PDT 24 77866190 ps
T804 /workspace/coverage/default/91.edn_err.1354952195 May 07 03:17:51 PM PDT 24 May 07 03:17:53 PM PDT 24 19328067 ps
T805 /workspace/coverage/default/24.edn_intr.2303480008 May 07 03:16:57 PM PDT 24 May 07 03:17:00 PM PDT 24 24397362 ps
T806 /workspace/coverage/default/70.edn_err.1974983542 May 07 03:17:52 PM PDT 24 May 07 03:17:55 PM PDT 24 19804886 ps
T807 /workspace/coverage/default/22.edn_stress_all.3721674158 May 07 03:16:58 PM PDT 24 May 07 03:17:04 PM PDT 24 191059304 ps
T808 /workspace/coverage/default/194.edn_genbits.2971352977 May 07 03:18:23 PM PDT 24 May 07 03:18:31 PM PDT 24 42715104 ps
T809 /workspace/coverage/default/26.edn_stress_all.1766245312 May 07 03:16:57 PM PDT 24 May 07 03:17:01 PM PDT 24 183457044 ps
T810 /workspace/coverage/default/11.edn_stress_all.2474589625 May 07 03:16:48 PM PDT 24 May 07 03:16:55 PM PDT 24 204880063 ps
T100 /workspace/coverage/default/12.edn_intr.4001860133 May 07 03:16:46 PM PDT 24 May 07 03:16:48 PM PDT 24 40385024 ps
T811 /workspace/coverage/default/15.edn_genbits.2397411587 May 07 03:16:51 PM PDT 24 May 07 03:16:55 PM PDT 24 43522820 ps
T812 /workspace/coverage/default/130.edn_genbits.1937552647 May 07 03:18:05 PM PDT 24 May 07 03:18:07 PM PDT 24 86785433 ps
T813 /workspace/coverage/default/13.edn_intr.2437690144 May 07 03:16:46 PM PDT 24 May 07 03:16:48 PM PDT 24 22264386 ps
T814 /workspace/coverage/default/259.edn_genbits.1946816042 May 07 03:18:24 PM PDT 24 May 07 03:18:28 PM PDT 24 50219653 ps
T815 /workspace/coverage/default/16.edn_alert.2486795639 May 07 03:16:54 PM PDT 24 May 07 03:16:57 PM PDT 24 77996542 ps
T816 /workspace/coverage/default/272.edn_genbits.3704159649 May 07 03:18:25 PM PDT 24 May 07 03:18:30 PM PDT 24 101288268 ps
T817 /workspace/coverage/default/42.edn_alert.3645540246 May 07 03:17:36 PM PDT 24 May 07 03:17:39 PM PDT 24 49071960 ps
T119 /workspace/coverage/default/73.edn_err.1662290485 May 07 03:17:48 PM PDT 24 May 07 03:17:50 PM PDT 24 35219671 ps
T818 /workspace/coverage/default/169.edn_genbits.3124256764 May 07 03:18:13 PM PDT 24 May 07 03:18:17 PM PDT 24 51413412 ps
T819 /workspace/coverage/default/32.edn_err.1467025986 May 07 03:17:12 PM PDT 24 May 07 03:17:15 PM PDT 24 28552467 ps
T820 /workspace/coverage/default/0.edn_stress_all.2782704066 May 07 03:16:10 PM PDT 24 May 07 03:16:14 PM PDT 24 80151305 ps
T821 /workspace/coverage/default/103.edn_genbits.1597065776 May 07 03:17:56 PM PDT 24 May 07 03:17:58 PM PDT 24 29731336 ps
T822 /workspace/coverage/default/23.edn_alert.3925124028 May 07 03:17:02 PM PDT 24 May 07 03:17:05 PM PDT 24 99304181 ps
T823 /workspace/coverage/default/99.edn_genbits.2828515763 May 07 03:18:00 PM PDT 24 May 07 03:18:03 PM PDT 24 71114288 ps
T824 /workspace/coverage/default/1.edn_stress_all_with_rand_reset.232923235 May 07 03:16:17 PM PDT 24 May 07 03:22:25 PM PDT 24 19520308519 ps
T825 /workspace/coverage/default/48.edn_err.142367570 May 07 03:17:42 PM PDT 24 May 07 03:17:45 PM PDT 24 31445334 ps
T826 /workspace/coverage/default/25.edn_smoke.377566728 May 07 03:16:58 PM PDT 24 May 07 03:17:02 PM PDT 24 52124421 ps
T827 /workspace/coverage/default/92.edn_genbits.880195844 May 07 03:17:51 PM PDT 24 May 07 03:17:54 PM PDT 24 61314912 ps
T828 /workspace/coverage/default/32.edn_intr.2111909146 May 07 03:17:10 PM PDT 24 May 07 03:17:12 PM PDT 24 22589933 ps
T829 /workspace/coverage/default/45.edn_err.2707028319 May 07 03:17:34 PM PDT 24 May 07 03:17:36 PM PDT 24 29214419 ps
T830 /workspace/coverage/default/20.edn_alert_test.2619484505 May 07 03:16:52 PM PDT 24 May 07 03:16:54 PM PDT 24 20798563 ps
T831 /workspace/coverage/default/13.edn_disable_auto_req_mode.2458235926 May 07 03:16:46 PM PDT 24 May 07 03:16:48 PM PDT 24 65037426 ps
T832 /workspace/coverage/default/157.edn_genbits.1018439998 May 07 03:18:07 PM PDT 24 May 07 03:18:11 PM PDT 24 119487580 ps
T833 /workspace/coverage/default/18.edn_intr.1636368884 May 07 03:16:52 PM PDT 24 May 07 03:16:55 PM PDT 24 33952883 ps
T834 /workspace/coverage/default/52.edn_genbits.3747236265 May 07 03:17:42 PM PDT 24 May 07 03:17:45 PM PDT 24 78272843 ps
T835 /workspace/coverage/default/47.edn_disable.4061822782 May 07 03:17:41 PM PDT 24 May 07 03:17:45 PM PDT 24 39078257 ps
T836 /workspace/coverage/default/253.edn_genbits.4272253967 May 07 03:18:22 PM PDT 24 May 07 03:18:26 PM PDT 24 231678212 ps
T181 /workspace/coverage/default/3.edn_err.1104860194 May 07 03:16:20 PM PDT 24 May 07 03:16:22 PM PDT 24 18674082 ps
T837 /workspace/coverage/default/41.edn_disable.3999168834 May 07 03:17:27 PM PDT 24 May 07 03:17:30 PM PDT 24 13541320 ps
T838 /workspace/coverage/default/236.edn_genbits.1801485820 May 07 03:18:21 PM PDT 24 May 07 03:18:24 PM PDT 24 116858321 ps
T220 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2235715753 May 07 02:07:58 PM PDT 24 May 07 02:08:00 PM PDT 24 18235449 ps
T221 /workspace/coverage/cover_reg_top/13.edn_csr_rw.2319034916 May 07 02:07:50 PM PDT 24 May 07 02:07:51 PM PDT 24 13942875 ps
T839 /workspace/coverage/cover_reg_top/14.edn_intr_test.2233764754 May 07 02:07:53 PM PDT 24 May 07 02:07:54 PM PDT 24 11707031 ps
T237 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2645216910 May 07 02:07:57 PM PDT 24 May 07 02:07:59 PM PDT 24 35938376 ps
T222 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.428538797 May 07 02:07:19 PM PDT 24 May 07 02:07:21 PM PDT 24 25743396 ps
T252 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2348489516 May 07 02:08:04 PM PDT 24 May 07 02:08:07 PM PDT 24 244826744 ps
T840 /workspace/coverage/cover_reg_top/4.edn_tl_errors.291426096 May 07 02:07:26 PM PDT 24 May 07 02:07:29 PM PDT 24 278548988 ps
T841 /workspace/coverage/cover_reg_top/24.edn_intr_test.1658851228 May 07 02:08:04 PM PDT 24 May 07 02:08:05 PM PDT 24 23408383 ps
T842 /workspace/coverage/cover_reg_top/5.edn_tl_errors.4240544658 May 07 02:07:31 PM PDT 24 May 07 02:07:33 PM PDT 24 78840934 ps
T253 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.33319553 May 07 02:07:51 PM PDT 24 May 07 02:07:54 PM PDT 24 188208736 ps
T223 /workspace/coverage/cover_reg_top/8.edn_csr_rw.2391527279 May 07 02:07:47 PM PDT 24 May 07 02:07:48 PM PDT 24 37367528 ps
T254 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1854090616 May 07 02:08:03 PM PDT 24 May 07 02:08:09 PM PDT 24 451615988 ps
T843 /workspace/coverage/cover_reg_top/32.edn_intr_test.2722917637 May 07 02:08:14 PM PDT 24 May 07 02:08:16 PM PDT 24 11506710 ps
T844 /workspace/coverage/cover_reg_top/9.edn_intr_test.3491494595 May 07 02:07:47 PM PDT 24 May 07 02:07:49 PM PDT 24 35297863 ps
T250 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3629492338 May 07 02:07:34 PM PDT 24 May 07 02:07:36 PM PDT 24 29331985 ps
T845 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3037811805 May 07 02:07:56 PM PDT 24 May 07 02:07:59 PM PDT 24 27000509 ps
T846 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.109578533 May 07 02:07:38 PM PDT 24 May 07 02:07:40 PM PDT 24 84776772 ps
T847 /workspace/coverage/cover_reg_top/23.edn_intr_test.3401531126 May 07 02:08:00 PM PDT 24 May 07 02:08:02 PM PDT 24 22881054 ps
T251 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3361492940 May 07 02:07:08 PM PDT 24 May 07 02:07:11 PM PDT 24 47714185 ps
T848 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.709975183 May 07 02:07:34 PM PDT 24 May 07 02:07:36 PM PDT 24 25391532 ps
T263 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.4106458913 May 07 02:07:30 PM PDT 24 May 07 02:07:35 PM PDT 24 287197133 ps
T849 /workspace/coverage/cover_reg_top/39.edn_intr_test.1529683828 May 07 02:08:09 PM PDT 24 May 07 02:08:11 PM PDT 24 21746728 ps
T850 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2728929267 May 07 02:08:04 PM PDT 24 May 07 02:08:07 PM PDT 24 250704370 ps
T851 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.154573016 May 07 02:07:37 PM PDT 24 May 07 02:07:39 PM PDT 24 269296092 ps
T852 /workspace/coverage/cover_reg_top/3.edn_tl_errors.4120684198 May 07 02:07:22 PM PDT 24 May 07 02:07:24 PM PDT 24 93483905 ps
T853 /workspace/coverage/cover_reg_top/33.edn_intr_test.231701612 May 07 02:08:09 PM PDT 24 May 07 02:08:11 PM PDT 24 22028829 ps
T854 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3935503947 May 07 02:07:37 PM PDT 24 May 07 02:07:40 PM PDT 24 41562732 ps
T855 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3793890408 May 07 02:07:55 PM PDT 24 May 07 02:07:58 PM PDT 24 40526986 ps
T856 /workspace/coverage/cover_reg_top/30.edn_intr_test.3638922916 May 07 02:08:01 PM PDT 24 May 07 02:08:03 PM PDT 24 15573308 ps
T857 /workspace/coverage/cover_reg_top/20.edn_intr_test.3465256887 May 07 02:08:02 PM PDT 24 May 07 02:08:04 PM PDT 24 14136055 ps
T858 /workspace/coverage/cover_reg_top/45.edn_intr_test.1395478228 May 07 02:08:14 PM PDT 24 May 07 02:08:16 PM PDT 24 44156193 ps
T859 /workspace/coverage/cover_reg_top/8.edn_intr_test.1418169589 May 07 02:07:43 PM PDT 24 May 07 02:07:44 PM PDT 24 46095764 ps
T860 /workspace/coverage/cover_reg_top/17.edn_intr_test.3849349982 May 07 02:07:59 PM PDT 24 May 07 02:08:01 PM PDT 24 17369144 ps
T861 /workspace/coverage/cover_reg_top/43.edn_intr_test.2613463287 May 07 02:08:14 PM PDT 24 May 07 02:08:16 PM PDT 24 13717587 ps
T224 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.653696335 May 07 02:07:47 PM PDT 24 May 07 02:07:49 PM PDT 24 37445481 ps
T238 /workspace/coverage/cover_reg_top/9.edn_csr_rw.4102175048 May 07 02:07:48 PM PDT 24 May 07 02:07:50 PM PDT 24 14758982 ps
T862 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.4166825978 May 07 02:07:08 PM PDT 24 May 07 02:07:15 PM PDT 24 493583045 ps
T863 /workspace/coverage/cover_reg_top/25.edn_intr_test.1917826603 May 07 02:08:03 PM PDT 24 May 07 02:08:05 PM PDT 24 19985972 ps
T239 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2661493063 May 07 02:07:52 PM PDT 24 May 07 02:07:54 PM PDT 24 100177795 ps
T864 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2572832393 May 07 02:07:07 PM PDT 24 May 07 02:07:12 PM PDT 24 784275420 ps
T865 /workspace/coverage/cover_reg_top/28.edn_intr_test.775142481 May 07 02:08:03 PM PDT 24 May 07 02:08:05 PM PDT 24 12987545 ps
T866 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3579345316 May 07 02:07:52 PM PDT 24 May 07 02:07:54 PM PDT 24 28089983 ps
T240 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.838336212 May 07 02:07:33 PM PDT 24 May 07 02:07:35 PM PDT 24 61598546 ps
T867 /workspace/coverage/cover_reg_top/1.edn_tl_errors.94127044 May 07 02:07:08 PM PDT 24 May 07 02:07:11 PM PDT 24 53213925 ps
T264 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2221547656 May 07 02:07:08 PM PDT 24 May 07 02:07:12 PM PDT 24 81725682 ps
T868 /workspace/coverage/cover_reg_top/12.edn_intr_test.4156061210 May 07 02:07:50 PM PDT 24 May 07 02:07:51 PM PDT 24 14911993 ps
T869 /workspace/coverage/cover_reg_top/8.edn_tl_errors.4047130427 May 07 02:07:39 PM PDT 24 May 07 02:07:42 PM PDT 24 46079232 ps
T870 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2913456566 May 07 02:08:04 PM PDT 24 May 07 02:08:07 PM PDT 24 199884898 ps
T871 /workspace/coverage/cover_reg_top/26.edn_intr_test.2654237660 May 07 02:08:03 PM PDT 24 May 07 02:08:05 PM PDT 24 39614396 ps
T225 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.559531655 May 07 02:07:13 PM PDT 24 May 07 02:07:15 PM PDT 24 32256728 ps
T872 /workspace/coverage/cover_reg_top/36.edn_intr_test.3006399764 May 07 02:08:08 PM PDT 24 May 07 02:08:10 PM PDT 24 37430192 ps
T873 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2195470488 May 07 02:07:48 PM PDT 24 May 07 02:07:52 PM PDT 24 149135512 ps
T874 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3650274665 May 07 02:07:12 PM PDT 24 May 07 02:07:15 PM PDT 24 196965006 ps
T241 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1137558724 May 07 02:07:52 PM PDT 24 May 07 02:07:54 PM PDT 24 31913853 ps
T226 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4060326424 May 07 02:07:21 PM PDT 24 May 07 02:07:28 PM PDT 24 1248937431 ps
T875 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1888496737 May 07 02:07:51 PM PDT 24 May 07 02:07:54 PM PDT 24 242363535 ps
T876 /workspace/coverage/cover_reg_top/5.edn_intr_test.155373764 May 07 02:07:33 PM PDT 24 May 07 02:07:35 PM PDT 24 51837953 ps
T877 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4027978826 May 07 02:07:15 PM PDT 24 May 07 02:07:18 PM PDT 24 337253636 ps
T878 /workspace/coverage/cover_reg_top/13.edn_intr_test.619505441 May 07 02:07:51 PM PDT 24 May 07 02:07:52 PM PDT 24 36767841 ps
T879 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3854057030 May 07 02:07:35 PM PDT 24 May 07 02:07:37 PM PDT 24 88906136 ps
T880 /workspace/coverage/cover_reg_top/48.edn_intr_test.748733418 May 07 02:08:15 PM PDT 24 May 07 02:08:17 PM PDT 24 15134771 ps
T881 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2066195371 May 07 02:07:27 PM PDT 24 May 07 02:07:30 PM PDT 24 313967987 ps
T882 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3920799815 May 07 02:07:44 PM PDT 24 May 07 02:07:47 PM PDT 24 68590594 ps
T883 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2724323436 May 07 02:07:59 PM PDT 24 May 07 02:08:01 PM PDT 24 39724602 ps
T884 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1776860776 May 07 02:07:51 PM PDT 24 May 07 02:07:55 PM PDT 24 358767030 ps
T885 /workspace/coverage/cover_reg_top/6.edn_intr_test.2609315868 May 07 02:07:39 PM PDT 24 May 07 02:07:40 PM PDT 24 13061620 ps
T227 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.790175778 May 07 02:07:25 PM PDT 24 May 07 02:07:27 PM PDT 24 32822807 ps
T886 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.388460897 May 07 02:07:18 PM PDT 24 May 07 02:07:20 PM PDT 24 15517682 ps
T887 /workspace/coverage/cover_reg_top/2.edn_intr_test.4217807910 May 07 02:07:18 PM PDT 24 May 07 02:07:19 PM PDT 24 42089409 ps
T888 /workspace/coverage/cover_reg_top/41.edn_intr_test.1203791358 May 07 02:08:08 PM PDT 24 May 07 02:08:09 PM PDT 24 17904758 ps
T889 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2791568802 May 07 02:07:45 PM PDT 24 May 07 02:07:47 PM PDT 24 151488774 ps
T890 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3938970747 May 07 02:07:56 PM PDT 24 May 07 02:08:00 PM PDT 24 245242304 ps
T891 /workspace/coverage/cover_reg_top/15.edn_intr_test.4035868594 May 07 02:07:52 PM PDT 24 May 07 02:07:54 PM PDT 24 59592708 ps
T892 /workspace/coverage/cover_reg_top/27.edn_intr_test.1068879990 May 07 02:08:06 PM PDT 24 May 07 02:08:07 PM PDT 24 11658346 ps
T893 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1051038579 May 07 02:07:50 PM PDT 24 May 07 02:07:52 PM PDT 24 67838587 ps
T228 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2351666801 May 07 02:07:22 PM PDT 24 May 07 02:07:23 PM PDT 24 15249182 ps
T894 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1007014229 May 07 02:07:58 PM PDT 24 May 07 02:07:59 PM PDT 24 11559297 ps
T229 /workspace/coverage/cover_reg_top/3.edn_csr_rw.690399388 May 07 02:07:25 PM PDT 24 May 07 02:07:27 PM PDT 24 15446925 ps
T895 /workspace/coverage/cover_reg_top/44.edn_intr_test.3670299956 May 07 02:08:07 PM PDT 24 May 07 02:08:08 PM PDT 24 15224071 ps
T896 /workspace/coverage/cover_reg_top/35.edn_intr_test.2708483448 May 07 02:08:09 PM PDT 24 May 07 02:08:11 PM PDT 24 12595778 ps
T897 /workspace/coverage/cover_reg_top/1.edn_intr_test.3411929621 May 07 02:07:13 PM PDT 24 May 07 02:07:16 PM PDT 24 27630725 ps
T898 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4083924519 May 07 02:07:54 PM PDT 24 May 07 02:07:56 PM PDT 24 17161693 ps
T899 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1213762959 May 07 02:07:27 PM PDT 24 May 07 02:07:29 PM PDT 24 19049474 ps
T900 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3482760790 May 07 02:07:38 PM PDT 24 May 07 02:07:41 PM PDT 24 32621047 ps
T901 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.646725611 May 07 02:07:32 PM PDT 24 May 07 02:07:33 PM PDT 24 95634829 ps
T902 /workspace/coverage/cover_reg_top/21.edn_intr_test.3379909769 May 07 02:08:01 PM PDT 24 May 07 02:08:03 PM PDT 24 36953346 ps
T903 /workspace/coverage/cover_reg_top/6.edn_csr_rw.995649485 May 07 02:07:40 PM PDT 24 May 07 02:07:41 PM PDT 24 38054993 ps
T904 /workspace/coverage/cover_reg_top/46.edn_intr_test.461472706 May 07 02:08:08 PM PDT 24 May 07 02:08:10 PM PDT 24 15887338 ps
T905 /workspace/coverage/cover_reg_top/19.edn_intr_test.3544522430 May 07 02:08:01 PM PDT 24 May 07 02:08:03 PM PDT 24 15385572 ps
T906 /workspace/coverage/cover_reg_top/16.edn_intr_test.3634045978 May 07 02:07:54 PM PDT 24 May 07 02:07:56 PM PDT 24 39542422 ps
T907 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1531837601 May 07 02:07:52 PM PDT 24 May 07 02:07:55 PM PDT 24 49311127 ps
T908 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1846992737 May 07 02:07:15 PM PDT 24 May 07 02:07:17 PM PDT 24 48640093 ps
T909 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3809200957 May 07 02:07:57 PM PDT 24 May 07 02:07:59 PM PDT 24 56425816 ps
T910 /workspace/coverage/cover_reg_top/47.edn_intr_test.4210501801 May 07 02:08:13 PM PDT 24 May 07 02:08:15 PM PDT 24 18135931 ps
T266 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3661750663 May 07 02:07:57 PM PDT 24 May 07 02:07:59 PM PDT 24 43538056 ps
T911 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3138936572 May 07 02:07:08 PM PDT 24 May 07 02:07:10 PM PDT 24 117665636 ps
T265 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1767882210 May 07 02:07:51 PM PDT 24 May 07 02:07:54 PM PDT 24 188937284 ps
T912 /workspace/coverage/cover_reg_top/34.edn_intr_test.228070063 May 07 02:08:07 PM PDT 24 May 07 02:08:08 PM PDT 24 31714402 ps
T913 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3435185934 May 07 02:07:45 PM PDT 24 May 07 02:07:47 PM PDT 24 78597527 ps
T914 /workspace/coverage/cover_reg_top/15.edn_tl_errors.567416016 May 07 02:07:56 PM PDT 24 May 07 02:08:01 PM PDT 24 1084798462 ps
T915 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2009970708 May 07 02:07:52 PM PDT 24 May 07 02:07:54 PM PDT 24 118376636 ps
T916 /workspace/coverage/cover_reg_top/7.edn_intr_test.3723792774 May 07 02:07:36 PM PDT 24 May 07 02:07:37 PM PDT 24 17964640 ps
T917 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2140392000 May 07 02:07:58 PM PDT 24 May 07 02:08:02 PM PDT 24 445576785 ps
T918 /workspace/coverage/cover_reg_top/3.edn_intr_test.472815563 May 07 02:07:19 PM PDT 24 May 07 02:07:20 PM PDT 24 109059743 ps
T919 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1520769381 May 07 02:07:32 PM PDT 24 May 07 02:07:34 PM PDT 24 52543610 ps
T920 /workspace/coverage/cover_reg_top/18.edn_intr_test.895500176 May 07 02:07:57 PM PDT 24 May 07 02:07:59 PM PDT 24 39425556 ps
T921 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2658148113 May 07 02:07:51 PM PDT 24 May 07 02:07:53 PM PDT 24 105421712 ps
T922 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.777001167 May 07 02:07:55 PM PDT 24 May 07 02:07:57 PM PDT 24 27065819 ps
T923 /workspace/coverage/cover_reg_top/2.edn_tl_errors.4266816422 May 07 02:07:13 PM PDT 24 May 07 02:07:16 PM PDT 24 103495973 ps
T924 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2944229136 May 07 02:07:38 PM PDT 24 May 07 02:07:40 PM PDT 24 21850111 ps
T925 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.27069402 May 07 02:08:04 PM PDT 24 May 07 02:08:08 PM PDT 24 115285792 ps
T926 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2391777163 May 07 02:07:19 PM PDT 24 May 07 02:07:22 PM PDT 24 150132546 ps
T927 /workspace/coverage/cover_reg_top/37.edn_intr_test.4050323454 May 07 02:08:08 PM PDT 24 May 07 02:08:10 PM PDT 24 44516205 ps
T230 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.865382313 May 07 02:07:24 PM PDT 24 May 07 02:07:26 PM PDT 24 17082655 ps
T928 /workspace/coverage/cover_reg_top/40.edn_intr_test.3963917921 May 07 02:08:08 PM PDT 24 May 07 02:08:10 PM PDT 24 54695817 ps
T929 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.723720325 May 07 02:07:51 PM PDT 24 May 07 02:07:54 PM PDT 24 88003058 ps
T930 /workspace/coverage/cover_reg_top/10.edn_intr_test.2226834487 May 07 02:07:47 PM PDT 24 May 07 02:07:49 PM PDT 24 12788061 ps
T931 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.4236737293 May 07 02:07:36 PM PDT 24 May 07 02:07:39 PM PDT 24 301731497 ps
T932 /workspace/coverage/cover_reg_top/31.edn_intr_test.2926385664 May 07 02:08:01 PM PDT 24 May 07 02:08:03 PM PDT 24 19434742 ps
T933 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1487586678 May 07 02:07:48 PM PDT 24 May 07 02:07:50 PM PDT 24 23789596 ps
T231 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.951773327 May 07 02:07:24 PM PDT 24 May 07 02:07:25 PM PDT 24 28115165 ps
T934 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2437751879 May 07 02:07:24 PM PDT 24 May 07 02:07:27 PM PDT 24 133587492 ps
T935 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1896201782 May 07 02:07:32 PM PDT 24 May 07 02:07:34 PM PDT 24 40184705 ps
T936 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.991018979 May 07 02:08:00 PM PDT 24 May 07 02:08:03 PM PDT 24 29364007 ps
T937 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.936772391 May 07 02:07:58 PM PDT 24 May 07 02:08:00 PM PDT 24 310777336 ps
T938 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1571834755 May 07 02:07:58 PM PDT 24 May 07 02:08:00 PM PDT 24 46773787 ps
T939 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.401128525 May 07 02:07:20 PM PDT 24 May 07 02:07:22 PM PDT 24 72126773 ps
T940 /workspace/coverage/cover_reg_top/0.edn_intr_test.1935669605 May 07 02:07:08 PM PDT 24 May 07 02:07:10 PM PDT 24 16568286 ps
T232 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2072252618 May 07 02:07:54 PM PDT 24 May 07 02:07:56 PM PDT 24 23260190 ps
T941 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1998397380 May 07 02:07:13 PM PDT 24 May 07 02:07:20 PM PDT 24 251926320 ps
T942 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.4070362722 May 07 02:07:56 PM PDT 24 May 07 02:07:58 PM PDT 24 49102577 ps
T233 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.385996237 May 07 02:07:13 PM PDT 24 May 07 02:07:16 PM PDT 24 177343081 ps
T943 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1308089466 May 07 02:07:41 PM PDT 24 May 07 02:07:43 PM PDT 24 13751851 ps
T944 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.4244292578 May 07 02:07:37 PM PDT 24 May 07 02:07:38 PM PDT 24 43353998 ps
T234 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1879667185 May 07 02:07:55 PM PDT 24 May 07 02:07:57 PM PDT 24 46693647 ps
T945 /workspace/coverage/cover_reg_top/22.edn_intr_test.1591001975 May 07 02:08:06 PM PDT 24 May 07 02:08:07 PM PDT 24 18567252 ps
T946 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2767462959 May 07 02:08:01 PM PDT 24 May 07 02:08:04 PM PDT 24 68259396 ps
T947 /workspace/coverage/cover_reg_top/19.edn_csr_rw.249394701 May 07 02:08:02 PM PDT 24 May 07 02:08:03 PM PDT 24 20513921 ps
T948 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2782409933 May 07 02:07:52 PM PDT 24 May 07 02:07:54 PM PDT 24 51281729 ps
T235 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2288198732 May 07 02:07:55 PM PDT 24 May 07 02:07:56 PM PDT 24 140229226 ps
T949 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.268883848 May 07 02:07:31 PM PDT 24 May 07 02:07:38 PM PDT 24 312198647 ps
T950 /workspace/coverage/cover_reg_top/29.edn_intr_test.3805992635 May 07 02:08:02 PM PDT 24 May 07 02:08:04 PM PDT 24 11331873 ps
T951 /workspace/coverage/cover_reg_top/18.edn_tl_errors.335827661 May 07 02:07:58 PM PDT 24 May 07 02:08:01 PM PDT 24 188677899 ps
T952 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1416090231 May 07 02:07:44 PM PDT 24 May 07 02:07:46 PM PDT 24 158490279 ps
T953 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3350446828 May 07 02:07:57 PM PDT 24 May 07 02:07:59 PM PDT 24 14839032 ps
T954 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3891266372 May 07 02:07:53 PM PDT 24 May 07 02:07:55 PM PDT 24 113713282 ps
T236 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1843040590 May 07 02:07:07 PM PDT 24 May 07 02:07:09 PM PDT 24 44789248 ps
T955 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3635386156 May 07 02:07:12 PM PDT 24 May 07 02:07:14 PM PDT 24 23551503 ps
T956 /workspace/coverage/cover_reg_top/49.edn_intr_test.423332179 May 07 02:08:13 PM PDT 24 May 07 02:08:15 PM PDT 24 45410806 ps
T957 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2793533561 May 07 02:07:18 PM PDT 24 May 07 02:07:20 PM PDT 24 80126943 ps
T958 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.4176958694 May 07 02:07:53 PM PDT 24 May 07 02:07:56 PM PDT 24 26339232 ps
T959 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2280210553 May 07 02:07:53 PM PDT 24 May 07 02:07:59 PM PDT 24 224224525 ps
T960 /workspace/coverage/cover_reg_top/4.edn_intr_test.1010589976 May 07 02:07:27 PM PDT 24 May 07 02:07:29 PM PDT 24 14173591 ps
T961 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.4053690202 May 07 02:07:25 PM PDT 24 May 07 02:07:27 PM PDT 24 328078222 ps
T962 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.352074999 May 07 02:07:57 PM PDT 24 May 07 02:07:59 PM PDT 24 35127003 ps
T963 /workspace/coverage/cover_reg_top/11.edn_intr_test.2746439013 May 07 02:07:51 PM PDT 24 May 07 02:07:53 PM PDT 24 13899392 ps
T964 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3964157345 May 07 02:07:51 PM PDT 24 May 07 02:07:53 PM PDT 24 43704162 ps
T965 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1424792228 May 07 02:07:11 PM PDT 24 May 07 02:07:13 PM PDT 24 61577499 ps
T966 /workspace/coverage/cover_reg_top/42.edn_intr_test.2872658462 May 07 02:08:09 PM PDT 24 May 07 02:08:10 PM PDT 24 31924989 ps
T967 /workspace/coverage/cover_reg_top/38.edn_intr_test.570758322 May 07 02:08:09 PM PDT 24 May 07 02:08:11 PM PDT 24 27944565 ps
T968 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1441930083 May 07 02:07:51 PM PDT 24 May 07 02:07:54 PM PDT 24 41308341 ps
T969 /workspace/coverage/cover_reg_top/0.edn_csr_rw.269969782 May 07 02:07:09 PM PDT 24 May 07 02:07:11 PM PDT 24 55353511 ps
T970 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3601918076 May 07 02:07:44 PM PDT 24 May 07 02:07:46 PM PDT 24 119796547 ps
T971 /workspace/coverage/cover_reg_top/4.edn_csr_rw.4085464895 May 07 02:07:32 PM PDT 24 May 07 02:07:34 PM PDT 24 57502110 ps
T972 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3143503060 May 07 02:07:08 PM PDT 24 May 07 02:07:11 PM PDT 24 52552012 ps

Test location /workspace/coverage/default/188.edn_genbits.2310884733
Short name T25
Test name
Test status
Simulation time 58190971 ps
CPU time 1.38 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:27 PM PDT 24
Peak memory 218708 kb
Host smart-4811438e-4579-494c-b083-b61c3c5b001f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310884733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2310884733
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.256364863
Short name T40
Test name
Test status
Simulation time 60919290401 ps
CPU time 311.92 seconds
Started May 07 03:17:36 PM PDT 24
Finished May 07 03:22:50 PM PDT 24
Peak memory 223328 kb
Host smart-d1631b83-61df-4c36-a1d0-0abed29440a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256364863 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.256364863
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/266.edn_genbits.980145175
Short name T12
Test name
Test status
Simulation time 121115041 ps
CPU time 1.3 seconds
Started May 07 03:18:22 PM PDT 24
Finished May 07 03:18:25 PM PDT 24
Peak memory 220252 kb
Host smart-f609b8b6-80f4-4ee0-840e-df56bf6af8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980145175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.980145175
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_err.1145190799
Short name T5
Test name
Test status
Simulation time 19317368 ps
CPU time 0.99 seconds
Started May 07 03:16:58 PM PDT 24
Finished May 07 03:17:01 PM PDT 24
Peak memory 218828 kb
Host smart-6b01debf-1c59-45f7-b203-367ab1a67115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145190799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1145190799
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2558240353
Short name T18
Test name
Test status
Simulation time 249754175 ps
CPU time 4.64 seconds
Started May 07 03:16:20 PM PDT 24
Finished May 07 03:16:26 PM PDT 24
Peak memory 237020 kb
Host smart-378a60fe-3970-445a-b7c7-f8c1eaff5d7a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558240353 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2558240353
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/21.edn_alert.1209396744
Short name T22
Test name
Test status
Simulation time 101951546 ps
CPU time 1.24 seconds
Started May 07 03:16:54 PM PDT 24
Finished May 07 03:16:57 PM PDT 24
Peak memory 216124 kb
Host smart-876aa04f-fa13-4e5d-94e0-6c05fb235022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209396744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1209396744
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/41.edn_stress_all.1783122406
Short name T172
Test name
Test status
Simulation time 277715324 ps
CPU time 5.68 seconds
Started May 07 03:17:29 PM PDT 24
Finished May 07 03:17:37 PM PDT 24
Peak memory 217220 kb
Host smart-28b803d2-816b-459f-9dec-8b4fe1c75ad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783122406 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1783122406
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3887875067
Short name T20
Test name
Test status
Simulation time 442066146 ps
CPU time 6.92 seconds
Started May 07 03:16:17 PM PDT 24
Finished May 07 03:16:26 PM PDT 24
Peak memory 237736 kb
Host smart-2cb32a70-dbe2-4c8c-ae4c-8e20ebc8af9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887875067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3887875067
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1706511436
Short name T24
Test name
Test status
Simulation time 47463639 ps
CPU time 1.31 seconds
Started May 07 03:17:35 PM PDT 24
Finished May 07 03:17:39 PM PDT 24
Peak memory 217156 kb
Host smart-6d8cd872-7aa3-410c-b89c-595eca4907b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706511436 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1706511436
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_alert.2609590721
Short name T169
Test name
Test status
Simulation time 82244925 ps
CPU time 1.14 seconds
Started May 07 03:17:04 PM PDT 24
Finished May 07 03:17:07 PM PDT 24
Peak memory 216076 kb
Host smart-0d09dd3f-4f2a-4711-be04-12a751395805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609590721 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2609590721
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3963552758
Short name T41
Test name
Test status
Simulation time 83013530376 ps
CPU time 543.92 seconds
Started May 07 03:16:35 PM PDT 24
Finished May 07 03:25:40 PM PDT 24
Peak memory 219976 kb
Host smart-6c7b59a5-23c7-42a6-8b8c-69cc926c03ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963552758 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3963552758
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/189.edn_genbits.578537867
Short name T45
Test name
Test status
Simulation time 78493822 ps
CPU time 1.48 seconds
Started May 07 03:18:18 PM PDT 24
Finished May 07 03:18:21 PM PDT 24
Peak memory 217456 kb
Host smart-04e0d4c9-d573-40e6-b915-899941e9146f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578537867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.578537867
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.2811421828
Short name T27
Test name
Test status
Simulation time 21581142 ps
CPU time 0.92 seconds
Started May 07 03:16:15 PM PDT 24
Finished May 07 03:16:19 PM PDT 24
Peak memory 207448 kb
Host smart-4af2a553-27b5-41ff-9332-01ba6c9acc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811421828 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2811421828
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2319034916
Short name T221
Test name
Test status
Simulation time 13942875 ps
CPU time 0.9 seconds
Started May 07 02:07:50 PM PDT 24
Finished May 07 02:07:51 PM PDT 24
Peak memory 206740 kb
Host smart-5083ded3-d4e9-4e97-a244-9b98925b29a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319034916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2319034916
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1624776625
Short name T162
Test name
Test status
Simulation time 38060467936 ps
CPU time 192.06 seconds
Started May 07 03:17:40 PM PDT 24
Finished May 07 03:20:55 PM PDT 24
Peak memory 223984 kb
Host smart-98ad0e9d-6ca2-43c5-9fe3-7182164487cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624776625 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1624776625
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2221547656
Short name T264
Test name
Test status
Simulation time 81725682 ps
CPU time 2.39 seconds
Started May 07 02:07:08 PM PDT 24
Finished May 07 02:07:12 PM PDT 24
Peak memory 206768 kb
Host smart-b657f616-5273-4101-8527-fb15fe2ea45c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221547656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2221547656
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/6.edn_alert.488776393
Short name T144
Test name
Test status
Simulation time 33408083 ps
CPU time 1.2 seconds
Started May 07 03:16:36 PM PDT 24
Finished May 07 03:16:38 PM PDT 24
Peak memory 216092 kb
Host smart-e292d0d7-84ba-4b2c-9788-38bef6372d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488776393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.488776393
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/5.edn_disable.638913647
Short name T134
Test name
Test status
Simulation time 12348787 ps
CPU time 0.9 seconds
Started May 07 03:16:28 PM PDT 24
Finished May 07 03:16:30 PM PDT 24
Peak memory 216812 kb
Host smart-227738f3-74cf-412c-8821-55b0c1ea9e77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638913647 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.638913647
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/113.edn_genbits.3010694363
Short name T50
Test name
Test status
Simulation time 132781234 ps
CPU time 1.38 seconds
Started May 07 03:18:01 PM PDT 24
Finished May 07 03:18:04 PM PDT 24
Peak memory 220228 kb
Host smart-6770fa45-e4e0-4bfb-a954-120b66bb7b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010694363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3010694363
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_disable.167076805
Short name T153
Test name
Test status
Simulation time 12844001 ps
CPU time 0.88 seconds
Started May 07 03:16:41 PM PDT 24
Finished May 07 03:16:43 PM PDT 24
Peak memory 216932 kb
Host smart-1af7cdc3-1a70-4419-a699-3e107b1535ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167076805 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.167076805
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable.3140228621
Short name T177
Test name
Test status
Simulation time 35128121 ps
CPU time 0.93 seconds
Started May 07 03:16:59 PM PDT 24
Finished May 07 03:17:03 PM PDT 24
Peak memory 216728 kb
Host smart-8d82c50d-72fe-47db-8ccf-8d3455ef278a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140228621 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3140228621
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2161428984
Short name T108
Test name
Test status
Simulation time 35934509 ps
CPU time 1.2 seconds
Started May 07 03:17:03 PM PDT 24
Finished May 07 03:17:05 PM PDT 24
Peak memory 217140 kb
Host smart-ed404875-c463-4378-8d73-c66bc754a381
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161428984 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2161428984
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_alert.4081868833
Short name T258
Test name
Test status
Simulation time 80384621 ps
CPU time 1.28 seconds
Started May 07 03:16:59 PM PDT 24
Finished May 07 03:17:03 PM PDT 24
Peak memory 216068 kb
Host smart-933d8e3b-bc8c-4363-b631-985ce57230da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081868833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.4081868833
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert.2237801953
Short name T783
Test name
Test status
Simulation time 104613860 ps
CPU time 1.19 seconds
Started May 07 03:16:48 PM PDT 24
Finished May 07 03:16:52 PM PDT 24
Peak memory 216000 kb
Host smart-de4bdac7-d6b6-4b1a-a95f-a56680c13dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237801953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2237801953
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.1468596877
Short name T285
Test name
Test status
Simulation time 123377819 ps
CPU time 1.53 seconds
Started May 07 03:18:11 PM PDT 24
Finished May 07 03:18:14 PM PDT 24
Peak memory 219772 kb
Host smart-3312e154-d24f-4306-91af-fb9f4cf7864c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468596877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1468596877
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.887539637
Short name T59
Test name
Test status
Simulation time 30831019 ps
CPU time 1.4 seconds
Started May 07 03:17:50 PM PDT 24
Finished May 07 03:17:52 PM PDT 24
Peak memory 225984 kb
Host smart-a281a2fd-3b1f-4960-80ec-e206680fd8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887539637 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.887539637
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/23.edn_intr.1265786756
Short name T32
Test name
Test status
Simulation time 31266356 ps
CPU time 1.2 seconds
Started May 07 03:16:59 PM PDT 24
Finished May 07 03:17:03 PM PDT 24
Peak memory 217216 kb
Host smart-c0540768-1c83-4c9b-bb58-7de2c478478f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265786756 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1265786756
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2713579845
Short name T125
Test name
Test status
Simulation time 44656588 ps
CPU time 1.35 seconds
Started May 07 03:16:15 PM PDT 24
Finished May 07 03:16:19 PM PDT 24
Peak memory 217268 kb
Host smart-ce5ed4cf-8336-441f-a427-35e6fbcd6efe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713579845 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2713579845
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_disable.3882660092
Short name T128
Test name
Test status
Simulation time 17315079 ps
CPU time 0.81 seconds
Started May 07 03:17:05 PM PDT 24
Finished May 07 03:17:08 PM PDT 24
Peak memory 215808 kb
Host smart-df72eba2-ab63-420a-b507-29682732f772
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882660092 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3882660092
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/14.edn_intr.643184586
Short name T38
Test name
Test status
Simulation time 60533790 ps
CPU time 0.82 seconds
Started May 07 03:16:48 PM PDT 24
Finished May 07 03:16:50 PM PDT 24
Peak memory 216128 kb
Host smart-5378fb49-8b8e-4a41-b9e5-121643b7667a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643184586 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.643184586
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/12.edn_disable.2088058739
Short name T26
Test name
Test status
Simulation time 42091658 ps
CPU time 0.84 seconds
Started May 07 03:16:45 PM PDT 24
Finished May 07 03:16:47 PM PDT 24
Peak memory 216640 kb
Host smart-1786afa8-1eb6-449f-9e92-0e3a417bd08d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088058739 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2088058739
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.4220939119
Short name T87
Test name
Test status
Simulation time 59922627 ps
CPU time 1.08 seconds
Started May 07 03:16:45 PM PDT 24
Finished May 07 03:16:47 PM PDT 24
Peak memory 220068 kb
Host smart-95c798c0-6384-4627-a45c-d205aa3a31b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220939119 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.4220939119
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_disable.3353271643
Short name T151
Test name
Test status
Simulation time 27215914 ps
CPU time 0.84 seconds
Started May 07 03:16:55 PM PDT 24
Finished May 07 03:16:57 PM PDT 24
Peak memory 216124 kb
Host smart-3e6177bf-08ab-4544-aadf-3004e910c3d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353271643 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3353271643
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2300633077
Short name T123
Test name
Test status
Simulation time 47970334 ps
CPU time 1.07 seconds
Started May 07 03:16:55 PM PDT 24
Finished May 07 03:16:58 PM PDT 24
Peak memory 218512 kb
Host smart-2ba1b9ad-006c-4be5-9cd0-304c7d889bed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300633077 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2300633077
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_disable.1915357264
Short name T187
Test name
Test status
Simulation time 12161372 ps
CPU time 0.86 seconds
Started May 07 03:17:03 PM PDT 24
Finished May 07 03:17:05 PM PDT 24
Peak memory 216784 kb
Host smart-5b710bc6-8227-4c6d-aaeb-46ef3b57c6cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915357264 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1915357264
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.21856515
Short name T114
Test name
Test status
Simulation time 124679165 ps
CPU time 1.13 seconds
Started May 07 03:17:03 PM PDT 24
Finished May 07 03:17:05 PM PDT 24
Peak memory 219788 kb
Host smart-bfb0cad9-64f6-4a47-a0fb-063b27d6ff52
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21856515 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_dis
able_auto_req_mode.21856515
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2337188749
Short name T624
Test name
Test status
Simulation time 25916382915 ps
CPU time 688.18 seconds
Started May 07 03:16:56 PM PDT 24
Finished May 07 03:28:26 PM PDT 24
Peak memory 223972 kb
Host smart-0e0b8100-7348-418e-999f-c055211138af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337188749 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2337188749
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.edn_alert_test.3699235862
Short name T305
Test name
Test status
Simulation time 25351015 ps
CPU time 1.09 seconds
Started May 07 03:16:47 PM PDT 24
Finished May 07 03:16:50 PM PDT 24
Peak memory 207136 kb
Host smart-da5ff00d-bbf6-4c07-8ee0-dac9cf27caa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699235862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3699235862
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/118.edn_genbits.772529306
Short name T47
Test name
Test status
Simulation time 111718705 ps
CPU time 2.55 seconds
Started May 07 03:18:02 PM PDT 24
Finished May 07 03:18:06 PM PDT 24
Peak memory 219704 kb
Host smart-d659d1c0-abd7-4e59-8c7d-ff58323c29c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772529306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.772529306
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_regwen.1940000857
Short name T28
Test name
Test status
Simulation time 24575370 ps
CPU time 0.93 seconds
Started May 07 03:16:27 PM PDT 24
Finished May 07 03:16:29 PM PDT 24
Peak memory 207420 kb
Host smart-2364f04b-bb4a-4d2a-81d8-3e8293bb78a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940000857 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1940000857
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.736939594
Short name T197
Test name
Test status
Simulation time 141175769939 ps
CPU time 863.62 seconds
Started May 07 03:17:38 PM PDT 24
Finished May 07 03:32:05 PM PDT 24
Peak memory 221936 kb
Host smart-73c132f2-bbf7-437d-b9d6-41f43d5e074c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736939594 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.736939594
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/184.edn_genbits.3726919480
Short name T271
Test name
Test status
Simulation time 33943199 ps
CPU time 1.48 seconds
Started May 07 03:18:16 PM PDT 24
Finished May 07 03:18:18 PM PDT 24
Peak memory 220008 kb
Host smart-19a6c6d8-2c63-4eda-88c6-08b756fd54b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726919480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3726919480
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.2876694412
Short name T294
Test name
Test status
Simulation time 57418247 ps
CPU time 0.92 seconds
Started May 07 03:16:16 PM PDT 24
Finished May 07 03:16:19 PM PDT 24
Peak memory 207484 kb
Host smart-d2200b91-d1fe-40b3-b08c-ffa54c10f219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876694412 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2876694412
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/34.edn_alert.468496856
Short name T296
Test name
Test status
Simulation time 83348506 ps
CPU time 1.16 seconds
Started May 07 03:17:17 PM PDT 24
Finished May 07 03:17:20 PM PDT 24
Peak memory 216084 kb
Host smart-3d1e8bf7-c5c1-4a3e-a279-b754358a7123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468496856 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.468496856
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/45.edn_intr.958526441
Short name T37
Test name
Test status
Simulation time 38320430 ps
CPU time 0.88 seconds
Started May 07 03:17:38 PM PDT 24
Finished May 07 03:17:42 PM PDT 24
Peak memory 216012 kb
Host smart-ae8d1333-99fd-425f-bfee-9e0248873210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958526441 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.958526441
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.33319553
Short name T253
Test name
Test status
Simulation time 188208736 ps
CPU time 1.45 seconds
Started May 07 02:07:51 PM PDT 24
Finished May 07 02:07:54 PM PDT 24
Peak memory 206904 kb
Host smart-184d14ce-920e-4662-8667-deb4d6b93bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33319553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.33319553
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/default/10.edn_alert.30570874
Short name T702
Test name
Test status
Simulation time 25358227 ps
CPU time 1.4 seconds
Started May 07 03:16:40 PM PDT 24
Finished May 07 03:16:43 PM PDT 24
Peak memory 216076 kb
Host smart-fcdb2e5a-fe11-43f3-8886-fce31ea9e997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30570874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.30570874
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.581621603
Short name T319
Test name
Test status
Simulation time 64944604 ps
CPU time 1.48 seconds
Started May 07 03:17:58 PM PDT 24
Finished May 07 03:18:00 PM PDT 24
Peak memory 219864 kb
Host smart-4a77263d-69eb-4ccc-8cfc-1b716023b11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581621603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.581621603
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.1529417589
Short name T272
Test name
Test status
Simulation time 47866621 ps
CPU time 1.63 seconds
Started May 07 03:18:02 PM PDT 24
Finished May 07 03:18:05 PM PDT 24
Peak memory 218588 kb
Host smart-be84ff91-8a2b-4039-a3b6-4a0016311054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529417589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1529417589
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.3664837015
Short name T89
Test name
Test status
Simulation time 196564126 ps
CPU time 1.21 seconds
Started May 07 03:18:02 PM PDT 24
Finished May 07 03:18:04 PM PDT 24
Peak memory 217324 kb
Host smart-22d25406-72a7-4cfb-b11f-28f6183eda1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664837015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3664837015
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1392812005
Short name T30
Test name
Test status
Simulation time 451557308 ps
CPU time 1.25 seconds
Started May 07 03:16:54 PM PDT 24
Finished May 07 03:16:57 PM PDT 24
Peak memory 216096 kb
Host smart-b9e79190-5c00-49d4-b624-9f3a5bc269bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392812005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1392812005
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.105094433
Short name T594
Test name
Test status
Simulation time 62952996 ps
CPU time 1.33 seconds
Started May 07 03:18:11 PM PDT 24
Finished May 07 03:18:13 PM PDT 24
Peak memory 218804 kb
Host smart-8989a3cd-18f4-47ad-82e6-2e00dbe49c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105094433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.105094433
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2539363902
Short name T270
Test name
Test status
Simulation time 67516897 ps
CPU time 1.08 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:22 PM PDT 24
Peak memory 217212 kb
Host smart-2cd44067-b35c-4aff-8363-a994e350999b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539363902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2539363902
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.604181870
Short name T94
Test name
Test status
Simulation time 62198522 ps
CPU time 1.68 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:25 PM PDT 24
Peak memory 218948 kb
Host smart-b7996b62-5456-481a-a921-86f3a3e37dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604181870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.604181870
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.4284244276
Short name T287
Test name
Test status
Simulation time 114701928 ps
CPU time 1.24 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:22 PM PDT 24
Peak memory 218176 kb
Host smart-fc7d7762-6641-4a4c-9163-f4f06e3594af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284244276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.4284244276
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3029553785
Short name T281
Test name
Test status
Simulation time 42333902 ps
CPU time 1.52 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:23 PM PDT 24
Peak memory 218632 kb
Host smart-63c1498d-2e4c-4c09-8bb8-7ed0a893b75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029553785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3029553785
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_genbits.3518335484
Short name T284
Test name
Test status
Simulation time 33267059 ps
CPU time 1.56 seconds
Started May 07 03:17:27 PM PDT 24
Finished May 07 03:17:31 PM PDT 24
Peak memory 218720 kb
Host smart-f5fd7a14-4a14-48fc-af2a-df39931331fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518335484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3518335484
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_alert.4209706863
Short name T259
Test name
Test status
Simulation time 66727630 ps
CPU time 1.04 seconds
Started May 07 03:17:38 PM PDT 24
Finished May 07 03:17:42 PM PDT 24
Peak memory 216096 kb
Host smart-949247fe-f1fd-4b12-a1ba-fce46fab3a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209706863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.4209706863
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/7.edn_regwen.183879548
Short name T295
Test name
Test status
Simulation time 34846793 ps
CPU time 0.89 seconds
Started May 07 03:16:36 PM PDT 24
Finished May 07 03:16:38 PM PDT 24
Peak memory 207432 kb
Host smart-49bd229f-9ae5-4438-8f91-9bb53f8c0b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183879548 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.183879548
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/29.edn_intr.78723157
Short name T102
Test name
Test status
Simulation time 24481202 ps
CPU time 0.95 seconds
Started May 07 03:17:05 PM PDT 24
Finished May 07 03:17:07 PM PDT 24
Peak memory 216268 kb
Host smart-72baf31c-1333-4a25-8087-02b4ea6479c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78723157 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.78723157
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/19.edn_disable.259575349
Short name T136
Test name
Test status
Simulation time 99582002 ps
CPU time 0.89 seconds
Started May 07 03:16:56 PM PDT 24
Finished May 07 03:16:58 PM PDT 24
Peak memory 216588 kb
Host smart-ba4b0bdf-9960-4849-9af4-1dcaa4586310
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259575349 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.259575349
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable.2398358133
Short name T194
Test name
Test status
Simulation time 94741330 ps
CPU time 0.91 seconds
Started May 07 03:17:07 PM PDT 24
Finished May 07 03:17:09 PM PDT 24
Peak memory 216496 kb
Host smart-04045aa8-2412-467c-bfd2-a6b6deaafe27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398358133 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2398358133
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3361492940
Short name T251
Test name
Test status
Simulation time 47714185 ps
CPU time 1.01 seconds
Started May 07 02:07:08 PM PDT 24
Finished May 07 02:07:11 PM PDT 24
Peak memory 206676 kb
Host smart-17cbbea3-4782-4264-b9cb-091e9d9ac757
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361492940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3361492940
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.4166825978
Short name T862
Test name
Test status
Simulation time 493583045 ps
CPU time 5.17 seconds
Started May 07 02:07:08 PM PDT 24
Finished May 07 02:07:15 PM PDT 24
Peak memory 206788 kb
Host smart-0e6d5f0a-f40a-4c88-aa39-1aa2d870487f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166825978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.4166825978
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1843040590
Short name T236
Test name
Test status
Simulation time 44789248 ps
CPU time 0.96 seconds
Started May 07 02:07:07 PM PDT 24
Finished May 07 02:07:09 PM PDT 24
Peak memory 206660 kb
Host smart-42b08119-efc6-4de7-93e7-e607b02769b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843040590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1843040590
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3143503060
Short name T972
Test name
Test status
Simulation time 52552012 ps
CPU time 1.36 seconds
Started May 07 02:07:08 PM PDT 24
Finished May 07 02:07:11 PM PDT 24
Peak memory 215012 kb
Host smart-9a1811b3-0b07-494c-a43d-fdf793d758ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143503060 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3143503060
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.269969782
Short name T969
Test name
Test status
Simulation time 55353511 ps
CPU time 0.9 seconds
Started May 07 02:07:09 PM PDT 24
Finished May 07 02:07:11 PM PDT 24
Peak memory 206744 kb
Host smart-3fc79344-928b-45bf-8f5a-519a27b366c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269969782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.269969782
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1935669605
Short name T940
Test name
Test status
Simulation time 16568286 ps
CPU time 0.97 seconds
Started May 07 02:07:08 PM PDT 24
Finished May 07 02:07:10 PM PDT 24
Peak memory 206668 kb
Host smart-e35496c7-0c94-4fa5-b9a5-6dfc14db9242
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935669605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1935669605
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3138936572
Short name T911
Test name
Test status
Simulation time 117665636 ps
CPU time 1.34 seconds
Started May 07 02:07:08 PM PDT 24
Finished May 07 02:07:10 PM PDT 24
Peak memory 206756 kb
Host smart-9d0bf535-70ea-4253-b605-de9a331d62a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138936572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3138936572
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2572832393
Short name T864
Test name
Test status
Simulation time 784275420 ps
CPU time 4.56 seconds
Started May 07 02:07:07 PM PDT 24
Finished May 07 02:07:12 PM PDT 24
Peak memory 214948 kb
Host smart-802d5d21-9465-4526-b1ec-4a8e50d89e26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572832393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2572832393
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.385996237
Short name T233
Test name
Test status
Simulation time 177343081 ps
CPU time 1.56 seconds
Started May 07 02:07:13 PM PDT 24
Finished May 07 02:07:16 PM PDT 24
Peak memory 206744 kb
Host smart-1c47ef9f-220b-47d4-ad93-75a361b92151
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385996237 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.385996237
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1998397380
Short name T941
Test name
Test status
Simulation time 251926320 ps
CPU time 5.45 seconds
Started May 07 02:07:13 PM PDT 24
Finished May 07 02:07:20 PM PDT 24
Peak memory 206792 kb
Host smart-060f3a3b-9bff-4cb5-bd85-035a73cc1516
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998397380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1998397380
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.559531655
Short name T225
Test name
Test status
Simulation time 32256728 ps
CPU time 0.91 seconds
Started May 07 02:07:13 PM PDT 24
Finished May 07 02:07:15 PM PDT 24
Peak memory 206740 kb
Host smart-aebade53-0e98-4d27-ae72-a9af0199d751
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559531655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.559531655
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1846992737
Short name T908
Test name
Test status
Simulation time 48640093 ps
CPU time 0.98 seconds
Started May 07 02:07:15 PM PDT 24
Finished May 07 02:07:17 PM PDT 24
Peak memory 215012 kb
Host smart-d57cdba4-a004-47be-b580-8b2f1c759586
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846992737 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1846992737
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3635386156
Short name T955
Test name
Test status
Simulation time 23551503 ps
CPU time 0.86 seconds
Started May 07 02:07:12 PM PDT 24
Finished May 07 02:07:14 PM PDT 24
Peak memory 206760 kb
Host smart-635fc401-f8b3-4ca4-8696-295df46e0baa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635386156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3635386156
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3411929621
Short name T897
Test name
Test status
Simulation time 27630725 ps
CPU time 0.9 seconds
Started May 07 02:07:13 PM PDT 24
Finished May 07 02:07:16 PM PDT 24
Peak memory 206492 kb
Host smart-bc9cefea-f583-4987-a47e-2d1db049bd73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411929621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3411929621
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1424792228
Short name T965
Test name
Test status
Simulation time 61577499 ps
CPU time 1.07 seconds
Started May 07 02:07:11 PM PDT 24
Finished May 07 02:07:13 PM PDT 24
Peak memory 206812 kb
Host smart-3cbc9799-9963-4146-8a31-79f9014401c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424792228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1424792228
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.94127044
Short name T867
Test name
Test status
Simulation time 53213925 ps
CPU time 1.82 seconds
Started May 07 02:07:08 PM PDT 24
Finished May 07 02:07:11 PM PDT 24
Peak memory 214940 kb
Host smart-20790849-56c2-4350-8c7c-30f198f8cbe4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94127044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.94127044
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3650274665
Short name T874
Test name
Test status
Simulation time 196965006 ps
CPU time 1.52 seconds
Started May 07 02:07:12 PM PDT 24
Finished May 07 02:07:15 PM PDT 24
Peak memory 206696 kb
Host smart-6c47cfef-b635-40d8-a081-5314063a6ca1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650274665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3650274665
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2658148113
Short name T921
Test name
Test status
Simulation time 105421712 ps
CPU time 1.31 seconds
Started May 07 02:07:51 PM PDT 24
Finished May 07 02:07:53 PM PDT 24
Peak memory 217952 kb
Host smart-c8d2106c-2a37-4ee8-b8cc-9b18d9cd46af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658148113 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2658148113
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1487586678
Short name T933
Test name
Test status
Simulation time 23789596 ps
CPU time 0.86 seconds
Started May 07 02:07:48 PM PDT 24
Finished May 07 02:07:50 PM PDT 24
Peak memory 206720 kb
Host smart-034df656-a77b-40bb-96ae-9e68b85139cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487586678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1487586678
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2226834487
Short name T930
Test name
Test status
Simulation time 12788061 ps
CPU time 0.83 seconds
Started May 07 02:07:47 PM PDT 24
Finished May 07 02:07:49 PM PDT 24
Peak memory 206684 kb
Host smart-41b4df1e-9325-4023-9649-534f9de8444a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226834487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2226834487
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.653696335
Short name T224
Test name
Test status
Simulation time 37445481 ps
CPU time 1.23 seconds
Started May 07 02:07:47 PM PDT 24
Finished May 07 02:07:49 PM PDT 24
Peak memory 206732 kb
Host smart-f61c2921-7d13-49a9-84dc-af323617650c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653696335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.653696335
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2195470488
Short name T873
Test name
Test status
Simulation time 149135512 ps
CPU time 2.98 seconds
Started May 07 02:07:48 PM PDT 24
Finished May 07 02:07:52 PM PDT 24
Peak memory 214920 kb
Host smart-a9797676-a965-41df-9dac-bb4280101dbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195470488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2195470488
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2791568802
Short name T889
Test name
Test status
Simulation time 151488774 ps
CPU time 2.17 seconds
Started May 07 02:07:45 PM PDT 24
Finished May 07 02:07:47 PM PDT 24
Peak memory 206716 kb
Host smart-74834be6-2fca-4d5e-8749-8a0165ebef27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791568802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2791568802
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1888496737
Short name T875
Test name
Test status
Simulation time 242363535 ps
CPU time 1.12 seconds
Started May 07 02:07:51 PM PDT 24
Finished May 07 02:07:54 PM PDT 24
Peak memory 215024 kb
Host smart-7d33d9ac-43a0-4322-8f99-8b953d839b1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888496737 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1888496737
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2072252618
Short name T232
Test name
Test status
Simulation time 23260190 ps
CPU time 0.92 seconds
Started May 07 02:07:54 PM PDT 24
Finished May 07 02:07:56 PM PDT 24
Peak memory 206788 kb
Host smart-a820615e-4ed4-4279-b3b9-94e36b17773e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072252618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2072252618
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2746439013
Short name T963
Test name
Test status
Simulation time 13899392 ps
CPU time 0.88 seconds
Started May 07 02:07:51 PM PDT 24
Finished May 07 02:07:53 PM PDT 24
Peak memory 206704 kb
Host smart-1ea93772-8124-4970-9f8b-397a2f944c54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746439013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2746439013
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2782409933
Short name T948
Test name
Test status
Simulation time 51281729 ps
CPU time 1.01 seconds
Started May 07 02:07:52 PM PDT 24
Finished May 07 02:07:54 PM PDT 24
Peak memory 206760 kb
Host smart-3ffbece7-bb01-4a41-918d-0d1af6c349d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782409933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2782409933
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2280210553
Short name T959
Test name
Test status
Simulation time 224224525 ps
CPU time 4.26 seconds
Started May 07 02:07:53 PM PDT 24
Finished May 07 02:07:59 PM PDT 24
Peak memory 214948 kb
Host smart-5618081c-5697-414e-b2fa-f941c97e6382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280210553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2280210553
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.4176958694
Short name T958
Test name
Test status
Simulation time 26339232 ps
CPU time 1.29 seconds
Started May 07 02:07:53 PM PDT 24
Finished May 07 02:07:56 PM PDT 24
Peak memory 214964 kb
Host smart-f8276ba0-e944-48b5-996f-bae3eaff8ae2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176958694 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.4176958694
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2288198732
Short name T235
Test name
Test status
Simulation time 140229226 ps
CPU time 0.89 seconds
Started May 07 02:07:55 PM PDT 24
Finished May 07 02:07:56 PM PDT 24
Peak memory 206668 kb
Host smart-2873e18a-00d5-4345-bb93-e9d197a937e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288198732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2288198732
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.4156061210
Short name T868
Test name
Test status
Simulation time 14911993 ps
CPU time 0.83 seconds
Started May 07 02:07:50 PM PDT 24
Finished May 07 02:07:51 PM PDT 24
Peak memory 206680 kb
Host smart-aff12466-05f9-492e-862d-852d5521c568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156061210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.4156061210
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1137558724
Short name T241
Test name
Test status
Simulation time 31913853 ps
CPU time 1.12 seconds
Started May 07 02:07:52 PM PDT 24
Finished May 07 02:07:54 PM PDT 24
Peak memory 206756 kb
Host smart-9eb71d5a-fe37-46a3-b9af-3a3cd8c9131e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137558724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1137558724
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3938970747
Short name T890
Test name
Test status
Simulation time 245242304 ps
CPU time 2.65 seconds
Started May 07 02:07:56 PM PDT 24
Finished May 07 02:08:00 PM PDT 24
Peak memory 218956 kb
Host smart-68aba965-d4c8-411e-88d9-9703b6bfd085
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938970747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3938970747
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3661750663
Short name T266
Test name
Test status
Simulation time 43538056 ps
CPU time 1.56 seconds
Started May 07 02:07:57 PM PDT 24
Finished May 07 02:07:59 PM PDT 24
Peak memory 206756 kb
Host smart-dd6b2ab3-e116-4869-8314-0644a83d1126
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661750663 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3661750663
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3579345316
Short name T866
Test name
Test status
Simulation time 28089983 ps
CPU time 0.95 seconds
Started May 07 02:07:52 PM PDT 24
Finished May 07 02:07:54 PM PDT 24
Peak memory 215020 kb
Host smart-6c89b379-5087-43ed-8eaf-2dbc7fc59bd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579345316 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3579345316
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.619505441
Short name T878
Test name
Test status
Simulation time 36767841 ps
CPU time 0.83 seconds
Started May 07 02:07:51 PM PDT 24
Finished May 07 02:07:52 PM PDT 24
Peak memory 206488 kb
Host smart-d9221fb6-a1a7-477e-8740-937da08e82a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619505441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.619505441
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2661493063
Short name T239
Test name
Test status
Simulation time 100177795 ps
CPU time 1.22 seconds
Started May 07 02:07:52 PM PDT 24
Finished May 07 02:07:54 PM PDT 24
Peak memory 206800 kb
Host smart-ba0be956-f2c1-48ed-a7a5-4747618609f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661493063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2661493063
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1776860776
Short name T884
Test name
Test status
Simulation time 358767030 ps
CPU time 3.41 seconds
Started May 07 02:07:51 PM PDT 24
Finished May 07 02:07:55 PM PDT 24
Peak memory 215004 kb
Host smart-ae9eb54b-25ce-478d-8421-1dea9d4fd52f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776860776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1776860776
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1767882210
Short name T265
Test name
Test status
Simulation time 188937284 ps
CPU time 2.06 seconds
Started May 07 02:07:51 PM PDT 24
Finished May 07 02:07:54 PM PDT 24
Peak memory 206804 kb
Host smart-bb45f87c-e274-4e80-bbe8-6ddffaba524d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767882210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1767882210
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4083924519
Short name T898
Test name
Test status
Simulation time 17161693 ps
CPU time 1.15 seconds
Started May 07 02:07:54 PM PDT 24
Finished May 07 02:07:56 PM PDT 24
Peak memory 215012 kb
Host smart-a07dab42-7e0e-470b-b485-aac9e63b74f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083924519 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.4083924519
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3964157345
Short name T964
Test name
Test status
Simulation time 43704162 ps
CPU time 0.86 seconds
Started May 07 02:07:51 PM PDT 24
Finished May 07 02:07:53 PM PDT 24
Peak memory 206668 kb
Host smart-2a990ef8-544f-424d-bb59-d6cd18cf3a7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964157345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3964157345
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2233764754
Short name T839
Test name
Test status
Simulation time 11707031 ps
CPU time 0.89 seconds
Started May 07 02:07:53 PM PDT 24
Finished May 07 02:07:54 PM PDT 24
Peak memory 206656 kb
Host smart-e213a8df-110c-47f7-ba4f-60bc4260fcf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233764754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2233764754
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2009970708
Short name T915
Test name
Test status
Simulation time 118376636 ps
CPU time 1.05 seconds
Started May 07 02:07:52 PM PDT 24
Finished May 07 02:07:54 PM PDT 24
Peak memory 206852 kb
Host smart-5207a32d-6563-4cff-9808-49aeb384bb4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009970708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2009970708
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1531837601
Short name T907
Test name
Test status
Simulation time 49311127 ps
CPU time 1.85 seconds
Started May 07 02:07:52 PM PDT 24
Finished May 07 02:07:55 PM PDT 24
Peak memory 214952 kb
Host smart-179fb65a-f0e2-4f43-a395-1d0d089aa133
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531837601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1531837601
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3793890408
Short name T855
Test name
Test status
Simulation time 40526986 ps
CPU time 1.49 seconds
Started May 07 02:07:55 PM PDT 24
Finished May 07 02:07:58 PM PDT 24
Peak memory 206756 kb
Host smart-2a614412-15e4-41c3-8a38-8f8480a62331
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793890408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3793890408
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3809200957
Short name T909
Test name
Test status
Simulation time 56425816 ps
CPU time 1.06 seconds
Started May 07 02:07:57 PM PDT 24
Finished May 07 02:07:59 PM PDT 24
Peak memory 215148 kb
Host smart-a41eb341-9f63-4f07-b608-366409dba439
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809200957 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3809200957
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2724323436
Short name T883
Test name
Test status
Simulation time 39724602 ps
CPU time 0.85 seconds
Started May 07 02:07:59 PM PDT 24
Finished May 07 02:08:01 PM PDT 24
Peak memory 206736 kb
Host smart-bfeb2bd2-1fb6-47d0-9d12-fb9cb213d234
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724323436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2724323436
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.4035868594
Short name T891
Test name
Test status
Simulation time 59592708 ps
CPU time 0.81 seconds
Started May 07 02:07:52 PM PDT 24
Finished May 07 02:07:54 PM PDT 24
Peak memory 206492 kb
Host smart-8db9536d-f297-4413-b589-ab47110d8940
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035868594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.4035868594
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3350446828
Short name T953
Test name
Test status
Simulation time 14839032 ps
CPU time 0.94 seconds
Started May 07 02:07:57 PM PDT 24
Finished May 07 02:07:59 PM PDT 24
Peak memory 206752 kb
Host smart-a3213709-f567-4132-aa67-4c71ff19629b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350446828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3350446828
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.567416016
Short name T914
Test name
Test status
Simulation time 1084798462 ps
CPU time 3.68 seconds
Started May 07 02:07:56 PM PDT 24
Finished May 07 02:08:01 PM PDT 24
Peak memory 214884 kb
Host smart-28c463a1-dca8-4eb1-89ee-f776de7df226
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567416016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.567416016
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3891266372
Short name T954
Test name
Test status
Simulation time 113713282 ps
CPU time 1.49 seconds
Started May 07 02:07:53 PM PDT 24
Finished May 07 02:07:55 PM PDT 24
Peak memory 206856 kb
Host smart-62d83298-0c24-431b-bce4-fbe7ad91e602
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891266372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3891266372
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3037811805
Short name T845
Test name
Test status
Simulation time 27000509 ps
CPU time 1.8 seconds
Started May 07 02:07:56 PM PDT 24
Finished May 07 02:07:59 PM PDT 24
Peak memory 215032 kb
Host smart-9e3595fb-d4e9-43b3-8ab9-1c7d92b1d490
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037811805 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3037811805
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1007014229
Short name T894
Test name
Test status
Simulation time 11559297 ps
CPU time 0.81 seconds
Started May 07 02:07:58 PM PDT 24
Finished May 07 02:07:59 PM PDT 24
Peak memory 206624 kb
Host smart-09589962-fab5-4410-9135-60446ef7aa1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007014229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1007014229
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3634045978
Short name T906
Test name
Test status
Simulation time 39542422 ps
CPU time 0.74 seconds
Started May 07 02:07:54 PM PDT 24
Finished May 07 02:07:56 PM PDT 24
Peak memory 206484 kb
Host smart-3ef047a6-ca5d-4285-9501-330188bd9445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634045978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3634045978
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2645216910
Short name T237
Test name
Test status
Simulation time 35938376 ps
CPU time 1.03 seconds
Started May 07 02:07:57 PM PDT 24
Finished May 07 02:07:59 PM PDT 24
Peak memory 206756 kb
Host smart-884d8db8-d340-40de-9e1a-581a715aa542
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645216910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2645216910
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2913456566
Short name T870
Test name
Test status
Simulation time 199884898 ps
CPU time 2.05 seconds
Started May 07 02:08:04 PM PDT 24
Finished May 07 02:08:07 PM PDT 24
Peak memory 215020 kb
Host smart-15ee09a0-1725-4bd3-9cee-0384c9f0eb8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913456566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2913456566
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1854090616
Short name T254
Test name
Test status
Simulation time 451615988 ps
CPU time 4.89 seconds
Started May 07 02:08:03 PM PDT 24
Finished May 07 02:08:09 PM PDT 24
Peak memory 207148 kb
Host smart-d7f075aa-ee83-4c09-bff0-1083ec4bfddd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854090616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1854090616
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.777001167
Short name T922
Test name
Test status
Simulation time 27065819 ps
CPU time 0.95 seconds
Started May 07 02:07:55 PM PDT 24
Finished May 07 02:07:57 PM PDT 24
Peak memory 206824 kb
Host smart-1a7f3945-b3f6-497b-961f-6ac9ef49db65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777001167 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.777001167
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1571834755
Short name T938
Test name
Test status
Simulation time 46773787 ps
CPU time 0.92 seconds
Started May 07 02:07:58 PM PDT 24
Finished May 07 02:08:00 PM PDT 24
Peak memory 206748 kb
Host smart-00e5281a-9baf-4fbe-bbe1-b1d5589c19f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571834755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1571834755
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3849349982
Short name T860
Test name
Test status
Simulation time 17369144 ps
CPU time 0.92 seconds
Started May 07 02:07:59 PM PDT 24
Finished May 07 02:08:01 PM PDT 24
Peak memory 206772 kb
Host smart-4f0446f9-4f5f-49c6-8a04-823bcaa159a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849349982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3849349982
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2235715753
Short name T220
Test name
Test status
Simulation time 18235449 ps
CPU time 1.16 seconds
Started May 07 02:07:58 PM PDT 24
Finished May 07 02:08:00 PM PDT 24
Peak memory 206768 kb
Host smart-04b1fd00-cc28-4ca2-8b32-8c40e671a2c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235715753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2235715753
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2140392000
Short name T917
Test name
Test status
Simulation time 445576785 ps
CPU time 3.3 seconds
Started May 07 02:07:58 PM PDT 24
Finished May 07 02:08:02 PM PDT 24
Peak memory 215052 kb
Host smart-3dce599d-69d0-4314-badc-f65aeb305b60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140392000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2140392000
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.4070362722
Short name T942
Test name
Test status
Simulation time 49102577 ps
CPU time 1.61 seconds
Started May 07 02:07:56 PM PDT 24
Finished May 07 02:07:58 PM PDT 24
Peak memory 206808 kb
Host smart-b20b4615-aecd-4601-b284-4ad92fae0d9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070362722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.4070362722
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.352074999
Short name T962
Test name
Test status
Simulation time 35127003 ps
CPU time 1.03 seconds
Started May 07 02:07:57 PM PDT 24
Finished May 07 02:07:59 PM PDT 24
Peak memory 215044 kb
Host smart-a2eefba3-ce4f-4528-ae06-ae69f13df557
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352074999 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.352074999
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1879667185
Short name T234
Test name
Test status
Simulation time 46693647 ps
CPU time 0.82 seconds
Started May 07 02:07:55 PM PDT 24
Finished May 07 02:07:57 PM PDT 24
Peak memory 206540 kb
Host smart-b74b00ec-7392-4bc4-9a6e-778df2be2c8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879667185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1879667185
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.895500176
Short name T920
Test name
Test status
Simulation time 39425556 ps
CPU time 0.82 seconds
Started May 07 02:07:57 PM PDT 24
Finished May 07 02:07:59 PM PDT 24
Peak memory 206588 kb
Host smart-fb76e726-9582-4896-baf3-f43aad18706b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895500176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.895500176
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.936772391
Short name T937
Test name
Test status
Simulation time 310777336 ps
CPU time 1.34 seconds
Started May 07 02:07:58 PM PDT 24
Finished May 07 02:08:00 PM PDT 24
Peak memory 206796 kb
Host smart-191f2421-70d0-4842-9cf4-e2eff0193bb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936772391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.936772391
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.335827661
Short name T951
Test name
Test status
Simulation time 188677899 ps
CPU time 2.52 seconds
Started May 07 02:07:58 PM PDT 24
Finished May 07 02:08:01 PM PDT 24
Peak memory 215036 kb
Host smart-290896ff-c1d1-4456-85cd-a85d18ae659b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335827661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.335827661
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2348489516
Short name T252
Test name
Test status
Simulation time 244826744 ps
CPU time 1.49 seconds
Started May 07 02:08:04 PM PDT 24
Finished May 07 02:08:07 PM PDT 24
Peak memory 206840 kb
Host smart-4658cea1-62bb-4a8e-9291-936f484494d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348489516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2348489516
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.991018979
Short name T936
Test name
Test status
Simulation time 29364007 ps
CPU time 1.38 seconds
Started May 07 02:08:00 PM PDT 24
Finished May 07 02:08:03 PM PDT 24
Peak memory 215012 kb
Host smart-1858e9ff-3d42-444d-aa5d-f6334cb2ecbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991018979 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.991018979
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.249394701
Short name T947
Test name
Test status
Simulation time 20513921 ps
CPU time 0.9 seconds
Started May 07 02:08:02 PM PDT 24
Finished May 07 02:08:03 PM PDT 24
Peak memory 206472 kb
Host smart-cb6ca654-05f6-4bb0-a6f1-db8f2ad1adaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249394701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.249394701
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3544522430
Short name T905
Test name
Test status
Simulation time 15385572 ps
CPU time 0.9 seconds
Started May 07 02:08:01 PM PDT 24
Finished May 07 02:08:03 PM PDT 24
Peak memory 206684 kb
Host smart-7370386d-17ee-43aa-9fd9-dcd5b3bd2c7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544522430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3544522430
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2767462959
Short name T946
Test name
Test status
Simulation time 68259396 ps
CPU time 1.39 seconds
Started May 07 02:08:01 PM PDT 24
Finished May 07 02:08:04 PM PDT 24
Peak memory 206764 kb
Host smart-82838d8c-e611-4b06-986a-60247aaad57b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767462959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2767462959
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2728929267
Short name T850
Test name
Test status
Simulation time 250704370 ps
CPU time 2.55 seconds
Started May 07 02:08:04 PM PDT 24
Finished May 07 02:08:07 PM PDT 24
Peak memory 214988 kb
Host smart-9b364e8d-b9e9-4a85-ab5f-98f91426ef94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728929267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2728929267
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.27069402
Short name T925
Test name
Test status
Simulation time 115285792 ps
CPU time 3 seconds
Started May 07 02:08:04 PM PDT 24
Finished May 07 02:08:08 PM PDT 24
Peak memory 214984 kb
Host smart-6be0c2f2-c4b0-4117-8988-9902ca4f774f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27069402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.27069402
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.401128525
Short name T939
Test name
Test status
Simulation time 72126773 ps
CPU time 1.08 seconds
Started May 07 02:07:20 PM PDT 24
Finished May 07 02:07:22 PM PDT 24
Peak memory 206860 kb
Host smart-5f5602c7-8fa6-4a5d-a9a9-c949089c97a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401128525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.401128525
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4060326424
Short name T226
Test name
Test status
Simulation time 1248937431 ps
CPU time 6.41 seconds
Started May 07 02:07:21 PM PDT 24
Finished May 07 02:07:28 PM PDT 24
Peak memory 206796 kb
Host smart-0c6db56a-c42d-433c-b7c5-8580f6f3e327
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060326424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.4060326424
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.388460897
Short name T886
Test name
Test status
Simulation time 15517682 ps
CPU time 0.9 seconds
Started May 07 02:07:18 PM PDT 24
Finished May 07 02:07:20 PM PDT 24
Peak memory 206744 kb
Host smart-5623aa8c-f2fb-40f9-8630-5f51c869f34e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388460897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.388460897
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2793533561
Short name T957
Test name
Test status
Simulation time 80126943 ps
CPU time 1.14 seconds
Started May 07 02:07:18 PM PDT 24
Finished May 07 02:07:20 PM PDT 24
Peak memory 216268 kb
Host smart-349118e8-65aa-497c-aa30-bd7615e60355
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793533561 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2793533561
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2351666801
Short name T228
Test name
Test status
Simulation time 15249182 ps
CPU time 0.89 seconds
Started May 07 02:07:22 PM PDT 24
Finished May 07 02:07:23 PM PDT 24
Peak memory 206756 kb
Host smart-07d99296-d70e-4d2f-8c7b-ac1ccb99db31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351666801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2351666801
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.4217807910
Short name T887
Test name
Test status
Simulation time 42089409 ps
CPU time 0.78 seconds
Started May 07 02:07:18 PM PDT 24
Finished May 07 02:07:19 PM PDT 24
Peak memory 206676 kb
Host smart-bf6dbb58-7a0d-4e5f-afd0-795cc455f2b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217807910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.4217807910
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.428538797
Short name T222
Test name
Test status
Simulation time 25743396 ps
CPU time 1.17 seconds
Started May 07 02:07:19 PM PDT 24
Finished May 07 02:07:21 PM PDT 24
Peak memory 206760 kb
Host smart-4018d7e1-f02d-4eb0-b7d2-d23eca6657e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428538797 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out
standing.428538797
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.4266816422
Short name T923
Test name
Test status
Simulation time 103495973 ps
CPU time 1.96 seconds
Started May 07 02:07:13 PM PDT 24
Finished May 07 02:07:16 PM PDT 24
Peak memory 215024 kb
Host smart-328f9d8d-f82f-499b-80eb-9a0a9e486f06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266816422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.4266816422
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4027978826
Short name T877
Test name
Test status
Simulation time 337253636 ps
CPU time 2.36 seconds
Started May 07 02:07:15 PM PDT 24
Finished May 07 02:07:18 PM PDT 24
Peak memory 215004 kb
Host smart-ac096292-0440-47df-b751-4aba8ed0bcc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027978826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.4027978826
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3465256887
Short name T857
Test name
Test status
Simulation time 14136055 ps
CPU time 0.87 seconds
Started May 07 02:08:02 PM PDT 24
Finished May 07 02:08:04 PM PDT 24
Peak memory 206692 kb
Host smart-6a3e59d2-e75a-45d6-bce4-f132fc16cc78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465256887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3465256887
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3379909769
Short name T902
Test name
Test status
Simulation time 36953346 ps
CPU time 0.78 seconds
Started May 07 02:08:01 PM PDT 24
Finished May 07 02:08:03 PM PDT 24
Peak memory 206476 kb
Host smart-e0a9a3a7-4e0c-4e81-8c92-b9dea406f21c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379909769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3379909769
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1591001975
Short name T945
Test name
Test status
Simulation time 18567252 ps
CPU time 0.78 seconds
Started May 07 02:08:06 PM PDT 24
Finished May 07 02:08:07 PM PDT 24
Peak memory 206496 kb
Host smart-6448daf9-d3bb-4d22-9946-578754db4911
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591001975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1591001975
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3401531126
Short name T847
Test name
Test status
Simulation time 22881054 ps
CPU time 0.84 seconds
Started May 07 02:08:00 PM PDT 24
Finished May 07 02:08:02 PM PDT 24
Peak memory 206696 kb
Host smart-aec1c4b9-2500-4d0d-84dd-c3ad437c7e8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401531126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3401531126
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1658851228
Short name T841
Test name
Test status
Simulation time 23408383 ps
CPU time 0.87 seconds
Started May 07 02:08:04 PM PDT 24
Finished May 07 02:08:05 PM PDT 24
Peak memory 206796 kb
Host smart-8032c309-8173-4bd4-9072-365fb5512f9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658851228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1658851228
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1917826603
Short name T863
Test name
Test status
Simulation time 19985972 ps
CPU time 0.91 seconds
Started May 07 02:08:03 PM PDT 24
Finished May 07 02:08:05 PM PDT 24
Peak memory 206732 kb
Host smart-7f66d27a-37bd-492a-bb45-32e3084fd140
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917826603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1917826603
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2654237660
Short name T871
Test name
Test status
Simulation time 39614396 ps
CPU time 0.88 seconds
Started May 07 02:08:03 PM PDT 24
Finished May 07 02:08:05 PM PDT 24
Peak memory 206696 kb
Host smart-dea97a9b-5b88-4a71-9a0e-ec4facc15a7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654237660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2654237660
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1068879990
Short name T892
Test name
Test status
Simulation time 11658346 ps
CPU time 0.82 seconds
Started May 07 02:08:06 PM PDT 24
Finished May 07 02:08:07 PM PDT 24
Peak memory 206692 kb
Host smart-f4b26b9d-c063-4d2e-a5a9-12b857579b32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068879990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1068879990
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.775142481
Short name T865
Test name
Test status
Simulation time 12987545 ps
CPU time 0.85 seconds
Started May 07 02:08:03 PM PDT 24
Finished May 07 02:08:05 PM PDT 24
Peak memory 206696 kb
Host smart-f78d8050-6553-41a3-a689-c8f01377432c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775142481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.775142481
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3805992635
Short name T950
Test name
Test status
Simulation time 11331873 ps
CPU time 0.84 seconds
Started May 07 02:08:02 PM PDT 24
Finished May 07 02:08:04 PM PDT 24
Peak memory 206632 kb
Host smart-ecc4da1c-0e1d-4fbe-aa36-9e11619d92d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805992635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3805992635
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.790175778
Short name T227
Test name
Test status
Simulation time 32822807 ps
CPU time 1.43 seconds
Started May 07 02:07:25 PM PDT 24
Finished May 07 02:07:27 PM PDT 24
Peak memory 206660 kb
Host smart-c04d7d8f-63e9-4e62-bcd3-eab6378a6630
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790175778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.790175778
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2066195371
Short name T881
Test name
Test status
Simulation time 313967987 ps
CPU time 2.08 seconds
Started May 07 02:07:27 PM PDT 24
Finished May 07 02:07:30 PM PDT 24
Peak memory 206732 kb
Host smart-2884ac7c-d1fd-41bf-845f-4a15dc8f81d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066195371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2066195371
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.865382313
Short name T230
Test name
Test status
Simulation time 17082655 ps
CPU time 0.8 seconds
Started May 07 02:07:24 PM PDT 24
Finished May 07 02:07:26 PM PDT 24
Peak memory 206428 kb
Host smart-afc91c2f-0115-4992-a8ed-7861a8e895bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865382313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.865382313
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.4053690202
Short name T961
Test name
Test status
Simulation time 328078222 ps
CPU time 1.23 seconds
Started May 07 02:07:25 PM PDT 24
Finished May 07 02:07:27 PM PDT 24
Peak memory 215004 kb
Host smart-8bf93079-3c5a-4f72-ba2c-eba04964e529
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053690202 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.4053690202
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.690399388
Short name T229
Test name
Test status
Simulation time 15446925 ps
CPU time 0.88 seconds
Started May 07 02:07:25 PM PDT 24
Finished May 07 02:07:27 PM PDT 24
Peak memory 206676 kb
Host smart-4ed73ed3-98c1-422f-aa8e-232925485101
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690399388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.690399388
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.472815563
Short name T918
Test name
Test status
Simulation time 109059743 ps
CPU time 0.95 seconds
Started May 07 02:07:19 PM PDT 24
Finished May 07 02:07:20 PM PDT 24
Peak memory 206636 kb
Host smart-e4c3883a-c174-468b-9a1c-8e4fafae097d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472815563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.472815563
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1213762959
Short name T899
Test name
Test status
Simulation time 19049474 ps
CPU time 1.17 seconds
Started May 07 02:07:27 PM PDT 24
Finished May 07 02:07:29 PM PDT 24
Peak memory 206724 kb
Host smart-7926d7f8-bfee-4ebb-859e-ecac39e20ddc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213762959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1213762959
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.4120684198
Short name T852
Test name
Test status
Simulation time 93483905 ps
CPU time 1.92 seconds
Started May 07 02:07:22 PM PDT 24
Finished May 07 02:07:24 PM PDT 24
Peak memory 214948 kb
Host smart-27ca9848-61a8-42c2-b541-e8dc282c1733
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120684198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.4120684198
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2391777163
Short name T926
Test name
Test status
Simulation time 150132546 ps
CPU time 1.48 seconds
Started May 07 02:07:19 PM PDT 24
Finished May 07 02:07:22 PM PDT 24
Peak memory 215000 kb
Host smart-321a6d51-735a-409a-b14f-e6d5e5d66c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391777163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2391777163
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3638922916
Short name T856
Test name
Test status
Simulation time 15573308 ps
CPU time 0.89 seconds
Started May 07 02:08:01 PM PDT 24
Finished May 07 02:08:03 PM PDT 24
Peak memory 206744 kb
Host smart-35aaf4ef-c661-4588-84ea-52318ec42b4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638922916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3638922916
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2926385664
Short name T932
Test name
Test status
Simulation time 19434742 ps
CPU time 0.97 seconds
Started May 07 02:08:01 PM PDT 24
Finished May 07 02:08:03 PM PDT 24
Peak memory 206680 kb
Host smart-70907bd9-f9c5-4aac-9af8-56ae72f81251
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926385664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2926385664
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2722917637
Short name T843
Test name
Test status
Simulation time 11506710 ps
CPU time 0.87 seconds
Started May 07 02:08:14 PM PDT 24
Finished May 07 02:08:16 PM PDT 24
Peak memory 206456 kb
Host smart-39e8e4bf-2fa7-4b34-9db8-c2dd02033062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722917637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2722917637
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.231701612
Short name T853
Test name
Test status
Simulation time 22028829 ps
CPU time 0.84 seconds
Started May 07 02:08:09 PM PDT 24
Finished May 07 02:08:11 PM PDT 24
Peak memory 206448 kb
Host smart-7db22808-a840-485a-9b10-17ddad4a405f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231701612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.231701612
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.228070063
Short name T912
Test name
Test status
Simulation time 31714402 ps
CPU time 0.77 seconds
Started May 07 02:08:07 PM PDT 24
Finished May 07 02:08:08 PM PDT 24
Peak memory 206484 kb
Host smart-5849a709-9123-4156-92d0-44e0170f862a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228070063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.228070063
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2708483448
Short name T896
Test name
Test status
Simulation time 12595778 ps
CPU time 0.84 seconds
Started May 07 02:08:09 PM PDT 24
Finished May 07 02:08:11 PM PDT 24
Peak memory 206692 kb
Host smart-0634fd0c-f624-4020-ae82-8ed3180605d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708483448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2708483448
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3006399764
Short name T872
Test name
Test status
Simulation time 37430192 ps
CPU time 0.79 seconds
Started May 07 02:08:08 PM PDT 24
Finished May 07 02:08:10 PM PDT 24
Peak memory 206480 kb
Host smart-cc4c73ea-afd1-4060-a3dc-7464922867cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006399764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3006399764
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.4050323454
Short name T927
Test name
Test status
Simulation time 44516205 ps
CPU time 0.89 seconds
Started May 07 02:08:08 PM PDT 24
Finished May 07 02:08:10 PM PDT 24
Peak memory 206828 kb
Host smart-d16c4164-fbd1-46e4-9556-501bdfabb2b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050323454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.4050323454
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.570758322
Short name T967
Test name
Test status
Simulation time 27944565 ps
CPU time 0.92 seconds
Started May 07 02:08:09 PM PDT 24
Finished May 07 02:08:11 PM PDT 24
Peak memory 206444 kb
Host smart-44ea09a9-31c4-4571-ba6d-8fc4e5bc3580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570758322 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.570758322
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1529683828
Short name T849
Test name
Test status
Simulation time 21746728 ps
CPU time 0.87 seconds
Started May 07 02:08:09 PM PDT 24
Finished May 07 02:08:11 PM PDT 24
Peak memory 206656 kb
Host smart-630f380b-a340-4894-8bd1-4b869a4a00be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529683828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1529683828
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3629492338
Short name T250
Test name
Test status
Simulation time 29331985 ps
CPU time 1.03 seconds
Started May 07 02:07:34 PM PDT 24
Finished May 07 02:07:36 PM PDT 24
Peak memory 206768 kb
Host smart-fe7efed7-1b73-4536-a783-3e9c5633f2db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629492338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3629492338
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.268883848
Short name T949
Test name
Test status
Simulation time 312198647 ps
CPU time 6.03 seconds
Started May 07 02:07:31 PM PDT 24
Finished May 07 02:07:38 PM PDT 24
Peak memory 206800 kb
Host smart-003b48ea-7775-4c87-9b5b-69c207d0555c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268883848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.268883848
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.951773327
Short name T231
Test name
Test status
Simulation time 28115165 ps
CPU time 0.92 seconds
Started May 07 02:07:24 PM PDT 24
Finished May 07 02:07:25 PM PDT 24
Peak memory 206744 kb
Host smart-7354d59e-0305-4c04-b7be-9c9e93bdba70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951773327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.951773327
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.709975183
Short name T848
Test name
Test status
Simulation time 25391532 ps
CPU time 1.23 seconds
Started May 07 02:07:34 PM PDT 24
Finished May 07 02:07:36 PM PDT 24
Peak memory 214932 kb
Host smart-9e670bbb-6b93-4e09-95a8-ee173015c37a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709975183 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.709975183
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.4085464895
Short name T971
Test name
Test status
Simulation time 57502110 ps
CPU time 0.93 seconds
Started May 07 02:07:32 PM PDT 24
Finished May 07 02:07:34 PM PDT 24
Peak memory 206784 kb
Host smart-635f7d6f-1336-47a7-beb9-a296526ebaf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085464895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.4085464895
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1010589976
Short name T960
Test name
Test status
Simulation time 14173591 ps
CPU time 0.89 seconds
Started May 07 02:07:27 PM PDT 24
Finished May 07 02:07:29 PM PDT 24
Peak memory 206656 kb
Host smart-f9e2a5fd-558d-44c2-9b23-ef215b82c040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010589976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1010589976
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.838336212
Short name T240
Test name
Test status
Simulation time 61598546 ps
CPU time 0.87 seconds
Started May 07 02:07:33 PM PDT 24
Finished May 07 02:07:35 PM PDT 24
Peak memory 206724 kb
Host smart-4227beca-3b49-45cd-a93b-a0d4c78dd468
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838336212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.838336212
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.291426096
Short name T840
Test name
Test status
Simulation time 278548988 ps
CPU time 2.8 seconds
Started May 07 02:07:26 PM PDT 24
Finished May 07 02:07:29 PM PDT 24
Peak memory 214964 kb
Host smart-f7b068f1-1560-40c8-b8d2-293d71bdbc8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291426096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.291426096
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2437751879
Short name T934
Test name
Test status
Simulation time 133587492 ps
CPU time 2.13 seconds
Started May 07 02:07:24 PM PDT 24
Finished May 07 02:07:27 PM PDT 24
Peak memory 206848 kb
Host smart-902b9ea1-33e4-4fc0-85cf-15965c060664
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437751879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2437751879
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3963917921
Short name T928
Test name
Test status
Simulation time 54695817 ps
CPU time 0.9 seconds
Started May 07 02:08:08 PM PDT 24
Finished May 07 02:08:10 PM PDT 24
Peak memory 206676 kb
Host smart-32129491-0f02-4eb1-856c-cfd0e6a31f32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963917921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3963917921
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1203791358
Short name T888
Test name
Test status
Simulation time 17904758 ps
CPU time 0.96 seconds
Started May 07 02:08:08 PM PDT 24
Finished May 07 02:08:09 PM PDT 24
Peak memory 206676 kb
Host smart-4d13287c-b6fa-4dab-bef9-a387864ad29e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203791358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1203791358
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2872658462
Short name T966
Test name
Test status
Simulation time 31924989 ps
CPU time 0.77 seconds
Started May 07 02:08:09 PM PDT 24
Finished May 07 02:08:10 PM PDT 24
Peak memory 206448 kb
Host smart-45b5a101-ad03-40b3-99b9-76aefde0cc2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872658462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2872658462
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2613463287
Short name T861
Test name
Test status
Simulation time 13717587 ps
CPU time 0.87 seconds
Started May 07 02:08:14 PM PDT 24
Finished May 07 02:08:16 PM PDT 24
Peak memory 206668 kb
Host smart-b2415b15-ab77-40ea-afbd-eb30a26c3af4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613463287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2613463287
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3670299956
Short name T895
Test name
Test status
Simulation time 15224071 ps
CPU time 0.89 seconds
Started May 07 02:08:07 PM PDT 24
Finished May 07 02:08:08 PM PDT 24
Peak memory 206656 kb
Host smart-de2302a7-dca1-45ba-8b3f-1c2e89ea2884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670299956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3670299956
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1395478228
Short name T858
Test name
Test status
Simulation time 44156193 ps
CPU time 0.85 seconds
Started May 07 02:08:14 PM PDT 24
Finished May 07 02:08:16 PM PDT 24
Peak memory 206440 kb
Host smart-d399b7c3-9c86-4709-b206-1081a97f1374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395478228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1395478228
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.461472706
Short name T904
Test name
Test status
Simulation time 15887338 ps
CPU time 0.93 seconds
Started May 07 02:08:08 PM PDT 24
Finished May 07 02:08:10 PM PDT 24
Peak memory 206620 kb
Host smart-cec209ba-1082-41e7-879e-6b62bdfd5ad8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461472706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.461472706
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.4210501801
Short name T910
Test name
Test status
Simulation time 18135931 ps
CPU time 0.9 seconds
Started May 07 02:08:13 PM PDT 24
Finished May 07 02:08:15 PM PDT 24
Peak memory 206688 kb
Host smart-51a66bce-0f88-4234-9b40-012fe64921f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210501801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.4210501801
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.748733418
Short name T880
Test name
Test status
Simulation time 15134771 ps
CPU time 0.89 seconds
Started May 07 02:08:15 PM PDT 24
Finished May 07 02:08:17 PM PDT 24
Peak memory 206692 kb
Host smart-e6d10448-1c22-4b0c-b793-e3d525b7f794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748733418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.748733418
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.423332179
Short name T956
Test name
Test status
Simulation time 45410806 ps
CPU time 0.82 seconds
Started May 07 02:08:13 PM PDT 24
Finished May 07 02:08:15 PM PDT 24
Peak memory 206684 kb
Host smart-1794cb87-08b4-4bed-a09f-7f8fa09a89f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423332179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.423332179
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.646725611
Short name T901
Test name
Test status
Simulation time 95634829 ps
CPU time 0.94 seconds
Started May 07 02:07:32 PM PDT 24
Finished May 07 02:07:33 PM PDT 24
Peak memory 206828 kb
Host smart-0ca2075d-3c17-4367-8a6f-f8b4948bc2ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646725611 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.646725611
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1896201782
Short name T935
Test name
Test status
Simulation time 40184705 ps
CPU time 0.84 seconds
Started May 07 02:07:32 PM PDT 24
Finished May 07 02:07:34 PM PDT 24
Peak memory 206508 kb
Host smart-d0a04b75-f270-43d0-8927-b3627d5ac7f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896201782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1896201782
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.155373764
Short name T876
Test name
Test status
Simulation time 51837953 ps
CPU time 0.89 seconds
Started May 07 02:07:33 PM PDT 24
Finished May 07 02:07:35 PM PDT 24
Peak memory 206692 kb
Host smart-97c01776-8663-4579-aa3a-21df8a04d696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155373764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.155373764
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1520769381
Short name T919
Test name
Test status
Simulation time 52543610 ps
CPU time 0.99 seconds
Started May 07 02:07:32 PM PDT 24
Finished May 07 02:07:34 PM PDT 24
Peak memory 206768 kb
Host smart-d8dea549-2170-4402-ab4f-101100859aca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520769381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1520769381
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.4240544658
Short name T842
Test name
Test status
Simulation time 78840934 ps
CPU time 1.7 seconds
Started May 07 02:07:31 PM PDT 24
Finished May 07 02:07:33 PM PDT 24
Peak memory 215004 kb
Host smart-c60a7e41-32b3-432d-afb7-83d031197c0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240544658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.4240544658
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.4106458913
Short name T263
Test name
Test status
Simulation time 287197133 ps
CPU time 3.3 seconds
Started May 07 02:07:30 PM PDT 24
Finished May 07 02:07:35 PM PDT 24
Peak memory 206740 kb
Host smart-5c041090-44a0-4246-b61f-97b438bd2cd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106458913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.4106458913
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.109578533
Short name T846
Test name
Test status
Simulation time 84776772 ps
CPU time 1.6 seconds
Started May 07 02:07:38 PM PDT 24
Finished May 07 02:07:40 PM PDT 24
Peak memory 215024 kb
Host smart-811092c9-0e6b-4ef6-bb29-99a541fb966e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109578533 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.109578533
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.995649485
Short name T903
Test name
Test status
Simulation time 38054993 ps
CPU time 0.82 seconds
Started May 07 02:07:40 PM PDT 24
Finished May 07 02:07:41 PM PDT 24
Peak memory 206528 kb
Host smart-5246bb02-7c43-4d29-bd06-294be9fe5c65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995649485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.995649485
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2609315868
Short name T885
Test name
Test status
Simulation time 13061620 ps
CPU time 0.88 seconds
Started May 07 02:07:39 PM PDT 24
Finished May 07 02:07:40 PM PDT 24
Peak memory 206692 kb
Host smart-9f5249db-a99a-4869-8564-534cf92ffc87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609315868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2609315868
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.4244292578
Short name T944
Test name
Test status
Simulation time 43353998 ps
CPU time 1.06 seconds
Started May 07 02:07:37 PM PDT 24
Finished May 07 02:07:38 PM PDT 24
Peak memory 206812 kb
Host smart-bdcb549a-49d7-427b-a4be-9e75a713a68e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244292578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.4244292578
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3482760790
Short name T900
Test name
Test status
Simulation time 32621047 ps
CPU time 2.03 seconds
Started May 07 02:07:38 PM PDT 24
Finished May 07 02:07:41 PM PDT 24
Peak memory 214908 kb
Host smart-22b3e617-19e7-4c09-9e05-1533958af6af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482760790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3482760790
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.154573016
Short name T851
Test name
Test status
Simulation time 269296092 ps
CPU time 2.13 seconds
Started May 07 02:07:37 PM PDT 24
Finished May 07 02:07:39 PM PDT 24
Peak memory 206764 kb
Host smart-138c7253-d0c0-48ee-8127-3f9de6579752
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154573016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.154573016
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3854057030
Short name T879
Test name
Test status
Simulation time 88906136 ps
CPU time 1.2 seconds
Started May 07 02:07:35 PM PDT 24
Finished May 07 02:07:37 PM PDT 24
Peak memory 215024 kb
Host smart-4fcab226-f9b8-4563-be01-d395beeb536e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854057030 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3854057030
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1308089466
Short name T943
Test name
Test status
Simulation time 13751851 ps
CPU time 0.87 seconds
Started May 07 02:07:41 PM PDT 24
Finished May 07 02:07:43 PM PDT 24
Peak memory 206688 kb
Host smart-6d351d0b-f928-45c9-947c-5b968cdd6e04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308089466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1308089466
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3723792774
Short name T916
Test name
Test status
Simulation time 17964640 ps
CPU time 0.92 seconds
Started May 07 02:07:36 PM PDT 24
Finished May 07 02:07:37 PM PDT 24
Peak memory 206664 kb
Host smart-53b2ddfb-89a3-4a4b-b168-3a71ba1a21b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723792774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3723792774
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2944229136
Short name T924
Test name
Test status
Simulation time 21850111 ps
CPU time 1.08 seconds
Started May 07 02:07:38 PM PDT 24
Finished May 07 02:07:40 PM PDT 24
Peak memory 206764 kb
Host smart-9f46033c-d9c7-42f5-9363-2edc11520e0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944229136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2944229136
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3935503947
Short name T854
Test name
Test status
Simulation time 41562732 ps
CPU time 1.53 seconds
Started May 07 02:07:37 PM PDT 24
Finished May 07 02:07:40 PM PDT 24
Peak memory 214956 kb
Host smart-17416477-138d-4487-b1da-34872a8e645b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935503947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3935503947
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.4236737293
Short name T931
Test name
Test status
Simulation time 301731497 ps
CPU time 2.32 seconds
Started May 07 02:07:36 PM PDT 24
Finished May 07 02:07:39 PM PDT 24
Peak memory 207040 kb
Host smart-b45aa04f-152e-4579-baa9-54f36813db1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236737293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.4236737293
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3601918076
Short name T970
Test name
Test status
Simulation time 119796547 ps
CPU time 1.27 seconds
Started May 07 02:07:44 PM PDT 24
Finished May 07 02:07:46 PM PDT 24
Peak memory 214988 kb
Host smart-a057b955-c9fd-454e-8ec1-044b66f75f03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601918076 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3601918076
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2391527279
Short name T223
Test name
Test status
Simulation time 37367528 ps
CPU time 0.84 seconds
Started May 07 02:07:47 PM PDT 24
Finished May 07 02:07:48 PM PDT 24
Peak memory 206760 kb
Host smart-c8e64939-af32-4a1c-92c6-e6e2071930ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391527279 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2391527279
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1418169589
Short name T859
Test name
Test status
Simulation time 46095764 ps
CPU time 0.86 seconds
Started May 07 02:07:43 PM PDT 24
Finished May 07 02:07:44 PM PDT 24
Peak memory 206632 kb
Host smart-8586c21c-f9e3-483a-bdb7-ed63d82a9bfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418169589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1418169589
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1051038579
Short name T893
Test name
Test status
Simulation time 67838587 ps
CPU time 0.87 seconds
Started May 07 02:07:50 PM PDT 24
Finished May 07 02:07:52 PM PDT 24
Peak memory 206692 kb
Host smart-41d8d4f6-b244-4661-92ab-9515dcb15cdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051038579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1051038579
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.4047130427
Short name T869
Test name
Test status
Simulation time 46079232 ps
CPU time 1.9 seconds
Started May 07 02:07:39 PM PDT 24
Finished May 07 02:07:42 PM PDT 24
Peak memory 214948 kb
Host smart-7e21c51f-8346-4722-9aea-4607a5bcfba0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047130427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.4047130427
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1416090231
Short name T952
Test name
Test status
Simulation time 158490279 ps
CPU time 1.53 seconds
Started May 07 02:07:44 PM PDT 24
Finished May 07 02:07:46 PM PDT 24
Peak memory 206756 kb
Host smart-ea1e088d-fb6a-4ba9-ab1f-d4bf1278f832
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416090231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1416090231
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1441930083
Short name T968
Test name
Test status
Simulation time 41308341 ps
CPU time 1.33 seconds
Started May 07 02:07:51 PM PDT 24
Finished May 07 02:07:54 PM PDT 24
Peak memory 214964 kb
Host smart-6c95ab9d-c03e-4854-b62d-df22ce106c14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441930083 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1441930083
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.4102175048
Short name T238
Test name
Test status
Simulation time 14758982 ps
CPU time 0.89 seconds
Started May 07 02:07:48 PM PDT 24
Finished May 07 02:07:50 PM PDT 24
Peak memory 206756 kb
Host smart-44c8eb24-7a6f-4a1e-808d-09283c81d735
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102175048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.4102175048
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3491494595
Short name T844
Test name
Test status
Simulation time 35297863 ps
CPU time 0.84 seconds
Started May 07 02:07:47 PM PDT 24
Finished May 07 02:07:49 PM PDT 24
Peak memory 206684 kb
Host smart-dfd725be-4641-449e-a75f-5781bc275d84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491494595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3491494595
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3435185934
Short name T913
Test name
Test status
Simulation time 78597527 ps
CPU time 1.08 seconds
Started May 07 02:07:45 PM PDT 24
Finished May 07 02:07:47 PM PDT 24
Peak memory 206732 kb
Host smart-168ee5c5-48eb-48f0-a4ed-1f3e2d79bd59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435185934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3435185934
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3920799815
Short name T882
Test name
Test status
Simulation time 68590594 ps
CPU time 2.47 seconds
Started May 07 02:07:44 PM PDT 24
Finished May 07 02:07:47 PM PDT 24
Peak memory 214936 kb
Host smart-d0af8fb9-0c21-4d9a-b5c9-e5e809a7e608
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920799815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3920799815
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.723720325
Short name T929
Test name
Test status
Simulation time 88003058 ps
CPU time 1.58 seconds
Started May 07 02:07:51 PM PDT 24
Finished May 07 02:07:54 PM PDT 24
Peak memory 214892 kb
Host smart-83a68396-b014-4093-bbe4-ea9fb6338395
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723720325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.723720325
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.1137608751
Short name T195
Test name
Test status
Simulation time 43644697 ps
CPU time 1.29 seconds
Started May 07 03:16:17 PM PDT 24
Finished May 07 03:16:20 PM PDT 24
Peak memory 215924 kb
Host smart-f5c805ee-9489-45f2-a83a-240353426684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137608751 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1137608751
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2716863181
Short name T77
Test name
Test status
Simulation time 18546881 ps
CPU time 0.86 seconds
Started May 07 03:16:15 PM PDT 24
Finished May 07 03:16:18 PM PDT 24
Peak memory 207148 kb
Host smart-1948befe-8069-4bbc-a089-7982083a0b4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716863181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2716863181
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.1875915657
Short name T173
Test name
Test status
Simulation time 21447974 ps
CPU time 0.87 seconds
Started May 07 03:16:14 PM PDT 24
Finished May 07 03:16:17 PM PDT 24
Peak memory 216620 kb
Host smart-f94c1dba-8e4b-4c96-adce-e389482f75d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875915657 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1875915657
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1630237374
Short name T734
Test name
Test status
Simulation time 62465348 ps
CPU time 1.12 seconds
Started May 07 03:16:14 PM PDT 24
Finished May 07 03:16:18 PM PDT 24
Peak memory 218312 kb
Host smart-2f15a4c4-48b6-40a8-9d59-a89996b68db7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630237374 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1630237374
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.807199101
Short name T590
Test name
Test status
Simulation time 23513200 ps
CPU time 0.9 seconds
Started May 07 03:16:15 PM PDT 24
Finished May 07 03:16:18 PM PDT 24
Peak memory 218672 kb
Host smart-17be5c2f-6f2a-4b14-b3ac-90ab243b182b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807199101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.807199101
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.656127086
Short name T333
Test name
Test status
Simulation time 70046520 ps
CPU time 1.42 seconds
Started May 07 03:16:10 PM PDT 24
Finished May 07 03:16:13 PM PDT 24
Peak memory 218928 kb
Host smart-1592d771-f9ba-4dc6-aed6-58474a5cfcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656127086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.656127086
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1311119789
Short name T33
Test name
Test status
Simulation time 21289288 ps
CPU time 1.09 seconds
Started May 07 03:16:13 PM PDT 24
Finished May 07 03:16:16 PM PDT 24
Peak memory 216292 kb
Host smart-e6d646e5-d9e4-4745-a7e3-d61f8cadd703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311119789 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1311119789
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.3302432041
Short name T638
Test name
Test status
Simulation time 18334417 ps
CPU time 1.03 seconds
Started May 07 03:16:10 PM PDT 24
Finished May 07 03:16:12 PM PDT 24
Peak memory 207448 kb
Host smart-7162da87-35d9-4916-bb25-a0613d504164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302432041 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3302432041
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3648818924
Short name T66
Test name
Test status
Simulation time 472578643 ps
CPU time 4.4 seconds
Started May 07 03:16:15 PM PDT 24
Finished May 07 03:16:22 PM PDT 24
Peak memory 240176 kb
Host smart-d2b1b0ee-44d2-45e9-a7f4-646f952bfa61
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648818924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3648818924
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.935219879
Short name T468
Test name
Test status
Simulation time 48151809 ps
CPU time 0.89 seconds
Started May 07 03:16:12 PM PDT 24
Finished May 07 03:16:14 PM PDT 24
Peak memory 215660 kb
Host smart-0ce63cab-6679-4bcf-a228-258e24a43e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935219879 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.935219879
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2782704066
Short name T820
Test name
Test status
Simulation time 80151305 ps
CPU time 2.04 seconds
Started May 07 03:16:10 PM PDT 24
Finished May 07 03:16:14 PM PDT 24
Peak memory 215628 kb
Host smart-7e2ac3b5-ab1d-4072-b96f-2868bbf138df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782704066 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2782704066
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1871411279
Short name T789
Test name
Test status
Simulation time 133167651403 ps
CPU time 373.98 seconds
Started May 07 03:16:09 PM PDT 24
Finished May 07 03:22:25 PM PDT 24
Peak memory 219252 kb
Host smart-b3733596-d33e-479f-bb8a-be1219a341c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871411279 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1871411279
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.109831865
Short name T493
Test name
Test status
Simulation time 25890510 ps
CPU time 1.22 seconds
Started May 07 03:16:16 PM PDT 24
Finished May 07 03:16:20 PM PDT 24
Peak memory 216080 kb
Host smart-d25bcb43-cb45-4949-83a1-04d0f9f63099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109831865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.109831865
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.4085417795
Short name T318
Test name
Test status
Simulation time 41287634 ps
CPU time 0.86 seconds
Started May 07 03:16:16 PM PDT 24
Finished May 07 03:16:19 PM PDT 24
Peak memory 206800 kb
Host smart-bcce8a9e-e52e-4b0f-a7a8-b9a0762161bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085417795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.4085417795
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.4195495559
Short name T360
Test name
Test status
Simulation time 16005544 ps
CPU time 0.81 seconds
Started May 07 03:16:14 PM PDT 24
Finished May 07 03:16:17 PM PDT 24
Peak memory 216256 kb
Host smart-3fefd245-361b-4962-b783-9c06716ab37a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195495559 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.4195495559
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.2922515819
Short name T60
Test name
Test status
Simulation time 24441175 ps
CPU time 1.09 seconds
Started May 07 03:16:14 PM PDT 24
Finished May 07 03:16:17 PM PDT 24
Peak memory 224528 kb
Host smart-19386b1f-bb99-4cb8-8aa7-b51892cf1898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922515819 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2922515819
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.4144669097
Short name T568
Test name
Test status
Simulation time 92145596 ps
CPU time 1.15 seconds
Started May 07 03:16:16 PM PDT 24
Finished May 07 03:16:19 PM PDT 24
Peak memory 218628 kb
Host smart-c9923d06-c0d9-4893-9db6-4a4051de8a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144669097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.4144669097
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.218626264
Short name T36
Test name
Test status
Simulation time 56872131 ps
CPU time 0.88 seconds
Started May 07 03:16:15 PM PDT 24
Finished May 07 03:16:18 PM PDT 24
Peak memory 215640 kb
Host smart-bf8b4bf0-2d43-41aa-b456-1a5cd7ce3030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218626264 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.218626264
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_smoke.814386970
Short name T369
Test name
Test status
Simulation time 50358120 ps
CPU time 1.01 seconds
Started May 07 03:16:15 PM PDT 24
Finished May 07 03:16:18 PM PDT 24
Peak memory 215668 kb
Host smart-070e4401-bab6-4fc3-be16-52b8ca03c08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814386970 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.814386970
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2097928569
Short name T567
Test name
Test status
Simulation time 171199744 ps
CPU time 1.8 seconds
Started May 07 03:16:16 PM PDT 24
Finished May 07 03:16:20 PM PDT 24
Peak memory 215648 kb
Host smart-c9ce9657-5206-4c96-a961-a00a27741c31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097928569 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2097928569
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.232923235
Short name T824
Test name
Test status
Simulation time 19520308519 ps
CPU time 366.07 seconds
Started May 07 03:16:17 PM PDT 24
Finished May 07 03:22:25 PM PDT 24
Peak memory 219752 kb
Host smart-aa50941d-c459-4d36-8d03-b35e99aa90f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232923235 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.232923235
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.2996689182
Short name T682
Test name
Test status
Simulation time 68025607 ps
CPU time 0.92 seconds
Started May 07 03:16:42 PM PDT 24
Finished May 07 03:16:44 PM PDT 24
Peak memory 207028 kb
Host smart-a7bb719c-2003-4d71-8f6e-1adcf84725d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996689182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2996689182
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_err.1425531710
Short name T602
Test name
Test status
Simulation time 28612745 ps
CPU time 0.91 seconds
Started May 07 03:16:38 PM PDT 24
Finished May 07 03:16:40 PM PDT 24
Peak memory 218612 kb
Host smart-01736507-c26e-4189-b6a2-befac95261d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425531710 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1425531710
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.286650332
Short name T626
Test name
Test status
Simulation time 144816710 ps
CPU time 1.02 seconds
Started May 07 03:16:41 PM PDT 24
Finished May 07 03:16:44 PM PDT 24
Peak memory 217348 kb
Host smart-0188e501-1472-4d8a-8eff-fde43f80547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286650332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.286650332
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1503907711
Short name T311
Test name
Test status
Simulation time 31637768 ps
CPU time 0.91 seconds
Started May 07 03:16:48 PM PDT 24
Finished May 07 03:16:51 PM PDT 24
Peak memory 215936 kb
Host smart-fccd64af-13e3-4d97-b85f-3bc4949ab09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503907711 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1503907711
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.720523989
Short name T372
Test name
Test status
Simulation time 30284477 ps
CPU time 0.93 seconds
Started May 07 03:16:42 PM PDT 24
Finished May 07 03:16:44 PM PDT 24
Peak memory 215608 kb
Host smart-162381be-b3ba-4577-a44b-6fe904dc5bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720523989 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.720523989
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2209700814
Short name T717
Test name
Test status
Simulation time 257368160 ps
CPU time 5.02 seconds
Started May 07 03:16:41 PM PDT 24
Finished May 07 03:16:48 PM PDT 24
Peak memory 217328 kb
Host smart-d53862ae-c5ec-433b-8754-50a19ea3d744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209700814 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2209700814
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.280448449
Short name T566
Test name
Test status
Simulation time 137510798136 ps
CPU time 883.05 seconds
Started May 07 03:16:41 PM PDT 24
Finished May 07 03:31:25 PM PDT 24
Peak memory 223164 kb
Host smart-ac581a52-e35b-4b42-abe3-3b213634bdeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280448449 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.280448449
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.1609006731
Short name T401
Test name
Test status
Simulation time 45854808 ps
CPU time 1.11 seconds
Started May 07 03:17:57 PM PDT 24
Finished May 07 03:17:59 PM PDT 24
Peak memory 217464 kb
Host smart-11e0918c-ee1a-46b5-841f-f1ddfdabda77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609006731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1609006731
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.3396751929
Short name T433
Test name
Test status
Simulation time 76505987 ps
CPU time 2.92 seconds
Started May 07 03:18:00 PM PDT 24
Finished May 07 03:18:04 PM PDT 24
Peak memory 220328 kb
Host smart-d14cba26-59b1-4ab5-8788-99247c90de51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396751929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3396751929
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.200553775
Short name T85
Test name
Test status
Simulation time 44627220 ps
CPU time 1.22 seconds
Started May 07 03:17:56 PM PDT 24
Finished May 07 03:17:59 PM PDT 24
Peak memory 217452 kb
Host smart-c08b9683-1fbc-45dd-85d5-367385a4c4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200553775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.200553775
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.1597065776
Short name T821
Test name
Test status
Simulation time 29731336 ps
CPU time 1.3 seconds
Started May 07 03:17:56 PM PDT 24
Finished May 07 03:17:58 PM PDT 24
Peak memory 215644 kb
Host smart-3fd61d13-3ebd-4d5f-9c59-903518cbbbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597065776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1597065776
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.2692177431
Short name T730
Test name
Test status
Simulation time 30403687 ps
CPU time 1.54 seconds
Started May 07 03:17:58 PM PDT 24
Finished May 07 03:18:01 PM PDT 24
Peak memory 218800 kb
Host smart-5b169faf-64d6-4e24-95ef-0538c71b9171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692177431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2692177431
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.3289785581
Short name T288
Test name
Test status
Simulation time 212611263 ps
CPU time 1.21 seconds
Started May 07 03:17:55 PM PDT 24
Finished May 07 03:17:58 PM PDT 24
Peak memory 217512 kb
Host smart-f0696dfb-5fd4-4e13-b21e-31362d666d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289785581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3289785581
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.4282510541
Short name T365
Test name
Test status
Simulation time 119182705 ps
CPU time 1.64 seconds
Started May 07 03:18:00 PM PDT 24
Finished May 07 03:18:03 PM PDT 24
Peak memory 220212 kb
Host smart-529e727b-974e-4c6a-b368-a7ee76b37f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282510541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.4282510541
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.2903111001
Short name T414
Test name
Test status
Simulation time 42350320 ps
CPU time 1.62 seconds
Started May 07 03:17:55 PM PDT 24
Finished May 07 03:17:58 PM PDT 24
Peak memory 218428 kb
Host smart-aa5da23c-ee24-453f-be61-afcbe0b63c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903111001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2903111001
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.3153695326
Short name T620
Test name
Test status
Simulation time 91379095 ps
CPU time 3.18 seconds
Started May 07 03:17:56 PM PDT 24
Finished May 07 03:18:00 PM PDT 24
Peak memory 220196 kb
Host smart-fe479aaf-876e-4eba-af4c-c693a2f6de35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153695326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3153695326
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.507873237
Short name T688
Test name
Test status
Simulation time 79992111 ps
CPU time 1.17 seconds
Started May 07 03:16:47 PM PDT 24
Finished May 07 03:16:50 PM PDT 24
Peak memory 216056 kb
Host smart-63e219a5-7c4d-47c7-a4f5-ef47a9e4781c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507873237 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.507873237
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.2871576149
Short name T346
Test name
Test status
Simulation time 168181881 ps
CPU time 0.95 seconds
Started May 07 03:16:49 PM PDT 24
Finished May 07 03:16:52 PM PDT 24
Peak memory 207012 kb
Host smart-6c8f9196-c75e-4122-bafe-2c4da3bc7f9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871576149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2871576149
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2371953670
Short name T86
Test name
Test status
Simulation time 153780913 ps
CPU time 0.98 seconds
Started May 07 03:16:47 PM PDT 24
Finished May 07 03:16:49 PM PDT 24
Peak memory 219876 kb
Host smart-6240f209-8664-4162-b924-ce1197dea78e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371953670 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2371953670
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.3494254334
Short name T366
Test name
Test status
Simulation time 24842667 ps
CPU time 0.95 seconds
Started May 07 03:16:45 PM PDT 24
Finished May 07 03:16:48 PM PDT 24
Peak memory 218956 kb
Host smart-0dfbd3c6-7c70-4505-96b9-1ae0895b2c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494254334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3494254334
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.388022154
Short name T445
Test name
Test status
Simulation time 49682388 ps
CPU time 1.29 seconds
Started May 07 03:16:41 PM PDT 24
Finished May 07 03:16:43 PM PDT 24
Peak memory 218664 kb
Host smart-b70d5f1d-7d7f-4e60-b6c1-7dd4af85e5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388022154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.388022154
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.3837554158
Short name T603
Test name
Test status
Simulation time 41685223 ps
CPU time 0.9 seconds
Started May 07 03:16:47 PM PDT 24
Finished May 07 03:16:49 PM PDT 24
Peak memory 216008 kb
Host smart-c6251161-cbcc-483d-98fa-940e7bb711e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837554158 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3837554158
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1313122750
Short name T634
Test name
Test status
Simulation time 50402869 ps
CPU time 0.99 seconds
Started May 07 03:16:40 PM PDT 24
Finished May 07 03:16:42 PM PDT 24
Peak memory 215748 kb
Host smart-fb282669-d437-41e3-a4ad-5ac2ad3fa1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313122750 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1313122750
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2474589625
Short name T810
Test name
Test status
Simulation time 204880063 ps
CPU time 4.47 seconds
Started May 07 03:16:48 PM PDT 24
Finished May 07 03:16:55 PM PDT 24
Peak memory 217416 kb
Host smart-e839b166-7ec8-40a7-905d-9b312cd56566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474589625 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2474589625
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3955289724
Short name T204
Test name
Test status
Simulation time 321203886717 ps
CPU time 1323.48 seconds
Started May 07 03:16:43 PM PDT 24
Finished May 07 03:38:47 PM PDT 24
Peak memory 223140 kb
Host smart-3d4324ee-b910-4f9f-8fb5-5f818214dc23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955289724 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3955289724
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.3755123038
Short name T362
Test name
Test status
Simulation time 95687153 ps
CPU time 1.8 seconds
Started May 07 03:18:00 PM PDT 24
Finished May 07 03:18:03 PM PDT 24
Peak memory 219972 kb
Host smart-26b8c9e9-5622-484f-b6b0-4d53664eedaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755123038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3755123038
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.1752532241
Short name T514
Test name
Test status
Simulation time 41571597 ps
CPU time 1.54 seconds
Started May 07 03:17:57 PM PDT 24
Finished May 07 03:17:59 PM PDT 24
Peak memory 215624 kb
Host smart-4fa6d3be-a782-4d91-8cc3-400163f7f198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752532241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1752532241
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.715748787
Short name T255
Test name
Test status
Simulation time 57777292 ps
CPU time 0.98 seconds
Started May 07 03:17:59 PM PDT 24
Finished May 07 03:18:01 PM PDT 24
Peak memory 217376 kb
Host smart-e2633244-7670-4f83-862d-a829d9e1f11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715748787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.715748787
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.1286783677
Short name T757
Test name
Test status
Simulation time 63490317 ps
CPU time 1.1 seconds
Started May 07 03:18:03 PM PDT 24
Finished May 07 03:18:05 PM PDT 24
Peak memory 220036 kb
Host smart-70007b65-a4ee-43c7-9ca1-ebbdad1b8848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286783677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1286783677
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.3106088033
Short name T505
Test name
Test status
Simulation time 54686369 ps
CPU time 1.86 seconds
Started May 07 03:18:04 PM PDT 24
Finished May 07 03:18:07 PM PDT 24
Peak memory 218476 kb
Host smart-1bca3fe7-6dfe-4888-ab02-500c6c2808c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106088033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3106088033
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.2089158244
Short name T766
Test name
Test status
Simulation time 321782430 ps
CPU time 3.66 seconds
Started May 07 03:18:03 PM PDT 24
Finished May 07 03:18:08 PM PDT 24
Peak memory 219964 kb
Host smart-bfb960f3-04b8-4bab-a0dd-4c4308199fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089158244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2089158244
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.2394643364
Short name T796
Test name
Test status
Simulation time 50907831 ps
CPU time 1.74 seconds
Started May 07 03:18:01 PM PDT 24
Finished May 07 03:18:05 PM PDT 24
Peak memory 218456 kb
Host smart-132467d0-1737-4829-a240-54c0ec2f4311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394643364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2394643364
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2763919641
Short name T297
Test name
Test status
Simulation time 82432203 ps
CPU time 1.21 seconds
Started May 07 03:16:46 PM PDT 24
Finished May 07 03:16:49 PM PDT 24
Peak memory 216068 kb
Host smart-1b657bee-540a-4d01-8a21-8526627a4b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763919641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2763919641
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2478394272
Short name T483
Test name
Test status
Simulation time 50951474 ps
CPU time 0.89 seconds
Started May 07 03:16:49 PM PDT 24
Finished May 07 03:16:52 PM PDT 24
Peak memory 206992 kb
Host smart-d1fff740-f194-406d-bfba-0334d064a4f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478394272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2478394272
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_err.334517479
Short name T411
Test name
Test status
Simulation time 21593222 ps
CPU time 0.93 seconds
Started May 07 03:16:44 PM PDT 24
Finished May 07 03:16:46 PM PDT 24
Peak memory 219152 kb
Host smart-8343ab79-4736-452d-a071-4efb5807d9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334517479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.334517479
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.573721013
Short name T523
Test name
Test status
Simulation time 28977916 ps
CPU time 1.22 seconds
Started May 07 03:16:46 PM PDT 24
Finished May 07 03:16:49 PM PDT 24
Peak memory 218372 kb
Host smart-74bcc998-4ce8-4194-96b1-3e8529f17bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573721013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.573721013
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.4001860133
Short name T100
Test name
Test status
Simulation time 40385024 ps
CPU time 0.85 seconds
Started May 07 03:16:46 PM PDT 24
Finished May 07 03:16:48 PM PDT 24
Peak memory 216036 kb
Host smart-4377ad8c-2676-45f7-9d04-9e19672833b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001860133 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.4001860133
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1315702952
Short name T378
Test name
Test status
Simulation time 53952770 ps
CPU time 0.97 seconds
Started May 07 03:16:50 PM PDT 24
Finished May 07 03:16:52 PM PDT 24
Peak memory 215604 kb
Host smart-a2609247-1ebd-465c-ae65-966e2df1f0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315702952 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1315702952
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1817676894
Short name T494
Test name
Test status
Simulation time 270360449 ps
CPU time 2.17 seconds
Started May 07 03:16:45 PM PDT 24
Finished May 07 03:16:49 PM PDT 24
Peak memory 217368 kb
Host smart-bd41b066-1999-4ac8-9a75-92064629ecbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817676894 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1817676894
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3486876076
Short name T196
Test name
Test status
Simulation time 136725732671 ps
CPU time 907.85 seconds
Started May 07 03:16:47 PM PDT 24
Finished May 07 03:31:57 PM PDT 24
Peak memory 222536 kb
Host smart-9760457d-15a1-4259-b385-7d48803d8085
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486876076 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3486876076
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.1899252670
Short name T391
Test name
Test status
Simulation time 35383447 ps
CPU time 1.38 seconds
Started May 07 03:18:02 PM PDT 24
Finished May 07 03:18:04 PM PDT 24
Peak memory 219140 kb
Host smart-c96b7cf0-e95b-418e-a04f-8f09ee6f5a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899252670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1899252670
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.3599002271
Short name T716
Test name
Test status
Simulation time 67499411 ps
CPU time 1.09 seconds
Started May 07 03:18:07 PM PDT 24
Finished May 07 03:18:09 PM PDT 24
Peak memory 219524 kb
Host smart-030258e0-b5ff-46fe-b8f3-bd7a48ed481a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599002271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3599002271
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.329257607
Short name T740
Test name
Test status
Simulation time 71035338 ps
CPU time 1.27 seconds
Started May 07 03:18:01 PM PDT 24
Finished May 07 03:18:04 PM PDT 24
Peak memory 218928 kb
Host smart-775472a1-45a1-49b9-b810-56880238df62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329257607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.329257607
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.2844613730
Short name T415
Test name
Test status
Simulation time 66204589 ps
CPU time 1.19 seconds
Started May 07 03:18:01 PM PDT 24
Finished May 07 03:18:03 PM PDT 24
Peak memory 217700 kb
Host smart-b99d14ee-1aba-45d5-8d69-a656d16c8f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844613730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2844613730
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2665422800
Short name T484
Test name
Test status
Simulation time 58069897 ps
CPU time 1.13 seconds
Started May 07 03:18:06 PM PDT 24
Finished May 07 03:18:08 PM PDT 24
Peak memory 217444 kb
Host smart-1c9b41be-e298-4e59-8fc3-cddf34c21e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665422800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2665422800
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3032932905
Short name T778
Test name
Test status
Simulation time 74803519 ps
CPU time 1.58 seconds
Started May 07 03:18:02 PM PDT 24
Finished May 07 03:18:05 PM PDT 24
Peak memory 219136 kb
Host smart-e7721e1b-6a1f-4ca4-901e-bfe2251ece41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032932905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3032932905
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.2300819330
Short name T644
Test name
Test status
Simulation time 54300255 ps
CPU time 1.27 seconds
Started May 07 03:18:01 PM PDT 24
Finished May 07 03:18:04 PM PDT 24
Peak memory 218576 kb
Host smart-c07fc9b1-7880-44bb-ab1b-3a71543c2df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300819330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2300819330
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.2503061576
Short name T457
Test name
Test status
Simulation time 75840658 ps
CPU time 1.19 seconds
Started May 07 03:18:05 PM PDT 24
Finished May 07 03:18:07 PM PDT 24
Peak memory 217512 kb
Host smart-1546e6e7-3d31-485b-87fa-3c8a96177a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503061576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2503061576
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.622701644
Short name T472
Test name
Test status
Simulation time 100214860 ps
CPU time 1.26 seconds
Started May 07 03:18:06 PM PDT 24
Finished May 07 03:18:08 PM PDT 24
Peak memory 217396 kb
Host smart-100db4f8-d5e1-49fb-a1d4-0366bd4ce575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622701644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.622701644
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2771865041
Short name T105
Test name
Test status
Simulation time 72581602 ps
CPU time 1.2 seconds
Started May 07 03:16:47 PM PDT 24
Finished May 07 03:16:51 PM PDT 24
Peak memory 216236 kb
Host smart-a622e335-7f1e-4587-b809-d255e1e74418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771865041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2771865041
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.782436739
Short name T685
Test name
Test status
Simulation time 108081152 ps
CPU time 1.47 seconds
Started May 07 03:16:47 PM PDT 24
Finished May 07 03:16:50 PM PDT 24
Peak memory 207100 kb
Host smart-786811ed-4fd4-46c4-8fb6-044980a9e497
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782436739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.782436739
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.862254642
Short name T185
Test name
Test status
Simulation time 13059076 ps
CPU time 0.88 seconds
Started May 07 03:16:46 PM PDT 24
Finished May 07 03:16:48 PM PDT 24
Peak memory 216644 kb
Host smart-71db2440-c6f2-4e4f-b85d-388145f7e30f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862254642 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.862254642
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2458235926
Short name T831
Test name
Test status
Simulation time 65037426 ps
CPU time 1.05 seconds
Started May 07 03:16:46 PM PDT 24
Finished May 07 03:16:48 PM PDT 24
Peak memory 218784 kb
Host smart-3e367543-4c4c-425f-84d1-3d5723365aa9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458235926 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2458235926
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3060857262
Short name T406
Test name
Test status
Simulation time 82086793 ps
CPU time 0.81 seconds
Started May 07 03:16:48 PM PDT 24
Finished May 07 03:16:51 PM PDT 24
Peak memory 218428 kb
Host smart-d9cfc821-8c53-4ded-a9ae-8e7645f5feb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060857262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3060857262
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1618817436
Short name T331
Test name
Test status
Simulation time 109776042 ps
CPU time 1.21 seconds
Started May 07 03:16:50 PM PDT 24
Finished May 07 03:16:53 PM PDT 24
Peak memory 217444 kb
Host smart-f3fecf52-4693-4f66-89a9-3d875220586a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618817436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1618817436
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2437690144
Short name T813
Test name
Test status
Simulation time 22264386 ps
CPU time 1.04 seconds
Started May 07 03:16:46 PM PDT 24
Finished May 07 03:16:48 PM PDT 24
Peak memory 216056 kb
Host smart-872f1c0e-05b6-46c9-912f-9fd4a6839131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437690144 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2437690144
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1698932980
Short name T490
Test name
Test status
Simulation time 121409768 ps
CPU time 0.97 seconds
Started May 07 03:16:45 PM PDT 24
Finished May 07 03:16:47 PM PDT 24
Peak memory 215588 kb
Host smart-0616ca64-8167-4e73-94a9-4246afc0a74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698932980 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1698932980
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.896443366
Short name T351
Test name
Test status
Simulation time 239419490 ps
CPU time 4.97 seconds
Started May 07 03:16:48 PM PDT 24
Finished May 07 03:16:55 PM PDT 24
Peak memory 217420 kb
Host smart-bf334ab2-618d-4be7-88eb-4bbe35f40622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896443366 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.896443366
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3503123880
Short name T412
Test name
Test status
Simulation time 287880046450 ps
CPU time 1710.59 seconds
Started May 07 03:16:48 PM PDT 24
Finished May 07 03:45:20 PM PDT 24
Peak memory 225416 kb
Host smart-c83f5fb7-8ee6-4418-b368-7e1604cf0fca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503123880 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3503123880
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1937552647
Short name T812
Test name
Test status
Simulation time 86785433 ps
CPU time 1.2 seconds
Started May 07 03:18:05 PM PDT 24
Finished May 07 03:18:07 PM PDT 24
Peak memory 217460 kb
Host smart-0608d2bf-f193-4e7c-ac4b-8ce45adb447f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937552647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1937552647
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.1750803896
Short name T711
Test name
Test status
Simulation time 48121339 ps
CPU time 1.46 seconds
Started May 07 03:18:02 PM PDT 24
Finished May 07 03:18:05 PM PDT 24
Peak memory 218508 kb
Host smart-51c98938-553e-4879-9838-90a3205bbb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750803896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1750803896
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.3914501325
Short name T496
Test name
Test status
Simulation time 39582299 ps
CPU time 1.43 seconds
Started May 07 03:18:03 PM PDT 24
Finished May 07 03:18:06 PM PDT 24
Peak memory 218292 kb
Host smart-22f6a17f-55f0-41a3-9650-3a5a62c8f5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914501325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3914501325
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.395514159
Short name T606
Test name
Test status
Simulation time 41056849 ps
CPU time 1.21 seconds
Started May 07 03:18:02 PM PDT 24
Finished May 07 03:18:04 PM PDT 24
Peak memory 220016 kb
Host smart-3a15e563-b489-471f-bd54-0971e0742cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395514159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.395514159
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2054720694
Short name T359
Test name
Test status
Simulation time 43467578 ps
CPU time 1.44 seconds
Started May 07 03:18:01 PM PDT 24
Finished May 07 03:18:03 PM PDT 24
Peak memory 218692 kb
Host smart-21a31dac-1bf0-45a7-b932-ccf61da34602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054720694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2054720694
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.3355959435
Short name T794
Test name
Test status
Simulation time 76023585 ps
CPU time 1.31 seconds
Started May 07 03:18:12 PM PDT 24
Finished May 07 03:18:15 PM PDT 24
Peak memory 218748 kb
Host smart-bd7da699-ea34-41c4-9c3e-85f4225f5d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355959435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3355959435
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.2519926280
Short name T502
Test name
Test status
Simulation time 67355444 ps
CPU time 1.36 seconds
Started May 07 03:18:08 PM PDT 24
Finished May 07 03:18:10 PM PDT 24
Peak memory 218764 kb
Host smart-a8ce5e28-e8dc-49c8-a205-33e66f1afd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519926280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2519926280
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1730093140
Short name T442
Test name
Test status
Simulation time 78043936 ps
CPU time 1.3 seconds
Started May 07 03:18:08 PM PDT 24
Finished May 07 03:18:11 PM PDT 24
Peak memory 217616 kb
Host smart-5e3e7724-035a-4043-ab91-56ede50570ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730093140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1730093140
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.4113867954
Short name T475
Test name
Test status
Simulation time 87918447 ps
CPU time 1.19 seconds
Started May 07 03:18:13 PM PDT 24
Finished May 07 03:18:16 PM PDT 24
Peak memory 217208 kb
Host smart-374afc94-d4f9-41a4-a5a0-cbc86c1f56ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113867954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.4113867954
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.4080613809
Short name T528
Test name
Test status
Simulation time 47938529 ps
CPU time 1.19 seconds
Started May 07 03:18:07 PM PDT 24
Finished May 07 03:18:09 PM PDT 24
Peak memory 218564 kb
Host smart-a9f1e249-9c7e-4794-8446-7e43be24ab98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080613809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.4080613809
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3563611667
Short name T68
Test name
Test status
Simulation time 70661541 ps
CPU time 1.26 seconds
Started May 07 03:16:48 PM PDT 24
Finished May 07 03:16:51 PM PDT 24
Peak memory 216096 kb
Host smart-39752bd8-108d-41a3-aa59-ff2d92c7fe05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563611667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3563611667
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1585018588
Short name T343
Test name
Test status
Simulation time 14619736 ps
CPU time 0.88 seconds
Started May 07 03:16:57 PM PDT 24
Finished May 07 03:17:00 PM PDT 24
Peak memory 206948 kb
Host smart-98b7e420-e9f4-4c37-9d89-cace38635ce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585018588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1585018588
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1551165223
Short name T180
Test name
Test status
Simulation time 45622704 ps
CPU time 0.89 seconds
Started May 07 03:16:46 PM PDT 24
Finished May 07 03:16:49 PM PDT 24
Peak memory 216620 kb
Host smart-ce241c9f-c037-42fd-bc46-c100106f1d42
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551165223 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1551165223
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_genbits.3272440884
Short name T278
Test name
Test status
Simulation time 41095498 ps
CPU time 1.56 seconds
Started May 07 03:16:48 PM PDT 24
Finished May 07 03:16:51 PM PDT 24
Peak memory 219624 kb
Host smart-c3c87a95-501b-4b70-a3b1-be218a7ac027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272440884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3272440884
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.1432598765
Short name T646
Test name
Test status
Simulation time 16331723 ps
CPU time 0.96 seconds
Started May 07 03:16:44 PM PDT 24
Finished May 07 03:16:46 PM PDT 24
Peak memory 215636 kb
Host smart-c5f15bf2-6bfc-4a30-b2af-c7789144a1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432598765 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1432598765
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3572139159
Short name T710
Test name
Test status
Simulation time 660822489 ps
CPU time 6.56 seconds
Started May 07 03:16:46 PM PDT 24
Finished May 07 03:16:54 PM PDT 24
Peak memory 217220 kb
Host smart-343e4b98-5e67-4192-b004-a9824a71f3ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572139159 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3572139159
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2653560812
Short name T524
Test name
Test status
Simulation time 48436563433 ps
CPU time 710.48 seconds
Started May 07 03:16:49 PM PDT 24
Finished May 07 03:28:41 PM PDT 24
Peak memory 219804 kb
Host smart-1c52875c-32fe-4d9f-8c84-23c10d155d84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653560812 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2653560812
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.3576473372
Short name T166
Test name
Test status
Simulation time 102405793 ps
CPU time 1.21 seconds
Started May 07 03:18:08 PM PDT 24
Finished May 07 03:18:10 PM PDT 24
Peak memory 217584 kb
Host smart-dc61e075-4f56-4556-92b9-021a18d2f323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576473372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3576473372
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.2615315510
Short name T726
Test name
Test status
Simulation time 29904718 ps
CPU time 1.29 seconds
Started May 07 03:18:10 PM PDT 24
Finished May 07 03:18:13 PM PDT 24
Peak memory 217432 kb
Host smart-eadf5236-6297-4079-a5ca-a65d58be61b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615315510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2615315510
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.2530883920
Short name T374
Test name
Test status
Simulation time 48814659 ps
CPU time 1.1 seconds
Started May 07 03:18:07 PM PDT 24
Finished May 07 03:18:09 PM PDT 24
Peak memory 217504 kb
Host smart-dc804773-3528-4784-afa6-12270dd90f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530883920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2530883920
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.3297448490
Short name T630
Test name
Test status
Simulation time 37755665 ps
CPU time 1.63 seconds
Started May 07 03:18:12 PM PDT 24
Finished May 07 03:18:16 PM PDT 24
Peak memory 218332 kb
Host smart-fd2e7f73-3602-41b8-a397-efba76aad671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297448490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3297448490
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.937083148
Short name T582
Test name
Test status
Simulation time 86035200 ps
CPU time 1.42 seconds
Started May 07 03:18:07 PM PDT 24
Finished May 07 03:18:10 PM PDT 24
Peak memory 217480 kb
Host smart-b9ec0e3b-4799-4f4c-99c8-ce707ada7840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937083148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.937083148
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.2705939826
Short name T337
Test name
Test status
Simulation time 95909910 ps
CPU time 0.92 seconds
Started May 07 03:18:09 PM PDT 24
Finished May 07 03:18:11 PM PDT 24
Peak memory 217352 kb
Host smart-8b7a10c8-ecbd-4b3f-83e7-b669419da6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705939826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2705939826
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1534792518
Short name T504
Test name
Test status
Simulation time 44168120 ps
CPU time 1.63 seconds
Started May 07 03:18:07 PM PDT 24
Finished May 07 03:18:09 PM PDT 24
Peak memory 217372 kb
Host smart-b6e10fa1-3cc7-496e-9f6f-087283a46fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534792518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1534792518
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.134107708
Short name T758
Test name
Test status
Simulation time 37507422 ps
CPU time 1.46 seconds
Started May 07 03:18:14 PM PDT 24
Finished May 07 03:18:17 PM PDT 24
Peak memory 218464 kb
Host smart-a0ab19fe-09c2-41a4-a12e-fb0ffa73ea44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134107708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.134107708
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.4095819356
Short name T515
Test name
Test status
Simulation time 37273677 ps
CPU time 1.36 seconds
Started May 07 03:18:10 PM PDT 24
Finished May 07 03:18:13 PM PDT 24
Peak memory 217396 kb
Host smart-a8563a61-6523-4156-817e-b25409aab607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095819356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.4095819356
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2865007767
Short name T256
Test name
Test status
Simulation time 184081059 ps
CPU time 1.17 seconds
Started May 07 03:16:58 PM PDT 24
Finished May 07 03:17:01 PM PDT 24
Peak memory 216020 kb
Host smart-c403e010-c44d-45a4-8d9e-5a8acb88173c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865007767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2865007767
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable.1074621969
Short name T635
Test name
Test status
Simulation time 13697177 ps
CPU time 0.96 seconds
Started May 07 03:16:59 PM PDT 24
Finished May 07 03:17:03 PM PDT 24
Peak memory 216772 kb
Host smart-800168a4-88f8-4d02-adb5-e11fd231a076
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074621969 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1074621969
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1168905828
Short name T675
Test name
Test status
Simulation time 21854161 ps
CPU time 1.02 seconds
Started May 07 03:16:46 PM PDT 24
Finished May 07 03:16:49 PM PDT 24
Peak memory 218472 kb
Host smart-fe9370fc-7951-4e1e-b6e3-8dd5e0ce44e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168905828 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1168905828
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2886708603
Short name T557
Test name
Test status
Simulation time 18389020 ps
CPU time 1.03 seconds
Started May 07 03:16:48 PM PDT 24
Finished May 07 03:16:51 PM PDT 24
Peak memory 218904 kb
Host smart-8c406a3b-02f3-4b03-b37b-8160628a749f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886708603 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2886708603
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2397411587
Short name T811
Test name
Test status
Simulation time 43522820 ps
CPU time 1.54 seconds
Started May 07 03:16:51 PM PDT 24
Finished May 07 03:16:55 PM PDT 24
Peak memory 218560 kb
Host smart-fd9a69f9-1487-4168-95c6-ee039d5f629e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397411587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2397411587
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1183556453
Short name T693
Test name
Test status
Simulation time 21122144 ps
CPU time 1.13 seconds
Started May 07 03:16:59 PM PDT 24
Finished May 07 03:17:03 PM PDT 24
Peak memory 215956 kb
Host smart-c328c253-b901-4497-884d-ef90633fc01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183556453 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1183556453
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.81695565
Short name T489
Test name
Test status
Simulation time 17443738 ps
CPU time 1 seconds
Started May 07 03:16:59 PM PDT 24
Finished May 07 03:17:03 PM PDT 24
Peak memory 215588 kb
Host smart-7dc9ce5a-0bc8-4351-916c-3fc3d4b410a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81695565 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.81695565
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.257365923
Short name T631
Test name
Test status
Simulation time 174932024 ps
CPU time 3.94 seconds
Started May 07 03:16:46 PM PDT 24
Finished May 07 03:16:52 PM PDT 24
Peak memory 215652 kb
Host smart-4f9b5ac4-08a5-4e10-b33f-be0cdc7250bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257365923 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.257365923
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.243146322
Short name T413
Test name
Test status
Simulation time 81998947269 ps
CPU time 856.41 seconds
Started May 07 03:16:58 PM PDT 24
Finished May 07 03:31:18 PM PDT 24
Peak memory 224040 kb
Host smart-b57c8a59-5394-4885-99c5-c45ee3ec7447
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243146322 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.243146322
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.1009859279
Short name T213
Test name
Test status
Simulation time 19043171 ps
CPU time 1.03 seconds
Started May 07 03:18:12 PM PDT 24
Finished May 07 03:18:15 PM PDT 24
Peak memory 215616 kb
Host smart-e556ffd4-8227-4d39-af68-d4b9c8324e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009859279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1009859279
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.3311046584
Short name T368
Test name
Test status
Simulation time 71657908 ps
CPU time 1.22 seconds
Started May 07 03:18:08 PM PDT 24
Finished May 07 03:18:10 PM PDT 24
Peak memory 218912 kb
Host smart-c5b235cb-e44e-445e-9a36-ef6c79b87eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311046584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3311046584
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.878193231
Short name T731
Test name
Test status
Simulation time 73472819 ps
CPU time 1.28 seconds
Started May 07 03:18:10 PM PDT 24
Finished May 07 03:18:12 PM PDT 24
Peak memory 219000 kb
Host smart-6bdf9592-9cc2-451d-bddc-0bcbf635456b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878193231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.878193231
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.828487356
Short name T375
Test name
Test status
Simulation time 96753618 ps
CPU time 1.52 seconds
Started May 07 03:18:09 PM PDT 24
Finished May 07 03:18:12 PM PDT 24
Peak memory 219732 kb
Host smart-71bf8221-9214-4919-8254-9713e3348d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828487356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.828487356
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.2039397477
Short name T392
Test name
Test status
Simulation time 37098080 ps
CPU time 1.37 seconds
Started May 07 03:18:12 PM PDT 24
Finished May 07 03:18:15 PM PDT 24
Peak memory 217404 kb
Host smart-5f2475a7-aa13-4574-a96c-dd9e6834d969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039397477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2039397477
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.4001442041
Short name T611
Test name
Test status
Simulation time 44422627 ps
CPU time 1.46 seconds
Started May 07 03:18:08 PM PDT 24
Finished May 07 03:18:11 PM PDT 24
Peak memory 218500 kb
Host smart-903a09bb-ff72-428d-9517-02bed2294882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001442041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.4001442041
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.2623400405
Short name T747
Test name
Test status
Simulation time 69688012 ps
CPU time 1.25 seconds
Started May 07 03:18:12 PM PDT 24
Finished May 07 03:18:15 PM PDT 24
Peak memory 219084 kb
Host smart-b8fbc974-26af-4f72-8b04-7b574c693223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623400405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2623400405
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.1018439998
Short name T832
Test name
Test status
Simulation time 119487580 ps
CPU time 2.33 seconds
Started May 07 03:18:07 PM PDT 24
Finished May 07 03:18:11 PM PDT 24
Peak memory 220192 kb
Host smart-96a1dc26-b924-4cc0-99ac-6703d68716a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018439998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1018439998
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.1982689757
Short name T93
Test name
Test status
Simulation time 45925432 ps
CPU time 1.18 seconds
Started May 07 03:18:10 PM PDT 24
Finished May 07 03:18:12 PM PDT 24
Peak memory 217432 kb
Host smart-e451311e-ef4f-40ef-9f29-2d353a24e51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982689757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1982689757
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.3528060203
Short name T537
Test name
Test status
Simulation time 84744921 ps
CPU time 3.03 seconds
Started May 07 03:18:10 PM PDT 24
Finished May 07 03:18:14 PM PDT 24
Peak memory 220024 kb
Host smart-92392f0a-3162-471a-8e7b-150a262b417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528060203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3528060203
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2486795639
Short name T815
Test name
Test status
Simulation time 77996542 ps
CPU time 1.18 seconds
Started May 07 03:16:54 PM PDT 24
Finished May 07 03:16:57 PM PDT 24
Peak memory 216120 kb
Host smart-0a95ef7c-79b3-49b0-9785-a96468c20184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486795639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2486795639
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1076202905
Short name T431
Test name
Test status
Simulation time 31976829 ps
CPU time 0.85 seconds
Started May 07 03:16:52 PM PDT 24
Finished May 07 03:16:55 PM PDT 24
Peak memory 206336 kb
Host smart-22f289f4-9252-4646-a9c2-1c995bd25bd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076202905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1076202905
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.1308500972
Short name T439
Test name
Test status
Simulation time 24492770 ps
CPU time 0.88 seconds
Started May 07 03:16:50 PM PDT 24
Finished May 07 03:16:53 PM PDT 24
Peak memory 216288 kb
Host smart-d19ced30-b79a-4209-90f5-ac73643248e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308500972 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1308500972
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1762894643
Short name T465
Test name
Test status
Simulation time 51450086 ps
CPU time 0.99 seconds
Started May 07 03:16:51 PM PDT 24
Finished May 07 03:16:53 PM PDT 24
Peak memory 218420 kb
Host smart-233f9718-092d-49c5-afe6-0f70a7ec38c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762894643 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1762894643
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.2884881661
Short name T188
Test name
Test status
Simulation time 28262081 ps
CPU time 1.14 seconds
Started May 07 03:16:50 PM PDT 24
Finished May 07 03:16:53 PM PDT 24
Peak memory 220444 kb
Host smart-676cff9d-3252-4d8e-888e-507a2afa046f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884881661 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2884881661
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2973988465
Short name T329
Test name
Test status
Simulation time 31208039 ps
CPU time 1.29 seconds
Started May 07 03:16:51 PM PDT 24
Finished May 07 03:16:54 PM PDT 24
Peak memory 217508 kb
Host smart-400a7ae3-60ca-4f5a-9d8f-4b1fe6effaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973988465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2973988465
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.4208976662
Short name T499
Test name
Test status
Simulation time 27064067 ps
CPU time 1.12 seconds
Started May 07 03:17:03 PM PDT 24
Finished May 07 03:17:05 PM PDT 24
Peak memory 224484 kb
Host smart-ccc9de7d-e567-44d6-a362-3d7edf3fce09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208976662 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.4208976662
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2347464669
Short name T386
Test name
Test status
Simulation time 26894239 ps
CPU time 0.98 seconds
Started May 07 03:16:48 PM PDT 24
Finished May 07 03:16:51 PM PDT 24
Peak memory 215636 kb
Host smart-0877f088-336b-4ba0-a2be-814a83e649cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347464669 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2347464669
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2826621223
Short name T160
Test name
Test status
Simulation time 221182537 ps
CPU time 4.4 seconds
Started May 07 03:16:58 PM PDT 24
Finished May 07 03:17:05 PM PDT 24
Peak memory 217284 kb
Host smart-7ce8aaae-e161-46e0-9506-b3c07c6f74c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826621223 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2826621223
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1845844928
Short name T416
Test name
Test status
Simulation time 47065509062 ps
CPU time 367.18 seconds
Started May 07 03:16:50 PM PDT 24
Finished May 07 03:22:59 PM PDT 24
Peak memory 218604 kb
Host smart-d4ac56c8-e74f-4042-82b5-80793d4c3ef5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845844928 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1845844928
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.2645536600
Short name T214
Test name
Test status
Simulation time 38312800 ps
CPU time 1.31 seconds
Started May 07 03:18:13 PM PDT 24
Finished May 07 03:18:16 PM PDT 24
Peak memory 215608 kb
Host smart-6e94a39a-9f9f-4532-aa55-56cf8d8cf6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645536600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2645536600
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.1206376293
Short name T795
Test name
Test status
Simulation time 274332081 ps
CPU time 3.6 seconds
Started May 07 03:18:07 PM PDT 24
Finished May 07 03:18:12 PM PDT 24
Peak memory 220008 kb
Host smart-21c86554-4503-4b70-bb81-2ef21f452b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206376293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1206376293
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.3430948443
Short name T385
Test name
Test status
Simulation time 140027663 ps
CPU time 1.89 seconds
Started May 07 03:18:12 PM PDT 24
Finished May 07 03:18:16 PM PDT 24
Peak memory 219832 kb
Host smart-cb79c969-34ba-4333-b138-cea46f46f9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430948443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3430948443
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.3436154096
Short name T389
Test name
Test status
Simulation time 95681836 ps
CPU time 1.23 seconds
Started May 07 03:18:12 PM PDT 24
Finished May 07 03:18:14 PM PDT 24
Peak memory 220340 kb
Host smart-5ec836c1-302b-4ba7-940d-aaaa1a847815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436154096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3436154096
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.3855534897
Short name T487
Test name
Test status
Simulation time 66985165 ps
CPU time 1.14 seconds
Started May 07 03:18:12 PM PDT 24
Finished May 07 03:18:15 PM PDT 24
Peak memory 218948 kb
Host smart-e0fc17c7-3c4a-418b-827d-a8a7fc1f82db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855534897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3855534897
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.422423879
Short name T802
Test name
Test status
Simulation time 41967161 ps
CPU time 1.52 seconds
Started May 07 03:18:14 PM PDT 24
Finished May 07 03:18:17 PM PDT 24
Peak memory 218680 kb
Host smart-e26f3405-30e4-4418-a78a-147515f129a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422423879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.422423879
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.87841449
Short name T694
Test name
Test status
Simulation time 33963395 ps
CPU time 1.1 seconds
Started May 07 03:18:12 PM PDT 24
Finished May 07 03:18:14 PM PDT 24
Peak memory 217292 kb
Host smart-6dd153e4-a523-4a48-8eb4-c5bd45591a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87841449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.87841449
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.519824138
Short name T261
Test name
Test status
Simulation time 43098756 ps
CPU time 1.12 seconds
Started May 07 03:18:11 PM PDT 24
Finished May 07 03:18:14 PM PDT 24
Peak memory 217640 kb
Host smart-a6da561b-a6a4-4a0b-a1cb-63dcb37c3961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519824138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.519824138
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.118186404
Short name T335
Test name
Test status
Simulation time 61021052 ps
CPU time 1.65 seconds
Started May 07 03:18:12 PM PDT 24
Finished May 07 03:18:16 PM PDT 24
Peak memory 218328 kb
Host smart-d447aa3e-ccfe-4297-95e3-85dc002e28d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118186404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.118186404
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.3124256764
Short name T818
Test name
Test status
Simulation time 51413412 ps
CPU time 1.8 seconds
Started May 07 03:18:13 PM PDT 24
Finished May 07 03:18:17 PM PDT 24
Peak memory 218596 kb
Host smart-ce886366-ed73-4fab-8c7d-4c5a9a672bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124256764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3124256764
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.1514069922
Short name T308
Test name
Test status
Simulation time 20477910 ps
CPU time 0.98 seconds
Started May 07 03:16:50 PM PDT 24
Finished May 07 03:16:53 PM PDT 24
Peak memory 206980 kb
Host smart-57b3b2a4-ec49-4728-a080-293e0d3de305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514069922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1514069922
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.1005449346
Short name T135
Test name
Test status
Simulation time 27276265 ps
CPU time 0.86 seconds
Started May 07 03:16:53 PM PDT 24
Finished May 07 03:16:55 PM PDT 24
Peak memory 216792 kb
Host smart-36e65efd-256e-428d-82f0-ff34c051514a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005449346 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1005449346
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.4279166135
Short name T216
Test name
Test status
Simulation time 27881136 ps
CPU time 1.14 seconds
Started May 07 03:16:53 PM PDT 24
Finished May 07 03:16:56 PM PDT 24
Peak memory 218484 kb
Host smart-1b54be3a-6c5c-49f9-812d-0808bee520d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279166135 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.4279166135
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.927162321
Short name T482
Test name
Test status
Simulation time 26753545 ps
CPU time 1.26 seconds
Started May 07 03:16:54 PM PDT 24
Finished May 07 03:16:57 PM PDT 24
Peak memory 221316 kb
Host smart-49b46f0e-0f08-4503-a6ea-dea1dbcf1942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927162321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.927162321
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1270740286
Short name T749
Test name
Test status
Simulation time 33333432 ps
CPU time 1.48 seconds
Started May 07 03:16:51 PM PDT 24
Finished May 07 03:16:55 PM PDT 24
Peak memory 217424 kb
Host smart-318fea04-6545-4d5d-b69c-619ea46ce2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270740286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1270740286
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.38618719
Short name T371
Test name
Test status
Simulation time 28483389 ps
CPU time 0.9 seconds
Started May 07 03:16:50 PM PDT 24
Finished May 07 03:16:52 PM PDT 24
Peak memory 216032 kb
Host smart-ba6bf386-dee3-4131-911e-427a35390f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38618719 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.38618719
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1564796567
Short name T569
Test name
Test status
Simulation time 26931988 ps
CPU time 0.98 seconds
Started May 07 03:16:52 PM PDT 24
Finished May 07 03:16:55 PM PDT 24
Peak memory 215636 kb
Host smart-582a8138-f9f8-468d-9cda-ec64ac093cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564796567 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1564796567
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.4133387657
Short name T338
Test name
Test status
Simulation time 153770181 ps
CPU time 3.51 seconds
Started May 07 03:16:51 PM PDT 24
Finished May 07 03:16:56 PM PDT 24
Peak memory 220420 kb
Host smart-7bb929da-ddcc-4520-835c-becca9dfc4db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133387657 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.4133387657
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2929067120
Short name T632
Test name
Test status
Simulation time 16842087098 ps
CPU time 225.05 seconds
Started May 07 03:16:53 PM PDT 24
Finished May 07 03:20:40 PM PDT 24
Peak memory 218220 kb
Host smart-091c2aaa-e7e5-4607-a345-303b8fa8f6e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929067120 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2929067120
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.4273359582
Short name T301
Test name
Test status
Simulation time 19971769 ps
CPU time 1.13 seconds
Started May 07 03:18:08 PM PDT 24
Finished May 07 03:18:10 PM PDT 24
Peak memory 219864 kb
Host smart-668686bb-b2d7-483d-8885-1b6335337803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273359582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.4273359582
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.1838042700
Short name T21
Test name
Test status
Simulation time 71532504 ps
CPU time 1.55 seconds
Started May 07 03:18:08 PM PDT 24
Finished May 07 03:18:10 PM PDT 24
Peak memory 218556 kb
Host smart-fe146089-a695-4233-bd49-8f698813d4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838042700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1838042700
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.769002080
Short name T458
Test name
Test status
Simulation time 168168316 ps
CPU time 1.36 seconds
Started May 07 03:18:11 PM PDT 24
Finished May 07 03:18:14 PM PDT 24
Peak memory 218992 kb
Host smart-9ed9993a-5e9a-48f9-b330-ab688ee759a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769002080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.769002080
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.3784635785
Short name T495
Test name
Test status
Simulation time 111229776 ps
CPU time 1.17 seconds
Started May 07 03:18:09 PM PDT 24
Finished May 07 03:18:12 PM PDT 24
Peak memory 219984 kb
Host smart-e99256d8-dc00-4c8b-b1ce-736f47c0aa62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784635785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3784635785
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.318818842
Short name T440
Test name
Test status
Simulation time 82497482 ps
CPU time 2.57 seconds
Started May 07 03:18:13 PM PDT 24
Finished May 07 03:18:17 PM PDT 24
Peak memory 218632 kb
Host smart-b69b7abf-3327-4b1b-acf4-2f6588bf75e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318818842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.318818842
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2213343924
Short name T665
Test name
Test status
Simulation time 54859664 ps
CPU time 1.19 seconds
Started May 07 03:18:14 PM PDT 24
Finished May 07 03:18:16 PM PDT 24
Peak memory 218392 kb
Host smart-840ba4a7-9827-4cb6-bb3d-af9be4645adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213343924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2213343924
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.2494036260
Short name T745
Test name
Test status
Simulation time 48278131 ps
CPU time 1.02 seconds
Started May 07 03:18:13 PM PDT 24
Finished May 07 03:18:16 PM PDT 24
Peak memory 218524 kb
Host smart-bb497389-88c5-4ca4-917d-02ab15991239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494036260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2494036260
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.3627852621
Short name T13
Test name
Test status
Simulation time 45115564 ps
CPU time 1.21 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:24 PM PDT 24
Peak memory 219464 kb
Host smart-b22703b1-71a7-4f1c-a0f0-397579e456c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627852621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3627852621
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.4023636474
Short name T298
Test name
Test status
Simulation time 77028797 ps
CPU time 1.25 seconds
Started May 07 03:16:50 PM PDT 24
Finished May 07 03:16:53 PM PDT 24
Peak memory 216056 kb
Host smart-bc8a2068-a444-49b7-88b1-618f2599c88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023636474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.4023636474
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1231919436
Short name T78
Test name
Test status
Simulation time 32755281 ps
CPU time 0.86 seconds
Started May 07 03:16:53 PM PDT 24
Finished May 07 03:16:56 PM PDT 24
Peak memory 206860 kb
Host smart-205df688-7ce6-4897-8145-e44181c49215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231919436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1231919436
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.983020805
Short name T698
Test name
Test status
Simulation time 31198087 ps
CPU time 1.11 seconds
Started May 07 03:16:54 PM PDT 24
Finished May 07 03:16:57 PM PDT 24
Peak memory 217524 kb
Host smart-b59d5c05-960e-4b9f-a3dc-152f7b8e57ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983020805 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.983020805
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2679819746
Short name T9
Test name
Test status
Simulation time 31672663 ps
CPU time 1.04 seconds
Started May 07 03:16:51 PM PDT 24
Finished May 07 03:16:54 PM PDT 24
Peak memory 220944 kb
Host smart-36e597a0-4376-4222-9ae4-8a54d4da9a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679819746 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2679819746
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1141728686
Short name T325
Test name
Test status
Simulation time 96561709 ps
CPU time 1.04 seconds
Started May 07 03:16:53 PM PDT 24
Finished May 07 03:16:55 PM PDT 24
Peak memory 217476 kb
Host smart-4a038887-47d3-4788-a9cd-178e7f9a5dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141728686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1141728686
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1636368884
Short name T833
Test name
Test status
Simulation time 33952883 ps
CPU time 0.98 seconds
Started May 07 03:16:52 PM PDT 24
Finished May 07 03:16:55 PM PDT 24
Peak memory 224448 kb
Host smart-0a1ffd67-1f52-45d8-ab43-c8dc4bae2897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636368884 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1636368884
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3832816780
Short name T248
Test name
Test status
Simulation time 18409454 ps
CPU time 0.95 seconds
Started May 07 03:16:55 PM PDT 24
Finished May 07 03:16:58 PM PDT 24
Peak memory 215596 kb
Host smart-f679368e-222e-4f32-ad74-5673df746caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832816780 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3832816780
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2664215314
Short name T728
Test name
Test status
Simulation time 143851519 ps
CPU time 1.51 seconds
Started May 07 03:16:53 PM PDT 24
Finished May 07 03:16:56 PM PDT 24
Peak memory 217224 kb
Host smart-51366634-de50-4757-be41-4e37242860c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664215314 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2664215314
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.4278616670
Short name T201
Test name
Test status
Simulation time 40254097958 ps
CPU time 498.41 seconds
Started May 07 03:16:51 PM PDT 24
Finished May 07 03:25:11 PM PDT 24
Peak memory 218404 kb
Host smart-20992860-4d04-4238-ad90-529f94d58af0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278616670 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.4278616670
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.591444551
Short name T283
Test name
Test status
Simulation time 94647733 ps
CPU time 1.39 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:23 PM PDT 24
Peak memory 217468 kb
Host smart-dd8ad603-e2d3-4392-bb79-d1900ed1e975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591444551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.591444551
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.2832026944
Short name T670
Test name
Test status
Simulation time 83074138 ps
CPU time 1.18 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:22 PM PDT 24
Peak memory 219644 kb
Host smart-8b1d248f-994d-4be1-87be-eeb15b950f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832026944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2832026944
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.3097901455
Short name T273
Test name
Test status
Simulation time 71696043 ps
CPU time 1.06 seconds
Started May 07 03:18:13 PM PDT 24
Finished May 07 03:18:15 PM PDT 24
Peak memory 217560 kb
Host smart-e7a39ece-4b2d-4f20-b4e8-64bf14a29983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097901455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3097901455
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.3738226662
Short name T447
Test name
Test status
Simulation time 42296913 ps
CPU time 1.76 seconds
Started May 07 03:18:10 PM PDT 24
Finished May 07 03:18:13 PM PDT 24
Peak memory 218604 kb
Host smart-4b8b0f39-b3bd-4239-8859-7ec0a23beaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738226662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3738226662
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.34786154
Short name T384
Test name
Test status
Simulation time 33262282 ps
CPU time 1.39 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:23 PM PDT 24
Peak memory 219568 kb
Host smart-323154b4-90c9-4b11-a9ab-362bb6252558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34786154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.34786154
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.2788975656
Short name T165
Test name
Test status
Simulation time 47184670 ps
CPU time 1.53 seconds
Started May 07 03:18:15 PM PDT 24
Finished May 07 03:18:17 PM PDT 24
Peak memory 217416 kb
Host smart-3ed463ac-b3cc-4f83-a708-f6958bfe9e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788975656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2788975656
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.2313111841
Short name T803
Test name
Test status
Simulation time 77866190 ps
CPU time 1.33 seconds
Started May 07 03:18:13 PM PDT 24
Finished May 07 03:18:16 PM PDT 24
Peak memory 217512 kb
Host smart-888f2364-84d0-4562-9922-b1d45d2f58f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313111841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2313111841
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.4098033883
Short name T300
Test name
Test status
Simulation time 56112048 ps
CPU time 1.33 seconds
Started May 07 03:16:52 PM PDT 24
Finished May 07 03:16:55 PM PDT 24
Peak memory 216240 kb
Host smart-2c5eafdf-43b3-4bf8-b8bd-9eca55991b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098033883 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.4098033883
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3253162574
Short name T249
Test name
Test status
Simulation time 14351046 ps
CPU time 0.94 seconds
Started May 07 03:16:52 PM PDT 24
Finished May 07 03:16:55 PM PDT 24
Peak memory 215536 kb
Host smart-d81c4bca-c2c7-4d71-b0b4-ca1a072f8810
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253162574 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3253162574
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1420945646
Short name T122
Test name
Test status
Simulation time 94318472 ps
CPU time 1.16 seconds
Started May 07 03:16:54 PM PDT 24
Finished May 07 03:16:57 PM PDT 24
Peak memory 217248 kb
Host smart-5d07a923-d2d9-4ca3-95ec-4c11467b3eca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420945646 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1420945646
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2985738163
Short name T6
Test name
Test status
Simulation time 21302776 ps
CPU time 1.08 seconds
Started May 07 03:16:53 PM PDT 24
Finished May 07 03:16:56 PM PDT 24
Peak memory 224448 kb
Host smart-880be088-278b-4335-9bee-69c6abfc4d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985738163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2985738163
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.4018841932
Short name T601
Test name
Test status
Simulation time 41134822 ps
CPU time 1.29 seconds
Started May 07 03:16:53 PM PDT 24
Finished May 07 03:16:56 PM PDT 24
Peak memory 219772 kb
Host smart-7b4ed994-6755-43e6-b0bc-a1ee5529b847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018841932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.4018841932
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3604797268
Short name T574
Test name
Test status
Simulation time 22030985 ps
CPU time 1.21 seconds
Started May 07 03:16:52 PM PDT 24
Finished May 07 03:16:55 PM PDT 24
Peak memory 224440 kb
Host smart-f71ea4e1-8de5-4fc3-84a9-bf9f8e8653e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604797268 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3604797268
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.4028229367
Short name T733
Test name
Test status
Simulation time 34054150 ps
CPU time 0.88 seconds
Started May 07 03:16:52 PM PDT 24
Finished May 07 03:16:55 PM PDT 24
Peak memory 215656 kb
Host smart-3bb73100-d768-4cc4-82da-1d01121dcc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028229367 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.4028229367
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3223380528
Short name T610
Test name
Test status
Simulation time 95892399 ps
CPU time 2.33 seconds
Started May 07 03:17:03 PM PDT 24
Finished May 07 03:17:07 PM PDT 24
Peak memory 217076 kb
Host smart-47d9a7ad-9475-41c3-b052-0326ad024e85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223380528 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3223380528
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3426893411
Short name T690
Test name
Test status
Simulation time 40267247144 ps
CPU time 450.38 seconds
Started May 07 03:16:54 PM PDT 24
Finished May 07 03:24:26 PM PDT 24
Peak memory 218280 kb
Host smart-1e43a3c0-9997-43e6-9d37-d56b06eefbce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426893411 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3426893411
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.2355601548
Short name T647
Test name
Test status
Simulation time 49373630 ps
CPU time 1.48 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:22 PM PDT 24
Peak memory 218232 kb
Host smart-fe3a0f1d-2f01-48d6-aecd-6a841277bffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355601548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2355601548
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.3875018848
Short name T686
Test name
Test status
Simulation time 40380120 ps
CPU time 1.59 seconds
Started May 07 03:18:16 PM PDT 24
Finished May 07 03:18:18 PM PDT 24
Peak memory 218692 kb
Host smart-65c87df8-7eb2-407d-922e-afe2120ab369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875018848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3875018848
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.1582067386
Short name T463
Test name
Test status
Simulation time 81088555 ps
CPU time 1.12 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:24 PM PDT 24
Peak memory 217292 kb
Host smart-24d00895-9315-49e1-988f-d8cc3c7046b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582067386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1582067386
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3141987690
Short name T692
Test name
Test status
Simulation time 69855712 ps
CPU time 1.38 seconds
Started May 07 03:18:18 PM PDT 24
Finished May 07 03:18:21 PM PDT 24
Peak memory 216712 kb
Host smart-5e9dd31b-c8cf-469f-9b24-d239a7972ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141987690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3141987690
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.2971352977
Short name T808
Test name
Test status
Simulation time 42715104 ps
CPU time 1.33 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:31 PM PDT 24
Peak memory 217384 kb
Host smart-08173069-3b51-490d-b1be-539ef9319585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971352977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2971352977
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3102417677
Short name T480
Test name
Test status
Simulation time 86604519 ps
CPU time 1.2 seconds
Started May 07 03:18:21 PM PDT 24
Finished May 07 03:18:25 PM PDT 24
Peak memory 220084 kb
Host smart-4c035684-6b94-4679-a765-004eb7bfe058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102417677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3102417677
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.1232171527
Short name T664
Test name
Test status
Simulation time 35904369 ps
CPU time 1.1 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:23 PM PDT 24
Peak memory 217480 kb
Host smart-101afec5-f26b-4c02-8bac-3b868daf3833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232171527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1232171527
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.82354637
Short name T541
Test name
Test status
Simulation time 77177955 ps
CPU time 1.31 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:22 PM PDT 24
Peak memory 215608 kb
Host smart-79f54f87-d3d8-496b-a3e3-776b9e0d9cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82354637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.82354637
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.853638215
Short name T257
Test name
Test status
Simulation time 89276594 ps
CPU time 1.22 seconds
Started May 07 03:16:17 PM PDT 24
Finished May 07 03:16:20 PM PDT 24
Peak memory 216088 kb
Host smart-4c6f3577-f5ae-4d9b-bd7a-58b4b6359db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853638215 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.853638215
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2728654386
Short name T398
Test name
Test status
Simulation time 38013825 ps
CPU time 0.83 seconds
Started May 07 03:16:20 PM PDT 24
Finished May 07 03:16:23 PM PDT 24
Peak memory 206796 kb
Host smart-898f6677-053b-4f5d-9d75-a5714a636f04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728654386 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2728654386
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3789751315
Short name T179
Test name
Test status
Simulation time 35124789 ps
CPU time 0.82 seconds
Started May 07 03:16:23 PM PDT 24
Finished May 07 03:16:25 PM PDT 24
Peak memory 216744 kb
Host smart-c288fc36-557f-4270-b1b8-7a96c91821a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789751315 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3789751315
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.71903901
Short name T356
Test name
Test status
Simulation time 32198353 ps
CPU time 1.19 seconds
Started May 07 03:16:21 PM PDT 24
Finished May 07 03:16:24 PM PDT 24
Peak memory 217264 kb
Host smart-4409d6d2-26a2-4c6d-8ba1-49bab6753d63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71903901 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disa
ble_auto_req_mode.71903901
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.2406961226
Short name T361
Test name
Test status
Simulation time 22279062 ps
CPU time 1.22 seconds
Started May 07 03:16:16 PM PDT 24
Finished May 07 03:16:19 PM PDT 24
Peak memory 224444 kb
Host smart-fd204bde-8f2c-4b64-a560-b0dd9bb337a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406961226 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2406961226
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.2233078583
Short name T723
Test name
Test status
Simulation time 44473114 ps
CPU time 1.36 seconds
Started May 07 03:16:17 PM PDT 24
Finished May 07 03:16:20 PM PDT 24
Peak memory 218688 kb
Host smart-e258df3c-671d-4438-ba0a-6d34ed6f09b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233078583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2233078583
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2033052628
Short name T666
Test name
Test status
Simulation time 40252494 ps
CPU time 0.89 seconds
Started May 07 03:16:16 PM PDT 24
Finished May 07 03:16:19 PM PDT 24
Peak memory 215664 kb
Host smart-11b25346-b4a9-4082-9025-86d6ac121f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033052628 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2033052628
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_smoke.3661201193
Short name T737
Test name
Test status
Simulation time 67171557 ps
CPU time 0.91 seconds
Started May 07 03:16:15 PM PDT 24
Finished May 07 03:16:18 PM PDT 24
Peak memory 215484 kb
Host smart-08464531-3ba5-4ae3-8844-b57c089c0c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661201193 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3661201193
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1668596206
Short name T357
Test name
Test status
Simulation time 118164408 ps
CPU time 2.84 seconds
Started May 07 03:16:14 PM PDT 24
Finished May 07 03:16:19 PM PDT 24
Peak memory 215624 kb
Host smart-1ae5c310-51d3-40e5-bfd7-2e6510e05a41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668596206 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1668596206
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.228247188
Short name T207
Test name
Test status
Simulation time 97608537005 ps
CPU time 556.31 seconds
Started May 07 03:16:15 PM PDT 24
Finished May 07 03:25:33 PM PDT 24
Peak memory 219516 kb
Host smart-b32ebcc4-749e-465a-a922-bf7858d20f95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228247188 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.228247188
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2241442247
Short name T668
Test name
Test status
Simulation time 66411362 ps
CPU time 1.15 seconds
Started May 07 03:16:55 PM PDT 24
Finished May 07 03:16:58 PM PDT 24
Peak memory 216040 kb
Host smart-0710618d-11bf-4e7b-8294-b686b4405216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241442247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2241442247
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2619484505
Short name T830
Test name
Test status
Simulation time 20798563 ps
CPU time 0.85 seconds
Started May 07 03:16:52 PM PDT 24
Finished May 07 03:16:54 PM PDT 24
Peak memory 207248 kb
Host smart-afc99546-afc3-48df-9de9-7f9b1cecfd3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619484505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2619484505
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.825418861
Short name T752
Test name
Test status
Simulation time 22284978 ps
CPU time 0.89 seconds
Started May 07 03:16:54 PM PDT 24
Finished May 07 03:16:57 PM PDT 24
Peak memory 216320 kb
Host smart-c87177ab-f793-4aa9-8265-35208770cda2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825418861 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.825418861
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.1551629715
Short name T140
Test name
Test status
Simulation time 18432741 ps
CPU time 1.12 seconds
Started May 07 03:16:55 PM PDT 24
Finished May 07 03:16:58 PM PDT 24
Peak memory 224420 kb
Host smart-2e32cb20-b2a9-4879-9b78-c5f068429932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551629715 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1551629715
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.4208109339
Short name T540
Test name
Test status
Simulation time 35425693 ps
CPU time 1.11 seconds
Started May 07 03:16:53 PM PDT 24
Finished May 07 03:16:56 PM PDT 24
Peak memory 217364 kb
Host smart-a7a7bdc7-3f44-4c0c-bad4-98ad9fa76eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208109339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.4208109339
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1045302632
Short name T159
Test name
Test status
Simulation time 22615612 ps
CPU time 1.1 seconds
Started May 07 03:16:55 PM PDT 24
Finished May 07 03:16:58 PM PDT 24
Peak memory 216304 kb
Host smart-2479fa11-84eb-4308-9789-77b486b19d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045302632 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1045302632
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2861048716
Short name T547
Test name
Test status
Simulation time 50847462 ps
CPU time 0.93 seconds
Started May 07 03:16:53 PM PDT 24
Finished May 07 03:16:56 PM PDT 24
Peak memory 215564 kb
Host smart-65aed2c7-951d-4f01-b1bf-3280cf16952d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861048716 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2861048716
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.895225926
Short name T595
Test name
Test status
Simulation time 750085193 ps
CPU time 4.34 seconds
Started May 07 03:16:54 PM PDT 24
Finished May 07 03:17:00 PM PDT 24
Peak memory 217300 kb
Host smart-84d6c837-090e-4ef9-a674-9265138c5eb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895225926 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.895225926
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3367732443
Short name T637
Test name
Test status
Simulation time 30241547512 ps
CPU time 703.31 seconds
Started May 07 03:16:50 PM PDT 24
Finished May 07 03:28:35 PM PDT 24
Peak memory 217816 kb
Host smart-002dcaae-213d-485c-87d9-c8381490fc0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367732443 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3367732443
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.90384226
Short name T64
Test name
Test status
Simulation time 252656840 ps
CPU time 1.63 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:24 PM PDT 24
Peak memory 218812 kb
Host smart-4d139a7a-aa0a-491b-aaa1-48558c4836b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90384226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.90384226
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.616569949
Short name T395
Test name
Test status
Simulation time 41355336 ps
CPU time 1.21 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:24 PM PDT 24
Peak memory 218600 kb
Host smart-dda39f92-0360-4d8f-807b-ac789d8360a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616569949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.616569949
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.821453816
Short name T792
Test name
Test status
Simulation time 93196006 ps
CPU time 1.58 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:23 PM PDT 24
Peak memory 218872 kb
Host smart-e6078001-f239-48ec-af6f-f2a0a7672983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821453816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.821453816
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2564326654
Short name T444
Test name
Test status
Simulation time 49464577 ps
CPU time 1.56 seconds
Started May 07 03:18:14 PM PDT 24
Finished May 07 03:18:17 PM PDT 24
Peak memory 218660 kb
Host smart-e34340cf-ecc0-4d34-bb12-2772b10dfb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564326654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2564326654
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.10114353
Short name T72
Test name
Test status
Simulation time 40136744 ps
CPU time 1.43 seconds
Started May 07 03:18:16 PM PDT 24
Finished May 07 03:18:18 PM PDT 24
Peak memory 218460 kb
Host smart-e5a84d9d-255c-458e-8398-bdfc2cd49954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10114353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.10114353
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.2566223846
Short name T426
Test name
Test status
Simulation time 48308504 ps
CPU time 1.74 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:24 PM PDT 24
Peak memory 218392 kb
Host smart-918a1b5b-8c23-46f4-9426-1003e0a80083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566223846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.2566223846
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.74757190
Short name T454
Test name
Test status
Simulation time 74487450 ps
CPU time 1.28 seconds
Started May 07 03:18:17 PM PDT 24
Finished May 07 03:18:19 PM PDT 24
Peak memory 219192 kb
Host smart-6351a587-2207-44f8-b3a0-0f65e360bc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74757190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.74757190
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2064019618
Short name T653
Test name
Test status
Simulation time 38465476 ps
CPU time 1.36 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:27 PM PDT 24
Peak memory 218596 kb
Host smart-47dc7d68-cbc6-46c5-9b5d-dfbe62d9fc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064019618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2064019618
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3720568736
Short name T661
Test name
Test status
Simulation time 104688496 ps
CPU time 2.19 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:28 PM PDT 24
Peak memory 218540 kb
Host smart-53ff9459-deb7-4130-a8f8-0e408e7906e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720568736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3720568736
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1292246499
Short name T260
Test name
Test status
Simulation time 25759007 ps
CPU time 1.33 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:23 PM PDT 24
Peak memory 218440 kb
Host smart-38c857ee-9bd7-4fd4-a53d-a1c6d7c5810a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292246499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1292246499
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert_test.3633159775
Short name T507
Test name
Test status
Simulation time 28107159 ps
CPU time 0.9 seconds
Started May 07 03:17:00 PM PDT 24
Finished May 07 03:17:03 PM PDT 24
Peak memory 215036 kb
Host smart-a8c18a67-c814-4362-b1c1-f5845f727db1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633159775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3633159775
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_err.2968080002
Short name T471
Test name
Test status
Simulation time 32908247 ps
CPU time 1.02 seconds
Started May 07 03:16:52 PM PDT 24
Finished May 07 03:16:55 PM PDT 24
Peak memory 224432 kb
Host smart-6a0a9246-4771-44a2-8ee1-b1e7a8f75538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968080002 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2968080002
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3169850343
Short name T382
Test name
Test status
Simulation time 103478807 ps
CPU time 1.14 seconds
Started May 07 03:16:54 PM PDT 24
Finished May 07 03:16:57 PM PDT 24
Peak memory 217240 kb
Host smart-a5481756-2acd-4cce-bd5c-3c20108c3628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169850343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3169850343
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.195423550
Short name T324
Test name
Test status
Simulation time 24348967 ps
CPU time 1.17 seconds
Started May 07 03:17:04 PM PDT 24
Finished May 07 03:17:07 PM PDT 24
Peak memory 215816 kb
Host smart-0fc29f50-5485-438e-a2d5-38cc29ae97dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195423550 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.195423550
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.364688254
Short name T585
Test name
Test status
Simulation time 29324260 ps
CPU time 1.02 seconds
Started May 07 03:16:52 PM PDT 24
Finished May 07 03:16:55 PM PDT 24
Peak memory 215656 kb
Host smart-79907bdd-4f00-4f66-9134-685a020a61c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364688254 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.364688254
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2114746335
Short name T161
Test name
Test status
Simulation time 480660753 ps
CPU time 5 seconds
Started May 07 03:17:03 PM PDT 24
Finished May 07 03:17:10 PM PDT 24
Peak memory 217472 kb
Host smart-859088ea-86ac-4bb9-8315-a98066a95a4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114746335 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2114746335
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3676456091
Short name T449
Test name
Test status
Simulation time 121638150324 ps
CPU time 596.74 seconds
Started May 07 03:17:03 PM PDT 24
Finished May 07 03:27:01 PM PDT 24
Peak memory 220544 kb
Host smart-c363a1a8-66a3-445e-b100-003a930d5be9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676456091 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3676456091
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3355299920
Short name T276
Test name
Test status
Simulation time 297095173 ps
CPU time 1.81 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:23 PM PDT 24
Peak memory 218808 kb
Host smart-3a762f2e-45aa-408a-8dc6-198976eaf5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355299920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3355299920
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.980441749
Short name T536
Test name
Test status
Simulation time 77230445 ps
CPU time 1.28 seconds
Started May 07 03:18:21 PM PDT 24
Finished May 07 03:18:24 PM PDT 24
Peak memory 218460 kb
Host smart-cba2cb29-082c-4998-b5f3-d8c824d46e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980441749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.980441749
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1066560663
Short name T704
Test name
Test status
Simulation time 37641566 ps
CPU time 1.48 seconds
Started May 07 03:18:24 PM PDT 24
Finished May 07 03:18:28 PM PDT 24
Peak memory 218712 kb
Host smart-57adadbf-e6cf-4b13-b525-0da7a34677f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066560663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1066560663
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1255155993
Short name T724
Test name
Test status
Simulation time 25180311 ps
CPU time 1.15 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:24 PM PDT 24
Peak memory 217268 kb
Host smart-2cbd6128-1349-4ade-a710-74f264469a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255155993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1255155993
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.4054742303
Short name T793
Test name
Test status
Simulation time 71076025 ps
CPU time 1.39 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:27 PM PDT 24
Peak memory 219056 kb
Host smart-afea414a-304f-4654-9cf9-26077934c257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054742303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.4054742303
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2768529960
Short name T748
Test name
Test status
Simulation time 103284668 ps
CPU time 1.11 seconds
Started May 07 03:18:18 PM PDT 24
Finished May 07 03:18:21 PM PDT 24
Peak memory 217316 kb
Host smart-b090e1fe-7240-4327-9f43-45bbaf3b53fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768529960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2768529960
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1721936101
Short name T518
Test name
Test status
Simulation time 41645371 ps
CPU time 1.57 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:24 PM PDT 24
Peak memory 218580 kb
Host smart-2cee6092-c656-41f1-8083-83842a925335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721936101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1721936101
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2288807733
Short name T554
Test name
Test status
Simulation time 60827106 ps
CPU time 1.35 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:24 PM PDT 24
Peak memory 218664 kb
Host smart-91cddcc8-a9b1-4cec-9166-f329c5390c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288807733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2288807733
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.158564812
Short name T306
Test name
Test status
Simulation time 116214233 ps
CPU time 1.47 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:23 PM PDT 24
Peak memory 218672 kb
Host smart-75868075-9bd6-4510-989b-6aa5cbafe8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158564812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.158564812
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2895970622
Short name T139
Test name
Test status
Simulation time 49259356 ps
CPU time 1.21 seconds
Started May 07 03:16:58 PM PDT 24
Finished May 07 03:17:02 PM PDT 24
Peak memory 216052 kb
Host smart-5824b3ae-3c10-4259-b4a3-e51fda7d67aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895970622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2895970622
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.566859031
Short name T800
Test name
Test status
Simulation time 16903183 ps
CPU time 1 seconds
Started May 07 03:16:57 PM PDT 24
Finished May 07 03:16:59 PM PDT 24
Peak memory 215216 kb
Host smart-a51d317a-ea95-4c40-ae2f-1e389e3e19af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566859031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.566859031
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2343000795
Short name T97
Test name
Test status
Simulation time 14070875 ps
CPU time 0.96 seconds
Started May 07 03:16:58 PM PDT 24
Finished May 07 03:17:02 PM PDT 24
Peak memory 216804 kb
Host smart-984a74d8-6a83-45f8-8482-a731e618211b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343000795 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2343000795
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3499078063
Short name T672
Test name
Test status
Simulation time 87291658 ps
CPU time 1.11 seconds
Started May 07 03:16:57 PM PDT 24
Finished May 07 03:17:00 PM PDT 24
Peak memory 217224 kb
Host smart-c778cf19-0540-4003-8d65-556f531b4623
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499078063 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3499078063
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1906648672
Short name T491
Test name
Test status
Simulation time 22505736 ps
CPU time 0.91 seconds
Started May 07 03:16:57 PM PDT 24
Finished May 07 03:16:59 PM PDT 24
Peak memory 218576 kb
Host smart-4fa67e61-f3cd-4199-81ab-9ae61b286160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906648672 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1906648672
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.4065807464
Short name T741
Test name
Test status
Simulation time 141537395 ps
CPU time 2.64 seconds
Started May 07 03:16:59 PM PDT 24
Finished May 07 03:17:05 PM PDT 24
Peak memory 219448 kb
Host smart-47d8850e-9c8c-4de0-af85-5445c8138894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065807464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.4065807464
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3920120853
Short name T561
Test name
Test status
Simulation time 102764569 ps
CPU time 0.82 seconds
Started May 07 03:16:57 PM PDT 24
Finished May 07 03:16:59 PM PDT 24
Peak memory 215812 kb
Host smart-dca02e5c-d4df-4454-b6e4-1674786f8b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920120853 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3920120853
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.774786171
Short name T323
Test name
Test status
Simulation time 16486892 ps
CPU time 0.96 seconds
Started May 07 03:17:00 PM PDT 24
Finished May 07 03:17:03 PM PDT 24
Peak memory 215636 kb
Host smart-c8a9182b-5b2b-40b2-b923-359732934a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774786171 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.774786171
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3721674158
Short name T807
Test name
Test status
Simulation time 191059304 ps
CPU time 4.06 seconds
Started May 07 03:16:58 PM PDT 24
Finished May 07 03:17:04 PM PDT 24
Peak memory 217384 kb
Host smart-fa7f223f-ece5-4ef8-b8bd-0755259a9d1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721674158 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3721674158
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1299531187
Short name T596
Test name
Test status
Simulation time 11296886053 ps
CPU time 266 seconds
Started May 07 03:16:59 PM PDT 24
Finished May 07 03:21:28 PM PDT 24
Peak memory 222316 kb
Host smart-4ab8795a-a98e-4232-b369-62976f7c41fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299531187 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1299531187
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.168849961
Short name T503
Test name
Test status
Simulation time 66933598 ps
CPU time 1.09 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:23 PM PDT 24
Peak memory 217340 kb
Host smart-74db1c5d-fcba-491d-8b45-2d16e7297600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168849961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.168849961
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2361923315
Short name T437
Test name
Test status
Simulation time 158486654 ps
CPU time 1.68 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:22 PM PDT 24
Peak memory 220028 kb
Host smart-e5724b08-dae8-40d0-bd52-2358f3d353da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361923315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2361923315
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3273699586
Short name T608
Test name
Test status
Simulation time 68523436 ps
CPU time 1.33 seconds
Started May 07 03:18:18 PM PDT 24
Finished May 07 03:18:20 PM PDT 24
Peak memory 220096 kb
Host smart-f41e68d5-2afa-4088-aa1f-71d1c4f8d34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273699586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3273699586
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2200196647
Short name T46
Test name
Test status
Simulation time 39942871 ps
CPU time 1.53 seconds
Started May 07 03:18:17 PM PDT 24
Finished May 07 03:18:20 PM PDT 24
Peak memory 218728 kb
Host smart-2ae30eea-2759-438d-ac1c-890f29005c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200196647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2200196647
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3071481430
Short name T474
Test name
Test status
Simulation time 109503466 ps
CPU time 0.95 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:22 PM PDT 24
Peak memory 217352 kb
Host smart-d373135a-d0de-4151-a34e-0596eea10c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071481430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3071481430
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.186184097
Short name T707
Test name
Test status
Simulation time 43434074 ps
CPU time 1.43 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:24 PM PDT 24
Peak memory 218680 kb
Host smart-e8fa8607-df91-4856-a088-7c3e016a9088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186184097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.186184097
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1385751134
Short name T662
Test name
Test status
Simulation time 246856833 ps
CPU time 3.47 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:25 PM PDT 24
Peak memory 220196 kb
Host smart-38de55ae-db70-4326-9d2f-e33ec36b3d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385751134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1385751134
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.4111798504
Short name T652
Test name
Test status
Simulation time 36960613 ps
CPU time 1.12 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:23 PM PDT 24
Peak memory 217492 kb
Host smart-2e8d99d9-5e74-4f47-8c25-b9aa1333ef07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111798504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.4111798504
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3126942856
Short name T684
Test name
Test status
Simulation time 54924069 ps
CPU time 1.03 seconds
Started May 07 03:18:18 PM PDT 24
Finished May 07 03:18:20 PM PDT 24
Peak memory 217524 kb
Host smart-9d89b5bb-2803-4e2e-8c9f-b6fc51211808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126942856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3126942856
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.300587275
Short name T607
Test name
Test status
Simulation time 37039066 ps
CPU time 1.09 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:23 PM PDT 24
Peak memory 216908 kb
Host smart-e9097724-2107-475d-bdd2-8ffa18227ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300587275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.300587275
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3925124028
Short name T822
Test name
Test status
Simulation time 99304181 ps
CPU time 1.13 seconds
Started May 07 03:17:02 PM PDT 24
Finished May 07 03:17:05 PM PDT 24
Peak memory 216032 kb
Host smart-17cc53fb-b5db-4a23-925d-4076092de12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925124028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3925124028
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2524058148
Short name T428
Test name
Test status
Simulation time 43045386 ps
CPU time 0.85 seconds
Started May 07 03:17:00 PM PDT 24
Finished May 07 03:17:03 PM PDT 24
Peak memory 206884 kb
Host smart-f9d8c378-79aa-4413-949f-058e481a792f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524058148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2524058148
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1194506969
Short name T640
Test name
Test status
Simulation time 16143519 ps
CPU time 0.89 seconds
Started May 07 03:16:58 PM PDT 24
Finished May 07 03:17:02 PM PDT 24
Peak memory 216636 kb
Host smart-0f7de07b-c09a-48bc-a1e8-e25c97075397
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194506969 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1194506969
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3776273868
Short name T409
Test name
Test status
Simulation time 34076588 ps
CPU time 1.13 seconds
Started May 07 03:16:57 PM PDT 24
Finished May 07 03:17:00 PM PDT 24
Peak memory 218528 kb
Host smart-f0a67ac3-1f50-4f68-b314-3593c1df3029
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776273868 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3776273868
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.2574023148
Short name T150
Test name
Test status
Simulation time 31661837 ps
CPU time 0.86 seconds
Started May 07 03:16:57 PM PDT 24
Finished May 07 03:17:00 PM PDT 24
Peak memory 218648 kb
Host smart-4d98cafa-8881-40fc-a638-e05c887c2284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574023148 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2574023148
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1382837808
Short name T10
Test name
Test status
Simulation time 824483514 ps
CPU time 6.83 seconds
Started May 07 03:16:57 PM PDT 24
Finished May 07 03:17:05 PM PDT 24
Peak memory 217716 kb
Host smart-e7534d6f-431d-4b3d-a25d-fa423272711b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382837808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1382837808
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_smoke.3580896305
Short name T615
Test name
Test status
Simulation time 26136043 ps
CPU time 0.91 seconds
Started May 07 03:16:58 PM PDT 24
Finished May 07 03:17:01 PM PDT 24
Peak memory 215628 kb
Host smart-80839f4e-19f7-45a4-b68b-082540dc89a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580896305 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3580896305
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2773133088
Short name T738
Test name
Test status
Simulation time 754930298 ps
CPU time 2.7 seconds
Started May 07 03:17:01 PM PDT 24
Finished May 07 03:17:05 PM PDT 24
Peak memory 220112 kb
Host smart-2a6fcf48-5907-420d-919c-b548ebae12f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773133088 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2773133088
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.553075599
Short name T581
Test name
Test status
Simulation time 42509120180 ps
CPU time 1047.29 seconds
Started May 07 03:16:58 PM PDT 24
Finished May 07 03:34:27 PM PDT 24
Peak memory 220492 kb
Host smart-d34c94be-0086-4f6f-8563-6775e8269ef2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553075599 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.553075599
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1710328716
Short name T339
Test name
Test status
Simulation time 45687832 ps
CPU time 1.49 seconds
Started May 07 03:18:21 PM PDT 24
Finished May 07 03:18:24 PM PDT 24
Peak memory 218460 kb
Host smart-f34ccff2-b24f-475d-b55e-9748edd20fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710328716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1710328716
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.4190461759
Short name T393
Test name
Test status
Simulation time 92419497 ps
CPU time 1.15 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:22 PM PDT 24
Peak memory 217276 kb
Host smart-f7ea2e61-6e59-47e0-8f8b-3449142000a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190461759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.4190461759
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3481648685
Short name T558
Test name
Test status
Simulation time 43358887 ps
CPU time 1.57 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:23 PM PDT 24
Peak memory 217636 kb
Host smart-74189dfb-17e9-4394-90b5-2a8fe7d3ee9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481648685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3481648685
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.780770544
Short name T280
Test name
Test status
Simulation time 32857820 ps
CPU time 1.24 seconds
Started May 07 03:18:17 PM PDT 24
Finished May 07 03:18:20 PM PDT 24
Peak memory 218640 kb
Host smart-35fea14e-9a8d-47ac-92e9-91420e8a6b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780770544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.780770544
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1760889844
Short name T96
Test name
Test status
Simulation time 250106062 ps
CPU time 1.33 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:27 PM PDT 24
Peak memory 217500 kb
Host smart-0896c9c0-d8b3-4d02-9207-da00da95144f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760889844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1760889844
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2954780588
Short name T760
Test name
Test status
Simulation time 114424282 ps
CPU time 1.24 seconds
Started May 07 03:18:21 PM PDT 24
Finished May 07 03:18:24 PM PDT 24
Peak memory 217412 kb
Host smart-fd84b0a5-dc34-48b4-9114-f7d7b195c26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954780588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2954780588
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1801485820
Short name T838
Test name
Test status
Simulation time 116858321 ps
CPU time 1.17 seconds
Started May 07 03:18:21 PM PDT 24
Finished May 07 03:18:24 PM PDT 24
Peak memory 217504 kb
Host smart-dbf72ffa-3e57-44af-99c1-dc93ea38ca61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801485820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1801485820
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3219226650
Short name T282
Test name
Test status
Simulation time 32234744 ps
CPU time 1.25 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:23 PM PDT 24
Peak memory 219940 kb
Host smart-99bdc754-a8e6-4502-9cfd-196f4b0507ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219226650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3219226650
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2144114664
Short name T91
Test name
Test status
Simulation time 113798818 ps
CPU time 1.54 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:27 PM PDT 24
Peak memory 220428 kb
Host smart-e610a76e-2ae7-49ed-ad85-a900ecc6e466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144114664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2144114664
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.673946845
Short name T405
Test name
Test status
Simulation time 61291203 ps
CPU time 1.47 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:24 PM PDT 24
Peak memory 218784 kb
Host smart-6adfafe6-5611-4b4f-9493-7f75cea659db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673946845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.673946845
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2004077501
Short name T775
Test name
Test status
Simulation time 136207084 ps
CPU time 1.37 seconds
Started May 07 03:16:59 PM PDT 24
Finished May 07 03:17:03 PM PDT 24
Peak memory 216068 kb
Host smart-84daaa7c-63d1-4a82-8ba7-6c2fddb3346c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004077501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2004077501
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2097979040
Short name T565
Test name
Test status
Simulation time 51628455 ps
CPU time 0.91 seconds
Started May 07 03:16:58 PM PDT 24
Finished May 07 03:17:02 PM PDT 24
Peak memory 206968 kb
Host smart-e5cb15c3-af49-4cbd-9d3b-35f38159d77c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097979040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2097979040
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2068452636
Short name T577
Test name
Test status
Simulation time 11593761 ps
CPU time 0.88 seconds
Started May 07 03:17:04 PM PDT 24
Finished May 07 03:17:07 PM PDT 24
Peak memory 216264 kb
Host smart-45e8478d-8cc0-4281-a02a-a3d9cff33939
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068452636 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2068452636
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.627357974
Short name T120
Test name
Test status
Simulation time 166947779 ps
CPU time 0.98 seconds
Started May 07 03:16:59 PM PDT 24
Finished May 07 03:17:03 PM PDT 24
Peak memory 217184 kb
Host smart-592ac164-8a59-4dde-ab3d-fdf020ef01b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627357974 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.627357974
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.323373707
Short name T689
Test name
Test status
Simulation time 21406522 ps
CPU time 0.91 seconds
Started May 07 03:17:01 PM PDT 24
Finished May 07 03:17:04 PM PDT 24
Peak memory 218840 kb
Host smart-f64a8ef8-31f9-4bd7-b405-1f18bbceaf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323373707 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.323373707
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1085773450
Short name T657
Test name
Test status
Simulation time 56730579 ps
CPU time 1.78 seconds
Started May 07 03:16:59 PM PDT 24
Finished May 07 03:17:03 PM PDT 24
Peak memory 217488 kb
Host smart-4d44a067-4766-4b97-a3c8-491cc3e940fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085773450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1085773450
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2303480008
Short name T805
Test name
Test status
Simulation time 24397362 ps
CPU time 0.98 seconds
Started May 07 03:16:57 PM PDT 24
Finished May 07 03:17:00 PM PDT 24
Peak memory 215932 kb
Host smart-10531253-ce84-485f-9bc4-ded6a2830af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303480008 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2303480008
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.821170305
Short name T648
Test name
Test status
Simulation time 15857687 ps
CPU time 0.96 seconds
Started May 07 03:16:57 PM PDT 24
Finished May 07 03:17:00 PM PDT 24
Peak memory 215608 kb
Host smart-580223a2-0981-4adf-a5cc-e8270471a0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821170305 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.821170305
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2624414686
Short name T782
Test name
Test status
Simulation time 834155771 ps
CPU time 1.82 seconds
Started May 07 03:16:58 PM PDT 24
Finished May 07 03:17:02 PM PDT 24
Peak memory 215608 kb
Host smart-a7b4bfe4-20bc-4564-8f9c-5f7232541957
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624414686 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2624414686
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/240.edn_genbits.488409617
Short name T383
Test name
Test status
Simulation time 21437098 ps
CPU time 1.12 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:22 PM PDT 24
Peak memory 219968 kb
Host smart-01e4a809-dcb4-418d-9047-acf445f90530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488409617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.488409617
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1594759496
Short name T355
Test name
Test status
Simulation time 67430603 ps
CPU time 1.32 seconds
Started May 07 03:18:22 PM PDT 24
Finished May 07 03:18:26 PM PDT 24
Peak memory 219008 kb
Host smart-20235df5-917f-40f8-b99b-1718ef604837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594759496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1594759496
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.876801023
Short name T244
Test name
Test status
Simulation time 53556753 ps
CPU time 1.07 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:23 PM PDT 24
Peak memory 217364 kb
Host smart-93d72312-8891-4746-a298-4807f89f8b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876801023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.876801023
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1345000325
Short name T580
Test name
Test status
Simulation time 53069514 ps
CPU time 1.33 seconds
Started May 07 03:18:21 PM PDT 24
Finished May 07 03:18:25 PM PDT 24
Peak memory 217396 kb
Host smart-03c6b90d-351b-4fa5-9fd8-037e4376a92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345000325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1345000325
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3858414614
Short name T604
Test name
Test status
Simulation time 64135533 ps
CPU time 1.12 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:22 PM PDT 24
Peak memory 217440 kb
Host smart-5fa6c29b-7db3-4a2f-b0f4-9a3a88a89172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858414614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3858414614
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1561192276
Short name T705
Test name
Test status
Simulation time 97036496 ps
CPU time 1.13 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:21 PM PDT 24
Peak memory 217508 kb
Host smart-5dd53f8a-14cb-430e-9987-89b257ff7c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561192276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1561192276
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.198502404
Short name T525
Test name
Test status
Simulation time 192205293 ps
CPU time 1.34 seconds
Started May 07 03:18:25 PM PDT 24
Finished May 07 03:18:29 PM PDT 24
Peak memory 218680 kb
Host smart-7f53b8b5-1608-4dde-8653-ad77593cbb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198502404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.198502404
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.4285181516
Short name T667
Test name
Test status
Simulation time 122482097 ps
CPU time 1.16 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:23 PM PDT 24
Peak memory 218716 kb
Host smart-91d2eb8d-4339-41e2-98c4-e916d366f43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285181516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.4285181516
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2404387954
Short name T546
Test name
Test status
Simulation time 78681239 ps
CPU time 2.6 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:28 PM PDT 24
Peak memory 220432 kb
Host smart-89481656-a523-44a9-b491-18eb88a68e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404387954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2404387954
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2401148115
Short name T326
Test name
Test status
Simulation time 93180065 ps
CPU time 1.39 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:26 PM PDT 24
Peak memory 218872 kb
Host smart-f671415a-83a0-429b-a4ec-8752a6de5b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401148115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2401148115
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3502454002
Short name T106
Test name
Test status
Simulation time 27754413 ps
CPU time 1.23 seconds
Started May 07 03:17:00 PM PDT 24
Finished May 07 03:17:04 PM PDT 24
Peak memory 216056 kb
Host smart-8f54cc82-e9ab-4983-9689-5fa3495d0211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502454002 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3502454002
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.506782110
Short name T571
Test name
Test status
Simulation time 22990197 ps
CPU time 0.91 seconds
Started May 07 03:16:59 PM PDT 24
Finished May 07 03:17:02 PM PDT 24
Peak memory 215200 kb
Host smart-9ad00c5c-ae5f-4867-9e21-b06616ece906
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506782110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.506782110
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3711775828
Short name T95
Test name
Test status
Simulation time 33407037 ps
CPU time 0.93 seconds
Started May 07 03:16:57 PM PDT 24
Finished May 07 03:17:00 PM PDT 24
Peak memory 216388 kb
Host smart-0db1a23e-5d3b-4fe1-8714-053361cfcdd0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711775828 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3711775828
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2669204689
Short name T121
Test name
Test status
Simulation time 30784975 ps
CPU time 1 seconds
Started May 07 03:17:00 PM PDT 24
Finished May 07 03:17:03 PM PDT 24
Peak memory 217288 kb
Host smart-1bf67914-cb0c-4a75-8c3b-beca79a53163
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669204689 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2669204689
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.288585990
Short name T118
Test name
Test status
Simulation time 67313886 ps
CPU time 1.09 seconds
Started May 07 03:16:57 PM PDT 24
Finished May 07 03:16:59 PM PDT 24
Peak memory 230084 kb
Host smart-e739a79a-93d3-4e62-b094-486865d13147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288585990 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.288585990
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2987032352
Short name T289
Test name
Test status
Simulation time 50905016 ps
CPU time 1.48 seconds
Started May 07 03:16:57 PM PDT 24
Finished May 07 03:17:01 PM PDT 24
Peak memory 217412 kb
Host smart-b1706310-bc10-411c-b30a-2a8867bf4b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987032352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2987032352
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.72191801
Short name T80
Test name
Test status
Simulation time 25714846 ps
CPU time 1.13 seconds
Started May 07 03:16:59 PM PDT 24
Finished May 07 03:17:03 PM PDT 24
Peak memory 215872 kb
Host smart-99396a73-f44b-4f10-aaae-6419c9eee504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72191801 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.72191801
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.377566728
Short name T826
Test name
Test status
Simulation time 52124421 ps
CPU time 0.99 seconds
Started May 07 03:16:58 PM PDT 24
Finished May 07 03:17:02 PM PDT 24
Peak memory 215612 kb
Host smart-78c0f21b-1450-4cca-822e-18ec16d09a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377566728 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.377566728
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2411102762
Short name T641
Test name
Test status
Simulation time 503647504 ps
CPU time 4.9 seconds
Started May 07 03:17:02 PM PDT 24
Finished May 07 03:17:09 PM PDT 24
Peak memory 215596 kb
Host smart-0cba2647-2c3d-4aca-93bb-1b6c398ad004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411102762 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2411102762
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3909683316
Short name T202
Test name
Test status
Simulation time 434209517437 ps
CPU time 1022.24 seconds
Started May 07 03:16:59 PM PDT 24
Finished May 07 03:34:04 PM PDT 24
Peak memory 221496 kb
Host smart-b00ed84f-518b-400c-8279-ad6137f71f83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909683316 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3909683316
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.618352235
Short name T771
Test name
Test status
Simulation time 34909561 ps
CPU time 1.41 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:27 PM PDT 24
Peak memory 218544 kb
Host smart-04a31e86-ae24-4841-84b3-4f8dd129a5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618352235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.618352235
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2968581400
Short name T15
Test name
Test status
Simulation time 121601963 ps
CPU time 1.19 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:23 PM PDT 24
Peak memory 219980 kb
Host smart-0e99009b-b428-4ef8-af3c-538f782320a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968581400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2968581400
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1294671503
Short name T419
Test name
Test status
Simulation time 73055732 ps
CPU time 1.08 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:27 PM PDT 24
Peak memory 217368 kb
Host smart-d37587a0-382b-4122-87d9-b7c4166736a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294671503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1294671503
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.4272253967
Short name T836
Test name
Test status
Simulation time 231678212 ps
CPU time 1.97 seconds
Started May 07 03:18:22 PM PDT 24
Finished May 07 03:18:26 PM PDT 24
Peak memory 218768 kb
Host smart-5641ffcc-1f9c-47c9-b15c-efb48ab5ae73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272253967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.4272253967
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1502514289
Short name T312
Test name
Test status
Simulation time 40341803 ps
CPU time 1.14 seconds
Started May 07 03:18:19 PM PDT 24
Finished May 07 03:18:23 PM PDT 24
Peak memory 217568 kb
Host smart-f735f0d3-102f-4272-8474-e06742d53667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502514289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1502514289
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3796284262
Short name T23
Test name
Test status
Simulation time 59659378 ps
CPU time 1.11 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:27 PM PDT 24
Peak memory 220084 kb
Host smart-677bc20f-b3e8-4548-acdc-11082a843fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796284262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3796284262
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.840726689
Short name T699
Test name
Test status
Simulation time 28072987 ps
CPU time 1.32 seconds
Started May 07 03:18:25 PM PDT 24
Finished May 07 03:18:29 PM PDT 24
Peak memory 217296 kb
Host smart-3b0c6071-3866-411c-bb5e-c9dcf860b815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840726689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.840726689
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1249481022
Short name T753
Test name
Test status
Simulation time 28057157 ps
CPU time 1.28 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:27 PM PDT 24
Peak memory 217376 kb
Host smart-17d0918c-c9a6-49c9-b64b-580163b1a159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249481022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1249481022
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.865405523
Short name T436
Test name
Test status
Simulation time 30625629 ps
CPU time 1.27 seconds
Started May 07 03:18:25 PM PDT 24
Finished May 07 03:18:29 PM PDT 24
Peak memory 218404 kb
Host smart-756f139d-90a3-43de-a785-cdac1726d26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865405523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.865405523
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1946816042
Short name T814
Test name
Test status
Simulation time 50219653 ps
CPU time 1.32 seconds
Started May 07 03:18:24 PM PDT 24
Finished May 07 03:18:28 PM PDT 24
Peak memory 218784 kb
Host smart-af5717ae-7af3-4bf5-bc41-5b94118b76e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946816042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1946816042
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert_test.3188500034
Short name T246
Test name
Test status
Simulation time 185016690 ps
CPU time 0.94 seconds
Started May 07 03:17:07 PM PDT 24
Finished May 07 03:17:09 PM PDT 24
Peak memory 207004 kb
Host smart-cd55a638-9441-4680-bdd3-31846d99e199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188500034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3188500034
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1037241248
Short name T186
Test name
Test status
Simulation time 50189195 ps
CPU time 0.87 seconds
Started May 07 03:17:04 PM PDT 24
Finished May 07 03:17:07 PM PDT 24
Peak memory 216756 kb
Host smart-ef5ca5dd-1e45-456a-906b-4e8eb319737f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037241248 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1037241248
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1039325951
Short name T719
Test name
Test status
Simulation time 83977327 ps
CPU time 1.01 seconds
Started May 07 03:17:05 PM PDT 24
Finished May 07 03:17:08 PM PDT 24
Peak memory 217276 kb
Host smart-69ad7f80-fbe3-4697-8f2e-2d7158b2d6ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039325951 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1039325951
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3277045363
Short name T612
Test name
Test status
Simulation time 19066303 ps
CPU time 1.07 seconds
Started May 07 03:17:09 PM PDT 24
Finished May 07 03:17:11 PM PDT 24
Peak memory 219160 kb
Host smart-79655f37-82e5-4fc6-8990-338d869f45cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277045363 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3277045363
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3782723359
Short name T535
Test name
Test status
Simulation time 116060516 ps
CPU time 1.73 seconds
Started May 07 03:17:04 PM PDT 24
Finished May 07 03:17:07 PM PDT 24
Peak memory 220276 kb
Host smart-d58590f1-6cd3-4b6a-9736-e80859955229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782723359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3782723359
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2127281412
Short name T158
Test name
Test status
Simulation time 23369984 ps
CPU time 0.97 seconds
Started May 07 03:16:58 PM PDT 24
Finished May 07 03:17:01 PM PDT 24
Peak memory 216264 kb
Host smart-968a251b-6928-43ae-97cd-31f33c0f4f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127281412 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2127281412
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2260881817
Short name T379
Test name
Test status
Simulation time 16549846 ps
CPU time 1.02 seconds
Started May 07 03:16:59 PM PDT 24
Finished May 07 03:17:03 PM PDT 24
Peak memory 215696 kb
Host smart-9a4474c4-911c-46d1-8a23-e0004c00ec1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260881817 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2260881817
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1766245312
Short name T809
Test name
Test status
Simulation time 183457044 ps
CPU time 2.49 seconds
Started May 07 03:16:57 PM PDT 24
Finished May 07 03:17:01 PM PDT 24
Peak memory 217248 kb
Host smart-ff0a92dd-718d-4fe6-bad1-15fe73101c4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766245312 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1766245312
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/260.edn_genbits.2218990325
Short name T364
Test name
Test status
Simulation time 96133770 ps
CPU time 1.2 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:27 PM PDT 24
Peak memory 217364 kb
Host smart-b518fa94-2c0f-4341-803a-cbe115f1e83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218990325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2218990325
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3696510154
Short name T655
Test name
Test status
Simulation time 30329494 ps
CPU time 1.2 seconds
Started May 07 03:18:25 PM PDT 24
Finished May 07 03:18:29 PM PDT 24
Peak memory 217392 kb
Host smart-2836bc10-b9e1-45f2-ab42-6981d90152a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696510154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3696510154
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1324735347
Short name T400
Test name
Test status
Simulation time 87403681 ps
CPU time 2.39 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:28 PM PDT 24
Peak memory 220276 kb
Host smart-ae17494b-6890-4ec8-9055-27ef247cc566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324735347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1324735347
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1868408699
Short name T403
Test name
Test status
Simulation time 109222991 ps
CPU time 1.59 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:28 PM PDT 24
Peak memory 218772 kb
Host smart-0468943b-6798-4423-a311-49019edca94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868408699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1868408699
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.591829630
Short name T532
Test name
Test status
Simulation time 106324182 ps
CPU time 1.35 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:27 PM PDT 24
Peak memory 217512 kb
Host smart-00c478d5-d048-4d52-b5ef-2e57e74c015b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591829630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.591829630
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.978174844
Short name T709
Test name
Test status
Simulation time 107956624 ps
CPU time 1.24 seconds
Started May 07 03:18:20 PM PDT 24
Finished May 07 03:18:24 PM PDT 24
Peak memory 218544 kb
Host smart-a67ed49c-b998-40ba-af86-75a56338c1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978174844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.978174844
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2742120370
Short name T600
Test name
Test status
Simulation time 69867021 ps
CPU time 0.99 seconds
Started May 07 03:18:24 PM PDT 24
Finished May 07 03:18:28 PM PDT 24
Peak memory 217464 kb
Host smart-fbb652a4-bd06-4319-84e7-97ced9e2f453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742120370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2742120370
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.129595002
Short name T797
Test name
Test status
Simulation time 40463094 ps
CPU time 1.39 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:27 PM PDT 24
Peak memory 218564 kb
Host smart-57d3d94f-2865-4855-a384-13af801bd619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129595002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.129595002
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1672254720
Short name T660
Test name
Test status
Simulation time 85042947 ps
CPU time 1.49 seconds
Started May 07 03:18:25 PM PDT 24
Finished May 07 03:18:29 PM PDT 24
Peak memory 218968 kb
Host smart-f8575e32-58d5-4483-b2eb-c637c578d9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672254720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1672254720
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.628111877
Short name T54
Test name
Test status
Simulation time 25051127 ps
CPU time 1.19 seconds
Started May 07 03:17:04 PM PDT 24
Finished May 07 03:17:07 PM PDT 24
Peak memory 216080 kb
Host smart-a8095d06-ab15-42b2-99de-ee7a62318267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628111877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.628111877
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.474392788
Short name T461
Test name
Test status
Simulation time 64762014 ps
CPU time 0.9 seconds
Started May 07 03:17:03 PM PDT 24
Finished May 07 03:17:06 PM PDT 24
Peak memory 206956 kb
Host smart-f9a109e7-11df-4b14-a10a-6e6d956c6e83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474392788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.474392788
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.4162879152
Short name T341
Test name
Test status
Simulation time 56765419 ps
CPU time 0.87 seconds
Started May 07 03:17:07 PM PDT 24
Finished May 07 03:17:09 PM PDT 24
Peak memory 216644 kb
Host smart-2834714c-1752-4f7d-b29a-2872e134a376
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162879152 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.4162879152
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.4292722711
Short name T599
Test name
Test status
Simulation time 18176753 ps
CPU time 1.01 seconds
Started May 07 03:17:09 PM PDT 24
Finished May 07 03:17:11 PM PDT 24
Peak memory 218676 kb
Host smart-13df83e7-e1ae-4f78-b01f-57a72cb74c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292722711 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.4292722711
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.4124647990
Short name T376
Test name
Test status
Simulation time 92046501 ps
CPU time 1.76 seconds
Started May 07 03:17:07 PM PDT 24
Finished May 07 03:17:10 PM PDT 24
Peak memory 218652 kb
Host smart-67563147-9e46-46f0-9fba-cbe70956a094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124647990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.4124647990
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1649628388
Short name T425
Test name
Test status
Simulation time 27506190 ps
CPU time 0.98 seconds
Started May 07 03:17:06 PM PDT 24
Finished May 07 03:17:09 PM PDT 24
Peak memory 215996 kb
Host smart-8918d572-47ff-4b45-bc18-648c85016b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649628388 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1649628388
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3750119954
Short name T573
Test name
Test status
Simulation time 23332739 ps
CPU time 0.89 seconds
Started May 07 03:17:07 PM PDT 24
Finished May 07 03:17:09 PM PDT 24
Peak memory 207412 kb
Host smart-e49aaf49-388f-487f-8559-0e9a96a4e6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750119954 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3750119954
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3249800442
Short name T218
Test name
Test status
Simulation time 265495007 ps
CPU time 5.54 seconds
Started May 07 03:17:04 PM PDT 24
Finished May 07 03:17:11 PM PDT 24
Peak memory 217256 kb
Host smart-75e69f88-c4a9-43d0-a0b2-58acce084fcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249800442 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3249800442
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3374531022
Short name T199
Test name
Test status
Simulation time 20168489001 ps
CPU time 234.82 seconds
Started May 07 03:17:06 PM PDT 24
Finished May 07 03:21:03 PM PDT 24
Peak memory 219104 kb
Host smart-8b20ce1b-29fe-4629-94a3-446402292b5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374531022 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3374531022
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1060924499
Short name T307
Test name
Test status
Simulation time 107549936 ps
CPU time 1.13 seconds
Started May 07 03:18:25 PM PDT 24
Finished May 07 03:18:29 PM PDT 24
Peak memory 217512 kb
Host smart-e8592171-2f59-4ece-ace9-c997555b7199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060924499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1060924499
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.924524254
Short name T269
Test name
Test status
Simulation time 762535549 ps
CPU time 4.65 seconds
Started May 07 03:18:22 PM PDT 24
Finished May 07 03:18:29 PM PDT 24
Peak memory 219860 kb
Host smart-3c4f6aaf-1adc-42be-8455-a01682e87dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924524254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.924524254
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3704159649
Short name T816
Test name
Test status
Simulation time 101288268 ps
CPU time 1.55 seconds
Started May 07 03:18:25 PM PDT 24
Finished May 07 03:18:30 PM PDT 24
Peak memory 217364 kb
Host smart-74991c53-51f3-4594-8cc1-4ed11e25f194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704159649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3704159649
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3484248561
Short name T680
Test name
Test status
Simulation time 128555576 ps
CPU time 1.16 seconds
Started May 07 03:18:24 PM PDT 24
Finished May 07 03:18:28 PM PDT 24
Peak memory 219284 kb
Host smart-6f5c25c5-185c-4485-86c1-599d74eb04ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484248561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3484248561
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.668357370
Short name T643
Test name
Test status
Simulation time 31820169 ps
CPU time 1.32 seconds
Started May 07 03:18:25 PM PDT 24
Finished May 07 03:18:29 PM PDT 24
Peak memory 215680 kb
Host smart-4e0f2917-321e-408c-ade7-df2d15a7c47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668357370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.668357370
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1540796443
Short name T770
Test name
Test status
Simulation time 99045687 ps
CPU time 1.25 seconds
Started May 07 03:18:29 PM PDT 24
Finished May 07 03:18:32 PM PDT 24
Peak memory 218572 kb
Host smart-a6be4d1b-7454-42ce-baa9-11f8f3648165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540796443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1540796443
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3477841165
Short name T701
Test name
Test status
Simulation time 49331075 ps
CPU time 1.18 seconds
Started May 07 03:18:24 PM PDT 24
Finished May 07 03:18:28 PM PDT 24
Peak memory 217256 kb
Host smart-004e3cf9-022c-44cb-a14a-ab1bd78f6f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477841165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3477841165
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2986994559
Short name T477
Test name
Test status
Simulation time 54080211 ps
CPU time 1.01 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:27 PM PDT 24
Peak memory 217376 kb
Host smart-c611ac7c-6fa7-45a7-ad26-e070969c435c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986994559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2986994559
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.79607307
Short name T621
Test name
Test status
Simulation time 47881200 ps
CPU time 1.27 seconds
Started May 07 03:18:24 PM PDT 24
Finished May 07 03:18:28 PM PDT 24
Peak memory 217292 kb
Host smart-8e7d8a8a-6b3f-4904-adeb-1b474ed86dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79607307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.79607307
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2635034463
Short name T14
Test name
Test status
Simulation time 386365677 ps
CPU time 1.47 seconds
Started May 07 03:18:25 PM PDT 24
Finished May 07 03:18:30 PM PDT 24
Peak memory 220008 kb
Host smart-51b3e843-7ff8-451e-badc-acfadcc9bc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635034463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2635034463
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.2843927847
Short name T211
Test name
Test status
Simulation time 43055632 ps
CPU time 0.81 seconds
Started May 07 03:17:09 PM PDT 24
Finished May 07 03:17:10 PM PDT 24
Peak memory 206204 kb
Host smart-67827edf-fee2-4cba-b3d9-3431b06e7ae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843927847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2843927847
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_err.2024158290
Short name T617
Test name
Test status
Simulation time 37740304 ps
CPU time 0.85 seconds
Started May 07 03:17:05 PM PDT 24
Finished May 07 03:17:08 PM PDT 24
Peak memory 218744 kb
Host smart-751eb9d2-1e88-4ec5-b64c-e608170e7eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024158290 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2024158290
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3739448923
Short name T628
Test name
Test status
Simulation time 42163180 ps
CPU time 1.06 seconds
Started May 07 03:17:04 PM PDT 24
Finished May 07 03:17:06 PM PDT 24
Peak memory 217524 kb
Host smart-bc2fbeb3-7e55-4ded-8576-3b39112e1589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739448923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3739448923
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2612837611
Short name T674
Test name
Test status
Simulation time 21393206 ps
CPU time 1.17 seconds
Started May 07 03:17:07 PM PDT 24
Finished May 07 03:17:09 PM PDT 24
Peak memory 224428 kb
Host smart-2d68fe8a-a81c-458b-834d-6acf2dcdf4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612837611 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2612837611
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3307542726
Short name T579
Test name
Test status
Simulation time 17423600 ps
CPU time 1.04 seconds
Started May 07 03:17:06 PM PDT 24
Finished May 07 03:17:08 PM PDT 24
Peak memory 207420 kb
Host smart-e603ee3b-5660-4c55-b983-fdc3b2d6b2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307542726 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3307542726
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1028984411
Short name T649
Test name
Test status
Simulation time 33901659 ps
CPU time 0.95 seconds
Started May 07 03:17:11 PM PDT 24
Finished May 07 03:17:14 PM PDT 24
Peak memory 206636 kb
Host smart-ac379b37-f370-49ac-acb0-c42fa4cf7d00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028984411 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1028984411
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2307440728
Short name T206
Test name
Test status
Simulation time 96947864642 ps
CPU time 1081.89 seconds
Started May 07 03:17:06 PM PDT 24
Finished May 07 03:35:09 PM PDT 24
Peak memory 222676 kb
Host smart-46fea417-b1a3-4ebd-9d0d-45956a839045
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307440728 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2307440728
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1440476535
Short name T342
Test name
Test status
Simulation time 27921272 ps
CPU time 1.22 seconds
Started May 07 03:18:25 PM PDT 24
Finished May 07 03:18:29 PM PDT 24
Peak memory 217412 kb
Host smart-8fe5a67a-5fff-4338-b048-5edadcba26c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440476535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1440476535
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2365949615
Short name T367
Test name
Test status
Simulation time 57681982 ps
CPU time 1.34 seconds
Started May 07 03:18:25 PM PDT 24
Finished May 07 03:18:29 PM PDT 24
Peak memory 218976 kb
Host smart-d70d9186-8066-4e1b-af26-07a4879fc4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365949615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2365949615
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2058424549
Short name T1
Test name
Test status
Simulation time 46509418 ps
CPU time 1.15 seconds
Started May 07 03:18:25 PM PDT 24
Finished May 07 03:18:30 PM PDT 24
Peak memory 218808 kb
Host smart-dcbb6bcd-8b61-457f-a19c-29af9175910c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058424549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2058424549
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1631740888
Short name T387
Test name
Test status
Simulation time 35277854 ps
CPU time 1.38 seconds
Started May 07 03:18:27 PM PDT 24
Finished May 07 03:18:31 PM PDT 24
Peak memory 218404 kb
Host smart-36235807-e324-4a9a-8b2a-2349e6a972ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631740888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1631740888
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1129094755
Short name T274
Test name
Test status
Simulation time 291147865 ps
CPU time 3.54 seconds
Started May 07 03:18:27 PM PDT 24
Finished May 07 03:18:33 PM PDT 24
Peak memory 218652 kb
Host smart-ae3494f6-8a0d-4189-bc19-bfaf48208211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129094755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1129094755
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.4083259838
Short name T777
Test name
Test status
Simulation time 43135994 ps
CPU time 1.79 seconds
Started May 07 03:18:24 PM PDT 24
Finished May 07 03:18:28 PM PDT 24
Peak memory 217788 kb
Host smart-d6c5effc-4db1-4d80-a3df-11b149438795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083259838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.4083259838
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1524246838
Short name T347
Test name
Test status
Simulation time 568746770 ps
CPU time 5.48 seconds
Started May 07 03:18:24 PM PDT 24
Finished May 07 03:18:33 PM PDT 24
Peak memory 220376 kb
Host smart-bc2a8750-7ce4-41bb-9e60-4947d2caf558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524246838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1524246838
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.491669956
Short name T345
Test name
Test status
Simulation time 70522217 ps
CPU time 1.15 seconds
Started May 07 03:18:28 PM PDT 24
Finished May 07 03:18:31 PM PDT 24
Peak memory 219544 kb
Host smart-c0ddc129-7c3b-4402-983e-6d2a4acb7809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491669956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.491669956
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.281128477
Short name T424
Test name
Test status
Simulation time 124698142 ps
CPU time 0.97 seconds
Started May 07 03:18:25 PM PDT 24
Finished May 07 03:18:29 PM PDT 24
Peak memory 217436 kb
Host smart-0f725479-35dc-4c9d-b278-74b0e91db488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281128477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.281128477
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1644702369
Short name T320
Test name
Test status
Simulation time 77220401 ps
CPU time 1.07 seconds
Started May 07 03:18:25 PM PDT 24
Finished May 07 03:18:29 PM PDT 24
Peak memory 217784 kb
Host smart-2818d821-630b-455e-afc7-a1afa34d47b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644702369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1644702369
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.3234442756
Short name T636
Test name
Test status
Simulation time 28847667 ps
CPU time 1.34 seconds
Started May 07 03:17:04 PM PDT 24
Finished May 07 03:17:07 PM PDT 24
Peak memory 216092 kb
Host smart-4d86043f-573f-4446-8802-c80aefdfc1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234442756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3234442756
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1887455906
Short name T560
Test name
Test status
Simulation time 17194701 ps
CPU time 0.91 seconds
Started May 07 03:17:08 PM PDT 24
Finished May 07 03:17:10 PM PDT 24
Peak memory 206964 kb
Host smart-47837d3f-b777-4143-9e0c-a10dbbd4caf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887455906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1887455906
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1277950821
Short name T677
Test name
Test status
Simulation time 34320193 ps
CPU time 1.23 seconds
Started May 07 03:17:03 PM PDT 24
Finished May 07 03:17:06 PM PDT 24
Peak memory 217228 kb
Host smart-611bf890-1532-46e0-b5be-7d2b9ed34c66
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277950821 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1277950821
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2912454206
Short name T673
Test name
Test status
Simulation time 107734580 ps
CPU time 1.09 seconds
Started May 07 03:17:06 PM PDT 24
Finished May 07 03:17:09 PM PDT 24
Peak memory 219940 kb
Host smart-feb9b916-184f-4269-a7b3-1448b0051935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912454206 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2912454206
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3665830060
Short name T290
Test name
Test status
Simulation time 129035587 ps
CPU time 1.73 seconds
Started May 07 03:17:05 PM PDT 24
Finished May 07 03:17:08 PM PDT 24
Peak memory 218720 kb
Host smart-84f276f8-72df-45b9-8fc0-da621cf73cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665830060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3665830060
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_smoke.1317859106
Short name T544
Test name
Test status
Simulation time 48436799 ps
CPU time 0.9 seconds
Started May 07 03:17:05 PM PDT 24
Finished May 07 03:17:08 PM PDT 24
Peak memory 215640 kb
Host smart-809e78a3-3bb6-429f-94f8-620b6d888940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317859106 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1317859106
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3957908118
Short name T742
Test name
Test status
Simulation time 464563111 ps
CPU time 3.57 seconds
Started May 07 03:17:06 PM PDT 24
Finished May 07 03:17:11 PM PDT 24
Peak memory 217300 kb
Host smart-2bf693de-f56e-41e6-91a6-60c3309f7850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957908118 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3957908118
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1302202117
Short name T200
Test name
Test status
Simulation time 333181320498 ps
CPU time 2157.6 seconds
Started May 07 03:17:05 PM PDT 24
Finished May 07 03:53:05 PM PDT 24
Peak memory 229916 kb
Host smart-b426d50d-f16b-4c96-b983-dc6b4acaacb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302202117 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1302202117
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.3919198764
Short name T243
Test name
Test status
Simulation time 115814807 ps
CPU time 1.44 seconds
Started May 07 03:18:25 PM PDT 24
Finished May 07 03:18:30 PM PDT 24
Peak memory 219052 kb
Host smart-9342dc6f-ce2c-49c7-b51b-bf5df904bd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919198764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3919198764
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3779474872
Short name T587
Test name
Test status
Simulation time 49109890 ps
CPU time 1.41 seconds
Started May 07 03:18:25 PM PDT 24
Finished May 07 03:18:30 PM PDT 24
Peak memory 219856 kb
Host smart-375d69db-da0a-4f8c-8f6c-13a37db4abab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779474872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3779474872
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2943713026
Short name T11
Test name
Test status
Simulation time 121794125 ps
CPU time 1.82 seconds
Started May 07 03:18:27 PM PDT 24
Finished May 07 03:18:31 PM PDT 24
Peak memory 217640 kb
Host smart-c469740c-d3a6-474b-a358-bd855d8121c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943713026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2943713026
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.4280158799
Short name T348
Test name
Test status
Simulation time 57709925 ps
CPU time 1.21 seconds
Started May 07 03:18:25 PM PDT 24
Finished May 07 03:18:29 PM PDT 24
Peak memory 217272 kb
Host smart-8857ad67-3a73-4c6d-8d6c-7010a165a4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280158799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.4280158799
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3424076279
Short name T520
Test name
Test status
Simulation time 26358450 ps
CPU time 1.23 seconds
Started May 07 03:18:23 PM PDT 24
Finished May 07 03:18:27 PM PDT 24
Peak memory 217480 kb
Host smart-970c624f-4733-4f9d-8ef4-e844b640be60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424076279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3424076279
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1432328660
Short name T434
Test name
Test status
Simulation time 88277353 ps
CPU time 1.61 seconds
Started May 07 03:18:26 PM PDT 24
Finished May 07 03:18:30 PM PDT 24
Peak memory 218780 kb
Host smart-a898b4dc-c486-4385-bbbb-b3341117071b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432328660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1432328660
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3120954036
Short name T513
Test name
Test status
Simulation time 64966927 ps
CPU time 1.32 seconds
Started May 07 03:18:27 PM PDT 24
Finished May 07 03:18:30 PM PDT 24
Peak memory 218704 kb
Host smart-da00f168-3604-4795-8743-f8eaf46863c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120954036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3120954036
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.145970373
Short name T481
Test name
Test status
Simulation time 38340055 ps
CPU time 1.55 seconds
Started May 07 03:18:25 PM PDT 24
Finished May 07 03:18:29 PM PDT 24
Peak memory 219852 kb
Host smart-576555bc-f8f5-41d3-ba63-3cc7aa94cc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145970373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.145970373
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3536812415
Short name T678
Test name
Test status
Simulation time 45376434 ps
CPU time 1.65 seconds
Started May 07 03:18:27 PM PDT 24
Finished May 07 03:18:31 PM PDT 24
Peak memory 217444 kb
Host smart-d56a85cf-d772-4865-9267-3106e3cac54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536812415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3536812415
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.497140951
Short name T53
Test name
Test status
Simulation time 107178954 ps
CPU time 2.32 seconds
Started May 07 03:18:27 PM PDT 24
Finished May 07 03:18:32 PM PDT 24
Peak memory 219060 kb
Host smart-ab555caf-a724-449f-8c7b-9620ab8d31e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497140951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.497140951
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1779652989
Short name T497
Test name
Test status
Simulation time 86205136 ps
CPU time 1.18 seconds
Started May 07 03:16:20 PM PDT 24
Finished May 07 03:16:22 PM PDT 24
Peak memory 216016 kb
Host smart-b7672c93-d356-42d3-9b38-934d8aa290ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779652989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1779652989
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.77171149
Short name T578
Test name
Test status
Simulation time 37893798 ps
CPU time 1.06 seconds
Started May 07 03:16:21 PM PDT 24
Finished May 07 03:16:23 PM PDT 24
Peak memory 215212 kb
Host smart-48f73903-5137-4f55-b9b7-d1af419a03be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77171149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.77171149
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.264515599
Short name T183
Test name
Test status
Simulation time 17846109 ps
CPU time 0.86 seconds
Started May 07 03:16:21 PM PDT 24
Finished May 07 03:16:24 PM PDT 24
Peak memory 216628 kb
Host smart-5d2fbcdd-4cc2-44fd-936e-286906bc92a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264515599 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.264515599
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2064805309
Short name T115
Test name
Test status
Simulation time 41858474 ps
CPU time 1.36 seconds
Started May 07 03:16:22 PM PDT 24
Finished May 07 03:16:24 PM PDT 24
Peak memory 217272 kb
Host smart-0a7ae89a-542c-4548-82c3-0cb2800fbfa5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064805309 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2064805309
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1104860194
Short name T181
Test name
Test status
Simulation time 18674082 ps
CPU time 1.04 seconds
Started May 07 03:16:20 PM PDT 24
Finished May 07 03:16:22 PM PDT 24
Peak memory 218968 kb
Host smart-3c62cc63-3192-4728-9d21-8d149149eb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104860194 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1104860194
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1631392848
Short name T732
Test name
Test status
Simulation time 37979905 ps
CPU time 1.47 seconds
Started May 07 03:16:21 PM PDT 24
Finished May 07 03:16:24 PM PDT 24
Peak memory 218588 kb
Host smart-53eebada-0423-43f9-ad2d-6e470a59db1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631392848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1631392848
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2134374667
Short name T309
Test name
Test status
Simulation time 25995924 ps
CPU time 0.98 seconds
Started May 07 03:16:20 PM PDT 24
Finished May 07 03:16:23 PM PDT 24
Peak memory 216000 kb
Host smart-f48e44b6-38a9-4332-a9ab-1fadb33a5ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134374667 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2134374667
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1025038660
Short name T293
Test name
Test status
Simulation time 19415805 ps
CPU time 1.01 seconds
Started May 07 03:16:21 PM PDT 24
Finished May 07 03:16:23 PM PDT 24
Peak memory 207420 kb
Host smart-64a936b4-6f15-41ed-8041-8e00192900b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025038660 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1025038660
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.808300116
Short name T65
Test name
Test status
Simulation time 598005656 ps
CPU time 8.61 seconds
Started May 07 03:16:20 PM PDT 24
Finished May 07 03:16:30 PM PDT 24
Peak memory 243324 kb
Host smart-09c45a9a-6796-4873-98ae-fe1234427720
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808300116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.808300116
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.409064715
Short name T645
Test name
Test status
Simulation time 16837389 ps
CPU time 0.99 seconds
Started May 07 03:16:20 PM PDT 24
Finished May 07 03:16:23 PM PDT 24
Peak memory 215664 kb
Host smart-ed891f19-9713-443d-853a-232a5702b9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409064715 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.409064715
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3978873133
Short name T676
Test name
Test status
Simulation time 387262426 ps
CPU time 4.29 seconds
Started May 07 03:16:21 PM PDT 24
Finished May 07 03:16:27 PM PDT 24
Peak memory 217212 kb
Host smart-7fe3f280-7796-4f2a-b363-2a03d277876e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978873133 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3978873133
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2976248440
Short name T798
Test name
Test status
Simulation time 107886671508 ps
CPU time 1192.09 seconds
Started May 07 03:16:22 PM PDT 24
Finished May 07 03:36:15 PM PDT 24
Peak memory 223152 kb
Host smart-4d08e146-7cb5-4bb8-b649-8aab18fc8626
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976248440 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2976248440
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1104575158
Short name T3
Test name
Test status
Simulation time 79986359 ps
CPU time 1.2 seconds
Started May 07 03:17:14 PM PDT 24
Finished May 07 03:17:16 PM PDT 24
Peak memory 216084 kb
Host smart-7b61e264-1918-40ab-a60d-c12995e40f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104575158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1104575158
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1572265695
Short name T456
Test name
Test status
Simulation time 31438316 ps
CPU time 0.77 seconds
Started May 07 03:17:10 PM PDT 24
Finished May 07 03:17:12 PM PDT 24
Peak memory 206304 kb
Host smart-895b10c9-c339-4378-ad07-ddce5650d9f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572265695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1572265695
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3246594133
Short name T679
Test name
Test status
Simulation time 44173097 ps
CPU time 0.83 seconds
Started May 07 03:17:09 PM PDT 24
Finished May 07 03:17:10 PM PDT 24
Peak memory 216776 kb
Host smart-e71d8ef0-59f4-48df-8e37-393501fa06b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246594133 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3246594133
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2062807766
Short name T126
Test name
Test status
Simulation time 101827536 ps
CPU time 1.12 seconds
Started May 07 03:17:11 PM PDT 24
Finished May 07 03:17:14 PM PDT 24
Peak memory 217216 kb
Host smart-5561d665-ab7a-425c-abce-0e00237e179e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062807766 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2062807766
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.953256942
Short name T141
Test name
Test status
Simulation time 21926880 ps
CPU time 1.06 seconds
Started May 07 03:17:09 PM PDT 24
Finished May 07 03:17:11 PM PDT 24
Peak memory 219084 kb
Host smart-4625e010-02f9-486e-b70e-fc9dffd8329f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953256942 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.953256942
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.515107133
Short name T501
Test name
Test status
Simulation time 105726177 ps
CPU time 1.61 seconds
Started May 07 03:17:10 PM PDT 24
Finished May 07 03:17:13 PM PDT 24
Peak memory 218920 kb
Host smart-c4b78f82-4fdb-4be6-9b81-c73b1aaf16e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515107133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.515107133
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.928228628
Short name T422
Test name
Test status
Simulation time 20978933 ps
CPU time 1.09 seconds
Started May 07 03:17:08 PM PDT 24
Finished May 07 03:17:10 PM PDT 24
Peak memory 215824 kb
Host smart-48bb8565-af9c-4faf-b507-5605375c90b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928228628 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.928228628
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1182727905
Short name T531
Test name
Test status
Simulation time 126144443 ps
CPU time 0.89 seconds
Started May 07 03:17:10 PM PDT 24
Finished May 07 03:17:13 PM PDT 24
Peak memory 215612 kb
Host smart-91d13f7f-038c-4856-8ef3-0baefd697987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182727905 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1182727905
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.272436487
Short name T774
Test name
Test status
Simulation time 705393326 ps
CPU time 2.15 seconds
Started May 07 03:17:11 PM PDT 24
Finished May 07 03:17:15 PM PDT 24
Peak memory 217212 kb
Host smart-a627dc8f-7c1a-4874-8b09-bc5dc5f59b12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272436487 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.272436487
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2504452631
Short name T552
Test name
Test status
Simulation time 640779052869 ps
CPU time 1360.3 seconds
Started May 07 03:17:11 PM PDT 24
Finished May 07 03:39:53 PM PDT 24
Peak memory 224092 kb
Host smart-d5e67447-1d07-43f3-b3ae-f4584487b7f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504452631 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2504452631
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1165715251
Short name T191
Test name
Test status
Simulation time 44265126 ps
CPU time 1.21 seconds
Started May 07 03:17:12 PM PDT 24
Finished May 07 03:17:15 PM PDT 24
Peak memory 216052 kb
Host smart-477bf098-45f9-4f36-94db-b07fa989adba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165715251 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1165715251
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3806749918
Short name T71
Test name
Test status
Simulation time 59159726 ps
CPU time 0.94 seconds
Started May 07 03:17:16 PM PDT 24
Finished May 07 03:17:18 PM PDT 24
Peak memory 215128 kb
Host smart-8292e6a8-0060-4b78-8c0b-851ff1efd64b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806749918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3806749918
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.1652800232
Short name T529
Test name
Test status
Simulation time 101670729 ps
CPU time 0.84 seconds
Started May 07 03:17:11 PM PDT 24
Finished May 07 03:17:13 PM PDT 24
Peak memory 216300 kb
Host smart-6330cde7-4377-4350-9fae-84bf290b890d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652800232 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1652800232
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.4071137156
Short name T613
Test name
Test status
Simulation time 120658716 ps
CPU time 0.96 seconds
Started May 07 03:17:11 PM PDT 24
Finished May 07 03:17:14 PM PDT 24
Peak memory 218608 kb
Host smart-c75f7f57-dfa4-4a84-8cb6-4b4506a06bd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071137156 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.4071137156
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.835759831
Short name T17
Test name
Test status
Simulation time 69704241 ps
CPU time 1.16 seconds
Started May 07 03:17:14 PM PDT 24
Finished May 07 03:17:16 PM PDT 24
Peak memory 226264 kb
Host smart-0da324ef-7d6a-4a34-bc58-afdcb46d7c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835759831 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.835759831
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3052186255
Short name T593
Test name
Test status
Simulation time 126302895 ps
CPU time 1.27 seconds
Started May 07 03:17:12 PM PDT 24
Finished May 07 03:17:15 PM PDT 24
Peak memory 219048 kb
Host smart-7a970804-90d1-4d44-a71f-8d4e1b0c3497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052186255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3052186255
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3787025328
Short name T786
Test name
Test status
Simulation time 21935823 ps
CPU time 1.03 seconds
Started May 07 03:17:16 PM PDT 24
Finished May 07 03:17:19 PM PDT 24
Peak memory 215932 kb
Host smart-edc8e390-2a96-4432-a0a5-ed6a89ec3ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787025328 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3787025328
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3291491517
Short name T446
Test name
Test status
Simulation time 28670652 ps
CPU time 0.94 seconds
Started May 07 03:17:10 PM PDT 24
Finished May 07 03:17:13 PM PDT 24
Peak memory 215624 kb
Host smart-23e90f60-21db-43cf-9bd1-6dd0d98a0f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291491517 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3291491517
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.798229371
Short name T584
Test name
Test status
Simulation time 700597999 ps
CPU time 5.52 seconds
Started May 07 03:17:12 PM PDT 24
Finished May 07 03:17:20 PM PDT 24
Peak memory 215700 kb
Host smart-0dbc74e9-8151-4adc-bb29-aead0a938597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798229371 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.798229371
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.286015304
Short name T205
Test name
Test status
Simulation time 1686948334989 ps
CPU time 2773.83 seconds
Started May 07 03:17:10 PM PDT 24
Finished May 07 04:03:26 PM PDT 24
Peak memory 228284 kb
Host smart-10e6d38a-bcac-4012-a764-0a8b1c2cf006
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286015304 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.286015304
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.877403044
Short name T143
Test name
Test status
Simulation time 118202891 ps
CPU time 1.12 seconds
Started May 07 03:17:11 PM PDT 24
Finished May 07 03:17:14 PM PDT 24
Peak memory 216092 kb
Host smart-ad29e7cd-fffc-450d-bba0-d605330e2749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877403044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.877403044
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3368098021
Short name T303
Test name
Test status
Simulation time 21046198 ps
CPU time 0.81 seconds
Started May 07 03:17:12 PM PDT 24
Finished May 07 03:17:14 PM PDT 24
Peak memory 206772 kb
Host smart-42ba39c1-c781-4a00-83d0-10993b487fc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368098021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3368098021
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.170352325
Short name T508
Test name
Test status
Simulation time 27038884 ps
CPU time 0.8 seconds
Started May 07 03:17:15 PM PDT 24
Finished May 07 03:17:18 PM PDT 24
Peak memory 216556 kb
Host smart-234b8e92-2009-4b99-aa46-233fde6c8d43
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170352325 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.170352325
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.870727518
Short name T586
Test name
Test status
Simulation time 33358654 ps
CPU time 1.06 seconds
Started May 07 03:17:11 PM PDT 24
Finished May 07 03:17:14 PM PDT 24
Peak memory 218524 kb
Host smart-76b76a3e-476b-4480-9310-7b9cce8ca7d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870727518 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.870727518
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.1467025986
Short name T819
Test name
Test status
Simulation time 28552467 ps
CPU time 1.21 seconds
Started May 07 03:17:12 PM PDT 24
Finished May 07 03:17:15 PM PDT 24
Peak memory 220048 kb
Host smart-0fa75695-b1a3-4079-944a-260845bf358c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467025986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1467025986
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.806961272
Short name T466
Test name
Test status
Simulation time 76550815 ps
CPU time 1.31 seconds
Started May 07 03:17:12 PM PDT 24
Finished May 07 03:17:15 PM PDT 24
Peak memory 219828 kb
Host smart-d774e55a-b390-499c-aa65-7b456a276657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806961272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.806961272
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2111909146
Short name T828
Test name
Test status
Simulation time 22589933 ps
CPU time 1.27 seconds
Started May 07 03:17:10 PM PDT 24
Finished May 07 03:17:12 PM PDT 24
Peak memory 224544 kb
Host smart-945a9577-61a3-4fc4-a742-0ea57c1b5b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111909146 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2111909146
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.251722691
Short name T332
Test name
Test status
Simulation time 39586008 ps
CPU time 0.93 seconds
Started May 07 03:17:11 PM PDT 24
Finished May 07 03:17:14 PM PDT 24
Peak memory 215568 kb
Host smart-38bf478f-3e12-4e93-acfd-23df23a49d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251722691 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.251722691
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.342019359
Short name T671
Test name
Test status
Simulation time 142277189 ps
CPU time 2 seconds
Started May 07 03:17:10 PM PDT 24
Finished May 07 03:17:13 PM PDT 24
Peak memory 215688 kb
Host smart-ed3096c9-a06b-4669-ab7b-900de28245f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342019359 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.342019359
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1523831089
Short name T527
Test name
Test status
Simulation time 53170866659 ps
CPU time 1400.53 seconds
Started May 07 03:17:10 PM PDT 24
Finished May 07 03:40:31 PM PDT 24
Peak memory 223800 kb
Host smart-92d2abf8-37f9-4b8d-86a7-e05bb9188591
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523831089 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1523831089
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1161192557
Short name T192
Test name
Test status
Simulation time 31753543 ps
CPU time 1.32 seconds
Started May 07 03:17:15 PM PDT 24
Finished May 07 03:17:17 PM PDT 24
Peak memory 216076 kb
Host smart-2cea596c-03e5-476a-b5f9-d9a9493013f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161192557 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1161192557
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.755316247
Short name T538
Test name
Test status
Simulation time 22780613 ps
CPU time 0.87 seconds
Started May 07 03:17:19 PM PDT 24
Finished May 07 03:17:21 PM PDT 24
Peak memory 215184 kb
Host smart-6d142c4d-39f2-42af-80c4-f3fc6576f68b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755316247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.755316247
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1966347014
Short name T49
Test name
Test status
Simulation time 54746028 ps
CPU time 0.85 seconds
Started May 07 03:17:18 PM PDT 24
Finished May 07 03:17:20 PM PDT 24
Peak memory 216448 kb
Host smart-5acb3611-cb86-42ab-a23b-592c545c2072
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966347014 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1966347014
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_err.1289328520
Short name T510
Test name
Test status
Simulation time 20448905 ps
CPU time 1.03 seconds
Started May 07 03:17:16 PM PDT 24
Finished May 07 03:17:19 PM PDT 24
Peak memory 219052 kb
Host smart-7e54f15d-30f0-4984-b9fd-58ae7eeeaf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289328520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1289328520
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.165390327
Short name T352
Test name
Test status
Simulation time 37740900 ps
CPU time 1.54 seconds
Started May 07 03:17:13 PM PDT 24
Finished May 07 03:17:16 PM PDT 24
Peak memory 219896 kb
Host smart-0af56b96-96de-4e8e-9028-4810711810b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165390327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.165390327
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3138461446
Short name T156
Test name
Test status
Simulation time 19574216 ps
CPU time 1.09 seconds
Started May 07 03:17:16 PM PDT 24
Finished May 07 03:17:19 PM PDT 24
Peak memory 216280 kb
Host smart-5d6dc739-0867-492e-b2d5-1a8922cdb5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138461446 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3138461446
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1345264211
Short name T427
Test name
Test status
Simulation time 29437006 ps
CPU time 0.96 seconds
Started May 07 03:17:12 PM PDT 24
Finished May 07 03:17:15 PM PDT 24
Peak memory 215596 kb
Host smart-a5359904-acd7-48de-9c71-07d6aaa2b61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345264211 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1345264211
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1145677715
Short name T55
Test name
Test status
Simulation time 1060750139 ps
CPU time 2.74 seconds
Started May 07 03:17:16 PM PDT 24
Finished May 07 03:17:20 PM PDT 24
Peak memory 217336 kb
Host smart-703f8fb8-4a93-4154-bce0-5f268a30b48f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145677715 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1145677715
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1931513304
Short name T42
Test name
Test status
Simulation time 51497860420 ps
CPU time 1201.94 seconds
Started May 07 03:17:19 PM PDT 24
Finished May 07 03:37:22 PM PDT 24
Peak memory 221268 kb
Host smart-5b0c46e8-7b92-4e0a-a442-21ae4b92ef51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931513304 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1931513304
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert_test.2602025555
Short name T772
Test name
Test status
Simulation time 15356087 ps
CPU time 0.91 seconds
Started May 07 03:17:29 PM PDT 24
Finished May 07 03:17:33 PM PDT 24
Peak memory 215200 kb
Host smart-b3bf9cdd-d4e0-416a-a61d-856c19bba691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602025555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2602025555
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3205275527
Short name T129
Test name
Test status
Simulation time 13799076 ps
CPU time 0.91 seconds
Started May 07 03:17:15 PM PDT 24
Finished May 07 03:17:18 PM PDT 24
Peak memory 215988 kb
Host smart-14a2851f-256d-48f2-bb5a-21a90c35de10
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205275527 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3205275527
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.718048933
Short name T492
Test name
Test status
Simulation time 33991055 ps
CPU time 1.12 seconds
Started May 07 03:17:16 PM PDT 24
Finished May 07 03:17:18 PM PDT 24
Peak memory 217228 kb
Host smart-f9df179f-ffe2-4fa5-9403-1153e8edda8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718048933 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_di
sable_auto_req_mode.718048933
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2656622888
Short name T112
Test name
Test status
Simulation time 36951773 ps
CPU time 1.18 seconds
Started May 07 03:17:18 PM PDT 24
Finished May 07 03:17:21 PM PDT 24
Peak memory 229928 kb
Host smart-16cbae53-5ce1-41f6-be6a-428e2666ef33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656622888 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2656622888
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2468903436
Short name T304
Test name
Test status
Simulation time 50119418 ps
CPU time 1.65 seconds
Started May 07 03:17:20 PM PDT 24
Finished May 07 03:17:23 PM PDT 24
Peak memory 218656 kb
Host smart-b4983b70-725a-4b40-bd48-0ed0778cc32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468903436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2468903436
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2444716477
Short name T650
Test name
Test status
Simulation time 65643880 ps
CPU time 0.86 seconds
Started May 07 03:17:15 PM PDT 24
Finished May 07 03:17:18 PM PDT 24
Peak memory 215812 kb
Host smart-961c3ba0-8104-4234-9020-8cb4e492b3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444716477 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2444716477
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2456459939
Short name T500
Test name
Test status
Simulation time 23086871 ps
CPU time 0.9 seconds
Started May 07 03:17:17 PM PDT 24
Finished May 07 03:17:19 PM PDT 24
Peak memory 215656 kb
Host smart-306673c1-90f0-4abe-a939-f9bb22200206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456459939 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2456459939
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1497147530
Short name T217
Test name
Test status
Simulation time 91233954 ps
CPU time 2.21 seconds
Started May 07 03:17:16 PM PDT 24
Finished May 07 03:17:20 PM PDT 24
Peak memory 215632 kb
Host smart-36771c70-c3c4-48f0-b9c7-014d291a7e57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497147530 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1497147530
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1442176701
Short name T788
Test name
Test status
Simulation time 23130503660 ps
CPU time 301.22 seconds
Started May 07 03:17:19 PM PDT 24
Finished May 07 03:22:22 PM PDT 24
Peak memory 217160 kb
Host smart-ca36c23b-5d5d-42bc-aa62-c8ef7e0732b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442176701 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1442176701
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.409618276
Short name T190
Test name
Test status
Simulation time 94557772 ps
CPU time 1.26 seconds
Started May 07 03:17:21 PM PDT 24
Finished May 07 03:17:24 PM PDT 24
Peak memory 216072 kb
Host smart-a6982160-9b02-4b4d-84c6-21714166c60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409618276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.409618276
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2892799066
Short name T315
Test name
Test status
Simulation time 31678680 ps
CPU time 0.87 seconds
Started May 07 03:17:22 PM PDT 24
Finished May 07 03:17:24 PM PDT 24
Peak memory 207324 kb
Host smart-0f7c1fbd-1baf-4726-8123-2a36cd71f6fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892799066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2892799066
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1804901727
Short name T718
Test name
Test status
Simulation time 27976436 ps
CPU time 0.84 seconds
Started May 07 03:17:22 PM PDT 24
Finished May 07 03:17:24 PM PDT 24
Peak memory 216596 kb
Host smart-c11e30f8-9f36-411c-9a7b-4beadd376396
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804901727 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1804901727
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.653944033
Short name T453
Test name
Test status
Simulation time 26033339 ps
CPU time 1.15 seconds
Started May 07 03:17:22 PM PDT 24
Finished May 07 03:17:24 PM PDT 24
Peak memory 218616 kb
Host smart-c6c41bae-1565-4623-9b7c-963aefc4ff96
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653944033 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.653944033
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.735106465
Short name T132
Test name
Test status
Simulation time 20767750 ps
CPU time 0.99 seconds
Started May 07 03:17:21 PM PDT 24
Finished May 07 03:17:23 PM PDT 24
Peak memory 224456 kb
Host smart-5e60609e-1322-4488-bb75-d9c3c5db4605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735106465 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.735106465
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2135047741
Short name T48
Test name
Test status
Simulation time 102512859 ps
CPU time 2.15 seconds
Started May 07 03:17:25 PM PDT 24
Finished May 07 03:17:28 PM PDT 24
Peak memory 218880 kb
Host smart-9c1f82ab-382b-48bd-baa3-9d76c440a8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135047741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2135047741
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2706337633
Short name T39
Test name
Test status
Simulation time 58647079 ps
CPU time 0.84 seconds
Started May 07 03:17:28 PM PDT 24
Finished May 07 03:17:32 PM PDT 24
Peak memory 216100 kb
Host smart-8f502d28-f54f-45f2-980b-0a63bb2cd722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706337633 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2706337633
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.216478588
Short name T769
Test name
Test status
Simulation time 44558348 ps
CPU time 0.87 seconds
Started May 07 03:17:27 PM PDT 24
Finished May 07 03:17:30 PM PDT 24
Peak memory 215644 kb
Host smart-e4ce9708-783e-4745-9af6-28f7d8483e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216478588 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.216478588
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.643636995
Short name T408
Test name
Test status
Simulation time 306232002 ps
CPU time 5.82 seconds
Started May 07 03:17:21 PM PDT 24
Finished May 07 03:17:28 PM PDT 24
Peak memory 218492 kb
Host smart-eb8788bf-9ef5-47ba-bae4-ff777a73e66d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643636995 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.643636995
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.4024848490
Short name T452
Test name
Test status
Simulation time 86254441027 ps
CPU time 546.69 seconds
Started May 07 03:17:24 PM PDT 24
Finished May 07 03:26:32 PM PDT 24
Peak memory 220920 kb
Host smart-313eb4f5-da8f-462d-82f3-215dc504bab3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024848490 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.4024848490
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2547760272
Short name T268
Test name
Test status
Simulation time 39863907 ps
CPU time 1.18 seconds
Started May 07 03:17:22 PM PDT 24
Finished May 07 03:17:25 PM PDT 24
Peak memory 216080 kb
Host smart-a0c1114c-f711-4e59-a335-ef32243e3df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547760272 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2547760272
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.866513459
Short name T396
Test name
Test status
Simulation time 48361825 ps
CPU time 1.5 seconds
Started May 07 03:17:22 PM PDT 24
Finished May 07 03:17:24 PM PDT 24
Peak memory 207092 kb
Host smart-a9db36f2-d6e3-4fd5-bb7a-92193ac2cc7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866513459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.866513459
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.222902054
Short name T353
Test name
Test status
Simulation time 128141250 ps
CPU time 0.89 seconds
Started May 07 03:17:23 PM PDT 24
Finished May 07 03:17:25 PM PDT 24
Peak memory 216284 kb
Host smart-46599387-1f0f-4003-9d61-d74bcde3dc27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222902054 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.222902054
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3854729960
Short name T370
Test name
Test status
Simulation time 34707044 ps
CPU time 1.12 seconds
Started May 07 03:17:20 PM PDT 24
Finished May 07 03:17:22 PM PDT 24
Peak memory 219680 kb
Host smart-3d9658c3-b6ee-4764-9dd4-2ac9ba185122
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854729960 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3854729960
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3473151443
Short name T550
Test name
Test status
Simulation time 18564782 ps
CPU time 1.14 seconds
Started May 07 03:17:22 PM PDT 24
Finished May 07 03:17:24 PM PDT 24
Peak memory 224468 kb
Host smart-a90a2abb-3fc7-4531-8455-133316ed6e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473151443 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3473151443
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2667884171
Short name T765
Test name
Test status
Simulation time 38310476 ps
CPU time 1.82 seconds
Started May 07 03:17:28 PM PDT 24
Finished May 07 03:17:32 PM PDT 24
Peak memory 218684 kb
Host smart-8c572084-27df-4444-a2d7-5a4e4e763d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667884171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2667884171
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1989101599
Short name T171
Test name
Test status
Simulation time 33374962 ps
CPU time 0.81 seconds
Started May 07 03:17:27 PM PDT 24
Finished May 07 03:17:31 PM PDT 24
Peak memory 216108 kb
Host smart-c2cf54c3-70f7-43f6-b1ce-1cabb455cadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989101599 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1989101599
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1958135441
Short name T464
Test name
Test status
Simulation time 27673807 ps
CPU time 1.06 seconds
Started May 07 03:17:23 PM PDT 24
Finished May 07 03:17:25 PM PDT 24
Peak memory 215616 kb
Host smart-3e1f7adb-a397-4d8b-b5e0-c31d0027cd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958135441 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1958135441
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3516397340
Short name T618
Test name
Test status
Simulation time 2042537120 ps
CPU time 4.19 seconds
Started May 07 03:17:20 PM PDT 24
Finished May 07 03:17:25 PM PDT 24
Peak memory 217428 kb
Host smart-cec79e7c-d9c2-4317-90d7-b4e5ebb6c2b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516397340 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3516397340
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2676082851
Short name T659
Test name
Test status
Simulation time 72338475500 ps
CPU time 1469.94 seconds
Started May 07 03:17:23 PM PDT 24
Finished May 07 03:41:55 PM PDT 24
Peak memory 223456 kb
Host smart-14be6ad6-d2d4-423f-bef5-7b76cae2f464
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676082851 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2676082851
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.94392527
Short name T551
Test name
Test status
Simulation time 67676689 ps
CPU time 1.26 seconds
Started May 07 03:17:22 PM PDT 24
Finished May 07 03:17:24 PM PDT 24
Peak memory 216068 kb
Host smart-0f9dd0f5-bd75-4771-a08f-e85a45fa8e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94392527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.94392527
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3182653631
Short name T317
Test name
Test status
Simulation time 47309631 ps
CPU time 0.85 seconds
Started May 07 03:17:23 PM PDT 24
Finished May 07 03:17:25 PM PDT 24
Peak memory 206832 kb
Host smart-b568265b-41e7-441d-98ff-d811460b33fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182653631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3182653631
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1447493259
Short name T184
Test name
Test status
Simulation time 13703093 ps
CPU time 0.9 seconds
Started May 07 03:17:26 PM PDT 24
Finished May 07 03:17:27 PM PDT 24
Peak memory 216832 kb
Host smart-ef42cb9a-6f0a-4f29-84d2-24791282d1f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447493259 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1447493259
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3311736747
Short name T530
Test name
Test status
Simulation time 99751339 ps
CPU time 1.14 seconds
Started May 07 03:17:24 PM PDT 24
Finished May 07 03:17:26 PM PDT 24
Peak memory 216748 kb
Host smart-fb47a036-ecba-4cb1-80d1-b7f369ce3e91
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311736747 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3311736747
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1571430475
Short name T754
Test name
Test status
Simulation time 45457679 ps
CPU time 1.11 seconds
Started May 07 03:17:25 PM PDT 24
Finished May 07 03:17:27 PM PDT 24
Peak memory 216012 kb
Host smart-82e5eba6-99c8-4a73-b656-4d269ad605b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571430475 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1571430475
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2659054294
Short name T715
Test name
Test status
Simulation time 44741197 ps
CPU time 1.49 seconds
Started May 07 03:17:23 PM PDT 24
Finished May 07 03:17:26 PM PDT 24
Peak memory 219488 kb
Host smart-172f2c60-627c-4e4f-a5f6-097cabc324e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659054294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2659054294
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2231451503
Short name T404
Test name
Test status
Simulation time 21935557 ps
CPU time 1.19 seconds
Started May 07 03:17:24 PM PDT 24
Finished May 07 03:17:26 PM PDT 24
Peak memory 224444 kb
Host smart-9d08db5a-05b0-4087-9ea3-a041af4d3d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231451503 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2231451503
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3597275543
Short name T642
Test name
Test status
Simulation time 43971320 ps
CPU time 0.88 seconds
Started May 07 03:17:29 PM PDT 24
Finished May 07 03:17:33 PM PDT 24
Peak memory 215644 kb
Host smart-47b14dcd-c605-4fda-aee9-48c57a3624bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597275543 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3597275543
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3388667501
Short name T756
Test name
Test status
Simulation time 144052069 ps
CPU time 1.46 seconds
Started May 07 03:17:19 PM PDT 24
Finished May 07 03:17:22 PM PDT 24
Peak memory 217244 kb
Host smart-5d0513eb-2c07-4ab2-b51d-c34ab25977c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388667501 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3388667501
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1063310773
Short name T476
Test name
Test status
Simulation time 227311815566 ps
CPU time 1406.97 seconds
Started May 07 03:17:24 PM PDT 24
Finished May 07 03:40:52 PM PDT 24
Peak memory 226544 kb
Host smart-847aa9dc-53c4-40d3-bfb7-ac7db9e945f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063310773 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1063310773
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.61339795
Short name T74
Test name
Test status
Simulation time 165135128 ps
CPU time 1.23 seconds
Started May 07 03:17:28 PM PDT 24
Finished May 07 03:17:33 PM PDT 24
Peak memory 216056 kb
Host smart-f5123e36-1628-40bb-b5c6-24dbda20cb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61339795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.61339795
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1359420148
Short name T354
Test name
Test status
Simulation time 100028152 ps
CPU time 1.11 seconds
Started May 07 03:17:27 PM PDT 24
Finished May 07 03:17:31 PM PDT 24
Peak memory 207104 kb
Host smart-cfa35b8b-3603-47ac-9a65-c833e7b671f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359420148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1359420148
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1523603902
Short name T700
Test name
Test status
Simulation time 12145474 ps
CPU time 0.87 seconds
Started May 07 03:17:27 PM PDT 24
Finished May 07 03:17:30 PM PDT 24
Peak memory 216468 kb
Host smart-c6988c92-66f9-44d0-a35c-66b421cbbd13
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523603902 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1523603902
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3683354774
Short name T473
Test name
Test status
Simulation time 36039712 ps
CPU time 1.29 seconds
Started May 07 03:17:27 PM PDT 24
Finished May 07 03:17:30 PM PDT 24
Peak memory 219568 kb
Host smart-ef58cea0-d7a1-4f31-bb6b-28f645938a86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683354774 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3683354774
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3668737267
Short name T781
Test name
Test status
Simulation time 23718009 ps
CPU time 0.97 seconds
Started May 07 03:17:28 PM PDT 24
Finished May 07 03:17:32 PM PDT 24
Peak memory 218936 kb
Host smart-33a85acc-4a89-4adc-85e0-37d493dc7edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668737267 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3668737267
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_intr.1908898431
Short name T101
Test name
Test status
Simulation time 26945520 ps
CPU time 0.98 seconds
Started May 07 03:17:29 PM PDT 24
Finished May 07 03:17:33 PM PDT 24
Peak memory 216244 kb
Host smart-5446d9bb-8878-4514-94dc-9721ddd216e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908898431 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1908898431
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.348799115
Short name T751
Test name
Test status
Simulation time 22575335 ps
CPU time 1.01 seconds
Started May 07 03:17:35 PM PDT 24
Finished May 07 03:17:37 PM PDT 24
Peak memory 215116 kb
Host smart-b6134c95-fbc3-48de-b4da-df5605338180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348799115 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.348799115
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.10395566
Short name T163
Test name
Test status
Simulation time 2119985708 ps
CPU time 5.8 seconds
Started May 07 03:17:27 PM PDT 24
Finished May 07 03:17:34 PM PDT 24
Peak memory 217068 kb
Host smart-3d110e38-d23b-4182-957c-f2edb54447a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10395566 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.10395566
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.367215350
Short name T198
Test name
Test status
Simulation time 209543879468 ps
CPU time 303.84 seconds
Started May 07 03:17:28 PM PDT 24
Finished May 07 03:22:35 PM PDT 24
Peak memory 224004 kb
Host smart-76ba7c0b-d0b7-4ea1-8df5-3c480c72a5df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367215350 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.367215350
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2099158802
Short name T168
Test name
Test status
Simulation time 28765346 ps
CPU time 1.27 seconds
Started May 07 03:17:27 PM PDT 24
Finished May 07 03:17:30 PM PDT 24
Peak memory 216056 kb
Host smart-398921b4-b6a1-42b5-8288-40d150edb208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099158802 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2099158802
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1146471360
Short name T556
Test name
Test status
Simulation time 17079771 ps
CPU time 0.93 seconds
Started May 07 03:17:29 PM PDT 24
Finished May 07 03:17:32 PM PDT 24
Peak memory 206960 kb
Host smart-2350e934-1fc9-4092-9131-adf0c1be92f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146471360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1146471360
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.4005314926
Short name T498
Test name
Test status
Simulation time 18201887 ps
CPU time 0.81 seconds
Started May 07 03:17:27 PM PDT 24
Finished May 07 03:17:29 PM PDT 24
Peak memory 216636 kb
Host smart-ec359406-f40d-4a39-b365-2640c23dd068
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005314926 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.4005314926
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2808374739
Short name T651
Test name
Test status
Simulation time 19432208 ps
CPU time 1.02 seconds
Started May 07 03:17:28 PM PDT 24
Finished May 07 03:17:32 PM PDT 24
Peak memory 218784 kb
Host smart-a25c5544-b801-472a-831b-493f35d8bad8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808374739 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2808374739
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2695255479
Short name T107
Test name
Test status
Simulation time 116335646 ps
CPU time 1.24 seconds
Started May 07 03:17:29 PM PDT 24
Finished May 07 03:17:33 PM PDT 24
Peak memory 230136 kb
Host smart-41d54dd9-868a-4c2c-b1e4-9b71f3c01b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695255479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2695255479
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1789667023
Short name T543
Test name
Test status
Simulation time 119846480 ps
CPU time 0.95 seconds
Started May 07 03:17:27 PM PDT 24
Finished May 07 03:17:31 PM PDT 24
Peak memory 217408 kb
Host smart-d41d9a14-5b74-4022-863e-aacf7282a689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789667023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1789667023
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1453261440
Short name T625
Test name
Test status
Simulation time 64003811 ps
CPU time 0.96 seconds
Started May 07 03:17:28 PM PDT 24
Finished May 07 03:17:32 PM PDT 24
Peak memory 224236 kb
Host smart-24745258-45ab-4bf8-a742-b29f2961a9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453261440 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1453261440
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2467724711
Short name T377
Test name
Test status
Simulation time 31727953 ps
CPU time 0.95 seconds
Started May 07 03:17:28 PM PDT 24
Finished May 07 03:17:31 PM PDT 24
Peak memory 215604 kb
Host smart-3dd6cd4c-16cd-4fa8-b699-0d5bab8aa35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467724711 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2467724711
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.160374347
Short name T521
Test name
Test status
Simulation time 375558365 ps
CPU time 4.07 seconds
Started May 07 03:17:28 PM PDT 24
Finished May 07 03:17:34 PM PDT 24
Peak memory 215644 kb
Host smart-83187bc5-269c-4176-bbcf-fdf957bdb36c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160374347 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.160374347
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.995738117
Short name T210
Test name
Test status
Simulation time 237276491934 ps
CPU time 935.06 seconds
Started May 07 03:17:28 PM PDT 24
Finished May 07 03:33:06 PM PDT 24
Peak memory 224004 kb
Host smart-507e21e3-dee9-40c8-a29d-4e99fc989749
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995738117 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.995738117
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.4118518664
Short name T555
Test name
Test status
Simulation time 80443940 ps
CPU time 1.13 seconds
Started May 07 03:16:29 PM PDT 24
Finished May 07 03:16:31 PM PDT 24
Peak memory 216080 kb
Host smart-b5e6f067-4ad7-4e87-a6d8-8e2f20a102fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118518664 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.4118518664
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2581085557
Short name T768
Test name
Test status
Simulation time 19793415 ps
CPU time 0.95 seconds
Started May 07 03:16:29 PM PDT 24
Finished May 07 03:16:32 PM PDT 24
Peak memory 206960 kb
Host smart-8823fb8d-6006-4943-8488-2bace4fc39fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581085557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2581085557
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.18642314
Short name T152
Test name
Test status
Simulation time 178105205 ps
CPU time 0.85 seconds
Started May 07 03:16:27 PM PDT 24
Finished May 07 03:16:29 PM PDT 24
Peak memory 216600 kb
Host smart-ca446b23-5738-4f26-8183-f87d063952e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18642314 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.18642314
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3470388778
Short name T589
Test name
Test status
Simulation time 178335204 ps
CPU time 1.01 seconds
Started May 07 03:16:26 PM PDT 24
Finished May 07 03:16:28 PM PDT 24
Peak memory 217096 kb
Host smart-4e170518-766b-47d2-9bdb-c85bbe560514
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470388778 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3470388778
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2117542760
Short name T517
Test name
Test status
Simulation time 20991941 ps
CPU time 1.05 seconds
Started May 07 03:16:28 PM PDT 24
Finished May 07 03:16:30 PM PDT 24
Peak memory 219092 kb
Host smart-4e77b205-957e-4ec8-8eb4-9c16ed57266c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117542760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2117542760
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.4192715391
Short name T292
Test name
Test status
Simulation time 43344472 ps
CPU time 1.64 seconds
Started May 07 03:16:26 PM PDT 24
Finished May 07 03:16:29 PM PDT 24
Peak memory 218628 kb
Host smart-2e943b57-bb0d-41e4-911b-2f335d6e2203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192715391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.4192715391
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2665211949
Short name T516
Test name
Test status
Simulation time 20992563 ps
CPU time 1.11 seconds
Started May 07 03:16:31 PM PDT 24
Finished May 07 03:16:33 PM PDT 24
Peak memory 216512 kb
Host smart-1f827263-96ed-4f77-9ce0-e4fe1dd3c04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665211949 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2665211949
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.3186836438
Short name T683
Test name
Test status
Simulation time 39637202 ps
CPU time 0.89 seconds
Started May 07 03:16:22 PM PDT 24
Finished May 07 03:16:24 PM PDT 24
Peak memory 207436 kb
Host smart-b3f2d072-cac3-4476-a53e-e601373f11cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186836438 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3186836438
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1687742330
Short name T19
Test name
Test status
Simulation time 912445188 ps
CPU time 4.25 seconds
Started May 07 03:16:31 PM PDT 24
Finished May 07 03:16:36 PM PDT 24
Peak memory 235748 kb
Host smart-dd7c1d9e-57fd-4dff-ab79-0e848b3fd8db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687742330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1687742330
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3918315586
Short name T430
Test name
Test status
Simulation time 24091415 ps
CPU time 0.95 seconds
Started May 07 03:16:21 PM PDT 24
Finished May 07 03:16:23 PM PDT 24
Peak memory 207436 kb
Host smart-a6d94cfe-993e-432a-8faa-a5aad98c0322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918315586 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3918315586
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2861681086
Short name T512
Test name
Test status
Simulation time 158584748 ps
CPU time 3.49 seconds
Started May 07 03:16:26 PM PDT 24
Finished May 07 03:16:30 PM PDT 24
Peak memory 215612 kb
Host smart-39f98ff0-0b77-432e-b99c-0794e1bc2fd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861681086 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2861681086
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2774932196
Short name T572
Test name
Test status
Simulation time 40742807563 ps
CPU time 902.59 seconds
Started May 07 03:16:32 PM PDT 24
Finished May 07 03:31:36 PM PDT 24
Peak memory 219412 kb
Host smart-4069b5e1-48e3-40f4-93b0-e93202c793de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774932196 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2774932196
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.534488133
Short name T104
Test name
Test status
Simulation time 71704832 ps
CPU time 1.22 seconds
Started May 07 03:17:35 PM PDT 24
Finished May 07 03:17:38 PM PDT 24
Peak memory 215568 kb
Host smart-53abfa1c-bd40-4a7d-bdd3-43de2f5c4482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534488133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.534488133
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3465102889
Short name T619
Test name
Test status
Simulation time 20893977 ps
CPU time 0.88 seconds
Started May 07 03:17:29 PM PDT 24
Finished May 07 03:17:33 PM PDT 24
Peak memory 206948 kb
Host smart-66c864d6-33cd-4163-891b-3f81015ca489
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465102889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3465102889
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.382902887
Short name T193
Test name
Test status
Simulation time 12606795 ps
CPU time 0.9 seconds
Started May 07 03:17:27 PM PDT 24
Finished May 07 03:17:29 PM PDT 24
Peak memory 216920 kb
Host smart-f6c64fc0-5981-47e7-8c02-bc57d27f2aba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382902887 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.382902887
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2855432760
Short name T110
Test name
Test status
Simulation time 76202869 ps
CPU time 1.1 seconds
Started May 07 03:17:28 PM PDT 24
Finished May 07 03:17:32 PM PDT 24
Peak memory 217348 kb
Host smart-c65c6bcf-af34-4dba-b0dd-645b0c2b45c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855432760 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2855432760
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2152135213
Short name T486
Test name
Test status
Simulation time 46143963 ps
CPU time 1.09 seconds
Started May 07 03:17:28 PM PDT 24
Finished May 07 03:17:32 PM PDT 24
Peak memory 224460 kb
Host smart-0cf56f54-b1c9-431d-a42b-7379f4d9972b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152135213 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2152135213
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.209404871
Short name T746
Test name
Test status
Simulation time 48168395 ps
CPU time 1.4 seconds
Started May 07 03:17:31 PM PDT 24
Finished May 07 03:17:34 PM PDT 24
Peak memory 220032 kb
Host smart-3422ba9d-f7b3-4577-b06b-fecca5aa180e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209404871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.209404871
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2984100695
Short name T157
Test name
Test status
Simulation time 19837287 ps
CPU time 1.11 seconds
Started May 07 03:17:31 PM PDT 24
Finished May 07 03:17:34 PM PDT 24
Peak memory 216440 kb
Host smart-744a12d2-8d39-47dd-9f91-b547b04ebe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984100695 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2984100695
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2641040537
Short name T462
Test name
Test status
Simulation time 48945842 ps
CPU time 0.92 seconds
Started May 07 03:17:28 PM PDT 24
Finished May 07 03:17:32 PM PDT 24
Peak memory 215628 kb
Host smart-43daba9b-1f10-4eed-bc4f-f87e9ddd01ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641040537 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2641040537
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2799470506
Short name T735
Test name
Test status
Simulation time 178090308 ps
CPU time 3.79 seconds
Started May 07 03:17:28 PM PDT 24
Finished May 07 03:17:35 PM PDT 24
Peak memory 220296 kb
Host smart-935bbb07-7c2a-4015-bbc8-6c753033d751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799470506 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2799470506
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1704085272
Short name T208
Test name
Test status
Simulation time 71874845140 ps
CPU time 402.48 seconds
Started May 07 03:17:28 PM PDT 24
Finished May 07 03:24:14 PM PDT 24
Peak memory 219196 kb
Host smart-c838e42d-5f1e-4c8e-bc1d-9a28a946bf6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704085272 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1704085272
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.4136863553
Short name T299
Test name
Test status
Simulation time 37201578 ps
CPU time 1.16 seconds
Started May 07 03:17:27 PM PDT 24
Finished May 07 03:17:29 PM PDT 24
Peak memory 216072 kb
Host smart-fa85b4ec-5b61-409e-9cf8-dca8401c51cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136863553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.4136863553
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3313240480
Short name T743
Test name
Test status
Simulation time 17852136 ps
CPU time 0.97 seconds
Started May 07 03:17:36 PM PDT 24
Finished May 07 03:17:40 PM PDT 24
Peak memory 215728 kb
Host smart-855439bd-1ccc-465b-8af8-da19598db276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313240480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3313240480
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3999168834
Short name T837
Test name
Test status
Simulation time 13541320 ps
CPU time 0.91 seconds
Started May 07 03:17:27 PM PDT 24
Finished May 07 03:17:30 PM PDT 24
Peak memory 216804 kb
Host smart-0f7b7cc8-a8ac-40e7-8915-3ff3b7fedaa8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999168834 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3999168834
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.4108469209
Short name T44
Test name
Test status
Simulation time 109020665 ps
CPU time 1.14 seconds
Started May 07 03:17:36 PM PDT 24
Finished May 07 03:17:40 PM PDT 24
Peak memory 217112 kb
Host smart-bb27c72b-68fb-40a4-990e-06613edc44e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108469209 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.4108469209
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.1240874832
Short name T534
Test name
Test status
Simulation time 33655633 ps
CPU time 1.09 seconds
Started May 07 03:17:27 PM PDT 24
Finished May 07 03:17:29 PM PDT 24
Peak memory 224252 kb
Host smart-6ec4bfd0-d50b-4a15-8913-4a7cdf439301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240874832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1240874832
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.297351257
Short name T485
Test name
Test status
Simulation time 51056431 ps
CPU time 1.98 seconds
Started May 07 03:17:29 PM PDT 24
Finished May 07 03:17:34 PM PDT 24
Peak memory 218476 kb
Host smart-ae7ca7af-68aa-4dc3-b0e4-afce745ece3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297351257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.297351257
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.526274143
Short name T697
Test name
Test status
Simulation time 29548869 ps
CPU time 0.94 seconds
Started May 07 03:17:29 PM PDT 24
Finished May 07 03:17:33 PM PDT 24
Peak memory 215872 kb
Host smart-9d7c5a09-0f51-4b36-bed9-c831e7f5d38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526274143 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.526274143
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3029223603
Short name T373
Test name
Test status
Simulation time 15906536 ps
CPU time 1.08 seconds
Started May 07 03:17:32 PM PDT 24
Finished May 07 03:17:34 PM PDT 24
Peak memory 215600 kb
Host smart-7452c1bb-4049-4592-87a3-e601c320e4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029223603 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3029223603
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.258320158
Short name T381
Test name
Test status
Simulation time 10040726087 ps
CPU time 133.66 seconds
Started May 07 03:17:29 PM PDT 24
Finished May 07 03:19:45 PM PDT 24
Peak memory 218496 kb
Host smart-04fd5696-95dd-4078-8450-0b4bd6c826cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258320158 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.258320158
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3645540246
Short name T817
Test name
Test status
Simulation time 49071960 ps
CPU time 1.23 seconds
Started May 07 03:17:36 PM PDT 24
Finished May 07 03:17:39 PM PDT 24
Peak memory 216056 kb
Host smart-c1ef9c21-ef04-4bac-8d91-33b84804088e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645540246 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3645540246
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.4284911030
Short name T469
Test name
Test status
Simulation time 22820092 ps
CPU time 0.97 seconds
Started May 07 03:17:39 PM PDT 24
Finished May 07 03:17:43 PM PDT 24
Peak memory 215224 kb
Host smart-9c6073e3-e9fa-4e8d-9004-8792eb517774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284911030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.4284911030
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1583575189
Short name T801
Test name
Test status
Simulation time 17981108 ps
CPU time 0.83 seconds
Started May 07 03:17:37 PM PDT 24
Finished May 07 03:17:41 PM PDT 24
Peak memory 216612 kb
Host smart-a56a2405-f8f8-45b5-b285-0964093bf916
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583575189 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1583575189
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_err.4144184948
Short name T669
Test name
Test status
Simulation time 18376042 ps
CPU time 1 seconds
Started May 07 03:17:36 PM PDT 24
Finished May 07 03:17:39 PM PDT 24
Peak memory 218496 kb
Host smart-e1d1d0ab-d636-4d28-8217-d6b1bd1869a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144184948 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.4144184948
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.4096431229
Short name T576
Test name
Test status
Simulation time 63523559 ps
CPU time 1.1 seconds
Started May 07 03:17:34 PM PDT 24
Finished May 07 03:17:37 PM PDT 24
Peak memory 218680 kb
Host smart-c71f51b1-c463-4906-a05f-fef254141a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096431229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.4096431229
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.134699631
Short name T35
Test name
Test status
Simulation time 44375992 ps
CPU time 0.9 seconds
Started May 07 03:17:39 PM PDT 24
Finished May 07 03:17:43 PM PDT 24
Peak memory 216140 kb
Host smart-14c603d7-3ea4-4935-ab71-070fb4b02a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134699631 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.134699631
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2914648752
Short name T435
Test name
Test status
Simulation time 107450061 ps
CPU time 0.89 seconds
Started May 07 03:17:37 PM PDT 24
Finished May 07 03:17:40 PM PDT 24
Peak memory 215676 kb
Host smart-5f46ab38-ffc3-4835-956d-ab5d7f025be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914648752 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2914648752
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1488500756
Short name T712
Test name
Test status
Simulation time 97342620 ps
CPU time 1.57 seconds
Started May 07 03:17:36 PM PDT 24
Finished May 07 03:17:39 PM PDT 24
Peak memory 215628 kb
Host smart-23380aab-fd76-43ad-95b0-fb5278f8c7e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488500756 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1488500756
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_alert.3276970700
Short name T189
Test name
Test status
Simulation time 26604506 ps
CPU time 1.21 seconds
Started May 07 03:17:40 PM PDT 24
Finished May 07 03:17:45 PM PDT 24
Peak memory 216072 kb
Host smart-36220a26-697b-4817-895f-150763fcd15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276970700 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3276970700
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.746701602
Short name T79
Test name
Test status
Simulation time 126411542 ps
CPU time 0.84 seconds
Started May 07 03:17:38 PM PDT 24
Finished May 07 03:17:42 PM PDT 24
Peak memory 206672 kb
Host smart-724ee350-89a1-43de-9faf-6cf9f908ff24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746701602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.746701602
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2132862992
Short name T779
Test name
Test status
Simulation time 11572682 ps
CPU time 0.92 seconds
Started May 07 03:17:34 PM PDT 24
Finished May 07 03:17:36 PM PDT 24
Peak memory 207676 kb
Host smart-5be9fc79-e69e-4799-9956-44ec3d75aa75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132862992 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2132862992
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.942157391
Short name T215
Test name
Test status
Simulation time 122275329 ps
CPU time 1.12 seconds
Started May 07 03:17:38 PM PDT 24
Finished May 07 03:17:42 PM PDT 24
Peak memory 219688 kb
Host smart-6b42ed4c-4ba2-48d9-a86d-7da2dae568b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942157391 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.942157391
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2895335136
Short name T145
Test name
Test status
Simulation time 18560982 ps
CPU time 1.16 seconds
Started May 07 03:17:34 PM PDT 24
Finished May 07 03:17:37 PM PDT 24
Peak memory 218788 kb
Host smart-0f9863d9-6663-45f0-88ad-99ced959ced6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895335136 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2895335136
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1175471309
Short name T658
Test name
Test status
Simulation time 25804521 ps
CPU time 1.16 seconds
Started May 07 03:17:36 PM PDT 24
Finished May 07 03:17:39 PM PDT 24
Peak memory 217284 kb
Host smart-38cf6264-530a-46bc-ab33-f8265f0c2594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175471309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1175471309
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1913088714
Short name T16
Test name
Test status
Simulation time 26974025 ps
CPU time 1.12 seconds
Started May 07 03:17:39 PM PDT 24
Finished May 07 03:17:43 PM PDT 24
Peak memory 224452 kb
Host smart-26cbcfa1-3582-46d6-b50f-878f62106571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913088714 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1913088714
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2382411396
Short name T539
Test name
Test status
Simulation time 16577884 ps
CPU time 0.97 seconds
Started May 07 03:17:35 PM PDT 24
Finished May 07 03:17:38 PM PDT 24
Peak memory 215656 kb
Host smart-6cdd8622-56e6-4dfd-8ac2-488e56e3fb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382411396 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2382411396
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.790677684
Short name T614
Test name
Test status
Simulation time 908234257 ps
CPU time 5.29 seconds
Started May 07 03:17:36 PM PDT 24
Finished May 07 03:17:43 PM PDT 24
Peak memory 217400 kb
Host smart-d2285bab-7ae6-4a76-9f66-0a7ce9035c94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790677684 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.790677684
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_alert.3214451527
Short name T170
Test name
Test status
Simulation time 103252258 ps
CPU time 1.23 seconds
Started May 07 03:17:36 PM PDT 24
Finished May 07 03:17:40 PM PDT 24
Peak memory 216084 kb
Host smart-82d75933-023b-4447-a258-1afc5762e408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214451527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3214451527
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2520035201
Short name T764
Test name
Test status
Simulation time 59001332 ps
CPU time 0.82 seconds
Started May 07 03:17:37 PM PDT 24
Finished May 07 03:17:41 PM PDT 24
Peak memory 206760 kb
Host smart-8576fa16-8aa3-4fd0-acbf-14e102711350
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520035201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2520035201
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.159910518
Short name T176
Test name
Test status
Simulation time 20024189 ps
CPU time 0.88 seconds
Started May 07 03:17:36 PM PDT 24
Finished May 07 03:17:38 PM PDT 24
Peak memory 216956 kb
Host smart-49487e8b-bcf5-48a3-a59d-dec9f8896d54
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159910518 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.159910518
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1199838488
Short name T681
Test name
Test status
Simulation time 86092669 ps
CPU time 1.05 seconds
Started May 07 03:17:36 PM PDT 24
Finished May 07 03:17:39 PM PDT 24
Peak memory 219960 kb
Host smart-2fe47bc0-fbd7-4e77-bfd8-81ad605ceb2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199838488 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1199838488
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1657082234
Short name T148
Test name
Test status
Simulation time 18420671 ps
CPU time 1.2 seconds
Started May 07 03:17:35 PM PDT 24
Finished May 07 03:17:38 PM PDT 24
Peak memory 224432 kb
Host smart-a437cc8e-ba22-4e26-ba3e-b78de9c09976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657082234 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1657082234
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2883586786
Short name T286
Test name
Test status
Simulation time 71596205 ps
CPU time 1.09 seconds
Started May 07 03:17:35 PM PDT 24
Finished May 07 03:17:38 PM PDT 24
Peak memory 217296 kb
Host smart-366e07ce-f747-4cb1-b586-b30a3e726c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883586786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2883586786
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1982903933
Short name T344
Test name
Test status
Simulation time 70999346 ps
CPU time 0.92 seconds
Started May 07 03:17:37 PM PDT 24
Finished May 07 03:17:40 PM PDT 24
Peak memory 215632 kb
Host smart-0508bc05-7828-4b24-9cea-4fcec230cd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982903933 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1982903933
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1578303668
Short name T583
Test name
Test status
Simulation time 15876567 ps
CPU time 0.94 seconds
Started May 07 03:17:38 PM PDT 24
Finished May 07 03:17:42 PM PDT 24
Peak memory 215628 kb
Host smart-55158529-9073-44dd-9384-a63a66fe4539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578303668 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1578303668
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2057590793
Short name T62
Test name
Test status
Simulation time 56995242 ps
CPU time 1.71 seconds
Started May 07 03:17:36 PM PDT 24
Finished May 07 03:17:40 PM PDT 24
Peak memory 215636 kb
Host smart-11c8b975-3424-4746-b84e-7fdbd77abf14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057590793 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2057590793
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.957993093
Short name T209
Test name
Test status
Simulation time 203751395125 ps
CPU time 1148.86 seconds
Started May 07 03:17:34 PM PDT 24
Finished May 07 03:36:44 PM PDT 24
Peak memory 222364 kb
Host smart-ea419e07-5237-400c-8cc8-61a369dc061d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957993093 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.957993093
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3261315175
Short name T780
Test name
Test status
Simulation time 46895927 ps
CPU time 1.24 seconds
Started May 07 03:17:35 PM PDT 24
Finished May 07 03:17:39 PM PDT 24
Peak memory 216064 kb
Host smart-58a6bc10-8692-4659-ac3c-1e9a091cbfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261315175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3261315175
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2344615878
Short name T790
Test name
Test status
Simulation time 19286479 ps
CPU time 1.01 seconds
Started May 07 03:17:36 PM PDT 24
Finished May 07 03:17:39 PM PDT 24
Peak memory 207152 kb
Host smart-8fd16272-fa6c-411a-ad0d-ff9d43790753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344615878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2344615878
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2001957479
Short name T703
Test name
Test status
Simulation time 15217682 ps
CPU time 0.92 seconds
Started May 07 03:17:34 PM PDT 24
Finished May 07 03:17:37 PM PDT 24
Peak memory 215976 kb
Host smart-da98a816-bb3b-420e-87d9-b277d2799c77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001957479 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2001957479
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_err.2707028319
Short name T829
Test name
Test status
Simulation time 29214419 ps
CPU time 1.07 seconds
Started May 07 03:17:34 PM PDT 24
Finished May 07 03:17:36 PM PDT 24
Peak memory 219156 kb
Host smart-5751db4d-23d0-4ebf-a1cb-c01ea8761ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707028319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2707028319
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3765131910
Short name T43
Test name
Test status
Simulation time 53862489 ps
CPU time 1.83 seconds
Started May 07 03:17:40 PM PDT 24
Finished May 07 03:17:45 PM PDT 24
Peak memory 218704 kb
Host smart-fb674051-f0fc-4361-bd20-de1998e902a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765131910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3765131910
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_smoke.1432013873
Short name T219
Test name
Test status
Simulation time 17319293 ps
CPU time 1.01 seconds
Started May 07 03:17:38 PM PDT 24
Finished May 07 03:17:42 PM PDT 24
Peak memory 215608 kb
Host smart-0979b637-c060-44ed-a792-164affa85998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432013873 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1432013873
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3826640679
Short name T467
Test name
Test status
Simulation time 258627595 ps
CPU time 1.99 seconds
Started May 07 03:17:38 PM PDT 24
Finished May 07 03:17:43 PM PDT 24
Peak memory 215684 kb
Host smart-8cb916fd-001c-4eba-b472-183765af30d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826640679 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3826640679
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.308807998
Short name T767
Test name
Test status
Simulation time 222737275669 ps
CPU time 1269.9 seconds
Started May 07 03:17:37 PM PDT 24
Finished May 07 03:38:50 PM PDT 24
Peak memory 222644 kb
Host smart-9faa3418-bb2e-4f6c-8d66-5ca8e215f465
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308807998 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.308807998
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert_test.534724770
Short name T314
Test name
Test status
Simulation time 26855616 ps
CPU time 0.9 seconds
Started May 07 03:17:40 PM PDT 24
Finished May 07 03:17:44 PM PDT 24
Peak memory 215208 kb
Host smart-084fb717-7188-4490-9c41-ebf759511fc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534724770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.534724770
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1720779809
Short name T130
Test name
Test status
Simulation time 13139214 ps
CPU time 0.85 seconds
Started May 07 03:17:35 PM PDT 24
Finished May 07 03:17:38 PM PDT 24
Peak memory 216020 kb
Host smart-9122e404-3940-484f-b5b9-52a73657bd1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720779809 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1720779809
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1373218444
Short name T113
Test name
Test status
Simulation time 33687397 ps
CPU time 1.12 seconds
Started May 07 03:17:35 PM PDT 24
Finished May 07 03:17:38 PM PDT 24
Peak memory 217252 kb
Host smart-ffc6ee95-bcbb-4383-9495-103391e08cb0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373218444 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1373218444
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2055196606
Short name T417
Test name
Test status
Simulation time 17800301 ps
CPU time 1.01 seconds
Started May 07 03:17:40 PM PDT 24
Finished May 07 03:17:44 PM PDT 24
Peak memory 218792 kb
Host smart-f34d9892-6e98-4e0d-bf29-505b45ce55b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055196606 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2055196606
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1047592218
Short name T460
Test name
Test status
Simulation time 37636161 ps
CPU time 1.59 seconds
Started May 07 03:17:36 PM PDT 24
Finished May 07 03:17:40 PM PDT 24
Peak memory 217864 kb
Host smart-02ed9b4b-8ac6-4518-8b9b-fd39b24a2f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047592218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1047592218
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1135282252
Short name T450
Test name
Test status
Simulation time 28703219 ps
CPU time 1.13 seconds
Started May 07 03:17:36 PM PDT 24
Finished May 07 03:17:39 PM PDT 24
Peak memory 223904 kb
Host smart-c4e1ae35-81f1-4d6e-9f1f-08aa1b287492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135282252 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1135282252
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2511502911
Short name T562
Test name
Test status
Simulation time 19341333 ps
CPU time 1.01 seconds
Started May 07 03:17:37 PM PDT 24
Finished May 07 03:17:41 PM PDT 24
Peak memory 215652 kb
Host smart-b8d7e4c8-e958-45fe-aa56-946ca8c6dff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511502911 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2511502911
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2818445374
Short name T570
Test name
Test status
Simulation time 489952754 ps
CPU time 2.34 seconds
Started May 07 03:17:36 PM PDT 24
Finished May 07 03:17:40 PM PDT 24
Peak memory 215632 kb
Host smart-52915a9b-dbce-4c89-8197-5b30615a808d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818445374 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2818445374
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_alert.3864585953
Short name T138
Test name
Test status
Simulation time 43804878 ps
CPU time 1.27 seconds
Started May 07 03:17:39 PM PDT 24
Finished May 07 03:17:44 PM PDT 24
Peak memory 216072 kb
Host smart-e14ed751-0259-419b-aee2-296a615ba4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864585953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3864585953
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1935871410
Short name T212
Test name
Test status
Simulation time 60557289 ps
CPU time 0.93 seconds
Started May 07 03:17:40 PM PDT 24
Finished May 07 03:17:44 PM PDT 24
Peak memory 207008 kb
Host smart-585ba63f-31bd-4143-acfc-2bceed014b31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935871410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1935871410
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.4061822782
Short name T835
Test name
Test status
Simulation time 39078257 ps
CPU time 0.84 seconds
Started May 07 03:17:41 PM PDT 24
Finished May 07 03:17:45 PM PDT 24
Peak memory 216300 kb
Host smart-61117693-0529-4bd8-b559-8f349444bf15
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061822782 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.4061822782
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3139105370
Short name T429
Test name
Test status
Simulation time 43975914 ps
CPU time 1.35 seconds
Started May 07 03:17:42 PM PDT 24
Finished May 07 03:17:46 PM PDT 24
Peak memory 218628 kb
Host smart-c118eb8c-e437-4fab-b5a1-1f1cd1fdeaff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139105370 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3139105370
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3432868279
Short name T103
Test name
Test status
Simulation time 28230076 ps
CPU time 1.25 seconds
Started May 07 03:17:40 PM PDT 24
Finished May 07 03:17:45 PM PDT 24
Peak memory 230144 kb
Host smart-f2a5ec41-8e04-4a44-94d8-4df9c9f90f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432868279 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3432868279
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3028892916
Short name T509
Test name
Test status
Simulation time 51230337 ps
CPU time 1.31 seconds
Started May 07 03:17:36 PM PDT 24
Finished May 07 03:17:39 PM PDT 24
Peak memory 218664 kb
Host smart-ff22eb65-4855-4639-a1c8-da1b32d78555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028892916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3028892916
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.35384614
Short name T423
Test name
Test status
Simulation time 33837173 ps
CPU time 0.82 seconds
Started May 07 03:17:44 PM PDT 24
Finished May 07 03:17:47 PM PDT 24
Peak memory 216056 kb
Host smart-9d7eacd0-932b-4529-ab1e-37e960ec0968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35384614 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.35384614
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.510271733
Short name T443
Test name
Test status
Simulation time 35182943 ps
CPU time 0.92 seconds
Started May 07 03:17:37 PM PDT 24
Finished May 07 03:17:40 PM PDT 24
Peak memory 215648 kb
Host smart-bbc53d24-ccfa-4a0b-a38a-5c91f552d662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510271733 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.510271733
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3666259593
Short name T722
Test name
Test status
Simulation time 21396060 ps
CPU time 1.02 seconds
Started May 07 03:17:40 PM PDT 24
Finished May 07 03:17:44 PM PDT 24
Peak memory 206772 kb
Host smart-2755f094-381d-4fc5-8b81-c0094c3991af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666259593 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3666259593
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3877466049
Short name T279
Test name
Test status
Simulation time 34009155394 ps
CPU time 471.89 seconds
Started May 07 03:17:39 PM PDT 24
Finished May 07 03:25:34 PM PDT 24
Peak memory 217088 kb
Host smart-26420db6-faa7-4d91-9bd5-ac8e5e3ee647
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877466049 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3877466049
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.530130319
Short name T627
Test name
Test status
Simulation time 78319195 ps
CPU time 1.17 seconds
Started May 07 03:17:40 PM PDT 24
Finished May 07 03:17:45 PM PDT 24
Peak memory 216068 kb
Host smart-ebef2544-c7af-4215-b6e3-6ea5b78bc89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530130319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.530130319
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.860042497
Short name T623
Test name
Test status
Simulation time 34042871 ps
CPU time 0.77 seconds
Started May 07 03:17:45 PM PDT 24
Finished May 07 03:17:47 PM PDT 24
Peak memory 207220 kb
Host smart-3fec8404-b50c-42be-b948-58e7de099075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860042497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.860042497
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3500334811
Short name T154
Test name
Test status
Simulation time 13790817 ps
CPU time 0.83 seconds
Started May 07 03:17:38 PM PDT 24
Finished May 07 03:17:42 PM PDT 24
Peak memory 216620 kb
Host smart-b37db493-dc25-4751-80a5-3d94a3a386bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500334811 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3500334811
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1838910456
Short name T109
Test name
Test status
Simulation time 27181436 ps
CPU time 1.13 seconds
Started May 07 03:17:39 PM PDT 24
Finished May 07 03:17:43 PM PDT 24
Peak memory 217332 kb
Host smart-80da9c04-d7c9-42a0-9060-77e756cabad9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838910456 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1838910456
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.142367570
Short name T825
Test name
Test status
Simulation time 31445334 ps
CPU time 0.89 seconds
Started May 07 03:17:42 PM PDT 24
Finished May 07 03:17:45 PM PDT 24
Peak memory 218756 kb
Host smart-62ada7dd-8f86-478d-8cc5-08b7b7ffcf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142367570 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.142367570
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3976199771
Short name T302
Test name
Test status
Simulation time 157487541 ps
CPU time 2.62 seconds
Started May 07 03:17:40 PM PDT 24
Finished May 07 03:17:46 PM PDT 24
Peak memory 217476 kb
Host smart-f46bb22e-e739-4998-9c1a-7bea42f7fac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976199771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3976199771
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.725389013
Short name T34
Test name
Test status
Simulation time 37467389 ps
CPU time 0.9 seconds
Started May 07 03:17:38 PM PDT 24
Finished May 07 03:17:42 PM PDT 24
Peak memory 215952 kb
Host smart-09f75eb6-31a0-4676-a255-66cffefc9dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725389013 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.725389013
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.173112949
Short name T654
Test name
Test status
Simulation time 19396910 ps
CPU time 1.06 seconds
Started May 07 03:17:44 PM PDT 24
Finished May 07 03:17:47 PM PDT 24
Peak memory 215644 kb
Host smart-199c73a2-9eb6-4eff-a740-9fbdde9cab3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173112949 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.173112949
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1281498348
Short name T164
Test name
Test status
Simulation time 344384096 ps
CPU time 5.54 seconds
Started May 07 03:17:39 PM PDT 24
Finished May 07 03:17:48 PM PDT 24
Peak memory 218532 kb
Host smart-b4a3069b-0bb0-40c3-8a31-e7835621867d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281498348 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1281498348
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.4069337926
Short name T575
Test name
Test status
Simulation time 64626789444 ps
CPU time 1624.15 seconds
Started May 07 03:17:38 PM PDT 24
Finished May 07 03:44:45 PM PDT 24
Peak memory 226344 kb
Host smart-ae6a09e7-463e-4f81-9182-3aaeaa9a47f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069337926 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.4069337926
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1642184596
Short name T267
Test name
Test status
Simulation time 70181704 ps
CPU time 1.12 seconds
Started May 07 03:17:39 PM PDT 24
Finished May 07 03:17:43 PM PDT 24
Peak memory 216120 kb
Host smart-a14143ee-4f76-4808-8ca7-add4ec3e7acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642184596 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1642184596
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.4012918561
Short name T609
Test name
Test status
Simulation time 25827159 ps
CPU time 0.88 seconds
Started May 07 03:17:39 PM PDT 24
Finished May 07 03:17:43 PM PDT 24
Peak memory 206996 kb
Host smart-eafb5b0f-835a-4f11-b9c2-a190e655a024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012918561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.4012918561
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2520629714
Short name T90
Test name
Test status
Simulation time 19113209 ps
CPU time 0.83 seconds
Started May 07 03:17:45 PM PDT 24
Finished May 07 03:17:47 PM PDT 24
Peak memory 216400 kb
Host smart-73a69855-b1f1-44ec-84a1-bd2fbcbd20da
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520629714 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2520629714
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1740454362
Short name T750
Test name
Test status
Simulation time 219445068 ps
CPU time 1.23 seconds
Started May 07 03:17:39 PM PDT 24
Finished May 07 03:17:43 PM PDT 24
Peak memory 217232 kb
Host smart-0cc8c5dd-2f26-4732-bf3f-7eda1b6031f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740454362 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1740454362
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3854626618
Short name T67
Test name
Test status
Simulation time 22056554 ps
CPU time 0.91 seconds
Started May 07 03:17:39 PM PDT 24
Finished May 07 03:17:43 PM PDT 24
Peak memory 218908 kb
Host smart-a68c222b-79b8-45e2-82ad-96b99f1e35eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854626618 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3854626618
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.864608432
Short name T52
Test name
Test status
Simulation time 46113047 ps
CPU time 1.27 seconds
Started May 07 03:17:37 PM PDT 24
Finished May 07 03:17:41 PM PDT 24
Peak memory 218472 kb
Host smart-3552804e-85be-4d05-bfb4-ecdb8da32287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864608432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.864608432
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.388725725
Short name T506
Test name
Test status
Simulation time 19737607 ps
CPU time 1.05 seconds
Started May 07 03:17:41 PM PDT 24
Finished May 07 03:17:45 PM PDT 24
Peak memory 216260 kb
Host smart-8d045421-dce2-40c2-b5ad-a0a3364b144d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388725725 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.388725725
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.439638494
Short name T63
Test name
Test status
Simulation time 28261516 ps
CPU time 0.93 seconds
Started May 07 03:17:40 PM PDT 24
Finished May 07 03:17:44 PM PDT 24
Peak memory 215660 kb
Host smart-65ce3333-3236-4dc9-8a05-fa8d8ddb9b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439638494 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.439638494
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3187681413
Short name T597
Test name
Test status
Simulation time 217155679 ps
CPU time 2.09 seconds
Started May 07 03:17:39 PM PDT 24
Finished May 07 03:17:44 PM PDT 24
Peak memory 217420 kb
Host smart-c0f6d691-e9e7-4451-806f-9dac49a479c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187681413 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3187681413
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1762493125
Short name T629
Test name
Test status
Simulation time 48506628103 ps
CPU time 1205.12 seconds
Started May 07 03:17:41 PM PDT 24
Finished May 07 03:37:49 PM PDT 24
Peak memory 230704 kb
Host smart-17797399-a9bb-4361-807d-306202f4dcc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762493125 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1762493125
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.139293827
Short name T137
Test name
Test status
Simulation time 117170271 ps
CPU time 1.16 seconds
Started May 07 03:16:27 PM PDT 24
Finished May 07 03:16:29 PM PDT 24
Peak memory 216072 kb
Host smart-15293182-addd-46cc-81db-992765ea5c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139293827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.139293827
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.553389418
Short name T2
Test name
Test status
Simulation time 30382518 ps
CPU time 0.92 seconds
Started May 07 03:16:29 PM PDT 24
Finished May 07 03:16:31 PM PDT 24
Peak memory 215212 kb
Host smart-e99a895a-d9a9-4d27-8f9c-20999e8ddf8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553389418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.553389418
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3143406906
Short name T762
Test name
Test status
Simulation time 24037369 ps
CPU time 0.97 seconds
Started May 07 03:16:28 PM PDT 24
Finished May 07 03:16:30 PM PDT 24
Peak memory 218608 kb
Host smart-1f89c263-8827-4e73-b70f-f2114c7d11a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143406906 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3143406906
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2506824507
Short name T75
Test name
Test status
Simulation time 28966123 ps
CPU time 1 seconds
Started May 07 03:16:25 PM PDT 24
Finished May 07 03:16:27 PM PDT 24
Peak memory 219828 kb
Host smart-44164317-df25-495f-b866-e74d5b5d5b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506824507 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2506824507
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1298576582
Short name T88
Test name
Test status
Simulation time 107909087 ps
CPU time 1.5 seconds
Started May 07 03:16:28 PM PDT 24
Finished May 07 03:16:31 PM PDT 24
Peak memory 218876 kb
Host smart-53dba3ba-db5a-48f2-9fe2-fef7bacc7aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298576582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1298576582
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1581713291
Short name T99
Test name
Test status
Simulation time 25328054 ps
CPU time 0.97 seconds
Started May 07 03:16:26 PM PDT 24
Finished May 07 03:16:28 PM PDT 24
Peak memory 216252 kb
Host smart-2c57bddf-f4bd-4106-ae40-f5a45bb1485b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581713291 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1581713291
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2714726275
Short name T721
Test name
Test status
Simulation time 83500894 ps
CPU time 0.92 seconds
Started May 07 03:16:26 PM PDT 24
Finished May 07 03:16:28 PM PDT 24
Peak memory 207408 kb
Host smart-7638a965-953b-405f-9730-59ed9e23b79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714726275 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2714726275
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1532269685
Short name T327
Test name
Test status
Simulation time 39764619 ps
CPU time 0.93 seconds
Started May 07 03:16:26 PM PDT 24
Finished May 07 03:16:28 PM PDT 24
Peak memory 215680 kb
Host smart-ff9f2520-753f-4902-9f8b-3f10305728e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532269685 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1532269685
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2089733893
Short name T4
Test name
Test status
Simulation time 666022158 ps
CPU time 3.96 seconds
Started May 07 03:16:28 PM PDT 24
Finished May 07 03:16:33 PM PDT 24
Peak memory 217528 kb
Host smart-2312e526-64c5-454e-8458-0c78aeb81fbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089733893 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2089733893
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.750554938
Short name T542
Test name
Test status
Simulation time 25748549052 ps
CPU time 658.4 seconds
Started May 07 03:16:27 PM PDT 24
Finished May 07 03:27:26 PM PDT 24
Peak memory 218056 kb
Host smart-0452803b-2149-4609-bb73-ecebca3f16b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750554938 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.750554938
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.3847056925
Short name T784
Test name
Test status
Simulation time 21187315 ps
CPU time 0.91 seconds
Started May 07 03:17:45 PM PDT 24
Finished May 07 03:17:48 PM PDT 24
Peak memory 218492 kb
Host smart-2657c6cb-a55d-4d30-a2c8-0a669a7bc3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847056925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3847056925
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.879046053
Short name T69
Test name
Test status
Simulation time 118908619 ps
CPU time 1.28 seconds
Started May 07 03:17:38 PM PDT 24
Finished May 07 03:17:43 PM PDT 24
Peak memory 217440 kb
Host smart-5eacb4cb-881e-4ed6-850b-ffd3711c9b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879046053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.879046053
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.3882286331
Short name T124
Test name
Test status
Simulation time 61641626 ps
CPU time 0.92 seconds
Started May 07 03:17:38 PM PDT 24
Finished May 07 03:17:42 PM PDT 24
Peak memory 219996 kb
Host smart-d2cd263a-3b07-4879-a28c-816a7b20d315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882286331 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3882286331
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2907390024
Short name T713
Test name
Test status
Simulation time 55493697 ps
CPU time 1.29 seconds
Started May 07 03:17:39 PM PDT 24
Finished May 07 03:17:43 PM PDT 24
Peak memory 217368 kb
Host smart-2ec7b5c0-7e1a-4e38-a7ed-88625365f372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907390024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2907390024
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.3805000587
Short name T592
Test name
Test status
Simulation time 27610667 ps
CPU time 0.91 seconds
Started May 07 03:17:38 PM PDT 24
Finished May 07 03:17:42 PM PDT 24
Peak memory 232624 kb
Host smart-0594cca0-19e1-4eb6-b5cc-f2a9cf402046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805000587 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3805000587
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3747236265
Short name T834
Test name
Test status
Simulation time 78272843 ps
CPU time 1.2 seconds
Started May 07 03:17:42 PM PDT 24
Finished May 07 03:17:45 PM PDT 24
Peak memory 220000 kb
Host smart-85b08645-756c-4126-91ba-86e38d39f751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747236265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3747236265
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.1479101513
Short name T633
Test name
Test status
Simulation time 32893091 ps
CPU time 1.07 seconds
Started May 07 03:17:45 PM PDT 24
Finished May 07 03:17:48 PM PDT 24
Peak memory 220376 kb
Host smart-c353a994-7dc7-4e3e-ab06-2b2d3e7b33f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479101513 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1479101513
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3674979379
Short name T340
Test name
Test status
Simulation time 42455651 ps
CPU time 1.46 seconds
Started May 07 03:17:38 PM PDT 24
Finished May 07 03:17:43 PM PDT 24
Peak memory 218364 kb
Host smart-4a131cdb-d321-4e98-a44c-68dde771778c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674979379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3674979379
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.1550687011
Short name T522
Test name
Test status
Simulation time 34267847 ps
CPU time 0.89 seconds
Started May 07 03:17:39 PM PDT 24
Finished May 07 03:17:43 PM PDT 24
Peak memory 218876 kb
Host smart-73c8dcbc-edad-4096-9b9e-f6208d6ae49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550687011 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1550687011
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2905538763
Short name T691
Test name
Test status
Simulation time 168446475 ps
CPU time 1.09 seconds
Started May 07 03:17:39 PM PDT 24
Finished May 07 03:17:43 PM PDT 24
Peak memory 217444 kb
Host smart-c2835c47-2b89-4463-abb7-4971759bd581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905538763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2905538763
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.315032917
Short name T588
Test name
Test status
Simulation time 196468809 ps
CPU time 1.05 seconds
Started May 07 03:17:42 PM PDT 24
Finished May 07 03:17:45 PM PDT 24
Peak memory 220368 kb
Host smart-fc97b24f-3b6f-43ef-8212-0b91e0dd8294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315032917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.315032917
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2370665024
Short name T262
Test name
Test status
Simulation time 44538677 ps
CPU time 1.23 seconds
Started May 07 03:17:42 PM PDT 24
Finished May 07 03:17:45 PM PDT 24
Peak memory 218492 kb
Host smart-be01184a-405f-4468-91a6-3f3a2d3ec78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370665024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2370665024
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.3639418412
Short name T7
Test name
Test status
Simulation time 45144225 ps
CPU time 0.87 seconds
Started May 07 03:17:40 PM PDT 24
Finished May 07 03:17:44 PM PDT 24
Peak memory 218840 kb
Host smart-8fb35d29-0a00-45b0-b8e8-5d40bae9f6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639418412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3639418412
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2804430051
Short name T708
Test name
Test status
Simulation time 41365385 ps
CPU time 1.12 seconds
Started May 07 03:17:37 PM PDT 24
Finished May 07 03:17:41 PM PDT 24
Peak memory 219172 kb
Host smart-a40e6f15-674a-4176-807e-d90287fd2d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804430051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2804430051
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2838484441
Short name T142
Test name
Test status
Simulation time 45882066 ps
CPU time 1.22 seconds
Started May 07 03:17:44 PM PDT 24
Finished May 07 03:17:47 PM PDT 24
Peak memory 226024 kb
Host smart-f50310c7-3a0a-4747-959e-bdebc95d85f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838484441 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2838484441
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3759160441
Short name T479
Test name
Test status
Simulation time 200387141 ps
CPU time 1.27 seconds
Started May 07 03:17:40 PM PDT 24
Finished May 07 03:17:44 PM PDT 24
Peak memory 217524 kb
Host smart-9a4d8339-b325-49d1-9773-a81c692728fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759160441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3759160441
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.3731715991
Short name T363
Test name
Test status
Simulation time 60576143 ps
CPU time 0.84 seconds
Started May 07 03:17:42 PM PDT 24
Finished May 07 03:17:45 PM PDT 24
Peak memory 218488 kb
Host smart-f34bcda7-3fd4-48a2-819b-93cb340d1132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731715991 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3731715991
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.393381135
Short name T706
Test name
Test status
Simulation time 33535100 ps
CPU time 1.35 seconds
Started May 07 03:17:51 PM PDT 24
Finished May 07 03:17:53 PM PDT 24
Peak memory 218668 kb
Host smart-cd27cff1-2c41-4cd9-95e3-f45fc0bdd233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393381135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.393381135
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.2939287142
Short name T70
Test name
Test status
Simulation time 21712564 ps
CPU time 0.91 seconds
Started May 07 03:17:44 PM PDT 24
Finished May 07 03:17:47 PM PDT 24
Peak memory 218324 kb
Host smart-faabd8a3-1b15-4600-9ed6-fb5e7f833144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939287142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2939287142
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2429884420
Short name T548
Test name
Test status
Simulation time 69845277 ps
CPU time 1.42 seconds
Started May 07 03:17:47 PM PDT 24
Finished May 07 03:17:49 PM PDT 24
Peak memory 219492 kb
Host smart-e97fa16f-a998-47fd-8b07-e0dd44a90d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429884420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2429884420
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert_test.3703426981
Short name T598
Test name
Test status
Simulation time 12291473 ps
CPU time 0.81 seconds
Started May 07 03:16:32 PM PDT 24
Finished May 07 03:16:33 PM PDT 24
Peak memory 207220 kb
Host smart-f0f1e4a1-183f-4f69-a6d7-94c40ee9bac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703426981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3703426981
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3777653081
Short name T147
Test name
Test status
Simulation time 100329827 ps
CPU time 0.85 seconds
Started May 07 03:16:35 PM PDT 24
Finished May 07 03:16:37 PM PDT 24
Peak memory 216644 kb
Host smart-ba119e38-497e-43b2-9242-cef9d46433cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777653081 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3777653081
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_err.3547094856
Short name T358
Test name
Test status
Simulation time 23029460 ps
CPU time 1.2 seconds
Started May 07 03:16:34 PM PDT 24
Finished May 07 03:16:36 PM PDT 24
Peak memory 233144 kb
Host smart-aa50cace-8a06-4205-90e9-e469a317d0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547094856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3547094856
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3492582515
Short name T98
Test name
Test status
Simulation time 129822019 ps
CPU time 1.75 seconds
Started May 07 03:16:27 PM PDT 24
Finished May 07 03:16:30 PM PDT 24
Peak memory 217708 kb
Host smart-2c64b80f-f9df-4e4a-bb3b-52f8c98ce965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492582515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3492582515
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.895858084
Short name T31
Test name
Test status
Simulation time 31118525 ps
CPU time 0.87 seconds
Started May 07 03:16:35 PM PDT 24
Finished May 07 03:16:38 PM PDT 24
Peak memory 216012 kb
Host smart-41d3783d-f5cd-4bf3-9b9a-b022fb02c7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895858084 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.895858084
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.4215165485
Short name T761
Test name
Test status
Simulation time 48148420 ps
CPU time 0.88 seconds
Started May 07 03:16:27 PM PDT 24
Finished May 07 03:16:29 PM PDT 24
Peak memory 215636 kb
Host smart-cf5d6385-d4e0-496b-a0ef-936ee6313e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215165485 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.4215165485
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3156941583
Short name T432
Test name
Test status
Simulation time 37266444 ps
CPU time 1.28 seconds
Started May 07 03:16:33 PM PDT 24
Finished May 07 03:16:35 PM PDT 24
Peak memory 215636 kb
Host smart-d38a3179-7ebe-476b-9d80-554a17309fae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156941583 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3156941583
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/60.edn_err.3509399425
Short name T133
Test name
Test status
Simulation time 26803760 ps
CPU time 0.9 seconds
Started May 07 03:17:43 PM PDT 24
Finished May 07 03:17:46 PM PDT 24
Peak memory 218600 kb
Host smart-f90cf816-be49-4a95-9c63-0f7ffef13c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509399425 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3509399425
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3175740419
Short name T622
Test name
Test status
Simulation time 50900687 ps
CPU time 1.04 seconds
Started May 07 03:17:46 PM PDT 24
Finished May 07 03:17:48 PM PDT 24
Peak memory 217428 kb
Host smart-00a0012a-10e6-4f86-a3e6-7a7ef648da08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175740419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3175740419
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.1004955982
Short name T178
Test name
Test status
Simulation time 44382367 ps
CPU time 1.31 seconds
Started May 07 03:17:53 PM PDT 24
Finished May 07 03:17:56 PM PDT 24
Peak memory 225948 kb
Host smart-076449c3-8559-47bf-bd5f-d2eedb48bb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004955982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1004955982
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.427171391
Short name T291
Test name
Test status
Simulation time 75931823 ps
CPU time 1.57 seconds
Started May 07 03:17:45 PM PDT 24
Finished May 07 03:17:48 PM PDT 24
Peak memory 218856 kb
Host smart-2d9e901c-c013-4567-8936-1494aab318eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427171391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.427171391
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.2752941680
Short name T410
Test name
Test status
Simulation time 19186183 ps
CPU time 1 seconds
Started May 07 03:17:45 PM PDT 24
Finished May 07 03:17:48 PM PDT 24
Peak memory 218700 kb
Host smart-109adb79-4df1-4e4a-9e34-de9fbb3fc154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752941680 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2752941680
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3131803317
Short name T639
Test name
Test status
Simulation time 104506563 ps
CPU time 1.53 seconds
Started May 07 03:17:45 PM PDT 24
Finished May 07 03:17:48 PM PDT 24
Peak memory 219156 kb
Host smart-7d11ce4c-1449-45c1-b8b1-821834cd36f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131803317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3131803317
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.1771304496
Short name T334
Test name
Test status
Simulation time 18252703 ps
CPU time 1.08 seconds
Started May 07 03:17:53 PM PDT 24
Finished May 07 03:17:55 PM PDT 24
Peak memory 218816 kb
Host smart-a3696a2d-84ef-43d2-9729-36153b22b757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771304496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1771304496
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3734768142
Short name T277
Test name
Test status
Simulation time 39390021 ps
CPU time 1.21 seconds
Started May 07 03:17:43 PM PDT 24
Finished May 07 03:17:46 PM PDT 24
Peak memory 217624 kb
Host smart-44d4f23b-84d6-42df-a284-6e9e15f91480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734768142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3734768142
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.1534034668
Short name T175
Test name
Test status
Simulation time 30154305 ps
CPU time 1.23 seconds
Started May 07 03:17:47 PM PDT 24
Finished May 07 03:17:50 PM PDT 24
Peak memory 219904 kb
Host smart-20b4550d-1478-4af0-b8b0-ba94834ec432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534034668 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1534034668
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.329043965
Short name T763
Test name
Test status
Simulation time 82939284 ps
CPU time 1.12 seconds
Started May 07 03:17:45 PM PDT 24
Finished May 07 03:17:48 PM PDT 24
Peak memory 217440 kb
Host smart-43cc08e9-188c-4310-abf6-db8fc50a7666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329043965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.329043965
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.1301258106
Short name T73
Test name
Test status
Simulation time 30512896 ps
CPU time 1 seconds
Started May 07 03:17:49 PM PDT 24
Finished May 07 03:17:52 PM PDT 24
Peak memory 232924 kb
Host smart-4cb27415-6df8-4abd-8c26-86bad2d3b367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301258106 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1301258106
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2423371506
Short name T92
Test name
Test status
Simulation time 264347303 ps
CPU time 1.46 seconds
Started May 07 03:17:46 PM PDT 24
Finished May 07 03:17:49 PM PDT 24
Peak memory 218704 kb
Host smart-709461aa-9be5-4014-b3a0-e0389361e5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423371506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2423371506
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.569309071
Short name T58
Test name
Test status
Simulation time 23173693 ps
CPU time 1.01 seconds
Started May 07 03:17:52 PM PDT 24
Finished May 07 03:17:54 PM PDT 24
Peak memory 224376 kb
Host smart-0a56d591-0a07-4f4e-80f7-288f0bef4d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569309071 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.569309071
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.169772643
Short name T313
Test name
Test status
Simulation time 38003592 ps
CPU time 1.78 seconds
Started May 07 03:17:53 PM PDT 24
Finished May 07 03:17:56 PM PDT 24
Peak memory 218740 kb
Host smart-7d10d9dc-0865-4c3c-b565-7432ba24f142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169772643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.169772643
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.1252192153
Short name T82
Test name
Test status
Simulation time 19660338 ps
CPU time 1.02 seconds
Started May 07 03:17:49 PM PDT 24
Finished May 07 03:17:51 PM PDT 24
Peak memory 218692 kb
Host smart-c99b94d9-59df-46cb-9a93-97a25108bc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252192153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1252192153
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3599679576
Short name T328
Test name
Test status
Simulation time 46101994 ps
CPU time 1.77 seconds
Started May 07 03:17:43 PM PDT 24
Finished May 07 03:17:46 PM PDT 24
Peak memory 218552 kb
Host smart-0bd207e5-b262-49db-b033-80231e86bb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599679576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3599679576
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1455151006
Short name T321
Test name
Test status
Simulation time 39839197 ps
CPU time 0.85 seconds
Started May 07 03:17:50 PM PDT 24
Finished May 07 03:17:52 PM PDT 24
Peak memory 218472 kb
Host smart-1b6606b4-61d1-472d-a42e-3ba26c66f57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455151006 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1455151006
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3535753608
Short name T399
Test name
Test status
Simulation time 224553291 ps
CPU time 1.65 seconds
Started May 07 03:17:43 PM PDT 24
Finished May 07 03:17:47 PM PDT 24
Peak memory 218880 kb
Host smart-980783f6-ee43-4139-af10-6a56572b1eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535753608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3535753608
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.2574913758
Short name T81
Test name
Test status
Simulation time 40751293 ps
CPU time 0.83 seconds
Started May 07 03:17:47 PM PDT 24
Finished May 07 03:17:49 PM PDT 24
Peak memory 218864 kb
Host smart-6f94d7bb-bf9c-48e2-9f4d-85d0eac8a693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574913758 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2574913758
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1168080427
Short name T739
Test name
Test status
Simulation time 43969185 ps
CPU time 1.41 seconds
Started May 07 03:17:52 PM PDT 24
Finished May 07 03:17:55 PM PDT 24
Peak memory 218324 kb
Host smart-99f5ae15-6ddc-485a-8742-0220c6cd0c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168080427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1168080427
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.140218819
Short name T167
Test name
Test status
Simulation time 506654465 ps
CPU time 1.59 seconds
Started May 07 03:16:35 PM PDT 24
Finished May 07 03:16:38 PM PDT 24
Peak memory 215944 kb
Host smart-026dc240-c573-484b-a495-21d13bc2d609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140218819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.140218819
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.4252732982
Short name T394
Test name
Test status
Simulation time 20302876 ps
CPU time 0.85 seconds
Started May 07 03:16:32 PM PDT 24
Finished May 07 03:16:34 PM PDT 24
Peak memory 207224 kb
Host smart-ccbde338-d173-4bdc-84e2-e42ac5417e20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252732982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.4252732982
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2413867183
Short name T663
Test name
Test status
Simulation time 39820285 ps
CPU time 0.81 seconds
Started May 07 03:16:34 PM PDT 24
Finished May 07 03:16:36 PM PDT 24
Peak memory 216632 kb
Host smart-64ac149a-10db-4221-ab39-20dcbd3c87aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413867183 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2413867183
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_err.2351140101
Short name T591
Test name
Test status
Simulation time 41244660 ps
CPU time 1.18 seconds
Started May 07 03:16:34 PM PDT 24
Finished May 07 03:16:36 PM PDT 24
Peak memory 220048 kb
Host smart-2ac46e71-fde9-4722-956e-60a9437a1527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351140101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2351140101
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.531233273
Short name T390
Test name
Test status
Simulation time 43694315 ps
CPU time 1.45 seconds
Started May 07 03:16:36 PM PDT 24
Finished May 07 03:16:38 PM PDT 24
Peak memory 218648 kb
Host smart-fca6b724-3584-4ce6-b219-83d31136f8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531233273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.531233273
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.4036988188
Short name T316
Test name
Test status
Simulation time 22161998 ps
CPU time 1.01 seconds
Started May 07 03:16:38 PM PDT 24
Finished May 07 03:16:40 PM PDT 24
Peak memory 215832 kb
Host smart-c9791cd1-701d-4f5d-9e8d-a5816ea1605d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036988188 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.4036988188
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_smoke.366048521
Short name T533
Test name
Test status
Simulation time 30287616 ps
CPU time 0.92 seconds
Started May 07 03:16:35 PM PDT 24
Finished May 07 03:16:37 PM PDT 24
Peak memory 215640 kb
Host smart-3ead4685-accb-4db4-9bc4-91f63b3b75a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366048521 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.366048521
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1534880697
Short name T455
Test name
Test status
Simulation time 582927660 ps
CPU time 2.77 seconds
Started May 07 03:16:34 PM PDT 24
Finished May 07 03:16:38 PM PDT 24
Peak memory 217440 kb
Host smart-cec47a2f-d986-45f6-972f-06920d47bb5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534880697 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1534880697
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3350891961
Short name T776
Test name
Test status
Simulation time 81301744428 ps
CPU time 551.52 seconds
Started May 07 03:16:33 PM PDT 24
Finished May 07 03:25:46 PM PDT 24
Peak memory 222868 kb
Host smart-24be15b6-8dae-43af-9c9e-4ba1558d77c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350891961 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3350891961
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.1974983542
Short name T806
Test name
Test status
Simulation time 19804886 ps
CPU time 1.07 seconds
Started May 07 03:17:52 PM PDT 24
Finished May 07 03:17:55 PM PDT 24
Peak memory 218980 kb
Host smart-be2b42df-4724-4b84-9f20-346e52ab591a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974983542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1974983542
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3761628878
Short name T511
Test name
Test status
Simulation time 53330088 ps
CPU time 1.23 seconds
Started May 07 03:17:48 PM PDT 24
Finished May 07 03:17:50 PM PDT 24
Peak memory 217616 kb
Host smart-73b4c04b-c7c5-4447-9332-c0fb8eae5c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761628878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3761628878
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.30789849
Short name T687
Test name
Test status
Simulation time 49274647 ps
CPU time 0.93 seconds
Started May 07 03:17:44 PM PDT 24
Finished May 07 03:17:46 PM PDT 24
Peak memory 224228 kb
Host smart-33757759-dce3-484f-852f-12dce261b9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30789849 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.30789849
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.714866601
Short name T336
Test name
Test status
Simulation time 60340279 ps
CPU time 1.38 seconds
Started May 07 03:17:45 PM PDT 24
Finished May 07 03:17:48 PM PDT 24
Peak memory 218948 kb
Host smart-538fe865-c6d0-442c-85c9-653db5bdd58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714866601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.714866601
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.700135290
Short name T785
Test name
Test status
Simulation time 19466603 ps
CPU time 1.18 seconds
Started May 07 03:17:52 PM PDT 24
Finished May 07 03:17:55 PM PDT 24
Peak memory 233148 kb
Host smart-4170c1e0-5605-4b2c-964c-ac811e30b4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700135290 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.700135290
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.411119748
Short name T247
Test name
Test status
Simulation time 27836103 ps
CPU time 1.09 seconds
Started May 07 03:17:47 PM PDT 24
Finished May 07 03:17:49 PM PDT 24
Peak memory 217360 kb
Host smart-dd21aa76-52c3-46b7-a082-7a3959e2f759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411119748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.411119748
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.1662290485
Short name T119
Test name
Test status
Simulation time 35219671 ps
CPU time 0.88 seconds
Started May 07 03:17:48 PM PDT 24
Finished May 07 03:17:50 PM PDT 24
Peak memory 220004 kb
Host smart-d7e8e9dd-a0d4-42bd-bbc4-39b0f3e09197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662290485 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1662290485
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3464668572
Short name T402
Test name
Test status
Simulation time 30120409 ps
CPU time 1.11 seconds
Started May 07 03:17:53 PM PDT 24
Finished May 07 03:17:56 PM PDT 24
Peak memory 218576 kb
Host smart-1cafdbdf-2d17-40e0-bd5a-2a9d982509c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464668572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3464668572
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.4085388124
Short name T470
Test name
Test status
Simulation time 24125230 ps
CPU time 1.15 seconds
Started May 07 03:17:53 PM PDT 24
Finished May 07 03:17:56 PM PDT 24
Peak memory 218908 kb
Host smart-875f3d60-3e40-439a-8e61-8d9c0359e526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085388124 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.4085388124
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3211739930
Short name T242
Test name
Test status
Simulation time 447039130 ps
CPU time 3.72 seconds
Started May 07 03:17:49 PM PDT 24
Finished May 07 03:17:54 PM PDT 24
Peak memory 220184 kb
Host smart-72a2624c-85cb-41df-88dd-f19bd25023ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211739930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3211739930
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.1895563469
Short name T149
Test name
Test status
Simulation time 25437531 ps
CPU time 0.93 seconds
Started May 07 03:17:43 PM PDT 24
Finished May 07 03:17:46 PM PDT 24
Peak memory 218916 kb
Host smart-f3470bf3-f561-47f1-9fa9-3a195e9d67e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895563469 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1895563469
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.418454170
Short name T275
Test name
Test status
Simulation time 37232001 ps
CPU time 1.57 seconds
Started May 07 03:17:47 PM PDT 24
Finished May 07 03:17:50 PM PDT 24
Peak memory 217460 kb
Host smart-3d5e7a50-bb35-45b9-b7ac-9b16ca1ef149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418454170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.418454170
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.2310662660
Short name T388
Test name
Test status
Simulation time 27350472 ps
CPU time 0.92 seconds
Started May 07 03:17:45 PM PDT 24
Finished May 07 03:17:47 PM PDT 24
Peak memory 224208 kb
Host smart-74d6d0de-c1e0-4819-8997-cfb931e536d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310662660 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2310662660
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2258979139
Short name T720
Test name
Test status
Simulation time 44815950 ps
CPU time 1.62 seconds
Started May 07 03:17:49 PM PDT 24
Finished May 07 03:17:52 PM PDT 24
Peak memory 215660 kb
Host smart-0a83f335-2be0-47d2-b278-0a4e448bd256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258979139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2258979139
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.989355417
Short name T350
Test name
Test status
Simulation time 32636234 ps
CPU time 1.01 seconds
Started May 07 03:17:44 PM PDT 24
Finished May 07 03:17:47 PM PDT 24
Peak memory 218964 kb
Host smart-3c7fd679-c3be-4333-959b-fb821b858b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989355417 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.989355417
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3601418973
Short name T791
Test name
Test status
Simulation time 62113642 ps
CPU time 1.07 seconds
Started May 07 03:17:45 PM PDT 24
Finished May 07 03:17:47 PM PDT 24
Peak memory 217360 kb
Host smart-6962189b-7e57-4ca3-b20e-e9598213ec33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601418973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3601418973
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.2156817677
Short name T182
Test name
Test status
Simulation time 22214146 ps
CPU time 1.08 seconds
Started May 07 03:17:43 PM PDT 24
Finished May 07 03:17:46 PM PDT 24
Peak memory 220180 kb
Host smart-bca7cd7b-9593-4cc1-943f-3acf004b0553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156817677 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2156817677
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.4288991128
Short name T773
Test name
Test status
Simulation time 111619418 ps
CPU time 1.2 seconds
Started May 07 03:17:45 PM PDT 24
Finished May 07 03:17:47 PM PDT 24
Peak memory 219944 kb
Host smart-06b7f5f1-785f-43ee-8e5e-0bd692aed255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288991128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.4288991128
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.2181734545
Short name T759
Test name
Test status
Simulation time 21010692 ps
CPU time 0.9 seconds
Started May 07 03:17:50 PM PDT 24
Finished May 07 03:17:52 PM PDT 24
Peak memory 218672 kb
Host smart-16493fc9-696c-4f79-9afd-80cec8c0ebc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181734545 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2181734545
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2056452491
Short name T478
Test name
Test status
Simulation time 41492638 ps
CPU time 1.43 seconds
Started May 07 03:17:45 PM PDT 24
Finished May 07 03:17:48 PM PDT 24
Peak memory 217576 kb
Host smart-41ae3cf6-822a-46a7-a65c-5981504859f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056452491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2056452491
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert_test.185190130
Short name T245
Test name
Test status
Simulation time 49936450 ps
CPU time 0.91 seconds
Started May 07 03:16:44 PM PDT 24
Finished May 07 03:16:46 PM PDT 24
Peak memory 206488 kb
Host smart-9cc575fd-2623-4fca-98f4-afc6223955b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185190130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.185190130
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2277443760
Short name T545
Test name
Test status
Simulation time 28144335 ps
CPU time 0.9 seconds
Started May 07 03:16:39 PM PDT 24
Finished May 07 03:16:40 PM PDT 24
Peak memory 216132 kb
Host smart-786b869c-7c7b-4a26-b8f9-dbb59e9759a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277443760 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2277443760
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2326051794
Short name T725
Test name
Test status
Simulation time 61785768 ps
CPU time 1.11 seconds
Started May 07 03:16:41 PM PDT 24
Finished May 07 03:16:44 PM PDT 24
Peak memory 217356 kb
Host smart-e1f36ec9-f93f-4e5f-98a0-7bda2741baf5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326051794 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2326051794
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2207975344
Short name T380
Test name
Test status
Simulation time 24290581 ps
CPU time 0.95 seconds
Started May 07 03:16:48 PM PDT 24
Finished May 07 03:16:51 PM PDT 24
Peak memory 218920 kb
Host smart-0dcd887d-fa0a-4c1c-b4c5-5027d967ea10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207975344 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2207975344
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1189167529
Short name T421
Test name
Test status
Simulation time 48921896 ps
CPU time 1.34 seconds
Started May 07 03:16:35 PM PDT 24
Finished May 07 03:16:38 PM PDT 24
Peak memory 219004 kb
Host smart-2fcc1915-371c-445e-a97e-590e01a8d0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189167529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1189167529
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3320315460
Short name T787
Test name
Test status
Simulation time 28277618 ps
CPU time 1.11 seconds
Started May 07 03:16:45 PM PDT 24
Finished May 07 03:16:48 PM PDT 24
Peak memory 223908 kb
Host smart-5b9b2afd-0e60-42d2-8df1-64a8325d026c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320315460 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3320315460
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3907138945
Short name T526
Test name
Test status
Simulation time 50162487 ps
CPU time 0.97 seconds
Started May 07 03:16:34 PM PDT 24
Finished May 07 03:16:36 PM PDT 24
Peak memory 207396 kb
Host smart-dc0db2de-9e6a-4584-97e0-aaa2fb3f83d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907138945 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3907138945
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3885582587
Short name T438
Test name
Test status
Simulation time 29584253 ps
CPU time 0.93 seconds
Started May 07 03:16:37 PM PDT 24
Finished May 07 03:16:39 PM PDT 24
Peak memory 215612 kb
Host smart-0ee38e03-c2fe-4313-8f84-78f5fd667469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885582587 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3885582587
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3248931576
Short name T488
Test name
Test status
Simulation time 175472100 ps
CPU time 1.6 seconds
Started May 07 03:16:32 PM PDT 24
Finished May 07 03:16:34 PM PDT 24
Peak memory 215564 kb
Host smart-a58191bf-cbe0-46b5-989b-0821f77b62a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248931576 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3248931576
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3341588328
Short name T203
Test name
Test status
Simulation time 191154243471 ps
CPU time 1047.53 seconds
Started May 07 03:16:35 PM PDT 24
Finished May 07 03:34:03 PM PDT 24
Peak memory 224068 kb
Host smart-6674796f-85a0-46fe-9e4d-97065466105a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341588328 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3341588328
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.4261635261
Short name T131
Test name
Test status
Simulation time 25023770 ps
CPU time 1.05 seconds
Started May 07 03:17:52 PM PDT 24
Finished May 07 03:17:55 PM PDT 24
Peak memory 224408 kb
Host smart-df306b26-406b-462a-981e-8afc7c3ada46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261635261 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.4261635261
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2576175876
Short name T407
Test name
Test status
Simulation time 65376120 ps
CPU time 2.17 seconds
Started May 07 03:17:51 PM PDT 24
Finished May 07 03:17:55 PM PDT 24
Peak memory 220304 kb
Host smart-01b893a5-15ed-4580-b1cf-9c971ddcc7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576175876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2576175876
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.2747733648
Short name T322
Test name
Test status
Simulation time 50985667 ps
CPU time 1 seconds
Started May 07 03:17:50 PM PDT 24
Finished May 07 03:17:52 PM PDT 24
Peak memory 221248 kb
Host smart-995d789f-9208-48b1-bc94-c1778c4a8358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747733648 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2747733648
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1432642708
Short name T727
Test name
Test status
Simulation time 46751404 ps
CPU time 1.82 seconds
Started May 07 03:17:51 PM PDT 24
Finished May 07 03:17:55 PM PDT 24
Peak memory 220088 kb
Host smart-78616fb5-e08c-4879-9884-30ce48de72fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432642708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1432642708
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_genbits.2358142304
Short name T729
Test name
Test status
Simulation time 76854014 ps
CPU time 1.24 seconds
Started May 07 03:17:48 PM PDT 24
Finished May 07 03:17:50 PM PDT 24
Peak memory 218980 kb
Host smart-0ed812e7-90ef-40b8-92eb-4f929178d9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358142304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2358142304
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.2978900394
Short name T155
Test name
Test status
Simulation time 44912064 ps
CPU time 0.86 seconds
Started May 07 03:17:50 PM PDT 24
Finished May 07 03:17:52 PM PDT 24
Peak memory 218744 kb
Host smart-22e5ff2d-5df6-4860-881c-c20e659d9dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978900394 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2978900394
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2956671302
Short name T744
Test name
Test status
Simulation time 37195071 ps
CPU time 1.29 seconds
Started May 07 03:17:50 PM PDT 24
Finished May 07 03:17:52 PM PDT 24
Peak memory 217184 kb
Host smart-5f7b0028-bddd-4ca7-bb19-4a85aa2be2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956671302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2956671302
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.1442584234
Short name T57
Test name
Test status
Simulation time 86928042 ps
CPU time 1.15 seconds
Started May 07 03:17:54 PM PDT 24
Finished May 07 03:17:56 PM PDT 24
Peak memory 226172 kb
Host smart-67ba0c52-5713-4a5b-8823-984f1808b104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442584234 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1442584234
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1806096113
Short name T349
Test name
Test status
Simulation time 42917102 ps
CPU time 1.52 seconds
Started May 07 03:17:51 PM PDT 24
Finished May 07 03:17:53 PM PDT 24
Peak memory 219860 kb
Host smart-fa54681c-0af5-478c-b119-dbb098f67d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806096113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1806096113
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.4046733396
Short name T8
Test name
Test status
Simulation time 23519579 ps
CPU time 1.2 seconds
Started May 07 03:17:51 PM PDT 24
Finished May 07 03:17:53 PM PDT 24
Peak memory 218900 kb
Host smart-fd6259b9-5b91-4cff-a12e-e73ad4c26ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046733396 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.4046733396
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.997911994
Short name T448
Test name
Test status
Simulation time 115642588 ps
CPU time 2.91 seconds
Started May 07 03:17:52 PM PDT 24
Finished May 07 03:17:56 PM PDT 24
Peak memory 219716 kb
Host smart-0fc1e43d-86a8-4e60-ae23-a6dcb1bc0ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997911994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.997911994
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1524341712
Short name T605
Test name
Test status
Simulation time 32543775 ps
CPU time 1.03 seconds
Started May 07 03:17:49 PM PDT 24
Finished May 07 03:17:51 PM PDT 24
Peak memory 224268 kb
Host smart-20c52cf0-ee76-43b9-aa3c-edb35ecbecb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524341712 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1524341712
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3731625330
Short name T418
Test name
Test status
Simulation time 49145219 ps
CPU time 1.17 seconds
Started May 07 03:17:50 PM PDT 24
Finished May 07 03:17:52 PM PDT 24
Peak memory 218828 kb
Host smart-d5938241-44f6-4d69-87d4-c2ed40036513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731625330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3731625330
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.3550553155
Short name T146
Test name
Test status
Simulation time 73608434 ps
CPU time 1 seconds
Started May 07 03:17:53 PM PDT 24
Finished May 07 03:17:55 PM PDT 24
Peak memory 224248 kb
Host smart-c3407973-589f-4118-910d-d885ef190ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550553155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3550553155
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2242918530
Short name T799
Test name
Test status
Simulation time 27507492 ps
CPU time 1.42 seconds
Started May 07 03:17:53 PM PDT 24
Finished May 07 03:17:56 PM PDT 24
Peak memory 219780 kb
Host smart-94525c03-3b5e-412b-b8fd-1cd1c4e1e796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242918530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2242918530
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.3059813003
Short name T559
Test name
Test status
Simulation time 20428181 ps
CPU time 1.06 seconds
Started May 07 03:17:51 PM PDT 24
Finished May 07 03:17:53 PM PDT 24
Peak memory 218740 kb
Host smart-ae8fa7a1-6827-4781-9d6e-2a2d3416886c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059813003 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3059813003
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1385876139
Short name T656
Test name
Test status
Simulation time 86320459 ps
CPU time 2.85 seconds
Started May 07 03:17:50 PM PDT 24
Finished May 07 03:17:55 PM PDT 24
Peak memory 220120 kb
Host smart-50d3d10e-c5fa-46fb-8ac3-c0bab3f98227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385876139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1385876139
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.1202703545
Short name T83
Test name
Test status
Simulation time 26316341 ps
CPU time 0.93 seconds
Started May 07 03:17:51 PM PDT 24
Finished May 07 03:17:54 PM PDT 24
Peak memory 218760 kb
Host smart-e40a566e-b90a-4130-b520-5409af5c248b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202703545 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1202703545
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1464117857
Short name T330
Test name
Test status
Simulation time 30275524 ps
CPU time 1.24 seconds
Started May 07 03:17:50 PM PDT 24
Finished May 07 03:17:52 PM PDT 24
Peak memory 218768 kb
Host smart-70dabb2a-d062-40a8-bcec-509e0b3acd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464117857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1464117857
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1080166065
Short name T451
Test name
Test status
Simulation time 72321783 ps
CPU time 1.22 seconds
Started May 07 03:16:40 PM PDT 24
Finished May 07 03:16:42 PM PDT 24
Peak memory 216044 kb
Host smart-19dca2ee-28a5-423c-94a2-aab3868f8220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080166065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1080166065
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.3227741853
Short name T76
Test name
Test status
Simulation time 29056050 ps
CPU time 0.9 seconds
Started May 07 03:16:40 PM PDT 24
Finished May 07 03:16:42 PM PDT 24
Peak memory 206980 kb
Host smart-347ae7dc-06cd-4411-bd19-161159a7f6c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227741853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3227741853
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.588420353
Short name T714
Test name
Test status
Simulation time 25406685 ps
CPU time 0.89 seconds
Started May 07 03:16:45 PM PDT 24
Finished May 07 03:16:47 PM PDT 24
Peak memory 216108 kb
Host smart-11057740-a124-43ce-a491-98fd673d0e1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588420353 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.588420353
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1529527203
Short name T127
Test name
Test status
Simulation time 76771426 ps
CPU time 1.12 seconds
Started May 07 03:16:48 PM PDT 24
Finished May 07 03:16:51 PM PDT 24
Peak memory 217168 kb
Host smart-d7375626-979d-4856-aba0-0c04671e6fa4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529527203 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1529527203
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1478158062
Short name T519
Test name
Test status
Simulation time 32780000 ps
CPU time 0.96 seconds
Started May 07 03:16:47 PM PDT 24
Finished May 07 03:16:50 PM PDT 24
Peak memory 220012 kb
Host smart-759846e8-6012-4b15-b91e-90fb15c7201b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478158062 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1478158062
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.240285123
Short name T441
Test name
Test status
Simulation time 68004382 ps
CPU time 2.22 seconds
Started May 07 03:16:41 PM PDT 24
Finished May 07 03:16:44 PM PDT 24
Peak memory 219920 kb
Host smart-a6e13cfb-11f7-4e5a-ab3b-0c58235eb510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240285123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.240285123
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2645234113
Short name T564
Test name
Test status
Simulation time 22412814 ps
CPU time 1.12 seconds
Started May 07 03:16:40 PM PDT 24
Finished May 07 03:16:42 PM PDT 24
Peak memory 215980 kb
Host smart-ae7d2d5f-b46d-4cfb-9f59-55668dfc248d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645234113 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2645234113
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2538421924
Short name T29
Test name
Test status
Simulation time 19206649 ps
CPU time 1.07 seconds
Started May 07 03:16:45 PM PDT 24
Finished May 07 03:16:48 PM PDT 24
Peak memory 206932 kb
Host smart-ffa014cc-7be2-4805-b979-b642718083b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538421924 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2538421924
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3507558199
Short name T549
Test name
Test status
Simulation time 26914811 ps
CPU time 0.98 seconds
Started May 07 03:16:45 PM PDT 24
Finished May 07 03:16:48 PM PDT 24
Peak memory 215120 kb
Host smart-1aa8fa59-a6d8-4b4c-a8a5-3e5ab2d0ca46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507558199 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3507558199
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2280102153
Short name T755
Test name
Test status
Simulation time 474244110 ps
CPU time 3.04 seconds
Started May 07 03:16:39 PM PDT 24
Finished May 07 03:16:43 PM PDT 24
Peak memory 215624 kb
Host smart-c8e38595-d74c-460e-a734-dee0ef91657b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280102153 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2280102153
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3499100391
Short name T696
Test name
Test status
Simulation time 39819118871 ps
CPU time 596.22 seconds
Started May 07 03:16:40 PM PDT 24
Finished May 07 03:26:37 PM PDT 24
Peak memory 224036 kb
Host smart-ee2c8c05-2325-42d1-a3d8-65ce32d32973
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499100391 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3499100391
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.119208723
Short name T117
Test name
Test status
Simulation time 38190746 ps
CPU time 1.06 seconds
Started May 07 03:17:54 PM PDT 24
Finished May 07 03:17:56 PM PDT 24
Peak memory 220908 kb
Host smart-193b633c-ca77-4358-88ea-d155ed1908a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119208723 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.119208723
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.4241232109
Short name T563
Test name
Test status
Simulation time 53424363 ps
CPU time 1.2 seconds
Started May 07 03:17:51 PM PDT 24
Finished May 07 03:17:54 PM PDT 24
Peak memory 217404 kb
Host smart-683498d4-81c5-402b-806c-02458554132d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241232109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.4241232109
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.1354952195
Short name T804
Test name
Test status
Simulation time 19328067 ps
CPU time 1.2 seconds
Started May 07 03:17:51 PM PDT 24
Finished May 07 03:17:53 PM PDT 24
Peak memory 224428 kb
Host smart-12edcb82-7e13-4291-a0f9-4f09b54d01a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354952195 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1354952195
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1663759006
Short name T459
Test name
Test status
Simulation time 62447864 ps
CPU time 1.32 seconds
Started May 07 03:17:50 PM PDT 24
Finished May 07 03:17:52 PM PDT 24
Peak memory 218392 kb
Host smart-57a882be-ac99-4374-b1e1-6ca201af47d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663759006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1663759006
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.2352991654
Short name T397
Test name
Test status
Simulation time 19770944 ps
CPU time 1.09 seconds
Started May 07 03:17:52 PM PDT 24
Finished May 07 03:17:55 PM PDT 24
Peak memory 233108 kb
Host smart-bdc480bd-b0f7-4b37-be6f-6cfdf66f71a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352991654 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2352991654
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.880195844
Short name T827
Test name
Test status
Simulation time 61314912 ps
CPU time 1.32 seconds
Started May 07 03:17:51 PM PDT 24
Finished May 07 03:17:54 PM PDT 24
Peak memory 218564 kb
Host smart-ea4e3a1b-4788-4b00-90f2-1bc91a0c96f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880195844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.880195844
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.2843714392
Short name T736
Test name
Test status
Simulation time 19664752 ps
CPU time 1.27 seconds
Started May 07 03:18:00 PM PDT 24
Finished May 07 03:18:02 PM PDT 24
Peak memory 224468 kb
Host smart-2c346dd4-c6e2-4120-a991-d513c90df4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843714392 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2843714392
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2304128434
Short name T84
Test name
Test status
Simulation time 210979136 ps
CPU time 2.25 seconds
Started May 07 03:17:52 PM PDT 24
Finished May 07 03:17:56 PM PDT 24
Peak memory 219216 kb
Host smart-1bd76d5f-ed68-4b9a-831f-6a07efdc5b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304128434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2304128434
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.3164516323
Short name T174
Test name
Test status
Simulation time 38557287 ps
CPU time 1.15 seconds
Started May 07 03:18:02 PM PDT 24
Finished May 07 03:18:05 PM PDT 24
Peak memory 220144 kb
Host smart-ae0584f8-1273-4133-83c4-e2df28764b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164516323 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3164516323
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3344277134
Short name T695
Test name
Test status
Simulation time 61614897 ps
CPU time 1.14 seconds
Started May 07 03:18:00 PM PDT 24
Finished May 07 03:18:02 PM PDT 24
Peak memory 218612 kb
Host smart-68ffa0ec-2836-471a-b68c-70f85ce8ba7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344277134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3344277134
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.3654193080
Short name T56
Test name
Test status
Simulation time 19590701 ps
CPU time 1.19 seconds
Started May 07 03:17:56 PM PDT 24
Finished May 07 03:17:59 PM PDT 24
Peak memory 224472 kb
Host smart-3adbbcdb-03ec-4209-8ec9-7493a933294b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654193080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3654193080
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.886528462
Short name T310
Test name
Test status
Simulation time 96463416 ps
CPU time 1.19 seconds
Started May 07 03:17:56 PM PDT 24
Finished May 07 03:17:58 PM PDT 24
Peak memory 217356 kb
Host smart-e0738bf9-0f20-4d50-8da8-35db0c09c8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886528462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.886528462
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3568073670
Short name T111
Test name
Test status
Simulation time 36422899 ps
CPU time 1.13 seconds
Started May 07 03:17:55 PM PDT 24
Finished May 07 03:17:58 PM PDT 24
Peak memory 220972 kb
Host smart-044f0653-ba09-4a79-b7b9-4debfe152b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568073670 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3568073670
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1965031926
Short name T553
Test name
Test status
Simulation time 301917574 ps
CPU time 2.99 seconds
Started May 07 03:17:56 PM PDT 24
Finished May 07 03:18:00 PM PDT 24
Peak memory 218752 kb
Host smart-dc266623-0118-4276-b64f-4b29a0d57d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965031926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1965031926
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.4030412106
Short name T116
Test name
Test status
Simulation time 21661522 ps
CPU time 1.13 seconds
Started May 07 03:17:53 PM PDT 24
Finished May 07 03:17:55 PM PDT 24
Peak memory 220116 kb
Host smart-51b99a95-a377-4305-9c4e-b5325ed531c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030412106 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.4030412106
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.79150901
Short name T420
Test name
Test status
Simulation time 57330064 ps
CPU time 2.25 seconds
Started May 07 03:17:55 PM PDT 24
Finished May 07 03:17:59 PM PDT 24
Peak memory 219264 kb
Host smart-219eda46-d1c3-450c-b19b-508765030853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79150901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.79150901
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.338543284
Short name T616
Test name
Test status
Simulation time 18672114 ps
CPU time 1.1 seconds
Started May 07 03:17:55 PM PDT 24
Finished May 07 03:17:58 PM PDT 24
Peak memory 218784 kb
Host smart-db47da52-2ce9-4855-9681-dfe57dd33fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338543284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.338543284
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.4064142028
Short name T51
Test name
Test status
Simulation time 47579808 ps
CPU time 1.7 seconds
Started May 07 03:17:54 PM PDT 24
Finished May 07 03:17:57 PM PDT 24
Peak memory 219348 kb
Host smart-a707d24f-bf75-4471-aed8-4251522058e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064142028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.4064142028
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.766445755
Short name T61
Test name
Test status
Simulation time 30088176 ps
CPU time 1.37 seconds
Started May 07 03:18:00 PM PDT 24
Finished May 07 03:18:02 PM PDT 24
Peak memory 226036 kb
Host smart-c384448b-7375-449d-b65d-4d4f532bb8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766445755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.766445755
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2828515763
Short name T823
Test name
Test status
Simulation time 71114288 ps
CPU time 1.9 seconds
Started May 07 03:18:00 PM PDT 24
Finished May 07 03:18:03 PM PDT 24
Peak memory 217672 kb
Host smart-788c6dd1-8636-4d99-8d76-7cb70e661db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828515763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2828515763
Directory /workspace/99.edn_genbits/latest
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