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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.31 98.24 93.82 97.02 82.08 96.76 99.77 92.47


Total test records in report: 975
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T784 /workspace/coverage/default/20.edn_genbits.1477037577 May 09 02:25:59 PM PDT 24 May 09 02:26:02 PM PDT 24 82300367 ps
T785 /workspace/coverage/default/37.edn_intr.3813375050 May 09 02:26:52 PM PDT 24 May 09 02:26:57 PM PDT 24 20116186 ps
T786 /workspace/coverage/default/43.edn_smoke.507142086 May 09 02:27:07 PM PDT 24 May 09 02:27:16 PM PDT 24 41476588 ps
T787 /workspace/coverage/default/54.edn_err.2022470622 May 09 02:27:45 PM PDT 24 May 09 02:27:49 PM PDT 24 27158495 ps
T788 /workspace/coverage/default/45.edn_alert_test.1227089567 May 09 02:27:26 PM PDT 24 May 09 02:27:33 PM PDT 24 49255911 ps
T789 /workspace/coverage/default/11.edn_err.3384454470 May 09 02:25:46 PM PDT 24 May 09 02:25:51 PM PDT 24 28938272 ps
T790 /workspace/coverage/default/23.edn_disable_auto_req_mode.3320944726 May 09 02:26:05 PM PDT 24 May 09 02:26:09 PM PDT 24 59330645 ps
T791 /workspace/coverage/default/56.edn_genbits.120644947 May 09 02:27:46 PM PDT 24 May 09 02:27:51 PM PDT 24 40287921 ps
T286 /workspace/coverage/default/270.edn_genbits.3842733081 May 09 02:29:11 PM PDT 24 May 09 02:29:19 PM PDT 24 274870245 ps
T168 /workspace/coverage/default/43.edn_err.2595299730 May 09 02:27:12 PM PDT 24 May 09 02:27:19 PM PDT 24 77003450 ps
T792 /workspace/coverage/default/84.edn_genbits.4220929617 May 09 02:28:06 PM PDT 24 May 09 02:28:13 PM PDT 24 307339715 ps
T793 /workspace/coverage/default/38.edn_err.3089489226 May 09 02:26:55 PM PDT 24 May 09 02:27:00 PM PDT 24 29554214 ps
T794 /workspace/coverage/default/1.edn_err.826641841 May 09 02:25:27 PM PDT 24 May 09 02:25:31 PM PDT 24 29659036 ps
T795 /workspace/coverage/default/115.edn_genbits.3820676759 May 09 02:28:23 PM PDT 24 May 09 02:28:27 PM PDT 24 288957996 ps
T796 /workspace/coverage/default/23.edn_genbits.2397715672 May 09 02:26:04 PM PDT 24 May 09 02:26:07 PM PDT 24 84666932 ps
T797 /workspace/coverage/default/41.edn_stress_all.918062648 May 09 02:27:06 PM PDT 24 May 09 02:27:14 PM PDT 24 90531754 ps
T244 /workspace/coverage/default/5.edn_regwen.1344719052 May 09 02:25:33 PM PDT 24 May 09 02:25:35 PM PDT 24 53491647 ps
T798 /workspace/coverage/default/202.edn_genbits.3310471005 May 09 02:28:58 PM PDT 24 May 09 02:29:02 PM PDT 24 75114547 ps
T799 /workspace/coverage/default/287.edn_genbits.2585670850 May 09 02:29:28 PM PDT 24 May 09 02:29:35 PM PDT 24 55885795 ps
T800 /workspace/coverage/default/86.edn_err.1993083473 May 09 02:28:05 PM PDT 24 May 09 02:28:10 PM PDT 24 40950780 ps
T801 /workspace/coverage/default/45.edn_err.915524547 May 09 02:27:11 PM PDT 24 May 09 02:27:19 PM PDT 24 29219446 ps
T802 /workspace/coverage/default/18.edn_disable.2040337374 May 09 02:26:00 PM PDT 24 May 09 02:26:03 PM PDT 24 13307010 ps
T803 /workspace/coverage/default/31.edn_alert.694129013 May 09 02:26:37 PM PDT 24 May 09 02:26:41 PM PDT 24 67275960 ps
T804 /workspace/coverage/default/5.edn_err.3895243021 May 09 02:25:38 PM PDT 24 May 09 02:25:41 PM PDT 24 42535468 ps
T805 /workspace/coverage/default/38.edn_intr.294374074 May 09 02:26:55 PM PDT 24 May 09 02:27:00 PM PDT 24 54169444 ps
T806 /workspace/coverage/default/49.edn_alert.4108862957 May 09 02:27:34 PM PDT 24 May 09 02:27:39 PM PDT 24 363428978 ps
T807 /workspace/coverage/default/226.edn_genbits.2286018660 May 09 02:29:00 PM PDT 24 May 09 02:29:05 PM PDT 24 32030595 ps
T808 /workspace/coverage/default/8.edn_alert.552988365 May 09 02:25:47 PM PDT 24 May 09 02:25:52 PM PDT 24 51639980 ps
T809 /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3252254559 May 09 02:26:21 PM PDT 24 May 09 02:51:16 PM PDT 24 248312781268 ps
T810 /workspace/coverage/default/22.edn_disable_auto_req_mode.2795606480 May 09 02:26:12 PM PDT 24 May 09 02:26:14 PM PDT 24 80475243 ps
T811 /workspace/coverage/default/28.edn_intr.687993633 May 09 02:26:18 PM PDT 24 May 09 02:26:21 PM PDT 24 21653270 ps
T812 /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3155742055 May 09 02:25:42 PM PDT 24 May 09 03:04:08 PM PDT 24 510485162234 ps
T813 /workspace/coverage/default/35.edn_smoke.2998391366 May 09 02:26:51 PM PDT 24 May 09 02:26:55 PM PDT 24 18683315 ps
T814 /workspace/coverage/default/12.edn_disable.883308494 May 09 02:25:52 PM PDT 24 May 09 02:25:56 PM PDT 24 17487593 ps
T815 /workspace/coverage/default/1.edn_alert_test.3342196150 May 09 02:25:27 PM PDT 24 May 09 02:25:30 PM PDT 24 143516175 ps
T816 /workspace/coverage/default/21.edn_stress_all.3286264120 May 09 02:26:00 PM PDT 24 May 09 02:26:05 PM PDT 24 169920914 ps
T817 /workspace/coverage/default/70.edn_err.2040839242 May 09 02:27:55 PM PDT 24 May 09 02:28:00 PM PDT 24 24568813 ps
T818 /workspace/coverage/default/182.edn_genbits.2809231545 May 09 02:28:50 PM PDT 24 May 09 02:28:54 PM PDT 24 31817889 ps
T819 /workspace/coverage/default/135.edn_genbits.3037646582 May 09 02:28:29 PM PDT 24 May 09 02:28:32 PM PDT 24 74469112 ps
T820 /workspace/coverage/default/48.edn_smoke.95243724 May 09 02:27:24 PM PDT 24 May 09 02:27:30 PM PDT 24 19636060 ps
T107 /workspace/coverage/default/71.edn_err.92633823 May 09 02:27:53 PM PDT 24 May 09 02:27:58 PM PDT 24 49511467 ps
T821 /workspace/coverage/default/10.edn_smoke.1276054576 May 09 02:25:49 PM PDT 24 May 09 02:25:54 PM PDT 24 64065753 ps
T822 /workspace/coverage/default/198.edn_genbits.3466863506 May 09 02:28:50 PM PDT 24 May 09 02:28:55 PM PDT 24 36730065 ps
T823 /workspace/coverage/default/83.edn_genbits.2183548048 May 09 02:28:04 PM PDT 24 May 09 02:28:10 PM PDT 24 93148325 ps
T824 /workspace/coverage/default/36.edn_genbits.2301981573 May 09 02:26:50 PM PDT 24 May 09 02:26:57 PM PDT 24 159908038 ps
T825 /workspace/coverage/default/0.edn_regwen.1576895006 May 09 02:25:19 PM PDT 24 May 09 02:25:21 PM PDT 24 38466383 ps
T826 /workspace/coverage/default/96.edn_err.3801726224 May 09 02:28:11 PM PDT 24 May 09 02:28:16 PM PDT 24 78270744 ps
T827 /workspace/coverage/default/23.edn_alert.107015630 May 09 02:26:03 PM PDT 24 May 09 02:26:06 PM PDT 24 126081720 ps
T828 /workspace/coverage/default/23.edn_stress_all_with_rand_reset.932054346 May 09 02:26:12 PM PDT 24 May 09 02:33:28 PM PDT 24 71182948710 ps
T829 /workspace/coverage/default/282.edn_genbits.2312812481 May 09 02:29:19 PM PDT 24 May 09 02:29:25 PM PDT 24 178839275 ps
T830 /workspace/coverage/default/225.edn_genbits.2120892458 May 09 02:28:59 PM PDT 24 May 09 02:29:03 PM PDT 24 73180277 ps
T831 /workspace/coverage/default/27.edn_alert_test.1158274678 May 09 02:26:14 PM PDT 24 May 09 02:26:17 PM PDT 24 79698910 ps
T832 /workspace/coverage/default/13.edn_genbits.4108835034 May 09 02:25:46 PM PDT 24 May 09 02:25:50 PM PDT 24 106635313 ps
T833 /workspace/coverage/default/14.edn_smoke.383292174 May 09 02:25:49 PM PDT 24 May 09 02:25:54 PM PDT 24 20570363 ps
T834 /workspace/coverage/default/154.edn_genbits.2705633864 May 09 03:24:41 PM PDT 24 May 09 03:25:14 PM PDT 24 92491020 ps
T835 /workspace/coverage/default/8.edn_disable.4068248115 May 09 02:25:37 PM PDT 24 May 09 02:25:39 PM PDT 24 36544715 ps
T836 /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3506157078 May 09 02:26:40 PM PDT 24 May 09 03:01:24 PM PDT 24 181815769763 ps
T837 /workspace/coverage/default/65.edn_err.2930775265 May 09 02:27:45 PM PDT 24 May 09 02:27:49 PM PDT 24 29518645 ps
T838 /workspace/coverage/default/21.edn_stress_all_with_rand_reset.609416484 May 09 02:26:02 PM PDT 24 May 09 02:44:57 PM PDT 24 337278059559 ps
T839 /workspace/coverage/default/60.edn_genbits.989841040 May 09 02:27:50 PM PDT 24 May 09 02:27:54 PM PDT 24 209030296 ps
T840 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3130588892 May 09 01:40:08 PM PDT 24 May 09 01:40:10 PM PDT 24 84804010 ps
T841 /workspace/coverage/cover_reg_top/2.edn_intr_test.1868495663 May 09 01:39:56 PM PDT 24 May 09 01:39:59 PM PDT 24 42976183 ps
T222 /workspace/coverage/cover_reg_top/18.edn_csr_rw.2843075346 May 09 01:40:16 PM PDT 24 May 09 01:40:19 PM PDT 24 20623016 ps
T202 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4275567629 May 09 01:39:58 PM PDT 24 May 09 01:40:02 PM PDT 24 30456908 ps
T203 /workspace/coverage/cover_reg_top/0.edn_csr_rw.876697629 May 09 01:39:48 PM PDT 24 May 09 01:39:50 PM PDT 24 44169206 ps
T842 /workspace/coverage/cover_reg_top/42.edn_intr_test.1946915794 May 09 01:40:21 PM PDT 24 May 09 01:40:23 PM PDT 24 21651194 ps
T204 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.939738735 May 09 01:39:59 PM PDT 24 May 09 01:40:02 PM PDT 24 17258678 ps
T843 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3693953464 May 09 01:39:56 PM PDT 24 May 09 01:40:00 PM PDT 24 30846132 ps
T205 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3853707112 May 09 01:40:15 PM PDT 24 May 09 01:40:17 PM PDT 24 22302723 ps
T844 /workspace/coverage/cover_reg_top/34.edn_intr_test.1188729849 May 09 01:40:16 PM PDT 24 May 09 01:40:19 PM PDT 24 14001228 ps
T206 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2401490917 May 09 01:40:10 PM PDT 24 May 09 01:40:13 PM PDT 24 24632466 ps
T207 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2190456952 May 09 01:40:06 PM PDT 24 May 09 01:40:08 PM PDT 24 30763669 ps
T845 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3319682819 May 09 01:40:09 PM PDT 24 May 09 01:40:12 PM PDT 24 36521096 ps
T846 /workspace/coverage/cover_reg_top/5.edn_intr_test.1040058772 May 09 01:39:57 PM PDT 24 May 09 01:40:01 PM PDT 24 13021208 ps
T847 /workspace/coverage/cover_reg_top/3.edn_intr_test.126745029 May 09 01:39:55 PM PDT 24 May 09 01:39:58 PM PDT 24 13026995 ps
T218 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.539943152 May 09 01:40:19 PM PDT 24 May 09 01:40:22 PM PDT 24 27535339 ps
T848 /workspace/coverage/cover_reg_top/1.edn_tl_errors.2631860372 May 09 01:39:56 PM PDT 24 May 09 01:40:00 PM PDT 24 187055284 ps
T223 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1452371499 May 09 01:39:58 PM PDT 24 May 09 01:40:01 PM PDT 24 25725785 ps
T208 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1415444294 May 09 01:39:53 PM PDT 24 May 09 01:39:56 PM PDT 24 22151408 ps
T849 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3419062407 May 09 01:40:11 PM PDT 24 May 09 01:40:13 PM PDT 24 50139139 ps
T850 /workspace/coverage/cover_reg_top/13.edn_tl_errors.4181469253 May 09 01:40:11 PM PDT 24 May 09 01:40:16 PM PDT 24 105782375 ps
T209 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3619431044 May 09 01:40:09 PM PDT 24 May 09 01:40:11 PM PDT 24 24190146 ps
T851 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.390950836 May 09 01:39:55 PM PDT 24 May 09 01:40:04 PM PDT 24 224583457 ps
T219 /workspace/coverage/cover_reg_top/15.edn_csr_rw.231751532 May 09 01:40:12 PM PDT 24 May 09 01:40:14 PM PDT 24 59007098 ps
T210 /workspace/coverage/cover_reg_top/1.edn_csr_rw.1569514465 May 09 01:39:54 PM PDT 24 May 09 01:39:57 PM PDT 24 39552746 ps
T220 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2056068931 May 09 01:40:14 PM PDT 24 May 09 01:40:16 PM PDT 24 15359849 ps
T211 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2859558987 May 09 01:39:55 PM PDT 24 May 09 01:39:57 PM PDT 24 52017259 ps
T852 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3691448289 May 09 01:39:58 PM PDT 24 May 09 01:40:02 PM PDT 24 41974806 ps
T224 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1467522873 May 09 01:40:10 PM PDT 24 May 09 01:40:14 PM PDT 24 104343980 ps
T853 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.914102894 May 09 01:40:08 PM PDT 24 May 09 01:40:10 PM PDT 24 40526443 ps
T854 /workspace/coverage/cover_reg_top/27.edn_intr_test.1567501761 May 09 01:40:16 PM PDT 24 May 09 01:40:19 PM PDT 24 11151818 ps
T225 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2946763071 May 09 01:40:20 PM PDT 24 May 09 01:40:24 PM PDT 24 377878685 ps
T855 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3742554287 May 09 01:39:58 PM PDT 24 May 09 01:40:03 PM PDT 24 187891413 ps
T856 /workspace/coverage/cover_reg_top/1.edn_intr_test.1347569626 May 09 01:39:57 PM PDT 24 May 09 01:40:00 PM PDT 24 192429889 ps
T221 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4254148482 May 09 01:40:14 PM PDT 24 May 09 01:40:16 PM PDT 24 17821084 ps
T857 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2316082631 May 09 01:40:15 PM PDT 24 May 09 01:40:18 PM PDT 24 69928460 ps
T858 /workspace/coverage/cover_reg_top/0.edn_intr_test.476362905 May 09 01:39:46 PM PDT 24 May 09 01:39:50 PM PDT 24 14126607 ps
T859 /workspace/coverage/cover_reg_top/32.edn_intr_test.1149418453 May 09 01:40:20 PM PDT 24 May 09 01:40:23 PM PDT 24 39286862 ps
T860 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2699497383 May 09 01:40:05 PM PDT 24 May 09 01:40:07 PM PDT 24 33992294 ps
T861 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1659393409 May 09 01:39:55 PM PDT 24 May 09 01:39:58 PM PDT 24 17309219 ps
T862 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.371027415 May 09 01:39:58 PM PDT 24 May 09 01:40:01 PM PDT 24 267390089 ps
T863 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3462991612 May 09 01:40:01 PM PDT 24 May 09 01:40:04 PM PDT 24 20410411 ps
T864 /workspace/coverage/cover_reg_top/4.edn_intr_test.3336655366 May 09 01:39:56 PM PDT 24 May 09 01:40:00 PM PDT 24 53396786 ps
T226 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.4245896530 May 09 01:40:12 PM PDT 24 May 09 01:40:17 PM PDT 24 286729865 ps
T865 /workspace/coverage/cover_reg_top/19.edn_intr_test.3877891751 May 09 01:40:21 PM PDT 24 May 09 01:40:23 PM PDT 24 37847355 ps
T866 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3919573422 May 09 01:40:19 PM PDT 24 May 09 01:40:21 PM PDT 24 31213709 ps
T234 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2365833934 May 09 01:39:56 PM PDT 24 May 09 01:40:01 PM PDT 24 209381330 ps
T867 /workspace/coverage/cover_reg_top/15.edn_tl_errors.3495672215 May 09 01:40:13 PM PDT 24 May 09 01:40:16 PM PDT 24 111494788 ps
T868 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3158871098 May 09 01:40:03 PM PDT 24 May 09 01:40:05 PM PDT 24 102381290 ps
T869 /workspace/coverage/cover_reg_top/49.edn_intr_test.119663470 May 09 01:40:30 PM PDT 24 May 09 01:40:32 PM PDT 24 49131669 ps
T870 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.924110496 May 09 01:40:19 PM PDT 24 May 09 01:40:23 PM PDT 24 58691056 ps
T871 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1607955284 May 09 01:39:54 PM PDT 24 May 09 01:39:56 PM PDT 24 13455811 ps
T212 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2228329643 May 09 01:39:49 PM PDT 24 May 09 01:39:51 PM PDT 24 27082539 ps
T872 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.4241720869 May 09 01:40:13 PM PDT 24 May 09 01:40:16 PM PDT 24 22958911 ps
T873 /workspace/coverage/cover_reg_top/9.edn_intr_test.2519148911 May 09 01:40:06 PM PDT 24 May 09 01:40:08 PM PDT 24 26210569 ps
T874 /workspace/coverage/cover_reg_top/8.edn_tl_errors.2165445395 May 09 01:39:58 PM PDT 24 May 09 01:40:03 PM PDT 24 34102009 ps
T875 /workspace/coverage/cover_reg_top/6.edn_intr_test.1627738510 May 09 01:39:57 PM PDT 24 May 09 01:40:00 PM PDT 24 17747803 ps
T876 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3244324789 May 09 01:40:05 PM PDT 24 May 09 01:40:07 PM PDT 24 89168538 ps
T877 /workspace/coverage/cover_reg_top/3.edn_csr_rw.3468558413 May 09 01:39:57 PM PDT 24 May 09 01:40:01 PM PDT 24 17104978 ps
T878 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2229363696 May 09 01:40:07 PM PDT 24 May 09 01:40:10 PM PDT 24 105978045 ps
T879 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2914435473 May 09 01:39:56 PM PDT 24 May 09 01:40:00 PM PDT 24 14976525 ps
T880 /workspace/coverage/cover_reg_top/20.edn_intr_test.862243496 May 09 01:40:17 PM PDT 24 May 09 01:40:20 PM PDT 24 32048077 ps
T881 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1733184987 May 09 01:40:12 PM PDT 24 May 09 01:40:16 PM PDT 24 87023850 ps
T882 /workspace/coverage/cover_reg_top/15.edn_intr_test.2869421550 May 09 01:40:11 PM PDT 24 May 09 01:40:14 PM PDT 24 15983244 ps
T883 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.498746403 May 09 01:40:07 PM PDT 24 May 09 01:40:10 PM PDT 24 72032904 ps
T884 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3932605274 May 09 01:40:08 PM PDT 24 May 09 01:40:11 PM PDT 24 114622856 ps
T885 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1542224255 May 09 01:39:56 PM PDT 24 May 09 01:40:00 PM PDT 24 193572853 ps
T886 /workspace/coverage/cover_reg_top/48.edn_intr_test.83515447 May 09 01:40:32 PM PDT 24 May 09 01:40:35 PM PDT 24 82841754 ps
T887 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1071279134 May 09 01:40:13 PM PDT 24 May 09 01:40:16 PM PDT 24 120066425 ps
T888 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3922477378 May 09 01:39:57 PM PDT 24 May 09 01:40:01 PM PDT 24 112920795 ps
T889 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3943290319 May 09 01:40:13 PM PDT 24 May 09 01:40:16 PM PDT 24 73226107 ps
T890 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3088355868 May 09 01:40:17 PM PDT 24 May 09 01:40:21 PM PDT 24 40535489 ps
T891 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3426138481 May 09 01:40:12 PM PDT 24 May 09 01:40:16 PM PDT 24 153193351 ps
T892 /workspace/coverage/cover_reg_top/39.edn_intr_test.2950307696 May 09 01:40:16 PM PDT 24 May 09 01:40:19 PM PDT 24 15249323 ps
T893 /workspace/coverage/cover_reg_top/10.edn_intr_test.4154525441 May 09 01:40:08 PM PDT 24 May 09 01:40:10 PM PDT 24 15840344 ps
T894 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4150450531 May 09 01:39:59 PM PDT 24 May 09 01:40:03 PM PDT 24 38309483 ps
T895 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2540885320 May 09 01:39:59 PM PDT 24 May 09 01:40:02 PM PDT 24 40681683 ps
T896 /workspace/coverage/cover_reg_top/18.edn_intr_test.2748959141 May 09 01:40:15 PM PDT 24 May 09 01:40:17 PM PDT 24 118917153 ps
T235 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3179322342 May 09 01:40:05 PM PDT 24 May 09 01:40:08 PM PDT 24 151641912 ps
T897 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3453011375 May 09 01:40:06 PM PDT 24 May 09 01:40:09 PM PDT 24 73592769 ps
T898 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1052254774 May 09 01:40:06 PM PDT 24 May 09 01:40:10 PM PDT 24 336172545 ps
T236 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.71450904 May 09 01:39:55 PM PDT 24 May 09 01:40:01 PM PDT 24 468627036 ps
T899 /workspace/coverage/cover_reg_top/44.edn_intr_test.3211799209 May 09 01:40:17 PM PDT 24 May 09 01:40:20 PM PDT 24 11338710 ps
T900 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3418905276 May 09 01:40:05 PM PDT 24 May 09 01:40:08 PM PDT 24 91697140 ps
T901 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1136047066 May 09 01:39:54 PM PDT 24 May 09 01:39:57 PM PDT 24 17928081 ps
T237 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1174158388 May 09 01:39:58 PM PDT 24 May 09 01:40:03 PM PDT 24 239091719 ps
T902 /workspace/coverage/cover_reg_top/2.edn_tl_errors.62862993 May 09 01:39:56 PM PDT 24 May 09 01:40:01 PM PDT 24 174303602 ps
T903 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1579814331 May 09 01:40:01 PM PDT 24 May 09 01:40:03 PM PDT 24 25527628 ps
T904 /workspace/coverage/cover_reg_top/16.edn_intr_test.1128965697 May 09 01:40:12 PM PDT 24 May 09 01:40:14 PM PDT 24 10562013 ps
T905 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.135534978 May 09 01:40:18 PM PDT 24 May 09 01:40:21 PM PDT 24 25136916 ps
T213 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3654454730 May 09 01:39:55 PM PDT 24 May 09 01:39:57 PM PDT 24 45234135 ps
T906 /workspace/coverage/cover_reg_top/13.edn_csr_rw.2604734691 May 09 01:40:09 PM PDT 24 May 09 01:40:11 PM PDT 24 16010270 ps
T907 /workspace/coverage/cover_reg_top/37.edn_intr_test.3143852784 May 09 01:40:16 PM PDT 24 May 09 01:40:18 PM PDT 24 107013923 ps
T908 /workspace/coverage/cover_reg_top/23.edn_intr_test.1948617509 May 09 01:40:16 PM PDT 24 May 09 01:40:19 PM PDT 24 37163228 ps
T909 /workspace/coverage/cover_reg_top/29.edn_intr_test.2110150610 May 09 01:40:22 PM PDT 24 May 09 01:40:24 PM PDT 24 29316527 ps
T214 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3641107908 May 09 01:40:06 PM PDT 24 May 09 01:40:07 PM PDT 24 77809086 ps
T910 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2700999224 May 09 01:39:46 PM PDT 24 May 09 01:39:50 PM PDT 24 52884618 ps
T911 /workspace/coverage/cover_reg_top/8.edn_intr_test.2915743067 May 09 01:40:09 PM PDT 24 May 09 01:40:11 PM PDT 24 17407256 ps
T912 /workspace/coverage/cover_reg_top/13.edn_intr_test.3416710635 May 09 01:40:08 PM PDT 24 May 09 01:40:10 PM PDT 24 15293086 ps
T913 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1824321119 May 09 01:39:58 PM PDT 24 May 09 01:40:02 PM PDT 24 191123095 ps
T914 /workspace/coverage/cover_reg_top/45.edn_intr_test.1142088197 May 09 01:40:20 PM PDT 24 May 09 01:40:22 PM PDT 24 31755580 ps
T915 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1652209586 May 09 01:39:56 PM PDT 24 May 09 01:40:01 PM PDT 24 164998663 ps
T916 /workspace/coverage/cover_reg_top/9.edn_csr_rw.901627041 May 09 01:40:13 PM PDT 24 May 09 01:40:16 PM PDT 24 54280289 ps
T917 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1589654924 May 09 01:40:18 PM PDT 24 May 09 01:40:21 PM PDT 24 34452580 ps
T918 /workspace/coverage/cover_reg_top/11.edn_csr_rw.30303970 May 09 01:40:05 PM PDT 24 May 09 01:40:07 PM PDT 24 25966090 ps
T919 /workspace/coverage/cover_reg_top/21.edn_intr_test.1722703229 May 09 01:40:21 PM PDT 24 May 09 01:40:23 PM PDT 24 17685628 ps
T920 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1549514133 May 09 01:39:49 PM PDT 24 May 09 01:39:54 PM PDT 24 278032535 ps
T921 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.4068509961 May 09 01:39:58 PM PDT 24 May 09 01:40:02 PM PDT 24 28021719 ps
T922 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2102856922 May 09 01:39:55 PM PDT 24 May 09 01:39:59 PM PDT 24 134647707 ps
T923 /workspace/coverage/cover_reg_top/43.edn_intr_test.232610553 May 09 01:40:17 PM PDT 24 May 09 01:40:20 PM PDT 24 28035901 ps
T924 /workspace/coverage/cover_reg_top/0.edn_tl_errors.979679715 May 09 01:39:47 PM PDT 24 May 09 01:39:53 PM PDT 24 422623998 ps
T215 /workspace/coverage/cover_reg_top/12.edn_csr_rw.3213218413 May 09 01:40:05 PM PDT 24 May 09 01:40:07 PM PDT 24 15878948 ps
T925 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3831567526 May 09 01:40:11 PM PDT 24 May 09 01:40:14 PM PDT 24 20884476 ps
T926 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3227987843 May 09 01:40:06 PM PDT 24 May 09 01:40:11 PM PDT 24 390053612 ps
T927 /workspace/coverage/cover_reg_top/28.edn_intr_test.1186947029 May 09 01:40:17 PM PDT 24 May 09 01:40:19 PM PDT 24 13001247 ps
T928 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.214777478 May 09 01:40:13 PM PDT 24 May 09 01:40:17 PM PDT 24 42294990 ps
T929 /workspace/coverage/cover_reg_top/14.edn_intr_test.20361752 May 09 01:40:06 PM PDT 24 May 09 01:40:08 PM PDT 24 15306445 ps
T930 /workspace/coverage/cover_reg_top/31.edn_intr_test.1388232032 May 09 01:40:21 PM PDT 24 May 09 01:40:24 PM PDT 24 59052964 ps
T931 /workspace/coverage/cover_reg_top/17.edn_intr_test.3519378203 May 09 01:40:11 PM PDT 24 May 09 01:40:13 PM PDT 24 30413630 ps
T932 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.580631078 May 09 01:39:57 PM PDT 24 May 09 01:40:01 PM PDT 24 21216267 ps
T933 /workspace/coverage/cover_reg_top/33.edn_intr_test.1473623771 May 09 01:40:19 PM PDT 24 May 09 01:40:21 PM PDT 24 14884678 ps
T934 /workspace/coverage/cover_reg_top/8.edn_csr_rw.2830300083 May 09 01:40:06 PM PDT 24 May 09 01:40:08 PM PDT 24 185663576 ps
T935 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4187521782 May 09 01:40:01 PM PDT 24 May 09 01:40:04 PM PDT 24 27840234 ps
T936 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2611311327 May 09 01:39:53 PM PDT 24 May 09 01:39:56 PM PDT 24 21461022 ps
T937 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1532550535 May 09 01:39:58 PM PDT 24 May 09 01:40:02 PM PDT 24 40293124 ps
T938 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1750221644 May 09 01:40:07 PM PDT 24 May 09 01:40:09 PM PDT 24 84459416 ps
T939 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2303698366 May 09 01:39:55 PM PDT 24 May 09 01:39:59 PM PDT 24 90530028 ps
T940 /workspace/coverage/cover_reg_top/26.edn_intr_test.4171533570 May 09 01:40:16 PM PDT 24 May 09 01:40:19 PM PDT 24 15696080 ps
T941 /workspace/coverage/cover_reg_top/30.edn_intr_test.4250377293 May 09 01:40:20 PM PDT 24 May 09 01:40:23 PM PDT 24 20641896 ps
T942 /workspace/coverage/cover_reg_top/38.edn_intr_test.4263083187 May 09 01:40:18 PM PDT 24 May 09 01:40:21 PM PDT 24 23010881 ps
T943 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1059479987 May 09 01:40:12 PM PDT 24 May 09 01:40:16 PM PDT 24 49793342 ps
T944 /workspace/coverage/cover_reg_top/9.edn_tl_errors.4059249447 May 09 01:40:12 PM PDT 24 May 09 01:40:16 PM PDT 24 273925894 ps
T945 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2113273700 May 09 01:39:46 PM PDT 24 May 09 01:39:49 PM PDT 24 144366273 ps
T946 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2547974477 May 09 01:39:59 PM PDT 24 May 09 01:40:04 PM PDT 24 51316622 ps
T947 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2455961579 May 09 01:40:00 PM PDT 24 May 09 01:40:04 PM PDT 24 43354422 ps
T948 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1874289110 May 09 01:40:13 PM PDT 24 May 09 01:40:17 PM PDT 24 55802525 ps
T949 /workspace/coverage/cover_reg_top/3.edn_tl_errors.182411033 May 09 01:39:58 PM PDT 24 May 09 01:40:03 PM PDT 24 231217897 ps
T950 /workspace/coverage/cover_reg_top/46.edn_intr_test.1653217592 May 09 01:40:21 PM PDT 24 May 09 01:40:23 PM PDT 24 17013077 ps
T951 /workspace/coverage/cover_reg_top/12.edn_tl_errors.375184590 May 09 01:40:09 PM PDT 24 May 09 01:40:12 PM PDT 24 23217427 ps
T952 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.4000267058 May 09 01:39:53 PM PDT 24 May 09 01:39:56 PM PDT 24 35818659 ps
T953 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1811747370 May 09 01:40:15 PM PDT 24 May 09 01:40:19 PM PDT 24 32133862 ps
T954 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.843394348 May 09 01:39:57 PM PDT 24 May 09 01:40:01 PM PDT 24 57049649 ps
T955 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3089197694 May 09 01:39:57 PM PDT 24 May 09 01:40:02 PM PDT 24 375255293 ps
T956 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.464894462 May 09 01:39:57 PM PDT 24 May 09 01:40:01 PM PDT 24 65304732 ps
T957 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3553899884 May 09 01:39:57 PM PDT 24 May 09 01:40:00 PM PDT 24 76560689 ps
T958 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2404165966 May 09 01:40:17 PM PDT 24 May 09 01:40:21 PM PDT 24 1003691380 ps
T959 /workspace/coverage/cover_reg_top/41.edn_intr_test.449130168 May 09 01:40:18 PM PDT 24 May 09 01:40:21 PM PDT 24 41583057 ps
T960 /workspace/coverage/cover_reg_top/47.edn_intr_test.2684025926 May 09 01:40:28 PM PDT 24 May 09 01:40:30 PM PDT 24 15620806 ps
T961 /workspace/coverage/cover_reg_top/12.edn_intr_test.3305410257 May 09 01:40:13 PM PDT 24 May 09 01:40:16 PM PDT 24 31492729 ps
T962 /workspace/coverage/cover_reg_top/36.edn_intr_test.1309215293 May 09 01:40:19 PM PDT 24 May 09 01:40:22 PM PDT 24 42865689 ps
T963 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3465493704 May 09 01:40:19 PM PDT 24 May 09 01:40:23 PM PDT 24 63520256 ps
T964 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3365173711 May 09 01:39:59 PM PDT 24 May 09 01:40:03 PM PDT 24 35601263 ps
T965 /workspace/coverage/cover_reg_top/22.edn_intr_test.1958927195 May 09 01:40:16 PM PDT 24 May 09 01:40:19 PM PDT 24 42766800 ps
T966 /workspace/coverage/cover_reg_top/40.edn_intr_test.1991720292 May 09 01:40:23 PM PDT 24 May 09 01:40:24 PM PDT 24 16680838 ps
T967 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1322823050 May 09 01:40:16 PM PDT 24 May 09 01:40:19 PM PDT 24 50246090 ps
T968 /workspace/coverage/cover_reg_top/35.edn_intr_test.2480628854 May 09 01:40:17 PM PDT 24 May 09 01:40:20 PM PDT 24 24039947 ps
T969 /workspace/coverage/cover_reg_top/11.edn_intr_test.1068109148 May 09 01:40:08 PM PDT 24 May 09 01:40:10 PM PDT 24 20415257 ps
T970 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2098421597 May 09 01:40:18 PM PDT 24 May 09 01:40:21 PM PDT 24 40702814 ps
T971 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4142128195 May 09 01:40:15 PM PDT 24 May 09 01:40:19 PM PDT 24 127843063 ps
T972 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.388470702 May 09 01:39:59 PM PDT 24 May 09 01:40:02 PM PDT 24 108109294 ps
T973 /workspace/coverage/cover_reg_top/7.edn_intr_test.30261602 May 09 01:40:01 PM PDT 24 May 09 01:40:03 PM PDT 24 16515745 ps
T216 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1060665618 May 09 01:39:58 PM PDT 24 May 09 01:40:02 PM PDT 24 254215010 ps
T974 /workspace/coverage/cover_reg_top/25.edn_intr_test.4278411309 May 09 01:40:20 PM PDT 24 May 09 01:40:23 PM PDT 24 45083811 ps
T975 /workspace/coverage/cover_reg_top/24.edn_intr_test.5290167 May 09 01:40:17 PM PDT 24 May 09 01:40:20 PM PDT 24 22681961 ps
T217 /workspace/coverage/cover_reg_top/16.edn_csr_rw.411008541 May 09 01:40:13 PM PDT 24 May 09 01:40:16 PM PDT 24 14865163 ps

Test location /workspace/coverage/default/113.edn_genbits.2823053875
Short name T9
Test name
Test status
Simulation time 86886140 ps
CPU time 2.9 seconds
Started May 09 02:28:17 PM PDT 24
Finished May 09 02:28:25 PM PDT 24
Peak memory 215148 kb
Host smart-c76e4e3c-5b89-4cbd-baaa-fd65218bcd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823053875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2823053875
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.4156705191
Short name T41
Test name
Test status
Simulation time 57427493574 ps
CPU time 351.18 seconds
Started May 09 02:25:31 PM PDT 24
Finished May 09 02:31:24 PM PDT 24
Peak memory 217888 kb
Host smart-38b12e97-0812-4a5d-8fad-abb99d202d0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156705191 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.4156705191
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.edn_sec_cm.856176778
Short name T15
Test name
Test status
Simulation time 244062715 ps
CPU time 4.26 seconds
Started May 09 02:25:32 PM PDT 24
Finished May 09 02:25:38 PM PDT 24
Peak memory 239072 kb
Host smart-e4d06b96-1bb6-4113-b7a2-43fe658a736f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856176778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.856176778
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/25.edn_alert.2637605155
Short name T29
Test name
Test status
Simulation time 31899398 ps
CPU time 1.36 seconds
Started May 09 02:26:06 PM PDT 24
Finished May 09 02:26:10 PM PDT 24
Peak memory 215576 kb
Host smart-1adbd882-65c1-4178-8622-73b212f8dcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637605155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2637605155
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.336054398
Short name T10
Test name
Test status
Simulation time 20606886 ps
CPU time 0.99 seconds
Started May 09 02:26:36 PM PDT 24
Finished May 09 02:26:38 PM PDT 24
Peak memory 217892 kb
Host smart-9de3beca-872e-4080-81e1-c521f9ec39f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336054398 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.336054398
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.674121786
Short name T16
Test name
Test status
Simulation time 19147955 ps
CPU time 1.18 seconds
Started May 09 02:26:53 PM PDT 24
Finished May 09 02:26:58 PM PDT 24
Peak memory 223900 kb
Host smart-75cddb52-3cca-44cd-a850-ea03595a1fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674121786 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.674121786
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1021864350
Short name T40
Test name
Test status
Simulation time 217571802276 ps
CPU time 1294.2 seconds
Started May 09 02:26:51 PM PDT 24
Finished May 09 02:48:28 PM PDT 24
Peak memory 221664 kb
Host smart-6bd4dbe5-481c-4ca7-84bb-f3a3f67f30c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021864350 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1021864350
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.edn_alert.1997709049
Short name T86
Test name
Test status
Simulation time 55462926 ps
CPU time 1.24 seconds
Started May 09 02:26:08 PM PDT 24
Finished May 09 02:26:12 PM PDT 24
Peak memory 215616 kb
Host smart-2648b46e-b481-4f9a-be75-362e1d1a77ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997709049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1997709049
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/1.edn_regwen.3403317060
Short name T256
Test name
Test status
Simulation time 42058691 ps
CPU time 0.93 seconds
Started May 09 02:25:45 PM PDT 24
Finished May 09 02:25:49 PM PDT 24
Peak memory 206956 kb
Host smart-d594a019-35b5-4f53-b81e-c21a6e227931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403317060 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3403317060
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/42.edn_alert.404683578
Short name T30
Test name
Test status
Simulation time 257967647 ps
CPU time 1.23 seconds
Started May 09 02:27:11 PM PDT 24
Finished May 09 02:27:18 PM PDT 24
Peak memory 215544 kb
Host smart-7c1a02b3-115f-473c-aa0f-c43892637402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404683578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.404683578
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.71450904
Short name T236
Test name
Test status
Simulation time 468627036 ps
CPU time 3.42 seconds
Started May 09 01:39:55 PM PDT 24
Finished May 09 01:40:01 PM PDT 24
Peak memory 214532 kb
Host smart-4f061961-74a6-48ca-a4fb-0e03424fcd9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71450904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.71450904
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/default/46.edn_alert.2469336242
Short name T248
Test name
Test status
Simulation time 23848014 ps
CPU time 1.2 seconds
Started May 09 02:27:21 PM PDT 24
Finished May 09 02:27:26 PM PDT 24
Peak memory 215508 kb
Host smart-07feec72-2e8c-42e5-93c9-93e3367dfa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469336242 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2469336242
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.681100026
Short name T71
Test name
Test status
Simulation time 116361955 ps
CPU time 1.13 seconds
Started May 09 02:27:22 PM PDT 24
Finished May 09 02:27:28 PM PDT 24
Peak memory 216936 kb
Host smart-a4eedac5-79b5-498c-87aa-597cf5c5eaa3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681100026 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.681100026
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_disable.952999453
Short name T165
Test name
Test status
Simulation time 34741828 ps
CPU time 0.84 seconds
Started May 09 02:25:51 PM PDT 24
Finished May 09 02:25:56 PM PDT 24
Peak memory 216144 kb
Host smart-826ddda4-b378-4e70-aaf5-c68bfc53e0ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952999453 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.952999453
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.876697629
Short name T203
Test name
Test status
Simulation time 44169206 ps
CPU time 0.87 seconds
Started May 09 01:39:48 PM PDT 24
Finished May 09 01:39:50 PM PDT 24
Peak memory 206288 kb
Host smart-bf02595e-f580-434d-a1bf-3269735c2637
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876697629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.876697629
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/default/28.edn_disable.2870127662
Short name T120
Test name
Test status
Simulation time 22563606 ps
CPU time 0.89 seconds
Started May 09 02:26:26 PM PDT 24
Finished May 09 02:26:28 PM PDT 24
Peak memory 216248 kb
Host smart-d521051a-44f0-4931-8142-6d37f022c660
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870127662 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2870127662
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.2191044858
Short name T770
Test name
Test status
Simulation time 62275011 ps
CPU time 1.45 seconds
Started May 09 02:25:56 PM PDT 24
Finished May 09 02:26:00 PM PDT 24
Peak memory 216784 kb
Host smart-7eb0e960-8079-43cc-b287-4c559de51d76
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191044858 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.2191044858
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_disable.4251475451
Short name T158
Test name
Test status
Simulation time 14013239 ps
CPU time 0.94 seconds
Started May 09 02:25:57 PM PDT 24
Finished May 09 02:26:01 PM PDT 24
Peak memory 216236 kb
Host smart-d858fe95-fa6a-4558-8456-dacaa7da74e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251475451 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.4251475451
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/9.edn_genbits.2458879003
Short name T66
Test name
Test status
Simulation time 62273521 ps
CPU time 1.52 seconds
Started May 09 02:25:43 PM PDT 24
Finished May 09 02:25:46 PM PDT 24
Peak memory 218400 kb
Host smart-47cfbba3-24f2-4248-a218-214e9ab18af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458879003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2458879003
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3491383005
Short name T301
Test name
Test status
Simulation time 100612328 ps
CPU time 1.12 seconds
Started May 09 02:29:07 PM PDT 24
Finished May 09 02:29:11 PM PDT 24
Peak memory 219196 kb
Host smart-8c3b9e8c-a978-4a47-ac55-0f4ae24e044f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491383005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3491383005
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.4289987410
Short name T96
Test name
Test status
Simulation time 156361293 ps
CPU time 1.25 seconds
Started May 09 02:26:39 PM PDT 24
Finished May 09 02:26:44 PM PDT 24
Peak memory 215408 kb
Host smart-5ca36031-b340-4a52-af40-19139521df2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289987410 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.4289987410
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/92.edn_genbits.472599028
Short name T3
Test name
Test status
Simulation time 61635652 ps
CPU time 1.19 seconds
Started May 09 02:28:08 PM PDT 24
Finished May 09 02:28:14 PM PDT 24
Peak memory 216844 kb
Host smart-16c3fd55-5737-4628-8a5a-71e03c5e8df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472599028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.472599028
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2040734912
Short name T49
Test name
Test status
Simulation time 47522957 ps
CPU time 1.2 seconds
Started May 09 02:26:07 PM PDT 24
Finished May 09 02:26:11 PM PDT 24
Peak memory 215608 kb
Host smart-4115148a-9c0d-4ea4-9ee3-2a75b3da98f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040734912 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2040734912
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/26.edn_disable.4247530636
Short name T114
Test name
Test status
Simulation time 11958186 ps
CPU time 0.91 seconds
Started May 09 02:26:16 PM PDT 24
Finished May 09 02:26:19 PM PDT 24
Peak memory 215428 kb
Host smart-9216e5b9-7120-4454-8723-1abf4d076239
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247530636 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.4247530636
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/8.edn_intr.3929579917
Short name T36
Test name
Test status
Simulation time 31618848 ps
CPU time 0.85 seconds
Started May 09 02:25:45 PM PDT 24
Finished May 09 02:25:48 PM PDT 24
Peak memory 215524 kb
Host smart-d0d4fb53-417b-4541-a3f3-3adbfea8c19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929579917 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3929579917
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2224252843
Short name T108
Test name
Test status
Simulation time 64170991 ps
CPU time 1.08 seconds
Started May 09 02:26:28 PM PDT 24
Finished May 09 02:26:31 PM PDT 24
Peak memory 219368 kb
Host smart-f09115f8-4725-4b44-a6f0-b9c946d9469e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224252843 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2224252843
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_alert.653490622
Short name T177
Test name
Test status
Simulation time 93683494 ps
CPU time 1.31 seconds
Started May 09 02:26:14 PM PDT 24
Finished May 09 02:26:18 PM PDT 24
Peak memory 215560 kb
Host smart-96e57131-9aa9-41fe-ae94-e9aa13d8d8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653490622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.653490622
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.639267578
Short name T262
Test name
Test status
Simulation time 203444910960 ps
CPU time 618.71 seconds
Started May 09 02:27:35 PM PDT 24
Finished May 09 02:37:58 PM PDT 24
Peak memory 221036 kb
Host smart-aa30fd2d-3096-46be-904e-c602fcc89367
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639267578 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.639267578
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_disable.1931432085
Short name T119
Test name
Test status
Simulation time 88548666 ps
CPU time 0.81 seconds
Started May 09 02:26:54 PM PDT 24
Finished May 09 02:26:58 PM PDT 24
Peak memory 215244 kb
Host smart-bfc71207-2a18-4c80-b3ee-e9251f09989d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931432085 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1931432085
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.3577860393
Short name T8
Test name
Test status
Simulation time 51718822 ps
CPU time 1.26 seconds
Started May 09 02:25:48 PM PDT 24
Finished May 09 02:25:53 PM PDT 24
Peak memory 229592 kb
Host smart-c3516b6c-41ab-404f-b018-10bfb413689d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577860393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3577860393
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.1987691528
Short name T478
Test name
Test status
Simulation time 25213564 ps
CPU time 0.94 seconds
Started May 09 02:25:49 PM PDT 24
Finished May 09 02:25:54 PM PDT 24
Peak memory 215680 kb
Host smart-d05b243c-1b93-49f0-8dd6-e2d29843c74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987691528 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1987691528
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/0.edn_disable.325229963
Short name T662
Test name
Test status
Simulation time 147336979 ps
CPU time 0.88 seconds
Started May 09 02:25:17 PM PDT 24
Finished May 09 02:25:19 PM PDT 24
Peak memory 216116 kb
Host smart-4e81e30c-02af-45af-88fd-f351298a21c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325229963 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.325229963
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1639950366
Short name T531
Test name
Test status
Simulation time 90703275 ps
CPU time 1.14 seconds
Started May 09 02:25:38 PM PDT 24
Finished May 09 02:25:40 PM PDT 24
Peak memory 216852 kb
Host smart-7f8b2722-00f1-4ba5-b5f6-0d116ef19984
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639950366 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1639950366
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2230850238
Short name T91
Test name
Test status
Simulation time 111368560 ps
CPU time 1.18 seconds
Started May 09 02:25:56 PM PDT 24
Finished May 09 02:26:00 PM PDT 24
Peak memory 216716 kb
Host smart-1b8abe1c-180a-450f-8e45-03f00fc82134
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230850238 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2230850238
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_disable.2712654821
Short name T629
Test name
Test status
Simulation time 14031216 ps
CPU time 0.89 seconds
Started May 09 02:26:07 PM PDT 24
Finished May 09 02:26:10 PM PDT 24
Peak memory 215480 kb
Host smart-f743d134-5d98-4833-8e19-1c84fe9aa01f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712654821 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2712654821
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable.2329914789
Short name T166
Test name
Test status
Simulation time 17425857 ps
CPU time 0.84 seconds
Started May 09 02:26:04 PM PDT 24
Finished May 09 02:26:08 PM PDT 24
Peak memory 216220 kb
Host smart-d0dcde7e-e053-41c8-857b-4cec1adb6bd3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329914789 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2329914789
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable.3174085077
Short name T138
Test name
Test status
Simulation time 87629651 ps
CPU time 0.83 seconds
Started May 09 02:26:52 PM PDT 24
Finished May 09 02:26:56 PM PDT 24
Peak memory 216212 kb
Host smart-01d6dff2-a415-4e22-b39f-193a254ec2ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174085077 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3174085077
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/14.edn_genbits.3654916895
Short name T21
Test name
Test status
Simulation time 79980526 ps
CPU time 1.33 seconds
Started May 09 02:26:00 PM PDT 24
Finished May 09 02:26:03 PM PDT 24
Peak memory 219148 kb
Host smart-ab51c95a-64a7-445e-a118-5e3e8c0fc282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654916895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3654916895
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.3824390752
Short name T50
Test name
Test status
Simulation time 40131167 ps
CPU time 0.86 seconds
Started May 09 02:25:43 PM PDT 24
Finished May 09 02:25:46 PM PDT 24
Peak memory 206324 kb
Host smart-da6e5891-1485-4f44-9fbe-4836d57742a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824390752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3824390752
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/165.edn_genbits.3074340024
Short name T463
Test name
Test status
Simulation time 69489435 ps
CPU time 1.57 seconds
Started May 09 02:28:39 PM PDT 24
Finished May 09 02:28:44 PM PDT 24
Peak memory 217544 kb
Host smart-a24f94fb-8a26-4402-b5ce-32de2babbf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074340024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3074340024
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1645621889
Short name T264
Test name
Test status
Simulation time 120486680 ps
CPU time 1.3 seconds
Started May 09 02:28:19 PM PDT 24
Finished May 09 02:28:24 PM PDT 24
Peak memory 218556 kb
Host smart-cce0f2b8-bbf1-485b-9839-d20180c3ca2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645621889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1645621889
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.82272328
Short name T75
Test name
Test status
Simulation time 27359965 ps
CPU time 0.97 seconds
Started May 09 02:25:14 PM PDT 24
Finished May 09 02:25:17 PM PDT 24
Peak memory 215832 kb
Host smart-7e789a86-cee2-44c4-ad5e-86f6e0162c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82272328 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.82272328
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/29.edn_alert.3030459471
Short name T176
Test name
Test status
Simulation time 136623651 ps
CPU time 1.27 seconds
Started May 09 02:26:27 PM PDT 24
Finished May 09 02:26:31 PM PDT 24
Peak memory 215708 kb
Host smart-efe9ed3f-0bba-45f0-a53f-9353086792ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030459471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3030459471
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert.1995191079
Short name T592
Test name
Test status
Simulation time 27420168 ps
CPU time 1.25 seconds
Started May 09 02:26:51 PM PDT 24
Finished May 09 02:26:55 PM PDT 24
Peak memory 215564 kb
Host smart-eec79b64-2b85-43f3-8b75-7e851ef49196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995191079 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1995191079
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/41.edn_genbits.4226207357
Short name T287
Test name
Test status
Simulation time 53248377 ps
CPU time 2.02 seconds
Started May 09 02:27:04 PM PDT 24
Finished May 09 02:27:11 PM PDT 24
Peak memory 217080 kb
Host smart-14f19553-ae17-46aa-974d-64e07293714b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226207357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.4226207357
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2228329643
Short name T212
Test name
Test status
Simulation time 27082539 ps
CPU time 0.94 seconds
Started May 09 01:39:49 PM PDT 24
Finished May 09 01:39:51 PM PDT 24
Peak memory 206360 kb
Host smart-a74fee5a-894d-4fb5-a1b3-108d4310eb13
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228329643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2228329643
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.4060273889
Short name T260
Test name
Test status
Simulation time 44915961 ps
CPU time 1.17 seconds
Started May 09 02:28:19 PM PDT 24
Finished May 09 02:28:24 PM PDT 24
Peak memory 218312 kb
Host smart-12ee6db6-dd25-430a-a830-1a195a828b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060273889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.4060273889
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.3820676759
Short name T795
Test name
Test status
Simulation time 288957996 ps
CPU time 1.37 seconds
Started May 09 02:28:23 PM PDT 24
Finished May 09 02:28:27 PM PDT 24
Peak memory 217052 kb
Host smart-e866a7c6-2ce4-4bc0-935b-c16e2fd992f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820676759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3820676759
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3373995238
Short name T749
Test name
Test status
Simulation time 40020897 ps
CPU time 1.58 seconds
Started May 09 02:28:14 PM PDT 24
Finished May 09 02:28:20 PM PDT 24
Peak memory 216964 kb
Host smart-324a82e8-98dc-45b9-9ff6-a9ff60614dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373995238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3373995238
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/120.edn_genbits.1113450088
Short name T563
Test name
Test status
Simulation time 78335811 ps
CPU time 1.41 seconds
Started May 09 02:28:25 PM PDT 24
Finished May 09 02:28:28 PM PDT 24
Peak memory 216980 kb
Host smart-d42146a6-d789-41c8-93dc-9ba79a69188a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113450088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1113450088
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.926960655
Short name T68
Test name
Test status
Simulation time 26038646 ps
CPU time 1.35 seconds
Started May 09 02:28:40 PM PDT 24
Finished May 09 02:28:45 PM PDT 24
Peak memory 219720 kb
Host smart-a4adcf0c-9d12-48af-9b6d-c5ea30045966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926960655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.926960655
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.1007557487
Short name T729
Test name
Test status
Simulation time 39514088 ps
CPU time 1.49 seconds
Started May 09 02:28:41 PM PDT 24
Finished May 09 02:28:46 PM PDT 24
Peak memory 219108 kb
Host smart-106af93b-1519-4751-8038-7c6040acf5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007557487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1007557487
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.2790632138
Short name T266
Test name
Test status
Simulation time 62406491 ps
CPU time 1 seconds
Started May 09 02:28:39 PM PDT 24
Finished May 09 02:28:43 PM PDT 24
Peak memory 216952 kb
Host smart-bc23831d-cb46-4f7c-8626-fb7a8061edb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790632138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2790632138
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_genbits.264980518
Short name T279
Test name
Test status
Simulation time 55602319 ps
CPU time 1.82 seconds
Started May 09 02:25:54 PM PDT 24
Finished May 09 02:25:59 PM PDT 24
Peak memory 218248 kb
Host smart-31ab73c2-822e-4b93-8b33-6caf248160b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264980518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.264980518
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1401336942
Short name T246
Test name
Test status
Simulation time 93424044 ps
CPU time 1.24 seconds
Started May 09 02:25:31 PM PDT 24
Finished May 09 02:25:34 PM PDT 24
Peak memory 215536 kb
Host smart-8a4ac553-1384-4491-ba68-fd9222f67bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401336942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1401336942
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/200.edn_genbits.2294814551
Short name T528
Test name
Test status
Simulation time 155078135 ps
CPU time 1.82 seconds
Started May 09 02:29:02 PM PDT 24
Finished May 09 02:29:08 PM PDT 24
Peak memory 218488 kb
Host smart-f8d412b9-2b55-4ac2-ad7f-4980273de86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294814551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2294814551
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/270.edn_genbits.3842733081
Short name T286
Test name
Test status
Simulation time 274870245 ps
CPU time 2.63 seconds
Started May 09 02:29:11 PM PDT 24
Finished May 09 02:29:19 PM PDT 24
Peak memory 219904 kb
Host smart-3c8c918b-104f-43ff-ad43-bed256b478e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842733081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3842733081
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_alert.2084927664
Short name T250
Test name
Test status
Simulation time 159137472 ps
CPU time 1.33 seconds
Started May 09 02:26:37 PM PDT 24
Finished May 09 02:26:40 PM PDT 24
Peak memory 215564 kb
Host smart-edb8adde-edb0-4c2b-978c-550ba84f2b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084927664 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2084927664
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert.2694952769
Short name T173
Test name
Test status
Simulation time 38699617 ps
CPU time 1.22 seconds
Started May 09 02:25:37 PM PDT 24
Finished May 09 02:25:40 PM PDT 24
Peak memory 215808 kb
Host smart-6c5a6c32-db92-4c29-836d-e5676f190bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694952769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2694952769
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/6.edn_regwen.3268688371
Short name T242
Test name
Test status
Simulation time 28720328 ps
CPU time 0.98 seconds
Started May 09 02:25:39 PM PDT 24
Finished May 09 02:25:41 PM PDT 24
Peak memory 206912 kb
Host smart-bb178e5e-2f66-43ea-afb5-33bc8b3b44db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268688371 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3268688371
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/17.edn_intr.1667499742
Short name T79
Test name
Test status
Simulation time 49322128 ps
CPU time 0.85 seconds
Started May 09 02:26:02 PM PDT 24
Finished May 09 02:26:05 PM PDT 24
Peak memory 215408 kb
Host smart-36142d16-845f-45ec-a67a-102b4a9f8fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667499742 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1667499742
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/264.edn_genbits.2437849638
Short name T13
Test name
Test status
Simulation time 33294310 ps
CPU time 1.52 seconds
Started May 09 02:29:08 PM PDT 24
Finished May 09 02:29:14 PM PDT 24
Peak memory 219340 kb
Host smart-00e8fb8a-b274-4099-82a2-de924706170a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437849638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2437849638
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2113273700
Short name T945
Test name
Test status
Simulation time 144366273 ps
CPU time 1.16 seconds
Started May 09 01:39:46 PM PDT 24
Finished May 09 01:39:49 PM PDT 24
Peak memory 206148 kb
Host smart-ad9cef8b-6829-4056-b024-02a8d42946e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113273700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2113273700
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1549514133
Short name T920
Test name
Test status
Simulation time 278032535 ps
CPU time 3.53 seconds
Started May 09 01:39:49 PM PDT 24
Finished May 09 01:39:54 PM PDT 24
Peak memory 206356 kb
Host smart-49c1a53c-d562-4a30-ba49-27e09c3c5e79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549514133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1549514133
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2102856922
Short name T922
Test name
Test status
Simulation time 134647707 ps
CPU time 1.57 seconds
Started May 09 01:39:55 PM PDT 24
Finished May 09 01:39:59 PM PDT 24
Peak memory 217564 kb
Host smart-587f4377-3c0d-4465-a1f1-17ddb3b94cba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102856922 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2102856922
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.476362905
Short name T858
Test name
Test status
Simulation time 14126607 ps
CPU time 0.9 seconds
Started May 09 01:39:46 PM PDT 24
Finished May 09 01:39:50 PM PDT 24
Peak memory 206112 kb
Host smart-4c4d8011-f41b-4ba5-a497-28d62e8b3e0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476362905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.476362905
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.388470702
Short name T972
Test name
Test status
Simulation time 108109294 ps
CPU time 1.26 seconds
Started May 09 01:39:59 PM PDT 24
Finished May 09 01:40:02 PM PDT 24
Peak memory 206368 kb
Host smart-1b894860-e965-45e1-9171-17ff218bcc38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388470702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.388470702
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.979679715
Short name T924
Test name
Test status
Simulation time 422623998 ps
CPU time 4.06 seconds
Started May 09 01:39:47 PM PDT 24
Finished May 09 01:39:53 PM PDT 24
Peak memory 214404 kb
Host smart-f09b263e-b4d5-4484-818a-9316079608e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979679715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.979679715
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2700999224
Short name T910
Test name
Test status
Simulation time 52884618 ps
CPU time 1.77 seconds
Started May 09 01:39:46 PM PDT 24
Finished May 09 01:39:50 PM PDT 24
Peak memory 206604 kb
Host smart-6f242d10-cf02-422e-bda7-e8b09515b815
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700999224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2700999224
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1532550535
Short name T937
Test name
Test status
Simulation time 40293124 ps
CPU time 1.11 seconds
Started May 09 01:39:58 PM PDT 24
Finished May 09 01:40:02 PM PDT 24
Peak memory 206412 kb
Host smart-a835a190-530e-48e0-97ea-9d231d498bda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532550535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1532550535
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1542224255
Short name T885
Test name
Test status
Simulation time 193572853 ps
CPU time 1.97 seconds
Started May 09 01:39:56 PM PDT 24
Finished May 09 01:40:00 PM PDT 24
Peak memory 206288 kb
Host smart-25263f8e-bb27-4900-9e83-224c74aff159
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542224255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1542224255
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3654454730
Short name T213
Test name
Test status
Simulation time 45234135 ps
CPU time 0.88 seconds
Started May 09 01:39:55 PM PDT 24
Finished May 09 01:39:57 PM PDT 24
Peak memory 206368 kb
Host smart-57abf815-5d66-4899-bbb8-b7bf71435a16
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654454730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3654454730
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4150450531
Short name T894
Test name
Test status
Simulation time 38309483 ps
CPU time 1.44 seconds
Started May 09 01:39:59 PM PDT 24
Finished May 09 01:40:03 PM PDT 24
Peak memory 214620 kb
Host smart-af8dde4b-f7ad-4277-b7dc-d76c313392f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150450531 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.4150450531
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1569514465
Short name T210
Test name
Test status
Simulation time 39552746 ps
CPU time 0.89 seconds
Started May 09 01:39:54 PM PDT 24
Finished May 09 01:39:57 PM PDT 24
Peak memory 206324 kb
Host smart-a866df78-4cbd-4f2e-be4c-ec4fde30e45d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569514465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1569514465
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1347569626
Short name T856
Test name
Test status
Simulation time 192429889 ps
CPU time 0.86 seconds
Started May 09 01:39:57 PM PDT 24
Finished May 09 01:40:00 PM PDT 24
Peak memory 206208 kb
Host smart-1660e6ca-09a2-451e-b140-cd835dd4377b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347569626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1347569626
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1136047066
Short name T901
Test name
Test status
Simulation time 17928081 ps
CPU time 1.14 seconds
Started May 09 01:39:54 PM PDT 24
Finished May 09 01:39:57 PM PDT 24
Peak memory 206368 kb
Host smart-60e691e9-488e-4ed2-930d-55221339bb4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136047066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1136047066
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2631860372
Short name T848
Test name
Test status
Simulation time 187055284 ps
CPU time 2.26 seconds
Started May 09 01:39:56 PM PDT 24
Finished May 09 01:40:00 PM PDT 24
Peak memory 214528 kb
Host smart-48ece394-77cd-42cd-940a-b599d6f426f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631860372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2631860372
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1824321119
Short name T913
Test name
Test status
Simulation time 191123095 ps
CPU time 1.6 seconds
Started May 09 01:39:58 PM PDT 24
Finished May 09 01:40:02 PM PDT 24
Peak memory 214568 kb
Host smart-3c59b1c5-5f1d-4dd9-a79c-77756e4a1641
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824321119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1824321119
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.914102894
Short name T853
Test name
Test status
Simulation time 40526443 ps
CPU time 1.02 seconds
Started May 09 01:40:08 PM PDT 24
Finished May 09 01:40:10 PM PDT 24
Peak memory 206384 kb
Host smart-2696cde0-7f94-4e00-9314-25dd6e509177
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914102894 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.914102894
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3641107908
Short name T214
Test name
Test status
Simulation time 77809086 ps
CPU time 0.9 seconds
Started May 09 01:40:06 PM PDT 24
Finished May 09 01:40:07 PM PDT 24
Peak memory 206276 kb
Host smart-05f25d83-33df-43c9-acac-4c012b282c3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641107908 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3641107908
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.4154525441
Short name T893
Test name
Test status
Simulation time 15840344 ps
CPU time 0.92 seconds
Started May 09 01:40:08 PM PDT 24
Finished May 09 01:40:10 PM PDT 24
Peak memory 206288 kb
Host smart-a66b184e-d5f5-418c-95a0-75571610fb82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154525441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.4154525441
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2190456952
Short name T207
Test name
Test status
Simulation time 30763669 ps
CPU time 1.1 seconds
Started May 09 01:40:06 PM PDT 24
Finished May 09 01:40:08 PM PDT 24
Peak memory 206336 kb
Host smart-3c389ef4-1ad6-4597-9045-3c1be35e7aee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190456952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2190456952
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3932605274
Short name T884
Test name
Test status
Simulation time 114622856 ps
CPU time 2.39 seconds
Started May 09 01:40:08 PM PDT 24
Finished May 09 01:40:11 PM PDT 24
Peak memory 214544 kb
Host smart-e6ad232c-9a5b-4c4b-8832-572a244ec7b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932605274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3932605274
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1052254774
Short name T898
Test name
Test status
Simulation time 336172545 ps
CPU time 2.38 seconds
Started May 09 01:40:06 PM PDT 24
Finished May 09 01:40:10 PM PDT 24
Peak memory 206620 kb
Host smart-bc80981e-27cf-415f-92fc-c3fb8871d971
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052254774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1052254774
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.498746403
Short name T883
Test name
Test status
Simulation time 72032904 ps
CPU time 1.61 seconds
Started May 09 01:40:07 PM PDT 24
Finished May 09 01:40:10 PM PDT 24
Peak memory 219184 kb
Host smart-4ac12d6c-1ad7-48e0-a726-840f46dfa848
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498746403 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.498746403
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.30303970
Short name T918
Test name
Test status
Simulation time 25966090 ps
CPU time 0.95 seconds
Started May 09 01:40:05 PM PDT 24
Finished May 09 01:40:07 PM PDT 24
Peak memory 206248 kb
Host smart-b56a3293-746f-4d3c-96dc-8f6f4b922802
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30303970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.30303970
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1068109148
Short name T969
Test name
Test status
Simulation time 20415257 ps
CPU time 0.86 seconds
Started May 09 01:40:08 PM PDT 24
Finished May 09 01:40:10 PM PDT 24
Peak memory 206008 kb
Host smart-33771cf6-f1b1-4fd9-8fcb-51bea42b967c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068109148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1068109148
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3943290319
Short name T889
Test name
Test status
Simulation time 73226107 ps
CPU time 1.49 seconds
Started May 09 01:40:13 PM PDT 24
Finished May 09 01:40:16 PM PDT 24
Peak memory 206348 kb
Host smart-78553b1a-035f-4e53-b8a2-caf0fc2a4d57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943290319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3943290319
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3227987843
Short name T926
Test name
Test status
Simulation time 390053612 ps
CPU time 3.93 seconds
Started May 09 01:40:06 PM PDT 24
Finished May 09 01:40:11 PM PDT 24
Peak memory 214540 kb
Host smart-2c75611c-cc77-4deb-82ce-7f2e22efae94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227987843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3227987843
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1874289110
Short name T948
Test name
Test status
Simulation time 55802525 ps
CPU time 1.86 seconds
Started May 09 01:40:13 PM PDT 24
Finished May 09 01:40:17 PM PDT 24
Peak memory 206400 kb
Host smart-3dfc576d-0180-4d21-b34b-c0db682e57f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874289110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1874289110
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3130588892
Short name T840
Test name
Test status
Simulation time 84804010 ps
CPU time 1.32 seconds
Started May 09 01:40:08 PM PDT 24
Finished May 09 01:40:10 PM PDT 24
Peak memory 214648 kb
Host smart-f3e966f1-ef2d-472a-9416-c918e4739a1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130588892 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3130588892
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3213218413
Short name T215
Test name
Test status
Simulation time 15878948 ps
CPU time 0.9 seconds
Started May 09 01:40:05 PM PDT 24
Finished May 09 01:40:07 PM PDT 24
Peak memory 206356 kb
Host smart-cda74e73-b07c-4c30-8659-0a21e6cdb5c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213218413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3213218413
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3305410257
Short name T961
Test name
Test status
Simulation time 31492729 ps
CPU time 0.78 seconds
Started May 09 01:40:13 PM PDT 24
Finished May 09 01:40:16 PM PDT 24
Peak memory 205980 kb
Host smart-9f0815d1-22dc-4715-ac95-299044c74f8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305410257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3305410257
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1750221644
Short name T938
Test name
Test status
Simulation time 84459416 ps
CPU time 1.2 seconds
Started May 09 01:40:07 PM PDT 24
Finished May 09 01:40:09 PM PDT 24
Peak memory 206336 kb
Host smart-c2ce6377-d207-46be-bf6b-3f324a63a38b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750221644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1750221644
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.375184590
Short name T951
Test name
Test status
Simulation time 23217427 ps
CPU time 1.51 seconds
Started May 09 01:40:09 PM PDT 24
Finished May 09 01:40:12 PM PDT 24
Peak memory 214600 kb
Host smart-b3a878df-0f43-433a-89be-bac0843dc2f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375184590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.375184590
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3453011375
Short name T897
Test name
Test status
Simulation time 73592769 ps
CPU time 1.47 seconds
Started May 09 01:40:06 PM PDT 24
Finished May 09 01:40:09 PM PDT 24
Peak memory 206764 kb
Host smart-e307a4c3-0245-43fc-a0de-b1dcd071449a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453011375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3453011375
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3244324789
Short name T876
Test name
Test status
Simulation time 89168538 ps
CPU time 1.4 seconds
Started May 09 01:40:05 PM PDT 24
Finished May 09 01:40:07 PM PDT 24
Peak memory 214564 kb
Host smart-7e7e0ac9-4d0b-495b-bf6a-57339b3fa31b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244324789 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3244324789
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2604734691
Short name T906
Test name
Test status
Simulation time 16010270 ps
CPU time 0.86 seconds
Started May 09 01:40:09 PM PDT 24
Finished May 09 01:40:11 PM PDT 24
Peak memory 206328 kb
Host smart-cfb2b4b1-1ce3-45e2-b975-402c61edcdf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604734691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2604734691
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3416710635
Short name T912
Test name
Test status
Simulation time 15293086 ps
CPU time 0.83 seconds
Started May 09 01:40:08 PM PDT 24
Finished May 09 01:40:10 PM PDT 24
Peak memory 206208 kb
Host smart-a790aeba-2901-4cf4-95a8-e6e973b501fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416710635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3416710635
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2229363696
Short name T878
Test name
Test status
Simulation time 105978045 ps
CPU time 1.35 seconds
Started May 09 01:40:07 PM PDT 24
Finished May 09 01:40:10 PM PDT 24
Peak memory 206380 kb
Host smart-e53ec369-a50c-41f7-bf0c-31cd6e385de7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229363696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2229363696
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.4181469253
Short name T850
Test name
Test status
Simulation time 105782375 ps
CPU time 2.75 seconds
Started May 09 01:40:11 PM PDT 24
Finished May 09 01:40:16 PM PDT 24
Peak memory 214548 kb
Host smart-3d3358de-c955-42d5-a9f2-4c62ac0b85bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181469253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.4181469253
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1467522873
Short name T224
Test name
Test status
Simulation time 104343980 ps
CPU time 2.68 seconds
Started May 09 01:40:10 PM PDT 24
Finished May 09 01:40:14 PM PDT 24
Peak memory 206368 kb
Host smart-156ebedc-a284-48df-a3cb-6b24ee0046df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467522873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1467522873
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1071279134
Short name T887
Test name
Test status
Simulation time 120066425 ps
CPU time 1.01 seconds
Started May 09 01:40:13 PM PDT 24
Finished May 09 01:40:16 PM PDT 24
Peak memory 206384 kb
Host smart-ab8957c5-b345-4207-9a11-6f885167f2f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071279134 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1071279134
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2056068931
Short name T220
Test name
Test status
Simulation time 15359849 ps
CPU time 0.96 seconds
Started May 09 01:40:14 PM PDT 24
Finished May 09 01:40:16 PM PDT 24
Peak memory 206296 kb
Host smart-0e090dcb-d26f-499c-b7a1-6fb143601be5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056068931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2056068931
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.20361752
Short name T929
Test name
Test status
Simulation time 15306445 ps
CPU time 0.81 seconds
Started May 09 01:40:06 PM PDT 24
Finished May 09 01:40:08 PM PDT 24
Peak memory 206212 kb
Host smart-fa219ec7-9f4f-4479-976e-1b6a448ae6d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20361752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.20361752
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.4241720869
Short name T872
Test name
Test status
Simulation time 22958911 ps
CPU time 1.12 seconds
Started May 09 01:40:13 PM PDT 24
Finished May 09 01:40:16 PM PDT 24
Peak memory 206400 kb
Host smart-d45be0be-8942-42a1-aef5-987b756ef5c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241720869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.4241720869
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1811747370
Short name T953
Test name
Test status
Simulation time 32133862 ps
CPU time 2.08 seconds
Started May 09 01:40:15 PM PDT 24
Finished May 09 01:40:19 PM PDT 24
Peak memory 214476 kb
Host smart-64b24492-6926-4c59-8917-e6c006759925
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811747370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1811747370
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3418905276
Short name T900
Test name
Test status
Simulation time 91697140 ps
CPU time 2.28 seconds
Started May 09 01:40:05 PM PDT 24
Finished May 09 01:40:08 PM PDT 24
Peak memory 206536 kb
Host smart-bb791e35-4a3d-403f-99d5-44ba1bd30b04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418905276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3418905276
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3831567526
Short name T925
Test name
Test status
Simulation time 20884476 ps
CPU time 1.53 seconds
Started May 09 01:40:11 PM PDT 24
Finished May 09 01:40:14 PM PDT 24
Peak memory 214104 kb
Host smart-0e33b86c-fa9f-4806-a326-72c5264058d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831567526 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3831567526
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.231751532
Short name T219
Test name
Test status
Simulation time 59007098 ps
CPU time 0.83 seconds
Started May 09 01:40:12 PM PDT 24
Finished May 09 01:40:14 PM PDT 24
Peak memory 206072 kb
Host smart-a2c2d8c6-c3ac-49c8-b922-def98ad69efb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231751532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.231751532
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2869421550
Short name T882
Test name
Test status
Simulation time 15983244 ps
CPU time 0.89 seconds
Started May 09 01:40:11 PM PDT 24
Finished May 09 01:40:14 PM PDT 24
Peak memory 206228 kb
Host smart-c9a4a9c7-21f8-4449-b861-9f37c545b7ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869421550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2869421550
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4254148482
Short name T221
Test name
Test status
Simulation time 17821084 ps
CPU time 1.17 seconds
Started May 09 01:40:14 PM PDT 24
Finished May 09 01:40:16 PM PDT 24
Peak memory 206296 kb
Host smart-2a6fa15d-ad5c-48c9-a653-39a98c54ee50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254148482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.4254148482
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3495672215
Short name T867
Test name
Test status
Simulation time 111494788 ps
CPU time 1.84 seconds
Started May 09 01:40:13 PM PDT 24
Finished May 09 01:40:16 PM PDT 24
Peak memory 214568 kb
Host smart-8ab92e12-eaa6-4f1b-9915-a1e96ff2e8af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495672215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3495672215
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1059479987
Short name T943
Test name
Test status
Simulation time 49793342 ps
CPU time 1.67 seconds
Started May 09 01:40:12 PM PDT 24
Finished May 09 01:40:16 PM PDT 24
Peak memory 206304 kb
Host smart-05e28181-a821-461f-bc3d-46437a6afd5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059479987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1059479987
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3419062407
Short name T849
Test name
Test status
Simulation time 50139139 ps
CPU time 1.3 seconds
Started May 09 01:40:11 PM PDT 24
Finished May 09 01:40:13 PM PDT 24
Peak memory 216504 kb
Host smart-b5ae6253-ef71-46df-bec6-431be608e4dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419062407 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3419062407
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.411008541
Short name T217
Test name
Test status
Simulation time 14865163 ps
CPU time 0.91 seconds
Started May 09 01:40:13 PM PDT 24
Finished May 09 01:40:16 PM PDT 24
Peak memory 206336 kb
Host smart-fd44d4ab-c275-4c96-8c8d-f543dd5416b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411008541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.411008541
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1128965697
Short name T904
Test name
Test status
Simulation time 10562013 ps
CPU time 0.81 seconds
Started May 09 01:40:12 PM PDT 24
Finished May 09 01:40:14 PM PDT 24
Peak memory 206216 kb
Host smart-f3a605f2-66b2-4c91-8880-f2a59d143894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128965697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1128965697
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3853707112
Short name T205
Test name
Test status
Simulation time 22302723 ps
CPU time 0.98 seconds
Started May 09 01:40:15 PM PDT 24
Finished May 09 01:40:17 PM PDT 24
Peak memory 206284 kb
Host smart-610393d6-6ac3-42d8-823c-f9da6ad49db6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853707112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3853707112
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1733184987
Short name T881
Test name
Test status
Simulation time 87023850 ps
CPU time 1.83 seconds
Started May 09 01:40:12 PM PDT 24
Finished May 09 01:40:16 PM PDT 24
Peak memory 214572 kb
Host smart-f0aba806-37ce-46b6-94c6-27b0916e037d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733184987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1733184987
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.214777478
Short name T928
Test name
Test status
Simulation time 42294990 ps
CPU time 1.57 seconds
Started May 09 01:40:13 PM PDT 24
Finished May 09 01:40:17 PM PDT 24
Peak memory 206512 kb
Host smart-e5bcaa2f-1946-44ee-99bd-37009242b0c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214777478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.214777478
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1589654924
Short name T917
Test name
Test status
Simulation time 34452580 ps
CPU time 1.43 seconds
Started May 09 01:40:18 PM PDT 24
Finished May 09 01:40:21 PM PDT 24
Peak memory 214608 kb
Host smart-0ca4b51d-b135-4c16-a203-572e6726c93c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589654924 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1589654924
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1322823050
Short name T967
Test name
Test status
Simulation time 50246090 ps
CPU time 0.79 seconds
Started May 09 01:40:16 PM PDT 24
Finished May 09 01:40:19 PM PDT 24
Peak memory 206064 kb
Host smart-89001a6f-e834-4de8-ba5c-c2bea6783d91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322823050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1322823050
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3519378203
Short name T931
Test name
Test status
Simulation time 30413630 ps
CPU time 0.74 seconds
Started May 09 01:40:11 PM PDT 24
Finished May 09 01:40:13 PM PDT 24
Peak memory 206044 kb
Host smart-12b29d74-9ee8-469c-9a07-83178c85bb6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519378203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3519378203
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.135534978
Short name T905
Test name
Test status
Simulation time 25136916 ps
CPU time 0.94 seconds
Started May 09 01:40:18 PM PDT 24
Finished May 09 01:40:21 PM PDT 24
Peak memory 206420 kb
Host smart-6a700f50-2844-4956-bda2-b1fbaca1a0d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135534978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.135534978
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2316082631
Short name T857
Test name
Test status
Simulation time 69928460 ps
CPU time 1.76 seconds
Started May 09 01:40:15 PM PDT 24
Finished May 09 01:40:18 PM PDT 24
Peak memory 214400 kb
Host smart-f7641bf1-3ce1-4296-9969-c30b3ebf4227
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316082631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2316082631
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3426138481
Short name T891
Test name
Test status
Simulation time 153193351 ps
CPU time 1.65 seconds
Started May 09 01:40:12 PM PDT 24
Finished May 09 01:40:16 PM PDT 24
Peak memory 214664 kb
Host smart-b36e5d66-9d76-40ca-a367-a94e382f137b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426138481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3426138481
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3465493704
Short name T963
Test name
Test status
Simulation time 63520256 ps
CPU time 1.48 seconds
Started May 09 01:40:19 PM PDT 24
Finished May 09 01:40:23 PM PDT 24
Peak memory 217608 kb
Host smart-a7c2b2a0-6d75-4c51-97b4-eb66e3ba72e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465493704 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3465493704
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2843075346
Short name T222
Test name
Test status
Simulation time 20623016 ps
CPU time 0.89 seconds
Started May 09 01:40:16 PM PDT 24
Finished May 09 01:40:19 PM PDT 24
Peak memory 206112 kb
Host smart-41cb1363-7f36-47f0-a637-e106ddd73d57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843075346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2843075346
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2748959141
Short name T896
Test name
Test status
Simulation time 118917153 ps
CPU time 0.88 seconds
Started May 09 01:40:15 PM PDT 24
Finished May 09 01:40:17 PM PDT 24
Peak memory 206224 kb
Host smart-5e8ec516-3af6-4026-b638-811aa4381513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748959141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2748959141
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.539943152
Short name T218
Test name
Test status
Simulation time 27535339 ps
CPU time 1.21 seconds
Started May 09 01:40:19 PM PDT 24
Finished May 09 01:40:22 PM PDT 24
Peak memory 206396 kb
Host smart-565667ea-a4d7-437c-ae96-1076b0251924
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539943152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.539943152
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2404165966
Short name T958
Test name
Test status
Simulation time 1003691380 ps
CPU time 2.86 seconds
Started May 09 01:40:17 PM PDT 24
Finished May 09 01:40:21 PM PDT 24
Peak memory 214564 kb
Host smart-baa3cda9-c8e3-4028-be74-00ba77619618
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404165966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2404165966
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4142128195
Short name T971
Test name
Test status
Simulation time 127843063 ps
CPU time 3.14 seconds
Started May 09 01:40:15 PM PDT 24
Finished May 09 01:40:19 PM PDT 24
Peak memory 206384 kb
Host smart-0fe8365b-f369-45ee-a42c-7451db089f73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142128195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.4142128195
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.924110496
Short name T870
Test name
Test status
Simulation time 58691056 ps
CPU time 1.44 seconds
Started May 09 01:40:19 PM PDT 24
Finished May 09 01:40:23 PM PDT 24
Peak memory 214528 kb
Host smart-31bc85c5-7793-4f55-a16d-1608e2e0f417
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924110496 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.924110496
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3919573422
Short name T866
Test name
Test status
Simulation time 31213709 ps
CPU time 0.92 seconds
Started May 09 01:40:19 PM PDT 24
Finished May 09 01:40:21 PM PDT 24
Peak memory 206356 kb
Host smart-25e12c00-707a-4ca4-b0e2-410b2dcfa695
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919573422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3919573422
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3877891751
Short name T865
Test name
Test status
Simulation time 37847355 ps
CPU time 0.84 seconds
Started May 09 01:40:21 PM PDT 24
Finished May 09 01:40:23 PM PDT 24
Peak memory 206216 kb
Host smart-cb8f41b6-f35f-4439-a145-8c59ab5dc709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877891751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3877891751
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2098421597
Short name T970
Test name
Test status
Simulation time 40702814 ps
CPU time 1.09 seconds
Started May 09 01:40:18 PM PDT 24
Finished May 09 01:40:21 PM PDT 24
Peak memory 206328 kb
Host smart-7a5e94f2-56c2-44bf-8cfd-ab153e927767
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098421597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2098421597
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3088355868
Short name T890
Test name
Test status
Simulation time 40535489 ps
CPU time 1.84 seconds
Started May 09 01:40:17 PM PDT 24
Finished May 09 01:40:21 PM PDT 24
Peak memory 214600 kb
Host smart-65f1526c-a176-48ad-adc3-1aa9c3886e8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088355868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3088355868
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2946763071
Short name T225
Test name
Test status
Simulation time 377878685 ps
CPU time 2.29 seconds
Started May 09 01:40:20 PM PDT 24
Finished May 09 01:40:24 PM PDT 24
Peak memory 205608 kb
Host smart-1f621654-0b42-47a0-a68c-09eb91ba0b3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946763071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2946763071
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4275567629
Short name T202
Test name
Test status
Simulation time 30456908 ps
CPU time 1.05 seconds
Started May 09 01:39:58 PM PDT 24
Finished May 09 01:40:02 PM PDT 24
Peak memory 206252 kb
Host smart-b7e859ce-9134-4ce5-9658-dfbfdb5ffd7e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275567629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.4275567629
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3742554287
Short name T855
Test name
Test status
Simulation time 187891413 ps
CPU time 2.96 seconds
Started May 09 01:39:58 PM PDT 24
Finished May 09 01:40:03 PM PDT 24
Peak memory 206340 kb
Host smart-ae603de6-e8b0-49a2-972b-1243371adad5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742554287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3742554287
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.939738735
Short name T204
Test name
Test status
Simulation time 17258678 ps
CPU time 0.88 seconds
Started May 09 01:39:59 PM PDT 24
Finished May 09 01:40:02 PM PDT 24
Peak memory 206364 kb
Host smart-95e163bc-ebad-4862-93e8-e71b5e086181
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939738735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.939738735
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4187521782
Short name T935
Test name
Test status
Simulation time 27840234 ps
CPU time 1.44 seconds
Started May 09 01:40:01 PM PDT 24
Finished May 09 01:40:04 PM PDT 24
Peak memory 216916 kb
Host smart-a0b502a7-2579-4dc8-95a0-35d13003268a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187521782 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.4187521782
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2859558987
Short name T211
Test name
Test status
Simulation time 52017259 ps
CPU time 0.94 seconds
Started May 09 01:39:55 PM PDT 24
Finished May 09 01:39:57 PM PDT 24
Peak memory 206228 kb
Host smart-7fbbe650-22fe-4ac5-9ccf-a22c6313329d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859558987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2859558987
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1868495663
Short name T841
Test name
Test status
Simulation time 42976183 ps
CPU time 0.83 seconds
Started May 09 01:39:56 PM PDT 24
Finished May 09 01:39:59 PM PDT 24
Peak memory 206252 kb
Host smart-5851f84a-7387-4363-9e49-58976a85c899
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868495663 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1868495663
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1415444294
Short name T208
Test name
Test status
Simulation time 22151408 ps
CPU time 1.1 seconds
Started May 09 01:39:53 PM PDT 24
Finished May 09 01:39:56 PM PDT 24
Peak memory 206360 kb
Host smart-410b88a7-feeb-4fb4-9533-de8ee6bc9437
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415444294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1415444294
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.62862993
Short name T902
Test name
Test status
Simulation time 174303602 ps
CPU time 2.61 seconds
Started May 09 01:39:56 PM PDT 24
Finished May 09 01:40:01 PM PDT 24
Peak memory 214476 kb
Host smart-e9b669cf-d73a-4e9f-ac57-644155720c6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62862993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.62862993
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1174158388
Short name T237
Test name
Test status
Simulation time 239091719 ps
CPU time 2.15 seconds
Started May 09 01:39:58 PM PDT 24
Finished May 09 01:40:03 PM PDT 24
Peak memory 206420 kb
Host smart-4a5153c0-0206-4a00-89be-17d2a85476f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174158388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1174158388
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.862243496
Short name T880
Test name
Test status
Simulation time 32048077 ps
CPU time 0.81 seconds
Started May 09 01:40:17 PM PDT 24
Finished May 09 01:40:20 PM PDT 24
Peak memory 205888 kb
Host smart-f7983bed-731d-4ac9-8d1c-bac89cac02b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862243496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.862243496
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1722703229
Short name T919
Test name
Test status
Simulation time 17685628 ps
CPU time 0.98 seconds
Started May 09 01:40:21 PM PDT 24
Finished May 09 01:40:23 PM PDT 24
Peak memory 206136 kb
Host smart-66618461-3c62-433c-9fa4-b767636fa5c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722703229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1722703229
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1958927195
Short name T965
Test name
Test status
Simulation time 42766800 ps
CPU time 0.82 seconds
Started May 09 01:40:16 PM PDT 24
Finished May 09 01:40:19 PM PDT 24
Peak memory 206180 kb
Host smart-1f343bb6-c3c5-47da-8d0e-3e6bdbf5036d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958927195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1958927195
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1948617509
Short name T908
Test name
Test status
Simulation time 37163228 ps
CPU time 0.81 seconds
Started May 09 01:40:16 PM PDT 24
Finished May 09 01:40:19 PM PDT 24
Peak memory 205940 kb
Host smart-d37fb266-67f7-40d3-9cd6-c2836a55a0b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948617509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1948617509
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.5290167
Short name T975
Test name
Test status
Simulation time 22681961 ps
CPU time 0.86 seconds
Started May 09 01:40:17 PM PDT 24
Finished May 09 01:40:20 PM PDT 24
Peak memory 206260 kb
Host smart-54a36014-6a7a-46af-bf2f-9b392c15eff3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5290167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.5290167
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.4278411309
Short name T974
Test name
Test status
Simulation time 45083811 ps
CPU time 0.89 seconds
Started May 09 01:40:20 PM PDT 24
Finished May 09 01:40:23 PM PDT 24
Peak memory 206092 kb
Host smart-1d89d3dd-d390-41b7-a0a9-f41fd1002218
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278411309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.4278411309
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.4171533570
Short name T940
Test name
Test status
Simulation time 15696080 ps
CPU time 0.8 seconds
Started May 09 01:40:16 PM PDT 24
Finished May 09 01:40:19 PM PDT 24
Peak memory 205984 kb
Host smart-9d008f02-4988-4318-9dec-c01d53ff0501
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171533570 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.4171533570
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1567501761
Short name T854
Test name
Test status
Simulation time 11151818 ps
CPU time 0.83 seconds
Started May 09 01:40:16 PM PDT 24
Finished May 09 01:40:19 PM PDT 24
Peak memory 206192 kb
Host smart-a3d19ea9-9d2f-40d6-b90d-dceb501a6244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567501761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1567501761
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1186947029
Short name T927
Test name
Test status
Simulation time 13001247 ps
CPU time 0.86 seconds
Started May 09 01:40:17 PM PDT 24
Finished May 09 01:40:19 PM PDT 24
Peak memory 206128 kb
Host smart-9c5c6615-1ffe-4f44-83fa-a642503fcb45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186947029 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1186947029
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2110150610
Short name T909
Test name
Test status
Simulation time 29316527 ps
CPU time 0.9 seconds
Started May 09 01:40:22 PM PDT 24
Finished May 09 01:40:24 PM PDT 24
Peak memory 206212 kb
Host smart-9a06d16a-90ae-4f19-916c-b85b8d6dbbc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110150610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2110150610
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.4068509961
Short name T921
Test name
Test status
Simulation time 28021719 ps
CPU time 1.3 seconds
Started May 09 01:39:58 PM PDT 24
Finished May 09 01:40:02 PM PDT 24
Peak memory 206332 kb
Host smart-a3659a74-fd3e-49e8-a4c8-4d63e6a29b68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068509961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.4068509961
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.4000267058
Short name T952
Test name
Test status
Simulation time 35818659 ps
CPU time 2.05 seconds
Started May 09 01:39:53 PM PDT 24
Finished May 09 01:39:56 PM PDT 24
Peak memory 206320 kb
Host smart-10dca15b-f83d-48a8-8d27-9a6dba136b2e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000267058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.4000267058
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.843394348
Short name T954
Test name
Test status
Simulation time 57049649 ps
CPU time 0.94 seconds
Started May 09 01:39:57 PM PDT 24
Finished May 09 01:40:01 PM PDT 24
Peak memory 206360 kb
Host smart-729110a5-5a22-4ca5-82d2-af7bc26548de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843394348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.843394348
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.580631078
Short name T932
Test name
Test status
Simulation time 21216267 ps
CPU time 1.4 seconds
Started May 09 01:39:57 PM PDT 24
Finished May 09 01:40:01 PM PDT 24
Peak memory 214608 kb
Host smart-87428757-05b7-4377-bb58-8f5762d7f200
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580631078 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.580631078
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3468558413
Short name T877
Test name
Test status
Simulation time 17104978 ps
CPU time 0.79 seconds
Started May 09 01:39:57 PM PDT 24
Finished May 09 01:40:01 PM PDT 24
Peak memory 206092 kb
Host smart-5fbf940b-2c93-4567-b80a-7d1ab3c37ad6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468558413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3468558413
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.126745029
Short name T847
Test name
Test status
Simulation time 13026995 ps
CPU time 0.88 seconds
Started May 09 01:39:55 PM PDT 24
Finished May 09 01:39:58 PM PDT 24
Peak memory 206228 kb
Host smart-3349f012-ca8c-474d-b98d-adf8972b92ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126745029 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.126745029
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1607955284
Short name T871
Test name
Test status
Simulation time 13455811 ps
CPU time 0.98 seconds
Started May 09 01:39:54 PM PDT 24
Finished May 09 01:39:56 PM PDT 24
Peak memory 206356 kb
Host smart-51cfce87-d76a-4443-ab34-2be43e31b217
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607955284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1607955284
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.182411033
Short name T949
Test name
Test status
Simulation time 231217897 ps
CPU time 2.24 seconds
Started May 09 01:39:58 PM PDT 24
Finished May 09 01:40:03 PM PDT 24
Peak memory 214624 kb
Host smart-3472dc4e-b554-4b44-98bd-9193428fb32f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182411033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.182411033
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2365833934
Short name T234
Test name
Test status
Simulation time 209381330 ps
CPU time 2.82 seconds
Started May 09 01:39:56 PM PDT 24
Finished May 09 01:40:01 PM PDT 24
Peak memory 206520 kb
Host smart-c48d1977-d39e-40e2-9c1a-79f6fd077e3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365833934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2365833934
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.4250377293
Short name T941
Test name
Test status
Simulation time 20641896 ps
CPU time 0.82 seconds
Started May 09 01:40:20 PM PDT 24
Finished May 09 01:40:23 PM PDT 24
Peak memory 205872 kb
Host smart-78a57b21-e3b6-4ac7-8761-b9fa10be3961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250377293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.4250377293
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1388232032
Short name T930
Test name
Test status
Simulation time 59052964 ps
CPU time 0.92 seconds
Started May 09 01:40:21 PM PDT 24
Finished May 09 01:40:24 PM PDT 24
Peak memory 206220 kb
Host smart-4f7f2876-4ff1-40f3-9adc-233d555c03ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388232032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1388232032
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1149418453
Short name T859
Test name
Test status
Simulation time 39286862 ps
CPU time 0.84 seconds
Started May 09 01:40:20 PM PDT 24
Finished May 09 01:40:23 PM PDT 24
Peak memory 206212 kb
Host smart-0b2970a8-dc98-4ce0-a865-d752b4aff042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149418453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1149418453
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1473623771
Short name T933
Test name
Test status
Simulation time 14884678 ps
CPU time 0.89 seconds
Started May 09 01:40:19 PM PDT 24
Finished May 09 01:40:21 PM PDT 24
Peak memory 206216 kb
Host smart-77100276-0155-4734-a867-fc3ba1f19476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473623771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1473623771
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1188729849
Short name T844
Test name
Test status
Simulation time 14001228 ps
CPU time 0.89 seconds
Started May 09 01:40:16 PM PDT 24
Finished May 09 01:40:19 PM PDT 24
Peak memory 206188 kb
Host smart-51193782-00f8-4082-bcfa-cc17907aa431
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188729849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1188729849
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2480628854
Short name T968
Test name
Test status
Simulation time 24039947 ps
CPU time 0.88 seconds
Started May 09 01:40:17 PM PDT 24
Finished May 09 01:40:20 PM PDT 24
Peak memory 206240 kb
Host smart-6756859d-b1a0-47e0-9ff0-94aaeb7777a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480628854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2480628854
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1309215293
Short name T962
Test name
Test status
Simulation time 42865689 ps
CPU time 0.84 seconds
Started May 09 01:40:19 PM PDT 24
Finished May 09 01:40:22 PM PDT 24
Peak memory 206188 kb
Host smart-0b147f2d-110d-42df-9698-16dcc3510184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309215293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1309215293
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3143852784
Short name T907
Test name
Test status
Simulation time 107013923 ps
CPU time 0.85 seconds
Started May 09 01:40:16 PM PDT 24
Finished May 09 01:40:18 PM PDT 24
Peak memory 205976 kb
Host smart-aba000e2-e224-405d-9f19-5b006eb4826a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143852784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3143852784
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.4263083187
Short name T942
Test name
Test status
Simulation time 23010881 ps
CPU time 0.9 seconds
Started May 09 01:40:18 PM PDT 24
Finished May 09 01:40:21 PM PDT 24
Peak memory 206212 kb
Host smart-03198870-0a13-4803-8e71-f4e90e712fb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263083187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.4263083187
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2950307696
Short name T892
Test name
Test status
Simulation time 15249323 ps
CPU time 0.89 seconds
Started May 09 01:40:16 PM PDT 24
Finished May 09 01:40:19 PM PDT 24
Peak memory 206160 kb
Host smart-4e294c94-329d-42bb-abd3-974d6b75e300
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950307696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2950307696
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1060665618
Short name T216
Test name
Test status
Simulation time 254215010 ps
CPU time 1.52 seconds
Started May 09 01:39:58 PM PDT 24
Finished May 09 01:40:02 PM PDT 24
Peak memory 206380 kb
Host smart-94a862f0-4128-4127-810f-09411198774a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060665618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1060665618
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.390950836
Short name T851
Test name
Test status
Simulation time 224583457 ps
CPU time 6.26 seconds
Started May 09 01:39:55 PM PDT 24
Finished May 09 01:40:04 PM PDT 24
Peak memory 206480 kb
Host smart-b87b98de-2f41-40ef-9ef0-a65f97f570e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390950836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.390950836
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.371027415
Short name T862
Test name
Test status
Simulation time 267390089 ps
CPU time 1.01 seconds
Started May 09 01:39:58 PM PDT 24
Finished May 09 01:40:01 PM PDT 24
Peak memory 206336 kb
Host smart-c88e5f96-0c00-4347-ba4b-4a943d325991
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371027415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.371027415
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3553899884
Short name T957
Test name
Test status
Simulation time 76560689 ps
CPU time 1.11 seconds
Started May 09 01:39:57 PM PDT 24
Finished May 09 01:40:00 PM PDT 24
Peak memory 216196 kb
Host smart-f7f5da3a-278f-4261-a530-20885ff61a42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553899884 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3553899884
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2914435473
Short name T879
Test name
Test status
Simulation time 14976525 ps
CPU time 0.93 seconds
Started May 09 01:39:56 PM PDT 24
Finished May 09 01:40:00 PM PDT 24
Peak memory 206304 kb
Host smart-3f2bf687-f341-4c5a-9918-1108ec51de66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914435473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2914435473
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3336655366
Short name T864
Test name
Test status
Simulation time 53396786 ps
CPU time 0.88 seconds
Started May 09 01:39:56 PM PDT 24
Finished May 09 01:40:00 PM PDT 24
Peak memory 206192 kb
Host smart-ab2ceba7-3ab7-4729-872a-51c8cfd32691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336655366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3336655366
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.464894462
Short name T956
Test name
Test status
Simulation time 65304732 ps
CPU time 1.15 seconds
Started May 09 01:39:57 PM PDT 24
Finished May 09 01:40:01 PM PDT 24
Peak memory 206380 kb
Host smart-b0cea197-ad93-4540-b93e-602e6a40bc77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464894462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.464894462
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1652209586
Short name T915
Test name
Test status
Simulation time 164998663 ps
CPU time 2.45 seconds
Started May 09 01:39:56 PM PDT 24
Finished May 09 01:40:01 PM PDT 24
Peak memory 214608 kb
Host smart-412eb541-ef2f-49da-ae9b-adff65a3e329
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652209586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1652209586
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1991720292
Short name T966
Test name
Test status
Simulation time 16680838 ps
CPU time 0.96 seconds
Started May 09 01:40:23 PM PDT 24
Finished May 09 01:40:24 PM PDT 24
Peak memory 206228 kb
Host smart-3f3202a3-1d83-4e78-b477-e247b6ff6e10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991720292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1991720292
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.449130168
Short name T959
Test name
Test status
Simulation time 41583057 ps
CPU time 0.83 seconds
Started May 09 01:40:18 PM PDT 24
Finished May 09 01:40:21 PM PDT 24
Peak memory 206192 kb
Host smart-216a2c2f-bece-44c4-a827-9eac92277313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449130168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.449130168
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1946915794
Short name T842
Test name
Test status
Simulation time 21651194 ps
CPU time 0.86 seconds
Started May 09 01:40:21 PM PDT 24
Finished May 09 01:40:23 PM PDT 24
Peak memory 206184 kb
Host smart-2941e485-01a8-4d88-933c-7204cf610e76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946915794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1946915794
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.232610553
Short name T923
Test name
Test status
Simulation time 28035901 ps
CPU time 0.89 seconds
Started May 09 01:40:17 PM PDT 24
Finished May 09 01:40:20 PM PDT 24
Peak memory 206192 kb
Host smart-e5a1da54-d186-489b-95c3-6365aa3f2aca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232610553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.232610553
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3211799209
Short name T899
Test name
Test status
Simulation time 11338710 ps
CPU time 0.85 seconds
Started May 09 01:40:17 PM PDT 24
Finished May 09 01:40:20 PM PDT 24
Peak memory 206132 kb
Host smart-22e983a2-7a04-4447-b162-bf5c714d1b3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211799209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3211799209
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1142088197
Short name T914
Test name
Test status
Simulation time 31755580 ps
CPU time 0.79 seconds
Started May 09 01:40:20 PM PDT 24
Finished May 09 01:40:22 PM PDT 24
Peak memory 205300 kb
Host smart-a412f47a-49b9-4aa2-ab3e-5f63c1c5e24b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142088197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1142088197
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1653217592
Short name T950
Test name
Test status
Simulation time 17013077 ps
CPU time 0.96 seconds
Started May 09 01:40:21 PM PDT 24
Finished May 09 01:40:23 PM PDT 24
Peak memory 206216 kb
Host smart-9cbafb15-96fb-4748-8230-30a4698da065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653217592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1653217592
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2684025926
Short name T960
Test name
Test status
Simulation time 15620806 ps
CPU time 0.91 seconds
Started May 09 01:40:28 PM PDT 24
Finished May 09 01:40:30 PM PDT 24
Peak memory 206184 kb
Host smart-29481cfb-9ede-4379-958f-96fd63509a0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684025926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2684025926
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.83515447
Short name T886
Test name
Test status
Simulation time 82841754 ps
CPU time 0.8 seconds
Started May 09 01:40:32 PM PDT 24
Finished May 09 01:40:35 PM PDT 24
Peak memory 205932 kb
Host smart-6151e4a2-fb66-48cc-b792-416e20242844
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83515447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.83515447
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.119663470
Short name T869
Test name
Test status
Simulation time 49131669 ps
CPU time 0.87 seconds
Started May 09 01:40:30 PM PDT 24
Finished May 09 01:40:32 PM PDT 24
Peak memory 206200 kb
Host smart-54b56439-a510-4bc6-b23d-5197876e0e78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119663470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.119663470
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3693953464
Short name T843
Test name
Test status
Simulation time 30846132 ps
CPU time 1.25 seconds
Started May 09 01:39:56 PM PDT 24
Finished May 09 01:40:00 PM PDT 24
Peak memory 214624 kb
Host smart-5d83415d-8948-46e5-9cec-68625e6393df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693953464 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3693953464
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1579814331
Short name T903
Test name
Test status
Simulation time 25527628 ps
CPU time 0.85 seconds
Started May 09 01:40:01 PM PDT 24
Finished May 09 01:40:03 PM PDT 24
Peak memory 206004 kb
Host smart-cebb1117-aa2d-4772-893a-988e53cf8da0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579814331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1579814331
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1040058772
Short name T846
Test name
Test status
Simulation time 13021208 ps
CPU time 0.86 seconds
Started May 09 01:39:57 PM PDT 24
Finished May 09 01:40:01 PM PDT 24
Peak memory 206180 kb
Host smart-215ad0eb-29ae-4fa8-80dc-3e069a5a9791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040058772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1040058772
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1659393409
Short name T861
Test name
Test status
Simulation time 17309219 ps
CPU time 1.08 seconds
Started May 09 01:39:55 PM PDT 24
Finished May 09 01:39:58 PM PDT 24
Peak memory 206292 kb
Host smart-725b6c23-4110-41a8-9728-f8d38262fe2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659393409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1659393409
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2611311327
Short name T936
Test name
Test status
Simulation time 21461022 ps
CPU time 1.38 seconds
Started May 09 01:39:53 PM PDT 24
Finished May 09 01:39:56 PM PDT 24
Peak memory 214580 kb
Host smart-de2ff9a8-760c-4ced-ae93-41942e3c022f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611311327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2611311327
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2303698366
Short name T939
Test name
Test status
Simulation time 90530028 ps
CPU time 1.63 seconds
Started May 09 01:39:55 PM PDT 24
Finished May 09 01:39:59 PM PDT 24
Peak memory 206556 kb
Host smart-7354448f-4133-4da6-8a5a-5bec05daf216
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303698366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2303698366
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3462991612
Short name T863
Test name
Test status
Simulation time 20410411 ps
CPU time 1.41 seconds
Started May 09 01:40:01 PM PDT 24
Finished May 09 01:40:04 PM PDT 24
Peak memory 214540 kb
Host smart-a2dd23d1-8b37-4e32-aa20-cc5d28a82e7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462991612 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3462991612
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2540885320
Short name T895
Test name
Test status
Simulation time 40681683 ps
CPU time 0.9 seconds
Started May 09 01:39:59 PM PDT 24
Finished May 09 01:40:02 PM PDT 24
Peak memory 206372 kb
Host smart-d4ee977d-1b87-40a6-a702-3b4faafb2abe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540885320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2540885320
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1627738510
Short name T875
Test name
Test status
Simulation time 17747803 ps
CPU time 0.95 seconds
Started May 09 01:39:57 PM PDT 24
Finished May 09 01:40:00 PM PDT 24
Peak memory 206204 kb
Host smart-819160fd-34e8-4abf-8af7-c3df09dd7e6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627738510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1627738510
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3365173711
Short name T964
Test name
Test status
Simulation time 35601263 ps
CPU time 1.45 seconds
Started May 09 01:39:59 PM PDT 24
Finished May 09 01:40:03 PM PDT 24
Peak memory 206344 kb
Host smart-3a3d4fda-0b94-429e-9b85-403b2214c8c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365173711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3365173711
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3089197694
Short name T955
Test name
Test status
Simulation time 375255293 ps
CPU time 3.54 seconds
Started May 09 01:39:57 PM PDT 24
Finished May 09 01:40:02 PM PDT 24
Peak memory 214644 kb
Host smart-72f0e3c3-0c5e-4033-87bf-8c058b6d05fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089197694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3089197694
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3922477378
Short name T888
Test name
Test status
Simulation time 112920795 ps
CPU time 1.72 seconds
Started May 09 01:39:57 PM PDT 24
Finished May 09 01:40:01 PM PDT 24
Peak memory 214544 kb
Host smart-d0c52ccb-a75c-41c9-ab94-3b2ef4b38cdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922477378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3922477378
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3691448289
Short name T852
Test name
Test status
Simulation time 41974806 ps
CPU time 1.25 seconds
Started May 09 01:39:58 PM PDT 24
Finished May 09 01:40:02 PM PDT 24
Peak memory 216600 kb
Host smart-76293f45-c144-4a9c-8957-205675f20ec1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691448289 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3691448289
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1452371499
Short name T223
Test name
Test status
Simulation time 25725785 ps
CPU time 0.92 seconds
Started May 09 01:39:58 PM PDT 24
Finished May 09 01:40:01 PM PDT 24
Peak memory 206256 kb
Host smart-1a1c04c0-221a-4101-bede-04ce63c63ec5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452371499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1452371499
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.30261602
Short name T973
Test name
Test status
Simulation time 16515745 ps
CPU time 0.92 seconds
Started May 09 01:40:01 PM PDT 24
Finished May 09 01:40:03 PM PDT 24
Peak memory 206216 kb
Host smart-5483cf8b-df8b-47d9-a336-0c32951494c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30261602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.30261602
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3158871098
Short name T868
Test name
Test status
Simulation time 102381290 ps
CPU time 1.15 seconds
Started May 09 01:40:03 PM PDT 24
Finished May 09 01:40:05 PM PDT 24
Peak memory 206368 kb
Host smart-6422b927-6c42-49d8-b8b5-701de797123b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158871098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3158871098
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2547974477
Short name T946
Test name
Test status
Simulation time 51316622 ps
CPU time 2.06 seconds
Started May 09 01:39:59 PM PDT 24
Finished May 09 01:40:04 PM PDT 24
Peak memory 214632 kb
Host smart-753b2b52-2764-4375-8acb-6e52ac55040f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547974477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2547974477
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2455961579
Short name T947
Test name
Test status
Simulation time 43354422 ps
CPU time 1.65 seconds
Started May 09 01:40:00 PM PDT 24
Finished May 09 01:40:04 PM PDT 24
Peak memory 206528 kb
Host smart-a7793d50-f977-46e8-afbb-33413071d49c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455961579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2455961579
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2699497383
Short name T860
Test name
Test status
Simulation time 33992294 ps
CPU time 1.36 seconds
Started May 09 01:40:05 PM PDT 24
Finished May 09 01:40:07 PM PDT 24
Peak memory 217528 kb
Host smart-2d68647c-9e6a-48af-9dbc-d6cc2ace05cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699497383 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2699497383
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2830300083
Short name T934
Test name
Test status
Simulation time 185663576 ps
CPU time 0.99 seconds
Started May 09 01:40:06 PM PDT 24
Finished May 09 01:40:08 PM PDT 24
Peak memory 206372 kb
Host smart-247c2deb-f507-4f6e-b451-b85b342b47d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830300083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2830300083
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2915743067
Short name T911
Test name
Test status
Simulation time 17407256 ps
CPU time 0.79 seconds
Started May 09 01:40:09 PM PDT 24
Finished May 09 01:40:11 PM PDT 24
Peak memory 205968 kb
Host smart-4214db96-0647-48be-b623-c4e1f563398a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915743067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2915743067
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3619431044
Short name T209
Test name
Test status
Simulation time 24190146 ps
CPU time 1.22 seconds
Started May 09 01:40:09 PM PDT 24
Finished May 09 01:40:11 PM PDT 24
Peak memory 206384 kb
Host smart-162bcd23-2d5f-4b3c-a5d9-588010551747
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619431044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3619431044
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2165445395
Short name T874
Test name
Test status
Simulation time 34102009 ps
CPU time 2.36 seconds
Started May 09 01:39:58 PM PDT 24
Finished May 09 01:40:03 PM PDT 24
Peak memory 214484 kb
Host smart-10038d6c-bb78-4640-8d22-deed05c83c10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165445395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2165445395
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3179322342
Short name T235
Test name
Test status
Simulation time 151641912 ps
CPU time 2.37 seconds
Started May 09 01:40:05 PM PDT 24
Finished May 09 01:40:08 PM PDT 24
Peak memory 206452 kb
Host smart-8cc369b9-7275-4ccc-87b1-8dd6c68d02e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179322342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3179322342
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3319682819
Short name T845
Test name
Test status
Simulation time 36521096 ps
CPU time 1.28 seconds
Started May 09 01:40:09 PM PDT 24
Finished May 09 01:40:12 PM PDT 24
Peak memory 214680 kb
Host smart-77b9b80e-7bb0-4d51-9de6-aa8a367c383e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319682819 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3319682819
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.901627041
Short name T916
Test name
Test status
Simulation time 54280289 ps
CPU time 0.81 seconds
Started May 09 01:40:13 PM PDT 24
Finished May 09 01:40:16 PM PDT 24
Peak memory 206148 kb
Host smart-7f4c055a-8120-4cf3-8534-9bb5be3461b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901627041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.901627041
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2519148911
Short name T873
Test name
Test status
Simulation time 26210569 ps
CPU time 0.88 seconds
Started May 09 01:40:06 PM PDT 24
Finished May 09 01:40:08 PM PDT 24
Peak memory 206216 kb
Host smart-e1424b73-6727-4782-942a-f8b134449f95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519148911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2519148911
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2401490917
Short name T206
Test name
Test status
Simulation time 24632466 ps
CPU time 0.98 seconds
Started May 09 01:40:10 PM PDT 24
Finished May 09 01:40:13 PM PDT 24
Peak memory 206356 kb
Host smart-af576fda-e5b6-47bb-9b2b-401c585fd698
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401490917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2401490917
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.4059249447
Short name T944
Test name
Test status
Simulation time 273925894 ps
CPU time 2.06 seconds
Started May 09 01:40:12 PM PDT 24
Finished May 09 01:40:16 PM PDT 24
Peak memory 214512 kb
Host smart-c3fe976c-eda5-4dc1-851c-505ef1b5da76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059249447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.4059249447
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.4245896530
Short name T226
Test name
Test status
Simulation time 286729865 ps
CPU time 2.24 seconds
Started May 09 01:40:12 PM PDT 24
Finished May 09 01:40:17 PM PDT 24
Peak memory 214540 kb
Host smart-0f4b04fa-d771-4ff8-a0b0-cbfd4bd5e467
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245896530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.4245896530
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.2378564307
Short name T604
Test name
Test status
Simulation time 28314748 ps
CPU time 1.33 seconds
Started May 09 02:25:18 PM PDT 24
Finished May 09 02:25:21 PM PDT 24
Peak memory 215596 kb
Host smart-ba94faaa-a516-44a7-8d16-fc68c0a7c21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378564307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2378564307
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.3173216559
Short name T514
Test name
Test status
Simulation time 21785067 ps
CPU time 0.86 seconds
Started May 09 02:25:24 PM PDT 24
Finished May 09 02:25:26 PM PDT 24
Peak memory 214568 kb
Host smart-c445e8e3-843f-4baa-a4b5-770efddda14f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173216559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3173216559
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3803157446
Short name T336
Test name
Test status
Simulation time 69295940 ps
CPU time 1.29 seconds
Started May 09 02:25:28 PM PDT 24
Finished May 09 02:25:31 PM PDT 24
Peak memory 216824 kb
Host smart-548ea518-9d62-4957-9d38-a3bf541f6160
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803157446 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3803157446
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.2730294804
Short name T448
Test name
Test status
Simulation time 23071509 ps
CPU time 1.27 seconds
Started May 09 02:25:18 PM PDT 24
Finished May 09 02:25:21 PM PDT 24
Peak memory 223956 kb
Host smart-a76c04e5-e7e9-4c85-9c69-e581fcb793f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730294804 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2730294804
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.838492943
Short name T45
Test name
Test status
Simulation time 46351083 ps
CPU time 1.9 seconds
Started May 09 02:25:18 PM PDT 24
Finished May 09 02:25:21 PM PDT 24
Peak memory 217064 kb
Host smart-338b35bc-e27f-4d9e-9d94-5002188d5e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838492943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.838492943
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.1576895006
Short name T825
Test name
Test status
Simulation time 38466383 ps
CPU time 0.93 seconds
Started May 09 02:25:19 PM PDT 24
Finished May 09 02:25:21 PM PDT 24
Peak memory 207012 kb
Host smart-b592559d-75b2-41c5-bab7-a474a055c8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576895006 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1576895006
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3831896813
Short name T19
Test name
Test status
Simulation time 666436846 ps
CPU time 4.5 seconds
Started May 09 02:25:24 PM PDT 24
Finished May 09 02:25:29 PM PDT 24
Peak memory 236032 kb
Host smart-d3e8d444-eb9f-455a-9819-7fbf7c446e77
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831896813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3831896813
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.752110997
Short name T487
Test name
Test status
Simulation time 43520271 ps
CPU time 0.94 seconds
Started May 09 02:25:13 PM PDT 24
Finished May 09 02:25:16 PM PDT 24
Peak memory 215208 kb
Host smart-738a9327-00ef-4c34-abfc-269ae11cc554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752110997 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.752110997
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3075539549
Short name T5
Test name
Test status
Simulation time 157162898 ps
CPU time 3.65 seconds
Started May 09 02:25:15 PM PDT 24
Finished May 09 02:25:21 PM PDT 24
Peak memory 206968 kb
Host smart-88e6f75a-a8ab-41b4-94c0-fd31bb202bee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075539549 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3075539549
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1835776788
Short name T642
Test name
Test status
Simulation time 53982630768 ps
CPU time 1266.68 seconds
Started May 09 02:25:16 PM PDT 24
Finished May 09 02:46:24 PM PDT 24
Peak memory 223576 kb
Host smart-b2a864e5-4e78-4e35-b04d-846ebf2a55ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835776788 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1835776788
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.2530875892
Short name T174
Test name
Test status
Simulation time 76439848 ps
CPU time 1.25 seconds
Started May 09 02:25:27 PM PDT 24
Finished May 09 02:25:30 PM PDT 24
Peak memory 215612 kb
Host smart-8733178d-ffda-45bb-ba0c-9afbbb821406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530875892 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2530875892
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.3342196150
Short name T815
Test name
Test status
Simulation time 143516175 ps
CPU time 0.96 seconds
Started May 09 02:25:27 PM PDT 24
Finished May 09 02:25:30 PM PDT 24
Peak memory 206552 kb
Host smart-62e69579-d8bc-4f91-9065-59efcbea0406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342196150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3342196150
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.2012888928
Short name T175
Test name
Test status
Simulation time 22769288 ps
CPU time 0.91 seconds
Started May 09 02:25:33 PM PDT 24
Finished May 09 02:25:35 PM PDT 24
Peak memory 215300 kb
Host smart-338611a4-12af-456e-b3f2-3b5338243632
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012888928 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2012888928
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.826641841
Short name T794
Test name
Test status
Simulation time 29659036 ps
CPU time 1.05 seconds
Started May 09 02:25:27 PM PDT 24
Finished May 09 02:25:31 PM PDT 24
Peak memory 223760 kb
Host smart-1b683253-71d2-4226-85e7-4a16aa154b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826641841 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.826641841
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.452484734
Short name T43
Test name
Test status
Simulation time 93904060 ps
CPU time 3.44 seconds
Started May 09 02:25:24 PM PDT 24
Finished May 09 02:25:28 PM PDT 24
Peak memory 217416 kb
Host smart-754903ff-8554-49cb-9c52-1a47c5cac668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452484734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.452484734
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3286968472
Short name T504
Test name
Test status
Simulation time 21929568 ps
CPU time 1.08 seconds
Started May 09 02:25:37 PM PDT 24
Finished May 09 02:25:39 PM PDT 24
Peak memory 215720 kb
Host smart-40fdc2c4-f1fc-4b85-9a69-3e73f239d52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286968472 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3286968472
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.515140991
Short name T58
Test name
Test status
Simulation time 828567274 ps
CPU time 4.7 seconds
Started May 09 02:25:32 PM PDT 24
Finished May 09 02:25:38 PM PDT 24
Peak memory 235840 kb
Host smart-9e0da81a-4355-4db4-9e47-33212081074f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515140991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.515140991
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.3138350089
Short name T445
Test name
Test status
Simulation time 53658991 ps
CPU time 0.97 seconds
Started May 09 02:25:41 PM PDT 24
Finished May 09 02:25:42 PM PDT 24
Peak memory 215212 kb
Host smart-910d5747-7160-4168-beb0-c3cd1bd03656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138350089 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3138350089
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3229152285
Short name T678
Test name
Test status
Simulation time 270728741 ps
CPU time 5.3 seconds
Started May 09 02:25:24 PM PDT 24
Finished May 09 02:25:30 PM PDT 24
Peak memory 215152 kb
Host smart-518142e8-bcaf-41ad-a15f-7eb98b6a94a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229152285 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3229152285
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.897245119
Short name T191
Test name
Test status
Simulation time 84364551768 ps
CPU time 942.41 seconds
Started May 09 02:25:31 PM PDT 24
Finished May 09 02:41:15 PM PDT 24
Peak memory 221532 kb
Host smart-7c8e9b28-87b8-4449-a8fa-157f412dd8f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897245119 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.897245119
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1046598579
Short name T179
Test name
Test status
Simulation time 55237983 ps
CPU time 1.23 seconds
Started May 09 02:25:45 PM PDT 24
Finished May 09 02:25:48 PM PDT 24
Peak memory 215376 kb
Host smart-f62751ab-88ec-4df3-8bf2-f1576adc4d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046598579 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1046598579
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2792227767
Short name T751
Test name
Test status
Simulation time 15878413 ps
CPU time 0.97 seconds
Started May 09 02:25:45 PM PDT 24
Finished May 09 02:25:48 PM PDT 24
Peak memory 215132 kb
Host smart-650a2496-2da1-4895-ba16-030bc0230495
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792227767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2792227767
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.172208910
Short name T27
Test name
Test status
Simulation time 23295668 ps
CPU time 0.87 seconds
Started May 09 02:25:41 PM PDT 24
Finished May 09 02:25:43 PM PDT 24
Peak memory 215696 kb
Host smart-899b7343-21cc-4681-adab-95bcc3ecdc36
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172208910 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.172208910
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.2166329874
Short name T171
Test name
Test status
Simulation time 110395637 ps
CPU time 1.35 seconds
Started May 09 02:25:46 PM PDT 24
Finished May 09 02:25:51 PM PDT 24
Peak memory 216780 kb
Host smart-34687e09-82fd-4a12-af4a-0698f039bb3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166329874 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.2166329874
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.630398263
Short name T101
Test name
Test status
Simulation time 30717170 ps
CPU time 1.41 seconds
Started May 09 02:25:42 PM PDT 24
Finished May 09 02:25:45 PM PDT 24
Peak memory 228608 kb
Host smart-394d80d4-daf5-4196-b3ad-2659ae28c1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630398263 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.630398263
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.331970382
Short name T383
Test name
Test status
Simulation time 221235167 ps
CPU time 2.7 seconds
Started May 09 02:25:45 PM PDT 24
Finished May 09 02:25:49 PM PDT 24
Peak memory 218208 kb
Host smart-443886e8-8352-400c-83dc-92ebcb389eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331970382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.331970382
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1537396226
Short name T400
Test name
Test status
Simulation time 37580206 ps
CPU time 0.89 seconds
Started May 09 02:25:46 PM PDT 24
Finished May 09 02:25:50 PM PDT 24
Peak memory 215204 kb
Host smart-d5b148fd-d5bd-4952-a827-fbbf09a94448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537396226 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1537396226
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1276054576
Short name T821
Test name
Test status
Simulation time 64065753 ps
CPU time 0.88 seconds
Started May 09 02:25:49 PM PDT 24
Finished May 09 02:25:54 PM PDT 24
Peak memory 215064 kb
Host smart-34c79c23-7ea5-4c3e-b67b-ddd0fd2c8dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276054576 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1276054576
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.334336829
Short name T737
Test name
Test status
Simulation time 1314148638 ps
CPU time 1.98 seconds
Started May 09 02:25:45 PM PDT 24
Finished May 09 02:25:49 PM PDT 24
Peak memory 215188 kb
Host smart-647e15d1-70f2-4be4-a66d-b900409b7d53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334336829 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.334336829
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.4032745568
Short name T181
Test name
Test status
Simulation time 109184010388 ps
CPU time 395.17 seconds
Started May 09 02:25:42 PM PDT 24
Finished May 09 02:32:18 PM PDT 24
Peak memory 220788 kb
Host smart-0c49f0e9-9cec-4982-97b4-081acda73bfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032745568 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.4032745568
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.3464983683
Short name T768
Test name
Test status
Simulation time 46954245 ps
CPU time 1.04 seconds
Started May 09 02:28:14 PM PDT 24
Finished May 09 02:28:20 PM PDT 24
Peak memory 217080 kb
Host smart-b24ccd9c-d36a-4d04-bf69-048bef373c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464983683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3464983683
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.1139754606
Short name T201
Test name
Test status
Simulation time 45189295 ps
CPU time 0.93 seconds
Started May 09 02:28:12 PM PDT 24
Finished May 09 02:28:18 PM PDT 24
Peak memory 215212 kb
Host smart-86b7b0cf-c49b-4bb7-9c07-559e135fb3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139754606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1139754606
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.450395030
Short name T646
Test name
Test status
Simulation time 97369445 ps
CPU time 1.12 seconds
Started May 09 02:28:14 PM PDT 24
Finished May 09 02:28:21 PM PDT 24
Peak memory 217052 kb
Host smart-df2a2f3d-e867-4dc0-a472-580a8c262dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450395030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.450395030
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.2136878504
Short name T700
Test name
Test status
Simulation time 52683563 ps
CPU time 1.57 seconds
Started May 09 02:28:16 PM PDT 24
Finished May 09 02:28:22 PM PDT 24
Peak memory 218504 kb
Host smart-d5e3577e-3349-4c48-9b1e-be500e37e32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136878504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2136878504
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.4132955156
Short name T647
Test name
Test status
Simulation time 100680807 ps
CPU time 1.79 seconds
Started May 09 02:28:18 PM PDT 24
Finished May 09 02:28:25 PM PDT 24
Peak memory 218376 kb
Host smart-a26fcdd7-d269-4c5f-84ab-4307a5a0fe74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132955156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.4132955156
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.763044533
Short name T518
Test name
Test status
Simulation time 98051347 ps
CPU time 1.15 seconds
Started May 09 02:28:17 PM PDT 24
Finished May 09 02:28:23 PM PDT 24
Peak memory 217084 kb
Host smart-ea3ce432-0459-42fa-9553-9454ca5d2868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763044533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.763044533
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1406927988
Short name T490
Test name
Test status
Simulation time 55279591 ps
CPU time 1.3 seconds
Started May 09 02:28:18 PM PDT 24
Finished May 09 02:28:24 PM PDT 24
Peak memory 217996 kb
Host smart-18aa8a91-9d5a-4433-add9-be76b508ad8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406927988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1406927988
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.3076823067
Short name T609
Test name
Test status
Simulation time 69076009 ps
CPU time 1.11 seconds
Started May 09 02:28:18 PM PDT 24
Finished May 09 02:28:24 PM PDT 24
Peak memory 216956 kb
Host smart-045f32b4-0e74-4900-8577-bbcfb7940198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076823067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3076823067
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2904428684
Short name T374
Test name
Test status
Simulation time 171223060 ps
CPU time 1.16 seconds
Started May 09 02:28:14 PM PDT 24
Finished May 09 02:28:20 PM PDT 24
Peak memory 217076 kb
Host smart-1879b0dd-172b-4188-83c1-d8c57c749035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904428684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2904428684
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.1700154589
Short name T631
Test name
Test status
Simulation time 46153226 ps
CPU time 1.95 seconds
Started May 09 02:28:15 PM PDT 24
Finished May 09 02:28:23 PM PDT 24
Peak memory 218344 kb
Host smart-881765f7-1cdc-4bb0-9f96-12778f272a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700154589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1700154589
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.3885551376
Short name T674
Test name
Test status
Simulation time 44630637 ps
CPU time 1.18 seconds
Started May 09 02:25:46 PM PDT 24
Finished May 09 02:25:51 PM PDT 24
Peak memory 215540 kb
Host smart-b0b11405-2ea3-4d0c-93a0-de6e056bdb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885551376 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3885551376
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.3695963806
Short name T137
Test name
Test status
Simulation time 20173597 ps
CPU time 0.87 seconds
Started May 09 02:25:46 PM PDT 24
Finished May 09 02:25:51 PM PDT 24
Peak memory 216072 kb
Host smart-49dec6a7-0a30-4c52-82f8-d95114b8739f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695963806 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3695963806
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1846282896
Short name T767
Test name
Test status
Simulation time 60883511 ps
CPU time 1.25 seconds
Started May 09 02:25:46 PM PDT 24
Finished May 09 02:25:50 PM PDT 24
Peak memory 216708 kb
Host smart-b679680a-08d0-4320-b393-c71d6cdaf341
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846282896 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1846282896
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.3384454470
Short name T789
Test name
Test status
Simulation time 28938272 ps
CPU time 0.99 seconds
Started May 09 02:25:46 PM PDT 24
Finished May 09 02:25:51 PM PDT 24
Peak memory 223676 kb
Host smart-f287df2e-dba6-47e9-8609-356087e78ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384454470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3384454470
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.3626068343
Short name T434
Test name
Test status
Simulation time 97662883 ps
CPU time 1.42 seconds
Started May 09 02:25:38 PM PDT 24
Finished May 09 02:25:41 PM PDT 24
Peak memory 218552 kb
Host smart-f437df9c-24ba-4b46-9098-cf302d237cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626068343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3626068343
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.1070461175
Short name T337
Test name
Test status
Simulation time 33291791 ps
CPU time 0.92 seconds
Started May 09 02:25:46 PM PDT 24
Finished May 09 02:25:50 PM PDT 24
Peak memory 215160 kb
Host smart-2d19bd41-b6a4-45f7-8760-9d284a96582a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070461175 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1070461175
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1094776133
Short name T495
Test name
Test status
Simulation time 1357846318 ps
CPU time 4.59 seconds
Started May 09 02:25:49 PM PDT 24
Finished May 09 02:25:57 PM PDT 24
Peak memory 216688 kb
Host smart-e317bee5-2ac1-457c-943b-db4b755abc54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094776133 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1094776133
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2196580673
Short name T757
Test name
Test status
Simulation time 98488001983 ps
CPU time 1232.9 seconds
Started May 09 02:25:46 PM PDT 24
Finished May 09 02:46:22 PM PDT 24
Peak memory 225012 kb
Host smart-b26e7661-440d-4dbf-93cc-d23a0c8218ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196580673 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2196580673
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.edn_genbits.4013227775
Short name T711
Test name
Test status
Simulation time 57751891 ps
CPU time 1.25 seconds
Started May 09 02:28:19 PM PDT 24
Finished May 09 02:28:24 PM PDT 24
Peak memory 219600 kb
Host smart-0c0942c9-0d1f-4dd1-b7b0-18bf9a3919b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013227775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.4013227775
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.4149608211
Short name T311
Test name
Test status
Simulation time 103149426 ps
CPU time 1.24 seconds
Started May 09 02:28:22 PM PDT 24
Finished May 09 02:28:26 PM PDT 24
Peak memory 219384 kb
Host smart-54240bc6-35b6-4868-88e6-ee067b865b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149608211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.4149608211
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.2223641377
Short name T738
Test name
Test status
Simulation time 68803101 ps
CPU time 1.25 seconds
Started May 09 02:28:14 PM PDT 24
Finished May 09 02:28:21 PM PDT 24
Peak memory 218452 kb
Host smart-d5a048a3-ba5a-4fba-98b9-ad2a00da9fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223641377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2223641377
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.2945057567
Short name T699
Test name
Test status
Simulation time 48863516 ps
CPU time 1.62 seconds
Started May 09 02:28:14 PM PDT 24
Finished May 09 02:28:21 PM PDT 24
Peak memory 219348 kb
Host smart-357ed04d-fe45-4b20-b080-6de3cf058e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945057567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2945057567
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.2138679883
Short name T548
Test name
Test status
Simulation time 82789256 ps
CPU time 1.1 seconds
Started May 09 02:28:35 PM PDT 24
Finished May 09 02:28:37 PM PDT 24
Peak memory 217068 kb
Host smart-c71be7f4-0747-40c7-9b72-e7aa90c606bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138679883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2138679883
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.4065110321
Short name T252
Test name
Test status
Simulation time 22893078 ps
CPU time 1.18 seconds
Started May 09 02:25:44 PM PDT 24
Finished May 09 02:25:47 PM PDT 24
Peak memory 215544 kb
Host smart-97c0a325-d23d-48d6-b7ea-1ca82a1e8e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065110321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.4065110321
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3253514480
Short name T521
Test name
Test status
Simulation time 35736289 ps
CPU time 0.98 seconds
Started May 09 02:25:46 PM PDT 24
Finished May 09 02:25:51 PM PDT 24
Peak memory 206604 kb
Host smart-00dd5e93-59b7-4cb0-8e7e-51b8886c04eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253514480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3253514480
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.883308494
Short name T814
Test name
Test status
Simulation time 17487593 ps
CPU time 0.94 seconds
Started May 09 02:25:52 PM PDT 24
Finished May 09 02:25:56 PM PDT 24
Peak memory 216348 kb
Host smart-b48d2f36-6bce-4381-a240-83df3dd98f1c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883308494 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.883308494
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.3785909749
Short name T94
Test name
Test status
Simulation time 19978317 ps
CPU time 1.12 seconds
Started May 09 02:25:54 PM PDT 24
Finished May 09 02:25:58 PM PDT 24
Peak memory 219672 kb
Host smart-11974d59-9838-419b-872c-b8808450e5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785909749 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3785909749
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.277541679
Short name T263
Test name
Test status
Simulation time 50847803 ps
CPU time 1.83 seconds
Started May 09 02:25:48 PM PDT 24
Finished May 09 02:25:54 PM PDT 24
Peak memory 218176 kb
Host smart-a3bc74ea-5949-4323-81ce-6e8105a41c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277541679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.277541679
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1361969246
Short name T533
Test name
Test status
Simulation time 30227826 ps
CPU time 0.88 seconds
Started May 09 02:25:53 PM PDT 24
Finished May 09 02:25:57 PM PDT 24
Peak memory 215388 kb
Host smart-81ddf979-eb85-40ba-bc37-cfe5f910da17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361969246 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1361969246
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2601535844
Short name T515
Test name
Test status
Simulation time 15610533 ps
CPU time 0.98 seconds
Started May 09 02:25:54 PM PDT 24
Finished May 09 02:25:58 PM PDT 24
Peak memory 215228 kb
Host smart-6a4fde23-d34f-48b3-a616-fa4f89503e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601535844 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2601535844
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3305206884
Short name T547
Test name
Test status
Simulation time 75444103 ps
CPU time 1.32 seconds
Started May 09 02:25:48 PM PDT 24
Finished May 09 02:25:53 PM PDT 24
Peak memory 218008 kb
Host smart-4830214d-23aa-4fab-b303-05e32f9188ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305206884 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3305206884
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3005214831
Short name T516
Test name
Test status
Simulation time 243857162441 ps
CPU time 1581.4 seconds
Started May 09 02:25:48 PM PDT 24
Finished May 09 02:52:14 PM PDT 24
Peak memory 225324 kb
Host smart-1e3aa2e8-0c0d-41de-b959-8a1648b85b42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005214831 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3005214831
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.edn_genbits.2368321915
Short name T384
Test name
Test status
Simulation time 113915007 ps
CPU time 1.27 seconds
Started May 09 02:28:26 PM PDT 24
Finished May 09 02:28:30 PM PDT 24
Peak memory 218480 kb
Host smart-985e8040-25ff-4316-9beb-a13ae876aa14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368321915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2368321915
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.2352878460
Short name T527
Test name
Test status
Simulation time 39212539 ps
CPU time 1.74 seconds
Started May 09 02:28:26 PM PDT 24
Finished May 09 02:28:30 PM PDT 24
Peak memory 219636 kb
Host smart-66ed27ba-53a7-4a6c-b345-3b20a190ac2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352878460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2352878460
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.19301923
Short name T517
Test name
Test status
Simulation time 39009687 ps
CPU time 1.19 seconds
Started May 09 02:28:26 PM PDT 24
Finished May 09 02:28:29 PM PDT 24
Peak memory 219536 kb
Host smart-baf1cb5e-ec0a-4d0d-852f-10514d8924f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19301923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.19301923
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.4009024522
Short name T661
Test name
Test status
Simulation time 76893777 ps
CPU time 1.45 seconds
Started May 09 02:28:27 PM PDT 24
Finished May 09 02:28:31 PM PDT 24
Peak memory 218104 kb
Host smart-721b950f-ef10-431c-b52b-1717d11a4cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009024522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.4009024522
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.1246361424
Short name T608
Test name
Test status
Simulation time 69994100 ps
CPU time 1.14 seconds
Started May 09 02:28:28 PM PDT 24
Finished May 09 02:28:32 PM PDT 24
Peak memory 215244 kb
Host smart-547f10c5-c9d3-4ad8-a9b5-9b770d1ec7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246361424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1246361424
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3360855364
Short name T415
Test name
Test status
Simulation time 85060898 ps
CPU time 1.46 seconds
Started May 09 02:28:27 PM PDT 24
Finished May 09 02:28:31 PM PDT 24
Peak memory 218520 kb
Host smart-910c1e86-f9ec-4c0f-a6b4-0911df31a0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360855364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3360855364
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.4046730766
Short name T304
Test name
Test status
Simulation time 80909879 ps
CPU time 1.41 seconds
Started May 09 02:28:25 PM PDT 24
Finished May 09 02:28:29 PM PDT 24
Peak memory 217980 kb
Host smart-f5017bc4-791e-4a25-ace0-93565b953c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046730766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.4046730766
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.460005232
Short name T645
Test name
Test status
Simulation time 47760809 ps
CPU time 1.12 seconds
Started May 09 02:28:30 PM PDT 24
Finished May 09 02:28:33 PM PDT 24
Peak memory 216860 kb
Host smart-adaf2f1e-371b-489f-9453-a334fc533b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460005232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.460005232
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3451311846
Short name T482
Test name
Test status
Simulation time 33599976 ps
CPU time 1.58 seconds
Started May 09 02:28:29 PM PDT 24
Finished May 09 02:28:33 PM PDT 24
Peak memory 219648 kb
Host smart-96adbe22-cbec-4056-873f-4e751d872702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451311846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3451311846
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.456306993
Short name T694
Test name
Test status
Simulation time 42580561 ps
CPU time 1.16 seconds
Started May 09 02:25:52 PM PDT 24
Finished May 09 02:25:57 PM PDT 24
Peak memory 215804 kb
Host smart-35040581-e252-4f03-ba6a-f9ae3111a263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456306993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.456306993
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3022357035
Short name T539
Test name
Test status
Simulation time 59952642 ps
CPU time 0.94 seconds
Started May 09 02:25:43 PM PDT 24
Finished May 09 02:25:45 PM PDT 24
Peak memory 206596 kb
Host smart-4cd8a972-4327-4799-b31f-1025ff9da38e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022357035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3022357035
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_genbits.4108835034
Short name T832
Test name
Test status
Simulation time 106635313 ps
CPU time 1.02 seconds
Started May 09 02:25:46 PM PDT 24
Finished May 09 02:25:50 PM PDT 24
Peak memory 216820 kb
Host smart-576b9024-da95-4112-9e0e-8ca1078cbcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108835034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.4108835034
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3975132750
Short name T39
Test name
Test status
Simulation time 27771817 ps
CPU time 0.92 seconds
Started May 09 02:25:56 PM PDT 24
Finished May 09 02:25:59 PM PDT 24
Peak memory 215616 kb
Host smart-d2ae618e-4b2e-4671-8b9e-a1639ad16901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975132750 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3975132750
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1712256596
Short name T393
Test name
Test status
Simulation time 31014426 ps
CPU time 0.95 seconds
Started May 09 02:25:47 PM PDT 24
Finished May 09 02:25:52 PM PDT 24
Peak memory 215200 kb
Host smart-46d1bbfb-173d-40d0-8b28-f81da44f3a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712256596 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1712256596
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3131751005
Short name T620
Test name
Test status
Simulation time 463468646 ps
CPU time 4.73 seconds
Started May 09 02:25:47 PM PDT 24
Finished May 09 02:25:56 PM PDT 24
Peak memory 216776 kb
Host smart-35e21f94-4e44-41e2-8185-045abe2e2eac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131751005 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3131751005
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.4150129133
Short name T433
Test name
Test status
Simulation time 115052270118 ps
CPU time 1478.19 seconds
Started May 09 02:25:54 PM PDT 24
Finished May 09 02:50:36 PM PDT 24
Peak memory 226048 kb
Host smart-134ae549-7aa2-45e1-ace1-9c9599275527
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150129133 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.4150129133
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.611572248
Short name T310
Test name
Test status
Simulation time 34697921 ps
CPU time 1.31 seconds
Started May 09 02:28:27 PM PDT 24
Finished May 09 02:28:31 PM PDT 24
Peak memory 216732 kb
Host smart-af64a118-9304-46ba-8e39-1926dc5f7524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611572248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.611572248
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.3886241421
Short name T610
Test name
Test status
Simulation time 114811828 ps
CPU time 1.16 seconds
Started May 09 02:28:26 PM PDT 24
Finished May 09 02:28:30 PM PDT 24
Peak memory 217212 kb
Host smart-239e686d-5e43-4823-b7ac-415228ef7166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886241421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3886241421
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.2573535541
Short name T274
Test name
Test status
Simulation time 39778389 ps
CPU time 1.75 seconds
Started May 09 02:28:29 PM PDT 24
Finished May 09 02:28:34 PM PDT 24
Peak memory 218136 kb
Host smart-437187f3-6c77-4fd2-a538-2c212f27ad19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573535541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2573535541
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.4274843432
Short name T633
Test name
Test status
Simulation time 61106240 ps
CPU time 2.19 seconds
Started May 09 02:28:28 PM PDT 24
Finished May 09 02:28:33 PM PDT 24
Peak memory 219344 kb
Host smart-c12c8f00-0fb1-413e-a060-709e57800696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274843432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.4274843432
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.4055186037
Short name T73
Test name
Test status
Simulation time 115934823 ps
CPU time 1.4 seconds
Started May 09 02:28:27 PM PDT 24
Finished May 09 02:28:31 PM PDT 24
Peak memory 217200 kb
Host smart-990e6502-a0b1-4f71-aa2e-e4e13f7882b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055186037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.4055186037
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.3037646582
Short name T819
Test name
Test status
Simulation time 74469112 ps
CPU time 1.16 seconds
Started May 09 02:28:29 PM PDT 24
Finished May 09 02:28:32 PM PDT 24
Peak memory 216780 kb
Host smart-e014745d-bbbb-4e09-b2b6-fa40c94910b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037646582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3037646582
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.839143593
Short name T437
Test name
Test status
Simulation time 111893565 ps
CPU time 3.42 seconds
Started May 09 02:28:28 PM PDT 24
Finished May 09 02:28:34 PM PDT 24
Peak memory 219348 kb
Host smart-b3c8c13a-4e6f-4ad3-8548-12a679e7815c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839143593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.839143593
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.775055458
Short name T538
Test name
Test status
Simulation time 308026412 ps
CPU time 3.53 seconds
Started May 09 02:28:27 PM PDT 24
Finished May 09 02:28:33 PM PDT 24
Peak memory 215268 kb
Host smart-5a122db4-63a5-4ce7-b3d9-3fb8db70a3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775055458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.775055458
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2522432948
Short name T616
Test name
Test status
Simulation time 79396293 ps
CPU time 1.63 seconds
Started May 09 02:28:38 PM PDT 24
Finished May 09 02:28:41 PM PDT 24
Peak memory 218256 kb
Host smart-ba81a6ea-96bf-49a3-86ac-97be4423e80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522432948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2522432948
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1082750795
Short name T715
Test name
Test status
Simulation time 123691159 ps
CPU time 1.97 seconds
Started May 09 02:28:39 PM PDT 24
Finished May 09 02:28:44 PM PDT 24
Peak memory 219720 kb
Host smart-f57ffc2b-3b9c-4e12-9849-5fb8b75bffd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082750795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1082750795
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3089101449
Short name T238
Test name
Test status
Simulation time 26412321 ps
CPU time 1.28 seconds
Started May 09 02:25:47 PM PDT 24
Finished May 09 02:25:52 PM PDT 24
Peak memory 215596 kb
Host smart-001e64b2-5c5c-4111-9ed5-3728a0694eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089101449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3089101449
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.2550580332
Short name T392
Test name
Test status
Simulation time 23214044 ps
CPU time 0.87 seconds
Started May 09 02:25:48 PM PDT 24
Finished May 09 02:25:53 PM PDT 24
Peak memory 206580 kb
Host smart-99307292-b27d-45da-8686-b3f746fa683d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550580332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2550580332
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1055210807
Short name T133
Test name
Test status
Simulation time 19625545 ps
CPU time 0.86 seconds
Started May 09 02:25:54 PM PDT 24
Finished May 09 02:25:58 PM PDT 24
Peak memory 216084 kb
Host smart-db600ff0-1f01-45b6-9192-fa6e7cbb7ca2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055210807 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1055210807
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1491792423
Short name T163
Test name
Test status
Simulation time 35615248 ps
CPU time 0.98 seconds
Started May 09 02:25:47 PM PDT 24
Finished May 09 02:25:52 PM PDT 24
Peak memory 216948 kb
Host smart-6d10c471-7b61-4c86-9b2f-fffa8ebbab48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491792423 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1491792423
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.1956820514
Short name T116
Test name
Test status
Simulation time 65988410 ps
CPU time 0.86 seconds
Started May 09 02:25:56 PM PDT 24
Finished May 09 02:25:59 PM PDT 24
Peak memory 218176 kb
Host smart-f0a99bff-90c9-4782-91cb-c9cf78610fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956820514 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1956820514
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_intr.3407449663
Short name T742
Test name
Test status
Simulation time 23466307 ps
CPU time 0.9 seconds
Started May 09 02:25:45 PM PDT 24
Finished May 09 02:25:48 PM PDT 24
Peak memory 215844 kb
Host smart-09cd76ad-164e-4bae-8871-457239153ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407449663 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3407449663
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.383292174
Short name T833
Test name
Test status
Simulation time 20570363 ps
CPU time 0.98 seconds
Started May 09 02:25:49 PM PDT 24
Finished May 09 02:25:54 PM PDT 24
Peak memory 206992 kb
Host smart-a80c7fb8-efc2-4814-81a6-c4ef98e023fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383292174 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.383292174
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.4105439068
Short name T300
Test name
Test status
Simulation time 22744739 ps
CPU time 1.11 seconds
Started May 09 02:25:46 PM PDT 24
Finished May 09 02:25:49 PM PDT 24
Peak memory 215212 kb
Host smart-db8fc2a3-c362-4a2d-a0f2-7291aeb94d93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105439068 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.4105439068
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3111658309
Short name T582
Test name
Test status
Simulation time 119998405233 ps
CPU time 1533.44 seconds
Started May 09 02:25:53 PM PDT 24
Finished May 09 02:51:30 PM PDT 24
Peak memory 226808 kb
Host smart-af5d39bd-6fa3-44e8-b055-ce5d553016e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111658309 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3111658309
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.2194450847
Short name T67
Test name
Test status
Simulation time 103452084 ps
CPU time 1.61 seconds
Started May 09 02:28:40 PM PDT 24
Finished May 09 02:28:44 PM PDT 24
Peak memory 218060 kb
Host smart-6a4214c8-58dc-43a7-bbb9-70c48a8c7d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194450847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2194450847
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.21385162
Short name T783
Test name
Test status
Simulation time 68790980 ps
CPU time 1.06 seconds
Started May 09 02:28:39 PM PDT 24
Finished May 09 02:28:43 PM PDT 24
Peak memory 216884 kb
Host smart-dec60259-19bd-45f4-9493-c3ba2e53bbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21385162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.21385162
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.442861204
Short name T333
Test name
Test status
Simulation time 271233475 ps
CPU time 3.7 seconds
Started May 09 02:28:40 PM PDT 24
Finished May 09 02:28:47 PM PDT 24
Peak memory 219448 kb
Host smart-9b6c22fc-5545-405d-a3af-1c532957a01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442861204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.442861204
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.3299234787
Short name T461
Test name
Test status
Simulation time 35627372 ps
CPU time 1.26 seconds
Started May 09 02:28:38 PM PDT 24
Finished May 09 02:28:40 PM PDT 24
Peak memory 215168 kb
Host smart-008a4a90-e247-4080-ba53-6678b1f62dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299234787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3299234787
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.2855900875
Short name T233
Test name
Test status
Simulation time 81619931 ps
CPU time 1.22 seconds
Started May 09 02:28:43 PM PDT 24
Finished May 09 02:28:47 PM PDT 24
Peak memory 216940 kb
Host smart-82b51fd9-f69a-4976-bfc2-4501f94afbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855900875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2855900875
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1640459644
Short name T317
Test name
Test status
Simulation time 51868082 ps
CPU time 1.18 seconds
Started May 09 02:28:41 PM PDT 24
Finished May 09 02:28:45 PM PDT 24
Peak memory 215208 kb
Host smart-70ff2234-0e0e-4361-b4d0-2803b755cb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640459644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1640459644
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.3499922255
Short name T424
Test name
Test status
Simulation time 41557712 ps
CPU time 1.44 seconds
Started May 09 02:28:41 PM PDT 24
Finished May 09 02:28:46 PM PDT 24
Peak memory 216964 kb
Host smart-f5182c8a-c515-4ae0-9d88-de9cbd7b5de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499922255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3499922255
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.2715164880
Short name T385
Test name
Test status
Simulation time 235553869 ps
CPU time 1.04 seconds
Started May 09 02:28:39 PM PDT 24
Finished May 09 02:28:43 PM PDT 24
Peak memory 217036 kb
Host smart-4da292ef-f2dc-4b60-9110-a900fb520936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715164880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2715164880
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1916900809
Short name T243
Test name
Test status
Simulation time 48340455 ps
CPU time 1.27 seconds
Started May 09 02:25:59 PM PDT 24
Finished May 09 02:26:03 PM PDT 24
Peak memory 215580 kb
Host smart-3ba5267e-6873-4720-adbd-2ffcb390f594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916900809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1916900809
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3559757398
Short name T626
Test name
Test status
Simulation time 87084995 ps
CPU time 1.11 seconds
Started May 09 02:26:02 PM PDT 24
Finished May 09 02:26:05 PM PDT 24
Peak memory 214768 kb
Host smart-cd0eb737-437a-4e0a-8b4b-f35aa5b66ca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559757398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3559757398
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3301053507
Short name T257
Test name
Test status
Simulation time 12996284 ps
CPU time 0.92 seconds
Started May 09 02:26:00 PM PDT 24
Finished May 09 02:26:03 PM PDT 24
Peak memory 216020 kb
Host smart-16d22a0d-d835-4509-b096-7a70a689d933
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301053507 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3301053507
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.457344876
Short name T341
Test name
Test status
Simulation time 23441157 ps
CPU time 1.07 seconds
Started May 09 02:26:06 PM PDT 24
Finished May 09 02:26:10 PM PDT 24
Peak memory 218252 kb
Host smart-7294863b-39d8-405c-b293-d1e832d6bcd6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457344876 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.457344876
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2269618997
Short name T750
Test name
Test status
Simulation time 35743593 ps
CPU time 0.99 seconds
Started May 09 02:25:55 PM PDT 24
Finished May 09 02:25:59 PM PDT 24
Peak memory 223752 kb
Host smart-f173f017-d3e5-4c7f-950d-c72f28d91e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269618997 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2269618997
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2244766825
Short name T741
Test name
Test status
Simulation time 75310874 ps
CPU time 1.24 seconds
Started May 09 02:25:44 PM PDT 24
Finished May 09 02:25:48 PM PDT 24
Peak memory 218688 kb
Host smart-596c164b-9d09-4026-bae6-3563c8e604ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244766825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2244766825
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2490781659
Short name T460
Test name
Test status
Simulation time 29592787 ps
CPU time 0.84 seconds
Started May 09 02:25:55 PM PDT 24
Finished May 09 02:25:58 PM PDT 24
Peak memory 215532 kb
Host smart-93c13a68-d65a-49b8-ad7c-82588df55fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490781659 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2490781659
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2361100986
Short name T756
Test name
Test status
Simulation time 25785176 ps
CPU time 0.96 seconds
Started May 09 02:25:44 PM PDT 24
Finished May 09 02:25:47 PM PDT 24
Peak memory 215224 kb
Host smart-2dc2600a-4852-4ebb-8029-b165486d4bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361100986 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2361100986
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1268423812
Short name T611
Test name
Test status
Simulation time 1222487525 ps
CPU time 5.2 seconds
Started May 09 02:25:58 PM PDT 24
Finished May 09 02:26:06 PM PDT 24
Peak memory 215192 kb
Host smart-c5aa9984-9ac3-40d8-a5f7-b19ece3a1b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268423812 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1268423812
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.810596890
Short name T143
Test name
Test status
Simulation time 254243592350 ps
CPU time 3067.62 seconds
Started May 09 02:25:54 PM PDT 24
Finished May 09 03:17:05 PM PDT 24
Peak memory 229980 kb
Host smart-9971b7cb-9905-4204-9945-f51e35c99103
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810596890 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.810596890
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.2100727892
Short name T622
Test name
Test status
Simulation time 76857615 ps
CPU time 1.24 seconds
Started May 09 03:18:57 PM PDT 24
Finished May 09 03:19:00 PM PDT 24
Peak memory 216804 kb
Host smart-1f768083-46f6-452f-94ae-d894137ecf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100727892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2100727892
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.3252915211
Short name T345
Test name
Test status
Simulation time 34101846 ps
CPU time 1.46 seconds
Started May 09 03:52:38 PM PDT 24
Finished May 09 03:52:42 PM PDT 24
Peak memory 217028 kb
Host smart-992cb343-4296-4fab-8fe0-bb6c11885f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252915211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3252915211
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.2493284783
Short name T526
Test name
Test status
Simulation time 249801498 ps
CPU time 3.71 seconds
Started May 09 03:56:25 PM PDT 24
Finished May 09 03:56:30 PM PDT 24
Peak memory 217336 kb
Host smart-f7e44ec4-1a33-4ac4-bbf3-7a9cb9e1c1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493284783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2493284783
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.25798359
Short name T766
Test name
Test status
Simulation time 106791056 ps
CPU time 1.18 seconds
Started May 09 02:28:41 PM PDT 24
Finished May 09 02:28:46 PM PDT 24
Peak memory 216864 kb
Host smart-a83ee526-6a18-4299-a3ee-60fa62e2d984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25798359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.25798359
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.2705633864
Short name T834
Test name
Test status
Simulation time 92491020 ps
CPU time 1.54 seconds
Started May 09 03:24:41 PM PDT 24
Finished May 09 03:25:14 PM PDT 24
Peak memory 218496 kb
Host smart-b663fe75-a2f7-48a5-8d99-9e923e590ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705633864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2705633864
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.3181637498
Short name T643
Test name
Test status
Simulation time 141525497 ps
CPU time 1.06 seconds
Started May 09 02:28:40 PM PDT 24
Finished May 09 02:28:44 PM PDT 24
Peak memory 216968 kb
Host smart-5514a13e-b028-414c-b30d-43e592d87344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181637498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3181637498
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.261542652
Short name T600
Test name
Test status
Simulation time 74100102 ps
CPU time 1 seconds
Started May 09 02:28:38 PM PDT 24
Finished May 09 02:28:41 PM PDT 24
Peak memory 216796 kb
Host smart-7cdbc8f4-3381-4b5c-8320-d6dbab02ba13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261542652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.261542652
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.2079500981
Short name T265
Test name
Test status
Simulation time 180821867 ps
CPU time 1.68 seconds
Started May 09 02:28:39 PM PDT 24
Finished May 09 02:28:43 PM PDT 24
Peak memory 218536 kb
Host smart-444edc77-e4ef-44c6-a8a0-3aa224d7febc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079500981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2079500981
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.1382949833
Short name T315
Test name
Test status
Simulation time 34667154 ps
CPU time 1.26 seconds
Started May 09 02:28:41 PM PDT 24
Finished May 09 02:28:46 PM PDT 24
Peak memory 215196 kb
Host smart-c1a1cc5b-f084-41ac-9181-3e0475f5caae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382949833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1382949833
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.1103670633
Short name T439
Test name
Test status
Simulation time 77687204 ps
CPU time 1.62 seconds
Started May 09 02:28:37 PM PDT 24
Finished May 09 02:28:40 PM PDT 24
Peak memory 218420 kb
Host smart-4b5d007e-bb7c-4b4e-bc92-d464d14b8229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103670633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1103670633
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1435098599
Short name T251
Test name
Test status
Simulation time 46450997 ps
CPU time 1.12 seconds
Started May 09 02:25:57 PM PDT 24
Finished May 09 02:26:01 PM PDT 24
Peak memory 215572 kb
Host smart-1ae69575-6b6c-425c-9736-08d9462c97a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435098599 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1435098599
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3311973741
Short name T580
Test name
Test status
Simulation time 157996321 ps
CPU time 0.85 seconds
Started May 09 02:25:55 PM PDT 24
Finished May 09 02:25:59 PM PDT 24
Peak memory 206180 kb
Host smart-183a57b4-b05f-47fe-8fc2-a82e6cbe542d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311973741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3311973741
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.3053181175
Short name T118
Test name
Test status
Simulation time 20650433 ps
CPU time 0.86 seconds
Started May 09 02:25:55 PM PDT 24
Finished May 09 02:25:59 PM PDT 24
Peak memory 215296 kb
Host smart-09aea69e-cfa8-4da5-ad87-3c991fe200c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053181175 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3053181175
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1323275561
Short name T104
Test name
Test status
Simulation time 135837203 ps
CPU time 1.14 seconds
Started May 09 02:26:00 PM PDT 24
Finished May 09 02:26:03 PM PDT 24
Peak memory 216740 kb
Host smart-9c3a8aba-4755-4881-8d07-68278774854e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323275561 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1323275561
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.2792913194
Short name T775
Test name
Test status
Simulation time 53600017 ps
CPU time 1.13 seconds
Started May 09 02:26:03 PM PDT 24
Finished May 09 02:26:06 PM PDT 24
Peak memory 229188 kb
Host smart-f237ac15-6515-43ba-9c40-cc76ed655eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792913194 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2792913194
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3269470880
Short name T362
Test name
Test status
Simulation time 73199929 ps
CPU time 1.15 seconds
Started May 09 02:25:58 PM PDT 24
Finished May 09 02:26:02 PM PDT 24
Peak memory 216848 kb
Host smart-772eaa26-16e7-4f60-99cc-518388ae36cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269470880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3269470880
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2737989800
Short name T664
Test name
Test status
Simulation time 21900946 ps
CPU time 1.25 seconds
Started May 09 02:26:03 PM PDT 24
Finished May 09 02:26:06 PM PDT 24
Peak memory 224936 kb
Host smart-bb23b998-6b30-485c-ab54-a1969ab4bf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737989800 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2737989800
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.413904607
Short name T344
Test name
Test status
Simulation time 63877212 ps
CPU time 0.89 seconds
Started May 09 02:25:54 PM PDT 24
Finished May 09 02:25:58 PM PDT 24
Peak memory 215128 kb
Host smart-da0f9e32-5253-4eaf-b6df-da04d9d8cc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413904607 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.413904607
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.209321189
Short name T601
Test name
Test status
Simulation time 150857770 ps
CPU time 3.63 seconds
Started May 09 02:25:55 PM PDT 24
Finished May 09 02:26:01 PM PDT 24
Peak memory 216848 kb
Host smart-590a2dd2-ca03-4c37-8938-d079bc2338c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209321189 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.209321189
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2117878341
Short name T404
Test name
Test status
Simulation time 97319169909 ps
CPU time 1276.36 seconds
Started May 09 02:25:54 PM PDT 24
Finished May 09 02:47:14 PM PDT 24
Peak memory 223828 kb
Host smart-c7331f0b-36a9-45fc-a61b-21b77032aa41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117878341 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2117878341
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.179325531
Short name T354
Test name
Test status
Simulation time 85211453 ps
CPU time 1.19 seconds
Started May 09 02:28:40 PM PDT 24
Finished May 09 02:28:44 PM PDT 24
Peak memory 218132 kb
Host smart-aa34b06f-8dde-4377-8b64-cd2b9d56b6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179325531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.179325531
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.231038959
Short name T318
Test name
Test status
Simulation time 299628161 ps
CPU time 2.58 seconds
Started May 09 02:28:39 PM PDT 24
Finished May 09 02:28:44 PM PDT 24
Peak memory 220100 kb
Host smart-00062b00-64de-4f74-9a35-149b900d8b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231038959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.231038959
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2155365687
Short name T567
Test name
Test status
Simulation time 47654026 ps
CPU time 1.54 seconds
Started May 09 02:28:42 PM PDT 24
Finished May 09 02:28:47 PM PDT 24
Peak memory 215132 kb
Host smart-bcf40c40-d75b-406e-b568-603e71b5e8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155365687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2155365687
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.3993987948
Short name T743
Test name
Test status
Simulation time 45772226 ps
CPU time 1.3 seconds
Started May 09 02:28:37 PM PDT 24
Finished May 09 02:28:40 PM PDT 24
Peak memory 218176 kb
Host smart-37539969-5741-4151-a3d9-0925f4ae79e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993987948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3993987948
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.127445087
Short name T381
Test name
Test status
Simulation time 39794759 ps
CPU time 1.4 seconds
Started May 09 02:28:39 PM PDT 24
Finished May 09 02:28:43 PM PDT 24
Peak memory 217004 kb
Host smart-101404b9-a13b-4e62-84fa-0827f8074d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127445087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.127445087
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.1281044710
Short name T230
Test name
Test status
Simulation time 132837599 ps
CPU time 1.14 seconds
Started May 09 02:28:40 PM PDT 24
Finished May 09 02:28:44 PM PDT 24
Peak memory 217124 kb
Host smart-07a0da57-c220-49ed-b251-fbf6470e0852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281044710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1281044710
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.2356797127
Short name T305
Test name
Test status
Simulation time 60344023 ps
CPU time 1.24 seconds
Started May 09 02:28:44 PM PDT 24
Finished May 09 02:28:48 PM PDT 24
Peak memory 217920 kb
Host smart-0816c199-08a7-4fca-bedb-a1842bb4b875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356797127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2356797127
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.178193578
Short name T571
Test name
Test status
Simulation time 23101312 ps
CPU time 1.13 seconds
Started May 09 02:28:39 PM PDT 24
Finished May 09 02:28:42 PM PDT 24
Peak memory 216960 kb
Host smart-3abc69f4-6877-4f68-96ae-07828f23b72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178193578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.178193578
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1539765211
Short name T572
Test name
Test status
Simulation time 25313249 ps
CPU time 1.13 seconds
Started May 09 02:26:00 PM PDT 24
Finished May 09 02:26:03 PM PDT 24
Peak memory 215564 kb
Host smart-f63ab8b0-ff44-413e-9760-b1e8c4037970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539765211 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1539765211
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.1000851969
Short name T394
Test name
Test status
Simulation time 46699568 ps
CPU time 1.05 seconds
Started May 09 02:25:56 PM PDT 24
Finished May 09 02:26:00 PM PDT 24
Peak memory 206604 kb
Host smart-f42d4924-0193-402e-968a-079f2e9c77a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000851969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1000851969
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_err.4242157380
Short name T532
Test name
Test status
Simulation time 39097427 ps
CPU time 1.1 seconds
Started May 09 02:25:55 PM PDT 24
Finished May 09 02:25:59 PM PDT 24
Peak memory 220496 kb
Host smart-28a65d5a-7d0d-44be-b50f-9152f0c2c09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242157380 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.4242157380
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_smoke.579884295
Short name T758
Test name
Test status
Simulation time 63278762 ps
CPU time 0.9 seconds
Started May 09 02:26:02 PM PDT 24
Finished May 09 02:26:05 PM PDT 24
Peak memory 215204 kb
Host smart-744d20e5-b15c-45bc-ad9b-bd5d72d8edb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579884295 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.579884295
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3730731749
Short name T267
Test name
Test status
Simulation time 437866851 ps
CPU time 3.03 seconds
Started May 09 02:25:58 PM PDT 24
Finished May 09 02:26:03 PM PDT 24
Peak memory 218448 kb
Host smart-024df1db-fa93-42ce-bc54-305140153870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730731749 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3730731749
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2410135428
Short name T42
Test name
Test status
Simulation time 102271075001 ps
CPU time 645.12 seconds
Started May 09 02:26:00 PM PDT 24
Finished May 09 02:36:48 PM PDT 24
Peak memory 220288 kb
Host smart-64461a65-4e32-49ea-93b7-0e392904e8fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410135428 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2410135428
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.881832245
Short name T595
Test name
Test status
Simulation time 34970466 ps
CPU time 1.48 seconds
Started May 09 02:28:45 PM PDT 24
Finished May 09 02:28:49 PM PDT 24
Peak memory 219320 kb
Host smart-4ab905af-882c-4f59-acc7-5505a7d77f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881832245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.881832245
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.3563248931
Short name T562
Test name
Test status
Simulation time 53434686 ps
CPU time 1.77 seconds
Started May 09 02:28:47 PM PDT 24
Finished May 09 02:28:51 PM PDT 24
Peak memory 219880 kb
Host smart-26afc12d-0c99-4eb9-9ae8-ea85fffaecf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563248931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3563248931
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.194956606
Short name T375
Test name
Test status
Simulation time 48904006 ps
CPU time 1.27 seconds
Started May 09 02:28:49 PM PDT 24
Finished May 09 02:28:54 PM PDT 24
Peak memory 218408 kb
Host smart-a59e0832-9b8d-4268-804c-5bb58842720b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194956606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.194956606
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.2342263118
Short name T293
Test name
Test status
Simulation time 84664403 ps
CPU time 2.15 seconds
Started May 09 02:28:47 PM PDT 24
Finished May 09 02:28:51 PM PDT 24
Peak memory 218248 kb
Host smart-838ecfc5-5118-4584-854f-378e8f4334c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342263118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2342263118
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.2279721410
Short name T373
Test name
Test status
Simulation time 44000803 ps
CPU time 1.19 seconds
Started May 09 02:28:48 PM PDT 24
Finished May 09 02:28:51 PM PDT 24
Peak memory 218924 kb
Host smart-c8483d7d-9bb1-4415-83a7-3eebe9b57970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279721410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2279721410
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.196637057
Short name T560
Test name
Test status
Simulation time 82140283 ps
CPU time 1.19 seconds
Started May 09 02:28:50 PM PDT 24
Finished May 09 02:28:54 PM PDT 24
Peak memory 218896 kb
Host smart-9a175a71-7d27-4a3f-bba6-61cb90ab691d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196637057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.196637057
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.1150100225
Short name T722
Test name
Test status
Simulation time 66775679 ps
CPU time 1.19 seconds
Started May 09 02:28:46 PM PDT 24
Finished May 09 02:28:49 PM PDT 24
Peak memory 216856 kb
Host smart-b05b83d0-811c-44ad-8440-2d46d3c222ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150100225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1150100225
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.4255181451
Short name T535
Test name
Test status
Simulation time 63435899 ps
CPU time 1.01 seconds
Started May 09 02:28:47 PM PDT 24
Finished May 09 02:28:50 PM PDT 24
Peak memory 216836 kb
Host smart-bb47b8a1-6c1a-42f7-ab5b-98747402c4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255181451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.4255181451
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.3691146129
Short name T759
Test name
Test status
Simulation time 46654525 ps
CPU time 1.64 seconds
Started May 09 02:28:50 PM PDT 24
Finished May 09 02:28:54 PM PDT 24
Peak memory 218284 kb
Host smart-120537d3-40ea-4f52-b34d-ed898202c0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691146129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3691146129
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.4199951366
Short name T779
Test name
Test status
Simulation time 94957989 ps
CPU time 1.2 seconds
Started May 09 02:28:49 PM PDT 24
Finished May 09 02:28:53 PM PDT 24
Peak memory 218324 kb
Host smart-b050dbf0-92ed-46eb-84d1-1897b94a0067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199951366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.4199951366
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1559216961
Short name T625
Test name
Test status
Simulation time 277589299 ps
CPU time 1.41 seconds
Started May 09 02:26:03 PM PDT 24
Finished May 09 02:26:07 PM PDT 24
Peak memory 215548 kb
Host smart-10d4123a-17e2-45d3-b3d4-81aa5545e321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559216961 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1559216961
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.4082216049
Short name T546
Test name
Test status
Simulation time 44097810 ps
CPU time 0.92 seconds
Started May 09 02:25:54 PM PDT 24
Finished May 09 02:25:58 PM PDT 24
Peak memory 206584 kb
Host smart-5565bcfe-c64d-4486-92aa-cef66d9b38b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082216049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.4082216049
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2040337374
Short name T802
Test name
Test status
Simulation time 13307010 ps
CPU time 0.91 seconds
Started May 09 02:26:00 PM PDT 24
Finished May 09 02:26:03 PM PDT 24
Peak memory 215428 kb
Host smart-3950c27a-fa11-4347-aabe-78c3c554f23b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040337374 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2040337374
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2808380473
Short name T161
Test name
Test status
Simulation time 74408575 ps
CPU time 1.07 seconds
Started May 09 02:25:55 PM PDT 24
Finished May 09 02:25:59 PM PDT 24
Peak memory 216860 kb
Host smart-18d5dc01-681c-41bc-84d9-0c6a6074ef5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808380473 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2808380473
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.315800925
Short name T692
Test name
Test status
Simulation time 29914676 ps
CPU time 1.27 seconds
Started May 09 02:26:02 PM PDT 24
Finished May 09 02:26:05 PM PDT 24
Peak memory 219488 kb
Host smart-50bb03ba-47ff-431c-8a2a-14469fe315bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315800925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.315800925
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.281669881
Short name T391
Test name
Test status
Simulation time 111066488 ps
CPU time 1.29 seconds
Started May 09 02:25:57 PM PDT 24
Finished May 09 02:26:01 PM PDT 24
Peak memory 219228 kb
Host smart-19604172-40f4-456f-a0fb-761656698421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281669881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.281669881
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.3919982290
Short name T549
Test name
Test status
Simulation time 34073799 ps
CPU time 0.87 seconds
Started May 09 02:25:56 PM PDT 24
Finished May 09 02:25:59 PM PDT 24
Peak memory 215328 kb
Host smart-3be1aeaa-bce7-4681-8eff-639381e3e883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919982290 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3919982290
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.196135220
Short name T709
Test name
Test status
Simulation time 43778628 ps
CPU time 0.92 seconds
Started May 09 02:25:57 PM PDT 24
Finished May 09 02:26:01 PM PDT 24
Peak memory 215204 kb
Host smart-7f6df4a4-f311-4648-8a07-740bf3eb5f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196135220 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.196135220
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.799975622
Short name T491
Test name
Test status
Simulation time 49038286 ps
CPU time 1.02 seconds
Started May 09 02:26:02 PM PDT 24
Finished May 09 02:26:05 PM PDT 24
Peak memory 215056 kb
Host smart-271b497d-a623-4b6a-afae-cf6d7a18d944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799975622 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.799975622
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2202181920
Short name T534
Test name
Test status
Simulation time 88715549591 ps
CPU time 1135.87 seconds
Started May 09 02:25:56 PM PDT 24
Finished May 09 02:44:55 PM PDT 24
Peak memory 224312 kb
Host smart-877a4b0f-5493-44d0-9927-2e76644aff57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202181920 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2202181920
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.13174429
Short name T378
Test name
Test status
Simulation time 42111063 ps
CPU time 1.42 seconds
Started May 09 02:28:47 PM PDT 24
Finished May 09 02:28:51 PM PDT 24
Peak memory 217892 kb
Host smart-77740b65-68ed-4ea7-91c8-a4440d0422bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13174429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.13174429
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.2413561523
Short name T273
Test name
Test status
Simulation time 49019575 ps
CPU time 1.3 seconds
Started May 09 02:28:50 PM PDT 24
Finished May 09 02:28:54 PM PDT 24
Peak memory 217008 kb
Host smart-2a7e1f5f-814f-40c0-845b-2ea574dc275c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413561523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2413561523
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.2809231545
Short name T818
Test name
Test status
Simulation time 31817889 ps
CPU time 1.57 seconds
Started May 09 02:28:50 PM PDT 24
Finished May 09 02:28:54 PM PDT 24
Peak memory 217000 kb
Host smart-255ca76b-115d-4828-8dec-29e09d66b1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809231545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2809231545
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.2870372084
Short name T740
Test name
Test status
Simulation time 79978019 ps
CPU time 1.14 seconds
Started May 09 02:28:49 PM PDT 24
Finished May 09 02:28:54 PM PDT 24
Peak memory 216808 kb
Host smart-2298abc0-91ae-47fa-8413-4bdfa83e649b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870372084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2870372084
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.2711784419
Short name T698
Test name
Test status
Simulation time 76001837 ps
CPU time 1.15 seconds
Started May 09 02:28:49 PM PDT 24
Finished May 09 02:28:53 PM PDT 24
Peak memory 219420 kb
Host smart-c01ee767-2b9b-4938-926b-dddefa30e256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711784419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2711784419
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.4015135585
Short name T258
Test name
Test status
Simulation time 55549611 ps
CPU time 2.32 seconds
Started May 09 02:28:48 PM PDT 24
Finished May 09 02:28:53 PM PDT 24
Peak memory 219732 kb
Host smart-49cfec49-2b58-409f-be89-8c562cafe3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015135585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.4015135585
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.1992472815
Short name T734
Test name
Test status
Simulation time 39785871 ps
CPU time 1.38 seconds
Started May 09 02:28:48 PM PDT 24
Finished May 09 02:28:52 PM PDT 24
Peak memory 218232 kb
Host smart-90d261a7-e7a9-4af0-a906-e4de3763d6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992472815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1992472815
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.1369119154
Short name T725
Test name
Test status
Simulation time 51537500 ps
CPU time 1.82 seconds
Started May 09 02:28:48 PM PDT 24
Finished May 09 02:28:52 PM PDT 24
Peak memory 217960 kb
Host smart-8c0de714-0e92-4db6-b0d0-0888f7d2c309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369119154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1369119154
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1701757789
Short name T280
Test name
Test status
Simulation time 55087091 ps
CPU time 1.46 seconds
Started May 09 02:28:48 PM PDT 24
Finished May 09 02:28:53 PM PDT 24
Peak memory 218404 kb
Host smart-aa6a2467-ee3f-4e54-a28b-b218ef996051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701757789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1701757789
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.3604866945
Short name T588
Test name
Test status
Simulation time 67465311 ps
CPU time 1.28 seconds
Started May 09 02:28:48 PM PDT 24
Finished May 09 02:28:52 PM PDT 24
Peak memory 216940 kb
Host smart-6bef3332-31ee-41a0-92e8-914c4b153147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604866945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3604866945
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3752438125
Short name T696
Test name
Test status
Simulation time 88886494 ps
CPU time 1.31 seconds
Started May 09 02:26:06 PM PDT 24
Finished May 09 02:26:11 PM PDT 24
Peak memory 215544 kb
Host smart-f283fdac-627f-4a23-94fb-e2a732ef35d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752438125 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3752438125
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1370380899
Short name T320
Test name
Test status
Simulation time 35869761 ps
CPU time 0.92 seconds
Started May 09 02:25:58 PM PDT 24
Finished May 09 02:26:01 PM PDT 24
Peak memory 214588 kb
Host smart-8bb87652-c3bb-4776-ad2a-3ea849700319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370380899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1370380899
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1049136457
Short name T352
Test name
Test status
Simulation time 14716119 ps
CPU time 1.05 seconds
Started May 09 02:26:00 PM PDT 24
Finished May 09 02:26:03 PM PDT 24
Peak memory 215984 kb
Host smart-a9178fb8-adbe-4b98-8697-d53a77eddcb6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049136457 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1049136457
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.4150300148
Short name T728
Test name
Test status
Simulation time 63707966 ps
CPU time 1.03 seconds
Started May 09 02:26:00 PM PDT 24
Finished May 09 02:26:03 PM PDT 24
Peak memory 219276 kb
Host smart-e4d18198-900a-481f-99a3-4e16c7cb60a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150300148 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.4150300148
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1371756080
Short name T627
Test name
Test status
Simulation time 27336527 ps
CPU time 0.88 seconds
Started May 09 02:25:55 PM PDT 24
Finished May 09 02:25:59 PM PDT 24
Peak memory 218020 kb
Host smart-39ff5ca3-6705-4707-9055-ad689dc17b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371756080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1371756080
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2438410767
Short name T492
Test name
Test status
Simulation time 54068741 ps
CPU time 1.52 seconds
Started May 09 02:26:02 PM PDT 24
Finished May 09 02:26:06 PM PDT 24
Peak memory 218132 kb
Host smart-e6914adc-b4de-4379-8245-5e94098db50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438410767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2438410767
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.466316636
Short name T455
Test name
Test status
Simulation time 23928397 ps
CPU time 1.12 seconds
Started May 09 02:26:08 PM PDT 24
Finished May 09 02:26:12 PM PDT 24
Peak memory 215740 kb
Host smart-78e160cf-ffba-42b7-8b16-bc56e41b235a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466316636 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.466316636
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.4230311350
Short name T295
Test name
Test status
Simulation time 117197997 ps
CPU time 0.91 seconds
Started May 09 02:26:02 PM PDT 24
Finished May 09 02:26:05 PM PDT 24
Peak memory 215108 kb
Host smart-f5378ee0-34f0-4207-a399-0ec3b3d977b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230311350 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.4230311350
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2249693379
Short name T663
Test name
Test status
Simulation time 1382570521 ps
CPU time 3.5 seconds
Started May 09 02:26:03 PM PDT 24
Finished May 09 02:26:09 PM PDT 24
Peak memory 214804 kb
Host smart-e7fed840-c512-44d5-bbf2-f4c1253237f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249693379 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2249693379
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.906973156
Short name T458
Test name
Test status
Simulation time 330070931165 ps
CPU time 2292.65 seconds
Started May 09 02:25:56 PM PDT 24
Finished May 09 03:04:12 PM PDT 24
Peak memory 229188 kb
Host smart-575b5e59-d067-4d15-b5ab-d2bc033be3c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906973156 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.906973156
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.472304792
Short name T438
Test name
Test status
Simulation time 55870682 ps
CPU time 1.58 seconds
Started May 09 02:28:50 PM PDT 24
Finished May 09 02:28:54 PM PDT 24
Peak memory 218280 kb
Host smart-3226afd2-f85b-4100-be23-224b2251d4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472304792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.472304792
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.1654570080
Short name T649
Test name
Test status
Simulation time 75173349 ps
CPU time 1.43 seconds
Started May 09 02:28:50 PM PDT 24
Finished May 09 02:28:54 PM PDT 24
Peak memory 216884 kb
Host smart-71d428e0-5723-4626-be50-ecb25dced237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654570080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1654570080
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.2358273519
Short name T70
Test name
Test status
Simulation time 36247118 ps
CPU time 1.33 seconds
Started May 09 02:28:55 PM PDT 24
Finished May 09 02:28:58 PM PDT 24
Peak memory 216876 kb
Host smart-ebdf71f5-4f1c-4566-8341-69bdf92c43b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358273519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2358273519
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.990756029
Short name T493
Test name
Test status
Simulation time 93779016 ps
CPU time 1.43 seconds
Started May 09 02:28:50 PM PDT 24
Finished May 09 02:28:55 PM PDT 24
Peak memory 218424 kb
Host smart-0c759ac3-9a9c-4761-b6a2-c0bc5ad231cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990756029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.990756029
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.844547595
Short name T688
Test name
Test status
Simulation time 59524488 ps
CPU time 1.18 seconds
Started May 09 02:28:49 PM PDT 24
Finished May 09 02:28:53 PM PDT 24
Peak memory 216908 kb
Host smart-696f6afa-d9a3-4af2-a1d4-ed03ea9b9e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844547595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.844547595
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.4170879826
Short name T746
Test name
Test status
Simulation time 80467917 ps
CPU time 1.39 seconds
Started May 09 02:28:49 PM PDT 24
Finished May 09 02:28:54 PM PDT 24
Peak memory 216972 kb
Host smart-fabefe70-1f70-44a6-892b-a29d1f503b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170879826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.4170879826
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.2528461883
Short name T522
Test name
Test status
Simulation time 62516882 ps
CPU time 1.26 seconds
Started May 09 02:28:54 PM PDT 24
Finished May 09 02:28:57 PM PDT 24
Peak memory 218176 kb
Host smart-b898f30e-c1f0-48a1-a858-089d01fc9417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528461883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2528461883
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3863447227
Short name T480
Test name
Test status
Simulation time 41986414 ps
CPU time 1.28 seconds
Started May 09 02:28:49 PM PDT 24
Finished May 09 02:28:54 PM PDT 24
Peak memory 218040 kb
Host smart-fb64d93f-c89f-4331-a40f-408582dfad5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863447227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3863447227
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.3466863506
Short name T822
Test name
Test status
Simulation time 36730065 ps
CPU time 1.43 seconds
Started May 09 02:28:50 PM PDT 24
Finished May 09 02:28:55 PM PDT 24
Peak memory 216924 kb
Host smart-e23914ac-bc57-4733-90e2-416ebbdfb3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466863506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3466863506
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.4148517094
Short name T259
Test name
Test status
Simulation time 53503012 ps
CPU time 1.25 seconds
Started May 09 02:28:48 PM PDT 24
Finished May 09 02:28:52 PM PDT 24
Peak memory 219624 kb
Host smart-03d1fc17-5d47-4b7c-9bf1-52aa4a5c1628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148517094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.4148517094
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert_test.1067331365
Short name T411
Test name
Test status
Simulation time 17987814 ps
CPU time 0.99 seconds
Started May 09 02:25:27 PM PDT 24
Finished May 09 02:25:30 PM PDT 24
Peak memory 206560 kb
Host smart-c5b70f12-3df2-498e-ad59-a37a653b4047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067331365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1067331365
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3815181364
Short name T684
Test name
Test status
Simulation time 20957313 ps
CPU time 0.82 seconds
Started May 09 02:25:23 PM PDT 24
Finished May 09 02:25:24 PM PDT 24
Peak memory 215208 kb
Host smart-3f8e8008-4dad-4914-a209-5d8ab3006858
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815181364 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3815181364
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3097455641
Short name T109
Test name
Test status
Simulation time 74582672 ps
CPU time 1.07 seconds
Started May 09 02:25:36 PM PDT 24
Finished May 09 02:25:39 PM PDT 24
Peak memory 216688 kb
Host smart-8d10aaf2-215a-438b-b1f9-c5dbd613b749
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097455641 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3097455641
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.295511084
Short name T612
Test name
Test status
Simulation time 47669429 ps
CPU time 0.86 seconds
Started May 09 02:25:24 PM PDT 24
Finished May 09 02:25:26 PM PDT 24
Peak memory 218148 kb
Host smart-a547e20b-c721-4c04-8992-c4339de6eef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295511084 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.295511084
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1203420784
Short name T693
Test name
Test status
Simulation time 33333652 ps
CPU time 1.16 seconds
Started May 09 02:25:32 PM PDT 24
Finished May 09 02:25:35 PM PDT 24
Peak memory 217256 kb
Host smart-9a2380dd-110b-4731-a040-df0c88103d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203420784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1203420784
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2071465705
Short name T32
Test name
Test status
Simulation time 29288413 ps
CPU time 0.88 seconds
Started May 09 02:25:28 PM PDT 24
Finished May 09 02:25:31 PM PDT 24
Peak memory 215652 kb
Host smart-ba392cd2-b866-4c22-90c1-fab127a8dbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071465705 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2071465705
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3466655897
Short name T253
Test name
Test status
Simulation time 40852690 ps
CPU time 0.92 seconds
Started May 09 02:25:28 PM PDT 24
Finished May 09 02:25:31 PM PDT 24
Peak memory 206988 kb
Host smart-4deca8ee-e6ae-4bca-a3c2-107288eb985a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466655897 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3466655897
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1497369688
Short name T59
Test name
Test status
Simulation time 532489256 ps
CPU time 8.27 seconds
Started May 09 02:25:27 PM PDT 24
Finished May 09 02:25:38 PM PDT 24
Peak memory 243880 kb
Host smart-fa59ab05-f563-43cb-bb48-fca2666eaa9f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497369688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1497369688
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.4095236013
Short name T553
Test name
Test status
Simulation time 16630435 ps
CPU time 1.04 seconds
Started May 09 02:25:41 PM PDT 24
Finished May 09 02:25:43 PM PDT 24
Peak memory 215176 kb
Host smart-a6274cfc-8a8f-4d5a-8a8c-bbf719557b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095236013 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.4095236013
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.639836398
Short name T634
Test name
Test status
Simulation time 1353664652 ps
CPU time 4.07 seconds
Started May 09 02:25:39 PM PDT 24
Finished May 09 02:25:45 PM PDT 24
Peak memory 216896 kb
Host smart-860f731e-f229-42f5-8d29-813a3c541db3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639836398 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.639836398
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3777652186
Short name T764
Test name
Test status
Simulation time 82795368088 ps
CPU time 491.84 seconds
Started May 09 02:25:28 PM PDT 24
Finished May 09 02:33:43 PM PDT 24
Peak memory 223536 kb
Host smart-fda27c02-0de6-49e3-8bc6-abff4eb6e6d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777652186 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3777652186
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.4263025490
Short name T255
Test name
Test status
Simulation time 29196996 ps
CPU time 1.3 seconds
Started May 09 02:26:06 PM PDT 24
Finished May 09 02:26:11 PM PDT 24
Peak memory 215604 kb
Host smart-aa9a3e9c-ff01-4182-aaea-89154a17ccb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263025490 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.4263025490
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1882984880
Short name T61
Test name
Test status
Simulation time 15389234 ps
CPU time 0.95 seconds
Started May 09 02:25:56 PM PDT 24
Finished May 09 02:25:59 PM PDT 24
Peak memory 214772 kb
Host smart-cff5028e-1a57-41c5-9908-5bbee36777d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882984880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1882984880
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.2273198181
Short name T128
Test name
Test status
Simulation time 12702394 ps
CPU time 0.95 seconds
Started May 09 02:25:59 PM PDT 24
Finished May 09 02:26:02 PM PDT 24
Peak memory 216248 kb
Host smart-f5774fa1-0f08-4476-b287-29b290ba95c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273198181 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2273198181
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.544275719
Short name T360
Test name
Test status
Simulation time 76362029 ps
CPU time 1.22 seconds
Started May 09 02:26:06 PM PDT 24
Finished May 09 02:26:10 PM PDT 24
Peak memory 219548 kb
Host smart-39032727-1b9b-497e-8fbb-810450342870
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544275719 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.544275719
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.186053157
Short name T761
Test name
Test status
Simulation time 28086642 ps
CPU time 1.16 seconds
Started May 09 02:25:57 PM PDT 24
Finished May 09 02:26:01 PM PDT 24
Peak memory 223952 kb
Host smart-77f8a919-d0df-45cd-9e08-5d9548835f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186053157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.186053157
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1477037577
Short name T784
Test name
Test status
Simulation time 82300367 ps
CPU time 1.05 seconds
Started May 09 02:25:59 PM PDT 24
Finished May 09 02:26:02 PM PDT 24
Peak memory 217048 kb
Host smart-11bdbe96-369b-4470-8a5e-c49582594b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477037577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1477037577
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.2446841127
Short name T38
Test name
Test status
Simulation time 20314487 ps
CPU time 1.09 seconds
Started May 09 02:25:59 PM PDT 24
Finished May 09 02:26:03 PM PDT 24
Peak memory 215716 kb
Host smart-790abe89-e4fb-41d3-89e1-77985c5668af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446841127 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2446841127
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2990175099
Short name T22
Test name
Test status
Simulation time 18638000 ps
CPU time 1.07 seconds
Started May 09 02:26:01 PM PDT 24
Finished May 09 02:26:04 PM PDT 24
Peak memory 215212 kb
Host smart-3768d378-11e9-4e25-b94b-4923893a76b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990175099 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2990175099
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.983041531
Short name T690
Test name
Test status
Simulation time 1526848406 ps
CPU time 4.51 seconds
Started May 09 02:25:55 PM PDT 24
Finished May 09 02:26:02 PM PDT 24
Peak memory 216896 kb
Host smart-1fa868c4-7680-4f6d-b986-22ec6fd7ad71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983041531 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.983041531
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2317681571
Short name T190
Test name
Test status
Simulation time 117288280717 ps
CPU time 745.38 seconds
Started May 09 02:26:01 PM PDT 24
Finished May 09 02:38:29 PM PDT 24
Peak memory 220932 kb
Host smart-d589ec35-e66a-4214-bd55-793d7f33ee08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317681571 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2317681571
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/201.edn_genbits.8101671
Short name T459
Test name
Test status
Simulation time 53338079 ps
CPU time 1.43 seconds
Started May 09 02:28:58 PM PDT 24
Finished May 09 02:29:02 PM PDT 24
Peak memory 216960 kb
Host smart-9871b3d9-edbe-43cd-8793-bcc55ef6667a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8101671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.8101671
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3310471005
Short name T798
Test name
Test status
Simulation time 75114547 ps
CPU time 1.62 seconds
Started May 09 02:28:58 PM PDT 24
Finished May 09 02:29:02 PM PDT 24
Peak memory 219256 kb
Host smart-f508b22d-6d96-4467-9b2f-b820865b6ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310471005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3310471005
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1414643206
Short name T419
Test name
Test status
Simulation time 32850188 ps
CPU time 1.34 seconds
Started May 09 02:28:58 PM PDT 24
Finished May 09 02:29:01 PM PDT 24
Peak memory 219604 kb
Host smart-5a22b530-10ce-4665-b9f7-2e1bf8bfcbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414643206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1414643206
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2319981410
Short name T370
Test name
Test status
Simulation time 40125481 ps
CPU time 1.52 seconds
Started May 09 02:29:01 PM PDT 24
Finished May 09 02:29:05 PM PDT 24
Peak memory 219448 kb
Host smart-67530860-3cf3-4fed-901a-347d220b00f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319981410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2319981410
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.2337235233
Short name T368
Test name
Test status
Simulation time 38269137 ps
CPU time 1.53 seconds
Started May 09 02:28:57 PM PDT 24
Finished May 09 02:29:01 PM PDT 24
Peak memory 218012 kb
Host smart-b0ed414c-c167-4a68-8f8e-5d090c289bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337235233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.2337235233
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1039602697
Short name T332
Test name
Test status
Simulation time 33115334 ps
CPU time 1.4 seconds
Started May 09 02:28:57 PM PDT 24
Finished May 09 02:29:01 PM PDT 24
Peak memory 216828 kb
Host smart-82e9b02c-7a1b-4fd6-b263-f9a2b0db0294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039602697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1039602697
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3840037198
Short name T599
Test name
Test status
Simulation time 27656535 ps
CPU time 1.31 seconds
Started May 09 02:28:58 PM PDT 24
Finished May 09 02:29:01 PM PDT 24
Peak memory 216744 kb
Host smart-b946358c-1b97-48a5-93df-ea09deeeeed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840037198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3840037198
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2415752349
Short name T44
Test name
Test status
Simulation time 27582694 ps
CPU time 1.43 seconds
Started May 09 02:28:59 PM PDT 24
Finished May 09 02:29:03 PM PDT 24
Peak memory 217012 kb
Host smart-71a6a9ae-90db-4deb-b83d-f846b41ef991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415752349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2415752349
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3110291560
Short name T326
Test name
Test status
Simulation time 38397012 ps
CPU time 1.55 seconds
Started May 09 02:28:58 PM PDT 24
Finished May 09 02:29:01 PM PDT 24
Peak memory 219536 kb
Host smart-c2158850-5306-40d9-9c3c-167ca8f8779b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110291560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3110291560
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1074676478
Short name T140
Test name
Test status
Simulation time 220345867 ps
CPU time 1.29 seconds
Started May 09 02:26:06 PM PDT 24
Finished May 09 02:26:11 PM PDT 24
Peak memory 215600 kb
Host smart-c2ef902d-ba51-4d46-8d7c-0ddf8ce801ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074676478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1074676478
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3032918256
Short name T681
Test name
Test status
Simulation time 36053933 ps
CPU time 0.8 seconds
Started May 09 02:26:09 PM PDT 24
Finished May 09 02:26:12 PM PDT 24
Peak memory 206300 kb
Host smart-c3098c1f-4e36-4770-95c5-1d5c1373a0f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032918256 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3032918256
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1352265391
Short name T462
Test name
Test status
Simulation time 14401825 ps
CPU time 0.96 seconds
Started May 09 02:26:01 PM PDT 24
Finished May 09 02:26:05 PM PDT 24
Peak memory 216256 kb
Host smart-2e1a1cd2-4531-43e1-af69-ebf32ac67edd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352265391 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1352265391
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.889064386
Short name T353
Test name
Test status
Simulation time 208456472 ps
CPU time 1.2 seconds
Started May 09 02:26:07 PM PDT 24
Finished May 09 02:26:11 PM PDT 24
Peak memory 219268 kb
Host smart-809c357e-c6d9-4803-b3b5-95e2621c9bfc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889064386 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.889064386
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.1757968381
Short name T172
Test name
Test status
Simulation time 20601362 ps
CPU time 1.21 seconds
Started May 09 02:26:00 PM PDT 24
Finished May 09 02:26:03 PM PDT 24
Peak memory 229456 kb
Host smart-4bff8c48-cb07-4d76-b90c-341a078d33c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757968381 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1757968381
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2788946920
Short name T444
Test name
Test status
Simulation time 111258807 ps
CPU time 1.64 seconds
Started May 09 02:26:02 PM PDT 24
Finished May 09 02:26:06 PM PDT 24
Peak memory 218036 kb
Host smart-f0555aaf-a052-4fb8-82a2-6a777f1f1e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788946920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2788946920
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.661472706
Short name T395
Test name
Test status
Simulation time 21161087 ps
CPU time 1.26 seconds
Started May 09 02:26:01 PM PDT 24
Finished May 09 02:26:05 PM PDT 24
Peak memory 223888 kb
Host smart-79459b04-2378-4fa6-8106-0dad12d62c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661472706 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.661472706
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2058881261
Short name T470
Test name
Test status
Simulation time 23738868 ps
CPU time 0.87 seconds
Started May 09 02:25:57 PM PDT 24
Finished May 09 02:26:01 PM PDT 24
Peak memory 215188 kb
Host smart-6a58ca5b-261b-43bb-860b-8b9c5d6012b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058881261 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2058881261
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3286264120
Short name T816
Test name
Test status
Simulation time 169920914 ps
CPU time 2.65 seconds
Started May 09 02:26:00 PM PDT 24
Finished May 09 02:26:05 PM PDT 24
Peak memory 218184 kb
Host smart-1a633cb0-82a7-45af-9461-7c54300ed4ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286264120 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3286264120
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.609416484
Short name T838
Test name
Test status
Simulation time 337278059559 ps
CPU time 1132.94 seconds
Started May 09 02:26:02 PM PDT 24
Finished May 09 02:44:57 PM PDT 24
Peak memory 223584 kb
Host smart-36a27ed4-cc0f-48fc-a21a-26080702aa87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609416484 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.609416484
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3226918426
Short name T485
Test name
Test status
Simulation time 80380013 ps
CPU time 1.15 seconds
Started May 09 02:29:01 PM PDT 24
Finished May 09 02:29:05 PM PDT 24
Peak memory 216892 kb
Host smart-fd304f7a-ba4b-4811-b753-1abce18fe443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226918426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3226918426
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.224481069
Short name T272
Test name
Test status
Simulation time 101759096 ps
CPU time 1.29 seconds
Started May 09 02:29:01 PM PDT 24
Finished May 09 02:29:06 PM PDT 24
Peak memory 219376 kb
Host smart-a6e073a0-dca8-4ad6-aa74-42714f263b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224481069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.224481069
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2655187876
Short name T408
Test name
Test status
Simulation time 47011447 ps
CPU time 1.62 seconds
Started May 09 02:29:00 PM PDT 24
Finished May 09 02:29:05 PM PDT 24
Peak memory 218172 kb
Host smart-15eddb3c-081c-4b02-91a7-457cd0b8f473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655187876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2655187876
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.298439973
Short name T584
Test name
Test status
Simulation time 153278080 ps
CPU time 3.25 seconds
Started May 09 02:29:07 PM PDT 24
Finished May 09 02:29:13 PM PDT 24
Peak memory 219848 kb
Host smart-99c19c4d-ed25-426a-bb34-f1d53bf255fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298439973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.298439973
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2821077819
Short name T773
Test name
Test status
Simulation time 70879713 ps
CPU time 1.35 seconds
Started May 09 02:28:58 PM PDT 24
Finished May 09 02:29:01 PM PDT 24
Peak memory 218672 kb
Host smart-cd25ea92-85f4-432c-b421-d00b97136265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821077819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2821077819
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3350812977
Short name T198
Test name
Test status
Simulation time 37674883 ps
CPU time 0.93 seconds
Started May 09 02:28:57 PM PDT 24
Finished May 09 02:29:00 PM PDT 24
Peak memory 216860 kb
Host smart-0b6bd5b6-c86b-47f9-a720-0c195ecbd59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350812977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3350812977
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2956395044
Short name T331
Test name
Test status
Simulation time 118937423 ps
CPU time 1.07 seconds
Started May 09 02:29:01 PM PDT 24
Finished May 09 02:29:05 PM PDT 24
Peak memory 216936 kb
Host smart-6aae2ef4-6dfd-4e49-96ba-84303d73f95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956395044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2956395044
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2414567279
Short name T69
Test name
Test status
Simulation time 62002013 ps
CPU time 1.16 seconds
Started May 09 02:29:02 PM PDT 24
Finished May 09 02:29:06 PM PDT 24
Peak memory 216976 kb
Host smart-ab927daf-8a27-4e9a-a441-53dfafa0cd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414567279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2414567279
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1724666023
Short name T660
Test name
Test status
Simulation time 60575827 ps
CPU time 2.42 seconds
Started May 09 02:28:58 PM PDT 24
Finished May 09 02:29:02 PM PDT 24
Peak memory 219252 kb
Host smart-5c8e9a06-4769-4a68-abda-0255b834df4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724666023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1724666023
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert_test.3313891855
Short name T499
Test name
Test status
Simulation time 29978714 ps
CPU time 0.88 seconds
Started May 09 02:26:06 PM PDT 24
Finished May 09 02:26:10 PM PDT 24
Peak memory 206564 kb
Host smart-19b5a9f9-f01f-4f6d-87c0-713902896de1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313891855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3313891855
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2795606480
Short name T810
Test name
Test status
Simulation time 80475243 ps
CPU time 0.98 seconds
Started May 09 02:26:12 PM PDT 24
Finished May 09 02:26:14 PM PDT 24
Peak memory 219204 kb
Host smart-42bef02b-ea7b-44dd-83fe-9554db9ff364
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795606480 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2795606480
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2701253374
Short name T486
Test name
Test status
Simulation time 31720909 ps
CPU time 0.9 seconds
Started May 09 02:26:06 PM PDT 24
Finished May 09 02:26:10 PM PDT 24
Peak memory 217980 kb
Host smart-b2a0885c-39f0-4db3-bd2b-9cbf1cced69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701253374 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2701253374
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.409976707
Short name T63
Test name
Test status
Simulation time 99012009 ps
CPU time 1.19 seconds
Started May 09 02:26:04 PM PDT 24
Finished May 09 02:26:08 PM PDT 24
Peak memory 217100 kb
Host smart-36d7f2a3-06ae-48e7-8748-3b9a5c3014ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409976707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.409976707
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3141180671
Short name T644
Test name
Test status
Simulation time 55565471 ps
CPU time 0.89 seconds
Started May 09 02:26:05 PM PDT 24
Finished May 09 02:26:09 PM PDT 24
Peak memory 215388 kb
Host smart-437a54de-e815-4d0c-bb06-285d5fa2ebfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141180671 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3141180671
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3323994254
Short name T635
Test name
Test status
Simulation time 98837321 ps
CPU time 0.89 seconds
Started May 09 02:26:07 PM PDT 24
Finished May 09 02:26:11 PM PDT 24
Peak memory 215140 kb
Host smart-b19ec260-55b6-4da9-8fa9-867b2cceff9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323994254 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3323994254
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.668759890
Short name T51
Test name
Test status
Simulation time 298503051 ps
CPU time 5.57 seconds
Started May 09 02:26:11 PM PDT 24
Finished May 09 02:26:18 PM PDT 24
Peak memory 216908 kb
Host smart-800d0c80-7973-42db-b309-4d57264dfdfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668759890 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.668759890
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3154892366
Short name T704
Test name
Test status
Simulation time 62790574197 ps
CPU time 348.54 seconds
Started May 09 02:26:11 PM PDT 24
Finished May 09 02:32:02 PM PDT 24
Peak memory 223484 kb
Host smart-8c170658-0790-48df-a53a-62464f6097c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154892366 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3154892366
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1545128581
Short name T440
Test name
Test status
Simulation time 45590228 ps
CPU time 1.34 seconds
Started May 09 02:29:01 PM PDT 24
Finished May 09 02:29:06 PM PDT 24
Peak memory 219500 kb
Host smart-c7bb1d8a-c85b-4e50-a9ba-a6e19d03e88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545128581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1545128581
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3355089139
Short name T281
Test name
Test status
Simulation time 144149798 ps
CPU time 1.91 seconds
Started May 09 02:29:00 PM PDT 24
Finished May 09 02:29:04 PM PDT 24
Peak memory 217252 kb
Host smart-815912aa-7fb7-41c9-a7d6-3f468df0896e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355089139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3355089139
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2794445561
Short name T432
Test name
Test status
Simulation time 49412553 ps
CPU time 1.37 seconds
Started May 09 02:28:58 PM PDT 24
Finished May 09 02:29:02 PM PDT 24
Peak memory 216832 kb
Host smart-ec0977a8-a328-4cbb-9ba2-8fe04d5752b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794445561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2794445561
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.5981462
Short name T558
Test name
Test status
Simulation time 37582099 ps
CPU time 1.5 seconds
Started May 09 02:29:00 PM PDT 24
Finished May 09 02:29:05 PM PDT 24
Peak memory 218240 kb
Host smart-0c67798d-e083-4739-bd92-2a2d1089cd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5981462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.5981462
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3595425375
Short name T12
Test name
Test status
Simulation time 42006746 ps
CPU time 1.5 seconds
Started May 09 02:29:01 PM PDT 24
Finished May 09 02:29:05 PM PDT 24
Peak memory 219568 kb
Host smart-2ac1a102-8284-461b-b2e5-5ead42016b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595425375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3595425375
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2120892458
Short name T830
Test name
Test status
Simulation time 73180277 ps
CPU time 1.28 seconds
Started May 09 02:28:59 PM PDT 24
Finished May 09 02:29:03 PM PDT 24
Peak memory 218200 kb
Host smart-025b12dd-a4c6-4159-9550-198051634896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120892458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2120892458
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2286018660
Short name T807
Test name
Test status
Simulation time 32030595 ps
CPU time 1.28 seconds
Started May 09 02:29:00 PM PDT 24
Finished May 09 02:29:05 PM PDT 24
Peak memory 216764 kb
Host smart-943d8071-6c40-4ca4-b471-8e2a0dc63898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286018660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2286018660
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2012635407
Short name T77
Test name
Test status
Simulation time 39918584 ps
CPU time 1.43 seconds
Started May 09 02:29:07 PM PDT 24
Finished May 09 02:29:11 PM PDT 24
Peak memory 215172 kb
Host smart-09e45065-e3e8-48a4-ad68-27c5f38d5fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012635407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2012635407
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1364306825
Short name T276
Test name
Test status
Simulation time 37137150 ps
CPU time 1.4 seconds
Started May 09 02:28:58 PM PDT 24
Finished May 09 02:29:02 PM PDT 24
Peak memory 216904 kb
Host smart-e2ec56df-07ab-4db6-a27f-4106a702468a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364306825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1364306825
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2489442552
Short name T409
Test name
Test status
Simulation time 56294461 ps
CPU time 1.77 seconds
Started May 09 02:28:58 PM PDT 24
Finished May 09 02:29:01 PM PDT 24
Peak memory 218080 kb
Host smart-02572563-1e3f-4bae-b7af-36e622c84f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489442552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2489442552
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.107015630
Short name T827
Test name
Test status
Simulation time 126081720 ps
CPU time 1.14 seconds
Started May 09 02:26:03 PM PDT 24
Finished May 09 02:26:06 PM PDT 24
Peak memory 215556 kb
Host smart-cded3ac0-8431-49cc-bf80-4f800b4dd95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107015630 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.107015630
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1819370170
Short name T713
Test name
Test status
Simulation time 42674692 ps
CPU time 0.83 seconds
Started May 09 02:26:12 PM PDT 24
Finished May 09 02:26:15 PM PDT 24
Peak memory 206276 kb
Host smart-e5bab0d4-3ba7-438f-8ba3-94425517fc75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819370170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1819370170
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2509515074
Short name T131
Test name
Test status
Simulation time 122286260 ps
CPU time 0.84 seconds
Started May 09 02:26:12 PM PDT 24
Finished May 09 02:26:15 PM PDT 24
Peak memory 216180 kb
Host smart-8f135eb6-3a48-42a2-a3e2-67c66f6ea52d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509515074 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2509515074
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3320944726
Short name T790
Test name
Test status
Simulation time 59330645 ps
CPU time 1.1 seconds
Started May 09 02:26:05 PM PDT 24
Finished May 09 02:26:09 PM PDT 24
Peak memory 217716 kb
Host smart-25cca93f-e19f-41f5-a8a6-ac3ed9951508
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320944726 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3320944726
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3770512376
Short name T160
Test name
Test status
Simulation time 44672759 ps
CPU time 1.24 seconds
Started May 09 02:26:05 PM PDT 24
Finished May 09 02:26:09 PM PDT 24
Peak memory 225456 kb
Host smart-8669aa0a-85aa-4c99-bd98-73a9ebf21e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770512376 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3770512376
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2397715672
Short name T796
Test name
Test status
Simulation time 84666932 ps
CPU time 1.33 seconds
Started May 09 02:26:04 PM PDT 24
Finished May 09 02:26:07 PM PDT 24
Peak memory 219636 kb
Host smart-17d4917d-400d-4d6b-8f97-2a1da5ec78c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397715672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2397715672
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.62889099
Short name T402
Test name
Test status
Simulation time 21334639 ps
CPU time 1.11 seconds
Started May 09 02:26:06 PM PDT 24
Finished May 09 02:26:10 PM PDT 24
Peak memory 215696 kb
Host smart-08b0de69-ba73-4792-b4d2-50d317c143d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62889099 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.62889099
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2016895287
Short name T730
Test name
Test status
Simulation time 30893257 ps
CPU time 0.95 seconds
Started May 09 02:26:08 PM PDT 24
Finished May 09 02:26:11 PM PDT 24
Peak memory 215288 kb
Host smart-2d5aa46b-0c12-4cce-a6ba-33a48c32f3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016895287 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2016895287
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1815202899
Short name T261
Test name
Test status
Simulation time 781458691 ps
CPU time 3.36 seconds
Started May 09 02:26:09 PM PDT 24
Finished May 09 02:26:15 PM PDT 24
Peak memory 215216 kb
Host smart-c214c274-fe97-4df6-bb2f-78e0900f6053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815202899 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1815202899
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.932054346
Short name T828
Test name
Test status
Simulation time 71182948710 ps
CPU time 434.41 seconds
Started May 09 02:26:12 PM PDT 24
Finished May 09 02:33:28 PM PDT 24
Peak memory 218128 kb
Host smart-25ed92ef-b2a8-496c-9a21-b9c91192b5a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932054346 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.932054346
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1078670215
Short name T314
Test name
Test status
Simulation time 58488476 ps
CPU time 1.1 seconds
Started May 09 02:29:02 PM PDT 24
Finished May 09 02:29:07 PM PDT 24
Peak memory 217084 kb
Host smart-e42c28b6-02c0-4188-9800-d3a4cfb878dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078670215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1078670215
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2872207206
Short name T388
Test name
Test status
Simulation time 24419447 ps
CPU time 1.18 seconds
Started May 09 02:29:01 PM PDT 24
Finished May 09 02:29:05 PM PDT 24
Peak memory 216884 kb
Host smart-b1267592-a791-4ead-ae2c-fd06a59f5a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872207206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2872207206
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3330415416
Short name T275
Test name
Test status
Simulation time 143122133 ps
CPU time 2.39 seconds
Started May 09 02:29:02 PM PDT 24
Finished May 09 02:29:08 PM PDT 24
Peak memory 219152 kb
Host smart-50029e72-b439-4044-97e4-1bf44f55ecad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330415416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3330415416
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3923300496
Short name T20
Test name
Test status
Simulation time 39448019 ps
CPU time 1.4 seconds
Started May 09 02:29:03 PM PDT 24
Finished May 09 02:29:08 PM PDT 24
Peak memory 215200 kb
Host smart-5119bd51-0ca6-4fb1-aadc-663b955f7688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923300496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3923300496
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.374412664
Short name T359
Test name
Test status
Simulation time 77622075 ps
CPU time 1.8 seconds
Started May 09 02:29:02 PM PDT 24
Finished May 09 02:29:08 PM PDT 24
Peak memory 218204 kb
Host smart-c7e69197-01a2-4a0b-b05c-fd0c2b44de02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374412664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.374412664
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3215863372
Short name T426
Test name
Test status
Simulation time 65585655 ps
CPU time 1.48 seconds
Started May 09 02:28:58 PM PDT 24
Finished May 09 02:29:02 PM PDT 24
Peak memory 217960 kb
Host smart-bd97a807-b617-4e07-8b79-4f6f6c131272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215863372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3215863372
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2087781811
Short name T441
Test name
Test status
Simulation time 60924687 ps
CPU time 2.1 seconds
Started May 09 02:29:01 PM PDT 24
Finished May 09 02:29:06 PM PDT 24
Peak memory 219660 kb
Host smart-8a98ed40-abf9-4472-a9c4-656e109ec86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087781811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2087781811
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1562496365
Short name T639
Test name
Test status
Simulation time 37145144 ps
CPU time 1.41 seconds
Started May 09 02:29:07 PM PDT 24
Finished May 09 02:29:11 PM PDT 24
Peak memory 218260 kb
Host smart-236b3127-8c55-4941-8284-6a0547cc971f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562496365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1562496365
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.4191838653
Short name T762
Test name
Test status
Simulation time 295423636 ps
CPU time 1.49 seconds
Started May 09 02:29:01 PM PDT 24
Finished May 09 02:29:06 PM PDT 24
Peak memory 218628 kb
Host smart-43b7325d-2894-44d8-b117-5f1b01e39d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191838653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.4191838653
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.4248604935
Short name T199
Test name
Test status
Simulation time 31746446 ps
CPU time 1.31 seconds
Started May 09 02:29:02 PM PDT 24
Finished May 09 02:29:07 PM PDT 24
Peak memory 216916 kb
Host smart-835ff414-32b6-4186-a88f-008f2c961da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248604935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.4248604935
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert_test.3833515527
Short name T727
Test name
Test status
Simulation time 93672376 ps
CPU time 1.11 seconds
Started May 09 02:26:06 PM PDT 24
Finished May 09 02:26:10 PM PDT 24
Peak memory 206648 kb
Host smart-00fef4f9-e9c1-43ef-8154-0302fbdf85ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833515527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3833515527
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2800453055
Short name T376
Test name
Test status
Simulation time 123815369 ps
CPU time 1.29 seconds
Started May 09 02:26:04 PM PDT 24
Finished May 09 02:26:08 PM PDT 24
Peak memory 216720 kb
Host smart-24dc2a41-7a16-41d4-9a4a-cec3587a17de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800453055 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2800453055
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2820144404
Short name T17
Test name
Test status
Simulation time 25763432 ps
CPU time 0.97 seconds
Started May 09 02:26:04 PM PDT 24
Finished May 09 02:26:08 PM PDT 24
Peak memory 232596 kb
Host smart-fc1de510-90da-459e-bde9-086bbf9a6dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820144404 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2820144404
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2920111637
Short name T484
Test name
Test status
Simulation time 103516762 ps
CPU time 1.61 seconds
Started May 09 02:26:07 PM PDT 24
Finished May 09 02:26:11 PM PDT 24
Peak memory 218668 kb
Host smart-c042502a-bb61-4f7b-abd2-671cd2f0a40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920111637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2920111637
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.905570283
Short name T656
Test name
Test status
Simulation time 24610587 ps
CPU time 1.14 seconds
Started May 09 02:26:13 PM PDT 24
Finished May 09 02:26:16 PM PDT 24
Peak memory 223876 kb
Host smart-662ff98f-4674-4569-a0ee-7a22bd3313e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905570283 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.905570283
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3390016283
Short name T57
Test name
Test status
Simulation time 22889179 ps
CPU time 0.87 seconds
Started May 09 02:26:11 PM PDT 24
Finished May 09 02:26:14 PM PDT 24
Peak memory 215132 kb
Host smart-6d6dbbce-a7e3-47ef-809b-1dcce17cb561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390016283 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3390016283
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1392798754
Short name T573
Test name
Test status
Simulation time 769055041 ps
CPU time 4.04 seconds
Started May 09 02:26:05 PM PDT 24
Finished May 09 02:26:12 PM PDT 24
Peak memory 219768 kb
Host smart-4c81f072-edab-4b65-a351-377e6f834158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392798754 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1392798754
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3697756256
Short name T405
Test name
Test status
Simulation time 153547596619 ps
CPU time 585.39 seconds
Started May 09 02:26:06 PM PDT 24
Finished May 09 02:35:54 PM PDT 24
Peak memory 220208 kb
Host smart-61d18180-7220-4c80-8891-50b369e3ad93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697756256 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3697756256
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1640149140
Short name T705
Test name
Test status
Simulation time 27484582 ps
CPU time 1.46 seconds
Started May 09 02:29:08 PM PDT 24
Finished May 09 02:29:13 PM PDT 24
Peak memory 217024 kb
Host smart-7b832b44-4f3b-4e00-a75b-ee940f7bbc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640149140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1640149140
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3964376097
Short name T673
Test name
Test status
Simulation time 176022902 ps
CPU time 1.32 seconds
Started May 09 02:29:02 PM PDT 24
Finished May 09 02:29:07 PM PDT 24
Peak memory 217316 kb
Host smart-2deba12d-decb-4b1b-93d3-0a397165bc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964376097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3964376097
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1793804001
Short name T282
Test name
Test status
Simulation time 91468335 ps
CPU time 1.23 seconds
Started May 09 02:29:06 PM PDT 24
Finished May 09 02:29:10 PM PDT 24
Peak memory 219636 kb
Host smart-155f2d44-d244-40fc-9469-fdf1d5d6c8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793804001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1793804001
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1862105907
Short name T691
Test name
Test status
Simulation time 59955973 ps
CPU time 1.66 seconds
Started May 09 02:29:11 PM PDT 24
Finished May 09 02:29:18 PM PDT 24
Peak memory 218160 kb
Host smart-2706c249-8b32-4ab2-be62-44042264e0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862105907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1862105907
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3816873930
Short name T630
Test name
Test status
Simulation time 32331096 ps
CPU time 1.38 seconds
Started May 09 02:29:09 PM PDT 24
Finished May 09 02:29:14 PM PDT 24
Peak memory 217932 kb
Host smart-67b0af16-9c40-4d54-a945-e8fcf2e5f7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816873930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3816873930
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3704389385
Short name T454
Test name
Test status
Simulation time 83582103 ps
CPU time 1.46 seconds
Started May 09 02:29:12 PM PDT 24
Finished May 09 02:29:19 PM PDT 24
Peak memory 218464 kb
Host smart-3a20614f-d3f8-4748-bb46-b667e0feb1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704389385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3704389385
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.874119806
Short name T536
Test name
Test status
Simulation time 51117172 ps
CPU time 1.55 seconds
Started May 09 02:29:12 PM PDT 24
Finished May 09 02:29:19 PM PDT 24
Peak memory 216788 kb
Host smart-b598b790-4dea-4a9e-ae6f-540b918242e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874119806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.874119806
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.561333217
Short name T420
Test name
Test status
Simulation time 86554148 ps
CPU time 1.37 seconds
Started May 09 02:29:10 PM PDT 24
Finished May 09 02:29:16 PM PDT 24
Peak memory 218596 kb
Host smart-03fe31b4-4442-4e04-9230-66199bddf2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561333217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.561333217
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2960922028
Short name T774
Test name
Test status
Simulation time 331496556 ps
CPU time 3.23 seconds
Started May 09 02:29:11 PM PDT 24
Finished May 09 02:29:19 PM PDT 24
Peak memory 217104 kb
Host smart-a58a2050-9795-4dea-9813-dcad483e8989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960922028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2960922028
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.75638290
Short name T283
Test name
Test status
Simulation time 183644842 ps
CPU time 2.15 seconds
Started May 09 02:29:15 PM PDT 24
Finished May 09 02:29:23 PM PDT 24
Peak memory 220068 kb
Host smart-94033e52-9ad3-43ff-99bd-2a37029a1c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75638290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.75638290
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert_test.1462281403
Short name T747
Test name
Test status
Simulation time 16169114 ps
CPU time 0.91 seconds
Started May 09 02:26:15 PM PDT 24
Finished May 09 02:26:18 PM PDT 24
Peak memory 206584 kb
Host smart-072ed33f-93b6-4a3c-ac61-9148f6476f7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462281403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1462281403
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2048787334
Short name T416
Test name
Test status
Simulation time 21225778 ps
CPU time 0.88 seconds
Started May 09 02:26:04 PM PDT 24
Finished May 09 02:26:08 PM PDT 24
Peak memory 215936 kb
Host smart-4c6b582d-dbc7-4c3e-841e-54df0a812a02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048787334 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2048787334
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.3091199407
Short name T64
Test name
Test status
Simulation time 33843716 ps
CPU time 0.93 seconds
Started May 09 02:26:08 PM PDT 24
Finished May 09 02:26:11 PM PDT 24
Peak memory 218108 kb
Host smart-1a249f49-9685-49e2-ae2b-2cc828d54891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091199407 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3091199407
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1489878384
Short name T590
Test name
Test status
Simulation time 74126634 ps
CPU time 1.11 seconds
Started May 09 02:26:06 PM PDT 24
Finished May 09 02:26:10 PM PDT 24
Peak memory 216856 kb
Host smart-a8d41f47-2f55-4aa2-a479-163fe524f81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489878384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1489878384
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2862233401
Short name T732
Test name
Test status
Simulation time 22330101 ps
CPU time 1.08 seconds
Started May 09 02:26:08 PM PDT 24
Finished May 09 02:26:11 PM PDT 24
Peak memory 215332 kb
Host smart-3d9e408d-b418-4075-9876-c97f0a42f92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862233401 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2862233401
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2455597806
Short name T319
Test name
Test status
Simulation time 27992455 ps
CPU time 0.92 seconds
Started May 09 02:26:04 PM PDT 24
Finished May 09 02:26:08 PM PDT 24
Peak memory 215152 kb
Host smart-bfdb5ac3-7e75-4c9e-835a-b7666d675764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455597806 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2455597806
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2117794773
Short name T382
Test name
Test status
Simulation time 146748005 ps
CPU time 3.08 seconds
Started May 09 02:26:08 PM PDT 24
Finished May 09 02:26:13 PM PDT 24
Peak memory 215212 kb
Host smart-0f34a4ca-b733-4e41-bdea-4e2570a265a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117794773 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2117794773
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.590115405
Short name T186
Test name
Test status
Simulation time 16315319630 ps
CPU time 360.58 seconds
Started May 09 02:26:07 PM PDT 24
Finished May 09 02:32:11 PM PDT 24
Peak memory 217492 kb
Host smart-052ca628-4a98-4bb5-8185-3eadf7f6e10f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590115405 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.590115405
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.618255998
Short name T687
Test name
Test status
Simulation time 140318208 ps
CPU time 1.62 seconds
Started May 09 02:29:07 PM PDT 24
Finished May 09 02:29:12 PM PDT 24
Peak memory 218392 kb
Host smart-7a94179c-ddf9-4030-b93f-4441b4d4a8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618255998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.618255998
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1039319656
Short name T733
Test name
Test status
Simulation time 124746447 ps
CPU time 1.07 seconds
Started May 09 02:29:08 PM PDT 24
Finished May 09 02:29:13 PM PDT 24
Peak memory 216800 kb
Host smart-07360be4-8f7e-41fa-8984-696a5757c7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039319656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1039319656
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.4278047423
Short name T232
Test name
Test status
Simulation time 36883947 ps
CPU time 1.57 seconds
Started May 09 02:29:09 PM PDT 24
Finished May 09 02:29:15 PM PDT 24
Peak memory 218040 kb
Host smart-2cca8a00-2169-4240-a26b-6500a9ad6bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278047423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.4278047423
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.4138128091
Short name T447
Test name
Test status
Simulation time 85204628 ps
CPU time 1.13 seconds
Started May 09 02:29:17 PM PDT 24
Finished May 09 02:29:23 PM PDT 24
Peak memory 218132 kb
Host smart-9afc12a7-cc66-4880-ab3c-d32ca34afaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138128091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.4138128091
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3558361717
Short name T637
Test name
Test status
Simulation time 31538435 ps
CPU time 1.24 seconds
Started May 09 02:29:06 PM PDT 24
Finished May 09 02:29:11 PM PDT 24
Peak memory 216960 kb
Host smart-1b54c080-c049-44a1-928a-3869913771d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558361717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3558361717
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1568756351
Short name T145
Test name
Test status
Simulation time 54364844 ps
CPU time 1.23 seconds
Started May 09 02:29:08 PM PDT 24
Finished May 09 02:29:12 PM PDT 24
Peak memory 218292 kb
Host smart-9b5c7263-de6a-429b-a25a-f75afbc92cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568756351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1568756351
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.203707493
Short name T316
Test name
Test status
Simulation time 78236669 ps
CPU time 1.14 seconds
Started May 09 02:29:09 PM PDT 24
Finished May 09 02:29:15 PM PDT 24
Peak memory 216828 kb
Host smart-f4be8468-c4ff-463f-890d-64b1b3988733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203707493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.203707493
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1630788886
Short name T529
Test name
Test status
Simulation time 62287766 ps
CPU time 1.18 seconds
Started May 09 02:29:10 PM PDT 24
Finished May 09 02:29:16 PM PDT 24
Peak memory 218080 kb
Host smart-185be22d-4f40-47b6-bef8-ec7657ce549d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630788886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1630788886
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2137598142
Short name T312
Test name
Test status
Simulation time 45366753 ps
CPU time 1.52 seconds
Started May 09 02:29:08 PM PDT 24
Finished May 09 02:29:13 PM PDT 24
Peak memory 215212 kb
Host smart-80a25c99-6d07-48d4-9659-e54a01faea33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137598142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2137598142
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.4016237889
Short name T638
Test name
Test status
Simulation time 74659586 ps
CPU time 1.14 seconds
Started May 09 02:29:09 PM PDT 24
Finished May 09 02:29:15 PM PDT 24
Peak memory 215460 kb
Host smart-4f527872-b7cd-401e-8b6e-fa954e6272f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016237889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.4016237889
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert_test.2296396836
Short name T365
Test name
Test status
Simulation time 16979487 ps
CPU time 1.01 seconds
Started May 09 02:26:14 PM PDT 24
Finished May 09 02:26:17 PM PDT 24
Peak memory 206604 kb
Host smart-b35d8ff3-6b28-497e-8d02-b828224a429d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296396836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2296396836
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.926877165
Short name T651
Test name
Test status
Simulation time 152899007 ps
CPU time 0.99 seconds
Started May 09 02:26:14 PM PDT 24
Finished May 09 02:26:17 PM PDT 24
Peak memory 216684 kb
Host smart-8d091929-9d4d-4fa1-9291-48cfcc4fbacf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926877165 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_di
sable_auto_req_mode.926877165
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3234892659
Short name T389
Test name
Test status
Simulation time 92517133 ps
CPU time 0.84 seconds
Started May 09 02:26:17 PM PDT 24
Finished May 09 02:26:20 PM PDT 24
Peak memory 217880 kb
Host smart-7ed58bf7-ba19-4d91-9205-774702354fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234892659 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3234892659
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2280479089
Short name T650
Test name
Test status
Simulation time 32061247 ps
CPU time 1.09 seconds
Started May 09 02:26:14 PM PDT 24
Finished May 09 02:26:17 PM PDT 24
Peak memory 217068 kb
Host smart-c3b93dac-3ec6-420f-b10a-487714d0c452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280479089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2280479089
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2349230908
Short name T772
Test name
Test status
Simulation time 42458116 ps
CPU time 1 seconds
Started May 09 02:26:17 PM PDT 24
Finished May 09 02:26:19 PM PDT 24
Peak memory 223792 kb
Host smart-d29faa9c-fce9-4925-affe-8ee5e62da656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349230908 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2349230908
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2381004848
Short name T506
Test name
Test status
Simulation time 18143144 ps
CPU time 0.96 seconds
Started May 09 02:26:16 PM PDT 24
Finished May 09 02:26:19 PM PDT 24
Peak memory 215204 kb
Host smart-caf1df3f-7426-4e4e-8ca6-63aadb9773b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381004848 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2381004848
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2052482168
Short name T194
Test name
Test status
Simulation time 90228436 ps
CPU time 0.99 seconds
Started May 09 02:26:16 PM PDT 24
Finished May 09 02:26:19 PM PDT 24
Peak memory 206612 kb
Host smart-7014cc32-183d-40cb-8d69-9b9124a3a8e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052482168 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2052482168
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.969717978
Short name T364
Test name
Test status
Simulation time 293167593021 ps
CPU time 1441.08 seconds
Started May 09 02:26:14 PM PDT 24
Finished May 09 02:50:18 PM PDT 24
Peak memory 223984 kb
Host smart-df7d6dd2-226e-4eb5-b51c-37ab8e0b8ef3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969717978 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.969717978
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3029706547
Short name T288
Test name
Test status
Simulation time 43647125 ps
CPU time 1.16 seconds
Started May 09 02:29:07 PM PDT 24
Finished May 09 02:29:11 PM PDT 24
Peak memory 217060 kb
Host smart-b36db7d3-0b0d-42f6-b796-08278336943a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029706547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3029706547
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3040695539
Short name T240
Test name
Test status
Simulation time 44211328 ps
CPU time 1.69 seconds
Started May 09 02:29:16 PM PDT 24
Finished May 09 02:29:24 PM PDT 24
Peak memory 218324 kb
Host smart-2cfec819-33e3-42ef-b62c-902e70e0bb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040695539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3040695539
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.11918027
Short name T423
Test name
Test status
Simulation time 68400267 ps
CPU time 1.46 seconds
Started May 09 02:29:09 PM PDT 24
Finished May 09 02:29:14 PM PDT 24
Peak memory 218352 kb
Host smart-73c8d4e8-2ed3-41ae-ab18-ec031e03c661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11918027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.11918027
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3780469716
Short name T530
Test name
Test status
Simulation time 80822359 ps
CPU time 1.27 seconds
Started May 09 02:29:17 PM PDT 24
Finished May 09 02:29:24 PM PDT 24
Peak memory 219400 kb
Host smart-58748376-7b89-4ffc-a188-b3f4731e26b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780469716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3780469716
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.4035085283
Short name T386
Test name
Test status
Simulation time 133756644 ps
CPU time 1.46 seconds
Started May 09 02:29:08 PM PDT 24
Finished May 09 02:29:13 PM PDT 24
Peak memory 218944 kb
Host smart-a2551542-33b2-436e-aea0-9642f96a8f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035085283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.4035085283
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1294718310
Short name T585
Test name
Test status
Simulation time 45280014 ps
CPU time 1.74 seconds
Started May 09 02:29:15 PM PDT 24
Finished May 09 02:29:23 PM PDT 24
Peak memory 217044 kb
Host smart-6e06f491-dc6a-48e2-b09e-fc07eb28a5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294718310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1294718310
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3077266209
Short name T357
Test name
Test status
Simulation time 179873227 ps
CPU time 2.07 seconds
Started May 09 02:29:14 PM PDT 24
Finished May 09 02:29:22 PM PDT 24
Peak memory 219792 kb
Host smart-04e5f62a-089e-497a-8296-0a55f397b5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077266209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3077266209
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1865589285
Short name T703
Test name
Test status
Simulation time 39468802 ps
CPU time 1.14 seconds
Started May 09 02:29:20 PM PDT 24
Finished May 09 02:29:26 PM PDT 24
Peak memory 217128 kb
Host smart-b7939d81-c3a4-4a38-a5b2-66052abb83bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865589285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1865589285
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.190587505
Short name T466
Test name
Test status
Simulation time 80849015 ps
CPU time 1.48 seconds
Started May 09 02:29:10 PM PDT 24
Finished May 09 02:29:16 PM PDT 24
Peak memory 215196 kb
Host smart-01d73859-807c-4149-b109-412ae737aafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190587505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.190587505
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3700310303
Short name T124
Test name
Test status
Simulation time 45197300 ps
CPU time 1.13 seconds
Started May 09 02:26:18 PM PDT 24
Finished May 09 02:26:21 PM PDT 24
Peak memory 215688 kb
Host smart-2eaab05d-a7c7-4297-8d65-cffe1dc3ea3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700310303 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3700310303
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1158274678
Short name T831
Test name
Test status
Simulation time 79698910 ps
CPU time 0.94 seconds
Started May 09 02:26:14 PM PDT 24
Finished May 09 02:26:17 PM PDT 24
Peak memory 206596 kb
Host smart-e7a58f1b-5441-4430-9d52-b0227b8a2f45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158274678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1158274678
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1497260880
Short name T614
Test name
Test status
Simulation time 15134198 ps
CPU time 0.87 seconds
Started May 09 02:26:15 PM PDT 24
Finished May 09 02:26:18 PM PDT 24
Peak memory 216196 kb
Host smart-1824585b-f559-4f0f-9e22-bc0da59b101a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497260880 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1497260880
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1401590684
Short name T290
Test name
Test status
Simulation time 23889124 ps
CPU time 1.07 seconds
Started May 09 02:26:14 PM PDT 24
Finished May 09 02:26:17 PM PDT 24
Peak memory 217696 kb
Host smart-bc9be0f9-22e5-4d28-bacb-ccd5114617b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401590684 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1401590684
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.844488783
Short name T53
Test name
Test status
Simulation time 19987658 ps
CPU time 1.14 seconds
Started May 09 02:26:13 PM PDT 24
Finished May 09 02:26:16 PM PDT 24
Peak memory 223952 kb
Host smart-15d56b57-223b-421f-9933-227c0c53a1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844488783 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.844488783
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3980260015
Short name T81
Test name
Test status
Simulation time 55124908 ps
CPU time 1.32 seconds
Started May 09 02:26:22 PM PDT 24
Finished May 09 02:26:24 PM PDT 24
Peak memory 218124 kb
Host smart-8e412fd3-d854-446b-b041-62a99c19682f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980260015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3980260015
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2226617556
Short name T760
Test name
Test status
Simulation time 26739110 ps
CPU time 0.98 seconds
Started May 09 02:26:17 PM PDT 24
Finished May 09 02:26:21 PM PDT 24
Peak memory 215256 kb
Host smart-0e6ba907-c1d7-4846-9004-00ef1ae2572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226617556 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2226617556
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.262874183
Short name T686
Test name
Test status
Simulation time 30198328 ps
CPU time 1.01 seconds
Started May 09 02:26:14 PM PDT 24
Finished May 09 02:26:17 PM PDT 24
Peak memory 215172 kb
Host smart-795ae7ea-dc59-4991-b8f6-0b536f84de51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262874183 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.262874183
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1413664545
Short name T277
Test name
Test status
Simulation time 192138886 ps
CPU time 3.81 seconds
Started May 09 02:26:17 PM PDT 24
Finished May 09 02:26:23 PM PDT 24
Peak memory 217072 kb
Host smart-5726413a-e955-40be-9d61-279858610dbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413664545 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1413664545
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2324097910
Short name T654
Test name
Test status
Simulation time 72347228238 ps
CPU time 480.47 seconds
Started May 09 02:26:15 PM PDT 24
Finished May 09 02:34:17 PM PDT 24
Peak memory 223632 kb
Host smart-befb2166-c03d-403e-89ab-ed24d7418f2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324097910 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2324097910
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/271.edn_genbits.664958899
Short name T72
Test name
Test status
Simulation time 71135464 ps
CPU time 1.28 seconds
Started May 09 02:29:10 PM PDT 24
Finished May 09 02:29:16 PM PDT 24
Peak memory 218400 kb
Host smart-0313944a-034f-4962-b95b-1fd8d0378f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664958899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.664958899
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.25550129
Short name T701
Test name
Test status
Simulation time 59806610 ps
CPU time 1.54 seconds
Started May 09 02:29:20 PM PDT 24
Finished May 09 02:29:26 PM PDT 24
Peak memory 218364 kb
Host smart-72ba9f1f-6638-4dd0-b2d8-6c19b91cc6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25550129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.25550129
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1335196963
Short name T471
Test name
Test status
Simulation time 260124477 ps
CPU time 2.06 seconds
Started May 09 02:29:12 PM PDT 24
Finished May 09 02:29:19 PM PDT 24
Peak memory 217064 kb
Host smart-6a79049d-a7e1-4900-b380-a4379f4081bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335196963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1335196963
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3546998415
Short name T271
Test name
Test status
Simulation time 484884699 ps
CPU time 4.26 seconds
Started May 09 02:29:13 PM PDT 24
Finished May 09 02:29:22 PM PDT 24
Peak memory 217044 kb
Host smart-273587a6-0615-4d39-b37e-e18c981a466e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546998415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3546998415
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2686224541
Short name T11
Test name
Test status
Simulation time 123852324 ps
CPU time 2.68 seconds
Started May 09 02:29:12 PM PDT 24
Finished May 09 02:29:20 PM PDT 24
Peak memory 219692 kb
Host smart-f2ce8ba9-e05c-4a84-9c43-3594178e9cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686224541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2686224541
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3052659876
Short name T351
Test name
Test status
Simulation time 47873201 ps
CPU time 1.61 seconds
Started May 09 02:29:10 PM PDT 24
Finished May 09 02:29:17 PM PDT 24
Peak memory 218060 kb
Host smart-e7b1ff1b-2193-4320-bf48-644fe01d42e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052659876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3052659876
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.44356944
Short name T474
Test name
Test status
Simulation time 32765100 ps
CPU time 1.37 seconds
Started May 09 02:29:27 PM PDT 24
Finished May 09 02:29:32 PM PDT 24
Peak memory 218192 kb
Host smart-ffe6dd33-460d-428a-b884-96dcadf9220a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44356944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.44356944
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2662640762
Short name T227
Test name
Test status
Simulation time 58022875 ps
CPU time 1.32 seconds
Started May 09 02:29:20 PM PDT 24
Finished May 09 02:29:26 PM PDT 24
Peak memory 216836 kb
Host smart-8166f490-c301-4d4a-b3e8-fb0c2ccc121d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662640762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2662640762
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.320509763
Short name T556
Test name
Test status
Simulation time 88586640 ps
CPU time 1.41 seconds
Started May 09 02:29:28 PM PDT 24
Finished May 09 02:29:35 PM PDT 24
Peak memory 218144 kb
Host smart-0b731e07-ddaf-4715-8be1-627ca43f4cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320509763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.320509763
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2882429841
Short name T778
Test name
Test status
Simulation time 25202811 ps
CPU time 1.2 seconds
Started May 09 02:26:22 PM PDT 24
Finished May 09 02:26:25 PM PDT 24
Peak memory 215620 kb
Host smart-bd55670b-4215-4dec-b4c3-3a579ad1ca0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882429841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2882429841
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3347013356
Short name T363
Test name
Test status
Simulation time 14462023 ps
CPU time 0.92 seconds
Started May 09 02:26:31 PM PDT 24
Finished May 09 02:26:34 PM PDT 24
Peak memory 206484 kb
Host smart-fa52f3bd-29d9-47b8-bed5-5cf8b0c4ba06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347013356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3347013356
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.899016767
Short name T403
Test name
Test status
Simulation time 109959625 ps
CPU time 1.19 seconds
Started May 09 02:26:27 PM PDT 24
Finished May 09 02:26:30 PM PDT 24
Peak memory 216860 kb
Host smart-957c724d-86e5-4554-b9fb-977cbf2f2dc3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899016767 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.899016767
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.344435449
Short name T551
Test name
Test status
Simulation time 20925737 ps
CPU time 0.93 seconds
Started May 09 02:26:27 PM PDT 24
Finished May 09 02:26:30 PM PDT 24
Peak memory 218088 kb
Host smart-415795a1-d7d5-49fd-a2cb-13c3cdbeb73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344435449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.344435449
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1080035778
Short name T744
Test name
Test status
Simulation time 97594584 ps
CPU time 1.34 seconds
Started May 09 02:26:16 PM PDT 24
Finished May 09 02:26:19 PM PDT 24
Peak memory 217160 kb
Host smart-5dcb2f94-d1a1-48b1-8908-ebba2bcba870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080035778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1080035778
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.687993633
Short name T811
Test name
Test status
Simulation time 21653270 ps
CPU time 1.21 seconds
Started May 09 02:26:18 PM PDT 24
Finished May 09 02:26:21 PM PDT 24
Peak memory 224908 kb
Host smart-b38479d3-f84f-415d-af6c-8210fea1e146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687993633 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.687993633
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2706410561
Short name T498
Test name
Test status
Simulation time 56140710 ps
CPU time 0.89 seconds
Started May 09 02:26:20 PM PDT 24
Finished May 09 02:26:22 PM PDT 24
Peak memory 215108 kb
Host smart-e9a8834b-992a-4ef6-af4b-bd112f4495dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706410561 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2706410561
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3129899636
Short name T193
Test name
Test status
Simulation time 669429837 ps
CPU time 3.82 seconds
Started May 09 02:26:17 PM PDT 24
Finished May 09 02:26:23 PM PDT 24
Peak memory 218188 kb
Host smart-b0eb7ac3-ffcf-4406-a177-4198bfe3da04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129899636 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3129899636
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3252254559
Short name T809
Test name
Test status
Simulation time 248312781268 ps
CPU time 1492.93 seconds
Started May 09 02:26:21 PM PDT 24
Finished May 09 02:51:16 PM PDT 24
Peak memory 223436 kb
Host smart-0a262966-01ed-465d-ad99-8be067da6b28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252254559 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3252254559
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3079912481
Short name T452
Test name
Test status
Simulation time 20600588 ps
CPU time 1.12 seconds
Started May 09 02:29:18 PM PDT 24
Finished May 09 02:29:24 PM PDT 24
Peak memory 217192 kb
Host smart-87689ae9-62d9-4d4c-891a-96cb7c4e3bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079912481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3079912481
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1212777443
Short name T464
Test name
Test status
Simulation time 66984806 ps
CPU time 2.43 seconds
Started May 09 02:29:19 PM PDT 24
Finished May 09 02:29:26 PM PDT 24
Peak memory 215212 kb
Host smart-72e94112-180c-4fa4-acfb-5040275547df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212777443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1212777443
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2312812481
Short name T829
Test name
Test status
Simulation time 178839275 ps
CPU time 1.38 seconds
Started May 09 02:29:19 PM PDT 24
Finished May 09 02:29:25 PM PDT 24
Peak memory 217960 kb
Host smart-78437341-f761-4199-8f50-ac074215bd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312812481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2312812481
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.355797232
Short name T680
Test name
Test status
Simulation time 49013268 ps
CPU time 1.21 seconds
Started May 09 02:29:17 PM PDT 24
Finished May 09 02:29:24 PM PDT 24
Peak memory 218052 kb
Host smart-b444778b-ba85-45e4-9fd0-5ea97542edf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355797232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.355797232
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.656984602
Short name T297
Test name
Test status
Simulation time 86615876 ps
CPU time 1.03 seconds
Started May 09 02:29:22 PM PDT 24
Finished May 09 02:29:27 PM PDT 24
Peak memory 216880 kb
Host smart-e0de5809-1798-45f1-8503-ff12bac3a05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656984602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.656984602
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.719773984
Short name T292
Test name
Test status
Simulation time 46800749 ps
CPU time 2.04 seconds
Started May 09 02:29:22 PM PDT 24
Finished May 09 02:29:28 PM PDT 24
Peak memory 219884 kb
Host smart-4ff28a83-89e3-40c9-89dc-a1d8146d1e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719773984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.719773984
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.216407755
Short name T769
Test name
Test status
Simulation time 29978857 ps
CPU time 1.13 seconds
Started May 09 02:29:17 PM PDT 24
Finished May 09 02:29:24 PM PDT 24
Peak memory 218144 kb
Host smart-ee497298-6796-404c-a032-df0b1c933c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216407755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.216407755
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2585670850
Short name T799
Test name
Test status
Simulation time 55885795 ps
CPU time 1.78 seconds
Started May 09 02:29:28 PM PDT 24
Finished May 09 02:29:35 PM PDT 24
Peak memory 218212 kb
Host smart-db089c8c-2dbd-4bd1-8099-1805b433ee4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585670850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2585670850
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.1665947449
Short name T356
Test name
Test status
Simulation time 30452463 ps
CPU time 1.25 seconds
Started May 09 02:29:20 PM PDT 24
Finished May 09 02:29:26 PM PDT 24
Peak memory 219392 kb
Host smart-85ebaef7-90c2-4686-a30d-5b1c01405ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665947449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1665947449
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3182025682
Short name T278
Test name
Test status
Simulation time 68297084 ps
CPU time 1.09 seconds
Started May 09 02:29:26 PM PDT 24
Finished May 09 02:29:31 PM PDT 24
Peak memory 219036 kb
Host smart-012aa5b3-58f8-4382-8a0a-21ea4dddfbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182025682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3182025682
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert_test.1348246896
Short name T308
Test name
Test status
Simulation time 109539378 ps
CPU time 0.92 seconds
Started May 09 02:26:26 PM PDT 24
Finished May 09 02:26:29 PM PDT 24
Peak memory 206580 kb
Host smart-fa4a7025-025a-465a-abc6-9c99230708e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348246896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1348246896
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.4135740936
Short name T425
Test name
Test status
Simulation time 20229440 ps
CPU time 0.87 seconds
Started May 09 02:26:27 PM PDT 24
Finished May 09 02:26:30 PM PDT 24
Peak memory 215904 kb
Host smart-e0b7d66b-03af-4531-b1ab-5e4285dbded5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135740936 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.4135740936
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1648774668
Short name T453
Test name
Test status
Simulation time 30666138 ps
CPU time 1.18 seconds
Started May 09 02:26:25 PM PDT 24
Finished May 09 02:26:27 PM PDT 24
Peak memory 217832 kb
Host smart-5255e93b-e480-4232-98f7-a84ee8aec5d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648774668 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1648774668
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.501827292
Short name T753
Test name
Test status
Simulation time 81540310 ps
CPU time 1.2 seconds
Started May 09 02:26:29 PM PDT 24
Finished May 09 02:26:33 PM PDT 24
Peak memory 219672 kb
Host smart-d69f7dd8-9e2a-4be6-9b84-e7c1aa8cb493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501827292 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.501827292
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1761958107
Short name T570
Test name
Test status
Simulation time 93151968 ps
CPU time 1.13 seconds
Started May 09 02:26:29 PM PDT 24
Finished May 09 02:26:33 PM PDT 24
Peak memory 217052 kb
Host smart-ca40ac30-5f51-47be-aa53-76b8fdb7844b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761958107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1761958107
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2684665242
Short name T724
Test name
Test status
Simulation time 24408337 ps
CPU time 1.05 seconds
Started May 09 02:26:29 PM PDT 24
Finished May 09 02:26:32 PM PDT 24
Peak memory 223912 kb
Host smart-20977e78-3040-4f70-bbec-4043be2cf1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684665242 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2684665242
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1321576075
Short name T412
Test name
Test status
Simulation time 24412987 ps
CPU time 0.91 seconds
Started May 09 02:26:24 PM PDT 24
Finished May 09 02:26:26 PM PDT 24
Peak memory 215200 kb
Host smart-656fe4d8-ffc4-4330-bc7b-b4548f61d8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321576075 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1321576075
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2804406619
Short name T428
Test name
Test status
Simulation time 147181661 ps
CPU time 3.62 seconds
Started May 09 02:26:24 PM PDT 24
Finished May 09 02:26:29 PM PDT 24
Peak memory 219664 kb
Host smart-abff0596-6e1e-450e-b811-2500b5c647af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804406619 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2804406619
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3502298617
Short name T142
Test name
Test status
Simulation time 575736828438 ps
CPU time 2383.85 seconds
Started May 09 02:26:31 PM PDT 24
Finished May 09 03:06:18 PM PDT 24
Peak memory 231756 kb
Host smart-055dad55-b8d9-4fb4-9506-f9012c6492f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502298617 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3502298617
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.4132376794
Short name T619
Test name
Test status
Simulation time 126081755 ps
CPU time 2.74 seconds
Started May 09 02:29:26 PM PDT 24
Finished May 09 02:29:33 PM PDT 24
Peak memory 219840 kb
Host smart-012a25c6-03ab-4752-aaa7-d760bdb3e76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132376794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.4132376794
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2710277096
Short name T241
Test name
Test status
Simulation time 43301730 ps
CPU time 1.27 seconds
Started May 09 02:29:17 PM PDT 24
Finished May 09 02:29:24 PM PDT 24
Peak memory 218296 kb
Host smart-85a5dc1b-f7f7-4e8d-b70b-3cebb62f5505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710277096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2710277096
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1125200374
Short name T682
Test name
Test status
Simulation time 244830575 ps
CPU time 3.1 seconds
Started May 09 02:29:19 PM PDT 24
Finished May 09 02:29:27 PM PDT 24
Peak memory 219988 kb
Host smart-63a126a5-ed55-4b4a-ba06-165029a18603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125200374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1125200374
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.589585200
Short name T605
Test name
Test status
Simulation time 26428213 ps
CPU time 1.34 seconds
Started May 09 02:29:26 PM PDT 24
Finished May 09 02:29:30 PM PDT 24
Peak memory 217008 kb
Host smart-2fa8e3b5-1776-4b34-9131-7d09fb7d791b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589585200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.589585200
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.2364953543
Short name T613
Test name
Test status
Simulation time 49078865 ps
CPU time 1.5 seconds
Started May 09 02:29:28 PM PDT 24
Finished May 09 02:29:35 PM PDT 24
Peak memory 217092 kb
Host smart-29143f99-b3c9-46be-abcd-628bbc8e4d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364953543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2364953543
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2675492471
Short name T564
Test name
Test status
Simulation time 54638307 ps
CPU time 1.27 seconds
Started May 09 02:29:28 PM PDT 24
Finished May 09 02:29:35 PM PDT 24
Peak memory 218188 kb
Host smart-d26e843b-2d5d-4377-8f57-820b3efdc499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675492471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2675492471
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2513703679
Short name T658
Test name
Test status
Simulation time 43563868 ps
CPU time 1.19 seconds
Started May 09 02:29:19 PM PDT 24
Finished May 09 02:29:26 PM PDT 24
Peak memory 219736 kb
Host smart-dcaf417c-5b76-4868-b502-bbe89343ce29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513703679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2513703679
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1538204596
Short name T476
Test name
Test status
Simulation time 44094168 ps
CPU time 1.16 seconds
Started May 09 02:29:22 PM PDT 24
Finished May 09 02:29:27 PM PDT 24
Peak memory 219476 kb
Host smart-25445f10-cd60-4752-8d00-45cf4f1304e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538204596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1538204596
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.955110490
Short name T46
Test name
Test status
Simulation time 92751391 ps
CPU time 1.39 seconds
Started May 09 02:29:29 PM PDT 24
Finished May 09 02:29:35 PM PDT 24
Peak memory 219824 kb
Host smart-ebc66f15-6197-4add-baca-e4ba55832d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955110490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.955110490
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.536010760
Short name T671
Test name
Test status
Simulation time 39142721 ps
CPU time 1.24 seconds
Started May 09 02:29:27 PM PDT 24
Finished May 09 02:29:32 PM PDT 24
Peak memory 218240 kb
Host smart-49cb0200-3ca2-402d-8027-c177cd62ed3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536010760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.536010760
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3380243832
Short name T121
Test name
Test status
Simulation time 52590161 ps
CPU time 1.25 seconds
Started May 09 02:25:35 PM PDT 24
Finished May 09 02:25:37 PM PDT 24
Peak memory 215572 kb
Host smart-902bf4c1-8127-4ac1-8be6-134baff6a751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380243832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3380243832
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.637678933
Short name T477
Test name
Test status
Simulation time 35394891 ps
CPU time 1.05 seconds
Started May 09 02:25:26 PM PDT 24
Finished May 09 02:25:29 PM PDT 24
Peak memory 206668 kb
Host smart-199aa08e-8d68-477c-9553-ee0d93b753ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637678933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.637678933
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1503129672
Short name T115
Test name
Test status
Simulation time 77584508 ps
CPU time 0.84 seconds
Started May 09 02:25:26 PM PDT 24
Finished May 09 02:25:29 PM PDT 24
Peak memory 215276 kb
Host smart-c43db859-f9a3-4e83-b2b3-3046bfd62c2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503129672 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1503129672
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_err.2923454905
Short name T291
Test name
Test status
Simulation time 28568548 ps
CPU time 1 seconds
Started May 09 02:25:24 PM PDT 24
Finished May 09 02:25:27 PM PDT 24
Peak memory 218492 kb
Host smart-165ae4a3-ffd5-4a02-bd40-f83da4265574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923454905 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2923454905
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.276997465
Short name T446
Test name
Test status
Simulation time 46633294 ps
CPU time 1.3 seconds
Started May 09 02:25:24 PM PDT 24
Finished May 09 02:25:26 PM PDT 24
Peak memory 216828 kb
Host smart-9d9b9370-466f-4ea3-ae0b-8e44883cb32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276997465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.276997465
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3254619084
Short name T545
Test name
Test status
Simulation time 36957802 ps
CPU time 0.89 seconds
Started May 09 02:25:25 PM PDT 24
Finished May 09 02:25:27 PM PDT 24
Peak memory 215144 kb
Host smart-418806c3-17b5-49bc-8ee2-4f83024cea7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254619084 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3254619084
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1425473924
Short name T239
Test name
Test status
Simulation time 66511016 ps
CPU time 0.96 seconds
Started May 09 02:25:27 PM PDT 24
Finished May 09 02:25:30 PM PDT 24
Peak memory 206980 kb
Host smart-b23dcef2-fca7-4623-8bef-590d05b35fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425473924 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1425473924
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.147776514
Short name T603
Test name
Test status
Simulation time 23303292 ps
CPU time 0.91 seconds
Started May 09 02:25:24 PM PDT 24
Finished May 09 02:25:27 PM PDT 24
Peak memory 215176 kb
Host smart-41fc5250-dfd4-43db-8ca0-81569581f399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147776514 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.147776514
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1723839352
Short name T552
Test name
Test status
Simulation time 233974589 ps
CPU time 4.45 seconds
Started May 09 02:25:29 PM PDT 24
Finished May 09 02:25:35 PM PDT 24
Peak memory 219440 kb
Host smart-ff213675-a829-4353-a9ae-5873b95802c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723839352 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1723839352
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3875255606
Short name T777
Test name
Test status
Simulation time 63619702534 ps
CPU time 462.79 seconds
Started May 09 02:25:30 PM PDT 24
Finished May 09 02:33:15 PM PDT 24
Peak memory 218036 kb
Host smart-4eccf7a2-bf5d-4ef4-bdc8-f1945ea1a02d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875255606 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3875255606
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3019053947
Short name T657
Test name
Test status
Simulation time 26015692 ps
CPU time 1.27 seconds
Started May 09 02:26:28 PM PDT 24
Finished May 09 02:26:31 PM PDT 24
Peak memory 215552 kb
Host smart-c0dee84a-9d2f-4441-9f47-9743e941c78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019053947 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3019053947
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3996219109
Short name T349
Test name
Test status
Simulation time 22958861 ps
CPU time 0.95 seconds
Started May 09 02:26:37 PM PDT 24
Finished May 09 02:26:40 PM PDT 24
Peak memory 214760 kb
Host smart-0cf46fd7-acd8-422b-aec1-5eeda9a255f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996219109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3996219109
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2012031068
Short name T156
Test name
Test status
Simulation time 11425461 ps
CPU time 0.88 seconds
Started May 09 02:26:28 PM PDT 24
Finished May 09 02:26:31 PM PDT 24
Peak memory 216068 kb
Host smart-20088db4-eb7d-420a-8405-a26725d5001f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012031068 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2012031068
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_err.2452169089
Short name T113
Test name
Test status
Simulation time 29649731 ps
CPU time 1.33 seconds
Started May 09 02:26:29 PM PDT 24
Finished May 09 02:26:33 PM PDT 24
Peak memory 224752 kb
Host smart-09ad755e-65ba-4a1d-aafe-46ded6c0027a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452169089 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2452169089
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2747588408
Short name T418
Test name
Test status
Simulation time 69217860 ps
CPU time 1.5 seconds
Started May 09 02:26:28 PM PDT 24
Finished May 09 02:26:32 PM PDT 24
Peak memory 216948 kb
Host smart-09bb7734-99d9-4418-bda0-7dfbcf5d6966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747588408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2747588408
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3706113620
Short name T721
Test name
Test status
Simulation time 24846746 ps
CPU time 1 seconds
Started May 09 02:26:26 PM PDT 24
Finished May 09 02:26:29 PM PDT 24
Peak memory 215440 kb
Host smart-4fa87295-d406-42e0-818d-b13dc884443f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706113620 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3706113620
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.109859308
Short name T503
Test name
Test status
Simulation time 17608024 ps
CPU time 1.03 seconds
Started May 09 02:26:28 PM PDT 24
Finished May 09 02:26:31 PM PDT 24
Peak memory 215224 kb
Host smart-6f087e06-59e9-4af8-8aac-093d799228bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109859308 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.109859308
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1254211975
Short name T707
Test name
Test status
Simulation time 782775075 ps
CPU time 4.19 seconds
Started May 09 02:26:26 PM PDT 24
Finished May 09 02:26:32 PM PDT 24
Peak memory 216912 kb
Host smart-b155fdfe-9933-4167-a594-ff3414401e71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254211975 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1254211975
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1367733783
Short name T554
Test name
Test status
Simulation time 219410706124 ps
CPU time 872.54 seconds
Started May 09 02:26:25 PM PDT 24
Finished May 09 02:40:59 PM PDT 24
Peak memory 223772 kb
Host smart-743e3880-8657-4f5d-ac1a-607e5b6fd49e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367733783 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1367733783
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.694129013
Short name T803
Test name
Test status
Simulation time 67275960 ps
CPU time 1.27 seconds
Started May 09 02:26:37 PM PDT 24
Finished May 09 02:26:41 PM PDT 24
Peak memory 215512 kb
Host smart-84e9b995-3896-4633-b578-5f8604bfa145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694129013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.694129013
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.4279289601
Short name T479
Test name
Test status
Simulation time 30834352 ps
CPU time 0.92 seconds
Started May 09 02:26:37 PM PDT 24
Finished May 09 02:26:41 PM PDT 24
Peak memory 214712 kb
Host smart-2114dacd-3afe-4a61-8afa-d361d0931ade
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279289601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.4279289601
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3155020129
Short name T127
Test name
Test status
Simulation time 18477106 ps
CPU time 0.91 seconds
Started May 09 02:26:40 PM PDT 24
Finished May 09 02:26:45 PM PDT 24
Peak memory 216048 kb
Host smart-a4d6e093-efec-489f-b21b-93b9283ffe46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155020129 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3155020129
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.1754141121
Short name T141
Test name
Test status
Simulation time 35624586 ps
CPU time 1.08 seconds
Started May 09 02:26:37 PM PDT 24
Finished May 09 02:26:40 PM PDT 24
Peak memory 220464 kb
Host smart-953275cb-c700-4bcd-a9f1-15526be0ce70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754141121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1754141121
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.4102904520
Short name T449
Test name
Test status
Simulation time 62754797 ps
CPU time 1.28 seconds
Started May 09 02:26:41 PM PDT 24
Finished May 09 02:26:46 PM PDT 24
Peak memory 215200 kb
Host smart-3a3bd4a0-3dc3-42ec-be43-948bc8ddbceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102904520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.4102904520
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2406470084
Short name T1
Test name
Test status
Simulation time 39329068 ps
CPU time 0.93 seconds
Started May 09 02:26:37 PM PDT 24
Finished May 09 02:26:41 PM PDT 24
Peak memory 215452 kb
Host smart-eb78f337-a683-4be2-bdbe-2fb0a82d4a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406470084 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2406470084
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.119763827
Short name T706
Test name
Test status
Simulation time 15107279 ps
CPU time 1.01 seconds
Started May 09 02:26:39 PM PDT 24
Finished May 09 02:26:44 PM PDT 24
Peak memory 215180 kb
Host smart-e94753b8-d0b0-404e-b396-2fbb5e4bd53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119763827 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.119763827
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3365332708
Short name T153
Test name
Test status
Simulation time 538851393 ps
CPU time 2.63 seconds
Started May 09 02:26:38 PM PDT 24
Finished May 09 02:26:45 PM PDT 24
Peak memory 217044 kb
Host smart-e5949115-50a9-4433-abaf-7c483a70aa12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365332708 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3365332708
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1865471527
Short name T188
Test name
Test status
Simulation time 28606503483 ps
CPU time 309.85 seconds
Started May 09 02:26:42 PM PDT 24
Finished May 09 02:31:56 PM PDT 24
Peak memory 223284 kb
Host smart-e6903bd2-ada1-4b38-b7d0-a1b17d1691e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865471527 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1865471527
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert_test.2785241534
Short name T632
Test name
Test status
Simulation time 14579404 ps
CPU time 0.94 seconds
Started May 09 02:26:38 PM PDT 24
Finished May 09 02:26:42 PM PDT 24
Peak memory 214772 kb
Host smart-930fd428-bb96-46c0-9943-5ac0f3983f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785241534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2785241534
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1379957527
Short name T132
Test name
Test status
Simulation time 56973353 ps
CPU time 0.88 seconds
Started May 09 02:26:41 PM PDT 24
Finished May 09 02:26:46 PM PDT 24
Peak memory 216112 kb
Host smart-29cf3f00-137a-43e4-ad85-ef6ddc301905
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379957527 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1379957527
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.906275238
Short name T82
Test name
Test status
Simulation time 20048710 ps
CPU time 1.16 seconds
Started May 09 02:26:39 PM PDT 24
Finished May 09 02:26:44 PM PDT 24
Peak memory 219576 kb
Host smart-941866a7-0789-449f-8089-5b012be3c930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906275238 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.906275238
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3273896118
Short name T745
Test name
Test status
Simulation time 47999644 ps
CPU time 1.3 seconds
Started May 09 02:26:36 PM PDT 24
Finished May 09 02:26:39 PM PDT 24
Peak memory 218280 kb
Host smart-045dced0-56ee-492e-8a69-599dbf1e693d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273896118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3273896118
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.4136576997
Short name T456
Test name
Test status
Simulation time 24293174 ps
CPU time 0.98 seconds
Started May 09 02:26:40 PM PDT 24
Finished May 09 02:26:45 PM PDT 24
Peak memory 215436 kb
Host smart-2bf215d3-5a43-4478-af05-0bf622d70cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136576997 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.4136576997
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.623038448
Short name T776
Test name
Test status
Simulation time 27519896 ps
CPU time 0.98 seconds
Started May 09 02:26:36 PM PDT 24
Finished May 09 02:26:38 PM PDT 24
Peak memory 215128 kb
Host smart-9d726317-79ee-48db-b9d5-93491096ef25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623038448 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.623038448
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.4206557758
Short name T195
Test name
Test status
Simulation time 275402888 ps
CPU time 5.11 seconds
Started May 09 02:26:37 PM PDT 24
Finished May 09 02:26:44 PM PDT 24
Peak memory 219540 kb
Host smart-2614ccd4-e391-44df-a865-562d433fbbcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206557758 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.4206557758
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3628711053
Short name T185
Test name
Test status
Simulation time 38492486500 ps
CPU time 876.97 seconds
Started May 09 02:26:38 PM PDT 24
Finished May 09 02:41:19 PM PDT 24
Peak memory 223568 kb
Host smart-f3a7e75c-2594-4104-8630-efd278358d0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628711053 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3628711053
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.134305382
Short name T697
Test name
Test status
Simulation time 162948563 ps
CPU time 1.18 seconds
Started May 09 02:26:40 PM PDT 24
Finished May 09 02:26:45 PM PDT 24
Peak memory 215560 kb
Host smart-66ab401b-0493-4ff6-8037-558caaf337b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134305382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.134305382
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.82837233
Short name T542
Test name
Test status
Simulation time 32564683 ps
CPU time 0.95 seconds
Started May 09 02:26:42 PM PDT 24
Finished May 09 02:26:46 PM PDT 24
Peak memory 206480 kb
Host smart-fa64e8b8-25da-4722-8d6a-e9d49eddfbbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82837233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.82837233
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.319773921
Short name T129
Test name
Test status
Simulation time 21036953 ps
CPU time 0.86 seconds
Started May 09 02:26:42 PM PDT 24
Finished May 09 02:26:46 PM PDT 24
Peak memory 216000 kb
Host smart-0a528b24-3c86-468b-a7b5-6135fa329295
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319773921 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.319773921
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_err.1975896349
Short name T112
Test name
Test status
Simulation time 21444699 ps
CPU time 1.14 seconds
Started May 09 02:26:42 PM PDT 24
Finished May 09 02:26:46 PM PDT 24
Peak memory 223840 kb
Host smart-f94bd92e-6d75-49bd-9c3d-d234dfd20cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975896349 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1975896349
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3110150011
Short name T47
Test name
Test status
Simulation time 36096065 ps
CPU time 1.47 seconds
Started May 09 02:26:38 PM PDT 24
Finished May 09 02:26:43 PM PDT 24
Peak memory 219640 kb
Host smart-0335b15a-a4f0-4bbd-8f51-bb68ca5bc325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110150011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3110150011
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2797617025
Short name T33
Test name
Test status
Simulation time 24960923 ps
CPU time 0.86 seconds
Started May 09 02:26:42 PM PDT 24
Finished May 09 02:26:46 PM PDT 24
Peak memory 215556 kb
Host smart-0ad82d5d-63c9-4b61-8911-798cd3806702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797617025 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2797617025
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1012956265
Short name T366
Test name
Test status
Simulation time 23335231 ps
CPU time 0.98 seconds
Started May 09 02:26:41 PM PDT 24
Finished May 09 02:26:46 PM PDT 24
Peak memory 215212 kb
Host smart-6cc1b02b-908c-4722-ae52-7c642a66d1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012956265 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1012956265
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3813347646
Short name T152
Test name
Test status
Simulation time 256858876 ps
CPU time 5.29 seconds
Started May 09 02:26:39 PM PDT 24
Finished May 09 02:26:48 PM PDT 24
Peak memory 219476 kb
Host smart-070e9529-2231-47a0-96e2-0ccb9a2c1c8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813347646 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3813347646
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3506157078
Short name T836
Test name
Test status
Simulation time 181815769763 ps
CPU time 2080.01 seconds
Started May 09 02:26:40 PM PDT 24
Finished May 09 03:01:24 PM PDT 24
Peak memory 225780 kb
Host smart-895c1b43-b046-4c76-a758-bfda81c0fb4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506157078 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3506157078
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2312152943
Short name T74
Test name
Test status
Simulation time 75874930 ps
CPU time 1.05 seconds
Started May 09 02:26:43 PM PDT 24
Finished May 09 02:26:47 PM PDT 24
Peak memory 215564 kb
Host smart-b8a180e9-7c0b-439c-a586-c9b5f548bbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312152943 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2312152943
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.87093271
Short name T329
Test name
Test status
Simulation time 18195118 ps
CPU time 0.86 seconds
Started May 09 02:26:50 PM PDT 24
Finished May 09 02:26:52 PM PDT 24
Peak memory 206748 kb
Host smart-b1ce7431-6b69-4031-9fdb-32fdb3c30e8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87093271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.87093271
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1988808066
Short name T157
Test name
Test status
Simulation time 14072305 ps
CPU time 0.88 seconds
Started May 09 02:26:44 PM PDT 24
Finished May 09 02:26:48 PM PDT 24
Peak memory 216264 kb
Host smart-e2070855-8e12-418e-83f4-5c094a5e0f42
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988808066 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1988808066
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1136606188
Short name T712
Test name
Test status
Simulation time 102668325 ps
CPU time 1.06 seconds
Started May 09 02:26:38 PM PDT 24
Finished May 09 02:26:43 PM PDT 24
Peak memory 216800 kb
Host smart-59483e2e-e15e-4ef1-a24d-5404e4ca4eb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136606188 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1136606188
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.4124898614
Short name T83
Test name
Test status
Simulation time 32893512 ps
CPU time 0.93 seconds
Started May 09 02:26:38 PM PDT 24
Finished May 09 02:26:41 PM PDT 24
Peak memory 219544 kb
Host smart-91e45c9f-bf0e-4adf-a68e-5b0ce4458276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124898614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.4124898614
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1338721329
Short name T544
Test name
Test status
Simulation time 59625906 ps
CPU time 1.17 seconds
Started May 09 02:26:37 PM PDT 24
Finished May 09 02:26:40 PM PDT 24
Peak memory 217060 kb
Host smart-0012a5f0-7919-48d3-9f55-c2bc399c5c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338721329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1338721329
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.3795792501
Short name T78
Test name
Test status
Simulation time 41116919 ps
CPU time 0.81 seconds
Started May 09 02:26:44 PM PDT 24
Finished May 09 02:26:48 PM PDT 24
Peak memory 215596 kb
Host smart-ae6d1f5b-a3cd-4dec-850f-d3521ce537c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795792501 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3795792501
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3708157179
Short name T475
Test name
Test status
Simulation time 27336334 ps
CPU time 0.94 seconds
Started May 09 02:26:42 PM PDT 24
Finished May 09 02:26:47 PM PDT 24
Peak memory 215164 kb
Host smart-dac32f09-7d44-4c84-b5ed-ffcd67c7787a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708157179 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3708157179
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1440082279
Short name T579
Test name
Test status
Simulation time 342304148 ps
CPU time 4.68 seconds
Started May 09 02:26:36 PM PDT 24
Finished May 09 02:26:43 PM PDT 24
Peak memory 218264 kb
Host smart-d6d61f54-a2f7-4094-8c3e-d8e7c4fdb3f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440082279 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1440082279
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2786179232
Short name T676
Test name
Test status
Simulation time 41150877498 ps
CPU time 264.01 seconds
Started May 09 02:26:39 PM PDT 24
Finished May 09 02:31:07 PM PDT 24
Peak memory 218704 kb
Host smart-b16316d0-8c31-4498-a851-8462bf01d802
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786179232 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2786179232
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.208604587
Short name T254
Test name
Test status
Simulation time 43564296 ps
CPU time 1.28 seconds
Started May 09 02:26:50 PM PDT 24
Finished May 09 02:26:54 PM PDT 24
Peak memory 215552 kb
Host smart-2598754e-3507-49e2-9bf3-18aafc0c103b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208604587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.208604587
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2226958142
Short name T327
Test name
Test status
Simulation time 16883493 ps
CPU time 0.93 seconds
Started May 09 02:26:51 PM PDT 24
Finished May 09 02:26:56 PM PDT 24
Peak memory 206568 kb
Host smart-9ffa302a-71e9-4077-a2e7-16e9ee51c61d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226958142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2226958142
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2626926718
Short name T596
Test name
Test status
Simulation time 40444899 ps
CPU time 1.14 seconds
Started May 09 02:26:50 PM PDT 24
Finished May 09 02:26:52 PM PDT 24
Peak memory 218080 kb
Host smart-0f3c4f4e-3a31-48d6-a886-bde180473564
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626926718 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2626926718
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.4016206567
Short name T488
Test name
Test status
Simulation time 23206760 ps
CPU time 0.96 seconds
Started May 09 02:26:50 PM PDT 24
Finished May 09 02:26:52 PM PDT 24
Peak memory 218248 kb
Host smart-88ee2d09-817a-4a8c-991e-bbfb8f31b9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016206567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.4016206567
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.4107616032
Short name T577
Test name
Test status
Simulation time 98476131 ps
CPU time 1.18 seconds
Started May 09 02:26:51 PM PDT 24
Finished May 09 02:26:55 PM PDT 24
Peak memory 218584 kb
Host smart-d9e331c6-e61d-4d40-86f9-dcc40883e305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107616032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.4107616032
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1995438138
Short name T641
Test name
Test status
Simulation time 22504647 ps
CPU time 1.26 seconds
Started May 09 02:26:49 PM PDT 24
Finished May 09 02:26:52 PM PDT 24
Peak memory 223960 kb
Host smart-bf9e8bb9-fabb-4a8f-b3da-dbb0957f0032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995438138 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1995438138
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2998391366
Short name T813
Test name
Test status
Simulation time 18683315 ps
CPU time 1.03 seconds
Started May 09 02:26:51 PM PDT 24
Finished May 09 02:26:55 PM PDT 24
Peak memory 215128 kb
Host smart-77bad0a3-f1b5-4cd2-888f-4e0f36462328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998391366 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2998391366
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2145926314
Short name T380
Test name
Test status
Simulation time 126089245 ps
CPU time 1.28 seconds
Started May 09 02:26:50 PM PDT 24
Finished May 09 02:26:54 PM PDT 24
Peak memory 216848 kb
Host smart-70118c3b-820d-4482-8306-d4d55fddb3a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145926314 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2145926314
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3260176052
Short name T335
Test name
Test status
Simulation time 135012840303 ps
CPU time 387.26 seconds
Started May 09 02:26:52 PM PDT 24
Finished May 09 02:33:22 PM PDT 24
Peak memory 218900 kb
Host smart-2c2bf844-63c1-4db3-a2df-024a4fb7ec2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260176052 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3260176052
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert_test.2896960615
Short name T735
Test name
Test status
Simulation time 16920672 ps
CPU time 0.99 seconds
Started May 09 02:26:52 PM PDT 24
Finished May 09 02:26:56 PM PDT 24
Peak memory 206784 kb
Host smart-66edf0f7-8126-495b-b1b7-22c6c1653ac4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896960615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2896960615
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.4092915351
Short name T399
Test name
Test status
Simulation time 46929158 ps
CPU time 0.91 seconds
Started May 09 02:26:52 PM PDT 24
Finished May 09 02:26:56 PM PDT 24
Peak memory 215800 kb
Host smart-199f9af5-dbc4-4877-b514-0f22416a4c88
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092915351 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.4092915351
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.125527630
Short name T89
Test name
Test status
Simulation time 39855494 ps
CPU time 1.34 seconds
Started May 09 02:26:51 PM PDT 24
Finished May 09 02:26:55 PM PDT 24
Peak memory 216904 kb
Host smart-87098c40-befe-42d0-83c3-200424cbf913
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125527630 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.125527630
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2976435090
Short name T435
Test name
Test status
Simulation time 19264597 ps
CPU time 1.03 seconds
Started May 09 02:26:51 PM PDT 24
Finished May 09 02:26:55 PM PDT 24
Peak memory 218216 kb
Host smart-851affbb-d50b-43be-8dfe-613d8c472bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976435090 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2976435090
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2301981573
Short name T824
Test name
Test status
Simulation time 159908038 ps
CPU time 3.83 seconds
Started May 09 02:26:50 PM PDT 24
Finished May 09 02:26:57 PM PDT 24
Peak memory 218640 kb
Host smart-54feb559-f68a-42b8-af75-7b5c28a960f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301981573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2301981573
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1016134468
Short name T80
Test name
Test status
Simulation time 34366294 ps
CPU time 0.89 seconds
Started May 09 02:26:50 PM PDT 24
Finished May 09 02:26:53 PM PDT 24
Peak memory 215560 kb
Host smart-589dddb4-bf1b-455f-9bc7-a7d4afae61ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016134468 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1016134468
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2018236540
Short name T689
Test name
Test status
Simulation time 17883873 ps
CPU time 0.97 seconds
Started May 09 02:26:52 PM PDT 24
Finished May 09 02:26:56 PM PDT 24
Peak memory 215180 kb
Host smart-fa88a7b0-387b-448e-bf22-86a21f4d92bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018236540 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2018236540
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2136642198
Short name T196
Test name
Test status
Simulation time 397391981 ps
CPU time 4.39 seconds
Started May 09 02:26:51 PM PDT 24
Finished May 09 02:26:59 PM PDT 24
Peak memory 216928 kb
Host smart-1bdfb81c-fd8a-4fb6-be27-5db0d3d225ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136642198 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2136642198
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_alert.3166772332
Short name T149
Test name
Test status
Simulation time 70788807 ps
CPU time 1.2 seconds
Started May 09 02:26:53 PM PDT 24
Finished May 09 02:26:58 PM PDT 24
Peak memory 215592 kb
Host smart-fc7240bb-10e3-4fc7-afa3-57e17ee9fad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166772332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3166772332
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.883147764
Short name T60
Test name
Test status
Simulation time 34273342 ps
CPU time 0.98 seconds
Started May 09 02:26:56 PM PDT 24
Finished May 09 02:27:01 PM PDT 24
Peak memory 206580 kb
Host smart-be71aa05-3c47-4636-91b4-9f65ab799f3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883147764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.883147764
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2283619799
Short name T372
Test name
Test status
Simulation time 30581349 ps
CPU time 1.09 seconds
Started May 09 02:26:56 PM PDT 24
Finished May 09 02:27:01 PM PDT 24
Peak memory 218012 kb
Host smart-fdfab7b5-32e6-47ce-acfa-83fd42713316
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283619799 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2283619799
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_genbits.1626436233
Short name T494
Test name
Test status
Simulation time 55527700 ps
CPU time 2.16 seconds
Started May 09 02:26:50 PM PDT 24
Finished May 09 02:26:54 PM PDT 24
Peak memory 219684 kb
Host smart-8bc4c20c-df28-46cd-b596-26ac42319170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626436233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1626436233
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3813375050
Short name T785
Test name
Test status
Simulation time 20116186 ps
CPU time 1.08 seconds
Started May 09 02:26:52 PM PDT 24
Finished May 09 02:26:57 PM PDT 24
Peak memory 215768 kb
Host smart-75e9cd0e-e073-4e6d-93e6-795823ce8a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813375050 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3813375050
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.111088049
Short name T508
Test name
Test status
Simulation time 40083499 ps
CPU time 0.93 seconds
Started May 09 02:26:49 PM PDT 24
Finished May 09 02:26:50 PM PDT 24
Peak memory 215156 kb
Host smart-bf9d1d15-2a1f-4e55-b5d9-8bae0f0e939d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111088049 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.111088049
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.291216717
Short name T771
Test name
Test status
Simulation time 190666027 ps
CPU time 1.72 seconds
Started May 09 02:26:54 PM PDT 24
Finished May 09 02:26:59 PM PDT 24
Peak memory 216704 kb
Host smart-17b11e27-a45c-488a-8820-826ee16f52d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291216717 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.291216717
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3564894400
Short name T483
Test name
Test status
Simulation time 142190881367 ps
CPU time 1758.68 seconds
Started May 09 02:26:52 PM PDT 24
Finished May 09 02:56:14 PM PDT 24
Peak memory 228048 kb
Host smart-dd49c1f5-7da9-40f6-87b4-176a647a8bff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564894400 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3564894400
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.4148108004
Short name T178
Test name
Test status
Simulation time 44627465 ps
CPU time 1.16 seconds
Started May 09 02:26:55 PM PDT 24
Finished May 09 02:27:00 PM PDT 24
Peak memory 215548 kb
Host smart-03190eba-1148-4a61-b367-a10be0e363f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148108004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.4148108004
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.673442033
Short name T716
Test name
Test status
Simulation time 50308301 ps
CPU time 0.88 seconds
Started May 09 02:26:57 PM PDT 24
Finished May 09 02:27:01 PM PDT 24
Peak memory 206528 kb
Host smart-81f0ac22-1647-442c-b7e9-21a6b6d57ff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673442033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.673442033
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1034481327
Short name T710
Test name
Test status
Simulation time 21574121 ps
CPU time 0.85 seconds
Started May 09 02:26:51 PM PDT 24
Finished May 09 02:26:55 PM PDT 24
Peak memory 216128 kb
Host smart-e8907506-6d8b-4734-b2f9-850bba58895f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034481327 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1034481327
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.621295998
Short name T105
Test name
Test status
Simulation time 110536530 ps
CPU time 1.18 seconds
Started May 09 02:26:56 PM PDT 24
Finished May 09 02:27:01 PM PDT 24
Peak memory 216636 kb
Host smart-317ac52e-4ad0-4f6c-b386-81303a2d9abb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621295998 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.621295998
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3089489226
Short name T793
Test name
Test status
Simulation time 29554214 ps
CPU time 0.89 seconds
Started May 09 02:26:55 PM PDT 24
Finished May 09 02:27:00 PM PDT 24
Peak memory 218140 kb
Host smart-c73f8800-8a22-4caa-a456-2a0acb321f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089489226 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3089489226
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2915744818
Short name T465
Test name
Test status
Simulation time 65954738 ps
CPU time 1.48 seconds
Started May 09 02:26:54 PM PDT 24
Finished May 09 02:27:00 PM PDT 24
Peak memory 218076 kb
Host smart-7f43b35f-cfa4-42db-9e25-90a0c43cfd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915744818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2915744818
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.294374074
Short name T805
Test name
Test status
Simulation time 54169444 ps
CPU time 0.89 seconds
Started May 09 02:26:55 PM PDT 24
Finished May 09 02:27:00 PM PDT 24
Peak memory 215124 kb
Host smart-d09c6cb4-b9fb-4947-b8db-b545a1b714e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294374074 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.294374074
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.4049365085
Short name T519
Test name
Test status
Simulation time 23447538 ps
CPU time 0.94 seconds
Started May 09 02:26:54 PM PDT 24
Finished May 09 02:26:59 PM PDT 24
Peak memory 215152 kb
Host smart-78626595-5257-4a34-be07-5dd889f47af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049365085 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.4049365085
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3872166144
Short name T355
Test name
Test status
Simulation time 371031895 ps
CPU time 3.84 seconds
Started May 09 02:26:54 PM PDT 24
Finished May 09 02:27:02 PM PDT 24
Peak memory 216584 kb
Host smart-00cca825-6ea2-4f2b-977b-c3fd3a8462bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872166144 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3872166144
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.692248608
Short name T183
Test name
Test status
Simulation time 74262088620 ps
CPU time 1155.96 seconds
Started May 09 02:26:55 PM PDT 24
Finished May 09 02:46:15 PM PDT 24
Peak memory 221792 kb
Host smart-d9da5944-23d5-4006-9d2e-f3e9138ff202
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692248608 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.692248608
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1330333173
Short name T652
Test name
Test status
Simulation time 28316493 ps
CPU time 1.25 seconds
Started May 09 02:27:04 PM PDT 24
Finished May 09 02:27:08 PM PDT 24
Peak memory 215616 kb
Host smart-5daba536-51ef-4df7-8923-e1d3e1074f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330333173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1330333173
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1473310030
Short name T358
Test name
Test status
Simulation time 46965793 ps
CPU time 0.93 seconds
Started May 09 02:27:06 PM PDT 24
Finished May 09 02:27:13 PM PDT 24
Peak memory 215136 kb
Host smart-941aa98c-3235-4f0a-b81a-df01d9da710f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473310030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1473310030
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.831590413
Short name T154
Test name
Test status
Simulation time 28713030 ps
CPU time 0.87 seconds
Started May 09 02:27:04 PM PDT 24
Finished May 09 02:27:09 PM PDT 24
Peak memory 216040 kb
Host smart-c188ada5-30cb-46e6-a183-839e63c8a697
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831590413 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.831590413
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3275454399
Short name T90
Test name
Test status
Simulation time 47436699 ps
CPU time 1.39 seconds
Started May 09 02:27:05 PM PDT 24
Finished May 09 02:27:12 PM PDT 24
Peak memory 216724 kb
Host smart-375420b9-94ef-4036-8c1e-32033afaf9cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275454399 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3275454399
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3583455045
Short name T98
Test name
Test status
Simulation time 31940135 ps
CPU time 1.04 seconds
Started May 09 02:27:05 PM PDT 24
Finished May 09 02:27:12 PM PDT 24
Peak memory 218496 kb
Host smart-7e944c6e-1353-4f31-8faf-35415e71a9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583455045 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3583455045
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3123512056
Short name T430
Test name
Test status
Simulation time 108356722 ps
CPU time 1.29 seconds
Started May 09 02:27:01 PM PDT 24
Finished May 09 02:27:04 PM PDT 24
Peak memory 218248 kb
Host smart-68c5d995-806d-43f1-bfdf-c783b0c6824c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123512056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3123512056
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1762208806
Short name T34
Test name
Test status
Simulation time 25754981 ps
CPU time 0.93 seconds
Started May 09 02:27:01 PM PDT 24
Finished May 09 02:27:04 PM PDT 24
Peak memory 215716 kb
Host smart-bb01592a-0a05-4362-af09-bcfe9e0d1488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762208806 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1762208806
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1339881428
Short name T525
Test name
Test status
Simulation time 33725580 ps
CPU time 0.92 seconds
Started May 09 02:26:56 PM PDT 24
Finished May 09 02:27:01 PM PDT 24
Peak memory 206964 kb
Host smart-164a31b6-95f3-4a2b-941d-e6bd5c3dc220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339881428 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1339881428
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.868098167
Short name T197
Test name
Test status
Simulation time 873670311 ps
CPU time 5.34 seconds
Started May 09 02:27:04 PM PDT 24
Finished May 09 02:27:12 PM PDT 24
Peak memory 219776 kb
Host smart-e47d9d5e-fef4-4f2f-9db2-37c14ae00a9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868098167 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.868098167
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3722176832
Short name T184
Test name
Test status
Simulation time 20805795481 ps
CPU time 497.36 seconds
Started May 09 02:27:07 PM PDT 24
Finished May 09 02:35:32 PM PDT 24
Peak memory 217460 kb
Host smart-bf43b53b-ab7d-4508-9809-82f81237fb1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722176832 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3722176832
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert_test.3728968638
Short name T2
Test name
Test status
Simulation time 30242000 ps
CPU time 0.99 seconds
Started May 09 02:25:45 PM PDT 24
Finished May 09 02:25:48 PM PDT 24
Peak memory 214816 kb
Host smart-fd153984-ae4f-4d54-8d91-eccf4f46722c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728968638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3728968638
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1676125343
Short name T505
Test name
Test status
Simulation time 19999128 ps
CPU time 0.85 seconds
Started May 09 02:25:28 PM PDT 24
Finished May 09 02:25:31 PM PDT 24
Peak memory 215848 kb
Host smart-e25a06db-a95f-4754-9886-d5304649cbca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676125343 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1676125343
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.733135397
Short name T367
Test name
Test status
Simulation time 25985234 ps
CPU time 1.02 seconds
Started May 09 02:25:31 PM PDT 24
Finished May 09 02:25:34 PM PDT 24
Peak memory 219240 kb
Host smart-6d0cbd13-d944-4f9b-88d6-2c4b06f6f01d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733135397 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.733135397
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2891289896
Short name T6
Test name
Test status
Simulation time 49998665 ps
CPU time 1.01 seconds
Started May 09 02:25:37 PM PDT 24
Finished May 09 02:25:39 PM PDT 24
Peak memory 219412 kb
Host smart-b1b8be56-d471-46b1-8d37-4c681d1854a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891289896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2891289896
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2121977068
Short name T14
Test name
Test status
Simulation time 63385519 ps
CPU time 1.55 seconds
Started May 09 02:25:28 PM PDT 24
Finished May 09 02:25:32 PM PDT 24
Peak memory 219584 kb
Host smart-76dbd3e1-4b42-4c2c-a4d5-c3cca8df12df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121977068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2121977068
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.630406200
Short name T593
Test name
Test status
Simulation time 22338375 ps
CPU time 1.28 seconds
Started May 09 02:25:31 PM PDT 24
Finished May 09 02:25:34 PM PDT 24
Peak memory 223916 kb
Host smart-9e2d542c-151c-42c8-be1a-fb7bbd46d9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630406200 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.630406200
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1715964550
Short name T24
Test name
Test status
Simulation time 30565409 ps
CPU time 0.95 seconds
Started May 09 02:25:27 PM PDT 24
Finished May 09 02:25:31 PM PDT 24
Peak memory 206996 kb
Host smart-2699089a-eb36-4a8b-931d-cbec55998bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715964550 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1715964550
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1116852924
Short name T18
Test name
Test status
Simulation time 495720585 ps
CPU time 4.37 seconds
Started May 09 02:25:45 PM PDT 24
Finished May 09 02:25:52 PM PDT 24
Peak memory 236224 kb
Host smart-f5a4b660-ade9-4511-81d6-a9d377b01b60
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116852924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1116852924
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2561705604
Short name T328
Test name
Test status
Simulation time 41439323 ps
CPU time 0.97 seconds
Started May 09 02:25:27 PM PDT 24
Finished May 09 02:25:31 PM PDT 24
Peak memory 215228 kb
Host smart-419966c0-2156-4f6c-a43b-ba39560f0f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561705604 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2561705604
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1175775102
Short name T568
Test name
Test status
Simulation time 385432040 ps
CPU time 2.68 seconds
Started May 09 02:25:30 PM PDT 24
Finished May 09 02:25:35 PM PDT 24
Peak memory 215140 kb
Host smart-c934444c-4bae-42d8-b29a-82831f2a4b2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175775102 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1175775102
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_alert.3808410524
Short name T139
Test name
Test status
Simulation time 50094244 ps
CPU time 1.18 seconds
Started May 09 02:27:04 PM PDT 24
Finished May 09 02:27:09 PM PDT 24
Peak memory 215616 kb
Host smart-362bd0a1-2acc-40aa-9fb8-2f28b93d10ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808410524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3808410524
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.832258545
Short name T443
Test name
Test status
Simulation time 37606070 ps
CPU time 0.81 seconds
Started May 09 02:27:04 PM PDT 24
Finished May 09 02:27:09 PM PDT 24
Peak memory 206796 kb
Host smart-151d9014-681c-4ae5-a04c-a27d2b08c8d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832258545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.832258545
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2905852131
Short name T636
Test name
Test status
Simulation time 17404836 ps
CPU time 0.82 seconds
Started May 09 02:27:03 PM PDT 24
Finished May 09 02:27:06 PM PDT 24
Peak memory 215220 kb
Host smart-cb8b7458-14c3-4f8a-b13f-39d6d90c42b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905852131 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2905852131
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.233887596
Short name T586
Test name
Test status
Simulation time 23834191 ps
CPU time 1.11 seconds
Started May 09 02:27:04 PM PDT 24
Finished May 09 02:27:10 PM PDT 24
Peak memory 218056 kb
Host smart-71db7179-8c42-44a8-a61b-fd5bb9f7cf2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233887596 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.233887596
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2002716238
Short name T88
Test name
Test status
Simulation time 21353454 ps
CPU time 1.15 seconds
Started May 09 02:27:04 PM PDT 24
Finished May 09 02:27:08 PM PDT 24
Peak memory 219516 kb
Host smart-141456a6-05b1-4d71-9feb-858d40af0d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002716238 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2002716238
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.4262689440
Short name T655
Test name
Test status
Simulation time 59954087 ps
CPU time 1.46 seconds
Started May 09 02:27:04 PM PDT 24
Finished May 09 02:27:10 PM PDT 24
Peak memory 217192 kb
Host smart-e478e736-0527-433a-9271-1d26800fae95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262689440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.4262689440
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.600528172
Short name T150
Test name
Test status
Simulation time 110556882 ps
CPU time 0.9 seconds
Started May 09 02:27:06 PM PDT 24
Finished May 09 02:27:14 PM PDT 24
Peak memory 215492 kb
Host smart-8a696ac2-5c32-4ff9-af72-2671d549efed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600528172 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.600528172
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.183597575
Short name T565
Test name
Test status
Simulation time 22660878 ps
CPU time 0.95 seconds
Started May 09 02:27:11 PM PDT 24
Finished May 09 02:27:18 PM PDT 24
Peak memory 215128 kb
Host smart-4f612c0d-2d7a-4b3d-a78c-aeccce0cdb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183597575 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.183597575
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2475206903
Short name T589
Test name
Test status
Simulation time 492150186 ps
CPU time 5.02 seconds
Started May 09 02:27:03 PM PDT 24
Finished May 09 02:27:10 PM PDT 24
Peak memory 215228 kb
Host smart-3b50191b-82a9-460d-a410-74b3486a7ae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475206903 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2475206903
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2511127423
Short name T189
Test name
Test status
Simulation time 65357594136 ps
CPU time 1509.13 seconds
Started May 09 02:27:05 PM PDT 24
Finished May 09 02:52:20 PM PDT 24
Peak memory 221636 kb
Host smart-d77c6794-5ab2-4794-acda-b4abebb921e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511127423 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2511127423
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1421979449
Short name T617
Test name
Test status
Simulation time 25547248 ps
CPU time 1.24 seconds
Started May 09 02:27:09 PM PDT 24
Finished May 09 02:27:17 PM PDT 24
Peak memory 215536 kb
Host smart-6bd33ba1-dce0-4850-86c8-51958a54c7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421979449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1421979449
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1684375056
Short name T298
Test name
Test status
Simulation time 20972314 ps
CPU time 1.09 seconds
Started May 09 02:27:04 PM PDT 24
Finished May 09 02:27:08 PM PDT 24
Peak memory 206628 kb
Host smart-935945e1-f912-4035-857c-b785c33ed069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684375056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1684375056
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3247426235
Short name T136
Test name
Test status
Simulation time 74444981 ps
CPU time 0.86 seconds
Started May 09 02:27:04 PM PDT 24
Finished May 09 02:27:10 PM PDT 24
Peak memory 216236 kb
Host smart-4a5c7d79-301e-461e-8696-a6a255da2a9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247426235 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3247426235
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1807764208
Short name T350
Test name
Test status
Simulation time 41845034 ps
CPU time 1.32 seconds
Started May 09 02:27:09 PM PDT 24
Finished May 09 02:27:17 PM PDT 24
Peak memory 217952 kb
Host smart-9ca49ee6-a893-4d69-8fbf-7ea4f2437210
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807764208 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1807764208
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3006562027
Short name T422
Test name
Test status
Simulation time 32373321 ps
CPU time 0.94 seconds
Started May 09 02:27:06 PM PDT 24
Finished May 09 02:27:12 PM PDT 24
Peak memory 218368 kb
Host smart-0410a2aa-586e-4c24-aedc-736d8ef1a16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006562027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3006562027
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_intr.2205152559
Short name T31
Test name
Test status
Simulation time 19876575 ps
CPU time 1.03 seconds
Started May 09 02:27:07 PM PDT 24
Finished May 09 02:27:14 PM PDT 24
Peak memory 215708 kb
Host smart-b8f9d679-9f6b-44d3-a0af-13611bc12666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205152559 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2205152559
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1765795867
Short name T468
Test name
Test status
Simulation time 22564554 ps
CPU time 0.92 seconds
Started May 09 02:27:09 PM PDT 24
Finished May 09 02:27:17 PM PDT 24
Peak memory 215128 kb
Host smart-3fc8d4aa-dead-41bc-8e0a-e846cda0672a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765795867 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1765795867
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.918062648
Short name T797
Test name
Test status
Simulation time 90531754 ps
CPU time 2.26 seconds
Started May 09 02:27:06 PM PDT 24
Finished May 09 02:27:14 PM PDT 24
Peak memory 215176 kb
Host smart-afbbf63a-6c73-4410-b6ae-7de90df20706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918062648 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.918062648
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3194942202
Short name T413
Test name
Test status
Simulation time 13895744848 ps
CPU time 184.1 seconds
Started May 09 02:27:06 PM PDT 24
Finished May 09 02:30:17 PM PDT 24
Peak memory 222328 kb
Host smart-c040c353-f9ed-4f46-be95-45d12d11c5c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194942202 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3194942202
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert_test.467245010
Short name T667
Test name
Test status
Simulation time 23780364 ps
CPU time 0.92 seconds
Started May 09 02:27:05 PM PDT 24
Finished May 09 02:27:11 PM PDT 24
Peak memory 206568 kb
Host smart-549a3438-2a9d-40f1-8773-0e2949de61d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467245010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.467245010
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.974932602
Short name T169
Test name
Test status
Simulation time 33086305 ps
CPU time 0.86 seconds
Started May 09 02:27:06 PM PDT 24
Finished May 09 02:27:14 PM PDT 24
Peak memory 216060 kb
Host smart-5332ad91-33e7-4e14-9cd5-035a8b673dac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974932602 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.974932602
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3330290504
Short name T167
Test name
Test status
Simulation time 34918445 ps
CPU time 1.29 seconds
Started May 09 02:27:06 PM PDT 24
Finished May 09 02:27:14 PM PDT 24
Peak memory 216700 kb
Host smart-52c1ffdc-d17a-4bbe-b186-e86766f638e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330290504 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3330290504
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.4067025697
Short name T130
Test name
Test status
Simulation time 33045020 ps
CPU time 0.91 seconds
Started May 09 02:27:04 PM PDT 24
Finished May 09 02:27:09 PM PDT 24
Peak memory 223672 kb
Host smart-7e1cb4ab-2812-4cda-bdf0-fa0957430cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067025697 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.4067025697
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1037608470
Short name T540
Test name
Test status
Simulation time 55216579 ps
CPU time 1.98 seconds
Started May 09 02:27:05 PM PDT 24
Finished May 09 02:27:12 PM PDT 24
Peak memory 219816 kb
Host smart-9fb51117-8082-4673-8566-e4f73f3341ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037608470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1037608470
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3452256535
Short name T720
Test name
Test status
Simulation time 20318998 ps
CPU time 1.19 seconds
Started May 09 02:27:11 PM PDT 24
Finished May 09 02:27:19 PM PDT 24
Peak memory 223844 kb
Host smart-d50a3219-77a0-41e3-9f49-5be3cb7d99e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452256535 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3452256535
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.764829224
Short name T397
Test name
Test status
Simulation time 55348280 ps
CPU time 0.91 seconds
Started May 09 02:27:06 PM PDT 24
Finished May 09 02:27:14 PM PDT 24
Peak memory 215164 kb
Host smart-e45bef9e-15f9-445e-a87c-0e486cb63128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764829224 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.764829224
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.184194663
Short name T752
Test name
Test status
Simulation time 503321341 ps
CPU time 3 seconds
Started May 09 02:27:05 PM PDT 24
Finished May 09 02:27:12 PM PDT 24
Peak memory 215180 kb
Host smart-071abe1e-400e-4543-bd4d-bd6f673c8c34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184194663 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.184194663
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3580741571
Short name T414
Test name
Test status
Simulation time 23271160108 ps
CPU time 301.02 seconds
Started May 09 02:27:08 PM PDT 24
Finished May 09 02:32:16 PM PDT 24
Peak memory 218744 kb
Host smart-269031d5-824b-4132-926a-62423df453d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580741571 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3580741571
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2466817742
Short name T147
Test name
Test status
Simulation time 214757436 ps
CPU time 1.43 seconds
Started May 09 02:27:19 PM PDT 24
Finished May 09 02:27:24 PM PDT 24
Peak memory 215540 kb
Host smart-48c75b32-88c4-4ac6-b3cb-9ed7d2dadda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466817742 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2466817742
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2854407870
Short name T200
Test name
Test status
Simulation time 34928810 ps
CPU time 0.98 seconds
Started May 09 02:27:13 PM PDT 24
Finished May 09 02:27:20 PM PDT 24
Peak memory 214800 kb
Host smart-2efc3c17-9e7e-46c7-bf26-d36d4e1abd4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854407870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2854407870
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3888981653
Short name T714
Test name
Test status
Simulation time 26599187 ps
CPU time 0.82 seconds
Started May 09 02:27:12 PM PDT 24
Finished May 09 02:27:19 PM PDT 24
Peak memory 216120 kb
Host smart-636fa90b-5b4a-4dc0-9a1e-35723876dc5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888981653 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3888981653
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3866547028
Short name T450
Test name
Test status
Simulation time 80932619 ps
CPU time 1.09 seconds
Started May 09 02:27:13 PM PDT 24
Finished May 09 02:27:20 PM PDT 24
Peak memory 219340 kb
Host smart-d2a3fd71-4448-42cf-9f36-c4b8807af44d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866547028 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3866547028
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2595299730
Short name T168
Test name
Test status
Simulation time 77003450 ps
CPU time 1.09 seconds
Started May 09 02:27:12 PM PDT 24
Finished May 09 02:27:19 PM PDT 24
Peak memory 219748 kb
Host smart-6beeb920-af3b-4519-a22b-912df7c53c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595299730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2595299730
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.4184905940
Short name T602
Test name
Test status
Simulation time 67995708 ps
CPU time 1.38 seconds
Started May 09 02:27:11 PM PDT 24
Finished May 09 02:27:19 PM PDT 24
Peak memory 217076 kb
Host smart-dfa09033-767b-4170-96d6-76def1b32b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184905940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.4184905940
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.298971205
Short name T52
Test name
Test status
Simulation time 22349728 ps
CPU time 1.16 seconds
Started May 09 02:27:20 PM PDT 24
Finished May 09 02:27:25 PM PDT 24
Peak memory 223868 kb
Host smart-9e104011-7ae5-4f2f-8d2b-7b32fb99e5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298971205 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.298971205
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.507142086
Short name T786
Test name
Test status
Simulation time 41476588 ps
CPU time 0.96 seconds
Started May 09 02:27:07 PM PDT 24
Finished May 09 02:27:16 PM PDT 24
Peak memory 215176 kb
Host smart-199ff319-0511-4637-b6dc-fc9ab316b51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507142086 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.507142086
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3404057544
Short name T782
Test name
Test status
Simulation time 226763557 ps
CPU time 3 seconds
Started May 09 02:27:10 PM PDT 24
Finished May 09 02:27:20 PM PDT 24
Peak memory 216908 kb
Host smart-89c55f57-695d-43e4-9c27-fc6cc0f924b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404057544 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3404057544
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.692780242
Short name T473
Test name
Test status
Simulation time 89198990567 ps
CPU time 1431.21 seconds
Started May 09 02:27:17 PM PDT 24
Finished May 09 02:51:13 PM PDT 24
Peak memory 225772 kb
Host smart-6cb2c42c-ba31-4a0d-92d3-c81475660788
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692780242 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.692780242
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2581333176
Short name T245
Test name
Test status
Simulation time 57167414 ps
CPU time 1.21 seconds
Started May 09 02:27:17 PM PDT 24
Finished May 09 02:27:23 PM PDT 24
Peak memory 215604 kb
Host smart-6a5c3f2c-e089-4162-8411-f641a43c9d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581333176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2581333176
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2767219817
Short name T594
Test name
Test status
Simulation time 16898775 ps
CPU time 0.96 seconds
Started May 09 02:27:14 PM PDT 24
Finished May 09 02:27:20 PM PDT 24
Peak memory 214772 kb
Host smart-44acbb8e-4a36-4e39-9aab-ec17945a4adf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767219817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2767219817
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3593153057
Short name T695
Test name
Test status
Simulation time 20556249 ps
CPU time 0.86 seconds
Started May 09 02:27:12 PM PDT 24
Finished May 09 02:27:19 PM PDT 24
Peak memory 216096 kb
Host smart-a5cf8d60-079d-48fc-bb46-c134f1c62d67
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593153057 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3593153057
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.791008361
Short name T85
Test name
Test status
Simulation time 40827611 ps
CPU time 1.25 seconds
Started May 09 02:27:17 PM PDT 24
Finished May 09 02:27:23 PM PDT 24
Peak memory 219360 kb
Host smart-1731bcec-9b09-4c9d-8676-6a2b4bc8b112
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791008361 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.791008361
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2294386132
Short name T670
Test name
Test status
Simulation time 34147504 ps
CPU time 0.95 seconds
Started May 09 02:27:12 PM PDT 24
Finished May 09 02:27:19 PM PDT 24
Peak memory 223732 kb
Host smart-71aef266-ae39-4c4c-998d-38554e9b05f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294386132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2294386132
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.428805907
Short name T500
Test name
Test status
Simulation time 252706617 ps
CPU time 3.56 seconds
Started May 09 02:27:13 PM PDT 24
Finished May 09 02:27:22 PM PDT 24
Peak memory 219708 kb
Host smart-371918bc-53c8-4a13-824d-e70340876040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428805907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.428805907
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.519215620
Short name T679
Test name
Test status
Simulation time 42715247 ps
CPU time 0.89 seconds
Started May 09 02:27:12 PM PDT 24
Finished May 09 02:27:19 PM PDT 24
Peak memory 215060 kb
Host smart-2bd67c41-31d5-4ae0-9057-35812ba5861a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519215620 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.519215620
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3574547823
Short name T396
Test name
Test status
Simulation time 25426400 ps
CPU time 0.95 seconds
Started May 09 02:27:10 PM PDT 24
Finished May 09 02:27:18 PM PDT 24
Peak memory 215220 kb
Host smart-9d90aa2f-a337-4a3d-885b-a238c88bea22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574547823 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3574547823
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1297539231
Short name T371
Test name
Test status
Simulation time 283530206 ps
CPU time 1.85 seconds
Started May 09 02:27:17 PM PDT 24
Finished May 09 02:27:23 PM PDT 24
Peak memory 215280 kb
Host smart-45c7d036-6c3c-46f5-bb1b-b0a4dbce8b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297539231 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1297539231
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2554282588
Short name T417
Test name
Test status
Simulation time 62394698045 ps
CPU time 1357.31 seconds
Started May 09 02:27:19 PM PDT 24
Finished May 09 02:50:00 PM PDT 24
Peak memory 223584 kb
Host smart-f9c466d3-e78f-412a-add0-f5432e90415a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554282588 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2554282588
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2834663121
Short name T87
Test name
Test status
Simulation time 81396687 ps
CPU time 1.14 seconds
Started May 09 02:27:27 PM PDT 24
Finished May 09 02:27:33 PM PDT 24
Peak memory 215596 kb
Host smart-50c5edd4-4d60-4c3b-bba1-75333babfa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834663121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2834663121
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1227089567
Short name T788
Test name
Test status
Simulation time 49255911 ps
CPU time 0.91 seconds
Started May 09 02:27:26 PM PDT 24
Finished May 09 02:27:33 PM PDT 24
Peak memory 214720 kb
Host smart-b199a52e-042d-4e08-9db8-36e21ebeb2bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227089567 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1227089567
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.770384737
Short name T578
Test name
Test status
Simulation time 14860452 ps
CPU time 0.9 seconds
Started May 09 02:27:25 PM PDT 24
Finished May 09 02:27:32 PM PDT 24
Peak memory 215488 kb
Host smart-ae2fcc01-f740-432c-860d-f00e3f91975d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770384737 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.770384737
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_err.915524547
Short name T801
Test name
Test status
Simulation time 29219446 ps
CPU time 1.2 seconds
Started May 09 02:27:11 PM PDT 24
Finished May 09 02:27:19 PM PDT 24
Peak memory 219352 kb
Host smart-d32d2a09-4fa0-4f0e-89e9-bca97903bc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915524547 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.915524547
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3018998765
Short name T587
Test name
Test status
Simulation time 115784607 ps
CPU time 1.65 seconds
Started May 09 02:27:19 PM PDT 24
Finished May 09 02:27:25 PM PDT 24
Peak memory 218176 kb
Host smart-737e0e85-0378-4d8d-93bb-5bd229322cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018998765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3018998765
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1941489964
Short name T323
Test name
Test status
Simulation time 22750618 ps
CPU time 1.1 seconds
Started May 09 02:27:26 PM PDT 24
Finished May 09 02:27:32 PM PDT 24
Peak memory 215336 kb
Host smart-7da58c4c-5716-4ae9-a3b7-54df505cdaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941489964 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1941489964
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2135333144
Short name T541
Test name
Test status
Simulation time 24260605 ps
CPU time 0.96 seconds
Started May 09 02:27:15 PM PDT 24
Finished May 09 02:27:21 PM PDT 24
Peak memory 215212 kb
Host smart-7fcdf0b0-2620-4f59-a8df-cbd7475d253e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135333144 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2135333144
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3586891296
Short name T702
Test name
Test status
Simulation time 3037969219 ps
CPU time 4.2 seconds
Started May 09 02:27:15 PM PDT 24
Finished May 09 02:27:24 PM PDT 24
Peak memory 216928 kb
Host smart-b587ddea-8ded-4cdb-bdd8-1895e2740e88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586891296 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3586891296
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2966422163
Short name T550
Test name
Test status
Simulation time 52424976601 ps
CPU time 639.98 seconds
Started May 09 02:27:25 PM PDT 24
Finished May 09 02:38:10 PM PDT 24
Peak memory 218284 kb
Host smart-871fb245-c654-48e9-aced-eeae538e11b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966422163 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2966422163
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert_test.2549606775
Short name T523
Test name
Test status
Simulation time 11818461 ps
CPU time 0.87 seconds
Started May 09 02:27:21 PM PDT 24
Finished May 09 02:27:27 PM PDT 24
Peak memory 206416 kb
Host smart-8c6fcc3a-06ef-4f56-8664-2213a617cbda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549606775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2549606775
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1414361995
Short name T718
Test name
Test status
Simulation time 11923164 ps
CPU time 0.87 seconds
Started May 09 02:27:22 PM PDT 24
Finished May 09 02:27:28 PM PDT 24
Peak memory 216264 kb
Host smart-c2aa49c6-4247-45f0-a139-26c07371dd69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414361995 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1414361995
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_err.547454766
Short name T472
Test name
Test status
Simulation time 19079356 ps
CPU time 1.11 seconds
Started May 09 02:27:20 PM PDT 24
Finished May 09 02:27:25 PM PDT 24
Peak memory 218344 kb
Host smart-78404871-29ea-40c7-bc9c-202c11681706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547454766 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.547454766
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2664215964
Short name T708
Test name
Test status
Simulation time 83407942 ps
CPU time 1.41 seconds
Started May 09 02:27:20 PM PDT 24
Finished May 09 02:27:26 PM PDT 24
Peak memory 218668 kb
Host smart-b0ac4586-13f8-45d4-89ec-ce89231e7db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664215964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2664215964
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3108278888
Short name T481
Test name
Test status
Simulation time 59782302 ps
CPU time 0.89 seconds
Started May 09 02:27:22 PM PDT 24
Finished May 09 02:27:29 PM PDT 24
Peak memory 215292 kb
Host smart-bdae05ed-6973-482f-9721-61ad8111b906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108278888 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3108278888
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3454842150
Short name T755
Test name
Test status
Simulation time 43258886 ps
CPU time 0.92 seconds
Started May 09 02:27:22 PM PDT 24
Finished May 09 02:27:28 PM PDT 24
Peak memory 215216 kb
Host smart-a622aeb3-0d40-45a7-9052-9f3cace059c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454842150 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3454842150
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.88225148
Short name T557
Test name
Test status
Simulation time 314596332 ps
CPU time 5.99 seconds
Started May 09 02:27:26 PM PDT 24
Finished May 09 02:27:38 PM PDT 24
Peak memory 216860 kb
Host smart-62d29a2b-ab54-4105-af64-131811011e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88225148 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.88225148
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3492098996
Short name T675
Test name
Test status
Simulation time 81497271611 ps
CPU time 447.5 seconds
Started May 09 02:27:22 PM PDT 24
Finished May 09 02:34:54 PM PDT 24
Peak memory 218436 kb
Host smart-befbedb9-0749-4c9f-a012-42505485db5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492098996 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3492098996
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2292712987
Short name T229
Test name
Test status
Simulation time 29829738 ps
CPU time 1.17 seconds
Started May 09 02:27:23 PM PDT 24
Finished May 09 02:27:29 PM PDT 24
Peak memory 215592 kb
Host smart-fb13dadf-d80c-479c-b3a0-b8456b1ec4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292712987 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2292712987
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3437916430
Short name T606
Test name
Test status
Simulation time 23538711 ps
CPU time 0.84 seconds
Started May 09 02:27:26 PM PDT 24
Finished May 09 02:27:32 PM PDT 24
Peak memory 206280 kb
Host smart-c4fbf4e7-9906-4772-b381-ecc222c54125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437916430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3437916430
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3296539603
Short name T621
Test name
Test status
Simulation time 79782428 ps
CPU time 0.93 seconds
Started May 09 02:27:23 PM PDT 24
Finished May 09 02:27:29 PM PDT 24
Peak memory 216080 kb
Host smart-08e5bb01-62b8-4313-8446-12a49d660115
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296539603 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3296539603
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.113841733
Short name T340
Test name
Test status
Simulation time 46513278 ps
CPU time 1.32 seconds
Started May 09 02:27:24 PM PDT 24
Finished May 09 02:27:31 PM PDT 24
Peak memory 218064 kb
Host smart-e1dabb79-5694-46bd-8e5a-414dbc3ba194
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113841733 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.113841733
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3115818665
Short name T99
Test name
Test status
Simulation time 19577554 ps
CPU time 1.09 seconds
Started May 09 02:27:23 PM PDT 24
Finished May 09 02:27:29 PM PDT 24
Peak memory 218320 kb
Host smart-6cfa73d9-1e10-4f60-80ed-7e9e109e5753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115818665 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3115818665
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2065830087
Short name T285
Test name
Test status
Simulation time 183136800 ps
CPU time 1.58 seconds
Started May 09 02:27:24 PM PDT 24
Finished May 09 02:27:31 PM PDT 24
Peak memory 218136 kb
Host smart-5d2abd46-ee34-48ae-a74b-1c3606b21eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065830087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2065830087
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.4181581537
Short name T37
Test name
Test status
Simulation time 29181665 ps
CPU time 0.97 seconds
Started May 09 02:27:23 PM PDT 24
Finished May 09 02:27:29 PM PDT 24
Peak memory 215568 kb
Host smart-45409e47-13b3-4be4-b3c7-7ccaef894def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181581537 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.4181581537
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3897369791
Short name T146
Test name
Test status
Simulation time 15632275 ps
CPU time 0.95 seconds
Started May 09 02:27:21 PM PDT 24
Finished May 09 02:27:27 PM PDT 24
Peak memory 215188 kb
Host smart-3b7109a5-16c5-4408-a779-0e7d97e4e026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897369791 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3897369791
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.358983119
Short name T668
Test name
Test status
Simulation time 38465281 ps
CPU time 1.37 seconds
Started May 09 02:27:22 PM PDT 24
Finished May 09 02:27:29 PM PDT 24
Peak memory 215212 kb
Host smart-08bf257f-52ed-4c88-992d-a3a87a060a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358983119 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.358983119
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3453879009
Short name T369
Test name
Test status
Simulation time 718630815597 ps
CPU time 1941.7 seconds
Started May 09 02:27:22 PM PDT 24
Finished May 09 02:59:49 PM PDT 24
Peak memory 237048 kb
Host smart-d1ccd8d7-a690-4f99-aee0-da2a24a5f089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453879009 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3453879009
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1549169608
Short name T26
Test name
Test status
Simulation time 77413091 ps
CPU time 1.26 seconds
Started May 09 02:27:33 PM PDT 24
Finished May 09 02:27:38 PM PDT 24
Peak memory 215584 kb
Host smart-3ab7bfdb-ca26-467c-a14d-473acb6232bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549169608 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1549169608
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2268453199
Short name T442
Test name
Test status
Simulation time 103761054 ps
CPU time 0.99 seconds
Started May 09 02:27:35 PM PDT 24
Finished May 09 02:27:41 PM PDT 24
Peak memory 215084 kb
Host smart-334f782d-eabd-4528-ad93-4bc189931c55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268453199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2268453199
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.207327598
Short name T151
Test name
Test status
Simulation time 22562885 ps
CPU time 0.89 seconds
Started May 09 02:27:33 PM PDT 24
Finished May 09 02:27:38 PM PDT 24
Peak memory 216224 kb
Host smart-3469acdc-e3c9-4abb-a385-289a1ada0cf9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207327598 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.207327598
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2907490885
Short name T303
Test name
Test status
Simulation time 158084851 ps
CPU time 1.2 seconds
Started May 09 02:27:34 PM PDT 24
Finished May 09 02:27:39 PM PDT 24
Peak memory 216816 kb
Host smart-95b94d5f-94c7-476d-9931-2472b5082604
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907490885 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2907490885
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2246734672
Short name T56
Test name
Test status
Simulation time 28039841 ps
CPU time 1.26 seconds
Started May 09 02:27:32 PM PDT 24
Finished May 09 02:27:38 PM PDT 24
Peak memory 223788 kb
Host smart-a0d67c49-977d-4541-ba35-0b334b682073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246734672 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2246734672
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.470870119
Short name T607
Test name
Test status
Simulation time 106619510 ps
CPU time 1.39 seconds
Started May 09 02:27:23 PM PDT 24
Finished May 09 02:27:30 PM PDT 24
Peak memory 218364 kb
Host smart-91187456-a5f7-49a8-8026-0b323cb8c52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470870119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.470870119
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1433984256
Short name T65
Test name
Test status
Simulation time 21942167 ps
CPU time 1 seconds
Started May 09 02:27:35 PM PDT 24
Finished May 09 02:27:40 PM PDT 24
Peak memory 215316 kb
Host smart-c03f2250-cb4b-4144-b22e-e446783250b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433984256 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1433984256
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.95243724
Short name T820
Test name
Test status
Simulation time 19636060 ps
CPU time 1.02 seconds
Started May 09 02:27:24 PM PDT 24
Finished May 09 02:27:30 PM PDT 24
Peak memory 215188 kb
Host smart-9c451586-2e7e-48f8-b1a1-1f14af0eb936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95243724 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.95243724
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.391272251
Short name T559
Test name
Test status
Simulation time 2176895991 ps
CPU time 3.16 seconds
Started May 09 02:27:36 PM PDT 24
Finished May 09 02:27:43 PM PDT 24
Peak memory 215292 kb
Host smart-e0b2fa1e-f552-4eeb-aa1e-2f4009567917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391272251 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.391272251
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_alert.4108862957
Short name T806
Test name
Test status
Simulation time 363428978 ps
CPU time 1.53 seconds
Started May 09 02:27:34 PM PDT 24
Finished May 09 02:27:39 PM PDT 24
Peak memory 215588 kb
Host smart-11dad722-cfca-4fff-bb83-1a4ec2f65db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108862957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.4108862957
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.898866629
Short name T575
Test name
Test status
Simulation time 45155673 ps
CPU time 0.92 seconds
Started May 09 02:27:34 PM PDT 24
Finished May 09 02:27:39 PM PDT 24
Peak memory 214560 kb
Host smart-ce23efbd-1cdb-42f5-b12f-664beae6c8aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898866629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.898866629
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3485588121
Short name T763
Test name
Test status
Simulation time 70333763 ps
CPU time 1.03 seconds
Started May 09 02:27:36 PM PDT 24
Finished May 09 02:27:41 PM PDT 24
Peak memory 215500 kb
Host smart-18f90473-6b1d-4fbc-91cb-8e405ae014f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485588121 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3485588121
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2244449939
Short name T92
Test name
Test status
Simulation time 25259290 ps
CPU time 1.16 seconds
Started May 09 02:27:36 PM PDT 24
Finished May 09 02:27:41 PM PDT 24
Peak memory 216800 kb
Host smart-29eec88f-6ac0-4ad1-8088-54c6b31ec609
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244449939 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2244449939
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.4010090794
Short name T748
Test name
Test status
Simulation time 60904857 ps
CPU time 0.92 seconds
Started May 09 02:27:35 PM PDT 24
Finished May 09 02:27:40 PM PDT 24
Peak memory 218356 kb
Host smart-936f7276-a7a5-471b-9717-59db92a56ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010090794 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.4010090794
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1375549204
Short name T322
Test name
Test status
Simulation time 30279040 ps
CPU time 1.24 seconds
Started May 09 02:27:32 PM PDT 24
Finished May 09 02:27:38 PM PDT 24
Peak memory 218144 kb
Host smart-ebe0bcce-2094-41e5-b0d0-df6e08b63126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375549204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1375549204
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3018376744
Short name T581
Test name
Test status
Simulation time 22330920 ps
CPU time 1.1 seconds
Started May 09 02:27:35 PM PDT 24
Finished May 09 02:27:40 PM PDT 24
Peak memory 215204 kb
Host smart-34db60c7-7d2a-459d-8136-aeed5d1bdc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018376744 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3018376744
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1645939265
Short name T410
Test name
Test status
Simulation time 50816755 ps
CPU time 0.87 seconds
Started May 09 02:27:34 PM PDT 24
Finished May 09 02:27:39 PM PDT 24
Peak memory 215140 kb
Host smart-5531782c-2a95-4139-94ba-6cf93a71c57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645939265 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1645939265
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1155261672
Short name T781
Test name
Test status
Simulation time 511712546 ps
CPU time 3.02 seconds
Started May 09 02:27:34 PM PDT 24
Finished May 09 02:27:42 PM PDT 24
Peak memory 215176 kb
Host smart-8ac54614-135c-49fa-847e-63f6d1926844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155261672 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1155261672
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.474719869
Short name T731
Test name
Test status
Simulation time 55510727409 ps
CPU time 615.45 seconds
Started May 09 02:27:35 PM PDT 24
Finished May 09 02:37:54 PM PDT 24
Peak memory 217136 kb
Host smart-d668f985-c9a3-4141-b3ec-7983693d5c8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474719869 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.474719869
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.2802868122
Short name T591
Test name
Test status
Simulation time 53572368 ps
CPU time 1.32 seconds
Started May 09 02:25:31 PM PDT 24
Finished May 09 02:25:34 PM PDT 24
Peak memory 215584 kb
Host smart-8a79cce4-39a1-48cb-b65d-fe53944aa7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802868122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2802868122
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2108597774
Short name T299
Test name
Test status
Simulation time 40453455 ps
CPU time 0.99 seconds
Started May 09 02:25:45 PM PDT 24
Finished May 09 02:25:48 PM PDT 24
Peak memory 214768 kb
Host smart-dfdaca1f-4e2f-4a53-ac7a-6cab28445d4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108597774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2108597774
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3109975839
Short name T180
Test name
Test status
Simulation time 22103520 ps
CPU time 0.88 seconds
Started May 09 02:25:35 PM PDT 24
Finished May 09 02:25:37 PM PDT 24
Peak memory 216088 kb
Host smart-2fb45038-cdc4-4bd5-82fa-6e3924bd972f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109975839 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3109975839
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.493766190
Short name T103
Test name
Test status
Simulation time 199682652 ps
CPU time 1.07 seconds
Started May 09 02:25:33 PM PDT 24
Finished May 09 02:25:35 PM PDT 24
Peak memory 216644 kb
Host smart-26d72337-2ce3-4a1b-9c89-b1129c8e2c37
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493766190 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.493766190
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3895243021
Short name T804
Test name
Test status
Simulation time 42535468 ps
CPU time 1.06 seconds
Started May 09 02:25:38 PM PDT 24
Finished May 09 02:25:41 PM PDT 24
Peak memory 219552 kb
Host smart-049ec419-208d-4ad2-8964-8976386d7f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895243021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3895243021
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1985011570
Short name T451
Test name
Test status
Simulation time 58334516 ps
CPU time 1.64 seconds
Started May 09 02:25:27 PM PDT 24
Finished May 09 02:25:31 PM PDT 24
Peak memory 218120 kb
Host smart-9a5bd0d9-e712-4255-92e1-f862606c9470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985011570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1985011570
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1397606497
Short name T76
Test name
Test status
Simulation time 32400618 ps
CPU time 0.92 seconds
Started May 09 02:25:27 PM PDT 24
Finished May 09 02:25:30 PM PDT 24
Peak memory 215656 kb
Host smart-bf8c4123-d60f-4176-89ba-4c6c1fab869f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397606497 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1397606497
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1344719052
Short name T244
Test name
Test status
Simulation time 53491647 ps
CPU time 0.93 seconds
Started May 09 02:25:33 PM PDT 24
Finished May 09 02:25:35 PM PDT 24
Peak memory 206984 kb
Host smart-60393623-0ced-4a66-989e-26e17a26d092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344719052 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1344719052
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.4249359649
Short name T296
Test name
Test status
Simulation time 25218416 ps
CPU time 1.02 seconds
Started May 09 02:25:32 PM PDT 24
Finished May 09 02:25:34 PM PDT 24
Peak memory 215212 kb
Host smart-7d49ee50-8bd9-49cb-b345-2ab7fefb99fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249359649 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.4249359649
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2619818981
Short name T4
Test name
Test status
Simulation time 106983018 ps
CPU time 2.48 seconds
Started May 09 02:25:33 PM PDT 24
Finished May 09 02:25:36 PM PDT 24
Peak memory 216980 kb
Host smart-41e07f89-7043-4e39-9ce2-309891b97cb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619818981 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2619818981
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1527950347
Short name T182
Test name
Test status
Simulation time 150326959043 ps
CPU time 1668.51 seconds
Started May 09 02:25:36 PM PDT 24
Finished May 09 02:53:26 PM PDT 24
Peak memory 225240 kb
Host smart-0bc5f1ce-6dbf-4939-b02e-8fdfc3389c04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527950347 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1527950347
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.2203679940
Short name T334
Test name
Test status
Simulation time 19118660 ps
CPU time 1.07 seconds
Started May 09 02:27:33 PM PDT 24
Finished May 09 02:27:38 PM PDT 24
Peak memory 218124 kb
Host smart-f0348664-3725-45ce-bfdf-934ab0ca5951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203679940 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2203679940
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.4115091343
Short name T48
Test name
Test status
Simulation time 71472481 ps
CPU time 1.29 seconds
Started May 09 02:27:33 PM PDT 24
Finished May 09 02:27:39 PM PDT 24
Peak memory 215236 kb
Host smart-71912254-829c-436b-b91d-3e44ab06ef22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115091343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.4115091343
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.3652030735
Short name T126
Test name
Test status
Simulation time 36347185 ps
CPU time 1 seconds
Started May 09 02:27:35 PM PDT 24
Finished May 09 02:27:40 PM PDT 24
Peak memory 223644 kb
Host smart-e93f7609-cee2-4354-ae8f-c3cc523b6c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652030735 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3652030735
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2924678394
Short name T561
Test name
Test status
Simulation time 29342009 ps
CPU time 1.4 seconds
Started May 09 02:27:35 PM PDT 24
Finished May 09 02:27:41 PM PDT 24
Peak memory 219552 kb
Host smart-f6e8f6dc-172b-4457-867c-42933c6369b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924678394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2924678394
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.2687238910
Short name T111
Test name
Test status
Simulation time 34548623 ps
CPU time 0.95 seconds
Started May 09 02:27:36 PM PDT 24
Finished May 09 02:27:41 PM PDT 24
Peak memory 218360 kb
Host smart-0204f6a5-2173-4f12-981d-1a9f68561b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687238910 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2687238910
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3621587229
Short name T754
Test name
Test status
Simulation time 32786772 ps
CPU time 1.03 seconds
Started May 09 02:27:31 PM PDT 24
Finished May 09 02:27:37 PM PDT 24
Peak memory 218864 kb
Host smart-ccc93425-b317-46ba-9a6e-f55547631e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621587229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3621587229
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.328599012
Short name T672
Test name
Test status
Simulation time 47948082 ps
CPU time 1.1 seconds
Started May 09 02:27:45 PM PDT 24
Finished May 09 02:27:49 PM PDT 24
Peak memory 223832 kb
Host smart-e1935d66-1467-4d34-a65e-ac95401088ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328599012 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.328599012
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1634300028
Short name T765
Test name
Test status
Simulation time 104523291 ps
CPU time 2.78 seconds
Started May 09 02:27:46 PM PDT 24
Finished May 09 02:27:51 PM PDT 24
Peak memory 217332 kb
Host smart-df3e5ab8-6553-4445-8abe-b265e81cdf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634300028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1634300028
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.2022470622
Short name T787
Test name
Test status
Simulation time 27158495 ps
CPU time 1.32 seconds
Started May 09 02:27:45 PM PDT 24
Finished May 09 02:27:49 PM PDT 24
Peak memory 229544 kb
Host smart-f968a64f-0cd5-46f5-9710-747b012f7911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022470622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2022470622
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3614520705
Short name T723
Test name
Test status
Simulation time 56529663 ps
CPU time 1.32 seconds
Started May 09 02:27:50 PM PDT 24
Finished May 09 02:27:54 PM PDT 24
Peak memory 218304 kb
Host smart-69add14f-3051-4cfe-9db2-8396522b3d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614520705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3614520705
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.3569209622
Short name T387
Test name
Test status
Simulation time 19487840 ps
CPU time 1.03 seconds
Started May 09 02:27:43 PM PDT 24
Finished May 09 02:27:46 PM PDT 24
Peak memory 218112 kb
Host smart-45e55bab-55a5-4922-9dcc-be59ee2fd930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569209622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3569209622
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.603431066
Short name T659
Test name
Test status
Simulation time 115453602 ps
CPU time 2.61 seconds
Started May 09 02:27:42 PM PDT 24
Finished May 09 02:27:47 PM PDT 24
Peak memory 218148 kb
Host smart-a93a7ad9-13ba-413c-a98d-8dbbf8b7039e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603431066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.603431066
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.2878041244
Short name T489
Test name
Test status
Simulation time 71138220 ps
CPU time 1.06 seconds
Started May 09 02:27:43 PM PDT 24
Finished May 09 02:27:46 PM PDT 24
Peak memory 219596 kb
Host smart-4f0e1631-431a-4aac-b715-be6d40d3ae29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878041244 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2878041244
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.120644947
Short name T791
Test name
Test status
Simulation time 40287921 ps
CPU time 1.76 seconds
Started May 09 02:27:46 PM PDT 24
Finished May 09 02:27:51 PM PDT 24
Peak memory 216996 kb
Host smart-30a36e32-3c17-4828-93c9-62d25c1ffdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120644947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.120644947
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.4071267434
Short name T330
Test name
Test status
Simulation time 29956560 ps
CPU time 0.91 seconds
Started May 09 02:27:41 PM PDT 24
Finished May 09 02:27:44 PM PDT 24
Peak memory 218480 kb
Host smart-8a8fd4da-263a-4fd3-ae68-c11508fabc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071267434 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.4071267434
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.758269773
Short name T640
Test name
Test status
Simulation time 163244579 ps
CPU time 1.21 seconds
Started May 09 02:27:43 PM PDT 24
Finished May 09 02:27:46 PM PDT 24
Peak memory 217292 kb
Host smart-d5676c10-1d65-4880-8329-a1c346f78393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758269773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.758269773
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.1542933374
Short name T135
Test name
Test status
Simulation time 23563898 ps
CPU time 0.96 seconds
Started May 09 02:27:44 PM PDT 24
Finished May 09 02:27:48 PM PDT 24
Peak memory 218300 kb
Host smart-b21f20b4-08bc-435a-81b6-f0cc30786aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542933374 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1542933374
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1829463983
Short name T496
Test name
Test status
Simulation time 94533326 ps
CPU time 1.22 seconds
Started May 09 02:27:41 PM PDT 24
Finished May 09 02:27:44 PM PDT 24
Peak memory 217032 kb
Host smart-00ae6990-48fa-4e26-aedf-6cc7190e57da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829463983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1829463983
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.2649088951
Short name T84
Test name
Test status
Simulation time 26606622 ps
CPU time 1.33 seconds
Started May 09 02:27:44 PM PDT 24
Finished May 09 02:27:48 PM PDT 24
Peak memory 229636 kb
Host smart-40a3a9f0-ace8-47e2-ae4e-b1df893ed9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649088951 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2649088951
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2988268280
Short name T231
Test name
Test status
Simulation time 40890026 ps
CPU time 1.25 seconds
Started May 09 02:27:43 PM PDT 24
Finished May 09 02:27:46 PM PDT 24
Peak memory 216948 kb
Host smart-26a624d1-4b0d-4369-a9a3-524b3ae88190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988268280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2988268280
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3499405491
Short name T148
Test name
Test status
Simulation time 32094657 ps
CPU time 1.39 seconds
Started May 09 02:25:50 PM PDT 24
Finished May 09 02:25:55 PM PDT 24
Peak memory 215580 kb
Host smart-5bad6556-585b-48fe-8a07-bd60158ddaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499405491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3499405491
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3718189271
Short name T321
Test name
Test status
Simulation time 27701579 ps
CPU time 0.9 seconds
Started May 09 02:25:47 PM PDT 24
Finished May 09 02:25:52 PM PDT 24
Peak memory 206524 kb
Host smart-d922545e-2e8f-4346-9a00-fa7edcb414fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718189271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3718189271
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3363818831
Short name T401
Test name
Test status
Simulation time 19100420 ps
CPU time 0.86 seconds
Started May 09 02:25:42 PM PDT 24
Finished May 09 02:25:44 PM PDT 24
Peak memory 215812 kb
Host smart-28a508d1-e7bb-4e20-9f0e-644c8f0ae072
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363818831 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3363818831
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2851162126
Short name T648
Test name
Test status
Simulation time 39417333 ps
CPU time 1.31 seconds
Started May 09 02:25:51 PM PDT 24
Finished May 09 02:25:56 PM PDT 24
Peak memory 216592 kb
Host smart-3ad02002-9ffb-4a55-9f3a-6f112b68e344
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851162126 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2851162126
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.3253420315
Short name T583
Test name
Test status
Simulation time 72982089 ps
CPU time 1.02 seconds
Started May 09 02:25:42 PM PDT 24
Finished May 09 02:25:45 PM PDT 24
Peak memory 219624 kb
Host smart-917b3c0b-1551-4e1f-bf17-5acc9e86199a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253420315 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3253420315
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2251758571
Short name T338
Test name
Test status
Simulation time 115325115 ps
CPU time 1.52 seconds
Started May 09 02:25:36 PM PDT 24
Finished May 09 02:25:39 PM PDT 24
Peak memory 218500 kb
Host smart-d4226c90-cc29-4592-99ea-5c7554bf3833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251758571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2251758571
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2792600150
Short name T431
Test name
Test status
Simulation time 36207039 ps
CPU time 0.97 seconds
Started May 09 02:25:45 PM PDT 24
Finished May 09 02:25:48 PM PDT 24
Peak memory 223712 kb
Host smart-b9cfa377-61df-44d0-b5b9-f10c90f47a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792600150 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2792600150
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.163755857
Short name T628
Test name
Test status
Simulation time 38208531 ps
CPU time 0.84 seconds
Started May 09 02:25:48 PM PDT 24
Finished May 09 02:25:53 PM PDT 24
Peak memory 215000 kb
Host smart-2e92f7e7-09cb-43b1-8c4d-cd2ff62d307f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163755857 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.163755857
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2676097850
Short name T429
Test name
Test status
Simulation time 726787936 ps
CPU time 4.14 seconds
Started May 09 02:25:53 PM PDT 24
Finished May 09 02:26:01 PM PDT 24
Peak memory 215144 kb
Host smart-fbda3946-384c-4191-b262-47c144e9f4a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676097850 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2676097850
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1347237225
Short name T511
Test name
Test status
Simulation time 147434811027 ps
CPU time 949.45 seconds
Started May 09 02:25:49 PM PDT 24
Finished May 09 02:41:43 PM PDT 24
Peak memory 222820 kb
Host smart-06ec451c-d65f-49ce-bdcd-61b1a3791581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347237225 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1347237225
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.2002733186
Short name T309
Test name
Test status
Simulation time 21124833 ps
CPU time 0.92 seconds
Started May 09 02:27:47 PM PDT 24
Finished May 09 02:27:50 PM PDT 24
Peak memory 218208 kb
Host smart-18fa7cd7-007c-4958-b2d4-02a26c00922f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002733186 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2002733186
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.989841040
Short name T839
Test name
Test status
Simulation time 209030296 ps
CPU time 1.51 seconds
Started May 09 02:27:50 PM PDT 24
Finished May 09 02:27:54 PM PDT 24
Peak memory 218448 kb
Host smart-a47ebbfa-bc4e-44b4-a0e7-513943a6590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989841040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.989841040
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.3229082685
Short name T685
Test name
Test status
Simulation time 35986760 ps
CPU time 0.88 seconds
Started May 09 02:27:42 PM PDT 24
Finished May 09 02:27:44 PM PDT 24
Peak memory 218356 kb
Host smart-8f0ba246-93fc-48d7-a113-9456ad6961d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229082685 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3229082685
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1438418878
Short name T361
Test name
Test status
Simulation time 75658394 ps
CPU time 1.64 seconds
Started May 09 02:27:43 PM PDT 24
Finished May 09 02:27:47 PM PDT 24
Peak memory 217008 kb
Host smart-cea82aca-6123-4ee5-aa1c-19ce6229c99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438418878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1438418878
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.3625961455
Short name T555
Test name
Test status
Simulation time 24906699 ps
CPU time 1.01 seconds
Started May 09 02:27:45 PM PDT 24
Finished May 09 02:27:49 PM PDT 24
Peak memory 219488 kb
Host smart-5a10b842-cb4a-4f5b-96e6-a4d1e89132c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625961455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3625961455
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3456580714
Short name T306
Test name
Test status
Simulation time 67819564 ps
CPU time 1.19 seconds
Started May 09 02:27:45 PM PDT 24
Finished May 09 02:27:49 PM PDT 24
Peak memory 218380 kb
Host smart-fa029ddb-24de-4e0f-b17f-734077b82bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456580714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3456580714
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.1662314802
Short name T497
Test name
Test status
Simulation time 26680121 ps
CPU time 0.99 seconds
Started May 09 02:27:48 PM PDT 24
Finished May 09 02:27:51 PM PDT 24
Peak memory 218268 kb
Host smart-22e01d14-e954-471a-987f-7950ba0e3095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662314802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1662314802
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3614800842
Short name T576
Test name
Test status
Simulation time 37443243 ps
CPU time 1.83 seconds
Started May 09 02:27:44 PM PDT 24
Finished May 09 02:27:48 PM PDT 24
Peak memory 218244 kb
Host smart-025861ce-8945-40ce-8034-ef741d9f5b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614800842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3614800842
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.152530277
Short name T669
Test name
Test status
Simulation time 23365977 ps
CPU time 1.04 seconds
Started May 09 02:27:47 PM PDT 24
Finished May 09 02:27:50 PM PDT 24
Peak memory 218324 kb
Host smart-3c921548-bee1-4f26-ab9f-c4045e4d38f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152530277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.152530277
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2556057926
Short name T270
Test name
Test status
Simulation time 69804601 ps
CPU time 1.52 seconds
Started May 09 02:27:50 PM PDT 24
Finished May 09 02:27:54 PM PDT 24
Peak memory 218256 kb
Host smart-95b8287a-da20-47c7-bc71-e38ae575c8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556057926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2556057926
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.2930775265
Short name T837
Test name
Test status
Simulation time 29518645 ps
CPU time 0.81 seconds
Started May 09 02:27:45 PM PDT 24
Finished May 09 02:27:49 PM PDT 24
Peak memory 217888 kb
Host smart-3582339c-c173-46d3-a410-64ac4a6c27ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930775265 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2930775265
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1219154765
Short name T294
Test name
Test status
Simulation time 163667680 ps
CPU time 2.95 seconds
Started May 09 02:27:50 PM PDT 24
Finished May 09 02:27:56 PM PDT 24
Peak memory 218312 kb
Host smart-8aee88d4-ea4f-4bb0-9cf9-9f1b7d7dfd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219154765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1219154765
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.3224493809
Short name T615
Test name
Test status
Simulation time 31634509 ps
CPU time 0.9 seconds
Started May 09 02:27:45 PM PDT 24
Finished May 09 02:27:48 PM PDT 24
Peak memory 217776 kb
Host smart-051d1e48-ce3e-4b48-989d-60ef6e5ba3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224493809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3224493809
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.4273941864
Short name T566
Test name
Test status
Simulation time 50446053 ps
CPU time 1.33 seconds
Started May 09 02:27:42 PM PDT 24
Finished May 09 02:27:45 PM PDT 24
Peak memory 218140 kb
Host smart-c8a0c77b-f80f-42b0-a2c7-5654d4f5507a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273941864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.4273941864
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.1296311449
Short name T155
Test name
Test status
Simulation time 18152468 ps
CPU time 1.05 seconds
Started May 09 02:27:48 PM PDT 24
Finished May 09 02:27:51 PM PDT 24
Peak memory 218368 kb
Host smart-7fbbd7a1-f849-40b2-a1f6-39c41b2c25cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296311449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1296311449
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2694731702
Short name T144
Test name
Test status
Simulation time 82952568 ps
CPU time 1.16 seconds
Started May 09 02:27:48 PM PDT 24
Finished May 09 02:27:51 PM PDT 24
Peak memory 219532 kb
Host smart-f3cecc04-701f-4be8-907a-6c3ea64a8063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694731702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2694731702
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.107528174
Short name T377
Test name
Test status
Simulation time 20038971 ps
CPU time 1.13 seconds
Started May 09 02:27:42 PM PDT 24
Finished May 09 02:27:45 PM PDT 24
Peak memory 219628 kb
Host smart-f48ed767-f641-47a5-a55b-bc4b3c4914af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107528174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.107528174
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2841887917
Short name T537
Test name
Test status
Simulation time 76166885 ps
CPU time 2.49 seconds
Started May 09 02:27:45 PM PDT 24
Finished May 09 02:27:51 PM PDT 24
Peak memory 219120 kb
Host smart-19212ba4-0b11-45b2-8340-58081dfe04b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841887917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2841887917
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.1093564529
Short name T507
Test name
Test status
Simulation time 31396062 ps
CPU time 0.88 seconds
Started May 09 02:27:51 PM PDT 24
Finished May 09 02:27:56 PM PDT 24
Peak memory 218264 kb
Host smart-b6158b2f-1838-4b15-b25e-4ee3f68a1b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093564529 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1093564529
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1937377763
Short name T677
Test name
Test status
Simulation time 51121189 ps
CPU time 1.38 seconds
Started May 09 02:27:43 PM PDT 24
Finished May 09 02:27:46 PM PDT 24
Peak memory 216912 kb
Host smart-981b8339-025c-4f3e-9bb6-e6b957eb19df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937377763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1937377763
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1941887825
Short name T123
Test name
Test status
Simulation time 38885725 ps
CPU time 1.15 seconds
Started May 09 02:25:49 PM PDT 24
Finished May 09 02:25:54 PM PDT 24
Peak memory 215480 kb
Host smart-6236d4fc-f582-4355-956a-e5a47653cd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941887825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1941887825
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2820728346
Short name T436
Test name
Test status
Simulation time 15096254 ps
CPU time 0.89 seconds
Started May 09 02:25:43 PM PDT 24
Finished May 09 02:25:46 PM PDT 24
Peak memory 206544 kb
Host smart-45b47f11-5235-4ce7-8213-e69a0cda2b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820728346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2820728346
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.325616519
Short name T170
Test name
Test status
Simulation time 26307985 ps
CPU time 0.82 seconds
Started May 09 02:25:42 PM PDT 24
Finished May 09 02:25:44 PM PDT 24
Peak memory 216056 kb
Host smart-822c04d5-7867-4399-9023-f1860ca884ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325616519 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.325616519
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1742735948
Short name T110
Test name
Test status
Simulation time 465664522 ps
CPU time 1.2 seconds
Started May 09 02:25:46 PM PDT 24
Finished May 09 02:25:51 PM PDT 24
Peak memory 216708 kb
Host smart-677981d3-a801-4617-b985-d25bbb6c184d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742735948 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1742735948
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.727294589
Short name T93
Test name
Test status
Simulation time 61111035 ps
CPU time 1.19 seconds
Started May 09 02:25:38 PM PDT 24
Finished May 09 02:25:40 PM PDT 24
Peak memory 229524 kb
Host smart-319a409a-b2af-4930-a82d-aac0c0492ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727294589 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.727294589
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1475898816
Short name T343
Test name
Test status
Simulation time 64416628 ps
CPU time 1.37 seconds
Started May 09 02:25:45 PM PDT 24
Finished May 09 02:25:49 PM PDT 24
Peak memory 218076 kb
Host smart-c91bb6b1-1f23-4bf4-9358-56097583734e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475898816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1475898816
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.347281175
Short name T736
Test name
Test status
Simulation time 27463220 ps
CPU time 0.95 seconds
Started May 09 02:25:48 PM PDT 24
Finished May 09 02:25:53 PM PDT 24
Peak memory 215448 kb
Host smart-a2e607f4-8773-48a7-8f0e-b2b1f9b1405b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347281175 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.347281175
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.487693453
Short name T249
Test name
Test status
Simulation time 72533668 ps
CPU time 0.83 seconds
Started May 09 02:25:45 PM PDT 24
Finished May 09 02:25:48 PM PDT 24
Peak memory 206796 kb
Host smart-93c74fa5-7930-4fbe-9008-4c7cafffeb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487693453 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.487693453
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1891557802
Short name T513
Test name
Test status
Simulation time 15931941 ps
CPU time 1.02 seconds
Started May 09 02:25:35 PM PDT 24
Finished May 09 02:25:37 PM PDT 24
Peak memory 215176 kb
Host smart-7a0488fd-7145-4410-88f4-f0159467cc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891557802 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1891557802
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.603676904
Short name T379
Test name
Test status
Simulation time 730795863 ps
CPU time 4.46 seconds
Started May 09 02:25:37 PM PDT 24
Finished May 09 02:25:43 PM PDT 24
Peak memory 216776 kb
Host smart-ebd33230-eb8f-4ccf-819c-583d225a3760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603676904 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.603676904
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3377611266
Short name T62
Test name
Test status
Simulation time 125219205153 ps
CPU time 1620.03 seconds
Started May 09 02:25:34 PM PDT 24
Finished May 09 02:52:35 PM PDT 24
Peak memory 226444 kb
Host smart-ec7230ea-dd53-475f-ba66-be4f52e460a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377611266 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3377611266
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.2040839242
Short name T817
Test name
Test status
Simulation time 24568813 ps
CPU time 1.02 seconds
Started May 09 02:27:55 PM PDT 24
Finished May 09 02:28:00 PM PDT 24
Peak memory 219760 kb
Host smart-17f22385-05bd-4399-99b1-265bdbea461a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040839242 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2040839242
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2516857902
Short name T739
Test name
Test status
Simulation time 36070522 ps
CPU time 1.29 seconds
Started May 09 02:27:52 PM PDT 24
Finished May 09 02:27:58 PM PDT 24
Peak memory 218320 kb
Host smart-720da289-f28a-4abb-bbc5-4153b507133c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516857902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2516857902
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.92633823
Short name T107
Test name
Test status
Simulation time 49511467 ps
CPU time 0.98 seconds
Started May 09 02:27:53 PM PDT 24
Finished May 09 02:27:58 PM PDT 24
Peak memory 219424 kb
Host smart-c25fe56d-8f49-4f31-8e3b-88ef7b6ff07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92633823 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.92633823
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.622175556
Short name T666
Test name
Test status
Simulation time 73350972 ps
CPU time 1.22 seconds
Started May 09 02:27:54 PM PDT 24
Finished May 09 02:27:59 PM PDT 24
Peak memory 218412 kb
Host smart-31e5e41e-7a44-4968-968e-427b5631ed95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622175556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.622175556
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.717062124
Short name T122
Test name
Test status
Simulation time 19139143 ps
CPU time 1.11 seconds
Started May 09 02:27:55 PM PDT 24
Finished May 09 02:28:00 PM PDT 24
Peak memory 218292 kb
Host smart-f833ea9b-6037-496a-a420-d9dc62da54b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717062124 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.717062124
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.479677871
Short name T457
Test name
Test status
Simulation time 603696374 ps
CPU time 5.13 seconds
Started May 09 02:27:52 PM PDT 24
Finished May 09 02:28:00 PM PDT 24
Peak memory 218916 kb
Host smart-a4381fed-e6e0-449c-a484-48734dc41420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479677871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.479677871
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.625628664
Short name T598
Test name
Test status
Simulation time 22343184 ps
CPU time 1.01 seconds
Started May 09 02:27:53 PM PDT 24
Finished May 09 02:27:58 PM PDT 24
Peak memory 223920 kb
Host smart-cb1b2170-f9e7-4c54-a468-2da607b3d569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625628664 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.625628664
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.694831679
Short name T339
Test name
Test status
Simulation time 99622880 ps
CPU time 1.08 seconds
Started May 09 02:27:51 PM PDT 24
Finished May 09 02:27:56 PM PDT 24
Peak memory 219524 kb
Host smart-3714fd7e-4133-4644-9b8d-b0cde7413494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694831679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.694831679
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.2189818253
Short name T35
Test name
Test status
Simulation time 18252990 ps
CPU time 1.08 seconds
Started May 09 02:27:50 PM PDT 24
Finished May 09 02:27:54 PM PDT 24
Peak memory 218120 kb
Host smart-fd7e3488-57b0-4232-961f-2bdf90556e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189818253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2189818253
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2338527740
Short name T512
Test name
Test status
Simulation time 176593663 ps
CPU time 1.16 seconds
Started May 09 02:27:54 PM PDT 24
Finished May 09 02:27:59 PM PDT 24
Peak memory 219036 kb
Host smart-5d8899ee-8daf-409a-bb78-2050d1dfdfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338527740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2338527740
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.511487535
Short name T510
Test name
Test status
Simulation time 20866107 ps
CPU time 0.91 seconds
Started May 09 02:27:53 PM PDT 24
Finished May 09 02:27:58 PM PDT 24
Peak memory 218308 kb
Host smart-c1bc22ed-ff2e-4f48-a913-3b09c84dec08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511487535 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.511487535
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.4176706508
Short name T284
Test name
Test status
Simulation time 47646082 ps
CPU time 1.91 seconds
Started May 09 02:27:54 PM PDT 24
Finished May 09 02:28:00 PM PDT 24
Peak memory 218088 kb
Host smart-0595aa15-032c-4d7e-84d1-95a311308d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176706508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.4176706508
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.2419441858
Short name T117
Test name
Test status
Simulation time 34339093 ps
CPU time 0.86 seconds
Started May 09 02:27:53 PM PDT 24
Finished May 09 02:27:58 PM PDT 24
Peak memory 218292 kb
Host smart-190af960-5d25-43ff-99a1-35b08e2dacff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419441858 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2419441858
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.977992883
Short name T398
Test name
Test status
Simulation time 74421990 ps
CPU time 1.24 seconds
Started May 09 02:27:51 PM PDT 24
Finished May 09 02:27:56 PM PDT 24
Peak memory 215208 kb
Host smart-c20e86d4-d31c-4195-b8ec-e33603f33fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977992883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.977992883
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.3345323345
Short name T524
Test name
Test status
Simulation time 32635691 ps
CPU time 1.04 seconds
Started May 09 02:27:53 PM PDT 24
Finished May 09 02:27:58 PM PDT 24
Peak memory 224068 kb
Host smart-ea2fbf3c-cb3b-4737-993f-255bf5e42060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345323345 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3345323345
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2540415736
Short name T347
Test name
Test status
Simulation time 49087576 ps
CPU time 1.93 seconds
Started May 09 02:27:52 PM PDT 24
Finished May 09 02:27:58 PM PDT 24
Peak memory 217964 kb
Host smart-4e05d4c0-b16c-4d7f-bf21-145fc3008fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540415736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2540415736
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.1247857898
Short name T102
Test name
Test status
Simulation time 38188512 ps
CPU time 0.94 seconds
Started May 09 02:27:52 PM PDT 24
Finished May 09 02:27:57 PM PDT 24
Peak memory 219692 kb
Host smart-ce603683-357b-4259-8fc6-19e07e0f8fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247857898 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1247857898
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2950412528
Short name T520
Test name
Test status
Simulation time 28010617 ps
CPU time 1.41 seconds
Started May 09 02:27:55 PM PDT 24
Finished May 09 02:28:00 PM PDT 24
Peak memory 219556 kb
Host smart-13de34b9-51f6-42d4-bb8f-be3a5d2cb17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950412528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2950412528
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.4168713485
Short name T509
Test name
Test status
Simulation time 74050933 ps
CPU time 1.37 seconds
Started May 09 02:27:55 PM PDT 24
Finished May 09 02:28:00 PM PDT 24
Peak memory 224828 kb
Host smart-11664780-38c9-4fcd-bdb6-d5d4c5c7e3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168713485 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.4168713485
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3217093561
Short name T324
Test name
Test status
Simulation time 101790343 ps
CPU time 1.35 seconds
Started May 09 02:27:52 PM PDT 24
Finished May 09 02:27:58 PM PDT 24
Peak memory 217388 kb
Host smart-4913a2c6-89d2-4434-8d96-f16de27c39da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217093561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3217093561
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.552988365
Short name T808
Test name
Test status
Simulation time 51639980 ps
CPU time 1.18 seconds
Started May 09 02:25:47 PM PDT 24
Finished May 09 02:25:52 PM PDT 24
Peak memory 215500 kb
Host smart-a305b1fe-3f56-4f5c-bc6c-5bd55b4e7d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552988365 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.552988365
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3875246032
Short name T719
Test name
Test status
Simulation time 28435891 ps
CPU time 0.94 seconds
Started May 09 02:25:49 PM PDT 24
Finished May 09 02:25:54 PM PDT 24
Peak memory 214656 kb
Host smart-eff458c2-8ac3-4846-bbb5-312130243988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875246032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3875246032
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.4068248115
Short name T835
Test name
Test status
Simulation time 36544715 ps
CPU time 0.84 seconds
Started May 09 02:25:37 PM PDT 24
Finished May 09 02:25:39 PM PDT 24
Peak memory 216088 kb
Host smart-48a8e9ef-de22-495a-85f9-5790eee5bbfd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068248115 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.4068248115
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.758750146
Short name T289
Test name
Test status
Simulation time 25709948 ps
CPU time 1.06 seconds
Started May 09 02:25:42 PM PDT 24
Finished May 09 02:25:44 PM PDT 24
Peak memory 216716 kb
Host smart-e17dcdde-7131-4f38-afa0-0c84feffda68
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758750146 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.758750146
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.104692892
Short name T342
Test name
Test status
Simulation time 19379318 ps
CPU time 1.02 seconds
Started May 09 02:25:36 PM PDT 24
Finished May 09 02:25:38 PM PDT 24
Peak memory 218132 kb
Host smart-0e843021-6f0e-4f84-b6a9-7ed7f5bfd271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104692892 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.104692892
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1438586750
Short name T192
Test name
Test status
Simulation time 84196640 ps
CPU time 1.17 seconds
Started May 09 02:25:46 PM PDT 24
Finished May 09 02:25:51 PM PDT 24
Peak memory 218452 kb
Host smart-449b52fe-62c2-4e9d-a4e6-88d0ae58241d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438586750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1438586750
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_regwen.317268838
Short name T25
Test name
Test status
Simulation time 28165270 ps
CPU time 0.92 seconds
Started May 09 02:25:50 PM PDT 24
Finished May 09 02:25:55 PM PDT 24
Peak memory 206928 kb
Host smart-b477c706-ee65-4f36-a194-aa21b4f9963a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317268838 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.317268838
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3064447178
Short name T665
Test name
Test status
Simulation time 21541242 ps
CPU time 1.03 seconds
Started May 09 02:25:45 PM PDT 24
Finished May 09 02:25:49 PM PDT 24
Peak memory 215152 kb
Host smart-9e2eaa95-9fda-449e-88b3-c5f75b8570ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064447178 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3064447178
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.286950537
Short name T543
Test name
Test status
Simulation time 511091243 ps
CPU time 3.08 seconds
Started May 09 02:25:49 PM PDT 24
Finished May 09 02:25:56 PM PDT 24
Peak memory 216792 kb
Host smart-38a0081f-8f6e-4a18-81a3-e0ec15c172aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286950537 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.286950537
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1108258102
Short name T187
Test name
Test status
Simulation time 196446198628 ps
CPU time 1061.3 seconds
Started May 09 02:25:45 PM PDT 24
Finished May 09 02:43:28 PM PDT 24
Peak memory 221180 kb
Host smart-20c7abdc-6c17-41b4-acfb-e0ae4b06bdf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108258102 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1108258102
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.78787317
Short name T55
Test name
Test status
Simulation time 27095085 ps
CPU time 0.95 seconds
Started May 09 02:28:05 PM PDT 24
Finished May 09 02:28:10 PM PDT 24
Peak memory 223748 kb
Host smart-42d648f3-281a-4b10-9fe8-5201abbb86a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78787317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.78787317
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3706352450
Short name T726
Test name
Test status
Simulation time 128619018 ps
CPU time 1.35 seconds
Started May 09 02:28:05 PM PDT 24
Finished May 09 02:28:12 PM PDT 24
Peak memory 217332 kb
Host smart-b09f09c6-cd68-4bbb-b7aa-95c82800a2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706352450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3706352450
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.35069974
Short name T421
Test name
Test status
Simulation time 22857939 ps
CPU time 1.06 seconds
Started May 09 02:28:03 PM PDT 24
Finished May 09 02:28:07 PM PDT 24
Peak memory 223900 kb
Host smart-0b0dd20f-90c5-45c2-b807-ecbc5e3f19be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35069974 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.35069974
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.735699171
Short name T427
Test name
Test status
Simulation time 77627525 ps
CPU time 1.1 seconds
Started May 09 02:28:06 PM PDT 24
Finished May 09 02:28:12 PM PDT 24
Peak memory 216836 kb
Host smart-c823a6e2-c2ea-42ef-9968-a59239e55cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735699171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.735699171
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.3605526688
Short name T406
Test name
Test status
Simulation time 19017246 ps
CPU time 1.12 seconds
Started May 09 02:28:02 PM PDT 24
Finished May 09 02:28:05 PM PDT 24
Peak memory 223848 kb
Host smart-d3aefac5-7a2d-4a7a-8f41-ddfe897ae2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605526688 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3605526688
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.698430744
Short name T653
Test name
Test status
Simulation time 84618400 ps
CPU time 1.16 seconds
Started May 09 02:28:01 PM PDT 24
Finished May 09 02:28:03 PM PDT 24
Peak memory 219084 kb
Host smart-b4b7b338-b35e-47f9-95d7-b84ebd4e2748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698430744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.698430744
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.889185465
Short name T106
Test name
Test status
Simulation time 37915876 ps
CPU time 1.48 seconds
Started May 09 02:28:06 PM PDT 24
Finished May 09 02:28:13 PM PDT 24
Peak memory 229364 kb
Host smart-3fd147f0-17c1-4a28-9ddf-5707048fa552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889185465 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.889185465
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2183548048
Short name T823
Test name
Test status
Simulation time 93148325 ps
CPU time 1.45 seconds
Started May 09 02:28:04 PM PDT 24
Finished May 09 02:28:10 PM PDT 24
Peak memory 218532 kb
Host smart-a03d3c6e-322c-4576-a9b4-414d33d15eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183548048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2183548048
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.878722873
Short name T95
Test name
Test status
Simulation time 23632752 ps
CPU time 1.22 seconds
Started May 09 02:28:03 PM PDT 24
Finished May 09 02:28:07 PM PDT 24
Peak memory 219896 kb
Host smart-351e0deb-c253-44b4-a0c6-20bcb63d6db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878722873 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.878722873
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.4220929617
Short name T792
Test name
Test status
Simulation time 307339715 ps
CPU time 1.73 seconds
Started May 09 02:28:06 PM PDT 24
Finished May 09 02:28:13 PM PDT 24
Peak memory 217612 kb
Host smart-dd79d246-b994-46d6-af63-9964e9814030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220929617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.4220929617
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.309442441
Short name T159
Test name
Test status
Simulation time 19382248 ps
CPU time 1.03 seconds
Started May 09 02:28:04 PM PDT 24
Finished May 09 02:28:09 PM PDT 24
Peak memory 218424 kb
Host smart-0c4b8b99-0123-44f3-86e2-6797c3aa608d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309442441 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.309442441
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3607149058
Short name T469
Test name
Test status
Simulation time 77643586 ps
CPU time 1.37 seconds
Started May 09 02:28:06 PM PDT 24
Finished May 09 02:28:13 PM PDT 24
Peak memory 217392 kb
Host smart-c9167afa-1f83-4c56-8f91-265259439683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607149058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3607149058
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1993083473
Short name T800
Test name
Test status
Simulation time 40950780 ps
CPU time 1.11 seconds
Started May 09 02:28:05 PM PDT 24
Finished May 09 02:28:10 PM PDT 24
Peak memory 218248 kb
Host smart-4c62960b-36b0-4199-baf6-9d6ee030a299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993083473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1993083473
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.904421204
Short name T502
Test name
Test status
Simulation time 274776910 ps
CPU time 1.53 seconds
Started May 09 02:28:01 PM PDT 24
Finished May 09 02:28:04 PM PDT 24
Peak memory 218460 kb
Host smart-9b7355e0-eed4-46e9-85fb-69cc85c69bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904421204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.904421204
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.221555647
Short name T569
Test name
Test status
Simulation time 37202000 ps
CPU time 0.98 seconds
Started May 09 02:28:05 PM PDT 24
Finished May 09 02:28:10 PM PDT 24
Peak memory 219524 kb
Host smart-ac8290e7-3e93-4e8c-905c-5ae965676e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221555647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.221555647
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.339721830
Short name T390
Test name
Test status
Simulation time 55466923 ps
CPU time 1.24 seconds
Started May 09 02:28:05 PM PDT 24
Finished May 09 02:28:10 PM PDT 24
Peak memory 215244 kb
Host smart-11baab4f-62e6-4ab2-b7c8-f3343bd8116b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339721830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.339721830
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.473295810
Short name T7
Test name
Test status
Simulation time 25059053 ps
CPU time 1.18 seconds
Started May 09 02:28:03 PM PDT 24
Finished May 09 02:28:07 PM PDT 24
Peak memory 220492 kb
Host smart-11492a5e-5db3-45ea-96d5-af69c90e4041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473295810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.473295810
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1591441788
Short name T683
Test name
Test status
Simulation time 99112941 ps
CPU time 1.24 seconds
Started May 09 02:28:03 PM PDT 24
Finished May 09 02:28:07 PM PDT 24
Peak memory 218156 kb
Host smart-59887ed6-63b9-4894-9c22-e8a2779c9f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591441788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1591441788
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.2037902738
Short name T307
Test name
Test status
Simulation time 19017996 ps
CPU time 1.14 seconds
Started May 09 02:28:04 PM PDT 24
Finished May 09 02:28:10 PM PDT 24
Peak memory 218240 kb
Host smart-85eca6a5-9497-45f5-8f85-64e5d8d69dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037902738 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2037902738
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.690530719
Short name T780
Test name
Test status
Simulation time 47805967 ps
CPU time 1.1 seconds
Started May 09 02:28:08 PM PDT 24
Finished May 09 02:28:13 PM PDT 24
Peak memory 217008 kb
Host smart-4d700e0c-ecf9-4cf2-a520-bb6df44d969e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690530719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.690530719
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.4109258817
Short name T247
Test name
Test status
Simulation time 108370785 ps
CPU time 1.22 seconds
Started May 09 02:25:44 PM PDT 24
Finished May 09 02:25:48 PM PDT 24
Peak memory 215520 kb
Host smart-c1a37947-a81a-44db-84ad-013a1933f0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109258817 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.4109258817
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2564669595
Short name T346
Test name
Test status
Simulation time 15632069 ps
CPU time 0.88 seconds
Started May 09 02:25:42 PM PDT 24
Finished May 09 02:25:44 PM PDT 24
Peak memory 206576 kb
Host smart-2778d740-d390-4f0f-90a4-2eda3a208bce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564669595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2564669595
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1591043728
Short name T28
Test name
Test status
Simulation time 25447407 ps
CPU time 0.89 seconds
Started May 09 02:25:36 PM PDT 24
Finished May 09 02:25:38 PM PDT 24
Peak memory 215316 kb
Host smart-068f885a-644f-417d-a779-90ab37a14eb0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591043728 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1591043728
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1537259591
Short name T97
Test name
Test status
Simulation time 84965538 ps
CPU time 1.17 seconds
Started May 09 02:25:42 PM PDT 24
Finished May 09 02:25:45 PM PDT 24
Peak memory 218360 kb
Host smart-57fb52da-c85b-4601-ad3d-79668c3f2747
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537259591 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1537259591
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3232538688
Short name T100
Test name
Test status
Simulation time 20624398 ps
CPU time 1.13 seconds
Started May 09 02:25:44 PM PDT 24
Finished May 09 02:25:46 PM PDT 24
Peak memory 219660 kb
Host smart-58af72fd-5695-47fe-b76d-75ed192dcbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232538688 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3232538688
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_intr.1521512476
Short name T618
Test name
Test status
Simulation time 21734953 ps
CPU time 1.09 seconds
Started May 09 02:25:45 PM PDT 24
Finished May 09 02:25:48 PM PDT 24
Peak memory 215232 kb
Host smart-4f0d351f-ac74-4996-a55c-e5dd406a62ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521512476 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1521512476
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3305579233
Short name T23
Test name
Test status
Simulation time 28717485 ps
CPU time 0.96 seconds
Started May 09 02:25:43 PM PDT 24
Finished May 09 02:25:45 PM PDT 24
Peak memory 206948 kb
Host smart-caec1000-11ae-4ebe-b4a6-165c95908c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305579233 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3305579233
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3363154597
Short name T325
Test name
Test status
Simulation time 50459012 ps
CPU time 0.95 seconds
Started May 09 02:25:34 PM PDT 24
Finished May 09 02:25:37 PM PDT 24
Peak memory 215188 kb
Host smart-dd6e9324-d98e-4b21-9768-4c97dc831646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363154597 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3363154597
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1741243314
Short name T467
Test name
Test status
Simulation time 683816700 ps
CPU time 4.32 seconds
Started May 09 02:25:46 PM PDT 24
Finished May 09 02:25:52 PM PDT 24
Peak memory 215204 kb
Host smart-0a01cdd9-9e74-4f37-a634-45e6c142e1b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741243314 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1741243314
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3155742055
Short name T812
Test name
Test status
Simulation time 510485162234 ps
CPU time 2304.03 seconds
Started May 09 02:25:42 PM PDT 24
Finished May 09 03:04:08 PM PDT 24
Peak memory 228044 kb
Host smart-94f03f20-60a6-42a0-897f-60ad4a8cd51c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155742055 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3155742055
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.61044095
Short name T164
Test name
Test status
Simulation time 253777278 ps
CPU time 1.39 seconds
Started May 09 02:28:03 PM PDT 24
Finished May 09 02:28:08 PM PDT 24
Peak memory 225532 kb
Host smart-9f5e3acf-b6f7-4441-94ac-e18a63ba7822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61044095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.61044095
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2637537826
Short name T313
Test name
Test status
Simulation time 42208126 ps
CPU time 1.42 seconds
Started May 09 02:28:04 PM PDT 24
Finished May 09 02:28:09 PM PDT 24
Peak memory 216980 kb
Host smart-890214e6-9bee-4517-871c-387201aaa319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637537826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2637537826
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.4260260880
Short name T407
Test name
Test status
Simulation time 66154401 ps
CPU time 0.95 seconds
Started May 09 02:28:07 PM PDT 24
Finished May 09 02:28:13 PM PDT 24
Peak memory 218208 kb
Host smart-1c6be9f6-178a-48a2-b0ee-8fd0d8c29bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260260880 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.4260260880
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.925163316
Short name T717
Test name
Test status
Simulation time 204515309 ps
CPU time 1.07 seconds
Started May 09 02:28:05 PM PDT 24
Finished May 09 02:28:11 PM PDT 24
Peak memory 217084 kb
Host smart-b53c7094-9d65-40c9-9b48-82c4a8c38486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925163316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.925163316
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.2670775455
Short name T134
Test name
Test status
Simulation time 33536479 ps
CPU time 1 seconds
Started May 09 02:28:06 PM PDT 24
Finished May 09 02:28:12 PM PDT 24
Peak memory 223688 kb
Host smart-e3cc727d-0625-4626-8be2-475366699693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670775455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2670775455
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/93.edn_err.1980984965
Short name T597
Test name
Test status
Simulation time 29401890 ps
CPU time 1.24 seconds
Started May 09 02:28:06 PM PDT 24
Finished May 09 02:28:12 PM PDT 24
Peak memory 219580 kb
Host smart-f4e5233f-467d-4bb8-a789-4714b3c33e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980984965 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1980984965
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.4285471413
Short name T228
Test name
Test status
Simulation time 40852083 ps
CPU time 1.12 seconds
Started May 09 02:28:07 PM PDT 24
Finished May 09 02:28:13 PM PDT 24
Peak memory 218136 kb
Host smart-fc2fd49b-ff14-48bf-8f6d-7ec966a5942f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285471413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.4285471413
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.3191549211
Short name T54
Test name
Test status
Simulation time 29402496 ps
CPU time 0.98 seconds
Started May 09 02:28:06 PM PDT 24
Finished May 09 02:28:12 PM PDT 24
Peak memory 223748 kb
Host smart-52c42661-5cd1-4d18-a89a-133a582fb0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191549211 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3191549211
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3474366869
Short name T302
Test name
Test status
Simulation time 32931349 ps
CPU time 1.38 seconds
Started May 09 02:28:08 PM PDT 24
Finished May 09 02:28:14 PM PDT 24
Peak memory 218204 kb
Host smart-538fd4cd-670f-4fde-93d1-d1d049f133bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474366869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3474366869
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.3377231029
Short name T574
Test name
Test status
Simulation time 79370422 ps
CPU time 0.99 seconds
Started May 09 02:28:13 PM PDT 24
Finished May 09 02:28:18 PM PDT 24
Peak memory 218488 kb
Host smart-3ea6cd4c-50cf-4432-bb90-ccceb01dd727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377231029 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3377231029
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1610886014
Short name T348
Test name
Test status
Simulation time 145606391 ps
CPU time 1.19 seconds
Started May 09 02:28:12 PM PDT 24
Finished May 09 02:28:18 PM PDT 24
Peak memory 216868 kb
Host smart-a3cca464-64c4-476a-894f-91e95777de2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610886014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1610886014
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3801726224
Short name T826
Test name
Test status
Simulation time 78270744 ps
CPU time 0.9 seconds
Started May 09 02:28:11 PM PDT 24
Finished May 09 02:28:16 PM PDT 24
Peak memory 232164 kb
Host smart-65067550-8d8d-48ff-8c43-990f9295b52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801726224 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3801726224
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2574460071
Short name T623
Test name
Test status
Simulation time 64329617 ps
CPU time 1.04 seconds
Started May 09 02:28:12 PM PDT 24
Finished May 09 02:28:18 PM PDT 24
Peak memory 217092 kb
Host smart-0dea6814-4fc2-4f41-82b2-2246082eee3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574460071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2574460071
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.2744131277
Short name T162
Test name
Test status
Simulation time 33284913 ps
CPU time 0.91 seconds
Started May 09 02:28:14 PM PDT 24
Finished May 09 02:28:20 PM PDT 24
Peak memory 218316 kb
Host smart-28bc8dd3-b0f3-47c1-beea-1dcdc966195d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744131277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2744131277
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1638580268
Short name T269
Test name
Test status
Simulation time 54916021 ps
CPU time 1.39 seconds
Started May 09 02:28:12 PM PDT 24
Finished May 09 02:28:17 PM PDT 24
Peak memory 218272 kb
Host smart-cd74af5b-a1bd-4f73-9253-5e99835ef111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638580268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1638580268
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.3509097830
Short name T125
Test name
Test status
Simulation time 49874831 ps
CPU time 0.91 seconds
Started May 09 02:28:18 PM PDT 24
Finished May 09 02:28:23 PM PDT 24
Peak memory 218096 kb
Host smart-09cfc467-3201-452b-b0c3-7ae8e72295de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509097830 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3509097830
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3806963560
Short name T624
Test name
Test status
Simulation time 48457960 ps
CPU time 1.36 seconds
Started May 09 02:28:15 PM PDT 24
Finished May 09 02:28:22 PM PDT 24
Peak memory 218128 kb
Host smart-9f6e666f-e8f4-4dc6-8127-56000b86d4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806963560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3806963560
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.541780498
Short name T501
Test name
Test status
Simulation time 27786252 ps
CPU time 0.85 seconds
Started May 09 02:28:15 PM PDT 24
Finished May 09 02:28:22 PM PDT 24
Peak memory 218328 kb
Host smart-236bca31-c4b7-40d8-98c5-575c375bbcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541780498 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.541780498
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2776886130
Short name T268
Test name
Test status
Simulation time 136507136 ps
CPU time 1.23 seconds
Started May 09 02:28:15 PM PDT 24
Finished May 09 02:28:21 PM PDT 24
Peak memory 218704 kb
Host smart-ee390559-4d67-4f6b-b18c-c5faaad94d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776886130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2776886130
Directory /workspace/99.edn_genbits/latest
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