Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 2 0 2 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 7711 1 T3 199 T100 7 T101 96
all_values[1] 7711 1 T3 199 T100 7 T101 96


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8019 1 T3 202 T100 9 T101 116
auto[1] 7403 1 T3 196 T100 5 T101 76


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6069 1 T3 166 T100 1 T101 69
auto[1] 9353 1 T3 232 T100 13 T101 123


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9156 1 T3 232 T100 5 T101 113
auto[1] 6266 1 T3 166 T100 9 T101 79


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 12 0 12 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 1635 1 T3 46 T101 19 T125 3
all_values[0] auto[0] auto[0] auto[1] 773 1 T3 15 T100 1 T101 15
all_values[0] auto[0] auto[1] auto[0] 1420 1 T3 31 T101 11 T143 1
all_values[0] auto[0] auto[1] auto[1] 764 1 T3 15 T100 2 T101 8
all_values[0] auto[1] auto[0] auto[1] 1645 1 T3 42 T100 2 T101 27
all_values[0] auto[1] auto[1] auto[1] 1474 1 T3 50 T100 2 T101 16
all_values[1] auto[0] auto[0] auto[0] 1550 1 T3 42 T100 1 T101 21
all_values[1] auto[0] auto[0] auto[1] 813 1 T3 24 T101 14 T144 3
all_values[1] auto[0] auto[1] auto[0] 1464 1 T3 47 T101 18 T144 2
all_values[1] auto[0] auto[1] auto[1] 737 1 T3 12 T100 1 T101 7
all_values[1] auto[1] auto[0] auto[1] 1603 1 T3 33 T100 5 T101 20
all_values[1] auto[1] auto[1] auto[1] 1544 1 T3 41 T101 16 T125 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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