Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
7711 |
1 |
|
|
T3 |
199 |
|
T100 |
7 |
|
T101 |
96 |
all_values[1] |
7711 |
1 |
|
|
T3 |
199 |
|
T100 |
7 |
|
T101 |
96 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8019 |
1 |
|
|
T3 |
202 |
|
T100 |
9 |
|
T101 |
116 |
auto[1] |
7403 |
1 |
|
|
T3 |
196 |
|
T100 |
5 |
|
T101 |
76 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6069 |
1 |
|
|
T3 |
166 |
|
T100 |
1 |
|
T101 |
69 |
auto[1] |
9353 |
1 |
|
|
T3 |
232 |
|
T100 |
13 |
|
T101 |
123 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9156 |
1 |
|
|
T3 |
232 |
|
T100 |
5 |
|
T101 |
113 |
auto[1] |
6266 |
1 |
|
|
T3 |
166 |
|
T100 |
9 |
|
T101 |
79 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
12 |
0 |
12 |
100.00 |
|
Automatically Generated Cross Bins |
12 |
0 |
12 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
1635 |
1 |
|
|
T3 |
46 |
|
T101 |
19 |
|
T125 |
3 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
773 |
1 |
|
|
T3 |
15 |
|
T100 |
1 |
|
T101 |
15 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
1420 |
1 |
|
|
T3 |
31 |
|
T101 |
11 |
|
T143 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
764 |
1 |
|
|
T3 |
15 |
|
T100 |
2 |
|
T101 |
8 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
1645 |
1 |
|
|
T3 |
42 |
|
T100 |
2 |
|
T101 |
27 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
1474 |
1 |
|
|
T3 |
50 |
|
T100 |
2 |
|
T101 |
16 |
all_values[1] |
auto[0] |
auto[0] |
auto[0] |
1550 |
1 |
|
|
T3 |
42 |
|
T100 |
1 |
|
T101 |
21 |
all_values[1] |
auto[0] |
auto[0] |
auto[1] |
813 |
1 |
|
|
T3 |
24 |
|
T101 |
14 |
|
T144 |
3 |
all_values[1] |
auto[0] |
auto[1] |
auto[0] |
1464 |
1 |
|
|
T3 |
47 |
|
T101 |
18 |
|
T144 |
2 |
all_values[1] |
auto[0] |
auto[1] |
auto[1] |
737 |
1 |
|
|
T3 |
12 |
|
T100 |
1 |
|
T101 |
7 |
all_values[1] |
auto[1] |
auto[0] |
auto[1] |
1603 |
1 |
|
|
T3 |
33 |
|
T100 |
5 |
|
T101 |
20 |
all_values[1] |
auto[1] |
auto[1] |
auto[1] |
1544 |
1 |
|
|
T3 |
41 |
|
T101 |
16 |
|
T125 |
1 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |