Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.12 98.24 93.82 97.07 80.92 96.76 99.77 92.28


Total test records in report: 979
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T304 /workspace/coverage/default/26.edn_alert.3668495769 May 12 02:13:22 PM PDT 24 May 12 02:13:24 PM PDT 24 285343305 ps
T798 /workspace/coverage/default/36.edn_alert.3178925905 May 12 02:13:30 PM PDT 24 May 12 02:13:33 PM PDT 24 25351022 ps
T799 /workspace/coverage/default/66.edn_genbits.3528830916 May 12 02:13:54 PM PDT 24 May 12 02:13:56 PM PDT 24 47367597 ps
T800 /workspace/coverage/default/30.edn_stress_all.687034921 May 12 02:13:22 PM PDT 24 May 12 02:13:26 PM PDT 24 189900660 ps
T801 /workspace/coverage/default/46.edn_smoke.83188219 May 12 02:13:40 PM PDT 24 May 12 02:13:41 PM PDT 24 18360034 ps
T802 /workspace/coverage/default/35.edn_err.3386408783 May 12 02:13:29 PM PDT 24 May 12 02:13:32 PM PDT 24 19186636 ps
T803 /workspace/coverage/default/19.edn_alert_test.1700647338 May 12 02:12:57 PM PDT 24 May 12 02:12:59 PM PDT 24 14327434 ps
T804 /workspace/coverage/default/46.edn_err.1407353258 May 12 02:13:39 PM PDT 24 May 12 02:13:41 PM PDT 24 34382849 ps
T805 /workspace/coverage/default/196.edn_genbits.2161070883 May 12 02:14:15 PM PDT 24 May 12 02:14:18 PM PDT 24 38840193 ps
T806 /workspace/coverage/default/2.edn_smoke.3593780203 May 12 02:12:36 PM PDT 24 May 12 02:12:37 PM PDT 24 43155400 ps
T69 /workspace/coverage/default/33.edn_err.2883679138 May 12 02:13:25 PM PDT 24 May 12 02:13:28 PM PDT 24 22683175 ps
T807 /workspace/coverage/default/192.edn_genbits.1897899379 May 12 02:14:17 PM PDT 24 May 12 02:14:19 PM PDT 24 61916645 ps
T808 /workspace/coverage/default/155.edn_genbits.506902164 May 12 02:14:13 PM PDT 24 May 12 02:15:42 PM PDT 24 6613544662 ps
T809 /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3564344858 May 12 02:13:18 PM PDT 24 May 12 02:23:35 PM PDT 24 145888113385 ps
T810 /workspace/coverage/default/148.edn_genbits.2099254981 May 12 02:14:12 PM PDT 24 May 12 02:14:15 PM PDT 24 205339409 ps
T811 /workspace/coverage/default/46.edn_disable.896745425 May 12 02:13:39 PM PDT 24 May 12 02:13:41 PM PDT 24 12751019 ps
T297 /workspace/coverage/default/42.edn_alert.3350477145 May 12 02:13:29 PM PDT 24 May 12 02:13:33 PM PDT 24 168605507 ps
T159 /workspace/coverage/default/48.edn_disable.2787162742 May 12 02:13:46 PM PDT 24 May 12 02:13:47 PM PDT 24 28673112 ps
T812 /workspace/coverage/default/18.edn_disable.598941132 May 12 02:12:57 PM PDT 24 May 12 02:12:59 PM PDT 24 41511054 ps
T813 /workspace/coverage/default/190.edn_genbits.3349084261 May 12 02:14:17 PM PDT 24 May 12 02:14:20 PM PDT 24 38403476 ps
T814 /workspace/coverage/default/27.edn_genbits.410008729 May 12 02:13:18 PM PDT 24 May 12 02:13:21 PM PDT 24 38380043 ps
T815 /workspace/coverage/default/32.edn_alert_test.1168390770 May 12 02:13:21 PM PDT 24 May 12 02:13:23 PM PDT 24 30573399 ps
T816 /workspace/coverage/default/44.edn_err.2433880185 May 12 02:13:33 PM PDT 24 May 12 02:13:36 PM PDT 24 58232758 ps
T817 /workspace/coverage/default/12.edn_alert.1599950422 May 12 02:12:48 PM PDT 24 May 12 02:12:51 PM PDT 24 44435955 ps
T818 /workspace/coverage/default/59.edn_err.4210413698 May 12 02:13:55 PM PDT 24 May 12 02:13:57 PM PDT 24 33028272 ps
T819 /workspace/coverage/default/12.edn_genbits.2427010116 May 12 02:12:50 PM PDT 24 May 12 02:12:54 PM PDT 24 44971798 ps
T820 /workspace/coverage/default/9.edn_genbits.12620934 May 12 02:12:48 PM PDT 24 May 12 02:12:51 PM PDT 24 149333990 ps
T821 /workspace/coverage/default/260.edn_genbits.3694883166 May 12 02:14:34 PM PDT 24 May 12 02:14:37 PM PDT 24 45150145 ps
T822 /workspace/coverage/default/97.edn_err.2125789517 May 12 02:14:02 PM PDT 24 May 12 02:14:04 PM PDT 24 21840928 ps
T823 /workspace/coverage/default/43.edn_intr.2162534651 May 12 02:13:30 PM PDT 24 May 12 02:13:33 PM PDT 24 28888204 ps
T824 /workspace/coverage/default/258.edn_genbits.2173461552 May 12 02:14:30 PM PDT 24 May 12 02:14:32 PM PDT 24 22481425 ps
T825 /workspace/coverage/default/44.edn_stress_all.2087515367 May 12 02:13:34 PM PDT 24 May 12 02:13:38 PM PDT 24 148485303 ps
T160 /workspace/coverage/default/2.edn_disable.2022927770 May 12 02:12:42 PM PDT 24 May 12 02:12:44 PM PDT 24 40255580 ps
T826 /workspace/coverage/default/150.edn_genbits.3295616518 May 12 02:14:07 PM PDT 24 May 12 02:14:09 PM PDT 24 57272490 ps
T827 /workspace/coverage/default/130.edn_genbits.1063314786 May 12 02:14:05 PM PDT 24 May 12 02:14:08 PM PDT 24 47949082 ps
T828 /workspace/coverage/default/272.edn_genbits.1139624631 May 12 02:14:38 PM PDT 24 May 12 02:14:40 PM PDT 24 88464180 ps
T829 /workspace/coverage/default/25.edn_alert.1171596999 May 12 02:13:14 PM PDT 24 May 12 02:13:16 PM PDT 24 28012636 ps
T830 /workspace/coverage/default/30.edn_alert_test.3286783285 May 12 02:13:29 PM PDT 24 May 12 02:13:32 PM PDT 24 16319076 ps
T831 /workspace/coverage/default/87.edn_err.3355072521 May 12 02:14:01 PM PDT 24 May 12 02:14:03 PM PDT 24 55576513 ps
T832 /workspace/coverage/default/40.edn_genbits.1232514245 May 12 02:13:27 PM PDT 24 May 12 02:13:30 PM PDT 24 77754322 ps
T833 /workspace/coverage/default/67.edn_genbits.4229267100 May 12 02:13:53 PM PDT 24 May 12 02:13:55 PM PDT 24 70035304 ps
T834 /workspace/coverage/default/103.edn_genbits.1323393920 May 12 02:14:09 PM PDT 24 May 12 02:14:12 PM PDT 24 95678068 ps
T835 /workspace/coverage/default/27.edn_disable.3786014813 May 12 02:13:16 PM PDT 24 May 12 02:13:18 PM PDT 24 39510547 ps
T836 /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1588801380 May 12 02:13:26 PM PDT 24 May 12 02:18:17 PM PDT 24 16898451780 ps
T837 /workspace/coverage/default/180.edn_genbits.605609609 May 12 02:14:10 PM PDT 24 May 12 02:14:14 PM PDT 24 42543413 ps
T74 /workspace/coverage/default/17.edn_alert.4159029832 May 12 02:12:56 PM PDT 24 May 12 02:12:58 PM PDT 24 130389921 ps
T177 /workspace/coverage/default/11.edn_err.4191577265 May 12 02:12:51 PM PDT 24 May 12 02:12:54 PM PDT 24 32717702 ps
T838 /workspace/coverage/default/15.edn_disable.1440248878 May 12 02:12:56 PM PDT 24 May 12 02:12:58 PM PDT 24 30177623 ps
T839 /workspace/coverage/default/135.edn_genbits.1456791864 May 12 02:14:06 PM PDT 24 May 12 02:14:08 PM PDT 24 77600543 ps
T840 /workspace/coverage/default/2.edn_disable_auto_req_mode.551878430 May 12 02:12:37 PM PDT 24 May 12 02:12:39 PM PDT 24 169527641 ps
T841 /workspace/coverage/default/10.edn_alert.1195022260 May 12 02:12:50 PM PDT 24 May 12 02:12:53 PM PDT 24 33697366 ps
T32 /workspace/coverage/default/28.edn_err.118461554 May 12 02:13:16 PM PDT 24 May 12 02:13:18 PM PDT 24 34900023 ps
T842 /workspace/coverage/default/52.edn_err.1476912200 May 12 02:13:50 PM PDT 24 May 12 02:13:52 PM PDT 24 30677809 ps
T139 /workspace/coverage/default/5.edn_intr.759836801 May 12 02:12:35 PM PDT 24 May 12 02:12:36 PM PDT 24 29194182 ps
T843 /workspace/coverage/default/5.edn_stress_all_with_rand_reset.140748618 May 12 02:12:43 PM PDT 24 May 12 02:18:08 PM PDT 24 77404631159 ps
T844 /workspace/coverage/default/116.edn_genbits.692509407 May 12 02:14:07 PM PDT 24 May 12 02:14:09 PM PDT 24 33639811 ps
T845 /workspace/coverage/default/40.edn_disable.309801360 May 12 02:13:29 PM PDT 24 May 12 02:13:32 PM PDT 24 47538888 ps
T846 /workspace/coverage/default/56.edn_err.1507172709 May 12 02:13:58 PM PDT 24 May 12 02:14:00 PM PDT 24 38798509 ps
T847 /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2001082250 May 12 02:13:37 PM PDT 24 May 12 02:22:35 PM PDT 24 20447620690 ps
T848 /workspace/coverage/default/9.edn_smoke.2947766940 May 12 02:12:45 PM PDT 24 May 12 02:12:47 PM PDT 24 16583869 ps
T239 /workspace/coverage/default/29.edn_alert.880563707 May 12 02:13:18 PM PDT 24 May 12 02:13:20 PM PDT 24 38061057 ps
T240 /workspace/coverage/default/4.edn_alert.1770103876 May 12 02:12:41 PM PDT 24 May 12 02:12:43 PM PDT 24 50905270 ps
T241 /workspace/coverage/default/255.edn_genbits.2761975253 May 12 02:14:30 PM PDT 24 May 12 02:14:33 PM PDT 24 42066243 ps
T242 /workspace/coverage/default/5.edn_disable_auto_req_mode.1241610932 May 12 02:12:42 PM PDT 24 May 12 02:12:45 PM PDT 24 85009461 ps
T849 /workspace/coverage/cover_reg_top/18.edn_intr_test.1696138735 May 12 02:11:08 PM PDT 24 May 12 02:11:10 PM PDT 24 17439372 ps
T850 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3373771214 May 12 02:10:30 PM PDT 24 May 12 02:10:34 PM PDT 24 75388410 ps
T851 /workspace/coverage/cover_reg_top/6.edn_intr_test.3571447897 May 12 02:10:28 PM PDT 24 May 12 02:10:30 PM PDT 24 12116648 ps
T231 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1998706431 May 12 02:11:08 PM PDT 24 May 12 02:11:10 PM PDT 24 20660380 ps
T852 /workspace/coverage/cover_reg_top/47.edn_intr_test.1490196155 May 12 02:11:11 PM PDT 24 May 12 02:11:14 PM PDT 24 36574983 ps
T853 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2119745420 May 12 02:10:26 PM PDT 24 May 12 02:10:30 PM PDT 24 88065536 ps
T854 /workspace/coverage/cover_reg_top/25.edn_intr_test.2179681451 May 12 02:11:12 PM PDT 24 May 12 02:11:15 PM PDT 24 17491095 ps
T855 /workspace/coverage/cover_reg_top/48.edn_intr_test.3047604643 May 12 02:11:11 PM PDT 24 May 12 02:11:14 PM PDT 24 15116612 ps
T217 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2917787314 May 12 02:10:29 PM PDT 24 May 12 02:10:32 PM PDT 24 66494610 ps
T218 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2760784452 May 12 02:10:26 PM PDT 24 May 12 02:10:28 PM PDT 24 58878836 ps
T856 /workspace/coverage/cover_reg_top/33.edn_intr_test.1375041078 May 12 02:11:09 PM PDT 24 May 12 02:11:12 PM PDT 24 44345220 ps
T857 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3022192332 May 12 02:11:10 PM PDT 24 May 12 02:11:13 PM PDT 24 27472435 ps
T858 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.4252714655 May 12 02:11:13 PM PDT 24 May 12 02:11:16 PM PDT 24 24189732 ps
T232 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1949617782 May 12 02:10:41 PM PDT 24 May 12 02:10:43 PM PDT 24 21290828 ps
T859 /workspace/coverage/cover_reg_top/4.edn_intr_test.899765215 May 12 02:10:40 PM PDT 24 May 12 02:10:42 PM PDT 24 46571945 ps
T233 /workspace/coverage/cover_reg_top/0.edn_csr_rw.501726455 May 12 02:10:24 PM PDT 24 May 12 02:10:26 PM PDT 24 14888733 ps
T245 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.4237055773 May 12 02:10:30 PM PDT 24 May 12 02:10:34 PM PDT 24 95995974 ps
T860 /workspace/coverage/cover_reg_top/15.edn_intr_test.3060952568 May 12 02:11:08 PM PDT 24 May 12 02:11:10 PM PDT 24 85704537 ps
T243 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3075792739 May 12 02:10:36 PM PDT 24 May 12 02:10:37 PM PDT 24 14334400 ps
T234 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2264962749 May 12 02:10:39 PM PDT 24 May 12 02:10:41 PM PDT 24 15427536 ps
T219 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2801719105 May 12 02:10:30 PM PDT 24 May 12 02:10:33 PM PDT 24 82828485 ps
T246 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1731518964 May 12 02:10:34 PM PDT 24 May 12 02:10:36 PM PDT 24 80737908 ps
T861 /workspace/coverage/cover_reg_top/35.edn_intr_test.542942126 May 12 02:11:07 PM PDT 24 May 12 02:11:09 PM PDT 24 14173750 ps
T862 /workspace/coverage/cover_reg_top/41.edn_intr_test.232285935 May 12 02:11:15 PM PDT 24 May 12 02:11:19 PM PDT 24 18566706 ps
T244 /workspace/coverage/cover_reg_top/3.edn_csr_rw.160181292 May 12 02:10:25 PM PDT 24 May 12 02:10:27 PM PDT 24 19252927 ps
T863 /workspace/coverage/cover_reg_top/49.edn_intr_test.2303044436 May 12 02:11:14 PM PDT 24 May 12 02:11:18 PM PDT 24 31322956 ps
T247 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2797714835 May 12 02:11:07 PM PDT 24 May 12 02:11:10 PM PDT 24 294996198 ps
T864 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.117299886 May 12 02:10:36 PM PDT 24 May 12 02:10:38 PM PDT 24 19140568 ps
T865 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1589857938 May 12 02:11:09 PM PDT 24 May 12 02:11:12 PM PDT 24 45699695 ps
T866 /workspace/coverage/cover_reg_top/34.edn_intr_test.1855499253 May 12 02:11:08 PM PDT 24 May 12 02:11:11 PM PDT 24 22421293 ps
T867 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2764095212 May 12 02:11:06 PM PDT 24 May 12 02:11:10 PM PDT 24 344395490 ps
T868 /workspace/coverage/cover_reg_top/5.edn_intr_test.214332509 May 12 02:10:28 PM PDT 24 May 12 02:10:30 PM PDT 24 14902891 ps
T869 /workspace/coverage/cover_reg_top/7.edn_csr_rw.190597846 May 12 02:10:40 PM PDT 24 May 12 02:10:42 PM PDT 24 90426467 ps
T870 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1923374425 May 12 02:10:35 PM PDT 24 May 12 02:10:38 PM PDT 24 93402733 ps
T871 /workspace/coverage/cover_reg_top/19.edn_intr_test.2587700077 May 12 02:11:08 PM PDT 24 May 12 02:11:10 PM PDT 24 15571227 ps
T872 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2403229993 May 12 02:10:44 PM PDT 24 May 12 02:10:46 PM PDT 24 33761203 ps
T235 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.927202918 May 12 02:10:37 PM PDT 24 May 12 02:10:39 PM PDT 24 21338920 ps
T220 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3766008267 May 12 02:10:27 PM PDT 24 May 12 02:10:29 PM PDT 24 86942066 ps
T873 /workspace/coverage/cover_reg_top/38.edn_intr_test.469483708 May 12 02:11:12 PM PDT 24 May 12 02:11:15 PM PDT 24 62226535 ps
T236 /workspace/coverage/cover_reg_top/16.edn_csr_rw.939220720 May 12 02:11:12 PM PDT 24 May 12 02:11:15 PM PDT 24 28400333 ps
T237 /workspace/coverage/cover_reg_top/19.edn_csr_rw.287196955 May 12 02:11:07 PM PDT 24 May 12 02:11:10 PM PDT 24 15858808 ps
T874 /workspace/coverage/cover_reg_top/46.edn_intr_test.2739550031 May 12 02:11:12 PM PDT 24 May 12 02:11:15 PM PDT 24 33812707 ps
T221 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3602782678 May 12 02:10:29 PM PDT 24 May 12 02:10:32 PM PDT 24 69592989 ps
T875 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3127257508 May 12 02:10:23 PM PDT 24 May 12 02:10:26 PM PDT 24 107724574 ps
T876 /workspace/coverage/cover_reg_top/4.edn_tl_errors.882105693 May 12 02:10:25 PM PDT 24 May 12 02:10:28 PM PDT 24 113934378 ps
T877 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1189444027 May 12 02:10:42 PM PDT 24 May 12 02:10:43 PM PDT 24 14796632 ps
T878 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2251151924 May 12 02:10:24 PM PDT 24 May 12 02:10:30 PM PDT 24 719169406 ps
T879 /workspace/coverage/cover_reg_top/1.edn_csr_rw.1192759467 May 12 02:10:30 PM PDT 24 May 12 02:10:32 PM PDT 24 42211370 ps
T263 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.907488270 May 12 02:10:30 PM PDT 24 May 12 02:10:34 PM PDT 24 726412430 ps
T222 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2205628700 May 12 02:10:24 PM PDT 24 May 12 02:10:27 PM PDT 24 28902849 ps
T880 /workspace/coverage/cover_reg_top/21.edn_intr_test.4155191851 May 12 02:11:12 PM PDT 24 May 12 02:11:15 PM PDT 24 49983719 ps
T223 /workspace/coverage/cover_reg_top/5.edn_csr_rw.48416947 May 12 02:10:40 PM PDT 24 May 12 02:10:42 PM PDT 24 16464575 ps
T881 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2733254348 May 12 02:10:27 PM PDT 24 May 12 02:10:29 PM PDT 24 100648496 ps
T882 /workspace/coverage/cover_reg_top/43.edn_intr_test.2765658978 May 12 02:11:12 PM PDT 24 May 12 02:11:15 PM PDT 24 13543767 ps
T883 /workspace/coverage/cover_reg_top/39.edn_intr_test.498280012 May 12 02:11:13 PM PDT 24 May 12 02:11:16 PM PDT 24 15882033 ps
T260 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1722723400 May 12 02:11:07 PM PDT 24 May 12 02:11:10 PM PDT 24 56788436 ps
T884 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1293098383 May 12 02:10:37 PM PDT 24 May 12 02:10:41 PM PDT 24 51711507 ps
T885 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2147279698 May 12 02:11:08 PM PDT 24 May 12 02:11:13 PM PDT 24 127796066 ps
T224 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3144118117 May 12 02:10:30 PM PDT 24 May 12 02:10:33 PM PDT 24 58816586 ps
T225 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1001766919 May 12 02:10:28 PM PDT 24 May 12 02:10:30 PM PDT 24 96236518 ps
T886 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2699281221 May 12 02:10:24 PM PDT 24 May 12 02:10:26 PM PDT 24 211340546 ps
T887 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3753541965 May 12 02:10:39 PM PDT 24 May 12 02:10:41 PM PDT 24 34718263 ps
T226 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.615017801 May 12 02:10:37 PM PDT 24 May 12 02:10:39 PM PDT 24 29324187 ps
T888 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.130641491 May 12 02:10:30 PM PDT 24 May 12 02:10:33 PM PDT 24 48852471 ps
T889 /workspace/coverage/cover_reg_top/32.edn_intr_test.2543315889 May 12 02:11:13 PM PDT 24 May 12 02:11:16 PM PDT 24 24935354 ps
T258 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3442659093 May 12 02:10:39 PM PDT 24 May 12 02:10:42 PM PDT 24 153583692 ps
T890 /workspace/coverage/cover_reg_top/20.edn_intr_test.1857415043 May 12 02:11:10 PM PDT 24 May 12 02:11:13 PM PDT 24 34736698 ps
T238 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3521271301 May 12 02:10:23 PM PDT 24 May 12 02:10:25 PM PDT 24 42818021 ps
T891 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1851671678 May 12 02:11:08 PM PDT 24 May 12 02:11:12 PM PDT 24 126046466 ps
T892 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1246252856 May 12 02:10:25 PM PDT 24 May 12 02:10:28 PM PDT 24 47930103 ps
T893 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3461734506 May 12 02:10:39 PM PDT 24 May 12 02:10:41 PM PDT 24 90184370 ps
T227 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1729338155 May 12 02:10:30 PM PDT 24 May 12 02:10:33 PM PDT 24 12934092 ps
T894 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3099916180 May 12 02:10:30 PM PDT 24 May 12 02:10:35 PM PDT 24 65594439 ps
T895 /workspace/coverage/cover_reg_top/9.edn_intr_test.578693294 May 12 02:10:37 PM PDT 24 May 12 02:10:39 PM PDT 24 215488748 ps
T896 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4201716667 May 12 02:10:29 PM PDT 24 May 12 02:10:32 PM PDT 24 52425904 ps
T897 /workspace/coverage/cover_reg_top/16.edn_tl_errors.971369590 May 12 02:11:06 PM PDT 24 May 12 02:11:09 PM PDT 24 216731833 ps
T898 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2677544855 May 12 02:10:38 PM PDT 24 May 12 02:10:41 PM PDT 24 31274464 ps
T264 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1134764038 May 12 02:10:40 PM PDT 24 May 12 02:10:43 PM PDT 24 55227781 ps
T899 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2521084983 May 12 02:10:32 PM PDT 24 May 12 02:10:34 PM PDT 24 21638688 ps
T259 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1069863540 May 12 02:10:37 PM PDT 24 May 12 02:10:40 PM PDT 24 151317934 ps
T900 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2199470904 May 12 02:10:28 PM PDT 24 May 12 02:10:30 PM PDT 24 49723869 ps
T230 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.310957294 May 12 02:10:22 PM PDT 24 May 12 02:10:28 PM PDT 24 614792652 ps
T901 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.891964756 May 12 02:10:27 PM PDT 24 May 12 02:10:32 PM PDT 24 122040455 ps
T902 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1248286911 May 12 02:11:09 PM PDT 24 May 12 02:11:13 PM PDT 24 20116189 ps
T903 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3610345290 May 12 02:10:29 PM PDT 24 May 12 02:10:32 PM PDT 24 61532098 ps
T904 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.711375739 May 12 02:11:09 PM PDT 24 May 12 02:11:13 PM PDT 24 24784285 ps
T905 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3567104424 May 12 02:10:23 PM PDT 24 May 12 02:10:25 PM PDT 24 14489706 ps
T906 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3706666255 May 12 02:11:07 PM PDT 24 May 12 02:11:10 PM PDT 24 57724393 ps
T907 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1434366376 May 12 02:11:12 PM PDT 24 May 12 02:11:16 PM PDT 24 163994459 ps
T908 /workspace/coverage/cover_reg_top/45.edn_intr_test.102902060 May 12 02:11:11 PM PDT 24 May 12 02:11:14 PM PDT 24 19830122 ps
T909 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1705777375 May 12 02:10:29 PM PDT 24 May 12 02:10:31 PM PDT 24 26641103 ps
T910 /workspace/coverage/cover_reg_top/28.edn_intr_test.1568908000 May 12 02:11:10 PM PDT 24 May 12 02:11:13 PM PDT 24 29094444 ps
T911 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1198475162 May 12 02:11:08 PM PDT 24 May 12 02:11:11 PM PDT 24 32562868 ps
T912 /workspace/coverage/cover_reg_top/24.edn_intr_test.4112374213 May 12 02:11:09 PM PDT 24 May 12 02:11:11 PM PDT 24 30870853 ps
T913 /workspace/coverage/cover_reg_top/27.edn_intr_test.2772338893 May 12 02:11:08 PM PDT 24 May 12 02:11:11 PM PDT 24 22074954 ps
T914 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1246455726 May 12 02:10:38 PM PDT 24 May 12 02:10:41 PM PDT 24 265631007 ps
T915 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4133353195 May 12 02:10:30 PM PDT 24 May 12 02:10:35 PM PDT 24 178435685 ps
T916 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.494421278 May 12 02:11:08 PM PDT 24 May 12 02:11:10 PM PDT 24 31995153 ps
T917 /workspace/coverage/cover_reg_top/29.edn_intr_test.983582401 May 12 02:11:14 PM PDT 24 May 12 02:11:17 PM PDT 24 50849999 ps
T918 /workspace/coverage/cover_reg_top/26.edn_intr_test.2148466428 May 12 02:11:12 PM PDT 24 May 12 02:11:15 PM PDT 24 37121136 ps
T919 /workspace/coverage/cover_reg_top/7.edn_intr_test.249471822 May 12 02:10:35 PM PDT 24 May 12 02:10:37 PM PDT 24 25608542 ps
T920 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1430706283 May 12 02:10:40 PM PDT 24 May 12 02:10:45 PM PDT 24 118803289 ps
T921 /workspace/coverage/cover_reg_top/17.edn_tl_errors.736807053 May 12 02:11:07 PM PDT 24 May 12 02:11:13 PM PDT 24 1879969653 ps
T922 /workspace/coverage/cover_reg_top/30.edn_intr_test.4190949738 May 12 02:11:11 PM PDT 24 May 12 02:11:14 PM PDT 24 12417598 ps
T923 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2399205794 May 12 02:10:40 PM PDT 24 May 12 02:10:43 PM PDT 24 171805013 ps
T924 /workspace/coverage/cover_reg_top/37.edn_intr_test.2853738820 May 12 02:11:11 PM PDT 24 May 12 02:11:14 PM PDT 24 90212547 ps
T925 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2247041253 May 12 02:11:09 PM PDT 24 May 12 02:11:12 PM PDT 24 35991220 ps
T926 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1948008120 May 12 02:11:07 PM PDT 24 May 12 02:11:09 PM PDT 24 40421102 ps
T927 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1643294473 May 12 02:10:31 PM PDT 24 May 12 02:10:34 PM PDT 24 57858379 ps
T928 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2099874230 May 12 02:10:30 PM PDT 24 May 12 02:10:33 PM PDT 24 253992279 ps
T929 /workspace/coverage/cover_reg_top/3.edn_intr_test.701520694 May 12 02:10:34 PM PDT 24 May 12 02:10:35 PM PDT 24 16933299 ps
T930 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3045087630 May 12 02:10:35 PM PDT 24 May 12 02:10:36 PM PDT 24 32740426 ps
T931 /workspace/coverage/cover_reg_top/31.edn_intr_test.1889318572 May 12 02:11:14 PM PDT 24 May 12 02:11:18 PM PDT 24 51908665 ps
T932 /workspace/coverage/cover_reg_top/19.edn_tl_errors.265372242 May 12 02:11:14 PM PDT 24 May 12 02:11:20 PM PDT 24 90745512 ps
T933 /workspace/coverage/cover_reg_top/40.edn_intr_test.4011855124 May 12 02:11:11 PM PDT 24 May 12 02:11:14 PM PDT 24 50145297 ps
T934 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3381348761 May 12 02:11:08 PM PDT 24 May 12 02:11:11 PM PDT 24 28818364 ps
T935 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3499627552 May 12 02:10:34 PM PDT 24 May 12 02:10:36 PM PDT 24 36938113 ps
T936 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1475294477 May 12 02:10:40 PM PDT 24 May 12 02:10:43 PM PDT 24 91882374 ps
T937 /workspace/coverage/cover_reg_top/13.edn_tl_errors.4240464030 May 12 02:11:10 PM PDT 24 May 12 02:11:16 PM PDT 24 192535745 ps
T938 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3290883563 May 12 02:11:07 PM PDT 24 May 12 02:11:09 PM PDT 24 18083912 ps
T261 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.460612928 May 12 02:10:40 PM PDT 24 May 12 02:10:44 PM PDT 24 332871771 ps
T939 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3049023493 May 12 02:10:40 PM PDT 24 May 12 02:10:43 PM PDT 24 161495496 ps
T940 /workspace/coverage/cover_reg_top/2.edn_intr_test.2702134476 May 12 02:10:25 PM PDT 24 May 12 02:10:27 PM PDT 24 40831681 ps
T941 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3157548355 May 12 02:10:40 PM PDT 24 May 12 02:10:46 PM PDT 24 130139055 ps
T262 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.944073154 May 12 02:11:09 PM PDT 24 May 12 02:11:13 PM PDT 24 85784991 ps
T942 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2441145074 May 12 02:11:08 PM PDT 24 May 12 02:11:10 PM PDT 24 37917132 ps
T943 /workspace/coverage/cover_reg_top/23.edn_intr_test.3904452957 May 12 02:11:09 PM PDT 24 May 12 02:11:12 PM PDT 24 29971460 ps
T944 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.737945797 May 12 02:11:06 PM PDT 24 May 12 02:11:08 PM PDT 24 26131634 ps
T945 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.4063727041 May 12 02:11:01 PM PDT 24 May 12 02:11:02 PM PDT 24 14798254 ps
T946 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1164768015 May 12 02:10:29 PM PDT 24 May 12 02:10:31 PM PDT 24 24906293 ps
T947 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1402023550 May 12 02:10:37 PM PDT 24 May 12 02:10:39 PM PDT 24 41828792 ps
T948 /workspace/coverage/cover_reg_top/13.edn_intr_test.3727141068 May 12 02:11:09 PM PDT 24 May 12 02:11:12 PM PDT 24 52901372 ps
T949 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2134104705 May 12 02:10:30 PM PDT 24 May 12 02:10:33 PM PDT 24 42535489 ps
T950 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3317664711 May 12 02:10:29 PM PDT 24 May 12 02:10:36 PM PDT 24 232161392 ps
T951 /workspace/coverage/cover_reg_top/36.edn_intr_test.1285765983 May 12 02:11:12 PM PDT 24 May 12 02:11:15 PM PDT 24 64043743 ps
T952 /workspace/coverage/cover_reg_top/16.edn_intr_test.3767316506 May 12 02:11:09 PM PDT 24 May 12 02:11:12 PM PDT 24 19765026 ps
T953 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3943326528 May 12 02:10:26 PM PDT 24 May 12 02:10:29 PM PDT 24 44829330 ps
T954 /workspace/coverage/cover_reg_top/12.edn_intr_test.2975467518 May 12 02:10:40 PM PDT 24 May 12 02:10:42 PM PDT 24 25940529 ps
T955 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1485630928 May 12 02:10:43 PM PDT 24 May 12 02:10:46 PM PDT 24 190726471 ps
T956 /workspace/coverage/cover_reg_top/14.edn_intr_test.428626589 May 12 02:11:07 PM PDT 24 May 12 02:11:09 PM PDT 24 44532346 ps
T957 /workspace/coverage/cover_reg_top/18.edn_csr_rw.3265153906 May 12 02:11:08 PM PDT 24 May 12 02:11:10 PM PDT 24 23764935 ps
T958 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2993337330 May 12 02:11:08 PM PDT 24 May 12 02:11:12 PM PDT 24 81811028 ps
T959 /workspace/coverage/cover_reg_top/8.edn_intr_test.1409414646 May 12 02:10:38 PM PDT 24 May 12 02:10:39 PM PDT 24 36111632 ps
T960 /workspace/coverage/cover_reg_top/11.edn_intr_test.1913355722 May 12 02:10:39 PM PDT 24 May 12 02:10:41 PM PDT 24 41521809 ps
T961 /workspace/coverage/cover_reg_top/12.edn_csr_rw.22622097 May 12 02:11:06 PM PDT 24 May 12 02:11:08 PM PDT 24 34958477 ps
T962 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2677030911 May 12 02:10:44 PM PDT 24 May 12 02:10:45 PM PDT 24 54938960 ps
T963 /workspace/coverage/cover_reg_top/2.edn_tl_errors.4060982096 May 12 02:10:27 PM PDT 24 May 12 02:10:31 PM PDT 24 81696916 ps
T964 /workspace/coverage/cover_reg_top/11.edn_csr_rw.987213951 May 12 02:10:37 PM PDT 24 May 12 02:10:38 PM PDT 24 15424565 ps
T965 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1662718884 May 12 02:11:10 PM PDT 24 May 12 02:11:14 PM PDT 24 298249002 ps
T966 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1397581295 May 12 02:11:06 PM PDT 24 May 12 02:11:09 PM PDT 24 93591308 ps
T967 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3287337502 May 12 02:10:29 PM PDT 24 May 12 02:10:32 PM PDT 24 21509486 ps
T968 /workspace/coverage/cover_reg_top/42.edn_intr_test.183232691 May 12 02:11:11 PM PDT 24 May 12 02:11:13 PM PDT 24 96684593 ps
T969 /workspace/coverage/cover_reg_top/17.edn_intr_test.853595836 May 12 02:10:48 PM PDT 24 May 12 02:10:50 PM PDT 24 52685389 ps
T970 /workspace/coverage/cover_reg_top/10.edn_intr_test.1762077056 May 12 02:10:37 PM PDT 24 May 12 02:10:39 PM PDT 24 48097833 ps
T228 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3033521364 May 12 02:11:06 PM PDT 24 May 12 02:11:08 PM PDT 24 11810222 ps
T971 /workspace/coverage/cover_reg_top/44.edn_intr_test.3569112382 May 12 02:11:11 PM PDT 24 May 12 02:11:14 PM PDT 24 37698128 ps
T972 /workspace/coverage/cover_reg_top/22.edn_intr_test.4114892696 May 12 02:11:14 PM PDT 24 May 12 02:11:17 PM PDT 24 21578735 ps
T973 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3061388765 May 12 02:10:40 PM PDT 24 May 12 02:10:42 PM PDT 24 34521570 ps
T974 /workspace/coverage/cover_reg_top/1.edn_intr_test.3119799547 May 12 02:10:23 PM PDT 24 May 12 02:10:25 PM PDT 24 15078427 ps
T975 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.837235614 May 12 02:10:24 PM PDT 24 May 12 02:10:28 PM PDT 24 344061102 ps
T976 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1055663714 May 12 02:10:29 PM PDT 24 May 12 02:10:32 PM PDT 24 117306803 ps
T977 /workspace/coverage/cover_reg_top/0.edn_intr_test.1465428660 May 12 02:10:21 PM PDT 24 May 12 02:10:22 PM PDT 24 15580097 ps
T978 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2746306108 May 12 02:11:09 PM PDT 24 May 12 02:11:13 PM PDT 24 118545652 ps
T979 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3367351427 May 12 02:11:13 PM PDT 24 May 12 02:11:17 PM PDT 24 72209736 ps
T229 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2096939346 May 12 02:11:10 PM PDT 24 May 12 02:11:13 PM PDT 24 12381903 ps

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1732746931
Short name T3
Test name
Test status
Simulation time 179845407903 ps
CPU time 2355.54 seconds
Started May 12 02:13:40 PM PDT 24
Finished May 12 02:52:57 PM PDT 24
Peak memory 230680 kb
Host smart-dff7b022-89f4-4bb6-a5e3-6951d255ca77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732746931 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1732746931
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/156.edn_genbits.2741527923
Short name T113
Test name
Test status
Simulation time 290513791 ps
CPU time 2.77 seconds
Started May 12 02:14:14 PM PDT 24
Finished May 12 02:14:17 PM PDT 24
Peak memory 219356 kb
Host smart-bc636ac8-3af9-48a1-b8cf-ba79b744fe74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741527923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2741527923
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2811209360
Short name T5
Test name
Test status
Simulation time 1115561230 ps
CPU time 7.54 seconds
Started May 12 02:12:37 PM PDT 24
Finished May 12 02:12:45 PM PDT 24
Peak memory 235976 kb
Host smart-b23c75a6-c369-4cea-90e5-e2c67ef35901
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811209360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2811209360
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_alert.1832837222
Short name T9
Test name
Test status
Simulation time 30072832 ps
CPU time 1.26 seconds
Started May 12 02:12:37 PM PDT 24
Finished May 12 02:12:39 PM PDT 24
Peak memory 215668 kb
Host smart-91db8806-7018-4b2d-ab5c-08a6b6dba057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832837222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1832837222
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/227.edn_genbits.3974382261
Short name T22
Test name
Test status
Simulation time 33993884 ps
CPU time 1.57 seconds
Started May 12 02:14:21 PM PDT 24
Finished May 12 02:14:23 PM PDT 24
Peak memory 218128 kb
Host smart-d5f46c7f-5961-46bc-a475-9f74e18e3fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974382261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3974382261
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.3825692239
Short name T99
Test name
Test status
Simulation time 22853244 ps
CPU time 1.07 seconds
Started May 12 02:13:59 PM PDT 24
Finished May 12 02:14:01 PM PDT 24
Peak memory 223844 kb
Host smart-ea63c177-f531-4d1d-9861-b8770cb3284b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825692239 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3825692239
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/13.edn_disable.784020654
Short name T92
Test name
Test status
Simulation time 41306326 ps
CPU time 0.86 seconds
Started May 12 02:12:51 PM PDT 24
Finished May 12 02:12:54 PM PDT 24
Peak memory 215944 kb
Host smart-41411e0c-21ed-4647-ad33-2bc959e6fc86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784020654 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.784020654
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2600249653
Short name T28
Test name
Test status
Simulation time 58377885 ps
CPU time 1.23 seconds
Started May 12 02:12:49 PM PDT 24
Finished May 12 02:12:53 PM PDT 24
Peak memory 216736 kb
Host smart-fe52f396-4e17-40ef-8122-fb7c32f6ef16
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600249653 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2600249653
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_alert.1259508425
Short name T72
Test name
Test status
Simulation time 72056854 ps
CPU time 1.09 seconds
Started May 12 02:12:42 PM PDT 24
Finished May 12 02:12:44 PM PDT 24
Peak memory 215448 kb
Host smart-1a10c811-e0d9-4b06-afda-7adac8a8b284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259508425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1259508425
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert.289122389
Short name T29
Test name
Test status
Simulation time 48321676 ps
CPU time 1.21 seconds
Started May 12 02:12:56 PM PDT 24
Finished May 12 02:12:58 PM PDT 24
Peak memory 215476 kb
Host smart-2adce4d8-9592-4d4a-a693-ef9fe196bee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289122389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.289122389
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/4.edn_regwen.3320436370
Short name T104
Test name
Test status
Simulation time 31112341 ps
CPU time 1.02 seconds
Started May 12 02:12:41 PM PDT 24
Finished May 12 02:12:43 PM PDT 24
Peak memory 206936 kb
Host smart-21487193-a101-497c-9f2d-91bd133e8bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320436370 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3320436370
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.182549973
Short name T33
Test name
Test status
Simulation time 25098855 ps
CPU time 1.14 seconds
Started May 12 02:12:52 PM PDT 24
Finished May 12 02:12:54 PM PDT 24
Peak memory 216892 kb
Host smart-3e1c4d09-8f47-4449-b645-d7823718cbff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182549973 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.182549973
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2823402212
Short name T187
Test name
Test status
Simulation time 119906636781 ps
CPU time 1475.59 seconds
Started May 12 02:13:32 PM PDT 24
Finished May 12 02:38:09 PM PDT 24
Peak memory 225864 kb
Host smart-94019ca2-f92c-4af9-a125-6fa125f3d201
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823402212 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2823402212
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2760784452
Short name T218
Test name
Test status
Simulation time 58878836 ps
CPU time 1.27 seconds
Started May 12 02:10:26 PM PDT 24
Finished May 12 02:10:28 PM PDT 24
Peak memory 206276 kb
Host smart-6a71ca72-2a59-4a37-ab76-83cc49d9ea18
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760784452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2760784452
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3442659093
Short name T258
Test name
Test status
Simulation time 153583692 ps
CPU time 2.42 seconds
Started May 12 02:10:39 PM PDT 24
Finished May 12 02:10:42 PM PDT 24
Peak memory 214452 kb
Host smart-1d931e45-d6c4-4400-9978-1107cd032994
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442659093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3442659093
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/18.edn_alert.3970020586
Short name T713
Test name
Test status
Simulation time 75809037 ps
CPU time 1.13 seconds
Started May 12 02:12:54 PM PDT 24
Finished May 12 02:12:56 PM PDT 24
Peak memory 215484 kb
Host smart-3685e2ed-24fd-4852-94b7-fe4d504b722c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970020586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3970020586
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.4023382976
Short name T193
Test name
Test status
Simulation time 129316281808 ps
CPU time 1450.33 seconds
Started May 12 02:12:47 PM PDT 24
Finished May 12 02:37:00 PM PDT 24
Peak memory 223704 kb
Host smart-e9b97d66-e0ea-4114-8d3f-207c2355eeb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023382976 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.4023382976
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_disable.1945857040
Short name T94
Test name
Test status
Simulation time 60424603 ps
CPU time 0.88 seconds
Started May 12 02:13:29 PM PDT 24
Finished May 12 02:13:31 PM PDT 24
Peak memory 216156 kb
Host smart-69a6d9e0-04fa-4dfd-9161-9d6f2a3b1338
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945857040 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1945857040
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable.632045685
Short name T85
Test name
Test status
Simulation time 14859663 ps
CPU time 0.95 seconds
Started May 12 02:12:51 PM PDT 24
Finished May 12 02:12:53 PM PDT 24
Peak memory 216268 kb
Host smart-62fc86da-f1ef-4c66-937c-6203db8d27a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632045685 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.632045685
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable.3636492560
Short name T165
Test name
Test status
Simulation time 12508534 ps
CPU time 0.89 seconds
Started May 12 02:13:27 PM PDT 24
Finished May 12 02:13:29 PM PDT 24
Peak memory 216348 kb
Host smart-a729e7a0-9711-41ea-8c27-f2065d6844ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636492560 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3636492560
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable.1689147677
Short name T24
Test name
Test status
Simulation time 13091771 ps
CPU time 0.91 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 215388 kb
Host smart-8f7769ad-76ee-4b76-b6fc-70f500d46e04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689147677 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1689147677
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/27.edn_intr.2663099219
Short name T106
Test name
Test status
Simulation time 26892394 ps
CPU time 0.93 seconds
Started May 12 02:13:16 PM PDT 24
Finished May 12 02:13:17 PM PDT 24
Peak memory 215660 kb
Host smart-667229aa-6a33-4bd1-b22d-067b3d6e7271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663099219 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2663099219
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/14.edn_alert.2941353432
Short name T250
Test name
Test status
Simulation time 29567413 ps
CPU time 1.35 seconds
Started May 12 02:12:52 PM PDT 24
Finished May 12 02:12:55 PM PDT 24
Peak memory 215504 kb
Host smart-50d34aa7-6774-46f0-9f98-1e0637c79b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941353432 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2941353432
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/18.edn_genbits.1817047675
Short name T257
Test name
Test status
Simulation time 18788463 ps
CPU time 1.08 seconds
Started May 12 02:12:54 PM PDT 24
Finished May 12 02:12:56 PM PDT 24
Peak memory 217040 kb
Host smart-742aa90a-7102-42e6-93e6-937fda9b0dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817047675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1817047675
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.1290485223
Short name T25
Test name
Test status
Simulation time 44658659 ps
CPU time 1.09 seconds
Started May 12 02:13:58 PM PDT 24
Finished May 12 02:14:00 PM PDT 24
Peak memory 215620 kb
Host smart-501774aa-b56f-4c17-afde-3d6aa020b33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290485223 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1290485223
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1288056817
Short name T62
Test name
Test status
Simulation time 45103818 ps
CPU time 1.16 seconds
Started May 12 02:12:59 PM PDT 24
Finished May 12 02:13:01 PM PDT 24
Peak memory 216780 kb
Host smart-e488b8a7-e208-4f87-b2e2-02b9e6e70555
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288056817 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1288056817
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/131.edn_genbits.3195603966
Short name T370
Test name
Test status
Simulation time 26420588 ps
CPU time 1.21 seconds
Started May 12 02:14:09 PM PDT 24
Finished May 12 02:14:12 PM PDT 24
Peak memory 217080 kb
Host smart-f9607a56-d546-490f-a374-6f11232a2d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195603966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3195603966
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2700148842
Short name T147
Test name
Test status
Simulation time 59110712 ps
CPU time 1.45 seconds
Started May 12 02:14:36 PM PDT 24
Finished May 12 02:14:38 PM PDT 24
Peak memory 218344 kb
Host smart-eea61762-6755-4fb3-af54-52d565b2c020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700148842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2700148842
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_regwen.817330295
Short name T294
Test name
Test status
Simulation time 40245376 ps
CPU time 0.91 seconds
Started May 12 02:12:43 PM PDT 24
Finished May 12 02:12:45 PM PDT 24
Peak memory 206928 kb
Host smart-0315d0e7-bace-48f5-af3c-bdbaafe82b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817330295 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.817330295
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_disable.2022927770
Short name T160
Test name
Test status
Simulation time 40255580 ps
CPU time 0.87 seconds
Started May 12 02:12:42 PM PDT 24
Finished May 12 02:12:44 PM PDT 24
Peak memory 216080 kb
Host smart-719b4a7f-6e85-4461-8318-0da03ab3cad5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022927770 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2022927770
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/14.edn_intr.4243071023
Short name T108
Test name
Test status
Simulation time 19952508 ps
CPU time 1.1 seconds
Started May 12 02:12:53 PM PDT 24
Finished May 12 02:12:55 PM PDT 24
Peak memory 215632 kb
Host smart-f2cf91c4-d443-42c9-94af-b5490ef0760f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243071023 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.4243071023
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2668035452
Short name T49
Test name
Test status
Simulation time 45591029 ps
CPU time 1 seconds
Started May 12 02:12:37 PM PDT 24
Finished May 12 02:12:38 PM PDT 24
Peak memory 219240 kb
Host smart-d9cdff0e-1935-4d74-ad47-b582c6473ecd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668035452 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2668035452
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3495690999
Short name T173
Test name
Test status
Simulation time 47239614 ps
CPU time 1.14 seconds
Started May 12 02:12:45 PM PDT 24
Finished May 12 02:12:47 PM PDT 24
Peak memory 216568 kb
Host smart-49ab8168-5ef4-4330-9bfe-7c0724587732
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495690999 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3495690999
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.79797858
Short name T41
Test name
Test status
Simulation time 378311596 ps
CPU time 1.23 seconds
Started May 12 02:12:46 PM PDT 24
Finished May 12 02:12:48 PM PDT 24
Peak memory 216524 kb
Host smart-cd94c497-acea-4e20-8ea7-ab20f5abd148
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79797858 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_dis
able_auto_req_mode.79797858
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.4132639060
Short name T170
Test name
Test status
Simulation time 137362465 ps
CPU time 1.3 seconds
Started May 12 02:13:28 PM PDT 24
Finished May 12 02:13:31 PM PDT 24
Peak memory 216548 kb
Host smart-4d3274ff-3fb4-4c4e-bfdf-533a2060c6f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132639060 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.4132639060
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_disable.2907127594
Short name T96
Test name
Test status
Simulation time 12245422 ps
CPU time 0.95 seconds
Started May 12 02:13:40 PM PDT 24
Finished May 12 02:13:42 PM PDT 24
Peak memory 216052 kb
Host smart-a916f64f-3c75-4b6a-bbce-5dcf34df4f66
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907127594 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2907127594
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/245.edn_genbits.3243263159
Short name T445
Test name
Test status
Simulation time 61756659 ps
CPU time 1.42 seconds
Started May 12 02:14:29 PM PDT 24
Finished May 12 02:14:32 PM PDT 24
Peak memory 219208 kb
Host smart-3162d7bd-583d-40f2-b56e-a1bcad6adb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243263159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3243263159
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.4125682137
Short name T132
Test name
Test status
Simulation time 103177841 ps
CPU time 1.63 seconds
Started May 12 02:14:11 PM PDT 24
Finished May 12 02:14:14 PM PDT 24
Peak memory 218380 kb
Host smart-2a019244-a444-47cb-b25d-7d344577a894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125682137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.4125682137
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert_test.1583493546
Short name T319
Test name
Test status
Simulation time 25110053 ps
CPU time 0.97 seconds
Started May 12 02:12:56 PM PDT 24
Finished May 12 02:12:58 PM PDT 24
Peak memory 214736 kb
Host smart-59a4c9a2-4be6-4262-b33c-7ef10664d558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583493546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1583493546
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/283.edn_genbits.1443806838
Short name T287
Test name
Test status
Simulation time 145844507 ps
CPU time 1.71 seconds
Started May 12 02:14:34 PM PDT 24
Finished May 12 02:14:41 PM PDT 24
Peak memory 218048 kb
Host smart-887ce60c-b898-4ed2-9dc3-f50397256dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443806838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1443806838
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert.500816249
Short name T296
Test name
Test status
Simulation time 23542988 ps
CPU time 1.2 seconds
Started May 12 02:12:14 PM PDT 24
Finished May 12 02:12:16 PM PDT 24
Peak memory 215544 kb
Host smart-6c16aa88-cfe6-4b28-80bf-28049fd6e1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500816249 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.500816249
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.1270386808
Short name T18
Test name
Test status
Simulation time 83185283 ps
CPU time 1.21 seconds
Started May 12 02:14:09 PM PDT 24
Finished May 12 02:14:13 PM PDT 24
Peak memory 219648 kb
Host smart-604359cc-1d44-4d6c-aeb1-7d2e971f9bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270386808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1270386808
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_alert.1776919815
Short name T97
Test name
Test status
Simulation time 29943739 ps
CPU time 1.2 seconds
Started May 12 02:12:47 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 215492 kb
Host smart-42a709fa-bffb-4e04-bb76-d04f19ee4033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776919815 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1776919815
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/47.edn_intr.1085026471
Short name T16
Test name
Test status
Simulation time 27286839 ps
CPU time 0.95 seconds
Started May 12 02:13:37 PM PDT 24
Finished May 12 02:13:40 PM PDT 24
Peak memory 215672 kb
Host smart-0906aefb-0e82-4c99-982f-b1390d103ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085026471 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1085026471
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.501726455
Short name T233
Test name
Test status
Simulation time 14888733 ps
CPU time 0.9 seconds
Started May 12 02:10:24 PM PDT 24
Finished May 12 02:10:26 PM PDT 24
Peak memory 206212 kb
Host smart-fc91ca3b-f99b-4f01-8362-b122c914efdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501726455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.501726455
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.460612928
Short name T261
Test name
Test status
Simulation time 332871771 ps
CPU time 2.5 seconds
Started May 12 02:10:40 PM PDT 24
Finished May 12 02:10:44 PM PDT 24
Peak memory 206712 kb
Host smart-2dd052b6-25cb-482f-91d8-fc3a4607a5b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460612928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.460612928
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_regwen.2937427073
Short name T102
Test name
Test status
Simulation time 24301664 ps
CPU time 0.99 seconds
Started May 12 02:12:31 PM PDT 24
Finished May 12 02:12:32 PM PDT 24
Peak memory 206940 kb
Host smart-bb579cc9-a10f-4796-8820-8c8c92157a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937427073 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2937427073
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/109.edn_genbits.1825623366
Short name T277
Test name
Test status
Simulation time 47301836 ps
CPU time 1.43 seconds
Started May 12 02:14:08 PM PDT 24
Finished May 12 02:14:11 PM PDT 24
Peak memory 219748 kb
Host smart-0fb61d67-17c7-4ee0-8526-59bde088aeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825623366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1825623366
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.2042710032
Short name T772
Test name
Test status
Simulation time 55458605 ps
CPU time 1.22 seconds
Started May 12 02:14:08 PM PDT 24
Finished May 12 02:14:10 PM PDT 24
Peak memory 219252 kb
Host smart-3c20eb91-7a15-4400-94c0-d061effa53b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042710032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2042710032
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.4150366458
Short name T286
Test name
Test status
Simulation time 161562178 ps
CPU time 1.7 seconds
Started May 12 02:14:06 PM PDT 24
Finished May 12 02:14:09 PM PDT 24
Peak memory 218516 kb
Host smart-e97ec2cf-bde9-47e1-bd8d-27a2e07fd3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150366458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.4150366458
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.2541546420
Short name T525
Test name
Test status
Simulation time 123616830 ps
CPU time 3.06 seconds
Started May 12 02:14:12 PM PDT 24
Finished May 12 02:14:17 PM PDT 24
Peak memory 219744 kb
Host smart-066a78fa-762f-48e9-a23e-d7cc9c327636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541546420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2541546420
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2760013187
Short name T301
Test name
Test status
Simulation time 209147485 ps
CPU time 1.28 seconds
Started May 12 02:12:53 PM PDT 24
Finished May 12 02:12:56 PM PDT 24
Peak memory 215508 kb
Host smart-93114fba-554d-4ef2-ade8-9acf8b857a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760013187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2760013187
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1487213789
Short name T494
Test name
Test status
Simulation time 321689682120 ps
CPU time 1246.37 seconds
Started May 12 02:12:47 PM PDT 24
Finished May 12 02:33:36 PM PDT 24
Peak memory 223704 kb
Host smart-f2b8ce48-467a-449a-861f-68d23aa1409a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487213789 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1487213789
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.edn_genbits.3868613128
Short name T271
Test name
Test status
Simulation time 69907545 ps
CPU time 1.39 seconds
Started May 12 02:12:57 PM PDT 24
Finished May 12 02:12:59 PM PDT 24
Peak memory 218368 kb
Host smart-295f8b90-d04b-43ea-9c2d-f1116e1b2ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868613128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3868613128
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.1994176521
Short name T292
Test name
Test status
Simulation time 25183480 ps
CPU time 0.88 seconds
Started May 12 02:12:36 PM PDT 24
Finished May 12 02:12:38 PM PDT 24
Peak memory 206900 kb
Host smart-4a2e93db-e91f-4573-a463-72ea1278e135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994176521 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1994176521
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/21.edn_stress_all.333172971
Short name T289
Test name
Test status
Simulation time 412074273 ps
CPU time 2.75 seconds
Started May 12 02:12:47 PM PDT 24
Finished May 12 02:12:52 PM PDT 24
Peak memory 216736 kb
Host smart-58e338ce-ec75-440a-aea4-f5ec5fd108c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333172971 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.333172971
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_alert.880563707
Short name T239
Test name
Test status
Simulation time 38061057 ps
CPU time 1.26 seconds
Started May 12 02:13:18 PM PDT 24
Finished May 12 02:13:20 PM PDT 24
Peak memory 215552 kb
Host smart-e45acac3-01af-47dd-a2e3-b945c6de4dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880563707 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.880563707
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/295.edn_genbits.620700016
Short name T284
Test name
Test status
Simulation time 140359088 ps
CPU time 3.44 seconds
Started May 12 02:14:39 PM PDT 24
Finished May 12 02:14:43 PM PDT 24
Peak memory 219672 kb
Host smart-767af66b-1d90-42d0-909c-dd7583b5e385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620700016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.620700016
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2358083821
Short name T110
Test name
Test status
Simulation time 26209396 ps
CPU time 0.93 seconds
Started May 12 02:12:52 PM PDT 24
Finished May 12 02:12:55 PM PDT 24
Peak memory 215608 kb
Host smart-f7f79078-1431-43d9-91a0-05a828048a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358083821 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2358083821
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/22.edn_disable.232914610
Short name T655
Test name
Test status
Simulation time 59271706 ps
CPU time 0.89 seconds
Started May 12 02:12:59 PM PDT 24
Finished May 12 02:13:00 PM PDT 24
Peak memory 215252 kb
Host smart-48ecabfe-395e-4869-9a14-d9d7714bbf13
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232914610 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.232914610
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable.1334749598
Short name T183
Test name
Test status
Simulation time 10802060 ps
CPU time 0.88 seconds
Started May 12 02:13:29 PM PDT 24
Finished May 12 02:13:32 PM PDT 24
Peak memory 215264 kb
Host smart-f0db111d-0d1b-4954-b59d-918af36beeb0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334749598 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1334749598
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/125.edn_genbits.34257573
Short name T784
Test name
Test status
Simulation time 130370945 ps
CPU time 1.7 seconds
Started May 12 02:14:05 PM PDT 24
Finished May 12 02:14:08 PM PDT 24
Peak memory 219836 kb
Host smart-65d8ed35-a067-409a-b3dc-0be8ee4d70e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34257573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.34257573
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_err.2746552495
Short name T59
Test name
Test status
Simulation time 26015726 ps
CPU time 1.21 seconds
Started May 12 02:12:51 PM PDT 24
Finished May 12 02:12:54 PM PDT 24
Peak memory 216956 kb
Host smart-330bc65a-3972-40b0-bfdf-c252ad87eeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746552495 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2746552495
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2205628700
Short name T222
Test name
Test status
Simulation time 28902849 ps
CPU time 1.3 seconds
Started May 12 02:10:24 PM PDT 24
Finished May 12 02:10:27 PM PDT 24
Peak memory 206340 kb
Host smart-cea5635d-6630-47c4-865a-608091d92693
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205628700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2205628700
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.310957294
Short name T230
Test name
Test status
Simulation time 614792652 ps
CPU time 5.3 seconds
Started May 12 02:10:22 PM PDT 24
Finished May 12 02:10:28 PM PDT 24
Peak memory 206236 kb
Host smart-3b67493a-f2fb-4f6e-ab9b-ab092cdfc0a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310957294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.310957294
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3567104424
Short name T905
Test name
Test status
Simulation time 14489706 ps
CPU time 0.91 seconds
Started May 12 02:10:23 PM PDT 24
Finished May 12 02:10:25 PM PDT 24
Peak memory 206260 kb
Host smart-2d7209ef-ab12-44d4-bbfa-742b41ab88f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567104424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3567104424
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3610345290
Short name T903
Test name
Test status
Simulation time 61532098 ps
CPU time 1.14 seconds
Started May 12 02:10:29 PM PDT 24
Finished May 12 02:10:32 PM PDT 24
Peak memory 216676 kb
Host smart-b6d4dc8b-f237-44e8-a0f0-dafac292ee8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610345290 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3610345290
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1465428660
Short name T977
Test name
Test status
Simulation time 15580097 ps
CPU time 0.91 seconds
Started May 12 02:10:21 PM PDT 24
Finished May 12 02:10:22 PM PDT 24
Peak memory 206100 kb
Host smart-d4b9b2b6-29a6-4773-84b7-91ea97dec83d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465428660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1465428660
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3521271301
Short name T238
Test name
Test status
Simulation time 42818021 ps
CPU time 1.27 seconds
Started May 12 02:10:23 PM PDT 24
Finished May 12 02:10:25 PM PDT 24
Peak memory 206248 kb
Host smart-0de87a50-3929-4a55-8890-a1e18c7e7a3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521271301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3521271301
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3127257508
Short name T875
Test name
Test status
Simulation time 107724574 ps
CPU time 2.35 seconds
Started May 12 02:10:23 PM PDT 24
Finished May 12 02:10:26 PM PDT 24
Peak memory 214444 kb
Host smart-d9fdf152-be62-46ce-9f64-dcdd392b35ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127257508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3127257508
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.837235614
Short name T975
Test name
Test status
Simulation time 344061102 ps
CPU time 2.67 seconds
Started May 12 02:10:24 PM PDT 24
Finished May 12 02:10:28 PM PDT 24
Peak memory 206260 kb
Host smart-e92c7b6e-0418-44d7-8364-d552701b312e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837235614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.837235614
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1001766919
Short name T225
Test name
Test status
Simulation time 96236518 ps
CPU time 1.19 seconds
Started May 12 02:10:28 PM PDT 24
Finished May 12 02:10:30 PM PDT 24
Peak memory 206196 kb
Host smart-af51653e-5a43-40ff-846c-943b9ca43966
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001766919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1001766919
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2251151924
Short name T878
Test name
Test status
Simulation time 719169406 ps
CPU time 5.05 seconds
Started May 12 02:10:24 PM PDT 24
Finished May 12 02:10:30 PM PDT 24
Peak memory 206232 kb
Host smart-4cf48a7c-8837-47bd-9cc6-b2e723ca5205
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251151924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2251151924
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1729338155
Short name T227
Test name
Test status
Simulation time 12934092 ps
CPU time 0.93 seconds
Started May 12 02:10:30 PM PDT 24
Finished May 12 02:10:33 PM PDT 24
Peak memory 206252 kb
Host smart-01a68a0f-f2f7-4ea5-bf86-537a5cab8d19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729338155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1729338155
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2699281221
Short name T886
Test name
Test status
Simulation time 211340546 ps
CPU time 1.17 seconds
Started May 12 02:10:24 PM PDT 24
Finished May 12 02:10:26 PM PDT 24
Peak memory 214568 kb
Host smart-335d7ffb-3381-471b-a0b0-92a3c03f6f06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699281221 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2699281221
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1192759467
Short name T879
Test name
Test status
Simulation time 42211370 ps
CPU time 0.88 seconds
Started May 12 02:10:30 PM PDT 24
Finished May 12 02:10:32 PM PDT 24
Peak memory 206272 kb
Host smart-ab88483d-bf80-4c92-a821-d4227a656bde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192759467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1192759467
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3119799547
Short name T974
Test name
Test status
Simulation time 15078427 ps
CPU time 0.92 seconds
Started May 12 02:10:23 PM PDT 24
Finished May 12 02:10:25 PM PDT 24
Peak memory 206108 kb
Host smart-e1a9a5bf-c14b-4f14-94b1-1417ef40773e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119799547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3119799547
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1055663714
Short name T976
Test name
Test status
Simulation time 117306803 ps
CPU time 1.05 seconds
Started May 12 02:10:29 PM PDT 24
Finished May 12 02:10:32 PM PDT 24
Peak memory 206208 kb
Host smart-5f7f5423-38e5-4613-ae59-d5dfd63f3765
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055663714 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1055663714
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3373771214
Short name T850
Test name
Test status
Simulation time 75388410 ps
CPU time 2.58 seconds
Started May 12 02:10:30 PM PDT 24
Finished May 12 02:10:34 PM PDT 24
Peak memory 214468 kb
Host smart-dd821b3f-3695-485f-af3b-7ebf58cf30b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373771214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3373771214
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.4237055773
Short name T245
Test name
Test status
Simulation time 95995974 ps
CPU time 2.7 seconds
Started May 12 02:10:30 PM PDT 24
Finished May 12 02:10:34 PM PDT 24
Peak memory 206256 kb
Host smart-8c289c40-465e-4f3a-a663-d89e25446f16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237055773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.4237055773
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.117299886
Short name T864
Test name
Test status
Simulation time 19140568 ps
CPU time 1.2 seconds
Started May 12 02:10:36 PM PDT 24
Finished May 12 02:10:38 PM PDT 24
Peak memory 214552 kb
Host smart-67de4afb-f33e-45fb-8178-2e105621cbe0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117299886 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.117299886
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1949617782
Short name T232
Test name
Test status
Simulation time 21290828 ps
CPU time 0.92 seconds
Started May 12 02:10:41 PM PDT 24
Finished May 12 02:10:43 PM PDT 24
Peak memory 206276 kb
Host smart-704e4504-8285-4c7d-a58b-1e58a183ba88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949617782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1949617782
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1762077056
Short name T970
Test name
Test status
Simulation time 48097833 ps
CPU time 0.8 seconds
Started May 12 02:10:37 PM PDT 24
Finished May 12 02:10:39 PM PDT 24
Peak memory 205864 kb
Host smart-d4d3a76d-67eb-4843-ba07-aa3c8f92feb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762077056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1762077056
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2677030911
Short name T962
Test name
Test status
Simulation time 54938960 ps
CPU time 1.21 seconds
Started May 12 02:10:44 PM PDT 24
Finished May 12 02:10:45 PM PDT 24
Peak memory 206204 kb
Host smart-0671c0a8-8120-4a70-97b0-8f40fc8dbf36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677030911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2677030911
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2403229993
Short name T872
Test name
Test status
Simulation time 33761203 ps
CPU time 1.83 seconds
Started May 12 02:10:44 PM PDT 24
Finished May 12 02:10:46 PM PDT 24
Peak memory 214400 kb
Host smart-0f113c36-1849-446a-86bc-cb21c5c91a4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403229993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2403229993
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3049023493
Short name T939
Test name
Test status
Simulation time 161495496 ps
CPU time 1.59 seconds
Started May 12 02:10:40 PM PDT 24
Finished May 12 02:10:43 PM PDT 24
Peak memory 206316 kb
Host smart-19e51c9b-7a29-45ef-87f0-65f568741d47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049023493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3049023493
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3461734506
Short name T893
Test name
Test status
Simulation time 90184370 ps
CPU time 1.25 seconds
Started May 12 02:10:39 PM PDT 24
Finished May 12 02:10:41 PM PDT 24
Peak memory 214512 kb
Host smart-514d784c-d6fe-4932-a157-6fe06d70cc18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461734506 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3461734506
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.987213951
Short name T964
Test name
Test status
Simulation time 15424565 ps
CPU time 0.95 seconds
Started May 12 02:10:37 PM PDT 24
Finished May 12 02:10:38 PM PDT 24
Peak memory 206240 kb
Host smart-f0a19c96-f2bc-456f-a36e-58d1ea23af33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987213951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.987213951
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1913355722
Short name T960
Test name
Test status
Simulation time 41521809 ps
CPU time 0.8 seconds
Started May 12 02:10:39 PM PDT 24
Finished May 12 02:10:41 PM PDT 24
Peak memory 205940 kb
Host smart-003fb7a3-7b3e-40d0-8cba-dec153a2cd71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913355722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1913355722
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1402023550
Short name T947
Test name
Test status
Simulation time 41828792 ps
CPU time 1.06 seconds
Started May 12 02:10:37 PM PDT 24
Finished May 12 02:10:39 PM PDT 24
Peak memory 206272 kb
Host smart-cd7d1eca-0fad-436c-82f5-b06d5ecc65e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402023550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1402023550
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3157548355
Short name T941
Test name
Test status
Simulation time 130139055 ps
CPU time 4.57 seconds
Started May 12 02:10:40 PM PDT 24
Finished May 12 02:10:46 PM PDT 24
Peak memory 214412 kb
Host smart-4f45e2b6-b54b-4476-bdc2-f8c031c3b021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157548355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3157548355
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1485630928
Short name T955
Test name
Test status
Simulation time 190726471 ps
CPU time 1.78 seconds
Started May 12 02:10:43 PM PDT 24
Finished May 12 02:10:46 PM PDT 24
Peak memory 206444 kb
Host smart-25e4ef72-b6ba-412b-b955-4e675910b2bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485630928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1485630928
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3022192332
Short name T857
Test name
Test status
Simulation time 27472435 ps
CPU time 1.34 seconds
Started May 12 02:11:10 PM PDT 24
Finished May 12 02:11:13 PM PDT 24
Peak memory 214412 kb
Host smart-2e603d06-6de2-430e-a00c-c6bf33bedc9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022192332 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3022192332
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.22622097
Short name T961
Test name
Test status
Simulation time 34958477 ps
CPU time 0.84 seconds
Started May 12 02:11:06 PM PDT 24
Finished May 12 02:11:08 PM PDT 24
Peak memory 206240 kb
Host smart-d4354224-efea-4902-ab42-b6d9a4010dc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22622097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.22622097
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2975467518
Short name T954
Test name
Test status
Simulation time 25940529 ps
CPU time 0.87 seconds
Started May 12 02:10:40 PM PDT 24
Finished May 12 02:10:42 PM PDT 24
Peak memory 206160 kb
Host smart-cc8dea14-d021-4c78-a6a5-18ad57360092
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975467518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2975467518
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1198475162
Short name T911
Test name
Test status
Simulation time 32562868 ps
CPU time 1.19 seconds
Started May 12 02:11:08 PM PDT 24
Finished May 12 02:11:11 PM PDT 24
Peak memory 206336 kb
Host smart-16eb1e9c-5436-4a82-abca-7d5a339d3f99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198475162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1198475162
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1246455726
Short name T914
Test name
Test status
Simulation time 265631007 ps
CPU time 1.64 seconds
Started May 12 02:10:38 PM PDT 24
Finished May 12 02:10:41 PM PDT 24
Peak memory 214500 kb
Host smart-672c7434-3394-4049-9065-9bdd89e80510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246455726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1246455726
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3381348761
Short name T934
Test name
Test status
Simulation time 28818364 ps
CPU time 1.97 seconds
Started May 12 02:11:08 PM PDT 24
Finished May 12 02:11:11 PM PDT 24
Peak memory 214620 kb
Host smart-0e8d8ec8-a568-42ac-bc95-884a38d55fbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381348761 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3381348761
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3033521364
Short name T228
Test name
Test status
Simulation time 11810222 ps
CPU time 0.88 seconds
Started May 12 02:11:06 PM PDT 24
Finished May 12 02:11:08 PM PDT 24
Peak memory 206240 kb
Host smart-c1f12b6c-10a8-4c26-aa40-bb81c4dc947a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033521364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3033521364
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3727141068
Short name T948
Test name
Test status
Simulation time 52901372 ps
CPU time 0.92 seconds
Started May 12 02:11:09 PM PDT 24
Finished May 12 02:11:12 PM PDT 24
Peak memory 206096 kb
Host smart-4bd56b40-ed52-407f-a68b-786a0ddc7121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727141068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3727141068
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1998706431
Short name T231
Test name
Test status
Simulation time 20660380 ps
CPU time 1.08 seconds
Started May 12 02:11:08 PM PDT 24
Finished May 12 02:11:10 PM PDT 24
Peak memory 206524 kb
Host smart-f0fdafc6-c84b-47eb-99af-4dfd66c56658
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998706431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.1998706431
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.4240464030
Short name T937
Test name
Test status
Simulation time 192535745 ps
CPU time 3.75 seconds
Started May 12 02:11:10 PM PDT 24
Finished May 12 02:11:16 PM PDT 24
Peak memory 214444 kb
Host smart-4780d87f-d226-4fe1-b127-2b77a5303b88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240464030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.4240464030
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2797714835
Short name T247
Test name
Test status
Simulation time 294996198 ps
CPU time 2.42 seconds
Started May 12 02:11:07 PM PDT 24
Finished May 12 02:11:10 PM PDT 24
Peak memory 206296 kb
Host smart-b8161cd0-187f-48f7-976c-b9062f2543fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797714835 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2797714835
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1248286911
Short name T902
Test name
Test status
Simulation time 20116189 ps
CPU time 1.37 seconds
Started May 12 02:11:09 PM PDT 24
Finished May 12 02:11:13 PM PDT 24
Peak memory 214540 kb
Host smart-e6425a8c-0b11-4816-9f34-06566437bf6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248286911 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1248286911
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2247041253
Short name T925
Test name
Test status
Simulation time 35991220 ps
CPU time 0.83 seconds
Started May 12 02:11:09 PM PDT 24
Finished May 12 02:11:12 PM PDT 24
Peak memory 206076 kb
Host smart-32e0332e-e4b2-4c90-95b7-4519955fcc64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247041253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2247041253
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.428626589
Short name T956
Test name
Test status
Simulation time 44532346 ps
CPU time 0.91 seconds
Started May 12 02:11:07 PM PDT 24
Finished May 12 02:11:09 PM PDT 24
Peak memory 206116 kb
Host smart-960325af-c3e0-4d23-bd36-868b655e288a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428626589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.428626589
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3290883563
Short name T938
Test name
Test status
Simulation time 18083912 ps
CPU time 1.11 seconds
Started May 12 02:11:07 PM PDT 24
Finished May 12 02:11:09 PM PDT 24
Peak memory 206316 kb
Host smart-1652b67b-6e6f-42a9-b067-6b348ccb5b34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290883563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3290883563
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2764095212
Short name T867
Test name
Test status
Simulation time 344395490 ps
CPU time 2.87 seconds
Started May 12 02:11:06 PM PDT 24
Finished May 12 02:11:10 PM PDT 24
Peak memory 214452 kb
Host smart-3e7dbb6c-872c-4a82-a570-be190a5e03c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764095212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2764095212
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1722723400
Short name T260
Test name
Test status
Simulation time 56788436 ps
CPU time 1.77 seconds
Started May 12 02:11:07 PM PDT 24
Finished May 12 02:11:10 PM PDT 24
Peak memory 214552 kb
Host smart-a571ea12-fe04-4aab-b9ce-606d1697cc15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722723400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1722723400
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.494421278
Short name T916
Test name
Test status
Simulation time 31995153 ps
CPU time 1.05 seconds
Started May 12 02:11:08 PM PDT 24
Finished May 12 02:11:10 PM PDT 24
Peak memory 214560 kb
Host smart-5bca6a86-fd07-4996-b94d-6dc52e1d3b04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494421278 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.494421278
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2096939346
Short name T229
Test name
Test status
Simulation time 12381903 ps
CPU time 0.93 seconds
Started May 12 02:11:10 PM PDT 24
Finished May 12 02:11:13 PM PDT 24
Peak memory 206276 kb
Host smart-f0238b65-a714-42dc-8960-0648c9d340db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096939346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2096939346
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3060952568
Short name T860
Test name
Test status
Simulation time 85704537 ps
CPU time 0.86 seconds
Started May 12 02:11:08 PM PDT 24
Finished May 12 02:11:10 PM PDT 24
Peak memory 206116 kb
Host smart-ba450aac-db7c-4b8a-a3e7-4992937018d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060952568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3060952568
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3706666255
Short name T906
Test name
Test status
Simulation time 57724393 ps
CPU time 1.09 seconds
Started May 12 02:11:07 PM PDT 24
Finished May 12 02:11:10 PM PDT 24
Peak memory 206292 kb
Host smart-3c39a364-0f15-47a8-8a3f-49eab57e8451
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706666255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3706666255
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1851671678
Short name T891
Test name
Test status
Simulation time 126046466 ps
CPU time 2.54 seconds
Started May 12 02:11:08 PM PDT 24
Finished May 12 02:11:12 PM PDT 24
Peak memory 214364 kb
Host smart-b97dff10-aba1-441d-8f2b-48ff1e4f549e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851671678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1851671678
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1397581295
Short name T966
Test name
Test status
Simulation time 93591308 ps
CPU time 1.76 seconds
Started May 12 02:11:06 PM PDT 24
Finished May 12 02:11:09 PM PDT 24
Peak memory 206604 kb
Host smart-3374aba2-a911-48e4-9a55-b504c6b59a44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397581295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1397581295
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.737945797
Short name T944
Test name
Test status
Simulation time 26131634 ps
CPU time 1.77 seconds
Started May 12 02:11:06 PM PDT 24
Finished May 12 02:11:08 PM PDT 24
Peak memory 214776 kb
Host smart-6ce56da5-9e78-432a-a17a-f377ead7df3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737945797 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.737945797
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.939220720
Short name T236
Test name
Test status
Simulation time 28400333 ps
CPU time 0.81 seconds
Started May 12 02:11:12 PM PDT 24
Finished May 12 02:11:15 PM PDT 24
Peak memory 206064 kb
Host smart-635da41c-768f-44ac-8d29-f52600638bbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939220720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.939220720
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3767316506
Short name T952
Test name
Test status
Simulation time 19765026 ps
CPU time 0.9 seconds
Started May 12 02:11:09 PM PDT 24
Finished May 12 02:11:12 PM PDT 24
Peak memory 205984 kb
Host smart-39f052c3-4936-4fc8-9b53-614e67347dc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767316506 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3767316506
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1948008120
Short name T926
Test name
Test status
Simulation time 40421102 ps
CPU time 1.18 seconds
Started May 12 02:11:07 PM PDT 24
Finished May 12 02:11:09 PM PDT 24
Peak memory 206296 kb
Host smart-4946ed68-e18b-4214-8f2d-2e4314d13a8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948008120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1948008120
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.971369590
Short name T897
Test name
Test status
Simulation time 216731833 ps
CPU time 1.59 seconds
Started May 12 02:11:06 PM PDT 24
Finished May 12 02:11:09 PM PDT 24
Peak memory 214468 kb
Host smart-fcdc661e-fba4-4574-b038-e273cdf618dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971369590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.971369590
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.944073154
Short name T262
Test name
Test status
Simulation time 85784991 ps
CPU time 2.39 seconds
Started May 12 02:11:09 PM PDT 24
Finished May 12 02:11:13 PM PDT 24
Peak memory 206116 kb
Host smart-75f3b892-02de-4915-abf7-8202bcec4f00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944073154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.944073154
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.4252714655
Short name T858
Test name
Test status
Simulation time 24189732 ps
CPU time 1.04 seconds
Started May 12 02:11:13 PM PDT 24
Finished May 12 02:11:16 PM PDT 24
Peak memory 206352 kb
Host smart-725c965d-4e4d-4092-83ad-7e10246195d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252714655 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.4252714655
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1589857938
Short name T865
Test name
Test status
Simulation time 45699695 ps
CPU time 0.9 seconds
Started May 12 02:11:09 PM PDT 24
Finished May 12 02:11:12 PM PDT 24
Peak memory 206280 kb
Host smart-6cd599ef-7eb4-46c7-b056-c20decbf9938
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589857938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1589857938
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.853595836
Short name T969
Test name
Test status
Simulation time 52685389 ps
CPU time 0.84 seconds
Started May 12 02:10:48 PM PDT 24
Finished May 12 02:10:50 PM PDT 24
Peak memory 206100 kb
Host smart-3ec9b32b-da6a-4b49-abad-c4c916a8011c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853595836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.853595836
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.4063727041
Short name T945
Test name
Test status
Simulation time 14798254 ps
CPU time 0.99 seconds
Started May 12 02:11:01 PM PDT 24
Finished May 12 02:11:02 PM PDT 24
Peak memory 206292 kb
Host smart-701e5776-16ba-4511-99ca-ef8842fd21b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063727041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.4063727041
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.736807053
Short name T921
Test name
Test status
Simulation time 1879969653 ps
CPU time 4.33 seconds
Started May 12 02:11:07 PM PDT 24
Finished May 12 02:11:13 PM PDT 24
Peak memory 214432 kb
Host smart-c4a55cf6-6c65-4c3d-8aa1-0aa47882bcfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736807053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.736807053
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1434366376
Short name T907
Test name
Test status
Simulation time 163994459 ps
CPU time 1.74 seconds
Started May 12 02:11:12 PM PDT 24
Finished May 12 02:11:16 PM PDT 24
Peak memory 206376 kb
Host smart-90020cfa-3314-4f43-a4d2-34589bc67a91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434366376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1434366376
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.711375739
Short name T904
Test name
Test status
Simulation time 24784285 ps
CPU time 1.64 seconds
Started May 12 02:11:09 PM PDT 24
Finished May 12 02:11:13 PM PDT 24
Peak memory 214556 kb
Host smart-e16b22cd-be17-4fdc-bad2-f60bee0cb7e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711375739 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.711375739
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3265153906
Short name T957
Test name
Test status
Simulation time 23764935 ps
CPU time 0.9 seconds
Started May 12 02:11:08 PM PDT 24
Finished May 12 02:11:10 PM PDT 24
Peak memory 206164 kb
Host smart-9107e7a9-04e7-4b9d-a39b-1d6889fe842a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265153906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3265153906
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1696138735
Short name T849
Test name
Test status
Simulation time 17439372 ps
CPU time 0.88 seconds
Started May 12 02:11:08 PM PDT 24
Finished May 12 02:11:10 PM PDT 24
Peak memory 206148 kb
Host smart-170baab2-3263-435e-b262-43a9dcaa000d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696138735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1696138735
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2441145074
Short name T942
Test name
Test status
Simulation time 37917132 ps
CPU time 0.91 seconds
Started May 12 02:11:08 PM PDT 24
Finished May 12 02:11:10 PM PDT 24
Peak memory 206304 kb
Host smart-eaa07240-d1a5-4855-b464-dfaffb33d062
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441145074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2441145074
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2147279698
Short name T885
Test name
Test status
Simulation time 127796066 ps
CPU time 2.64 seconds
Started May 12 02:11:08 PM PDT 24
Finished May 12 02:11:13 PM PDT 24
Peak memory 214416 kb
Host smart-929365af-1880-4d32-8212-c1b61faf337b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147279698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2147279698
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1662718884
Short name T965
Test name
Test status
Simulation time 298249002 ps
CPU time 2.34 seconds
Started May 12 02:11:10 PM PDT 24
Finished May 12 02:11:14 PM PDT 24
Peak memory 214400 kb
Host smart-c12aa06e-3372-46e5-9d78-94e432ef4863
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662718884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1662718884
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2746306108
Short name T978
Test name
Test status
Simulation time 118545652 ps
CPU time 1.46 seconds
Started May 12 02:11:09 PM PDT 24
Finished May 12 02:11:13 PM PDT 24
Peak memory 214556 kb
Host smart-3d3342c7-3c4b-4ad1-b54c-4a2d9929154a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746306108 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2746306108
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.287196955
Short name T237
Test name
Test status
Simulation time 15858808 ps
CPU time 0.93 seconds
Started May 12 02:11:07 PM PDT 24
Finished May 12 02:11:10 PM PDT 24
Peak memory 206272 kb
Host smart-45f22a6b-5c60-4de6-b0ef-6333dd9604f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287196955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.287196955
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2587700077
Short name T871
Test name
Test status
Simulation time 15571227 ps
CPU time 0.91 seconds
Started May 12 02:11:08 PM PDT 24
Finished May 12 02:11:10 PM PDT 24
Peak memory 206108 kb
Host smart-1707294b-6909-4d17-b988-112f0907fb6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587700077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2587700077
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3367351427
Short name T979
Test name
Test status
Simulation time 72209736 ps
CPU time 1.17 seconds
Started May 12 02:11:13 PM PDT 24
Finished May 12 02:11:17 PM PDT 24
Peak memory 206268 kb
Host smart-e4760741-3c82-45e1-8364-8a5260835496
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367351427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3367351427
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.265372242
Short name T932
Test name
Test status
Simulation time 90745512 ps
CPU time 3.4 seconds
Started May 12 02:11:14 PM PDT 24
Finished May 12 02:11:20 PM PDT 24
Peak memory 214472 kb
Host smart-5e494ceb-c154-446e-bce7-dc9f990da35f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265372242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.265372242
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2993337330
Short name T958
Test name
Test status
Simulation time 81811028 ps
CPU time 2.4 seconds
Started May 12 02:11:08 PM PDT 24
Finished May 12 02:11:12 PM PDT 24
Peak memory 206384 kb
Host smart-cade9621-a18e-4bb1-8e08-e572edf6fc6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993337330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2993337330
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3317664711
Short name T950
Test name
Test status
Simulation time 232161392 ps
CPU time 5.78 seconds
Started May 12 02:10:29 PM PDT 24
Finished May 12 02:10:36 PM PDT 24
Peak memory 206324 kb
Host smart-fdf4ea9d-7916-4b02-9ba3-074dbf5381ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317664711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3317664711
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3766008267
Short name T220
Test name
Test status
Simulation time 86942066 ps
CPU time 0.85 seconds
Started May 12 02:10:27 PM PDT 24
Finished May 12 02:10:29 PM PDT 24
Peak memory 206164 kb
Host smart-36c4ff5a-d957-46bd-9e86-9277a2cd53dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766008267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3766008267
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1246252856
Short name T892
Test name
Test status
Simulation time 47930103 ps
CPU time 1.45 seconds
Started May 12 02:10:25 PM PDT 24
Finished May 12 02:10:28 PM PDT 24
Peak memory 214460 kb
Host smart-7b5ce56d-bc31-4f3e-ba09-209b9bda916f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246252856 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1246252856
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1705777375
Short name T909
Test name
Test status
Simulation time 26641103 ps
CPU time 0.77 seconds
Started May 12 02:10:29 PM PDT 24
Finished May 12 02:10:31 PM PDT 24
Peak memory 205996 kb
Host smart-4167c14c-517e-47c6-b01e-32117f94e3e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705777375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1705777375
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2702134476
Short name T940
Test name
Test status
Simulation time 40831681 ps
CPU time 0.81 seconds
Started May 12 02:10:25 PM PDT 24
Finished May 12 02:10:27 PM PDT 24
Peak memory 206148 kb
Host smart-5b2d5893-4db2-4495-8d6c-64fa48d59ea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702134476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2702134476
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3499627552
Short name T935
Test name
Test status
Simulation time 36938113 ps
CPU time 1.38 seconds
Started May 12 02:10:34 PM PDT 24
Finished May 12 02:10:36 PM PDT 24
Peak memory 206172 kb
Host smart-be0a1b94-1a60-4cde-8e2c-467b9791f27b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499627552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3499627552
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.4060982096
Short name T963
Test name
Test status
Simulation time 81696916 ps
CPU time 3.1 seconds
Started May 12 02:10:27 PM PDT 24
Finished May 12 02:10:31 PM PDT 24
Peak memory 214492 kb
Host smart-5c26749d-78a2-47ef-b1a1-5f4d3e8eda1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060982096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.4060982096
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3943326528
Short name T953
Test name
Test status
Simulation time 44829330 ps
CPU time 1.58 seconds
Started May 12 02:10:26 PM PDT 24
Finished May 12 02:10:29 PM PDT 24
Peak memory 206596 kb
Host smart-80b44751-5d20-421c-a405-17aca04ec3d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943326528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3943326528
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1857415043
Short name T890
Test name
Test status
Simulation time 34736698 ps
CPU time 0.84 seconds
Started May 12 02:11:10 PM PDT 24
Finished May 12 02:11:13 PM PDT 24
Peak memory 206076 kb
Host smart-44d4998e-7769-4833-944b-f9d8cb9a0386
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857415043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1857415043
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.4155191851
Short name T880
Test name
Test status
Simulation time 49983719 ps
CPU time 0.91 seconds
Started May 12 02:11:12 PM PDT 24
Finished May 12 02:11:15 PM PDT 24
Peak memory 206108 kb
Host smart-f8e32a05-85f0-4836-9dd0-f7c5b14d7f5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155191851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.4155191851
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.4114892696
Short name T972
Test name
Test status
Simulation time 21578735 ps
CPU time 0.82 seconds
Started May 12 02:11:14 PM PDT 24
Finished May 12 02:11:17 PM PDT 24
Peak memory 206144 kb
Host smart-646b5cef-c7ac-4260-be50-dc9645ff432f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114892696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.4114892696
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3904452957
Short name T943
Test name
Test status
Simulation time 29971460 ps
CPU time 0.92 seconds
Started May 12 02:11:09 PM PDT 24
Finished May 12 02:11:12 PM PDT 24
Peak memory 206216 kb
Host smart-4cceda27-cf87-4b72-accc-84615ea5877b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904452957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3904452957
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.4112374213
Short name T912
Test name
Test status
Simulation time 30870853 ps
CPU time 0.79 seconds
Started May 12 02:11:09 PM PDT 24
Finished May 12 02:11:11 PM PDT 24
Peak memory 205916 kb
Host smart-322b39f3-2cdc-4e9e-9c29-aa557e9918df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112374213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.4112374213
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2179681451
Short name T854
Test name
Test status
Simulation time 17491095 ps
CPU time 0.84 seconds
Started May 12 02:11:12 PM PDT 24
Finished May 12 02:11:15 PM PDT 24
Peak memory 206140 kb
Host smart-86e1ac88-27dd-4ab4-9b4b-9331a4b9d510
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179681451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2179681451
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2148466428
Short name T918
Test name
Test status
Simulation time 37121136 ps
CPU time 0.87 seconds
Started May 12 02:11:12 PM PDT 24
Finished May 12 02:11:15 PM PDT 24
Peak memory 205932 kb
Host smart-120e246f-bedc-4ee3-9cbf-a4cee7d5c100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148466428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2148466428
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2772338893
Short name T913
Test name
Test status
Simulation time 22074954 ps
CPU time 0.83 seconds
Started May 12 02:11:08 PM PDT 24
Finished May 12 02:11:11 PM PDT 24
Peak memory 206088 kb
Host smart-e6c76ba1-e4de-41ba-94f9-d109fc225b8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772338893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2772338893
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1568908000
Short name T910
Test name
Test status
Simulation time 29094444 ps
CPU time 0.78 seconds
Started May 12 02:11:10 PM PDT 24
Finished May 12 02:11:13 PM PDT 24
Peak memory 205932 kb
Host smart-59ba4452-f21b-4a16-8345-74a3da416923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568908000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1568908000
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.983582401
Short name T917
Test name
Test status
Simulation time 50849999 ps
CPU time 0.91 seconds
Started May 12 02:11:14 PM PDT 24
Finished May 12 02:11:17 PM PDT 24
Peak memory 206072 kb
Host smart-01899fea-8333-4fc6-9f72-d53acf1a5735
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983582401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.983582401
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1164768015
Short name T946
Test name
Test status
Simulation time 24906293 ps
CPU time 0.95 seconds
Started May 12 02:10:29 PM PDT 24
Finished May 12 02:10:31 PM PDT 24
Peak memory 206276 kb
Host smart-193bdf0a-ae8e-4d31-bc98-ad8fb17976ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164768015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1164768015
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.891964756
Short name T901
Test name
Test status
Simulation time 122040455 ps
CPU time 3.21 seconds
Started May 12 02:10:27 PM PDT 24
Finished May 12 02:10:32 PM PDT 24
Peak memory 206168 kb
Host smart-b4e5b7a9-e8a3-4370-8b66-95fb8a92f0d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891964756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.891964756
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3144118117
Short name T224
Test name
Test status
Simulation time 58816586 ps
CPU time 0.99 seconds
Started May 12 02:10:30 PM PDT 24
Finished May 12 02:10:33 PM PDT 24
Peak memory 206280 kb
Host smart-7a02358f-0b46-4b61-a312-2aa479f30990
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144118117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3144118117
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2199470904
Short name T900
Test name
Test status
Simulation time 49723869 ps
CPU time 1.07 seconds
Started May 12 02:10:28 PM PDT 24
Finished May 12 02:10:30 PM PDT 24
Peak memory 214616 kb
Host smart-dddf3c0a-4158-406f-ae06-e3ec221d6fcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199470904 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2199470904
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.160181292
Short name T244
Test name
Test status
Simulation time 19252927 ps
CPU time 0.88 seconds
Started May 12 02:10:25 PM PDT 24
Finished May 12 02:10:27 PM PDT 24
Peak memory 206244 kb
Host smart-cdc00107-e3e3-488a-b387-b3031f5e4b3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160181292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.160181292
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.701520694
Short name T929
Test name
Test status
Simulation time 16933299 ps
CPU time 0.81 seconds
Started May 12 02:10:34 PM PDT 24
Finished May 12 02:10:35 PM PDT 24
Peak memory 206040 kb
Host smart-8d8b0368-e13b-46c7-a3cb-4e27e1240dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701520694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.701520694
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2521084983
Short name T899
Test name
Test status
Simulation time 21638688 ps
CPU time 0.89 seconds
Started May 12 02:10:32 PM PDT 24
Finished May 12 02:10:34 PM PDT 24
Peak memory 206152 kb
Host smart-589d2918-04be-40e6-9867-abacd2f3235d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521084983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2521084983
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2119745420
Short name T853
Test name
Test status
Simulation time 88065536 ps
CPU time 2.53 seconds
Started May 12 02:10:26 PM PDT 24
Finished May 12 02:10:30 PM PDT 24
Peak memory 214380 kb
Host smart-7dcffea4-ddf2-45ad-8ef8-c0b5241d8ed5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119745420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2119745420
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2733254348
Short name T881
Test name
Test status
Simulation time 100648496 ps
CPU time 1.63 seconds
Started May 12 02:10:27 PM PDT 24
Finished May 12 02:10:29 PM PDT 24
Peak memory 214576 kb
Host smart-a56829d8-65d3-461f-a8c9-d74e62ecff23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733254348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2733254348
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.4190949738
Short name T922
Test name
Test status
Simulation time 12417598 ps
CPU time 0.85 seconds
Started May 12 02:11:11 PM PDT 24
Finished May 12 02:11:14 PM PDT 24
Peak memory 206124 kb
Host smart-a199b674-147c-4f80-8454-b64081e9e87b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190949738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.4190949738
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1889318572
Short name T931
Test name
Test status
Simulation time 51908665 ps
CPU time 0.88 seconds
Started May 12 02:11:14 PM PDT 24
Finished May 12 02:11:18 PM PDT 24
Peak memory 206144 kb
Host smart-66679b1d-e0ec-46b5-80c7-132211cc0456
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889318572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1889318572
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2543315889
Short name T889
Test name
Test status
Simulation time 24935354 ps
CPU time 0.89 seconds
Started May 12 02:11:13 PM PDT 24
Finished May 12 02:11:16 PM PDT 24
Peak memory 206084 kb
Host smart-19b5d610-75ca-42ba-920e-9e79fe0c6bff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543315889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2543315889
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1375041078
Short name T856
Test name
Test status
Simulation time 44345220 ps
CPU time 0.87 seconds
Started May 12 02:11:09 PM PDT 24
Finished May 12 02:11:12 PM PDT 24
Peak memory 205940 kb
Host smart-0aa82f1c-f4ae-4565-a891-5aa24ccca33d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375041078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1375041078
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1855499253
Short name T866
Test name
Test status
Simulation time 22421293 ps
CPU time 0.85 seconds
Started May 12 02:11:08 PM PDT 24
Finished May 12 02:11:11 PM PDT 24
Peak memory 206128 kb
Host smart-462f3e15-faac-4740-916a-ccd89013e47c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855499253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1855499253
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.542942126
Short name T861
Test name
Test status
Simulation time 14173750 ps
CPU time 0.84 seconds
Started May 12 02:11:07 PM PDT 24
Finished May 12 02:11:09 PM PDT 24
Peak memory 206080 kb
Host smart-048219b3-7915-4bba-9f07-d5a6a91c510a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542942126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.542942126
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1285765983
Short name T951
Test name
Test status
Simulation time 64043743 ps
CPU time 0.89 seconds
Started May 12 02:11:12 PM PDT 24
Finished May 12 02:11:15 PM PDT 24
Peak memory 206316 kb
Host smart-e2ffb766-a413-48da-8c9d-4f43adfce55d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285765983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1285765983
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2853738820
Short name T924
Test name
Test status
Simulation time 90212547 ps
CPU time 0.89 seconds
Started May 12 02:11:11 PM PDT 24
Finished May 12 02:11:14 PM PDT 24
Peak memory 206160 kb
Host smart-eea91992-1441-4bff-ac47-1a607e761f26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853738820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2853738820
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.469483708
Short name T873
Test name
Test status
Simulation time 62226535 ps
CPU time 0.88 seconds
Started May 12 02:11:12 PM PDT 24
Finished May 12 02:11:15 PM PDT 24
Peak memory 206096 kb
Host smart-f0c11197-2001-4e86-8d10-fe18150654ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469483708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.469483708
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.498280012
Short name T883
Test name
Test status
Simulation time 15882033 ps
CPU time 0.93 seconds
Started May 12 02:11:13 PM PDT 24
Finished May 12 02:11:16 PM PDT 24
Peak memory 206160 kb
Host smart-6a4b10d2-160b-4c25-8af8-9d1168e82df4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498280012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.498280012
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2917787314
Short name T217
Test name
Test status
Simulation time 66494610 ps
CPU time 1.59 seconds
Started May 12 02:10:29 PM PDT 24
Finished May 12 02:10:32 PM PDT 24
Peak memory 206344 kb
Host smart-7552a81a-fc91-4b04-a6fd-892b3e305ec1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917787314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2917787314
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4133353195
Short name T915
Test name
Test status
Simulation time 178435685 ps
CPU time 3.07 seconds
Started May 12 02:10:30 PM PDT 24
Finished May 12 02:10:35 PM PDT 24
Peak memory 206384 kb
Host smart-e1c87e5e-90ad-434c-81c7-8d468f66540c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133353195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.4133353195
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2134104705
Short name T949
Test name
Test status
Simulation time 42535489 ps
CPU time 0.83 seconds
Started May 12 02:10:30 PM PDT 24
Finished May 12 02:10:33 PM PDT 24
Peak memory 206064 kb
Host smart-d5a4c7ba-9430-4850-a012-399bd1755b0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134104705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2134104705
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.130641491
Short name T888
Test name
Test status
Simulation time 48852471 ps
CPU time 1.33 seconds
Started May 12 02:10:30 PM PDT 24
Finished May 12 02:10:33 PM PDT 24
Peak memory 214404 kb
Host smart-76663e7c-04d7-4c4f-8271-ebe7e525b572
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130641491 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.130641491
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2801719105
Short name T219
Test name
Test status
Simulation time 82828485 ps
CPU time 0.94 seconds
Started May 12 02:10:30 PM PDT 24
Finished May 12 02:10:33 PM PDT 24
Peak memory 206304 kb
Host smart-583348cf-9568-4d78-b5f0-53009eca691f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801719105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2801719105
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.899765215
Short name T859
Test name
Test status
Simulation time 46571945 ps
CPU time 0.91 seconds
Started May 12 02:10:40 PM PDT 24
Finished May 12 02:10:42 PM PDT 24
Peak memory 206048 kb
Host smart-d4ed7665-19db-42bd-b5f1-179207616427
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899765215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.899765215
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4201716667
Short name T896
Test name
Test status
Simulation time 52425904 ps
CPU time 1.31 seconds
Started May 12 02:10:29 PM PDT 24
Finished May 12 02:10:32 PM PDT 24
Peak memory 206304 kb
Host smart-a2b8b158-0584-40b0-af47-ff46d585e9e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201716667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.4201716667
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.882105693
Short name T876
Test name
Test status
Simulation time 113934378 ps
CPU time 1.72 seconds
Started May 12 02:10:25 PM PDT 24
Finished May 12 02:10:28 PM PDT 24
Peak memory 214716 kb
Host smart-826dfcf1-77e3-4a15-b0c0-9c66b01cb61a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882105693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.882105693
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1731518964
Short name T246
Test name
Test status
Simulation time 80737908 ps
CPU time 1.52 seconds
Started May 12 02:10:34 PM PDT 24
Finished May 12 02:10:36 PM PDT 24
Peak memory 206180 kb
Host smart-cbaa54ad-8c93-4dd6-88a8-684535b4f2aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731518964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1731518964
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.4011855124
Short name T933
Test name
Test status
Simulation time 50145297 ps
CPU time 0.95 seconds
Started May 12 02:11:11 PM PDT 24
Finished May 12 02:11:14 PM PDT 24
Peak memory 206128 kb
Host smart-c323b4eb-c48a-4efb-a4d1-cb72a95697f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011855124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.4011855124
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.232285935
Short name T862
Test name
Test status
Simulation time 18566706 ps
CPU time 0.85 seconds
Started May 12 02:11:15 PM PDT 24
Finished May 12 02:11:19 PM PDT 24
Peak memory 206032 kb
Host smart-e03c1f87-3fd9-4e53-9e71-75b81c8aeddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232285935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.232285935
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.183232691
Short name T968
Test name
Test status
Simulation time 96684593 ps
CPU time 0.86 seconds
Started May 12 02:11:11 PM PDT 24
Finished May 12 02:11:13 PM PDT 24
Peak memory 206152 kb
Host smart-7ec12dbe-cbaa-45f4-a82d-64c771f738e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183232691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.183232691
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2765658978
Short name T882
Test name
Test status
Simulation time 13543767 ps
CPU time 0.92 seconds
Started May 12 02:11:12 PM PDT 24
Finished May 12 02:11:15 PM PDT 24
Peak memory 206308 kb
Host smart-bc3706b1-3e6a-4301-ba4d-9b1961bf5a71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765658978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2765658978
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3569112382
Short name T971
Test name
Test status
Simulation time 37698128 ps
CPU time 0.82 seconds
Started May 12 02:11:11 PM PDT 24
Finished May 12 02:11:14 PM PDT 24
Peak memory 205920 kb
Host smart-de93e271-1ba2-4600-bb37-64a6fb3744d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569112382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3569112382
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.102902060
Short name T908
Test name
Test status
Simulation time 19830122 ps
CPU time 0.82 seconds
Started May 12 02:11:11 PM PDT 24
Finished May 12 02:11:14 PM PDT 24
Peak memory 205920 kb
Host smart-fd28a781-482a-4c1f-9834-20071d1da2a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102902060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.102902060
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2739550031
Short name T874
Test name
Test status
Simulation time 33812707 ps
CPU time 0.8 seconds
Started May 12 02:11:12 PM PDT 24
Finished May 12 02:11:15 PM PDT 24
Peak memory 205920 kb
Host smart-0b839855-dd76-43fd-b133-76db7aac9e81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739550031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2739550031
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1490196155
Short name T852
Test name
Test status
Simulation time 36574983 ps
CPU time 0.93 seconds
Started May 12 02:11:11 PM PDT 24
Finished May 12 02:11:14 PM PDT 24
Peak memory 206124 kb
Host smart-fcbe49d1-85f6-41f6-890d-f9f0f0148678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490196155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1490196155
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3047604643
Short name T855
Test name
Test status
Simulation time 15116612 ps
CPU time 0.97 seconds
Started May 12 02:11:11 PM PDT 24
Finished May 12 02:11:14 PM PDT 24
Peak memory 206120 kb
Host smart-74bcd339-2fdb-46b2-aeb0-3e6ac42efb9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047604643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3047604643
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2303044436
Short name T863
Test name
Test status
Simulation time 31322956 ps
CPU time 0.83 seconds
Started May 12 02:11:14 PM PDT 24
Finished May 12 02:11:18 PM PDT 24
Peak memory 205940 kb
Host smart-f71d42fe-58ac-4830-9383-11d50a3169bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303044436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2303044436
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1475294477
Short name T936
Test name
Test status
Simulation time 91882374 ps
CPU time 1.63 seconds
Started May 12 02:10:40 PM PDT 24
Finished May 12 02:10:43 PM PDT 24
Peak memory 214512 kb
Host smart-332a88ad-ee86-42c9-9349-ff8bf20ee8bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475294477 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1475294477
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.48416947
Short name T223
Test name
Test status
Simulation time 16464575 ps
CPU time 0.94 seconds
Started May 12 02:10:40 PM PDT 24
Finished May 12 02:10:42 PM PDT 24
Peak memory 206168 kb
Host smart-17d72b2b-6ed6-4685-acf4-a9f3f38ffc88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48416947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.48416947
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.214332509
Short name T868
Test name
Test status
Simulation time 14902891 ps
CPU time 0.89 seconds
Started May 12 02:10:28 PM PDT 24
Finished May 12 02:10:30 PM PDT 24
Peak memory 206112 kb
Host smart-0e1319eb-6d2e-4e1f-a61a-b5da00a2beea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214332509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.214332509
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3602782678
Short name T221
Test name
Test status
Simulation time 69592989 ps
CPU time 1.33 seconds
Started May 12 02:10:29 PM PDT 24
Finished May 12 02:10:32 PM PDT 24
Peak memory 206324 kb
Host smart-cedef6a1-3ef3-466b-82ac-052ecd9b03f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602782678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3602782678
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3099916180
Short name T894
Test name
Test status
Simulation time 65594439 ps
CPU time 2.5 seconds
Started May 12 02:10:30 PM PDT 24
Finished May 12 02:10:35 PM PDT 24
Peak memory 214424 kb
Host smart-46b0ce1c-88e2-4876-a581-ca28f209ab79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099916180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3099916180
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.907488270
Short name T263
Test name
Test status
Simulation time 726412430 ps
CPU time 2.27 seconds
Started May 12 02:10:30 PM PDT 24
Finished May 12 02:10:34 PM PDT 24
Peak memory 214568 kb
Host smart-6195a4b7-68a0-4370-8faf-7e994e16c86d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907488270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.907488270
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3061388765
Short name T973
Test name
Test status
Simulation time 34521570 ps
CPU time 1.09 seconds
Started May 12 02:10:40 PM PDT 24
Finished May 12 02:10:42 PM PDT 24
Peak memory 214440 kb
Host smart-fc18a993-5e99-4c20-92b5-eb28b58a899b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061388765 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3061388765
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3287337502
Short name T967
Test name
Test status
Simulation time 21509486 ps
CPU time 0.9 seconds
Started May 12 02:10:29 PM PDT 24
Finished May 12 02:10:32 PM PDT 24
Peak memory 206240 kb
Host smart-ef3566ba-0e4e-48c8-aadc-74f021c7610a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287337502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3287337502
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3571447897
Short name T851
Test name
Test status
Simulation time 12116648 ps
CPU time 0.81 seconds
Started May 12 02:10:28 PM PDT 24
Finished May 12 02:10:30 PM PDT 24
Peak memory 206140 kb
Host smart-ef9d46d1-e2f2-441e-8bbb-fe85af336ca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571447897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3571447897
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2099874230
Short name T928
Test name
Test status
Simulation time 253992279 ps
CPU time 1.2 seconds
Started May 12 02:10:30 PM PDT 24
Finished May 12 02:10:33 PM PDT 24
Peak memory 206332 kb
Host smart-a2682c73-2bed-4438-986b-bcdf05df235e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099874230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2099874230
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1643294473
Short name T927
Test name
Test status
Simulation time 57858379 ps
CPU time 1.98 seconds
Started May 12 02:10:31 PM PDT 24
Finished May 12 02:10:34 PM PDT 24
Peak memory 214456 kb
Host smart-8f9d8741-5ebd-454a-9ce4-0827c86ba9a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643294473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1643294473
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2399205794
Short name T923
Test name
Test status
Simulation time 171805013 ps
CPU time 1.58 seconds
Started May 12 02:10:40 PM PDT 24
Finished May 12 02:10:43 PM PDT 24
Peak memory 214372 kb
Host smart-93a69bf8-855a-421e-a6c2-29f5057e371c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399205794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2399205794
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3045087630
Short name T930
Test name
Test status
Simulation time 32740426 ps
CPU time 1.16 seconds
Started May 12 02:10:35 PM PDT 24
Finished May 12 02:10:36 PM PDT 24
Peak memory 214652 kb
Host smart-b2cd6254-295c-457d-ba24-600a3d8337b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045087630 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3045087630
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.190597846
Short name T869
Test name
Test status
Simulation time 90426467 ps
CPU time 0.9 seconds
Started May 12 02:10:40 PM PDT 24
Finished May 12 02:10:42 PM PDT 24
Peak memory 206168 kb
Host smart-aae2cc7e-b375-4188-951d-a008e148245d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190597846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.190597846
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.249471822
Short name T919
Test name
Test status
Simulation time 25608542 ps
CPU time 0.82 seconds
Started May 12 02:10:35 PM PDT 24
Finished May 12 02:10:37 PM PDT 24
Peak memory 205896 kb
Host smart-f2267304-604b-4c1e-9f57-6e8dad858cae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249471822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.249471822
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.927202918
Short name T235
Test name
Test status
Simulation time 21338920 ps
CPU time 1.24 seconds
Started May 12 02:10:37 PM PDT 24
Finished May 12 02:10:39 PM PDT 24
Peak memory 206268 kb
Host smart-f47f417d-73e3-49ea-9b59-19613fd765ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927202918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.927202918
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1293098383
Short name T884
Test name
Test status
Simulation time 51711507 ps
CPU time 3.08 seconds
Started May 12 02:10:37 PM PDT 24
Finished May 12 02:10:41 PM PDT 24
Peak memory 214456 kb
Host smart-620e4cee-a1ed-4a97-bcc8-5d2c530ee839
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293098383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1293098383
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1069863540
Short name T259
Test name
Test status
Simulation time 151317934 ps
CPU time 3.12 seconds
Started May 12 02:10:37 PM PDT 24
Finished May 12 02:10:40 PM PDT 24
Peak memory 214460 kb
Host smart-628ec9e5-f327-4582-b19c-a12be32b0486
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069863540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1069863540
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2677544855
Short name T898
Test name
Test status
Simulation time 31274464 ps
CPU time 1.92 seconds
Started May 12 02:10:38 PM PDT 24
Finished May 12 02:10:41 PM PDT 24
Peak memory 214752 kb
Host smart-6e502447-05b0-4c47-b1fb-e37a1194fff3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677544855 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2677544855
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1189444027
Short name T877
Test name
Test status
Simulation time 14796632 ps
CPU time 0.92 seconds
Started May 12 02:10:42 PM PDT 24
Finished May 12 02:10:43 PM PDT 24
Peak memory 206248 kb
Host smart-159390c8-7994-4bdb-8798-590e5b38d14d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189444027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1189444027
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1409414646
Short name T959
Test name
Test status
Simulation time 36111632 ps
CPU time 0.8 seconds
Started May 12 02:10:38 PM PDT 24
Finished May 12 02:10:39 PM PDT 24
Peak memory 205880 kb
Host smart-2bbb94e3-4465-417e-8d3b-ef53bc903c7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409414646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1409414646
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.615017801
Short name T226
Test name
Test status
Simulation time 29324187 ps
CPU time 1.14 seconds
Started May 12 02:10:37 PM PDT 24
Finished May 12 02:10:39 PM PDT 24
Peak memory 206324 kb
Host smart-d25955ed-8159-45e4-9ef7-87d071234d01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615017801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_out
standing.615017801
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1923374425
Short name T870
Test name
Test status
Simulation time 93402733 ps
CPU time 2.06 seconds
Started May 12 02:10:35 PM PDT 24
Finished May 12 02:10:38 PM PDT 24
Peak memory 214504 kb
Host smart-9495b797-a603-4333-9148-923e92a40436
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923374425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1923374425
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1134764038
Short name T264
Test name
Test status
Simulation time 55227781 ps
CPU time 1.57 seconds
Started May 12 02:10:40 PM PDT 24
Finished May 12 02:10:43 PM PDT 24
Peak memory 206236 kb
Host smart-41385d6e-e035-460d-aa09-3dfaf679a17d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134764038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1134764038
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3753541965
Short name T887
Test name
Test status
Simulation time 34718263 ps
CPU time 1.16 seconds
Started May 12 02:10:39 PM PDT 24
Finished May 12 02:10:41 PM PDT 24
Peak memory 216576 kb
Host smart-807044f3-179e-4252-affe-751afb67982c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753541965 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3753541965
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3075792739
Short name T243
Test name
Test status
Simulation time 14334400 ps
CPU time 0.89 seconds
Started May 12 02:10:36 PM PDT 24
Finished May 12 02:10:37 PM PDT 24
Peak memory 206260 kb
Host smart-ba5328b7-6b32-446a-b021-293081278afc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075792739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3075792739
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.578693294
Short name T895
Test name
Test status
Simulation time 215488748 ps
CPU time 0.88 seconds
Started May 12 02:10:37 PM PDT 24
Finished May 12 02:10:39 PM PDT 24
Peak memory 206120 kb
Host smart-a003be98-ee21-4dda-91c2-89ea86f935a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578693294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.578693294
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2264962749
Short name T234
Test name
Test status
Simulation time 15427536 ps
CPU time 1.02 seconds
Started May 12 02:10:39 PM PDT 24
Finished May 12 02:10:41 PM PDT 24
Peak memory 206228 kb
Host smart-0ad62ee5-2f43-4f2b-9a5b-7e4ed251bb20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264962749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2264962749
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1430706283
Short name T920
Test name
Test status
Simulation time 118803289 ps
CPU time 4.06 seconds
Started May 12 02:10:40 PM PDT 24
Finished May 12 02:10:45 PM PDT 24
Peak memory 214568 kb
Host smart-b75cd0a4-9fa0-4afb-8dd1-cb64b993b86f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430706283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1430706283
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/default/0.edn_alert_test.206341787
Short name T433
Test name
Test status
Simulation time 21388295 ps
CPU time 0.83 seconds
Started May 12 02:12:11 PM PDT 24
Finished May 12 02:12:13 PM PDT 24
Peak memory 206736 kb
Host smart-c00903ce-4ef2-4157-b001-9def7c516760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206341787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.206341787
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.2611432026
Short name T162
Test name
Test status
Simulation time 35041219 ps
CPU time 0.79 seconds
Started May 12 02:12:07 PM PDT 24
Finished May 12 02:12:09 PM PDT 24
Peak memory 216080 kb
Host smart-289db85a-2ad3-4107-aac7-254ff25fa1bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611432026 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2611432026
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1492481904
Short name T157
Test name
Test status
Simulation time 36653167 ps
CPU time 1.11 seconds
Started May 12 02:12:16 PM PDT 24
Finished May 12 02:12:17 PM PDT 24
Peak memory 219320 kb
Host smart-e3a71f95-bbd6-4e7f-892e-85a131584982
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492481904 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1492481904
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.972437412
Short name T291
Test name
Test status
Simulation time 23293685 ps
CPU time 1.15 seconds
Started May 12 02:12:10 PM PDT 24
Finished May 12 02:12:12 PM PDT 24
Peak memory 218584 kb
Host smart-ea08b7c0-fa02-42cd-8620-6d83a03690cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972437412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.972437412
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1607021812
Short name T727
Test name
Test status
Simulation time 79042074 ps
CPU time 1.21 seconds
Started May 12 02:12:14 PM PDT 24
Finished May 12 02:12:16 PM PDT 24
Peak memory 218416 kb
Host smart-9fd17125-b8ef-4e18-99cb-dce4ee47d509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607021812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1607021812
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.3955264306
Short name T641
Test name
Test status
Simulation time 20483493 ps
CPU time 1.11 seconds
Started May 12 02:12:11 PM PDT 24
Finished May 12 02:12:13 PM PDT 24
Peak memory 216668 kb
Host smart-0d284db2-8c22-4949-8020-f6ae271ae961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955264306 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3955264306
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.3803944864
Short name T298
Test name
Test status
Simulation time 34561387 ps
CPU time 0.88 seconds
Started May 12 02:12:10 PM PDT 24
Finished May 12 02:12:12 PM PDT 24
Peak memory 206972 kb
Host smart-91a311c7-8577-4532-9d1b-5f20e9939e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803944864 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3803944864
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2749009596
Short name T15
Test name
Test status
Simulation time 1980248157 ps
CPU time 7.21 seconds
Started May 12 02:12:12 PM PDT 24
Finished May 12 02:12:20 PM PDT 24
Peak memory 237004 kb
Host smart-35d3ef81-fde0-45e8-bd87-efce4b8725be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749009596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2749009596
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2696258071
Short name T503
Test name
Test status
Simulation time 17168480 ps
CPU time 0.99 seconds
Started May 12 02:12:13 PM PDT 24
Finished May 12 02:12:14 PM PDT 24
Peak memory 215136 kb
Host smart-90031352-7baa-4f79-b997-7f020bb98468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696258071 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2696258071
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3789581425
Short name T550
Test name
Test status
Simulation time 571806608 ps
CPU time 5.89 seconds
Started May 12 02:12:16 PM PDT 24
Finished May 12 02:12:22 PM PDT 24
Peak memory 215140 kb
Host smart-de507938-e6bb-4d57-abbc-5a7d0d0844b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789581425 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3789581425
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3819515648
Short name T737
Test name
Test status
Simulation time 163195999222 ps
CPU time 1108.1 seconds
Started May 12 02:12:10 PM PDT 24
Finished May 12 02:30:39 PM PDT 24
Peak memory 223352 kb
Host smart-fb4b923f-4ba6-4f50-83c4-cb2841f22551
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819515648 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3819515648
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.611880878
Short name T611
Test name
Test status
Simulation time 37738188 ps
CPU time 0.97 seconds
Started May 12 02:12:45 PM PDT 24
Finished May 12 02:12:47 PM PDT 24
Peak memory 214696 kb
Host smart-f2f2df71-1f77-4c81-9d13-8ef46c956f53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611880878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.611880878
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.2692926280
Short name T95
Test name
Test status
Simulation time 28395996 ps
CPU time 0.84 seconds
Started May 12 02:12:37 PM PDT 24
Finished May 12 02:12:39 PM PDT 24
Peak memory 216048 kb
Host smart-301f7f8b-2934-4ad1-9a2a-f75cfdd0e117
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692926280 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2692926280
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.3975809609
Short name T331
Test name
Test status
Simulation time 19548162 ps
CPU time 1.06 seconds
Started May 12 02:12:20 PM PDT 24
Finished May 12 02:12:21 PM PDT 24
Peak memory 218428 kb
Host smart-2e2e10db-6f5c-47c0-96d3-db58aa2ad006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975809609 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3975809609
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3720653784
Short name T539
Test name
Test status
Simulation time 91090439 ps
CPU time 1.62 seconds
Started May 12 02:12:39 PM PDT 24
Finished May 12 02:12:41 PM PDT 24
Peak memory 218504 kb
Host smart-292376c1-f003-4b7e-8542-f783a8b28954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720653784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3720653784
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.779974426
Short name T715
Test name
Test status
Simulation time 21979689 ps
CPU time 1.05 seconds
Started May 12 02:12:37 PM PDT 24
Finished May 12 02:12:39 PM PDT 24
Peak memory 215596 kb
Host smart-a8e47a96-69a7-4192-958b-f91992ca60aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779974426 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.779974426
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_smoke.861946410
Short name T453
Test name
Test status
Simulation time 17809503 ps
CPU time 0.99 seconds
Started May 12 02:12:16 PM PDT 24
Finished May 12 02:12:17 PM PDT 24
Peak memory 215168 kb
Host smart-31a5095b-932c-4fc1-82f9-85fd643cd667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861946410 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.861946410
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.242471392
Short name T597
Test name
Test status
Simulation time 181308106 ps
CPU time 3.64 seconds
Started May 12 02:12:37 PM PDT 24
Finished May 12 02:12:41 PM PDT 24
Peak memory 216720 kb
Host smart-c986d0b5-c910-499b-af9d-04c875eadb22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242471392 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.242471392
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2916277714
Short name T425
Test name
Test status
Simulation time 107553973385 ps
CPU time 754.86 seconds
Started May 12 02:12:39 PM PDT 24
Finished May 12 02:25:15 PM PDT 24
Peak memory 222008 kb
Host smart-b82fd5ba-6479-4091-b0be-e444891146b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916277714 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2916277714
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1195022260
Short name T841
Test name
Test status
Simulation time 33697366 ps
CPU time 1.24 seconds
Started May 12 02:12:50 PM PDT 24
Finished May 12 02:12:53 PM PDT 24
Peak memory 215508 kb
Host smart-dc829dd5-28b2-4939-ad86-28ef7d02c3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195022260 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1195022260
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2062666982
Short name T754
Test name
Test status
Simulation time 18440289 ps
CPU time 0.98 seconds
Started May 12 02:12:46 PM PDT 24
Finished May 12 02:12:49 PM PDT 24
Peak memory 206712 kb
Host smart-10f7901e-a140-4c46-972c-c01433af61e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062666982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2062666982
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.2211608041
Short name T644
Test name
Test status
Simulation time 39067513 ps
CPU time 0.88 seconds
Started May 12 02:12:46 PM PDT 24
Finished May 12 02:12:48 PM PDT 24
Peak memory 215252 kb
Host smart-a6cb7637-b8f7-460e-a10d-d7ddc5cc7f68
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211608041 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2211608041
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.1765176052
Short name T163
Test name
Test status
Simulation time 43154457 ps
CPU time 1.1 seconds
Started May 12 02:12:50 PM PDT 24
Finished May 12 02:12:53 PM PDT 24
Peak memory 219440 kb
Host smart-ba169fbe-0bb6-4635-9c14-c7f30eaedb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765176052 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1765176052
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2226956081
Short name T385
Test name
Test status
Simulation time 161722825 ps
CPU time 1.44 seconds
Started May 12 02:12:45 PM PDT 24
Finished May 12 02:12:47 PM PDT 24
Peak memory 216940 kb
Host smart-8463afab-3729-4674-8d46-6a700411ea2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226956081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2226956081
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.2339099283
Short name T615
Test name
Test status
Simulation time 22474644 ps
CPU time 1.15 seconds
Started May 12 02:12:51 PM PDT 24
Finished May 12 02:12:54 PM PDT 24
Peak memory 215272 kb
Host smart-3696e80c-b267-40b6-8f41-721af719e1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339099283 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2339099283
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3778534985
Short name T317
Test name
Test status
Simulation time 15832160 ps
CPU time 0.93 seconds
Started May 12 02:12:50 PM PDT 24
Finished May 12 02:12:53 PM PDT 24
Peak memory 206956 kb
Host smart-1c4442d8-9cd0-4c85-9ef6-bf74c3e06373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778534985 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3778534985
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3496920174
Short name T419
Test name
Test status
Simulation time 34570006 ps
CPU time 1.25 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:52 PM PDT 24
Peak memory 216672 kb
Host smart-b6ed8b19-a9d7-47d7-8678-2e8f778a883f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496920174 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3496920174
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.75954023
Short name T723
Test name
Test status
Simulation time 116880001062 ps
CPU time 455.76 seconds
Started May 12 02:12:47 PM PDT 24
Finished May 12 02:20:25 PM PDT 24
Peak memory 221488 kb
Host smart-9adfce2b-4460-46ea-9b25-ac5b35d1b698
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75954023 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.75954023
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.2314786081
Short name T361
Test name
Test status
Simulation time 151675991 ps
CPU time 1.17 seconds
Started May 12 02:14:08 PM PDT 24
Finished May 12 02:14:11 PM PDT 24
Peak memory 216728 kb
Host smart-14e6b72d-f6c2-48ea-8f6d-fe225f362459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314786081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2314786081
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.3439190286
Short name T363
Test name
Test status
Simulation time 59556813 ps
CPU time 1.28 seconds
Started May 12 02:14:03 PM PDT 24
Finished May 12 02:14:06 PM PDT 24
Peak memory 218324 kb
Host smart-205071ce-782a-4b88-8931-e24b23a40207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439190286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3439190286
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.573620811
Short name T133
Test name
Test status
Simulation time 261865110 ps
CPU time 3.49 seconds
Started May 12 02:14:03 PM PDT 24
Finished May 12 02:14:07 PM PDT 24
Peak memory 220000 kb
Host smart-8015fb27-774b-4d8a-9e03-74eab9f0f74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573620811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.573620811
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.1323393920
Short name T834
Test name
Test status
Simulation time 95678068 ps
CPU time 1.22 seconds
Started May 12 02:14:09 PM PDT 24
Finished May 12 02:14:12 PM PDT 24
Peak memory 216968 kb
Host smart-3def51b8-9458-497d-9d50-e8d6c32cf2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323393920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1323393920
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.3358089946
Short name T581
Test name
Test status
Simulation time 30937170 ps
CPU time 1.27 seconds
Started May 12 02:14:04 PM PDT 24
Finished May 12 02:14:06 PM PDT 24
Peak memory 216768 kb
Host smart-e411a773-fef4-480d-a96a-612b4a80301c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358089946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3358089946
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1729124444
Short name T780
Test name
Test status
Simulation time 31012074 ps
CPU time 1.31 seconds
Started May 12 02:14:10 PM PDT 24
Finished May 12 02:14:13 PM PDT 24
Peak memory 216920 kb
Host smart-9d0b4d29-c3f0-4ffe-9b0d-7ab117901f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729124444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1729124444
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1313583496
Short name T512
Test name
Test status
Simulation time 176265656 ps
CPU time 1.05 seconds
Started May 12 02:14:02 PM PDT 24
Finished May 12 02:14:04 PM PDT 24
Peak memory 216836 kb
Host smart-6753137e-db7c-43a2-8457-adc93c86547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313583496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1313583496
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.2541789118
Short name T318
Test name
Test status
Simulation time 90160935 ps
CPU time 1.2 seconds
Started May 12 02:14:02 PM PDT 24
Finished May 12 02:14:05 PM PDT 24
Peak memory 216848 kb
Host smart-48ce8458-b016-421a-a210-1820e40f578f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541789118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2541789118
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.1977667636
Short name T482
Test name
Test status
Simulation time 48473056 ps
CPU time 1.54 seconds
Started May 12 02:14:05 PM PDT 24
Finished May 12 02:14:08 PM PDT 24
Peak memory 218208 kb
Host smart-b6121d0c-0a6f-4b4c-93b8-56bfed154c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977667636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1977667636
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.370438898
Short name T295
Test name
Test status
Simulation time 37484431 ps
CPU time 1.15 seconds
Started May 12 02:12:46 PM PDT 24
Finished May 12 02:12:49 PM PDT 24
Peak memory 215532 kb
Host smart-a22b4c5d-8156-4b84-b614-0b9fbf98d65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370438898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.370438898
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3117171085
Short name T414
Test name
Test status
Simulation time 96313999 ps
CPU time 1.11 seconds
Started May 12 02:12:49 PM PDT 24
Finished May 12 02:12:52 PM PDT 24
Peak memory 206576 kb
Host smart-657b5a40-db04-4f02-9e39-30433cf29793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117171085 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3117171085
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.2182815869
Short name T182
Test name
Test status
Simulation time 45727735 ps
CPU time 0.89 seconds
Started May 12 02:12:47 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 216252 kb
Host smart-4377ed19-bc9a-4e9c-a0e1-ed41d43471ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182815869 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2182815869
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.4191577265
Short name T177
Test name
Test status
Simulation time 32717702 ps
CPU time 1.17 seconds
Started May 12 02:12:51 PM PDT 24
Finished May 12 02:12:54 PM PDT 24
Peak memory 220624 kb
Host smart-e1d66ff7-441f-41e3-8ad8-2d0d1f5d05d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191577265 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.4191577265
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1134160
Short name T541
Test name
Test status
Simulation time 68113318 ps
CPU time 1.33 seconds
Started May 12 02:12:49 PM PDT 24
Finished May 12 02:12:52 PM PDT 24
Peak memory 216920 kb
Host smart-31ec3763-9354-4cb1-8ffe-1f62c45d5ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1134160
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.503715671
Short name T417
Test name
Test status
Simulation time 33115307 ps
CPU time 0.95 seconds
Started May 12 02:12:49 PM PDT 24
Finished May 12 02:12:52 PM PDT 24
Peak memory 215340 kb
Host smart-9ab6386a-790d-4d40-9da0-6a0c687e1e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503715671 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.503715671
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1336555048
Short name T734
Test name
Test status
Simulation time 58285533 ps
CPU time 0.95 seconds
Started May 12 02:12:49 PM PDT 24
Finished May 12 02:12:53 PM PDT 24
Peak memory 215120 kb
Host smart-9a64a95a-2d0f-4a7f-9cbf-ee9f4ce5d184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336555048 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1336555048
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.3744307017
Short name T554
Test name
Test status
Simulation time 446658942 ps
CPU time 4.72 seconds
Started May 12 02:12:46 PM PDT 24
Finished May 12 02:12:52 PM PDT 24
Peak memory 216760 kb
Host smart-f6607434-39c9-4f0d-902e-3619362502c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744307017 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3744307017
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3141485628
Short name T463
Test name
Test status
Simulation time 93013612973 ps
CPU time 548.7 seconds
Started May 12 02:12:44 PM PDT 24
Finished May 12 02:21:55 PM PDT 24
Peak memory 218884 kb
Host smart-bff1293a-ff69-48c9-a830-f2da2e558ee4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141485628 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3141485628
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.2785987270
Short name T673
Test name
Test status
Simulation time 39024001 ps
CPU time 1.27 seconds
Started May 12 02:14:05 PM PDT 24
Finished May 12 02:14:08 PM PDT 24
Peak memory 216800 kb
Host smart-35f4f302-e443-4d6d-8c7b-e4edeea2e340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785987270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2785987270
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.158544013
Short name T545
Test name
Test status
Simulation time 50917816 ps
CPU time 1.88 seconds
Started May 12 02:14:02 PM PDT 24
Finished May 12 02:14:06 PM PDT 24
Peak memory 218448 kb
Host smart-63122f96-bacb-449e-af1c-e471a8f7a9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158544013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.158544013
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.4268662848
Short name T705
Test name
Test status
Simulation time 321955117 ps
CPU time 1.2 seconds
Started May 12 02:14:08 PM PDT 24
Finished May 12 02:14:11 PM PDT 24
Peak memory 217032 kb
Host smart-492cfeca-8563-4397-99f4-a380d74f40bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268662848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.4268662848
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.4000119032
Short name T498
Test name
Test status
Simulation time 40124074 ps
CPU time 1.18 seconds
Started May 12 02:14:09 PM PDT 24
Finished May 12 02:14:12 PM PDT 24
Peak memory 216748 kb
Host smart-a22230f0-46b4-42cb-8227-f00ea6b3d601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000119032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.4000119032
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.2925921646
Short name T205
Test name
Test status
Simulation time 188825931 ps
CPU time 2.91 seconds
Started May 12 02:14:05 PM PDT 24
Finished May 12 02:14:10 PM PDT 24
Peak memory 219960 kb
Host smart-ee7adc25-5c9f-4dd4-a0b6-ee65b0355286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925921646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2925921646
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.692509407
Short name T844
Test name
Test status
Simulation time 33639811 ps
CPU time 1.4 seconds
Started May 12 02:14:07 PM PDT 24
Finished May 12 02:14:09 PM PDT 24
Peak memory 218140 kb
Host smart-41320edf-0f7e-4ca9-9171-ac4ad91580f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692509407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.692509407
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.2509949918
Short name T518
Test name
Test status
Simulation time 176846998 ps
CPU time 1.7 seconds
Started May 12 02:14:05 PM PDT 24
Finished May 12 02:14:07 PM PDT 24
Peak memory 219656 kb
Host smart-9fdacf9b-f2d7-48fb-9d54-f553af594aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509949918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2509949918
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3082600777
Short name T11
Test name
Test status
Simulation time 39286827 ps
CPU time 1.15 seconds
Started May 12 02:14:08 PM PDT 24
Finished May 12 02:14:10 PM PDT 24
Peak memory 219232 kb
Host smart-8f4a1508-d476-4813-a781-0b32fbc8a786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082600777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3082600777
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1599950422
Short name T817
Test name
Test status
Simulation time 44435955 ps
CPU time 1.25 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 215444 kb
Host smart-fe32a66b-9bc8-4f2a-a463-d589ebf9514e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599950422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1599950422
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3012201909
Short name T534
Test name
Test status
Simulation time 40080327 ps
CPU time 0.88 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 206528 kb
Host smart-43316088-63f0-4d4b-8b93-950a0436899d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012201909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3012201909
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3228119048
Short name T601
Test name
Test status
Simulation time 75860522 ps
CPU time 1.09 seconds
Started May 12 02:12:46 PM PDT 24
Finished May 12 02:12:49 PM PDT 24
Peak memory 216604 kb
Host smart-67672e2c-8002-490f-948b-e3e757ee74fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228119048 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3228119048
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.4091703137
Short name T168
Test name
Test status
Simulation time 74420782 ps
CPU time 1.06 seconds
Started May 12 02:12:53 PM PDT 24
Finished May 12 02:12:55 PM PDT 24
Peak memory 219628 kb
Host smart-0ea7e49f-a3f9-4a67-83c5-83600b597168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091703137 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.4091703137
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2427010116
Short name T819
Test name
Test status
Simulation time 44971798 ps
CPU time 1.42 seconds
Started May 12 02:12:50 PM PDT 24
Finished May 12 02:12:54 PM PDT 24
Peak memory 215164 kb
Host smart-a00e11bb-df42-46ee-a6d8-19a6dbbde2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427010116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2427010116
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3451814212
Short name T605
Test name
Test status
Simulation time 22879808 ps
CPU time 1.08 seconds
Started May 12 02:12:50 PM PDT 24
Finished May 12 02:12:53 PM PDT 24
Peak memory 215208 kb
Host smart-e4cf10a5-73d8-4702-bb28-59fd73d462f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451814212 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3451814212
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2606458022
Short name T783
Test name
Test status
Simulation time 18245799 ps
CPU time 1.02 seconds
Started May 12 02:12:51 PM PDT 24
Finished May 12 02:12:54 PM PDT 24
Peak memory 215140 kb
Host smart-f60bff36-18e0-48cb-af05-72656b3c2510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606458022 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2606458022
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1574756851
Short name T212
Test name
Test status
Simulation time 152439417 ps
CPU time 3.33 seconds
Started May 12 02:12:52 PM PDT 24
Finished May 12 02:12:57 PM PDT 24
Peak memory 215048 kb
Host smart-70974a4c-278a-45a8-badc-2daac8942132
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574756851 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1574756851
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.878816902
Short name T148
Test name
Test status
Simulation time 205904472306 ps
CPU time 1082.53 seconds
Started May 12 02:12:50 PM PDT 24
Finished May 12 02:30:55 PM PDT 24
Peak memory 224148 kb
Host smart-12ee6387-c84c-4d49-8bb1-0fa0094fe97c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878816902 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.878816902
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.1198284356
Short name T781
Test name
Test status
Simulation time 48907518 ps
CPU time 1.52 seconds
Started May 12 02:14:05 PM PDT 24
Finished May 12 02:14:08 PM PDT 24
Peak memory 219088 kb
Host smart-0c1ccc85-5eeb-4c02-ae08-6077821eaa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198284356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1198284356
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.1753529603
Short name T624
Test name
Test status
Simulation time 41595885 ps
CPU time 1.44 seconds
Started May 12 02:14:15 PM PDT 24
Finished May 12 02:14:17 PM PDT 24
Peak memory 216768 kb
Host smart-2fa8dc6d-7d09-4236-b3fd-9bb9a06b06e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753529603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1753529603
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.2706890051
Short name T577
Test name
Test status
Simulation time 72805926 ps
CPU time 1.58 seconds
Started May 12 02:14:09 PM PDT 24
Finished May 12 02:14:13 PM PDT 24
Peak memory 218188 kb
Host smart-6e9ca23a-2ae0-4da0-8411-e203810a604c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706890051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2706890051
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2732537007
Short name T504
Test name
Test status
Simulation time 63358520 ps
CPU time 1.55 seconds
Started May 12 02:14:06 PM PDT 24
Finished May 12 02:14:09 PM PDT 24
Peak memory 218292 kb
Host smart-5b13e04e-1c98-4492-acae-faf80221e3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732537007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2732537007
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.4003902425
Short name T684
Test name
Test status
Simulation time 81119623 ps
CPU time 1.18 seconds
Started May 12 02:14:07 PM PDT 24
Finished May 12 02:14:09 PM PDT 24
Peak memory 219124 kb
Host smart-b0f15a51-23e6-4b9b-b45e-e950b552c79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003902425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.4003902425
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3564416507
Short name T698
Test name
Test status
Simulation time 59562738 ps
CPU time 1.19 seconds
Started May 12 02:14:09 PM PDT 24
Finished May 12 02:14:12 PM PDT 24
Peak memory 216924 kb
Host smart-eeef28ea-7cb9-4637-aebb-f9f0a7b4f58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564416507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3564416507
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.3940078026
Short name T634
Test name
Test status
Simulation time 43353080 ps
CPU time 1.66 seconds
Started May 12 02:14:06 PM PDT 24
Finished May 12 02:14:09 PM PDT 24
Peak memory 217912 kb
Host smart-007fe7ba-3bf7-434f-8b06-18bbdb9ac71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940078026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3940078026
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.1763704030
Short name T728
Test name
Test status
Simulation time 41278165 ps
CPU time 1.55 seconds
Started May 12 02:14:07 PM PDT 24
Finished May 12 02:14:09 PM PDT 24
Peak memory 219896 kb
Host smart-bb3ace01-c92c-43a2-83e0-b3e9b1f4a232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763704030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1763704030
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.2756232297
Short name T381
Test name
Test status
Simulation time 48037006 ps
CPU time 0.91 seconds
Started May 12 02:12:49 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 214708 kb
Host smart-a1b972f1-c4d2-4244-b8e3-cafefb141d73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756232297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2756232297
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.4283711792
Short name T408
Test name
Test status
Simulation time 182785168 ps
CPU time 1.09 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 216548 kb
Host smart-53120315-631d-4b37-9460-5b6ea876c9bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283711792 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.4283711792
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3799232282
Short name T82
Test name
Test status
Simulation time 53344661 ps
CPU time 0.88 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 218080 kb
Host smart-a35eb832-caf9-472b-afed-86f543f820ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799232282 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3799232282
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2251929867
Short name T786
Test name
Test status
Simulation time 36667808 ps
CPU time 1.58 seconds
Started May 12 02:12:53 PM PDT 24
Finished May 12 02:12:56 PM PDT 24
Peak memory 216924 kb
Host smart-2e20d108-2799-443f-ba42-7f6209ec2760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251929867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2251929867
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1923420518
Short name T119
Test name
Test status
Simulation time 36471281 ps
CPU time 1.01 seconds
Started May 12 02:12:52 PM PDT 24
Finished May 12 02:12:55 PM PDT 24
Peak memory 223576 kb
Host smart-79fee984-22e5-4d24-b06e-955ac8276d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923420518 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1923420518
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.3473331613
Short name T678
Test name
Test status
Simulation time 24456372 ps
CPU time 0.94 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 215176 kb
Host smart-8afee1cf-9e74-41b0-ad4f-fc6f15c5bd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473331613 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3473331613
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1576716805
Short name T528
Test name
Test status
Simulation time 45002849 ps
CPU time 1.39 seconds
Started May 12 02:12:53 PM PDT 24
Finished May 12 02:12:56 PM PDT 24
Peak memory 215124 kb
Host smart-1e7b9375-5412-40cd-92ae-572fdba09bcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576716805 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1576716805
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/130.edn_genbits.1063314786
Short name T827
Test name
Test status
Simulation time 47949082 ps
CPU time 1.32 seconds
Started May 12 02:14:05 PM PDT 24
Finished May 12 02:14:08 PM PDT 24
Peak memory 218132 kb
Host smart-3a680516-ab35-45d1-a611-b9825c874892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063314786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1063314786
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1941048147
Short name T471
Test name
Test status
Simulation time 77014590 ps
CPU time 1.19 seconds
Started May 12 02:14:10 PM PDT 24
Finished May 12 02:14:13 PM PDT 24
Peak memory 217180 kb
Host smart-d5d64172-2fbb-4967-9466-788755dd4170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941048147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1941048147
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.3629097195
Short name T305
Test name
Test status
Simulation time 30405518 ps
CPU time 1.41 seconds
Started May 12 02:14:06 PM PDT 24
Finished May 12 02:14:09 PM PDT 24
Peak memory 216872 kb
Host smart-c6bc1b56-2927-4993-8356-d7b89b87f104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629097195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3629097195
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3447518293
Short name T325
Test name
Test status
Simulation time 124049967 ps
CPU time 1.21 seconds
Started May 12 02:14:10 PM PDT 24
Finished May 12 02:14:13 PM PDT 24
Peak memory 216824 kb
Host smart-b29430cc-76a4-47c1-a545-8b17147f35fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447518293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3447518293
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.1456791864
Short name T839
Test name
Test status
Simulation time 77600543 ps
CPU time 1.2 seconds
Started May 12 02:14:06 PM PDT 24
Finished May 12 02:14:08 PM PDT 24
Peak memory 216896 kb
Host smart-e31934ef-e7ad-445a-ae7e-deaf8f6aeb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456791864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1456791864
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.1868111574
Short name T329
Test name
Test status
Simulation time 138210480 ps
CPU time 1.47 seconds
Started May 12 02:14:11 PM PDT 24
Finished May 12 02:14:14 PM PDT 24
Peak memory 218360 kb
Host smart-603d4f63-8eea-4c5c-a594-e184b87d411c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868111574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1868111574
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.332555409
Short name T128
Test name
Test status
Simulation time 36449312 ps
CPU time 1.37 seconds
Started May 12 02:14:06 PM PDT 24
Finished May 12 02:14:09 PM PDT 24
Peak memory 218024 kb
Host smart-eb89825e-7bac-4454-b5fd-90edff7a6849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332555409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.332555409
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2809726000
Short name T384
Test name
Test status
Simulation time 131155422 ps
CPU time 3.21 seconds
Started May 12 02:14:04 PM PDT 24
Finished May 12 02:14:09 PM PDT 24
Peak memory 219796 kb
Host smart-7af86dd7-795a-4d22-a874-da1b2dfa8fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809726000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2809726000
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.34465356
Short name T383
Test name
Test status
Simulation time 119902152 ps
CPU time 1.4 seconds
Started May 12 02:14:07 PM PDT 24
Finished May 12 02:14:09 PM PDT 24
Peak memory 218268 kb
Host smart-018025bf-e70b-4253-975a-3cc36edbb31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34465356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.34465356
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert_test.1856869794
Short name T352
Test name
Test status
Simulation time 30974189 ps
CPU time 1.05 seconds
Started May 12 02:12:53 PM PDT 24
Finished May 12 02:12:56 PM PDT 24
Peak memory 214724 kb
Host smart-f3d5209a-d88e-4968-b410-d90e7f251067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856869794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1856869794
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.4043227461
Short name T43
Test name
Test status
Simulation time 40084764 ps
CPU time 1.31 seconds
Started May 12 02:12:53 PM PDT 24
Finished May 12 02:12:56 PM PDT 24
Peak memory 216524 kb
Host smart-c4903f9f-0134-490c-ba14-d69934920c25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043227461 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.4043227461
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_genbits.2746366324
Short name T540
Test name
Test status
Simulation time 34654893 ps
CPU time 1.38 seconds
Started May 12 02:12:53 PM PDT 24
Finished May 12 02:12:56 PM PDT 24
Peak memory 218136 kb
Host smart-26a56dd6-d0dc-4db0-9bca-ae047eeb3460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746366324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2746366324
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.4252204203
Short name T337
Test name
Test status
Simulation time 15260389 ps
CPU time 0.99 seconds
Started May 12 02:12:53 PM PDT 24
Finished May 12 02:12:55 PM PDT 24
Peak memory 215128 kb
Host smart-03ed6403-f4e3-4a2f-b228-1aa388aa7905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252204203 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.4252204203
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.4072327559
Short name T326
Test name
Test status
Simulation time 294889609 ps
CPU time 5.98 seconds
Started May 12 02:12:53 PM PDT 24
Finished May 12 02:13:01 PM PDT 24
Peak memory 215064 kb
Host smart-37f794e3-648c-4179-9c8c-8231d64cd370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072327559 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.4072327559
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.321921510
Short name T194
Test name
Test status
Simulation time 141978823659 ps
CPU time 767.43 seconds
Started May 12 02:12:51 PM PDT 24
Finished May 12 02:25:40 PM PDT 24
Peak memory 219680 kb
Host smart-36b1d8e2-4ad0-4ea1-949a-59bb00c0f009
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321921510 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.321921510
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.2333805359
Short name T664
Test name
Test status
Simulation time 33766497 ps
CPU time 1.33 seconds
Started May 12 02:14:06 PM PDT 24
Finished May 12 02:14:08 PM PDT 24
Peak memory 219448 kb
Host smart-245d283a-d6c5-415c-98f7-fd17ceb90bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333805359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2333805359
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.3030344674
Short name T275
Test name
Test status
Simulation time 56742497 ps
CPU time 1.36 seconds
Started May 12 02:14:09 PM PDT 24
Finished May 12 02:14:12 PM PDT 24
Peak memory 218132 kb
Host smart-b4e31294-3d28-4dbe-bf8b-2917216d71e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030344674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3030344674
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.231813026
Short name T744
Test name
Test status
Simulation time 24073176 ps
CPU time 1.14 seconds
Started May 12 02:14:08 PM PDT 24
Finished May 12 02:14:10 PM PDT 24
Peak memory 217012 kb
Host smart-d23c7816-c55d-4f47-b411-ae085853593c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231813026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.231813026
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.1295102265
Short name T387
Test name
Test status
Simulation time 69242525 ps
CPU time 1.31 seconds
Started May 12 02:14:06 PM PDT 24
Finished May 12 02:14:09 PM PDT 24
Peak memory 218168 kb
Host smart-89c057c8-7993-4c19-a3ee-ed155c46b564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295102265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1295102265
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.914417212
Short name T362
Test name
Test status
Simulation time 69451442 ps
CPU time 1.11 seconds
Started May 12 02:14:10 PM PDT 24
Finished May 12 02:14:13 PM PDT 24
Peak memory 216712 kb
Host smart-b3454c16-cb97-4c33-af95-ca94bc87961c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914417212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.914417212
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.2638068361
Short name T690
Test name
Test status
Simulation time 47929802 ps
CPU time 1.2 seconds
Started May 12 02:14:12 PM PDT 24
Finished May 12 02:14:14 PM PDT 24
Peak memory 216928 kb
Host smart-c71ebf60-615a-4e54-89da-4fececedfe4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638068361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2638068361
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1812861770
Short name T679
Test name
Test status
Simulation time 52650684 ps
CPU time 0.94 seconds
Started May 12 02:14:05 PM PDT 24
Finished May 12 02:14:08 PM PDT 24
Peak memory 216840 kb
Host smart-0f7a264e-4955-4cc9-bd2d-7dd2fbf35acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812861770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1812861770
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.4163262230
Short name T700
Test name
Test status
Simulation time 55304328 ps
CPU time 1.31 seconds
Started May 12 02:14:12 PM PDT 24
Finished May 12 02:14:15 PM PDT 24
Peak memory 219508 kb
Host smart-3b824c46-4c6a-4687-be9f-c3846a42ed20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163262230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.4163262230
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.2099254981
Short name T810
Test name
Test status
Simulation time 205339409 ps
CPU time 1.45 seconds
Started May 12 02:14:12 PM PDT 24
Finished May 12 02:14:15 PM PDT 24
Peak memory 218824 kb
Host smart-06864ddd-a7e2-4ce8-a6dc-d8911386372d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099254981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2099254981
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.3577264682
Short name T315
Test name
Test status
Simulation time 127896723 ps
CPU time 3.06 seconds
Started May 12 02:14:05 PM PDT 24
Finished May 12 02:14:10 PM PDT 24
Peak memory 219852 kb
Host smart-5e386cd2-6b69-4454-9196-68fca0e3ca16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577264682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3577264682
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3395087334
Short name T774
Test name
Test status
Simulation time 92964622 ps
CPU time 1.28 seconds
Started May 12 02:12:51 PM PDT 24
Finished May 12 02:12:54 PM PDT 24
Peak memory 215436 kb
Host smart-9d00a471-6481-4fc9-b8c6-6d6b7522074f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395087334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3395087334
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.4088587128
Short name T796
Test name
Test status
Simulation time 24405339 ps
CPU time 0.88 seconds
Started May 12 02:12:49 PM PDT 24
Finished May 12 02:12:52 PM PDT 24
Peak memory 206700 kb
Host smart-4ff9a5fb-2bc3-4aa8-b539-0667730160e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088587128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.4088587128
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1440248878
Short name T838
Test name
Test status
Simulation time 30177623 ps
CPU time 0.82 seconds
Started May 12 02:12:56 PM PDT 24
Finished May 12 02:12:58 PM PDT 24
Peak memory 215776 kb
Host smart-91b10b90-0a08-4775-933d-dbbd5755018f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440248878 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1440248878
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1458581961
Short name T487
Test name
Test status
Simulation time 94208905 ps
CPU time 1.09 seconds
Started May 12 02:12:52 PM PDT 24
Finished May 12 02:12:54 PM PDT 24
Peak memory 216660 kb
Host smart-2cd50f3f-c674-4f69-8bd8-8019bf3d72de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458581961 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1458581961
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2806224154
Short name T489
Test name
Test status
Simulation time 29995702 ps
CPU time 1.08 seconds
Started May 12 02:12:53 PM PDT 24
Finished May 12 02:12:56 PM PDT 24
Peak memory 218408 kb
Host smart-f6f44cdb-8ca3-4fdf-87d3-b0c0c1e99431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806224154 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2806224154
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3946525840
Short name T712
Test name
Test status
Simulation time 84663586 ps
CPU time 1.57 seconds
Started May 12 02:12:52 PM PDT 24
Finished May 12 02:12:56 PM PDT 24
Peak memory 219080 kb
Host smart-1dfefc69-f5a3-40bb-a429-03a6239bcfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946525840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3946525840
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.3556494627
Short name T671
Test name
Test status
Simulation time 22865264 ps
CPU time 0.91 seconds
Started May 12 02:12:47 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 215088 kb
Host smart-0ae39015-8163-4c80-aa1d-3d382dd0441a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556494627 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3556494627
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2481598390
Short name T469
Test name
Test status
Simulation time 154954320 ps
CPU time 2.02 seconds
Started May 12 02:12:55 PM PDT 24
Finished May 12 02:12:59 PM PDT 24
Peak memory 216736 kb
Host smart-df763b71-302d-4c5b-adbe-e79124b07c0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481598390 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2481598390
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/150.edn_genbits.3295616518
Short name T826
Test name
Test status
Simulation time 57272490 ps
CPU time 1.42 seconds
Started May 12 02:14:07 PM PDT 24
Finished May 12 02:14:09 PM PDT 24
Peak memory 217920 kb
Host smart-1139c5b4-89ab-4c5e-b51c-12c96bff1186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295616518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3295616518
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.1521990515
Short name T358
Test name
Test status
Simulation time 79476485 ps
CPU time 2.62 seconds
Started May 12 02:14:10 PM PDT 24
Finished May 12 02:14:14 PM PDT 24
Peak memory 219652 kb
Host smart-0e53f875-f3ab-45d0-95f1-f91e86b9f6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521990515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1521990515
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.897923325
Short name T629
Test name
Test status
Simulation time 76825895 ps
CPU time 1.19 seconds
Started May 12 02:14:10 PM PDT 24
Finished May 12 02:14:13 PM PDT 24
Peak memory 218200 kb
Host smart-80949f39-2bfc-46b5-a977-3fcc92a39781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897923325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.897923325
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.313502956
Short name T207
Test name
Test status
Simulation time 22522726 ps
CPU time 1.22 seconds
Started May 12 02:14:14 PM PDT 24
Finished May 12 02:14:15 PM PDT 24
Peak memory 219444 kb
Host smart-cb509d8d-9170-408d-a0b7-5e8c2d59ac74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313502956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.313502956
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.2889441771
Short name T642
Test name
Test status
Simulation time 67616552 ps
CPU time 1.01 seconds
Started May 12 02:14:08 PM PDT 24
Finished May 12 02:14:10 PM PDT 24
Peak memory 216868 kb
Host smart-4fc6b457-91cf-430e-8757-6358be218219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889441771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2889441771
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.506902164
Short name T808
Test name
Test status
Simulation time 6613544662 ps
CPU time 87.97 seconds
Started May 12 02:14:13 PM PDT 24
Finished May 12 02:15:42 PM PDT 24
Peak memory 217200 kb
Host smart-f0c47668-af4f-4e89-9811-67bb1e96c1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506902164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.506902164
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.2515727613
Short name T537
Test name
Test status
Simulation time 94392836 ps
CPU time 1.19 seconds
Started May 12 02:14:08 PM PDT 24
Finished May 12 02:14:11 PM PDT 24
Peak memory 217040 kb
Host smart-162b3da0-5225-4f0c-920b-f09fcd6e63d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515727613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2515727613
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2734795167
Short name T436
Test name
Test status
Simulation time 271529973 ps
CPU time 3.07 seconds
Started May 12 02:14:13 PM PDT 24
Finished May 12 02:14:17 PM PDT 24
Peak memory 219032 kb
Host smart-b491770c-9517-4a30-b4cf-8a3ba1520142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734795167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2734795167
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.109528534
Short name T135
Test name
Test status
Simulation time 41147011 ps
CPU time 1.46 seconds
Started May 12 02:14:13 PM PDT 24
Finished May 12 02:14:15 PM PDT 24
Peak memory 216996 kb
Host smart-7af31b5a-ad69-442b-a39a-8e5e1075bd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109528534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.109528534
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1893556803
Short name T303
Test name
Test status
Simulation time 40785147 ps
CPU time 1.13 seconds
Started May 12 02:12:50 PM PDT 24
Finished May 12 02:12:53 PM PDT 24
Peak memory 215476 kb
Host smart-94b5ff1c-cc05-45c5-9c04-f44f0331a2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893556803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1893556803
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable.309632274
Short name T544
Test name
Test status
Simulation time 42636257 ps
CPU time 0.8 seconds
Started May 12 02:12:56 PM PDT 24
Finished May 12 02:12:58 PM PDT 24
Peak memory 216132 kb
Host smart-a3a22400-4af2-46ba-b4fe-b6a5b9c1fa1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309632274 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.309632274
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.2697414199
Short name T353
Test name
Test status
Simulation time 36388842 ps
CPU time 0.94 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 223708 kb
Host smart-ad7c6a50-bf95-47b8-81e4-fe56d3e4e254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697414199 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2697414199
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_intr.3352245386
Short name T542
Test name
Test status
Simulation time 53332715 ps
CPU time 0.85 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 215168 kb
Host smart-58bb7338-96c3-434d-8761-b5bd110027cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352245386 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3352245386
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3784759006
Short name T662
Test name
Test status
Simulation time 25733889 ps
CPU time 0.88 seconds
Started May 12 02:12:55 PM PDT 24
Finished May 12 02:12:58 PM PDT 24
Peak memory 215152 kb
Host smart-60cd349f-a0dd-479e-acb0-9fe0c6f89e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784759006 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3784759006
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3642608261
Short name T646
Test name
Test status
Simulation time 23905206 ps
CPU time 1.12 seconds
Started May 12 02:12:57 PM PDT 24
Finished May 12 02:12:59 PM PDT 24
Peak memory 215144 kb
Host smart-c51945be-7f1f-4e22-809c-ae311ee2e99f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642608261 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3642608261
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.731175023
Short name T622
Test name
Test status
Simulation time 174117338031 ps
CPU time 2178.59 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:49:09 PM PDT 24
Peak memory 230124 kb
Host smart-e6f15453-48ca-49fd-a7a9-b436a62b5d18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731175023 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.731175023
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.370849139
Short name T559
Test name
Test status
Simulation time 31907376 ps
CPU time 1.31 seconds
Started May 12 02:14:13 PM PDT 24
Finished May 12 02:14:15 PM PDT 24
Peak memory 218028 kb
Host smart-d7e8b01b-999b-4efd-abb2-43c01c4b5970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370849139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.370849139
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.2097295569
Short name T127
Test name
Test status
Simulation time 106880205 ps
CPU time 1.73 seconds
Started May 12 02:14:10 PM PDT 24
Finished May 12 02:14:14 PM PDT 24
Peak memory 218240 kb
Host smart-c04c15f6-138e-47cb-a288-55b182ee8f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097295569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2097295569
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.2119425597
Short name T681
Test name
Test status
Simulation time 140346592 ps
CPU time 2.6 seconds
Started May 12 02:14:09 PM PDT 24
Finished May 12 02:14:13 PM PDT 24
Peak memory 219588 kb
Host smart-e1d7df64-e1d7-405a-8e14-d64b1b322eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119425597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2119425597
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.761703100
Short name T764
Test name
Test status
Simulation time 275645491 ps
CPU time 1.21 seconds
Started May 12 02:14:08 PM PDT 24
Finished May 12 02:14:11 PM PDT 24
Peak memory 215304 kb
Host smart-37888553-fe51-4c34-af24-9af11b6d1555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761703100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.761703100
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.2750422982
Short name T340
Test name
Test status
Simulation time 41375217 ps
CPU time 1.74 seconds
Started May 12 02:14:09 PM PDT 24
Finished May 12 02:14:13 PM PDT 24
Peak memory 218268 kb
Host smart-1725eb4f-f35a-408b-832a-8ddefc2c4784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750422982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2750422982
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3503260455
Short name T612
Test name
Test status
Simulation time 48207898 ps
CPU time 1.18 seconds
Started May 12 02:14:15 PM PDT 24
Finished May 12 02:14:17 PM PDT 24
Peak memory 217012 kb
Host smart-4c28e799-1de8-4642-a200-ab117f200c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503260455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3503260455
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.2267619761
Short name T360
Test name
Test status
Simulation time 55591075 ps
CPU time 1.3 seconds
Started May 12 02:14:15 PM PDT 24
Finished May 12 02:14:17 PM PDT 24
Peak memory 218156 kb
Host smart-598935a1-3548-4eab-afd3-2a0fc48bba08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267619761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2267619761
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.709743894
Short name T131
Test name
Test status
Simulation time 109875194 ps
CPU time 1.62 seconds
Started May 12 02:14:15 PM PDT 24
Finished May 12 02:14:17 PM PDT 24
Peak memory 218440 kb
Host smart-48540851-7a3b-47e9-b386-b8868b1ece3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709743894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.709743894
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.1286926544
Short name T395
Test name
Test status
Simulation time 66961227 ps
CPU time 2.49 seconds
Started May 12 02:14:14 PM PDT 24
Finished May 12 02:14:18 PM PDT 24
Peak memory 219672 kb
Host smart-d1bf53d7-a71d-4b11-8fbf-cd176b5b62b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286926544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1286926544
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.4159029832
Short name T74
Test name
Test status
Simulation time 130389921 ps
CPU time 1.16 seconds
Started May 12 02:12:56 PM PDT 24
Finished May 12 02:12:58 PM PDT 24
Peak memory 215464 kb
Host smart-7895c2c3-45ed-42c0-8c96-40752ecf8101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159029832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.4159029832
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.1646168364
Short name T426
Test name
Test status
Simulation time 25326290 ps
CPU time 0.84 seconds
Started May 12 02:12:55 PM PDT 24
Finished May 12 02:12:57 PM PDT 24
Peak memory 206520 kb
Host smart-135263e8-82ed-4011-918d-253e2e085b25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646168364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1646168364
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.2579043737
Short name T443
Test name
Test status
Simulation time 30915476 ps
CPU time 0.83 seconds
Started May 12 02:12:52 PM PDT 24
Finished May 12 02:12:55 PM PDT 24
Peak memory 215216 kb
Host smart-ef196442-e59f-44a7-a3af-a2d5c40ef9c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579043737 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2579043737
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.318128599
Short name T661
Test name
Test status
Simulation time 36269482 ps
CPU time 1.3 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 216840 kb
Host smart-7e3dbea3-730b-4770-bf94-6511135ab4a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318128599 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.318128599
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1547034615
Short name T519
Test name
Test status
Simulation time 26075769 ps
CPU time 1.23 seconds
Started May 12 02:12:57 PM PDT 24
Finished May 12 02:12:59 PM PDT 24
Peak memory 219708 kb
Host smart-a796cc02-ecbe-499d-893f-a17d197ee25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547034615 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1547034615
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2316168106
Short name T694
Test name
Test status
Simulation time 39796351 ps
CPU time 1.54 seconds
Started May 12 02:12:47 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 217880 kb
Host smart-db30ad87-4e24-4f4c-b11f-4c3b5a4b6c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316168106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2316168106
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1523736022
Short name T344
Test name
Test status
Simulation time 22511544 ps
CPU time 1.08 seconds
Started May 12 02:12:55 PM PDT 24
Finished May 12 02:12:57 PM PDT 24
Peak memory 215244 kb
Host smart-f7393bdb-0d50-4ac3-84a0-10f68d1056c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523736022 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1523736022
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3614403272
Short name T619
Test name
Test status
Simulation time 23867652 ps
CPU time 0.97 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 206956 kb
Host smart-be8e4326-fc43-4aef-956d-0ec0e066701e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614403272 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3614403272
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1148471727
Short name T651
Test name
Test status
Simulation time 2026873974 ps
CPU time 4.37 seconds
Started May 12 02:12:55 PM PDT 24
Finished May 12 02:13:00 PM PDT 24
Peak memory 216848 kb
Host smart-a355d6cf-4188-4d57-bc42-62f28976845f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148471727 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1148471727
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1619998874
Short name T441
Test name
Test status
Simulation time 291274829496 ps
CPU time 1204.91 seconds
Started May 12 02:12:47 PM PDT 24
Finished May 12 02:32:54 PM PDT 24
Peak memory 222908 kb
Host smart-2a02f431-781d-4862-8512-3dc549a2b0e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619998874 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1619998874
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.3771225073
Short name T10
Test name
Test status
Simulation time 32406498 ps
CPU time 1.32 seconds
Started May 12 02:14:09 PM PDT 24
Finished May 12 02:14:13 PM PDT 24
Peak memory 219440 kb
Host smart-667e81f6-ecff-40b9-b55a-4077ac22fe91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771225073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3771225073
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.1061583937
Short name T502
Test name
Test status
Simulation time 35050197 ps
CPU time 1.36 seconds
Started May 12 02:14:12 PM PDT 24
Finished May 12 02:14:15 PM PDT 24
Peak memory 218060 kb
Host smart-c9c995af-1a9c-4cbe-a928-8721f452b4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061583937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1061583937
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.1490779358
Short name T366
Test name
Test status
Simulation time 61704927 ps
CPU time 1.45 seconds
Started May 12 02:14:14 PM PDT 24
Finished May 12 02:14:17 PM PDT 24
Peak memory 217944 kb
Host smart-4b8967fc-0003-4667-8bdf-2736d80f7865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490779358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1490779358
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.2520035276
Short name T450
Test name
Test status
Simulation time 33592295 ps
CPU time 1.29 seconds
Started May 12 02:14:12 PM PDT 24
Finished May 12 02:14:15 PM PDT 24
Peak memory 217192 kb
Host smart-01c55dd7-304d-4580-971b-025f9405fada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520035276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2520035276
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.3976688259
Short name T579
Test name
Test status
Simulation time 50307609 ps
CPU time 1.6 seconds
Started May 12 02:14:12 PM PDT 24
Finished May 12 02:14:15 PM PDT 24
Peak memory 218224 kb
Host smart-12663136-a9d1-47af-a507-36cf6aa076d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976688259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3976688259
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.849882861
Short name T27
Test name
Test status
Simulation time 59501557 ps
CPU time 1.73 seconds
Started May 12 02:14:10 PM PDT 24
Finished May 12 02:14:13 PM PDT 24
Peak memory 218420 kb
Host smart-c3c0d28f-7509-4c21-a12a-05f435f69e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849882861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.849882861
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.798432792
Short name T380
Test name
Test status
Simulation time 63439908 ps
CPU time 1.52 seconds
Started May 12 02:14:12 PM PDT 24
Finished May 12 02:14:15 PM PDT 24
Peak memory 217028 kb
Host smart-dfb4503c-c5b7-485d-9eee-ed119908bbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798432792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.798432792
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.775654422
Short name T687
Test name
Test status
Simulation time 88573579 ps
CPU time 1.27 seconds
Started May 12 02:14:14 PM PDT 24
Finished May 12 02:14:16 PM PDT 24
Peak memory 215200 kb
Host smart-29c43f49-016c-4424-adaa-de00e99e95d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775654422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.775654422
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.3800054411
Short name T680
Test name
Test status
Simulation time 45616448 ps
CPU time 1.6 seconds
Started May 12 02:14:10 PM PDT 24
Finished May 12 02:14:13 PM PDT 24
Peak memory 219108 kb
Host smart-54d000d6-7e7c-4de3-8f21-971d646d0c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800054411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3800054411
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.3530029799
Short name T625
Test name
Test status
Simulation time 87078688 ps
CPU time 1.38 seconds
Started May 12 02:14:14 PM PDT 24
Finished May 12 02:14:17 PM PDT 24
Peak memory 218064 kb
Host smart-c279ea8b-8241-43e7-afaa-71501202b373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530029799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3530029799
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.1002363619
Short name T345
Test name
Test status
Simulation time 65879248 ps
CPU time 0.81 seconds
Started May 12 02:12:55 PM PDT 24
Finished May 12 02:12:57 PM PDT 24
Peak memory 214512 kb
Host smart-aa30786a-a25c-415e-a1f9-6e7bc4446b95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002363619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1002363619
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.598941132
Short name T812
Test name
Test status
Simulation time 41511054 ps
CPU time 0.87 seconds
Started May 12 02:12:57 PM PDT 24
Finished May 12 02:12:59 PM PDT 24
Peak memory 214952 kb
Host smart-86fb5be1-9e06-45d6-bec4-f3b743d15b7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598941132 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.598941132
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2835249721
Short name T616
Test name
Test status
Simulation time 41557794 ps
CPU time 1.19 seconds
Started May 12 02:13:02 PM PDT 24
Finished May 12 02:13:03 PM PDT 24
Peak memory 216652 kb
Host smart-80948765-0544-47dd-ac4b-4ac84645305e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835249721 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2835249721
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2126890213
Short name T31
Test name
Test status
Simulation time 25310716 ps
CPU time 1.04 seconds
Started May 12 02:12:55 PM PDT 24
Finished May 12 02:12:58 PM PDT 24
Peak memory 219324 kb
Host smart-c45e467c-3780-49bd-8a10-b3cf73d72418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126890213 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2126890213
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_intr.713326909
Short name T336
Test name
Test status
Simulation time 63090732 ps
CPU time 0.88 seconds
Started May 12 02:12:53 PM PDT 24
Finished May 12 02:12:56 PM PDT 24
Peak memory 215188 kb
Host smart-32dd893b-01b0-443a-af04-7e42dcb630d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713326909 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.713326909
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1806572951
Short name T330
Test name
Test status
Simulation time 32875671 ps
CPU time 0.87 seconds
Started May 12 02:12:56 PM PDT 24
Finished May 12 02:12:58 PM PDT 24
Peak memory 215148 kb
Host smart-1328e0ee-c8e3-4940-b2f3-0ceaf10fba85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806572951 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1806572951
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.390801860
Short name T509
Test name
Test status
Simulation time 60427378 ps
CPU time 0.93 seconds
Started May 12 02:12:55 PM PDT 24
Finished May 12 02:12:58 PM PDT 24
Peak memory 206140 kb
Host smart-98e6ea4d-24e1-43dc-8a3c-35ae5908974b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390801860 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.390801860
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3852082971
Short name T201
Test name
Test status
Simulation time 262247810390 ps
CPU time 1301.02 seconds
Started May 12 02:12:55 PM PDT 24
Finished May 12 02:34:37 PM PDT 24
Peak memory 230840 kb
Host smart-5c188292-9ce4-44e8-a278-550056bdad62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852082971 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3852082971
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.605609609
Short name T837
Test name
Test status
Simulation time 42543413 ps
CPU time 1.56 seconds
Started May 12 02:14:10 PM PDT 24
Finished May 12 02:14:14 PM PDT 24
Peak memory 217860 kb
Host smart-6eaa1e0f-75bd-41f2-ae67-617db64196f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605609609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.605609609
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.748534255
Short name T640
Test name
Test status
Simulation time 45632199 ps
CPU time 1.53 seconds
Started May 12 02:14:11 PM PDT 24
Finished May 12 02:14:15 PM PDT 24
Peak memory 217208 kb
Host smart-71e51812-2612-4314-9f43-4117f3fc3cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748534255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.748534255
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.2670458897
Short name T647
Test name
Test status
Simulation time 54668366 ps
CPU time 1.17 seconds
Started May 12 02:14:09 PM PDT 24
Finished May 12 02:14:13 PM PDT 24
Peak memory 216952 kb
Host smart-69b4c0a4-9557-47d5-b352-a0d8974f24a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670458897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2670458897
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.3425920792
Short name T557
Test name
Test status
Simulation time 51229481 ps
CPU time 1.22 seconds
Started May 12 02:14:08 PM PDT 24
Finished May 12 02:14:11 PM PDT 24
Peak memory 219436 kb
Host smart-dc97f932-fe0a-4a72-b30e-89e029d54d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425920792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3425920792
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.4175176819
Short name T1
Test name
Test status
Simulation time 41167240 ps
CPU time 1.53 seconds
Started May 12 02:14:11 PM PDT 24
Finished May 12 02:14:15 PM PDT 24
Peak memory 217836 kb
Host smart-54946894-ba11-45e9-bef8-1f86090e059a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175176819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.4175176819
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.2971442287
Short name T327
Test name
Test status
Simulation time 52345472 ps
CPU time 1.35 seconds
Started May 12 02:14:16 PM PDT 24
Finished May 12 02:14:19 PM PDT 24
Peak memory 218452 kb
Host smart-4c6ab5a1-e4bc-46b0-9c1a-33313285464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971442287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2971442287
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.1920617055
Short name T771
Test name
Test status
Simulation time 177398027 ps
CPU time 1.39 seconds
Started May 12 02:14:10 PM PDT 24
Finished May 12 02:14:13 PM PDT 24
Peak memory 218480 kb
Host smart-5ce3fc68-6b11-4ad9-823b-0bd729b0bb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920617055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1920617055
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.3903448556
Short name T365
Test name
Test status
Simulation time 44757925 ps
CPU time 1.26 seconds
Started May 12 02:14:16 PM PDT 24
Finished May 12 02:14:19 PM PDT 24
Peak memory 217220 kb
Host smart-fe58d89b-7a22-4f94-85db-34cb4d28d929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903448556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3903448556
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.494063390
Short name T349
Test name
Test status
Simulation time 39825450 ps
CPU time 1.67 seconds
Started May 12 02:14:15 PM PDT 24
Finished May 12 02:14:17 PM PDT 24
Peak memory 216960 kb
Host smart-c4a3fbf7-bce4-4e38-b531-4840f6ae3889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494063390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.494063390
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.990440702
Short name T249
Test name
Test status
Simulation time 27159591 ps
CPU time 1.27 seconds
Started May 12 02:13:02 PM PDT 24
Finished May 12 02:13:03 PM PDT 24
Peak memory 215540 kb
Host smart-9e0e0126-077a-4f5f-a4b9-888439558bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990440702 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.990440702
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1700647338
Short name T803
Test name
Test status
Simulation time 14327434 ps
CPU time 0.96 seconds
Started May 12 02:12:57 PM PDT 24
Finished May 12 02:12:59 PM PDT 24
Peak memory 214736 kb
Host smart-a929a701-9fe3-439f-871f-857c2bbeb8a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700647338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1700647338
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.470351781
Short name T134
Test name
Test status
Simulation time 12399699 ps
CPU time 0.92 seconds
Started May 12 02:13:02 PM PDT 24
Finished May 12 02:13:03 PM PDT 24
Peak memory 215800 kb
Host smart-552f9478-b515-4a6b-ae25-b09757bbd454
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470351781 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.470351781
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3477312890
Short name T476
Test name
Test status
Simulation time 57671185 ps
CPU time 1.3 seconds
Started May 12 02:12:49 PM PDT 24
Finished May 12 02:12:52 PM PDT 24
Peak memory 219228 kb
Host smart-9d90e47c-b9be-4839-a432-0528b2353d02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477312890 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3477312890
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2571267828
Short name T526
Test name
Test status
Simulation time 18987636 ps
CPU time 1.08 seconds
Started May 12 02:12:56 PM PDT 24
Finished May 12 02:12:58 PM PDT 24
Peak memory 223864 kb
Host smart-db727323-db8e-4ae8-aba8-c4014f3e3987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571267828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2571267828
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1742684176
Short name T267
Test name
Test status
Simulation time 127915835 ps
CPU time 1.18 seconds
Started May 12 02:13:02 PM PDT 24
Finished May 12 02:13:04 PM PDT 24
Peak memory 217068 kb
Host smart-46117ce8-cccd-4abd-94d1-8ceb31af3740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742684176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1742684176
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3135740688
Short name T759
Test name
Test status
Simulation time 20224253 ps
CPU time 1.13 seconds
Started May 12 02:13:01 PM PDT 24
Finished May 12 02:13:03 PM PDT 24
Peak memory 215584 kb
Host smart-b24c8d4c-cf4f-4fc4-b361-e65df258c2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135740688 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3135740688
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.289404156
Short name T444
Test name
Test status
Simulation time 22238152 ps
CPU time 0.9 seconds
Started May 12 02:12:54 PM PDT 24
Finished May 12 02:12:56 PM PDT 24
Peak memory 215096 kb
Host smart-4696e37d-2fb4-4e59-9910-d25c06449830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289404156 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.289404156
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1694338076
Short name T145
Test name
Test status
Simulation time 29111431 ps
CPU time 1.19 seconds
Started May 12 02:12:55 PM PDT 24
Finished May 12 02:12:58 PM PDT 24
Peak memory 215184 kb
Host smart-7be2f688-1dc8-4f14-8f01-26e050003004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694338076 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1694338076
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3925710971
Short name T667
Test name
Test status
Simulation time 20369676433 ps
CPU time 532.4 seconds
Started May 12 02:13:02 PM PDT 24
Finished May 12 02:21:55 PM PDT 24
Peak memory 223592 kb
Host smart-56b024c0-d20d-4dd4-8cff-ec12da6566c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925710971 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3925710971
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.3349084261
Short name T813
Test name
Test status
Simulation time 38403476 ps
CPU time 1.57 seconds
Started May 12 02:14:17 PM PDT 24
Finished May 12 02:14:20 PM PDT 24
Peak memory 219648 kb
Host smart-abefffb3-2b70-483f-9fa7-f46315c09e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349084261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3349084261
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.4253726670
Short name T571
Test name
Test status
Simulation time 77788059 ps
CPU time 1.19 seconds
Started May 12 02:14:12 PM PDT 24
Finished May 12 02:14:15 PM PDT 24
Peak memory 216776 kb
Host smart-91068249-d5b9-4dbf-aff0-78b8d9673080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253726670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.4253726670
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.1897899379
Short name T807
Test name
Test status
Simulation time 61916645 ps
CPU time 1.42 seconds
Started May 12 02:14:17 PM PDT 24
Finished May 12 02:14:19 PM PDT 24
Peak memory 216812 kb
Host smart-beb0236d-18b3-4d6d-b594-b50d90a07938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897899379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1897899379
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.2984863005
Short name T654
Test name
Test status
Simulation time 52140738 ps
CPU time 1.94 seconds
Started May 12 02:14:15 PM PDT 24
Finished May 12 02:14:18 PM PDT 24
Peak memory 217952 kb
Host smart-46f645f4-5c73-40a8-bf00-e1025596e3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984863005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2984863005
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.35657675
Short name T633
Test name
Test status
Simulation time 98391461 ps
CPU time 1.19 seconds
Started May 12 02:14:16 PM PDT 24
Finished May 12 02:14:17 PM PDT 24
Peak memory 216960 kb
Host smart-399dcee0-9dca-41f4-9ee4-54ac2660a91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35657675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.35657675
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.1765696678
Short name T777
Test name
Test status
Simulation time 39389915 ps
CPU time 1.6 seconds
Started May 12 02:14:15 PM PDT 24
Finished May 12 02:14:17 PM PDT 24
Peak memory 217156 kb
Host smart-3849721b-ce35-462a-bfbb-e0c91f612384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765696678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1765696678
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.2161070883
Short name T805
Test name
Test status
Simulation time 38840193 ps
CPU time 1.42 seconds
Started May 12 02:14:15 PM PDT 24
Finished May 12 02:14:18 PM PDT 24
Peak memory 217980 kb
Host smart-d668f64a-d1bb-4f9c-8d56-ef3b347c54a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161070883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2161070883
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.1907221190
Short name T488
Test name
Test status
Simulation time 96134700 ps
CPU time 1.65 seconds
Started May 12 02:14:20 PM PDT 24
Finished May 12 02:14:22 PM PDT 24
Peak memory 218532 kb
Host smart-aea3547d-29d4-451a-a973-2f3b39a69444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907221190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1907221190
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.1144964773
Short name T778
Test name
Test status
Simulation time 44585644 ps
CPU time 1.49 seconds
Started May 12 02:14:13 PM PDT 24
Finished May 12 02:14:15 PM PDT 24
Peak memory 218108 kb
Host smart-69834768-c8f6-4d4a-8233-85e542d87c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144964773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1144964773
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.496934815
Short name T312
Test name
Test status
Simulation time 40104002 ps
CPU time 1.2 seconds
Started May 12 02:14:14 PM PDT 24
Finished May 12 02:14:16 PM PDT 24
Peak memory 218136 kb
Host smart-41a74db8-3bca-4857-b913-7985d4f6900a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496934815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.496934815
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert_test.2659613679
Short name T738
Test name
Test status
Simulation time 34684723 ps
CPU time 0.82 seconds
Started May 12 02:12:36 PM PDT 24
Finished May 12 02:12:38 PM PDT 24
Peak memory 206728 kb
Host smart-7cd0348a-15b6-4e7c-96bf-1fdab3081b01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659613679 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2659613679
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.551878430
Short name T840
Test name
Test status
Simulation time 169527641 ps
CPU time 1.24 seconds
Started May 12 02:12:37 PM PDT 24
Finished May 12 02:12:39 PM PDT 24
Peak memory 216832 kb
Host smart-0c7ff44c-e5d8-41ee-8049-a9b8fd1eb1f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551878430 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.551878430
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1946449256
Short name T631
Test name
Test status
Simulation time 18256600 ps
CPU time 1.02 seconds
Started May 12 02:12:42 PM PDT 24
Finished May 12 02:12:45 PM PDT 24
Peak memory 217952 kb
Host smart-b041f1c0-a92d-436d-9550-80a977c91436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946449256 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1946449256
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3703177901
Short name T421
Test name
Test status
Simulation time 125257966 ps
CPU time 2.74 seconds
Started May 12 02:12:39 PM PDT 24
Finished May 12 02:12:42 PM PDT 24
Peak memory 219660 kb
Host smart-da5e1a16-f925-4598-921f-0ba0aa1f56b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703177901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3703177901
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3517190633
Short name T405
Test name
Test status
Simulation time 25009948 ps
CPU time 1.07 seconds
Started May 12 02:12:21 PM PDT 24
Finished May 12 02:12:23 PM PDT 24
Peak memory 223860 kb
Host smart-55bf9d5a-90d7-433b-820b-9ecc16f88664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517190633 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3517190633
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3220218298
Short name T121
Test name
Test status
Simulation time 5898629706 ps
CPU time 9.58 seconds
Started May 12 02:12:40 PM PDT 24
Finished May 12 02:12:50 PM PDT 24
Peak memory 240216 kb
Host smart-fe6ab648-238a-4633-a4b9-cdcf76e79d61
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220218298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3220218298
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3593780203
Short name T806
Test name
Test status
Simulation time 43155400 ps
CPU time 0.93 seconds
Started May 12 02:12:36 PM PDT 24
Finished May 12 02:12:37 PM PDT 24
Peak memory 215124 kb
Host smart-3bd06627-a3b1-4902-9aa8-289ede4f7618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593780203 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3593780203
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3566712075
Short name T500
Test name
Test status
Simulation time 60972152 ps
CPU time 1.7 seconds
Started May 12 02:12:38 PM PDT 24
Finished May 12 02:12:40 PM PDT 24
Peak memory 215164 kb
Host smart-06958c97-e521-49db-b7dd-93b65cc40779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566712075 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3566712075
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2884285794
Short name T632
Test name
Test status
Simulation time 101065781216 ps
CPU time 1826.56 seconds
Started May 12 02:12:37 PM PDT 24
Finished May 12 02:43:05 PM PDT 24
Peak memory 225628 kb
Host smart-cce87bf9-83c2-4f4c-903c-f9fa50cdc02a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884285794 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2884285794
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert_test.2259440057
Short name T354
Test name
Test status
Simulation time 52950153 ps
CPU time 0.92 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 206564 kb
Host smart-fa9cd47e-1281-492f-9679-7c400f25a6b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259440057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2259440057
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3350491473
Short name T458
Test name
Test status
Simulation time 27479134 ps
CPU time 0.81 seconds
Started May 12 02:12:49 PM PDT 24
Finished May 12 02:12:52 PM PDT 24
Peak memory 215744 kb
Host smart-47b6bab0-00af-460b-a42d-da0e60af1576
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350491473 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3350491473
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3861278719
Short name T475
Test name
Test status
Simulation time 170820765 ps
CPU time 1.1 seconds
Started May 12 02:13:02 PM PDT 24
Finished May 12 02:13:03 PM PDT 24
Peak memory 216780 kb
Host smart-034ee907-51f6-423c-8b62-d85e733e6ad7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861278719 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3861278719
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2632151158
Short name T175
Test name
Test status
Simulation time 22682630 ps
CPU time 1.18 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:52 PM PDT 24
Peak memory 218420 kb
Host smart-cfdeae6a-9de8-430f-afec-f63a56e1dc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632151158 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2632151158
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.588260469
Short name T254
Test name
Test status
Simulation time 60351897 ps
CPU time 1.11 seconds
Started May 12 02:12:49 PM PDT 24
Finished May 12 02:12:52 PM PDT 24
Peak memory 218424 kb
Host smart-1a8dc50e-afd0-486d-8f96-2d71826b0c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588260469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.588260469
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.107050419
Short name T141
Test name
Test status
Simulation time 20137616 ps
CPU time 1.07 seconds
Started May 12 02:13:02 PM PDT 24
Finished May 12 02:13:03 PM PDT 24
Peak memory 215708 kb
Host smart-f157c24b-87b5-4f60-8440-538834fe025e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107050419 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.107050419
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.389616511
Short name T490
Test name
Test status
Simulation time 44179199 ps
CPU time 0.98 seconds
Started May 12 02:12:49 PM PDT 24
Finished May 12 02:12:52 PM PDT 24
Peak memory 215128 kb
Host smart-3ed58138-1a55-41e8-9068-05d21ece8a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389616511 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.389616511
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.436166088
Short name T452
Test name
Test status
Simulation time 395917828 ps
CPU time 2.51 seconds
Started May 12 02:12:49 PM PDT 24
Finished May 12 02:12:54 PM PDT 24
Peak memory 216704 kb
Host smart-be69cf1f-c511-4dcf-90a7-f4f29225174a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436166088 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.436166088
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.509800097
Short name T568
Test name
Test status
Simulation time 246507646095 ps
CPU time 1973.3 seconds
Started May 12 02:12:57 PM PDT 24
Finished May 12 02:45:51 PM PDT 24
Peak memory 226236 kb
Host smart-fac3512e-6748-4117-84d4-11052fe119d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509800097 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.509800097
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2744726956
Short name T731
Test name
Test status
Simulation time 31562024 ps
CPU time 1.35 seconds
Started May 12 02:14:18 PM PDT 24
Finished May 12 02:14:20 PM PDT 24
Peak memory 219424 kb
Host smart-f3f3d33a-9a63-4871-afa8-88438f23a98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744726956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2744726956
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2773118451
Short name T216
Test name
Test status
Simulation time 78017728 ps
CPU time 1.13 seconds
Started May 12 02:14:20 PM PDT 24
Finished May 12 02:14:22 PM PDT 24
Peak memory 216824 kb
Host smart-4e639b21-23c7-4c71-b660-5211cb64eb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773118451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2773118451
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3650428313
Short name T142
Test name
Test status
Simulation time 31711968 ps
CPU time 1.31 seconds
Started May 12 02:14:16 PM PDT 24
Finished May 12 02:14:18 PM PDT 24
Peak memory 218060 kb
Host smart-e147b030-a7c4-44a5-9c8e-c61fa0f92dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650428313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3650428313
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2758624438
Short name T709
Test name
Test status
Simulation time 44748728 ps
CPU time 1.3 seconds
Started May 12 02:14:18 PM PDT 24
Finished May 12 02:14:20 PM PDT 24
Peak memory 218028 kb
Host smart-61ca3bb1-7c27-462b-8e4c-9542e9a85348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758624438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2758624438
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3953623317
Short name T391
Test name
Test status
Simulation time 65535449 ps
CPU time 1.6 seconds
Started May 12 02:14:15 PM PDT 24
Finished May 12 02:14:18 PM PDT 24
Peak memory 217972 kb
Host smart-1aa45cee-d0cb-4e86-a6ad-c115fb4b27ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953623317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3953623317
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.2102829318
Short name T407
Test name
Test status
Simulation time 44755579 ps
CPU time 1.22 seconds
Started May 12 02:14:17 PM PDT 24
Finished May 12 02:14:19 PM PDT 24
Peak memory 219300 kb
Host smart-ada0a4ec-3f5e-428e-9957-dffaad62afda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102829318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.2102829318
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.586320344
Short name T479
Test name
Test status
Simulation time 159029848 ps
CPU time 2.03 seconds
Started May 12 02:14:17 PM PDT 24
Finished May 12 02:14:20 PM PDT 24
Peak memory 218492 kb
Host smart-76f1f261-fc6d-4eb8-bc81-0ea2943f58c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586320344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.586320344
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3175019032
Short name T206
Test name
Test status
Simulation time 61207125 ps
CPU time 1.78 seconds
Started May 12 02:14:18 PM PDT 24
Finished May 12 02:14:21 PM PDT 24
Peak memory 218048 kb
Host smart-e64093e1-861c-4bcd-b797-92cacb3f16c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175019032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3175019032
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1288128503
Short name T12
Test name
Test status
Simulation time 39539683 ps
CPU time 1.44 seconds
Started May 12 02:14:17 PM PDT 24
Finished May 12 02:14:19 PM PDT 24
Peak memory 219652 kb
Host smart-607af0bf-0ecb-4530-a05c-77b62451f7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288128503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1288128503
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3369657437
Short name T279
Test name
Test status
Simulation time 37492017 ps
CPU time 1.34 seconds
Started May 12 02:14:17 PM PDT 24
Finished May 12 02:14:20 PM PDT 24
Peak memory 219360 kb
Host smart-70600da2-57de-46c5-826e-80079830646e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369657437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3369657437
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2628987477
Short name T265
Test name
Test status
Simulation time 28058786 ps
CPU time 1.4 seconds
Started May 12 02:12:53 PM PDT 24
Finished May 12 02:12:56 PM PDT 24
Peak memory 215452 kb
Host smart-94868653-0881-4a04-b345-570c38dabd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628987477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2628987477
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1256195864
Short name T442
Test name
Test status
Simulation time 17516449 ps
CPU time 0.85 seconds
Started May 12 02:12:51 PM PDT 24
Finished May 12 02:12:53 PM PDT 24
Peak memory 206348 kb
Host smart-6081e01c-27d1-4fef-8a7c-27148c5d5889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256195864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1256195864
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.808321155
Short name T86
Test name
Test status
Simulation time 40084769 ps
CPU time 0.86 seconds
Started May 12 02:12:54 PM PDT 24
Finished May 12 02:12:56 PM PDT 24
Peak memory 216152 kb
Host smart-6e79b1d1-9615-470e-b376-a1efc160641c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808321155 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.808321155
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_err.1804053298
Short name T562
Test name
Test status
Simulation time 33042816 ps
CPU time 1.29 seconds
Started May 12 02:12:52 PM PDT 24
Finished May 12 02:12:55 PM PDT 24
Peak memory 229444 kb
Host smart-4327fcc9-b597-47d2-8893-1b25d6729435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804053298 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1804053298
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2966041685
Short name T574
Test name
Test status
Simulation time 73955506 ps
CPU time 1.05 seconds
Started May 12 02:12:46 PM PDT 24
Finished May 12 02:12:49 PM PDT 24
Peak memory 216752 kb
Host smart-fe8662c8-8936-4c3a-9bbe-980866a1e5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966041685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2966041685
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3234001016
Short name T535
Test name
Test status
Simulation time 21880040 ps
CPU time 1.11 seconds
Started May 12 02:12:53 PM PDT 24
Finished May 12 02:12:56 PM PDT 24
Peak memory 215312 kb
Host smart-1d54d39d-618d-4307-ac86-91e34298ef1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234001016 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3234001016
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3041386179
Short name T623
Test name
Test status
Simulation time 27584794 ps
CPU time 1.03 seconds
Started May 12 02:12:49 PM PDT 24
Finished May 12 02:12:53 PM PDT 24
Peak memory 206892 kb
Host smart-d882e12a-0aaa-43e6-8b35-3221ac6f7887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041386179 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3041386179
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.295343245
Short name T191
Test name
Test status
Simulation time 20583174779 ps
CPU time 228.56 seconds
Started May 12 02:12:57 PM PDT 24
Finished May 12 02:16:47 PM PDT 24
Peak memory 218120 kb
Host smart-75acdc77-5939-4996-8aa3-195fbc822c4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295343245 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.295343245
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1587977314
Short name T334
Test name
Test status
Simulation time 59668642 ps
CPU time 1.66 seconds
Started May 12 02:14:17 PM PDT 24
Finished May 12 02:14:20 PM PDT 24
Peak memory 218200 kb
Host smart-052da702-e558-41da-853f-846bc87bda95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587977314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1587977314
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1664055309
Short name T431
Test name
Test status
Simulation time 120313639 ps
CPU time 2.54 seconds
Started May 12 02:14:20 PM PDT 24
Finished May 12 02:14:23 PM PDT 24
Peak memory 218120 kb
Host smart-1289d1ce-57f4-48d3-ad68-6746d6f7285b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664055309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1664055309
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3079694935
Short name T699
Test name
Test status
Simulation time 50687382 ps
CPU time 1.28 seconds
Started May 12 02:14:21 PM PDT 24
Finished May 12 02:14:23 PM PDT 24
Peak memory 218296 kb
Host smart-30a9d427-8fdd-424e-acac-8c856ac9087e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079694935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3079694935
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3382048182
Short name T409
Test name
Test status
Simulation time 96899719 ps
CPU time 1.41 seconds
Started May 12 02:14:20 PM PDT 24
Finished May 12 02:14:22 PM PDT 24
Peak memory 218508 kb
Host smart-3c21dd12-55cb-4d1c-aa0e-c86aaa91e0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382048182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3382048182
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.150599005
Short name T578
Test name
Test status
Simulation time 64472968 ps
CPU time 1.1 seconds
Started May 12 02:14:21 PM PDT 24
Finished May 12 02:14:22 PM PDT 24
Peak memory 218372 kb
Host smart-a98f670b-b32c-4552-93df-fbbada5582e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150599005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.150599005
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3935036812
Short name T438
Test name
Test status
Simulation time 64403331 ps
CPU time 1.16 seconds
Started May 12 02:14:22 PM PDT 24
Finished May 12 02:14:24 PM PDT 24
Peak memory 216864 kb
Host smart-984e3818-2d03-4da5-8fc2-c5a6b722baf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935036812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3935036812
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.763272117
Short name T288
Test name
Test status
Simulation time 86091075 ps
CPU time 1.14 seconds
Started May 12 02:14:23 PM PDT 24
Finished May 12 02:14:24 PM PDT 24
Peak memory 216816 kb
Host smart-a92d0f3f-f1aa-4cd5-948a-e5f89dd24155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763272117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.763272117
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2852803769
Short name T424
Test name
Test status
Simulation time 33194948 ps
CPU time 1.33 seconds
Started May 12 02:14:24 PM PDT 24
Finished May 12 02:14:26 PM PDT 24
Peak memory 218144 kb
Host smart-49d197ae-9f7e-4485-b201-2f6f3fb9c0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852803769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2852803769
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.4199273059
Short name T347
Test name
Test status
Simulation time 31392475 ps
CPU time 1.33 seconds
Started May 12 02:14:19 PM PDT 24
Finished May 12 02:14:21 PM PDT 24
Peak memory 218080 kb
Host smart-f808676d-8238-4dcf-bfdb-7aa26f3a37f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199273059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.4199273059
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1909448015
Short name T563
Test name
Test status
Simulation time 66480280 ps
CPU time 1.22 seconds
Started May 12 02:14:24 PM PDT 24
Finished May 12 02:14:26 PM PDT 24
Peak memory 219732 kb
Host smart-0d1b9e21-e170-4052-9e7e-eab9e556a792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909448015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1909448015
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert_test.3777844456
Short name T564
Test name
Test status
Simulation time 15760830 ps
CPU time 0.98 seconds
Started May 12 02:13:01 PM PDT 24
Finished May 12 02:13:02 PM PDT 24
Peak memory 214932 kb
Host smart-5c586fed-936a-4018-96b4-3ac1fb870403
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777844456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3777844456
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_err.941286332
Short name T493
Test name
Test status
Simulation time 71418400 ps
CPU time 0.89 seconds
Started May 12 02:12:55 PM PDT 24
Finished May 12 02:12:58 PM PDT 24
Peak memory 217776 kb
Host smart-bf2eef35-a183-4bb6-8198-e530dd54785a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941286332 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.941286332
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1318909028
Short name T650
Test name
Test status
Simulation time 91686672 ps
CPU time 1.26 seconds
Started May 12 02:12:54 PM PDT 24
Finished May 12 02:12:57 PM PDT 24
Peak memory 219732 kb
Host smart-09c2dfa1-4531-4d2f-bba8-561513e3d83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318909028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1318909028
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.437046646
Short name T107
Test name
Test status
Simulation time 25224955 ps
CPU time 1.13 seconds
Started May 12 02:12:58 PM PDT 24
Finished May 12 02:12:59 PM PDT 24
Peak memory 215644 kb
Host smart-8d8f4895-5b74-48d2-9aab-5adc577c1361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437046646 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.437046646
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.318980085
Short name T418
Test name
Test status
Simulation time 61136031 ps
CPU time 0.93 seconds
Started May 12 02:12:54 PM PDT 24
Finished May 12 02:12:56 PM PDT 24
Peak memory 215144 kb
Host smart-795b9ac7-db0b-4892-b205-44ac1ef16c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318980085 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.318980085
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3261858504
Short name T691
Test name
Test status
Simulation time 250225566 ps
CPU time 2.92 seconds
Started May 12 02:12:52 PM PDT 24
Finished May 12 02:12:57 PM PDT 24
Peak memory 215208 kb
Host smart-39bd614c-eb2e-4098-9085-207b61f780f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261858504 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3261858504
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1535180086
Short name T670
Test name
Test status
Simulation time 111773279990 ps
CPU time 1430.56 seconds
Started May 12 02:12:55 PM PDT 24
Finished May 12 02:36:47 PM PDT 24
Peak memory 225812 kb
Host smart-d1a7273f-9487-452c-b7fd-6cd9641a187e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535180086 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1535180086
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2197902899
Short name T787
Test name
Test status
Simulation time 51152594 ps
CPU time 1.99 seconds
Started May 12 02:14:19 PM PDT 24
Finished May 12 02:14:22 PM PDT 24
Peak memory 218280 kb
Host smart-03f70f97-ba75-4257-882b-f80cf6bdf609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197902899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2197902899
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3539127297
Short name T278
Test name
Test status
Simulation time 108864535 ps
CPU time 2.45 seconds
Started May 12 02:14:26 PM PDT 24
Finished May 12 02:14:29 PM PDT 24
Peak memory 217160 kb
Host smart-24610bbe-e3af-427d-aca0-561390a68ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539127297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3539127297
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3227928856
Short name T208
Test name
Test status
Simulation time 87155248 ps
CPU time 1.8 seconds
Started May 12 02:14:28 PM PDT 24
Finished May 12 02:14:31 PM PDT 24
Peak memory 218448 kb
Host smart-13dcfedc-7873-4bc5-b652-0d50ea36a69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227928856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3227928856
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.839775512
Short name T323
Test name
Test status
Simulation time 82239795 ps
CPU time 1.35 seconds
Started May 12 02:14:23 PM PDT 24
Finished May 12 02:14:26 PM PDT 24
Peak memory 218640 kb
Host smart-fd7fa985-6f67-48b6-b7f7-0b59e4d65641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839775512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.839775512
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3367920005
Short name T112
Test name
Test status
Simulation time 55951977 ps
CPU time 1.42 seconds
Started May 12 02:14:24 PM PDT 24
Finished May 12 02:14:26 PM PDT 24
Peak memory 216920 kb
Host smart-19944207-d614-45f4-83de-8a61c2ec86cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367920005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3367920005
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.4209079747
Short name T280
Test name
Test status
Simulation time 282733364 ps
CPU time 3.87 seconds
Started May 12 02:14:23 PM PDT 24
Finished May 12 02:14:27 PM PDT 24
Peak memory 219724 kb
Host smart-04b826c7-7721-4d03-a666-7bb50f5d619b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209079747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.4209079747
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2135025165
Short name T474
Test name
Test status
Simulation time 86445167 ps
CPU time 2.88 seconds
Started May 12 02:14:25 PM PDT 24
Finished May 12 02:14:28 PM PDT 24
Peak memory 218392 kb
Host smart-f1bd67f3-ffdc-444e-a504-e90b1ededed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135025165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2135025165
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2596429324
Short name T356
Test name
Test status
Simulation time 138492127 ps
CPU time 3.21 seconds
Started May 12 02:14:28 PM PDT 24
Finished May 12 02:14:32 PM PDT 24
Peak memory 219620 kb
Host smart-d9163e1a-5b81-4bce-a65b-3c6819010655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596429324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2596429324
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2727458549
Short name T359
Test name
Test status
Simulation time 106621031 ps
CPU time 1.6 seconds
Started May 12 02:14:24 PM PDT 24
Finished May 12 02:14:26 PM PDT 24
Peak memory 218344 kb
Host smart-c7195866-7c11-46b7-a0a6-87116cf60faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727458549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2727458549
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3993900110
Short name T464
Test name
Test status
Simulation time 83828965 ps
CPU time 1.3 seconds
Started May 12 02:13:02 PM PDT 24
Finished May 12 02:13:04 PM PDT 24
Peak memory 215536 kb
Host smart-9d32ea8a-972c-4d93-a880-7b3efa090747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993900110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3993900110
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.668399928
Short name T496
Test name
Test status
Simulation time 42761266 ps
CPU time 0.9 seconds
Started May 12 02:13:05 PM PDT 24
Finished May 12 02:13:07 PM PDT 24
Peak memory 214716 kb
Host smart-3b78d27c-f1b3-4352-bb84-362d78eac901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668399928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.668399928
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2394082529
Short name T181
Test name
Test status
Simulation time 11097274 ps
CPU time 0.9 seconds
Started May 12 02:13:03 PM PDT 24
Finished May 12 02:13:04 PM PDT 24
Peak memory 216052 kb
Host smart-aad67ac4-7ed2-4eb0-97da-6b6d5d10185b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394082529 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2394082529
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.4228910543
Short name T369
Test name
Test status
Simulation time 94947967 ps
CPU time 1.23 seconds
Started May 12 02:13:06 PM PDT 24
Finished May 12 02:13:07 PM PDT 24
Peak memory 216820 kb
Host smart-494a7b84-49b3-4de2-8983-8c41192c86b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228910543 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.4228910543
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3480087454
Short name T161
Test name
Test status
Simulation time 33388505 ps
CPU time 1.15 seconds
Started May 12 02:13:02 PM PDT 24
Finished May 12 02:13:04 PM PDT 24
Peak memory 220624 kb
Host smart-6efad9a6-b0e1-40b1-9787-756ff64c4f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480087454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3480087454
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3759895104
Short name T130
Test name
Test status
Simulation time 91914751 ps
CPU time 1.21 seconds
Started May 12 02:13:00 PM PDT 24
Finished May 12 02:13:01 PM PDT 24
Peak memory 216880 kb
Host smart-38294409-43fd-4e07-a706-69650128312e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759895104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3759895104
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2307612261
Short name T797
Test name
Test status
Simulation time 20605489 ps
CPU time 1.17 seconds
Started May 12 02:13:00 PM PDT 24
Finished May 12 02:13:02 PM PDT 24
Peak memory 215792 kb
Host smart-7263cd2b-4e8c-44e4-80e6-f3d746f4e286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307612261 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2307612261
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3654760253
Short name T378
Test name
Test status
Simulation time 87075773 ps
CPU time 0.92 seconds
Started May 12 02:13:00 PM PDT 24
Finished May 12 02:13:02 PM PDT 24
Peak memory 215176 kb
Host smart-fc9a16e7-4d86-4e64-8a2b-33352d6dc37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654760253 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3654760253
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.377861852
Short name T614
Test name
Test status
Simulation time 428333290 ps
CPU time 4.73 seconds
Started May 12 02:12:59 PM PDT 24
Finished May 12 02:13:04 PM PDT 24
Peak memory 217024 kb
Host smart-bc4479f0-8329-4e05-9b53-62f66c0983f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377861852 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.377861852
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3980305064
Short name T555
Test name
Test status
Simulation time 314795495691 ps
CPU time 1797.32 seconds
Started May 12 02:13:00 PM PDT 24
Finished May 12 02:42:58 PM PDT 24
Peak memory 227320 kb
Host smart-dbaaaf66-05a7-4dbf-a466-b94369348403
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980305064 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3980305064
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.155589364
Short name T446
Test name
Test status
Simulation time 86583417 ps
CPU time 1.16 seconds
Started May 12 02:14:25 PM PDT 24
Finished May 12 02:14:27 PM PDT 24
Peak memory 216740 kb
Host smart-319c33fa-33bc-40d0-aa7a-0096095dd550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155589364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.155589364
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.295250124
Short name T268
Test name
Test status
Simulation time 48328903 ps
CPU time 1.63 seconds
Started May 12 02:14:28 PM PDT 24
Finished May 12 02:14:30 PM PDT 24
Peak memory 218192 kb
Host smart-08884398-8e6e-4f0e-b5e1-cbc9a2e02fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295250124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.295250124
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.933602069
Short name T306
Test name
Test status
Simulation time 134821815 ps
CPU time 3 seconds
Started May 12 02:14:28 PM PDT 24
Finished May 12 02:14:32 PM PDT 24
Peak memory 219596 kb
Host smart-b9d929ba-0525-4cb6-97fb-f716c6e54681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933602069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.933602069
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3376975970
Short name T685
Test name
Test status
Simulation time 43909406 ps
CPU time 1.79 seconds
Started May 12 02:14:24 PM PDT 24
Finished May 12 02:14:26 PM PDT 24
Peak memory 218140 kb
Host smart-c57e3393-75cb-432a-9f6d-22b0c600fc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376975970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3376975970
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1686892122
Short name T770
Test name
Test status
Simulation time 21882093 ps
CPU time 1.1 seconds
Started May 12 02:14:27 PM PDT 24
Finished May 12 02:14:29 PM PDT 24
Peak memory 217008 kb
Host smart-d6145967-a0df-475c-b496-809223516f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686892122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1686892122
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3815834027
Short name T665
Test name
Test status
Simulation time 73129884 ps
CPU time 1.1 seconds
Started May 12 02:14:28 PM PDT 24
Finished May 12 02:14:30 PM PDT 24
Peak memory 216776 kb
Host smart-f5510ad7-79f4-4c0b-ae74-80cd4ac0b07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815834027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3815834027
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2440852866
Short name T704
Test name
Test status
Simulation time 31095457 ps
CPU time 1.23 seconds
Started May 12 02:14:28 PM PDT 24
Finished May 12 02:14:31 PM PDT 24
Peak memory 216720 kb
Host smart-3828c895-41ed-4a50-b21a-278b0f9c7480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440852866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2440852866
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1041393017
Short name T272
Test name
Test status
Simulation time 85865236 ps
CPU time 1.24 seconds
Started May 12 02:14:27 PM PDT 24
Finished May 12 02:14:29 PM PDT 24
Peak memory 217028 kb
Host smart-2d163d83-a271-4846-9210-f83670af96c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041393017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1041393017
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.234946244
Short name T209
Test name
Test status
Simulation time 146789799 ps
CPU time 1.12 seconds
Started May 12 02:14:31 PM PDT 24
Finished May 12 02:14:33 PM PDT 24
Peak memory 215232 kb
Host smart-ee5bee92-10c2-4c6d-a88c-dc92abe8b77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234946244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.234946244
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2229328159
Short name T415
Test name
Test status
Simulation time 109247428 ps
CPU time 1.53 seconds
Started May 12 02:14:26 PM PDT 24
Finished May 12 02:14:29 PM PDT 24
Peak memory 218492 kb
Host smart-9895ae54-aaae-4660-a899-81353c1b1f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229328159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2229328159
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2479520860
Short name T617
Test name
Test status
Simulation time 42993211 ps
CPU time 1.24 seconds
Started May 12 02:13:15 PM PDT 24
Finished May 12 02:13:16 PM PDT 24
Peak memory 215480 kb
Host smart-99ed80fd-fd81-439d-a775-38a0a2bbd58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479520860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2479520860
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.4156691944
Short name T420
Test name
Test status
Simulation time 28317925 ps
CPU time 1.01 seconds
Started May 12 02:13:08 PM PDT 24
Finished May 12 02:13:10 PM PDT 24
Peak memory 206540 kb
Host smart-28833182-7f91-4ce3-aa99-6cde344bcdd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156691944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.4156691944
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.4250344365
Short name T84
Test name
Test status
Simulation time 15458190 ps
CPU time 0.85 seconds
Started May 12 02:13:09 PM PDT 24
Finished May 12 02:13:10 PM PDT 24
Peak memory 216036 kb
Host smart-1414320b-0ed0-41ad-883a-c481c0c45e17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250344365 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.4250344365
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1366890519
Short name T343
Test name
Test status
Simulation time 69167421 ps
CPU time 1.16 seconds
Started May 12 02:13:11 PM PDT 24
Finished May 12 02:13:12 PM PDT 24
Peak memory 216736 kb
Host smart-5d63e693-9b02-4670-843e-3b4a715809fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366890519 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1366890519
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1264707674
Short name T449
Test name
Test status
Simulation time 31967997 ps
CPU time 0.88 seconds
Started May 12 02:13:11 PM PDT 24
Finished May 12 02:13:12 PM PDT 24
Peak memory 218172 kb
Host smart-3cc0686e-d2cb-415c-b1d4-9f1d71ef804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264707674 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1264707674
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.636461857
Short name T724
Test name
Test status
Simulation time 59429271 ps
CPU time 1.24 seconds
Started May 12 02:13:08 PM PDT 24
Finished May 12 02:13:09 PM PDT 24
Peak memory 216824 kb
Host smart-b0e04ed5-29ff-4e11-b5de-eb7df339ab19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636461857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.636461857
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3650534017
Short name T588
Test name
Test status
Simulation time 29318238 ps
CPU time 0.95 seconds
Started May 12 02:13:09 PM PDT 24
Finished May 12 02:13:10 PM PDT 24
Peak memory 215708 kb
Host smart-d078df70-9fd1-41e6-a34d-ec5f986283c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650534017 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3650534017
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2718484921
Short name T666
Test name
Test status
Simulation time 56896281 ps
CPU time 0.91 seconds
Started May 12 02:13:07 PM PDT 24
Finished May 12 02:13:08 PM PDT 24
Peak memory 215104 kb
Host smart-e82ee94a-364c-4fb5-aaac-d990850ea551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718484921 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2718484921
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3164196193
Short name T100
Test name
Test status
Simulation time 205684563 ps
CPU time 1.63 seconds
Started May 12 02:13:12 PM PDT 24
Finished May 12 02:13:14 PM PDT 24
Peak memory 217024 kb
Host smart-e703b34e-d06d-4b07-8b37-1246a040429f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164196193 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3164196193
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1586350630
Short name T495
Test name
Test status
Simulation time 500083165711 ps
CPU time 2317.42 seconds
Started May 12 02:13:12 PM PDT 24
Finished May 12 02:51:50 PM PDT 24
Peak memory 229420 kb
Host smart-bf42d64d-fc0d-4b1f-beab-7bfe2caa719a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586350630 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1586350630
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3435496364
Short name T273
Test name
Test status
Simulation time 32918200 ps
CPU time 1.4 seconds
Started May 12 02:14:27 PM PDT 24
Finished May 12 02:14:30 PM PDT 24
Peak memory 216976 kb
Host smart-e9b9936a-343f-42b6-b932-d19c1ba30703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435496364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3435496364
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2757657468
Short name T430
Test name
Test status
Simulation time 84776972 ps
CPU time 1.16 seconds
Started May 12 02:14:29 PM PDT 24
Finished May 12 02:14:31 PM PDT 24
Peak memory 219324 kb
Host smart-b847d538-03bb-4ce4-badf-fd70a840d2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757657468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2757657468
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.4231077089
Short name T364
Test name
Test status
Simulation time 83475201 ps
CPU time 1.22 seconds
Started May 12 02:14:30 PM PDT 24
Finished May 12 02:14:33 PM PDT 24
Peak memory 216720 kb
Host smart-89af2022-5c53-4251-aaf7-8c3cbc243355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231077089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.4231077089
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3312378159
Short name T668
Test name
Test status
Simulation time 31210021 ps
CPU time 1.27 seconds
Started May 12 02:14:30 PM PDT 24
Finished May 12 02:14:32 PM PDT 24
Peak memory 216724 kb
Host smart-e85dbcb0-e950-465d-bb50-4715e8f09b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312378159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3312378159
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.4174922109
Short name T462
Test name
Test status
Simulation time 295116823 ps
CPU time 4 seconds
Started May 12 02:14:26 PM PDT 24
Finished May 12 02:14:31 PM PDT 24
Peak memory 218532 kb
Host smart-923a62ff-d959-42af-8b79-ae3cc29c937e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174922109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.4174922109
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2906052160
Short name T613
Test name
Test status
Simulation time 104400666 ps
CPU time 1.5 seconds
Started May 12 02:14:36 PM PDT 24
Finished May 12 02:14:38 PM PDT 24
Peak memory 217060 kb
Host smart-fe924f03-f97e-410b-a108-713d213cd2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906052160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2906052160
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.44828065
Short name T701
Test name
Test status
Simulation time 158469281 ps
CPU time 1.39 seconds
Started May 12 02:14:35 PM PDT 24
Finished May 12 02:14:37 PM PDT 24
Peak memory 219708 kb
Host smart-52fbd3b2-6bf9-41c5-b0de-11489cbaf171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44828065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.44828065
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1247162348
Short name T686
Test name
Test status
Simulation time 53138384 ps
CPU time 1.39 seconds
Started May 12 02:14:36 PM PDT 24
Finished May 12 02:14:38 PM PDT 24
Peak memory 217080 kb
Host smart-c96d93a2-12d4-44c1-8923-568eb04064eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247162348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1247162348
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3029898951
Short name T126
Test name
Test status
Simulation time 45902096 ps
CPU time 1.66 seconds
Started May 12 02:14:31 PM PDT 24
Finished May 12 02:14:34 PM PDT 24
Peak memory 218092 kb
Host smart-74f5e9dd-29b7-4c94-9242-fd4e643add5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029898951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3029898951
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1171596999
Short name T829
Test name
Test status
Simulation time 28012636 ps
CPU time 1.31 seconds
Started May 12 02:13:14 PM PDT 24
Finished May 12 02:13:16 PM PDT 24
Peak memory 215528 kb
Host smart-b84fd600-32e3-4756-9703-0304bac15657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171596999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1171596999
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1550193644
Short name T556
Test name
Test status
Simulation time 16551870 ps
CPU time 1.02 seconds
Started May 12 02:13:24 PM PDT 24
Finished May 12 02:13:26 PM PDT 24
Peak memory 206224 kb
Host smart-e361fd86-eaa0-447f-9a65-343ed7256851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550193644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1550193644
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.759748304
Short name T66
Test name
Test status
Simulation time 21377912 ps
CPU time 0.9 seconds
Started May 12 02:13:24 PM PDT 24
Finished May 12 02:13:26 PM PDT 24
Peak memory 214944 kb
Host smart-77fdbf92-7914-4818-b3da-4f9413a4a6a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759748304 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.759748304
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1978311197
Short name T635
Test name
Test status
Simulation time 89159553 ps
CPU time 1.31 seconds
Started May 12 02:13:14 PM PDT 24
Finished May 12 02:13:16 PM PDT 24
Peak memory 216692 kb
Host smart-dfe55fef-24b6-4a78-94a2-c9562bdcd82d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978311197 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1978311197
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.658243423
Short name T67
Test name
Test status
Simulation time 20897868 ps
CPU time 1.17 seconds
Started May 12 02:13:13 PM PDT 24
Finished May 12 02:13:15 PM PDT 24
Peak memory 223844 kb
Host smart-6d9186e9-322d-49cf-9537-d73fb42a0318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658243423 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.658243423
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1397414756
Short name T484
Test name
Test status
Simulation time 93963801 ps
CPU time 1.23 seconds
Started May 12 02:13:12 PM PDT 24
Finished May 12 02:13:14 PM PDT 24
Peak memory 218040 kb
Host smart-b80240c0-eb54-4132-995f-ab53dfa31509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397414756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1397414756
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3686520343
Short name T341
Test name
Test status
Simulation time 21010846 ps
CPU time 1.07 seconds
Started May 12 02:13:13 PM PDT 24
Finished May 12 02:13:15 PM PDT 24
Peak memory 216728 kb
Host smart-9c62fd45-994b-4f34-9982-0c32d90be8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686520343 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3686520343
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3928823064
Short name T460
Test name
Test status
Simulation time 41798178 ps
CPU time 0.94 seconds
Started May 12 02:13:10 PM PDT 24
Finished May 12 02:13:12 PM PDT 24
Peak memory 215136 kb
Host smart-33b98eb6-a36f-4022-a70b-3ad686167e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928823064 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3928823064
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1935944647
Short name T672
Test name
Test status
Simulation time 167774369 ps
CPU time 3.58 seconds
Started May 12 02:13:24 PM PDT 24
Finished May 12 02:13:29 PM PDT 24
Peak memory 218716 kb
Host smart-823ca3bc-0dec-4c7d-accc-615c19626c51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935944647 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1935944647
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2392792947
Short name T607
Test name
Test status
Simulation time 36169045584 ps
CPU time 729.86 seconds
Started May 12 02:13:22 PM PDT 24
Finished May 12 02:25:33 PM PDT 24
Peak memory 223424 kb
Host smart-aeb0d6c7-d155-4553-9ea9-a0f6d3d1baa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392792947 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2392792947
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1612784636
Short name T790
Test name
Test status
Simulation time 84514369 ps
CPU time 1.12 seconds
Started May 12 02:14:28 PM PDT 24
Finished May 12 02:14:30 PM PDT 24
Peak memory 216940 kb
Host smart-f43046ba-43d2-467d-b191-37715bfd3402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612784636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1612784636
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.247400123
Short name T586
Test name
Test status
Simulation time 57523901 ps
CPU time 1.54 seconds
Started May 12 02:14:31 PM PDT 24
Finished May 12 02:14:34 PM PDT 24
Peak memory 218504 kb
Host smart-f83b237a-376b-457b-9d43-e7a5a637c384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247400123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.247400123
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3993953497
Short name T582
Test name
Test status
Simulation time 99751950 ps
CPU time 1.6 seconds
Started May 12 02:14:30 PM PDT 24
Finished May 12 02:14:32 PM PDT 24
Peak memory 218052 kb
Host smart-1b37f0f2-cc64-49c6-ba26-f7965f1a2361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993953497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3993953497
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.4011841967
Short name T745
Test name
Test status
Simulation time 98077785 ps
CPU time 1.55 seconds
Started May 12 02:14:30 PM PDT 24
Finished May 12 02:14:33 PM PDT 24
Peak memory 218496 kb
Host smart-3b086019-14c9-43b7-876e-1f7ba14a4fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011841967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.4011841967
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2184004896
Short name T393
Test name
Test status
Simulation time 30640720 ps
CPU time 1.19 seconds
Started May 12 02:14:29 PM PDT 24
Finished May 12 02:14:32 PM PDT 24
Peak memory 216812 kb
Host smart-e6db085a-f69e-4f3c-badf-247e18c6df70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184004896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2184004896
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2761975253
Short name T241
Test name
Test status
Simulation time 42066243 ps
CPU time 1.62 seconds
Started May 12 02:14:30 PM PDT 24
Finished May 12 02:14:33 PM PDT 24
Peak memory 219644 kb
Host smart-78de0fba-fca5-443b-9b19-71a954b3c73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761975253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2761975253
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3086277503
Short name T290
Test name
Test status
Simulation time 72399125 ps
CPU time 1.85 seconds
Started May 12 02:14:37 PM PDT 24
Finished May 12 02:14:40 PM PDT 24
Peak memory 218548 kb
Host smart-9da05035-b59e-4039-b9ec-d4137ec4a052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086277503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3086277503
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.85668737
Short name T721
Test name
Test status
Simulation time 98721499 ps
CPU time 1.05 seconds
Started May 12 02:14:34 PM PDT 24
Finished May 12 02:14:36 PM PDT 24
Peak memory 216896 kb
Host smart-8c0ab2a0-a06a-4d94-ba44-30a345bf3519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85668737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.85668737
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2173461552
Short name T824
Test name
Test status
Simulation time 22481425 ps
CPU time 1.14 seconds
Started May 12 02:14:30 PM PDT 24
Finished May 12 02:14:32 PM PDT 24
Peak memory 217048 kb
Host smart-a1e3c5d1-6493-42d2-9503-3ab26f0f161c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173461552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2173461552
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2161224466
Short name T603
Test name
Test status
Simulation time 94215533 ps
CPU time 1.51 seconds
Started May 12 02:14:33 PM PDT 24
Finished May 12 02:14:35 PM PDT 24
Peak memory 218460 kb
Host smart-fdfa197d-a340-4d0e-be63-18291b408b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161224466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2161224466
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3668495769
Short name T304
Test name
Test status
Simulation time 285343305 ps
CPU time 1.44 seconds
Started May 12 02:13:22 PM PDT 24
Finished May 12 02:13:24 PM PDT 24
Peak memory 215440 kb
Host smart-82bad417-4dbb-4f6c-952e-9a9e2062b1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668495769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3668495769
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1620464210
Short name T122
Test name
Test status
Simulation time 261527895 ps
CPU time 0.94 seconds
Started May 12 02:13:14 PM PDT 24
Finished May 12 02:13:16 PM PDT 24
Peak memory 206540 kb
Host smart-6d769fbd-e6dc-4934-967e-2c20482fb6f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620464210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1620464210
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2491560760
Short name T406
Test name
Test status
Simulation time 41334289 ps
CPU time 0.92 seconds
Started May 12 02:13:16 PM PDT 24
Finished May 12 02:13:17 PM PDT 24
Peak memory 216204 kb
Host smart-3b57b1c0-8091-4e0f-8bdc-fd7f5532804e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491560760 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2491560760
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.4063320356
Short name T693
Test name
Test status
Simulation time 141760523 ps
CPU time 1.16 seconds
Started May 12 02:13:18 PM PDT 24
Finished May 12 02:13:19 PM PDT 24
Peak memory 216764 kb
Host smart-db0cbd72-f493-4042-a065-b85c864f0809
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063320356 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.4063320356
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2933363704
Short name T483
Test name
Test status
Simulation time 23998739 ps
CPU time 0.97 seconds
Started May 12 02:13:13 PM PDT 24
Finished May 12 02:13:15 PM PDT 24
Peak memory 218412 kb
Host smart-e462577c-d6d5-4cf7-9f26-a98714baca5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933363704 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2933363704
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.474545799
Short name T682
Test name
Test status
Simulation time 62457466 ps
CPU time 1.37 seconds
Started May 12 02:13:24 PM PDT 24
Finished May 12 02:13:27 PM PDT 24
Peak memory 216836 kb
Host smart-3f2d83b4-f58a-49c6-9fda-9be7c274c907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474545799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.474545799
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1811962775
Short name T461
Test name
Test status
Simulation time 23044488 ps
CPU time 1.18 seconds
Started May 12 02:13:12 PM PDT 24
Finished May 12 02:13:14 PM PDT 24
Peak memory 215340 kb
Host smart-debe95e7-75c2-4add-a482-ce49155fa76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811962775 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1811962775
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2456875125
Short name T313
Test name
Test status
Simulation time 42788782 ps
CPU time 0.97 seconds
Started May 12 02:13:15 PM PDT 24
Finished May 12 02:13:16 PM PDT 24
Peak memory 215132 kb
Host smart-85c7a944-7f28-437f-b7f3-4b842c4541ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456875125 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2456875125
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.66726360
Short name T351
Test name
Test status
Simulation time 435972294 ps
CPU time 4.84 seconds
Started May 12 02:13:24 PM PDT 24
Finished May 12 02:13:30 PM PDT 24
Peak memory 214620 kb
Host smart-cd4d0fe7-b8d4-4f82-b5e2-013186a25432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66726360 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.66726360
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2119487618
Short name T111
Test name
Test status
Simulation time 66777062421 ps
CPU time 422.7 seconds
Started May 12 02:13:16 PM PDT 24
Finished May 12 02:20:19 PM PDT 24
Peak memory 217792 kb
Host smart-68327f15-eb5f-4408-af26-71b181054eea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119487618 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2119487618
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3694883166
Short name T821
Test name
Test status
Simulation time 45150145 ps
CPU time 1.73 seconds
Started May 12 02:14:34 PM PDT 24
Finished May 12 02:14:37 PM PDT 24
Peak memory 218264 kb
Host smart-1e94feb0-a86b-427e-8459-9d9fa83b4bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694883166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3694883166
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.4084028806
Short name T214
Test name
Test status
Simulation time 50722136 ps
CPU time 1.99 seconds
Started May 12 02:14:30 PM PDT 24
Finished May 12 02:14:33 PM PDT 24
Peak memory 217048 kb
Host smart-3db12792-76f4-49b6-a843-b105665b9655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084028806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.4084028806
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3261296239
Short name T455
Test name
Test status
Simulation time 43350007 ps
CPU time 1.61 seconds
Started May 12 02:14:36 PM PDT 24
Finished May 12 02:14:39 PM PDT 24
Peak memory 217896 kb
Host smart-0fe77572-3990-49d2-873e-a39e7478c1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261296239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3261296239
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1944898395
Short name T741
Test name
Test status
Simulation time 37843857 ps
CPU time 1.25 seconds
Started May 12 02:14:33 PM PDT 24
Finished May 12 02:14:35 PM PDT 24
Peak memory 218232 kb
Host smart-6e60e306-943b-46eb-b0c3-2902866be4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944898395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1944898395
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.313366585
Short name T703
Test name
Test status
Simulation time 81469178 ps
CPU time 1.34 seconds
Started May 12 02:14:30 PM PDT 24
Finished May 12 02:14:33 PM PDT 24
Peak memory 218244 kb
Host smart-b30cba37-fa35-4771-a39f-ce47f7b92918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313366585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.313366585
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.65729896
Short name T270
Test name
Test status
Simulation time 140723766 ps
CPU time 1.49 seconds
Started May 12 02:14:30 PM PDT 24
Finished May 12 02:14:33 PM PDT 24
Peak memory 218132 kb
Host smart-605c1bf5-5478-4da4-bc3b-bfbaa8f39c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65729896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.65729896
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1125082242
Short name T20
Test name
Test status
Simulation time 30146234 ps
CPU time 1.36 seconds
Started May 12 02:14:32 PM PDT 24
Finished May 12 02:14:34 PM PDT 24
Peak memory 218896 kb
Host smart-e70650e2-fc4d-4a59-9785-e8899c8a4edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125082242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1125082242
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2618904619
Short name T2
Test name
Test status
Simulation time 86340143 ps
CPU time 1.41 seconds
Started May 12 02:14:29 PM PDT 24
Finished May 12 02:14:32 PM PDT 24
Peak memory 216960 kb
Host smart-f2e620d5-d12d-45b2-9310-e419b5cf7542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618904619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2618904619
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.932629313
Short name T657
Test name
Test status
Simulation time 72181808 ps
CPU time 2.8 seconds
Started May 12 02:14:37 PM PDT 24
Finished May 12 02:14:41 PM PDT 24
Peak memory 219528 kb
Host smart-d929e440-9402-40df-b166-822266493653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932629313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.932629313
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.4223994131
Short name T592
Test name
Test status
Simulation time 36028190 ps
CPU time 1.25 seconds
Started May 12 02:14:35 PM PDT 24
Finished May 12 02:14:38 PM PDT 24
Peak memory 218048 kb
Host smart-518757b2-b7a4-4cd4-aa78-b0253cc4d8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223994131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.4223994131
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.4164108953
Short name T726
Test name
Test status
Simulation time 225548555 ps
CPU time 1.25 seconds
Started May 12 02:13:18 PM PDT 24
Finished May 12 02:13:20 PM PDT 24
Peak memory 215448 kb
Host smart-50dc9aed-0d05-4161-9ae3-4e84af62b163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164108953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.4164108953
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.4158365638
Short name T706
Test name
Test status
Simulation time 142708703 ps
CPU time 0.83 seconds
Started May 12 02:13:24 PM PDT 24
Finished May 12 02:13:25 PM PDT 24
Peak memory 206216 kb
Host smart-6d18be5d-b509-48df-9887-d68966dba0bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158365638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.4158365638
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3786014813
Short name T835
Test name
Test status
Simulation time 39510547 ps
CPU time 0.91 seconds
Started May 12 02:13:16 PM PDT 24
Finished May 12 02:13:18 PM PDT 24
Peak memory 216312 kb
Host smart-57418c4f-7c46-4a1d-87d1-a8c0004ebef7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786014813 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3786014813
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2615773454
Short name T42
Test name
Test status
Simulation time 43583724 ps
CPU time 1.43 seconds
Started May 12 02:13:19 PM PDT 24
Finished May 12 02:13:21 PM PDT 24
Peak memory 219196 kb
Host smart-b98d24f1-8a05-4697-a733-ce7f6202fa93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615773454 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2615773454
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.858612315
Short name T118
Test name
Test status
Simulation time 19464281 ps
CPU time 1.11 seconds
Started May 12 02:13:19 PM PDT 24
Finished May 12 02:13:21 PM PDT 24
Peak memory 223892 kb
Host smart-a0a0c0de-4e96-4fda-b2fb-4abf8b879ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858612315 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.858612315
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.410008729
Short name T814
Test name
Test status
Simulation time 38380043 ps
CPU time 1.45 seconds
Started May 12 02:13:18 PM PDT 24
Finished May 12 02:13:21 PM PDT 24
Peak memory 218240 kb
Host smart-fe149d8d-9f31-47bb-8d26-7b520f828829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410008729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.410008729
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_smoke.1433547826
Short name T124
Test name
Test status
Simulation time 18225552 ps
CPU time 0.97 seconds
Started May 12 02:13:15 PM PDT 24
Finished May 12 02:13:16 PM PDT 24
Peak memory 215152 kb
Host smart-991ad098-674c-4db0-8069-2f95696cd8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433547826 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1433547826
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2657323813
Short name T688
Test name
Test status
Simulation time 107648851 ps
CPU time 2.7 seconds
Started May 12 02:13:20 PM PDT 24
Finished May 12 02:13:23 PM PDT 24
Peak memory 215164 kb
Host smart-50bd0d76-3caf-48de-8871-fba6e8b696cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657323813 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2657323813
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3564344858
Short name T809
Test name
Test status
Simulation time 145888113385 ps
CPU time 616.19 seconds
Started May 12 02:13:18 PM PDT 24
Finished May 12 02:23:35 PM PDT 24
Peak memory 223608 kb
Host smart-55139639-f3a3-4965-b382-19828329cf22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564344858 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3564344858
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.4163557023
Short name T675
Test name
Test status
Simulation time 164734761 ps
CPU time 1.5 seconds
Started May 12 02:14:35 PM PDT 24
Finished May 12 02:14:37 PM PDT 24
Peak memory 218312 kb
Host smart-4dc987ec-ef81-4d4e-920f-750c4b2c8587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163557023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.4163557023
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2578520121
Short name T620
Test name
Test status
Simulation time 76021933 ps
CPU time 1.3 seconds
Started May 12 02:14:31 PM PDT 24
Finished May 12 02:14:34 PM PDT 24
Peak memory 216748 kb
Host smart-572ba65a-15b6-47bc-a013-dd7656a817c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578520121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2578520121
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1139624631
Short name T828
Test name
Test status
Simulation time 88464180 ps
CPU time 1.18 seconds
Started May 12 02:14:38 PM PDT 24
Finished May 12 02:14:40 PM PDT 24
Peak memory 219160 kb
Host smart-692ffb7e-1eaa-49a9-bce5-0fc43c19d585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139624631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1139624631
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3712545247
Short name T656
Test name
Test status
Simulation time 73749990 ps
CPU time 1.26 seconds
Started May 12 02:14:31 PM PDT 24
Finished May 12 02:14:33 PM PDT 24
Peak memory 218440 kb
Host smart-8b720279-4529-4a20-ba2d-9c71cd709929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712545247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3712545247
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1877379010
Short name T602
Test name
Test status
Simulation time 53426365 ps
CPU time 1.35 seconds
Started May 12 02:14:32 PM PDT 24
Finished May 12 02:14:34 PM PDT 24
Peak memory 218156 kb
Host smart-7e5d09e4-4820-45ad-ab2a-7923cda5f76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877379010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1877379010
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1409241060
Short name T758
Test name
Test status
Simulation time 177492625 ps
CPU time 3.15 seconds
Started May 12 02:14:52 PM PDT 24
Finished May 12 02:14:55 PM PDT 24
Peak memory 219908 kb
Host smart-e89da4c2-c4d1-4a51-8ccf-384843290808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409241060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1409241060
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3883115592
Short name T114
Test name
Test status
Simulation time 32361845 ps
CPU time 1.26 seconds
Started May 12 02:14:37 PM PDT 24
Finished May 12 02:14:39 PM PDT 24
Peak memory 216844 kb
Host smart-6785b007-3b0a-49c6-a29b-1e569c2747e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883115592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3883115592
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2440099002
Short name T769
Test name
Test status
Simulation time 36131863 ps
CPU time 1.06 seconds
Started May 12 02:14:34 PM PDT 24
Finished May 12 02:14:36 PM PDT 24
Peak memory 219316 kb
Host smart-97ede5f7-6e50-4ed5-88ac-4fb4e622ad9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440099002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2440099002
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3862470399
Short name T515
Test name
Test status
Simulation time 139628800 ps
CPU time 1.11 seconds
Started May 12 02:14:34 PM PDT 24
Finished May 12 02:14:36 PM PDT 24
Peak memory 218188 kb
Host smart-10b56b70-c1c8-41af-b7ae-2f5afd2704dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862470399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3862470399
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2890155771
Short name T437
Test name
Test status
Simulation time 76630028 ps
CPU time 1.15 seconds
Started May 12 02:14:34 PM PDT 24
Finished May 12 02:14:36 PM PDT 24
Peak memory 216908 kb
Host smart-55f3ba56-0237-46de-a442-1b1a9ded0651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890155771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2890155771
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2515916655
Short name T248
Test name
Test status
Simulation time 24730624 ps
CPU time 1.22 seconds
Started May 12 02:13:20 PM PDT 24
Finished May 12 02:13:22 PM PDT 24
Peak memory 215536 kb
Host smart-5a54b1c8-533b-48af-bca3-2d9d4a263e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515916655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2515916655
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.757585875
Short name T716
Test name
Test status
Simulation time 19936174 ps
CPU time 0.85 seconds
Started May 12 02:13:16 PM PDT 24
Finished May 12 02:13:18 PM PDT 24
Peak memory 206732 kb
Host smart-e4a71c14-ce3f-4e5a-b3fd-47bf246d3a5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757585875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.757585875
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.4161593421
Short name T591
Test name
Test status
Simulation time 15356231 ps
CPU time 0.89 seconds
Started May 12 02:13:17 PM PDT 24
Finished May 12 02:13:18 PM PDT 24
Peak memory 216272 kb
Host smart-0e789e8e-4203-421f-b12f-bc2d8d24fe27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161593421 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.4161593421
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.999055924
Short name T714
Test name
Test status
Simulation time 74817116 ps
CPU time 1.03 seconds
Started May 12 02:13:18 PM PDT 24
Finished May 12 02:13:19 PM PDT 24
Peak memory 217728 kb
Host smart-c35755d6-ed9b-4e7f-b69b-b0da2c61507c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999055924 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.999055924
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.118461554
Short name T32
Test name
Test status
Simulation time 34900023 ps
CPU time 1.11 seconds
Started May 12 02:13:16 PM PDT 24
Finished May 12 02:13:18 PM PDT 24
Peak memory 229416 kb
Host smart-3b6ab732-cca8-4a4e-8d6d-003c388e2386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118461554 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.118461554
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1335971536
Short name T382
Test name
Test status
Simulation time 245546978 ps
CPU time 1.65 seconds
Started May 12 02:13:18 PM PDT 24
Finished May 12 02:13:20 PM PDT 24
Peak memory 218716 kb
Host smart-2214c082-8683-4d60-b0d6-e7e52989578f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335971536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1335971536
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.523084793
Short name T137
Test name
Test status
Simulation time 26316656 ps
CPU time 0.97 seconds
Started May 12 02:13:17 PM PDT 24
Finished May 12 02:13:19 PM PDT 24
Peak memory 215672 kb
Host smart-f64d314a-ce85-432d-ae20-39de84dc08f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523084793 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.523084793
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.4166963422
Short name T610
Test name
Test status
Simulation time 37493932 ps
CPU time 0.94 seconds
Started May 12 02:13:17 PM PDT 24
Finished May 12 02:13:19 PM PDT 24
Peak memory 215108 kb
Host smart-cf87c8e8-7a05-4fd2-9719-2f32c837f3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166963422 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.4166963422
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3311217811
Short name T560
Test name
Test status
Simulation time 429112774 ps
CPU time 4.38 seconds
Started May 12 02:13:20 PM PDT 24
Finished May 12 02:13:25 PM PDT 24
Peak memory 218104 kb
Host smart-3caad889-fd1d-4210-a1a1-801103011c36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311217811 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3311217811
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2476995418
Short name T573
Test name
Test status
Simulation time 26470982664 ps
CPU time 711.58 seconds
Started May 12 02:13:23 PM PDT 24
Finished May 12 02:25:15 PM PDT 24
Peak memory 223452 kb
Host smart-05389ac8-f7f4-48ac-98cb-52e49a3faad6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476995418 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2476995418
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3100536970
Short name T373
Test name
Test status
Simulation time 138139236 ps
CPU time 1.06 seconds
Started May 12 02:14:35 PM PDT 24
Finished May 12 02:14:37 PM PDT 24
Peak memory 216888 kb
Host smart-6dc4870c-99dd-487d-bda3-a373ce682872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100536970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3100536970
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2788257588
Short name T779
Test name
Test status
Simulation time 66449751 ps
CPU time 1.85 seconds
Started May 12 02:14:34 PM PDT 24
Finished May 12 02:14:37 PM PDT 24
Peak memory 218076 kb
Host smart-aee7f74b-ee1c-4b1e-a2ae-9405a8423c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788257588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2788257588
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2021327840
Short name T742
Test name
Test status
Simulation time 81494104 ps
CPU time 1.58 seconds
Started May 12 02:14:33 PM PDT 24
Finished May 12 02:14:35 PM PDT 24
Peak memory 219716 kb
Host smart-9b732b9d-02a5-4934-a3ea-723c98e9d1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021327840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2021327840
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2367436005
Short name T596
Test name
Test status
Simulation time 29217609 ps
CPU time 1.23 seconds
Started May 12 02:14:34 PM PDT 24
Finished May 12 02:14:36 PM PDT 24
Peak memory 218096 kb
Host smart-10c942ba-fcf1-4116-8559-2b52a490801f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367436005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2367436005
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2092064519
Short name T432
Test name
Test status
Simulation time 72456343 ps
CPU time 1.86 seconds
Started May 12 02:14:33 PM PDT 24
Finished May 12 02:14:36 PM PDT 24
Peak memory 218252 kb
Host smart-eeae0215-1632-4e4d-88fe-74805ae1321a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092064519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2092064519
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.959922081
Short name T739
Test name
Test status
Simulation time 140528534 ps
CPU time 1.98 seconds
Started May 12 02:14:35 PM PDT 24
Finished May 12 02:14:38 PM PDT 24
Peak memory 218572 kb
Host smart-eefe8371-2db0-437c-abe3-61690a8d300b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959922081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.959922081
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1086655415
Short name T618
Test name
Test status
Simulation time 106109101 ps
CPU time 1.24 seconds
Started May 12 02:14:34 PM PDT 24
Finished May 12 02:14:36 PM PDT 24
Peak memory 219480 kb
Host smart-41b25e3b-759b-4aa4-aabe-15a60fa710d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086655415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1086655415
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1655448088
Short name T465
Test name
Test status
Simulation time 45642483 ps
CPU time 1.59 seconds
Started May 12 02:14:39 PM PDT 24
Finished May 12 02:14:42 PM PDT 24
Peak memory 218176 kb
Host smart-897dbc29-0db1-469a-8709-adc39f4b5297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655448088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1655448088
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert_test.3430137074
Short name T736
Test name
Test status
Simulation time 33146507 ps
CPU time 1.04 seconds
Started May 12 02:13:18 PM PDT 24
Finished May 12 02:13:19 PM PDT 24
Peak memory 206484 kb
Host smart-5edf5cac-ce83-446a-9b39-07548b787bee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430137074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3430137074
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1074273600
Short name T178
Test name
Test status
Simulation time 25798800 ps
CPU time 0.88 seconds
Started May 12 02:13:18 PM PDT 24
Finished May 12 02:13:20 PM PDT 24
Peak memory 216116 kb
Host smart-652813f7-7812-4291-884c-9d12b5fb73d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074273600 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1074273600
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2403007637
Short name T472
Test name
Test status
Simulation time 33584436 ps
CPU time 1.06 seconds
Started May 12 02:13:18 PM PDT 24
Finished May 12 02:13:20 PM PDT 24
Peak memory 218196 kb
Host smart-b40d20cb-c176-4710-bdbf-80732839cf3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403007637 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2403007637
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1271261418
Short name T60
Test name
Test status
Simulation time 24556668 ps
CPU time 1.29 seconds
Started May 12 02:13:18 PM PDT 24
Finished May 12 02:13:20 PM PDT 24
Peak memory 219644 kb
Host smart-9a22ac1a-fcc2-43f6-8b98-cd777c675377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271261418 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1271261418
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.307300121
Short name T491
Test name
Test status
Simulation time 55148240 ps
CPU time 1.51 seconds
Started May 12 02:13:15 PM PDT 24
Finished May 12 02:13:17 PM PDT 24
Peak memory 217312 kb
Host smart-2af64097-90c1-4a94-af73-4cf8630d5db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307300121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.307300121
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3576174893
Short name T152
Test name
Test status
Simulation time 33481244 ps
CPU time 0.86 seconds
Started May 12 02:13:15 PM PDT 24
Finished May 12 02:13:16 PM PDT 24
Peak memory 215732 kb
Host smart-567b13f4-ef9d-4251-a6f8-aabb606a0247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576174893 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3576174893
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2286601018
Short name T747
Test name
Test status
Simulation time 47413950 ps
CPU time 0.93 seconds
Started May 12 02:13:17 PM PDT 24
Finished May 12 02:13:19 PM PDT 24
Peak memory 215236 kb
Host smart-9149872a-07c1-4ce5-aa2d-35f8b1d99981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286601018 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2286601018
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1285802336
Short name T513
Test name
Test status
Simulation time 149274792 ps
CPU time 1.42 seconds
Started May 12 02:13:17 PM PDT 24
Finished May 12 02:13:19 PM PDT 24
Peak memory 207164 kb
Host smart-7ac6583a-4306-4e49-8e38-82636f4f4021
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285802336 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1285802336
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2156644822
Short name T190
Test name
Test status
Simulation time 137287843212 ps
CPU time 780.19 seconds
Started May 12 02:13:23 PM PDT 24
Finished May 12 02:26:24 PM PDT 24
Peak memory 219684 kb
Host smart-9b49eaa6-d78e-4a3f-b7d9-9572e14bd722
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156644822 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2156644822
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1284123086
Short name T202
Test name
Test status
Simulation time 59509507 ps
CPU time 1.47 seconds
Started May 12 02:14:39 PM PDT 24
Finished May 12 02:14:42 PM PDT 24
Peak memory 218112 kb
Host smart-bbd36888-6fdd-496a-9d5c-74f3562c9c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284123086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1284123086
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1171968013
Short name T531
Test name
Test status
Simulation time 46181199 ps
CPU time 1.55 seconds
Started May 12 02:14:35 PM PDT 24
Finished May 12 02:14:37 PM PDT 24
Peak memory 218172 kb
Host smart-0f4ef7f5-ebc9-483f-8353-dd2cf6e96bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171968013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1171968013
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3251511662
Short name T307
Test name
Test status
Simulation time 161078783 ps
CPU time 2.12 seconds
Started May 12 02:14:35 PM PDT 24
Finished May 12 02:14:38 PM PDT 24
Peak memory 219672 kb
Host smart-e4e32796-0a24-47e4-bdff-a31771a31aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251511662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3251511662
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1028027195
Short name T478
Test name
Test status
Simulation time 241882926 ps
CPU time 1.02 seconds
Started May 12 02:14:34 PM PDT 24
Finished May 12 02:14:36 PM PDT 24
Peak memory 216800 kb
Host smart-dece50c8-8fa4-4721-b6ff-54908165eacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028027195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1028027195
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.4041166470
Short name T532
Test name
Test status
Simulation time 112770004 ps
CPU time 1.2 seconds
Started May 12 02:14:33 PM PDT 24
Finished May 12 02:14:35 PM PDT 24
Peak memory 217020 kb
Host smart-87480e7b-edbb-4696-bdf2-56e07eb79779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041166470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.4041166470
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2692843957
Short name T21
Test name
Test status
Simulation time 73486814 ps
CPU time 1.45 seconds
Started May 12 02:14:41 PM PDT 24
Finished May 12 02:14:43 PM PDT 24
Peak memory 218388 kb
Host smart-bb6f2b86-e8f9-47c8-8c7b-8fe88fb6abe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692843957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2692843957
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1551171255
Short name T766
Test name
Test status
Simulation time 49164255 ps
CPU time 1.31 seconds
Started May 12 02:14:41 PM PDT 24
Finished May 12 02:14:43 PM PDT 24
Peak memory 216900 kb
Host smart-0be30e8b-b080-4e72-b56d-0898462bee66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551171255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1551171255
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1907524489
Short name T136
Test name
Test status
Simulation time 133905547 ps
CPU time 1.6 seconds
Started May 12 02:14:35 PM PDT 24
Finished May 12 02:14:37 PM PDT 24
Peak memory 218220 kb
Host smart-ed8d21f5-4775-4244-a848-ff1413f19887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907524489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1907524489
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.565050021
Short name T357
Test name
Test status
Simulation time 98897029 ps
CPU time 1.15 seconds
Started May 12 02:14:34 PM PDT 24
Finished May 12 02:14:36 PM PDT 24
Peak memory 217012 kb
Host smart-25638569-5e70-4bb2-bca0-a8f01afb80f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565050021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.565050021
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2461835698
Short name T548
Test name
Test status
Simulation time 24566854 ps
CPU time 1.17 seconds
Started May 12 02:12:37 PM PDT 24
Finished May 12 02:12:39 PM PDT 24
Peak memory 215560 kb
Host smart-c9ae6894-83ac-4c56-95f6-28b8ef974dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461835698 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2461835698
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.474359262
Short name T718
Test name
Test status
Simulation time 23198560 ps
CPU time 0.97 seconds
Started May 12 02:12:38 PM PDT 24
Finished May 12 02:12:39 PM PDT 24
Peak memory 206580 kb
Host smart-a7cf4643-11bf-4173-a1a4-43aec424cf68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474359262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.474359262
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3384652062
Short name T456
Test name
Test status
Simulation time 42142666 ps
CPU time 0.92 seconds
Started May 12 02:12:43 PM PDT 24
Finished May 12 02:12:45 PM PDT 24
Peak memory 216156 kb
Host smart-a64f2c66-8208-496e-8266-4402bc5f02d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384652062 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3384652062
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2249437497
Short name T404
Test name
Test status
Simulation time 48796677 ps
CPU time 1.17 seconds
Started May 12 02:12:43 PM PDT 24
Finished May 12 02:12:46 PM PDT 24
Peak memory 219312 kb
Host smart-1548b728-a42d-4c3f-a907-8d53fec31ec1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249437497 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2249437497
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.778752591
Short name T695
Test name
Test status
Simulation time 29883305 ps
CPU time 1.03 seconds
Started May 12 02:12:40 PM PDT 24
Finished May 12 02:12:42 PM PDT 24
Peak memory 223640 kb
Host smart-91df4f89-abc2-469d-a654-172adb99321e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778752591 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.778752591
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.453483164
Short name T755
Test name
Test status
Simulation time 81110263 ps
CPU time 1.09 seconds
Started May 12 02:12:45 PM PDT 24
Finished May 12 02:12:47 PM PDT 24
Peak memory 216764 kb
Host smart-5b67debb-1e76-4569-8119-c2394a1aa738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453483164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.453483164
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2547351086
Short name T156
Test name
Test status
Simulation time 28407414 ps
CPU time 0.95 seconds
Started May 12 02:12:38 PM PDT 24
Finished May 12 02:12:39 PM PDT 24
Peak memory 215400 kb
Host smart-34b2d188-5923-4dd4-8536-e78c79cf9c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547351086 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2547351086
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3866375097
Short name T17
Test name
Test status
Simulation time 1129692190 ps
CPU time 17.41 seconds
Started May 12 02:12:30 PM PDT 24
Finished May 12 02:12:48 PM PDT 24
Peak memory 237344 kb
Host smart-cd39663d-6d83-425e-9175-f426a5acc6f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866375097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3866375097
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2927075067
Short name T775
Test name
Test status
Simulation time 15245994 ps
CPU time 1.02 seconds
Started May 12 02:12:39 PM PDT 24
Finished May 12 02:12:41 PM PDT 24
Peak memory 215064 kb
Host smart-f8e6707c-fea7-43dd-9609-1f3a11105398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927075067 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2927075067
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3453892109
Short name T143
Test name
Test status
Simulation time 323025927 ps
CPU time 2.43 seconds
Started May 12 02:12:42 PM PDT 24
Finished May 12 02:12:45 PM PDT 24
Peak memory 215024 kb
Host smart-11efe7aa-63bd-4118-9bff-81443ca923e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453892109 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3453892109
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2979306773
Short name T197
Test name
Test status
Simulation time 100435020696 ps
CPU time 1314.1 seconds
Started May 12 02:12:43 PM PDT 24
Finished May 12 02:34:39 PM PDT 24
Peak memory 223164 kb
Host smart-e10c6e6c-de1a-416d-9175-40314e1db2f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979306773 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2979306773
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1003584789
Short name T659
Test name
Test status
Simulation time 25302525 ps
CPU time 1.23 seconds
Started May 12 02:13:22 PM PDT 24
Finished May 12 02:13:24 PM PDT 24
Peak memory 215544 kb
Host smart-7ac2b738-fe34-44c9-b6d0-eabe88d18c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003584789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1003584789
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3286783285
Short name T830
Test name
Test status
Simulation time 16319076 ps
CPU time 0.84 seconds
Started May 12 02:13:29 PM PDT 24
Finished May 12 02:13:32 PM PDT 24
Peak memory 206724 kb
Host smart-41f93c70-8236-4063-856c-6a97aac266e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286783285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3286783285
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1206701788
Short name T663
Test name
Test status
Simulation time 68697667 ps
CPU time 0.87 seconds
Started May 12 02:13:19 PM PDT 24
Finished May 12 02:13:21 PM PDT 24
Peak memory 215260 kb
Host smart-2fb255f7-ce58-4268-bfe1-8597049b36b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206701788 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1206701788
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3063155105
Short name T567
Test name
Test status
Simulation time 44441403 ps
CPU time 1.46 seconds
Started May 12 02:13:21 PM PDT 24
Finished May 12 02:13:24 PM PDT 24
Peak memory 216540 kb
Host smart-bbdf4d08-7e5b-466a-8e84-e267fc840506
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063155105 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3063155105
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.4024151365
Short name T609
Test name
Test status
Simulation time 39151140 ps
CPU time 0.89 seconds
Started May 12 02:13:20 PM PDT 24
Finished May 12 02:13:21 PM PDT 24
Peak memory 218208 kb
Host smart-cb7b39c6-6d29-41a1-86a9-df8d9aa3a253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024151365 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.4024151365
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3063826239
Short name T388
Test name
Test status
Simulation time 55932446 ps
CPU time 1.21 seconds
Started May 12 02:13:23 PM PDT 24
Finished May 12 02:13:24 PM PDT 24
Peak memory 219488 kb
Host smart-73e8d20d-bb3b-46a6-ab91-2cc9933e0a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063826239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3063826239
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.216030612
Short name T524
Test name
Test status
Simulation time 42657797 ps
CPU time 0.92 seconds
Started May 12 02:13:20 PM PDT 24
Finished May 12 02:13:21 PM PDT 24
Peak memory 215264 kb
Host smart-76439b26-7d39-4910-b82e-0ddc669785c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216030612 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.216030612
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2376818464
Short name T627
Test name
Test status
Simulation time 68747890 ps
CPU time 0.9 seconds
Started May 12 02:13:21 PM PDT 24
Finished May 12 02:13:22 PM PDT 24
Peak memory 215156 kb
Host smart-12c5c1db-e4d9-46ec-9c29-f70d83257a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376818464 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2376818464
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.687034921
Short name T800
Test name
Test status
Simulation time 189900660 ps
CPU time 3.99 seconds
Started May 12 02:13:22 PM PDT 24
Finished May 12 02:13:26 PM PDT 24
Peak memory 216696 kb
Host smart-85eaee15-9999-4f13-9a93-5606444229be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687034921 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.687034921
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2083736517
Short name T636
Test name
Test status
Simulation time 62888447582 ps
CPU time 663.96 seconds
Started May 12 02:13:29 PM PDT 24
Finished May 12 02:24:34 PM PDT 24
Peak memory 218568 kb
Host smart-fab86f3a-58c8-45f1-8795-6c213c6bfae3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083736517 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2083736517
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3194428915
Short name T253
Test name
Test status
Simulation time 37277490 ps
CPU time 1.1 seconds
Started May 12 02:13:27 PM PDT 24
Finished May 12 02:13:30 PM PDT 24
Peak memory 215436 kb
Host smart-622bf01a-719e-48c6-863e-6e57d06f8c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194428915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3194428915
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1332397493
Short name T696
Test name
Test status
Simulation time 22721073 ps
CPU time 0.83 seconds
Started May 12 02:13:21 PM PDT 24
Finished May 12 02:13:22 PM PDT 24
Peak memory 215120 kb
Host smart-1211423b-9756-4578-b07a-b8f185b5bb64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332397493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1332397493
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.4268498034
Short name T637
Test name
Test status
Simulation time 36318466 ps
CPU time 1.27 seconds
Started May 12 02:13:23 PM PDT 24
Finished May 12 02:13:25 PM PDT 24
Peak memory 216892 kb
Host smart-4bc5749c-005f-4fe6-b393-295589e78714
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268498034 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.4268498034
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.407719335
Short name T8
Test name
Test status
Simulation time 25802456 ps
CPU time 1.08 seconds
Started May 12 02:13:20 PM PDT 24
Finished May 12 02:13:22 PM PDT 24
Peak memory 229496 kb
Host smart-625c8ce4-826c-49dc-87ec-330b7439d04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407719335 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.407719335
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1901416708
Short name T440
Test name
Test status
Simulation time 27361959 ps
CPU time 1.24 seconds
Started May 12 02:13:23 PM PDT 24
Finished May 12 02:13:24 PM PDT 24
Peak memory 218864 kb
Host smart-8a7b4dbd-7f1a-4550-b218-ef2fe6bab9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901416708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1901416708
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3865544319
Short name T791
Test name
Test status
Simulation time 54185931 ps
CPU time 0.91 seconds
Started May 12 02:13:20 PM PDT 24
Finished May 12 02:13:22 PM PDT 24
Peak memory 223700 kb
Host smart-6c276845-5a80-425e-a3f5-97aae96372a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865544319 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3865544319
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3381416481
Short name T658
Test name
Test status
Simulation time 16654870 ps
CPU time 0.98 seconds
Started May 12 02:13:23 PM PDT 24
Finished May 12 02:13:24 PM PDT 24
Peak memory 215196 kb
Host smart-f172e6de-91b1-48c2-9ab2-7ce5c444f3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381416481 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3381416481
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1426462617
Short name T707
Test name
Test status
Simulation time 220954267 ps
CPU time 1.68 seconds
Started May 12 02:13:22 PM PDT 24
Finished May 12 02:13:24 PM PDT 24
Peak memory 215232 kb
Host smart-ebd5cd22-fbee-48b2-af20-e8186566a85b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426462617 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1426462617
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.578882812
Short name T485
Test name
Test status
Simulation time 160681430553 ps
CPU time 457.34 seconds
Started May 12 02:13:29 PM PDT 24
Finished May 12 02:21:08 PM PDT 24
Peak memory 218632 kb
Host smart-2afb3a1e-ca04-42d6-b1c9-7b4c707b906b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578882812 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.578882812
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.320858516
Short name T151
Test name
Test status
Simulation time 28174793 ps
CPU time 1.28 seconds
Started May 12 02:13:27 PM PDT 24
Finished May 12 02:13:30 PM PDT 24
Peak memory 215468 kb
Host smart-e24e73c1-2f65-4f00-99ac-2dabda0e8ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320858516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.320858516
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1168390770
Short name T815
Test name
Test status
Simulation time 30573399 ps
CPU time 0.98 seconds
Started May 12 02:13:21 PM PDT 24
Finished May 12 02:13:23 PM PDT 24
Peak memory 206396 kb
Host smart-f4c48007-29be-41f9-beb9-dfdaab30cb22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168390770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1168390770
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2077073583
Short name T70
Test name
Test status
Simulation time 17667879 ps
CPU time 0.85 seconds
Started May 12 02:13:28 PM PDT 24
Finished May 12 02:13:31 PM PDT 24
Peak memory 215988 kb
Host smart-39ba05d4-c156-40ed-b90c-4849fc426bf0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077073583 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2077073583
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.696611616
Short name T76
Test name
Test status
Simulation time 30526922 ps
CPU time 1.08 seconds
Started May 12 02:13:20 PM PDT 24
Finished May 12 02:13:22 PM PDT 24
Peak memory 223568 kb
Host smart-94c6360d-8cce-4a45-8031-3c1e23aee571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696611616 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.696611616
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3006825247
Short name T585
Test name
Test status
Simulation time 165511399 ps
CPU time 1.25 seconds
Started May 12 02:13:28 PM PDT 24
Finished May 12 02:13:31 PM PDT 24
Peak memory 219456 kb
Host smart-22642582-3bd2-4ff2-9440-6cd9f3c249fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006825247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3006825247
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1391868078
Short name T140
Test name
Test status
Simulation time 30970486 ps
CPU time 0.87 seconds
Started May 12 02:13:29 PM PDT 24
Finished May 12 02:13:31 PM PDT 24
Peak memory 215556 kb
Host smart-ec040c75-fa88-4151-985b-bd24f40e90df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391868078 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1391868078
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1235544838
Short name T767
Test name
Test status
Simulation time 49083094 ps
CPU time 0.96 seconds
Started May 12 02:13:20 PM PDT 24
Finished May 12 02:13:22 PM PDT 24
Peak memory 215148 kb
Host smart-adefda0e-81c5-467e-bfaa-d34b7181c57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235544838 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1235544838
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2156091030
Short name T367
Test name
Test status
Simulation time 187972956 ps
CPU time 3.95 seconds
Started May 12 02:13:22 PM PDT 24
Finished May 12 02:13:26 PM PDT 24
Peak memory 218844 kb
Host smart-afc79f0c-9875-4434-9399-af0233bc0196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156091030 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2156091030
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1295368815
Short name T198
Test name
Test status
Simulation time 124960986125 ps
CPU time 2792.55 seconds
Started May 12 02:13:30 PM PDT 24
Finished May 12 03:00:05 PM PDT 24
Peak memory 229156 kb
Host smart-3d212775-5b8c-494f-b4d7-60fd0aa3d3cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295368815 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1295368815
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3310588898
Short name T80
Test name
Test status
Simulation time 71592161 ps
CPU time 1.11 seconds
Started May 12 02:13:24 PM PDT 24
Finished May 12 02:13:27 PM PDT 24
Peak memory 215668 kb
Host smart-763b26dc-2f76-418a-a955-d546fedd3bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310588898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3310588898
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.4256358452
Short name T350
Test name
Test status
Simulation time 41424201 ps
CPU time 0.99 seconds
Started May 12 02:13:23 PM PDT 24
Finished May 12 02:13:24 PM PDT 24
Peak memory 206532 kb
Host smart-b88cb61a-e7f4-43d2-8e4f-1168f4fde6c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256358452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.4256358452
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3867503402
Short name T90
Test name
Test status
Simulation time 11804075 ps
CPU time 0.91 seconds
Started May 12 02:13:26 PM PDT 24
Finished May 12 02:13:29 PM PDT 24
Peak memory 216376 kb
Host smart-c7049d3f-5841-4717-b832-b55db941bd69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867503402 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3867503402
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1350580246
Short name T332
Test name
Test status
Simulation time 36805804 ps
CPU time 1.28 seconds
Started May 12 02:13:23 PM PDT 24
Finished May 12 02:13:25 PM PDT 24
Peak memory 216544 kb
Host smart-261088e0-4a26-4f64-b186-3bbee307f62b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350580246 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1350580246
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2883679138
Short name T69
Test name
Test status
Simulation time 22683175 ps
CPU time 0.96 seconds
Started May 12 02:13:25 PM PDT 24
Finished May 12 02:13:28 PM PDT 24
Peak memory 218404 kb
Host smart-756defd6-fe21-4f20-a577-ba63cdb5be3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883679138 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2883679138
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.741332745
Short name T468
Test name
Test status
Simulation time 165666642 ps
CPU time 1.34 seconds
Started May 12 02:13:28 PM PDT 24
Finished May 12 02:13:31 PM PDT 24
Peak memory 218276 kb
Host smart-8339472f-8f8e-4d5e-a981-e07ddb57598b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741332745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.741332745
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.337784990
Short name T756
Test name
Test status
Simulation time 25185489 ps
CPU time 1.04 seconds
Started May 12 02:13:23 PM PDT 24
Finished May 12 02:13:25 PM PDT 24
Peak memory 215744 kb
Host smart-a84b4e39-d075-46b0-9c41-9f667d3b0442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337784990 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.337784990
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.571497587
Short name T711
Test name
Test status
Simulation time 18739566 ps
CPU time 1.04 seconds
Started May 12 02:13:20 PM PDT 24
Finished May 12 02:13:22 PM PDT 24
Peak memory 215176 kb
Host smart-201f0740-464e-423d-82d5-add355f34011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571497587 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.571497587
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2578593932
Short name T211
Test name
Test status
Simulation time 142780166 ps
CPU time 2.03 seconds
Started May 12 02:13:26 PM PDT 24
Finished May 12 02:13:29 PM PDT 24
Peak memory 215168 kb
Host smart-85351c5f-aa0d-46f0-b6bb-2dc10cd30b3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578593932 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2578593932
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1440645529
Short name T281
Test name
Test status
Simulation time 86728177363 ps
CPU time 1113.1 seconds
Started May 12 02:13:24 PM PDT 24
Finished May 12 02:31:59 PM PDT 24
Peak memory 223620 kb
Host smart-19f59b91-82e2-4b00-90ea-e3c47a66ed61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440645529 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1440645529
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2716909092
Short name T683
Test name
Test status
Simulation time 25702353 ps
CPU time 1.27 seconds
Started May 12 02:13:28 PM PDT 24
Finished May 12 02:13:31 PM PDT 24
Peak memory 215464 kb
Host smart-3045be91-6097-45b5-900a-e9335dd5749e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716909092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2716909092
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3789137705
Short name T116
Test name
Test status
Simulation time 16010880 ps
CPU time 1 seconds
Started May 12 02:13:26 PM PDT 24
Finished May 12 02:13:28 PM PDT 24
Peak memory 206472 kb
Host smart-510c7b41-810b-4e5c-a2b9-d71fffb259cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789137705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3789137705
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1502343885
Short name T180
Test name
Test status
Simulation time 50742342 ps
CPU time 0.88 seconds
Started May 12 02:13:26 PM PDT 24
Finished May 12 02:13:28 PM PDT 24
Peak memory 215272 kb
Host smart-7d4969b2-9451-4f73-b873-75c8720ecc9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502343885 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1502343885
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.899856258
Short name T58
Test name
Test status
Simulation time 50685850 ps
CPU time 1.51 seconds
Started May 12 02:13:24 PM PDT 24
Finished May 12 02:13:26 PM PDT 24
Peak memory 216868 kb
Host smart-5eb094e9-1b60-4062-9974-b76e18c512bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899856258 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_di
sable_auto_req_mode.899856258
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.1152105717
Short name T53
Test name
Test status
Simulation time 26459974 ps
CPU time 1.08 seconds
Started May 12 02:13:23 PM PDT 24
Finished May 12 02:13:25 PM PDT 24
Peak memory 223800 kb
Host smart-9a486ec4-5686-4da4-934d-ac5d92146c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152105717 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1152105717
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.632092607
Short name T508
Test name
Test status
Simulation time 43144463 ps
CPU time 1.65 seconds
Started May 12 02:13:31 PM PDT 24
Finished May 12 02:13:34 PM PDT 24
Peak memory 219136 kb
Host smart-38b72af0-a5d1-4491-bdc0-387e6cbc38ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632092607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.632092607
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2362383726
Short name T546
Test name
Test status
Simulation time 47659054 ps
CPU time 0.99 seconds
Started May 12 02:13:24 PM PDT 24
Finished May 12 02:13:27 PM PDT 24
Peak memory 223668 kb
Host smart-26931669-0390-43b4-923a-a7e6adb08b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362383726 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2362383726
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.712391872
Short name T719
Test name
Test status
Simulation time 27854269 ps
CPU time 0.96 seconds
Started May 12 02:13:27 PM PDT 24
Finished May 12 02:13:30 PM PDT 24
Peak memory 215124 kb
Host smart-d4bae8da-1d74-46d2-9264-28577aa87de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712391872 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.712391872
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2316809080
Short name T390
Test name
Test status
Simulation time 92932972 ps
CPU time 1.14 seconds
Started May 12 02:13:26 PM PDT 24
Finished May 12 02:13:29 PM PDT 24
Peak memory 215348 kb
Host smart-03c6bccb-c554-4ec8-8828-ed89250ff46d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316809080 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2316809080
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3391523438
Short name T389
Test name
Test status
Simulation time 141145763461 ps
CPU time 960.93 seconds
Started May 12 02:13:28 PM PDT 24
Finished May 12 02:29:31 PM PDT 24
Peak memory 222180 kb
Host smart-0081efe5-8a24-42bb-92c7-7212a9547867
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391523438 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3391523438
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1154080389
Short name T149
Test name
Test status
Simulation time 46508938 ps
CPU time 1.23 seconds
Started May 12 02:13:32 PM PDT 24
Finished May 12 02:13:34 PM PDT 24
Peak memory 215388 kb
Host smart-2d0a0f61-5529-4463-9175-397bf208ad77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154080389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1154080389
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3711387732
Short name T743
Test name
Test status
Simulation time 67338550 ps
CPU time 0.98 seconds
Started May 12 02:13:26 PM PDT 24
Finished May 12 02:13:29 PM PDT 24
Peak memory 215076 kb
Host smart-9b16571e-dece-4dfe-adb0-243e0ae96207
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711387732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3711387732
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2700932802
Short name T166
Test name
Test status
Simulation time 13576649 ps
CPU time 0.93 seconds
Started May 12 02:13:30 PM PDT 24
Finished May 12 02:13:33 PM PDT 24
Peak memory 216340 kb
Host smart-89c9a77e-ce9d-4d49-bda9-856804adc154
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700932802 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2700932802
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1065254971
Short name T63
Test name
Test status
Simulation time 33244113 ps
CPU time 1.2 seconds
Started May 12 02:13:25 PM PDT 24
Finished May 12 02:13:27 PM PDT 24
Peak memory 216676 kb
Host smart-b621f1cd-341c-4dd9-9120-c701e16b2797
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065254971 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1065254971
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3386408783
Short name T802
Test name
Test status
Simulation time 19186636 ps
CPU time 1.05 seconds
Started May 12 02:13:29 PM PDT 24
Finished May 12 02:13:32 PM PDT 24
Peak memory 218200 kb
Host smart-31c526de-2d69-45ed-946d-c473be790ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386408783 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3386408783
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3266140194
Short name T256
Test name
Test status
Simulation time 63116226 ps
CPU time 1.62 seconds
Started May 12 02:13:31 PM PDT 24
Finished May 12 02:13:34 PM PDT 24
Peak memory 218416 kb
Host smart-ec75fe9c-7db4-4689-bd5b-1ff12ebe14a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266140194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3266140194
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.410546981
Short name T399
Test name
Test status
Simulation time 33741120 ps
CPU time 0.9 seconds
Started May 12 02:13:23 PM PDT 24
Finished May 12 02:13:25 PM PDT 24
Peak memory 215360 kb
Host smart-7fe1dbb1-7f4f-4a38-8281-d9a8117755a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410546981 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.410546981
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.701067496
Short name T376
Test name
Test status
Simulation time 24076168 ps
CPU time 0.94 seconds
Started May 12 02:13:22 PM PDT 24
Finished May 12 02:13:23 PM PDT 24
Peak memory 215156 kb
Host smart-055b2a67-4c6f-44cb-ac6f-e567a7b2e0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701067496 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.701067496
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2647531006
Short name T439
Test name
Test status
Simulation time 832406867 ps
CPU time 4.82 seconds
Started May 12 02:13:24 PM PDT 24
Finished May 12 02:13:31 PM PDT 24
Peak memory 219368 kb
Host smart-bd1e3914-f0f4-457c-8514-4a92f425df8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647531006 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2647531006
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1218440678
Short name T196
Test name
Test status
Simulation time 48051965903 ps
CPU time 284.48 seconds
Started May 12 02:13:26 PM PDT 24
Finished May 12 02:18:12 PM PDT 24
Peak memory 218400 kb
Host smart-38862b8c-e287-42f5-92f1-cf47c8f12fc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218440678 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1218440678
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3178925905
Short name T798
Test name
Test status
Simulation time 25351022 ps
CPU time 1.39 seconds
Started May 12 02:13:30 PM PDT 24
Finished May 12 02:13:33 PM PDT 24
Peak memory 215496 kb
Host smart-165ffbfd-d66c-42d8-8f6a-fce4a9554584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178925905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3178925905
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.581333616
Short name T473
Test name
Test status
Simulation time 17709391 ps
CPU time 0.96 seconds
Started May 12 02:13:25 PM PDT 24
Finished May 12 02:13:27 PM PDT 24
Peak memory 214664 kb
Host smart-e3c82116-3fd3-4bef-97a8-60068a71a523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581333616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.581333616
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1006943196
Short name T466
Test name
Test status
Simulation time 44739700 ps
CPU time 0.88 seconds
Started May 12 02:13:26 PM PDT 24
Finished May 12 02:13:28 PM PDT 24
Peak memory 215744 kb
Host smart-ef972c86-fc9a-4ea4-b9d8-3961880c8c5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006943196 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1006943196
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.4165010433
Short name T730
Test name
Test status
Simulation time 31496812 ps
CPU time 1.17 seconds
Started May 12 02:13:25 PM PDT 24
Finished May 12 02:13:27 PM PDT 24
Peak memory 217780 kb
Host smart-1326a6a1-378b-4049-a4f9-cb4f6bc7b069
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165010433 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.4165010433
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1073035413
Short name T164
Test name
Test status
Simulation time 31181084 ps
CPU time 0.95 seconds
Started May 12 02:13:26 PM PDT 24
Finished May 12 02:13:28 PM PDT 24
Peak memory 218464 kb
Host smart-50fe703c-198a-49c4-a000-bb543c1bdce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073035413 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1073035413
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1673967211
Short name T308
Test name
Test status
Simulation time 54749964 ps
CPU time 1.31 seconds
Started May 12 02:13:22 PM PDT 24
Finished May 12 02:13:24 PM PDT 24
Peak memory 219056 kb
Host smart-e1ef8585-2bd5-4379-99fb-fc6bf5ca00c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673967211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1673967211
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3256553095
Short name T785
Test name
Test status
Simulation time 32198774 ps
CPU time 1.04 seconds
Started May 12 02:13:30 PM PDT 24
Finished May 12 02:13:33 PM PDT 24
Peak memory 223848 kb
Host smart-21773eb1-c847-4692-a356-4b3f56aeca59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256553095 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3256553095
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1248372928
Short name T309
Test name
Test status
Simulation time 29519625 ps
CPU time 0.96 seconds
Started May 12 02:13:29 PM PDT 24
Finished May 12 02:13:32 PM PDT 24
Peak memory 215096 kb
Host smart-8f007646-05f6-4198-9525-e4b3b144eb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248372928 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1248372928
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3365476946
Short name T125
Test name
Test status
Simulation time 231048993 ps
CPU time 2.33 seconds
Started May 12 02:13:26 PM PDT 24
Finished May 12 02:13:30 PM PDT 24
Peak memory 215100 kb
Host smart-19a22976-87d8-4626-834a-812d27ddf264
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365476946 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3365476946
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1895921905
Short name T768
Test name
Test status
Simulation time 288892178843 ps
CPU time 1844.34 seconds
Started May 12 02:13:23 PM PDT 24
Finished May 12 02:44:09 PM PDT 24
Peak memory 228456 kb
Host smart-49666967-70d9-4966-8e4a-f2b83a5c0ff8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895921905 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1895921905
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.185088214
Short name T73
Test name
Test status
Simulation time 24398424 ps
CPU time 1.17 seconds
Started May 12 02:13:26 PM PDT 24
Finished May 12 02:13:28 PM PDT 24
Peak memory 215532 kb
Host smart-793c1d8e-b491-40b7-beca-8a5356d68e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185088214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.185088214
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1496523312
Short name T499
Test name
Test status
Simulation time 50070746 ps
CPU time 0.92 seconds
Started May 12 02:13:25 PM PDT 24
Finished May 12 02:13:28 PM PDT 24
Peak memory 214712 kb
Host smart-73311981-0497-41c7-b32f-7e0eff8f192e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496523312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1496523312
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2939917971
Short name T158
Test name
Test status
Simulation time 11893077 ps
CPU time 0.88 seconds
Started May 12 02:13:31 PM PDT 24
Finished May 12 02:13:33 PM PDT 24
Peak memory 216012 kb
Host smart-47aae1e5-eac8-4182-86ec-d92e7df3c1b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939917971 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2939917971
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1001238271
Short name T648
Test name
Test status
Simulation time 23472637 ps
CPU time 1.17 seconds
Started May 12 02:13:32 PM PDT 24
Finished May 12 02:13:34 PM PDT 24
Peak memory 217780 kb
Host smart-ff1987a2-6482-4024-8bcc-baeb1330d7e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001238271 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1001238271
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2670231453
Short name T795
Test name
Test status
Simulation time 18773591 ps
CPU time 1.07 seconds
Started May 12 02:13:25 PM PDT 24
Finished May 12 02:13:28 PM PDT 24
Peak memory 218408 kb
Host smart-e02ae9c3-0ddf-4229-81a2-5ae4ea87bfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670231453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2670231453
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2743054075
Short name T517
Test name
Test status
Simulation time 39557760 ps
CPU time 1.25 seconds
Started May 12 02:13:29 PM PDT 24
Finished May 12 02:13:32 PM PDT 24
Peak memory 216864 kb
Host smart-17482b17-79c0-40a7-8191-84e3f64e6293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743054075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2743054075
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2408019025
Short name T402
Test name
Test status
Simulation time 20853040 ps
CPU time 1.22 seconds
Started May 12 02:13:32 PM PDT 24
Finished May 12 02:13:34 PM PDT 24
Peak memory 223700 kb
Host smart-0a9fb5fb-fea0-41de-96d8-bf75e060b674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408019025 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2408019025
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3380324313
Short name T710
Test name
Test status
Simulation time 49482275 ps
CPU time 0.93 seconds
Started May 12 02:13:25 PM PDT 24
Finished May 12 02:13:27 PM PDT 24
Peak memory 215140 kb
Host smart-da062a38-24c8-4d59-8509-85ae53f8d4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380324313 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3380324313
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.945189375
Short name T576
Test name
Test status
Simulation time 218774320 ps
CPU time 1.68 seconds
Started May 12 02:13:31 PM PDT 24
Finished May 12 02:13:34 PM PDT 24
Peak memory 215116 kb
Host smart-65250783-c75e-4459-8dec-1051f20dd4b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945189375 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.945189375
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2863172380
Short name T751
Test name
Test status
Simulation time 72769436348 ps
CPU time 1788.73 seconds
Started May 12 02:13:25 PM PDT 24
Finished May 12 02:43:15 PM PDT 24
Peak memory 226836 kb
Host smart-b007bcca-3567-4d9a-92a8-e74dcfa796c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863172380 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2863172380
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1008202379
Short name T98
Test name
Test status
Simulation time 65490774 ps
CPU time 1.17 seconds
Started May 12 02:13:35 PM PDT 24
Finished May 12 02:13:37 PM PDT 24
Peak memory 215492 kb
Host smart-3b41e641-276b-4ede-bc49-4e325ffb234d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008202379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1008202379
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3535244332
Short name T204
Test name
Test status
Simulation time 20998275 ps
CPU time 1.02 seconds
Started May 12 02:13:30 PM PDT 24
Finished May 12 02:13:33 PM PDT 24
Peak memory 214764 kb
Host smart-2cf9e426-f2d6-4de2-9f88-fbe709f4f016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535244332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3535244332
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.488014443
Short name T36
Test name
Test status
Simulation time 51845073 ps
CPU time 1.27 seconds
Started May 12 02:13:26 PM PDT 24
Finished May 12 02:13:28 PM PDT 24
Peak memory 216812 kb
Host smart-93a12cc2-4558-4f1e-9171-bac9a149b8df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488014443 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.488014443
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3427917848
Short name T78
Test name
Test status
Simulation time 18785402 ps
CPU time 1.06 seconds
Started May 12 02:13:27 PM PDT 24
Finished May 12 02:13:30 PM PDT 24
Peak memory 218168 kb
Host smart-c3bf2d74-bda6-4b34-8922-50344ad86862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427917848 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3427917848
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.948014719
Short name T14
Test name
Test status
Simulation time 45363284 ps
CPU time 1.64 seconds
Started May 12 02:13:29 PM PDT 24
Finished May 12 02:13:32 PM PDT 24
Peak memory 218172 kb
Host smart-6fe2ff1f-26d8-4e72-8b0b-530b2bf30eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948014719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.948014719
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3879465320
Short name T677
Test name
Test status
Simulation time 24265869 ps
CPU time 1 seconds
Started May 12 02:13:26 PM PDT 24
Finished May 12 02:13:29 PM PDT 24
Peak memory 215388 kb
Host smart-ca711f96-0ab9-475e-9b66-cd03cd222625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879465320 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3879465320
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.4278194188
Short name T510
Test name
Test status
Simulation time 65724999 ps
CPU time 0.92 seconds
Started May 12 02:13:32 PM PDT 24
Finished May 12 02:13:34 PM PDT 24
Peak memory 214996 kb
Host smart-1a1545dd-36de-4eb9-8caa-ef544b5e2df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278194188 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.4278194188
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3409500951
Short name T561
Test name
Test status
Simulation time 396062449 ps
CPU time 1.99 seconds
Started May 12 02:13:32 PM PDT 24
Finished May 12 02:13:35 PM PDT 24
Peak memory 216860 kb
Host smart-c7f07313-3c82-45ce-b092-ef5c47301d35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409500951 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3409500951
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1277155544
Short name T621
Test name
Test status
Simulation time 104737441425 ps
CPU time 1615.67 seconds
Started May 12 02:13:32 PM PDT 24
Finished May 12 02:40:30 PM PDT 24
Peak memory 224880 kb
Host smart-12456417-2526-4c34-a5cc-61b74eda5a9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277155544 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1277155544
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.823443116
Short name T150
Test name
Test status
Simulation time 88269564 ps
CPU time 1.22 seconds
Started May 12 02:13:26 PM PDT 24
Finished May 12 02:13:29 PM PDT 24
Peak memory 215464 kb
Host smart-9332c754-f24c-4aff-af37-c19dbeec1eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823443116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.823443116
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.771616099
Short name T386
Test name
Test status
Simulation time 24900961 ps
CPU time 0.9 seconds
Started May 12 02:13:28 PM PDT 24
Finished May 12 02:13:30 PM PDT 24
Peak memory 206552 kb
Host smart-2532f8b4-4149-46fd-8f17-5f4ed98ab0bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771616099 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.771616099
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2206636197
Short name T179
Test name
Test status
Simulation time 14068016 ps
CPU time 0.95 seconds
Started May 12 02:13:31 PM PDT 24
Finished May 12 02:13:33 PM PDT 24
Peak memory 215468 kb
Host smart-cf06acf1-f059-49f9-b1e3-c86fffe2463b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206636197 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2206636197
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.959601398
Short name T57
Test name
Test status
Simulation time 32090479 ps
CPU time 1.24 seconds
Started May 12 02:13:27 PM PDT 24
Finished May 12 02:13:30 PM PDT 24
Peak memory 216632 kb
Host smart-e5ac3b2c-b459-4e77-9fbe-4df9c605c6e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959601398 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.959601398
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.217659024
Short name T89
Test name
Test status
Simulation time 22306623 ps
CPU time 1.06 seconds
Started May 12 02:13:33 PM PDT 24
Finished May 12 02:13:36 PM PDT 24
Peak memory 223804 kb
Host smart-e9ae0f7b-9cb8-4af8-aa1f-faa9701739f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217659024 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.217659024
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1088042977
Short name T283
Test name
Test status
Simulation time 69941254 ps
CPU time 2.38 seconds
Started May 12 02:13:35 PM PDT 24
Finished May 12 02:13:38 PM PDT 24
Peak memory 219672 kb
Host smart-00eb35fa-24cc-4740-a4c8-bc84305b1a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088042977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1088042977
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1168039126
Short name T109
Test name
Test status
Simulation time 24804853 ps
CPU time 1.02 seconds
Started May 12 02:13:29 PM PDT 24
Finished May 12 02:13:32 PM PDT 24
Peak memory 215892 kb
Host smart-c458bb21-3135-4629-9564-0ba3c9c90ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168039126 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1168039126
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2612180987
Short name T652
Test name
Test status
Simulation time 191451717 ps
CPU time 1.01 seconds
Started May 12 02:13:27 PM PDT 24
Finished May 12 02:13:30 PM PDT 24
Peak memory 206928 kb
Host smart-da4ec4b7-672f-4056-ae57-10986fd0737e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612180987 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2612180987
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1244637766
Short name T598
Test name
Test status
Simulation time 307424422 ps
CPU time 6.86 seconds
Started May 12 02:13:26 PM PDT 24
Finished May 12 02:13:35 PM PDT 24
Peak memory 218072 kb
Host smart-d859a91c-39ae-4ef6-871f-617b518e69d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244637766 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1244637766
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2950017684
Short name T200
Test name
Test status
Simulation time 79543390081 ps
CPU time 920.75 seconds
Started May 12 02:13:31 PM PDT 24
Finished May 12 02:28:54 PM PDT 24
Peak memory 219560 kb
Host smart-478a3a9b-1f64-4c1d-9aef-b59a51e012e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950017684 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2950017684
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1770103876
Short name T240
Test name
Test status
Simulation time 50905270 ps
CPU time 1.2 seconds
Started May 12 02:12:41 PM PDT 24
Finished May 12 02:12:43 PM PDT 24
Peak memory 215572 kb
Host smart-ab349bbf-b7f9-40a5-aac1-190d759807a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770103876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1770103876
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1760812240
Short name T792
Test name
Test status
Simulation time 30750950 ps
CPU time 1.23 seconds
Started May 12 02:12:38 PM PDT 24
Finished May 12 02:12:40 PM PDT 24
Peak memory 206572 kb
Host smart-33764f73-7b92-4a95-97d8-e1d44597f2c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760812240 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1760812240
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1634767992
Short name T765
Test name
Test status
Simulation time 31710114 ps
CPU time 0.84 seconds
Started May 12 02:12:40 PM PDT 24
Finished May 12 02:12:42 PM PDT 24
Peak memory 215736 kb
Host smart-d827539e-c612-4c24-97fe-5af51fa1e729
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634767992 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1634767992
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1339294587
Short name T169
Test name
Test status
Simulation time 24248617 ps
CPU time 1.07 seconds
Started May 12 02:12:38 PM PDT 24
Finished May 12 02:12:40 PM PDT 24
Peak memory 216644 kb
Host smart-dfc9a66e-0566-42ac-8ebe-e284f558d905
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339294587 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1339294587
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1862661817
Short name T580
Test name
Test status
Simulation time 47207662 ps
CPU time 0.84 seconds
Started May 12 02:12:42 PM PDT 24
Finished May 12 02:12:44 PM PDT 24
Peak memory 218208 kb
Host smart-5d41538b-ee87-48b7-9302-b7de039d5188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862661817 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1862661817
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.924015427
Short name T371
Test name
Test status
Simulation time 61167615 ps
CPU time 1.05 seconds
Started May 12 02:12:41 PM PDT 24
Finished May 12 02:12:43 PM PDT 24
Peak memory 217016 kb
Host smart-951d9147-9b29-4663-98b6-ef6c522e1a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924015427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.924015427
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.321739177
Short name T401
Test name
Test status
Simulation time 21126212 ps
CPU time 1.14 seconds
Started May 12 02:12:42 PM PDT 24
Finished May 12 02:12:44 PM PDT 24
Peak memory 215264 kb
Host smart-def38d0e-f4ca-410c-8e33-e42cd9b47443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321739177 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.321739177
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1730185876
Short name T120
Test name
Test status
Simulation time 470121496 ps
CPU time 4.19 seconds
Started May 12 02:12:44 PM PDT 24
Finished May 12 02:12:50 PM PDT 24
Peak memory 236204 kb
Host smart-3dbf90af-2b92-43b6-84b4-63cc0362fefc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730185876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1730185876
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3764650888
Short name T506
Test name
Test status
Simulation time 46121657 ps
CPU time 0.97 seconds
Started May 12 02:12:42 PM PDT 24
Finished May 12 02:12:44 PM PDT 24
Peak memory 215184 kb
Host smart-480cc925-11f0-4d97-9dfa-95483522863f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764650888 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3764650888
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3245622848
Short name T153
Test name
Test status
Simulation time 155895254 ps
CPU time 2.02 seconds
Started May 12 02:12:44 PM PDT 24
Finished May 12 02:12:47 PM PDT 24
Peak memory 216716 kb
Host smart-4f03890a-c6ae-4ebb-b6e8-101708b72e35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245622848 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3245622848
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3269173412
Short name T189
Test name
Test status
Simulation time 61468913867 ps
CPU time 410.06 seconds
Started May 12 02:12:42 PM PDT 24
Finished May 12 02:19:33 PM PDT 24
Peak memory 223572 kb
Host smart-9487c279-552b-4af9-82d8-17867b8a278e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269173412 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3269173412
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.3181562866
Short name T184
Test name
Test status
Simulation time 30237165 ps
CPU time 1.31 seconds
Started May 12 02:13:33 PM PDT 24
Finished May 12 02:13:36 PM PDT 24
Peak memory 215468 kb
Host smart-970e5f6c-19a6-4d34-aa31-3ea9cd2eb4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181562866 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3181562866
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2054199366
Short name T497
Test name
Test status
Simulation time 22701294 ps
CPU time 0.87 seconds
Started May 12 02:13:29 PM PDT 24
Finished May 12 02:13:31 PM PDT 24
Peak memory 214880 kb
Host smart-01f9a017-532c-40c1-882f-9e70e69391b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054199366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2054199366
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.309801360
Short name T845
Test name
Test status
Simulation time 47538888 ps
CPU time 0.87 seconds
Started May 12 02:13:29 PM PDT 24
Finished May 12 02:13:32 PM PDT 24
Peak memory 215200 kb
Host smart-4bb376e2-5d9d-442d-b492-ef081a71bfed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309801360 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.309801360
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3994700150
Short name T403
Test name
Test status
Simulation time 32828577 ps
CPU time 1.17 seconds
Started May 12 02:13:28 PM PDT 24
Finished May 12 02:13:31 PM PDT 24
Peak memory 218044 kb
Host smart-c9207c35-58e3-4a98-9d0f-0c9f74bbdb23
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994700150 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3994700150
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2755704023
Short name T46
Test name
Test status
Simulation time 38440830 ps
CPU time 1.07 seconds
Started May 12 02:13:32 PM PDT 24
Finished May 12 02:13:34 PM PDT 24
Peak memory 220476 kb
Host smart-cfae588d-f508-4167-9f27-b532c9ab942a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755704023 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2755704023
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1232514245
Short name T832
Test name
Test status
Simulation time 77754322 ps
CPU time 1.44 seconds
Started May 12 02:13:27 PM PDT 24
Finished May 12 02:13:30 PM PDT 24
Peak memory 218436 kb
Host smart-a82d33c1-025c-453f-804d-79c2422ec453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232514245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1232514245
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2033198769
Short name T457
Test name
Test status
Simulation time 21473423 ps
CPU time 1 seconds
Started May 12 02:13:35 PM PDT 24
Finished May 12 02:13:37 PM PDT 24
Peak memory 215628 kb
Host smart-1fa28fdc-a1bc-4210-b19e-89c370de2878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033198769 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2033198769
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2849511278
Short name T451
Test name
Test status
Simulation time 18060150 ps
CPU time 1.05 seconds
Started May 12 02:13:30 PM PDT 24
Finished May 12 02:13:33 PM PDT 24
Peak memory 215120 kb
Host smart-c3ec5af8-8faf-4c11-9c70-ddd9f9312abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849511278 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2849511278
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1096698567
Short name T213
Test name
Test status
Simulation time 319744064 ps
CPU time 3.66 seconds
Started May 12 02:13:33 PM PDT 24
Finished May 12 02:13:38 PM PDT 24
Peak memory 216908 kb
Host smart-792a23ae-ff31-497d-8e4d-1552e846c4d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096698567 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1096698567
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3893956377
Short name T192
Test name
Test status
Simulation time 410148990648 ps
CPU time 1203.25 seconds
Started May 12 02:13:33 PM PDT 24
Finished May 12 02:33:37 PM PDT 24
Peak memory 224392 kb
Host smart-5d6b66fa-0d61-4330-aac0-abd977c8588a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893956377 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3893956377
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1289914045
Short name T757
Test name
Test status
Simulation time 26130545 ps
CPU time 1.3 seconds
Started May 12 02:13:31 PM PDT 24
Finished May 12 02:13:34 PM PDT 24
Peak memory 215492 kb
Host smart-6d94dc39-83dc-49f9-bf00-0fac1031f01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289914045 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1289914045
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.419971735
Short name T467
Test name
Test status
Simulation time 29105677 ps
CPU time 0.92 seconds
Started May 12 02:13:31 PM PDT 24
Finished May 12 02:13:33 PM PDT 24
Peak memory 206500 kb
Host smart-50b971dd-e159-4f80-91fc-f1eab49eb6dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419971735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.419971735
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2342470084
Short name T374
Test name
Test status
Simulation time 42847247 ps
CPU time 1.06 seconds
Started May 12 02:13:32 PM PDT 24
Finished May 12 02:13:35 PM PDT 24
Peak memory 216620 kb
Host smart-d6669118-498c-45f2-98bc-549cd00af570
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342470084 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2342470084
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3553112029
Short name T400
Test name
Test status
Simulation time 27059191 ps
CPU time 1.17 seconds
Started May 12 02:13:30 PM PDT 24
Finished May 12 02:13:33 PM PDT 24
Peak memory 220544 kb
Host smart-7e7c33ec-5f39-4d9f-b069-d6a206872a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553112029 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3553112029
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2152185123
Short name T746
Test name
Test status
Simulation time 32860919 ps
CPU time 1.32 seconds
Started May 12 02:13:30 PM PDT 24
Finished May 12 02:13:33 PM PDT 24
Peak memory 217068 kb
Host smart-650ec180-16df-433c-8962-d46eac24baa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152185123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2152185123
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2827872347
Short name T639
Test name
Test status
Simulation time 24769483 ps
CPU time 1.08 seconds
Started May 12 02:13:31 PM PDT 24
Finished May 12 02:13:33 PM PDT 24
Peak memory 215244 kb
Host smart-cd2ebf8e-1261-4e0a-9448-2f328ee37a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827872347 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2827872347
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2812473346
Short name T146
Test name
Test status
Simulation time 28216997 ps
CPU time 0.95 seconds
Started May 12 02:13:28 PM PDT 24
Finished May 12 02:13:30 PM PDT 24
Peak memory 215104 kb
Host smart-eed87e0b-4b4e-44c5-b749-b8b3dc45e9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812473346 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2812473346
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1465268706
Short name T480
Test name
Test status
Simulation time 98514563 ps
CPU time 1.02 seconds
Started May 12 02:13:29 PM PDT 24
Finished May 12 02:13:32 PM PDT 24
Peak memory 207164 kb
Host smart-04c584e7-f989-4f97-b1b5-d73d41971a0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465268706 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1465268706
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1588801380
Short name T836
Test name
Test status
Simulation time 16898451780 ps
CPU time 288.81 seconds
Started May 12 02:13:26 PM PDT 24
Finished May 12 02:18:17 PM PDT 24
Peak memory 217576 kb
Host smart-97b49f6a-64bf-4249-b109-cb5443992c1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588801380 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1588801380
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3350477145
Short name T297
Test name
Test status
Simulation time 168605507 ps
CPU time 1.48 seconds
Started May 12 02:13:29 PM PDT 24
Finished May 12 02:13:33 PM PDT 24
Peak memory 215524 kb
Host smart-67a82e6f-6b95-437f-85fb-9b0d9a0f6fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350477145 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3350477145
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1417270167
Short name T552
Test name
Test status
Simulation time 54547040 ps
CPU time 0.85 seconds
Started May 12 02:13:35 PM PDT 24
Finished May 12 02:13:37 PM PDT 24
Peak memory 206424 kb
Host smart-68f8c5cf-4677-43ba-9af3-25eebe497939
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417270167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1417270167
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.4070794086
Short name T394
Test name
Test status
Simulation time 11698488 ps
CPU time 0.89 seconds
Started May 12 02:13:33 PM PDT 24
Finished May 12 02:13:35 PM PDT 24
Peak memory 215804 kb
Host smart-cce8266d-49a4-41e4-9901-f0cd2e202545
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070794086 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.4070794086
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.453919440
Short name T155
Test name
Test status
Simulation time 74564859 ps
CPU time 1.33 seconds
Started May 12 02:13:33 PM PDT 24
Finished May 12 02:13:36 PM PDT 24
Peak memory 219052 kb
Host smart-2a649832-b1f7-4c41-bd9b-310221c23c4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453919440 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.453919440
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.810377068
Short name T717
Test name
Test status
Simulation time 23533517 ps
CPU time 0.98 seconds
Started May 12 02:13:34 PM PDT 24
Finished May 12 02:13:36 PM PDT 24
Peak memory 218468 kb
Host smart-85f8b6d4-9a0c-4079-97c9-d00e288732ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810377068 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.810377068
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.601459127
Short name T570
Test name
Test status
Simulation time 34381189 ps
CPU time 1.43 seconds
Started May 12 02:13:25 PM PDT 24
Finished May 12 02:13:28 PM PDT 24
Peak memory 216776 kb
Host smart-f2e60b9b-d81a-4064-a354-316f3cd6e445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601459127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.601459127
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.457717190
Short name T105
Test name
Test status
Simulation time 19891903 ps
CPU time 1.11 seconds
Started May 12 02:13:28 PM PDT 24
Finished May 12 02:13:31 PM PDT 24
Peak memory 215904 kb
Host smart-556b288d-a941-4b5d-be77-e09724902836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457717190 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.457717190
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.4289997893
Short name T368
Test name
Test status
Simulation time 26596723 ps
CPU time 0.97 seconds
Started May 12 02:13:28 PM PDT 24
Finished May 12 02:13:30 PM PDT 24
Peak memory 215112 kb
Host smart-ebba3f78-508f-453f-a29c-f5aca9d1cff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289997893 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.4289997893
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3153002137
Short name T339
Test name
Test status
Simulation time 197088332 ps
CPU time 2.77 seconds
Started May 12 02:13:33 PM PDT 24
Finished May 12 02:13:37 PM PDT 24
Peak memory 216560 kb
Host smart-7ee4e217-ed54-4c4b-ae4a-cc4d2dd71c9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153002137 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3153002137
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2625565405
Short name T750
Test name
Test status
Simulation time 26682397184 ps
CPU time 495.93 seconds
Started May 12 02:13:29 PM PDT 24
Finished May 12 02:21:47 PM PDT 24
Peak memory 223524 kb
Host smart-de5b178f-e095-4cd1-a33a-52bc770b0417
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625565405 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2625565405
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.3507776756
Short name T79
Test name
Test status
Simulation time 67187110 ps
CPU time 1.08 seconds
Started May 12 02:13:33 PM PDT 24
Finished May 12 02:13:36 PM PDT 24
Peak memory 215740 kb
Host smart-00531727-a569-4503-b4a6-ad50b33407c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507776756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3507776756
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.4208838776
Short name T355
Test name
Test status
Simulation time 29523786 ps
CPU time 0.93 seconds
Started May 12 02:13:34 PM PDT 24
Finished May 12 02:13:37 PM PDT 24
Peak memory 206440 kb
Host smart-bece13b0-fa18-413d-8254-5fc06e376ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208838776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.4208838776
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2537884383
Short name T427
Test name
Test status
Simulation time 14144558 ps
CPU time 0.96 seconds
Started May 12 02:13:32 PM PDT 24
Finished May 12 02:13:35 PM PDT 24
Peak memory 215416 kb
Host smart-f24ae5a3-6aba-46f3-bc37-752e787d6714
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537884383 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2537884383
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1508415155
Short name T167
Test name
Test status
Simulation time 66372743 ps
CPU time 1.04 seconds
Started May 12 02:13:36 PM PDT 24
Finished May 12 02:13:39 PM PDT 24
Peak memory 216568 kb
Host smart-125384d7-8815-4978-99e6-1d1483be96d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508415155 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1508415155
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2376036878
Short name T628
Test name
Test status
Simulation time 33020928 ps
CPU time 1 seconds
Started May 12 02:13:31 PM PDT 24
Finished May 12 02:13:33 PM PDT 24
Peak memory 223728 kb
Host smart-580a3341-b0ce-444b-a460-2f2a3c545e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376036878 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2376036878
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1837329198
Short name T321
Test name
Test status
Simulation time 132327796 ps
CPU time 1.21 seconds
Started May 12 02:13:34 PM PDT 24
Finished May 12 02:13:36 PM PDT 24
Peak memory 219368 kb
Host smart-d4f9d507-f707-4a15-ace4-300a928a5e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837329198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1837329198
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2162534651
Short name T823
Test name
Test status
Simulation time 28888204 ps
CPU time 1.13 seconds
Started May 12 02:13:30 PM PDT 24
Finished May 12 02:13:33 PM PDT 24
Peak memory 224080 kb
Host smart-c8aa3a56-a6d8-406d-ab00-0410918f94af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162534651 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2162534651
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.995072711
Short name T538
Test name
Test status
Simulation time 17243820 ps
CPU time 1.02 seconds
Started May 12 02:13:32 PM PDT 24
Finished May 12 02:13:34 PM PDT 24
Peak memory 215284 kb
Host smart-ce46e097-bd66-4df9-bf2e-11927af8df2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995072711 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.995072711
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.934744309
Short name T144
Test name
Test status
Simulation time 353799958 ps
CPU time 6.91 seconds
Started May 12 02:13:32 PM PDT 24
Finished May 12 02:13:40 PM PDT 24
Peak memory 216744 kb
Host smart-adcf5a3f-af95-4e48-a2ad-ef4ae1bed8a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934744309 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.934744309
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_alert.943998638
Short name T34
Test name
Test status
Simulation time 88381279 ps
CPU time 1.29 seconds
Started May 12 02:13:34 PM PDT 24
Finished May 12 02:13:36 PM PDT 24
Peak memory 215444 kb
Host smart-90c318a1-9820-4edb-b3bd-cef1013cce7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943998638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.943998638
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.562113125
Short name T788
Test name
Test status
Simulation time 20513730 ps
CPU time 1 seconds
Started May 12 02:13:35 PM PDT 24
Finished May 12 02:13:37 PM PDT 24
Peak memory 206468 kb
Host smart-5136f1be-e7ad-4140-94b8-dd8af058b91a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562113125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.562113125
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.405891208
Short name T51
Test name
Test status
Simulation time 84241372 ps
CPU time 1.05 seconds
Started May 12 02:13:34 PM PDT 24
Finished May 12 02:13:36 PM PDT 24
Peak memory 219216 kb
Host smart-ca1285b8-d320-4c22-8107-9dc64228359c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405891208 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.405891208
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2433880185
Short name T816
Test name
Test status
Simulation time 58232758 ps
CPU time 1.13 seconds
Started May 12 02:13:33 PM PDT 24
Finished May 12 02:13:36 PM PDT 24
Peak memory 219560 kb
Host smart-5edbc77f-d7da-4492-b7c5-d52011c2853e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433880185 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2433880185
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2961897982
Short name T594
Test name
Test status
Simulation time 74079263 ps
CPU time 1.19 seconds
Started May 12 02:13:34 PM PDT 24
Finished May 12 02:13:36 PM PDT 24
Peak memory 216848 kb
Host smart-9da6b192-8e54-4b45-a79f-1e773b591bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961897982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2961897982
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3264354068
Short name T763
Test name
Test status
Simulation time 19800641 ps
CPU time 1.07 seconds
Started May 12 02:13:33 PM PDT 24
Finished May 12 02:13:36 PM PDT 24
Peak memory 215604 kb
Host smart-1ff65ec8-fe44-4e34-885c-7ca0d9deb3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264354068 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3264354068
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.18245641
Short name T593
Test name
Test status
Simulation time 27066403 ps
CPU time 0.97 seconds
Started May 12 02:13:29 PM PDT 24
Finished May 12 02:13:31 PM PDT 24
Peak memory 215172 kb
Host smart-598448fc-ea45-4cbc-90db-1f0ca3858891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18245641 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.18245641
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2087515367
Short name T825
Test name
Test status
Simulation time 148485303 ps
CPU time 2.88 seconds
Started May 12 02:13:34 PM PDT 24
Finished May 12 02:13:38 PM PDT 24
Peak memory 217996 kb
Host smart-3ca6d693-2f39-46e6-8cb5-3311a3f29eb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087515367 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2087515367
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3995415036
Short name T793
Test name
Test status
Simulation time 19527945171 ps
CPU time 486.45 seconds
Started May 12 02:13:31 PM PDT 24
Finished May 12 02:21:39 PM PDT 24
Peak memory 218228 kb
Host smart-188a6d64-a1bc-4fd3-938d-dc0ad35e0317
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995415036 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3995415036
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3779319743
Short name T266
Test name
Test status
Simulation time 45333867 ps
CPU time 1.16 seconds
Started May 12 02:13:36 PM PDT 24
Finished May 12 02:13:39 PM PDT 24
Peak memory 215496 kb
Host smart-be132ed7-5dd0-4ff5-a509-56698ca56849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779319743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3779319743
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1487084978
Short name T748
Test name
Test status
Simulation time 56950000 ps
CPU time 0.87 seconds
Started May 12 02:13:37 PM PDT 24
Finished May 12 02:13:39 PM PDT 24
Peak memory 214652 kb
Host smart-c0dfad0a-4dd1-43bd-ac72-c7c7814cb38f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487084978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1487084978
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2742519112
Short name T606
Test name
Test status
Simulation time 14049209 ps
CPU time 0.95 seconds
Started May 12 02:13:41 PM PDT 24
Finished May 12 02:13:42 PM PDT 24
Peak memory 215912 kb
Host smart-e205837e-61a6-442b-89cc-eb9e4ad1b064
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742519112 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2742519112
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1229705939
Short name T584
Test name
Test status
Simulation time 35601593 ps
CPU time 1.3 seconds
Started May 12 02:13:37 PM PDT 24
Finished May 12 02:13:40 PM PDT 24
Peak memory 216564 kb
Host smart-85947bfb-99c6-4388-bddc-5a6636f0a411
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229705939 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1229705939
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1720677417
Short name T590
Test name
Test status
Simulation time 25206616 ps
CPU time 1.09 seconds
Started May 12 02:13:34 PM PDT 24
Finished May 12 02:13:37 PM PDT 24
Peak memory 219716 kb
Host smart-ad8f0915-9c5d-4e08-a997-dd2cf5478f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720677417 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1720677417
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.252398015
Short name T697
Test name
Test status
Simulation time 92439567 ps
CPU time 1.35 seconds
Started May 12 02:13:32 PM PDT 24
Finished May 12 02:13:34 PM PDT 24
Peak memory 219460 kb
Host smart-94412c6f-66f8-4e95-8284-c9fc6dbaad3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252398015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.252398015
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2465277974
Short name T481
Test name
Test status
Simulation time 40508617 ps
CPU time 1.04 seconds
Started May 12 02:13:35 PM PDT 24
Finished May 12 02:13:37 PM PDT 24
Peak memory 223580 kb
Host smart-37063b1f-384b-495e-bd67-b86d9ee254e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465277974 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2465277974
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2644420710
Short name T595
Test name
Test status
Simulation time 15136830 ps
CPU time 1.01 seconds
Started May 12 02:13:35 PM PDT 24
Finished May 12 02:13:37 PM PDT 24
Peak memory 215136 kb
Host smart-c3689f04-486a-46f9-9dbc-5fe9accdbdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644420710 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2644420710
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2552396814
Short name T626
Test name
Test status
Simulation time 437908392 ps
CPU time 2.83 seconds
Started May 12 02:13:34 PM PDT 24
Finished May 12 02:13:38 PM PDT 24
Peak memory 216768 kb
Host smart-2ce8640f-bf16-4f21-92b1-26ba8fe017ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552396814 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2552396814
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2558625297
Short name T505
Test name
Test status
Simulation time 268614126455 ps
CPU time 1471.28 seconds
Started May 12 02:13:38 PM PDT 24
Finished May 12 02:38:10 PM PDT 24
Peak memory 223492 kb
Host smart-d4f4a4d9-3d94-45ae-bd81-84dc1bdd9ce1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558625297 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2558625297
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2497347146
Short name T186
Test name
Test status
Simulation time 34138841 ps
CPU time 1.38 seconds
Started May 12 02:13:35 PM PDT 24
Finished May 12 02:13:38 PM PDT 24
Peak memory 215436 kb
Host smart-00dc8e63-6e28-4080-9ad7-37a0fd5a7b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497347146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2497347146
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4257134657
Short name T702
Test name
Test status
Simulation time 45116099 ps
CPU time 0.89 seconds
Started May 12 02:13:38 PM PDT 24
Finished May 12 02:13:40 PM PDT 24
Peak memory 214748 kb
Host smart-6d3b5f6b-b889-4394-8347-9e55ca08a384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257134657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4257134657
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.896745425
Short name T811
Test name
Test status
Simulation time 12751019 ps
CPU time 0.9 seconds
Started May 12 02:13:39 PM PDT 24
Finished May 12 02:13:41 PM PDT 24
Peak memory 215212 kb
Host smart-0ce304ed-ddc3-4c3b-a109-5b7062eb4c6b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896745425 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.896745425
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1229431375
Short name T50
Test name
Test status
Simulation time 76089281 ps
CPU time 1.11 seconds
Started May 12 02:13:36 PM PDT 24
Finished May 12 02:13:38 PM PDT 24
Peak memory 219552 kb
Host smart-eebd0853-c267-4c85-a7b9-5d90a4bf726e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229431375 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1229431375
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1407353258
Short name T804
Test name
Test status
Simulation time 34382849 ps
CPU time 1.08 seconds
Started May 12 02:13:39 PM PDT 24
Finished May 12 02:13:41 PM PDT 24
Peak memory 223668 kb
Host smart-69e254db-5808-4b70-b3e9-75079d234948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407353258 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1407353258
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1800039854
Short name T720
Test name
Test status
Simulation time 47420845 ps
CPU time 1.71 seconds
Started May 12 02:13:36 PM PDT 24
Finished May 12 02:13:39 PM PDT 24
Peak memory 219556 kb
Host smart-1fd704da-0a3e-4cbb-9e2a-f58c174cdddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800039854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1800039854
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1333690060
Short name T210
Test name
Test status
Simulation time 32487351 ps
CPU time 0.95 seconds
Started May 12 02:13:34 PM PDT 24
Finished May 12 02:13:36 PM PDT 24
Peak memory 215264 kb
Host smart-5314ce64-249d-443e-9423-4a77662d04f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333690060 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1333690060
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.83188219
Short name T801
Test name
Test status
Simulation time 18360034 ps
CPU time 1.1 seconds
Started May 12 02:13:40 PM PDT 24
Finished May 12 02:13:41 PM PDT 24
Peak memory 215132 kb
Host smart-c24a368c-ab99-4f1b-89fd-2fd81c150076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83188219 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.83188219
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3642239229
Short name T660
Test name
Test status
Simulation time 354135444 ps
CPU time 2.54 seconds
Started May 12 02:13:34 PM PDT 24
Finished May 12 02:13:38 PM PDT 24
Peak memory 216772 kb
Host smart-ca998b40-6728-494e-ad27-d93096f652e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642239229 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3642239229
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2001082250
Short name T847
Test name
Test status
Simulation time 20447620690 ps
CPU time 536.58 seconds
Started May 12 02:13:37 PM PDT 24
Finished May 12 02:22:35 PM PDT 24
Peak memory 219940 kb
Host smart-3f704d7a-ad95-4274-af0d-35465c1b6053
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001082250 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2001082250
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1021317628
Short name T299
Test name
Test status
Simulation time 98806525 ps
CPU time 1.16 seconds
Started May 12 02:13:38 PM PDT 24
Finished May 12 02:13:40 PM PDT 24
Peak memory 215488 kb
Host smart-49c61f55-c65d-4bbf-95c3-44fb811a5354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021317628 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1021317628
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2445407816
Short name T123
Test name
Test status
Simulation time 34157945 ps
CPU time 0.81 seconds
Started May 12 02:13:41 PM PDT 24
Finished May 12 02:13:42 PM PDT 24
Peak memory 206756 kb
Host smart-8063e341-190e-40b2-a1c2-4d556887fa15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445407816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2445407816
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.349819622
Short name T470
Test name
Test status
Simulation time 20322764 ps
CPU time 0.87 seconds
Started May 12 02:13:39 PM PDT 24
Finished May 12 02:13:40 PM PDT 24
Peak memory 215888 kb
Host smart-88cfea10-3bad-44d9-ac42-d0db50cabcd8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349819622 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.349819622
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2456830768
Short name T599
Test name
Test status
Simulation time 50091089 ps
CPU time 1.17 seconds
Started May 12 02:13:45 PM PDT 24
Finished May 12 02:13:47 PM PDT 24
Peak memory 216892 kb
Host smart-83788c15-6e37-4914-a523-9d442853da73
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456830768 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2456830768
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3983817349
Short name T81
Test name
Test status
Simulation time 38861250 ps
CPU time 1.02 seconds
Started May 12 02:13:39 PM PDT 24
Finished May 12 02:13:40 PM PDT 24
Peak memory 223912 kb
Host smart-a66cfece-2d06-47f3-8c02-f87775c40904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983817349 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3983817349
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2098587468
Short name T753
Test name
Test status
Simulation time 98498311 ps
CPU time 1.38 seconds
Started May 12 02:13:39 PM PDT 24
Finished May 12 02:13:41 PM PDT 24
Peak memory 219300 kb
Host smart-9d1d6f9f-0597-4c36-9349-c4f773c2df44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098587468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2098587468
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_smoke.1955822277
Short name T674
Test name
Test status
Simulation time 41834060 ps
CPU time 0.88 seconds
Started May 12 02:13:36 PM PDT 24
Finished May 12 02:13:38 PM PDT 24
Peak memory 215128 kb
Host smart-cc5f3ba1-451f-48a6-8050-799a72321ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955822277 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1955822277
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.125736804
Short name T604
Test name
Test status
Simulation time 424658703 ps
CPU time 4.67 seconds
Started May 12 02:13:38 PM PDT 24
Finished May 12 02:13:44 PM PDT 24
Peak memory 216976 kb
Host smart-7f571d74-be9a-4fbd-879a-92787018e9a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125736804 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.125736804
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3345630593
Short name T199
Test name
Test status
Simulation time 296662489502 ps
CPU time 1661.49 seconds
Started May 12 02:13:39 PM PDT 24
Finished May 12 02:41:21 PM PDT 24
Peak memory 224480 kb
Host smart-57c396ee-d664-4457-a4ae-e232cda64c0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345630593 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3345630593
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2630645457
Short name T252
Test name
Test status
Simulation time 42382250 ps
CPU time 1.13 seconds
Started May 12 02:13:48 PM PDT 24
Finished May 12 02:13:50 PM PDT 24
Peak memory 215508 kb
Host smart-d9eaa7b7-4c0a-4e14-9c51-b5aa0a4126b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630645457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2630645457
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3618136593
Short name T507
Test name
Test status
Simulation time 42561331 ps
CPU time 0.86 seconds
Started May 12 02:13:48 PM PDT 24
Finished May 12 02:13:50 PM PDT 24
Peak memory 214524 kb
Host smart-501627d7-1e51-42bc-94d3-4c6655b32836
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618136593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3618136593
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2787162742
Short name T159
Test name
Test status
Simulation time 28673112 ps
CPU time 0.89 seconds
Started May 12 02:13:46 PM PDT 24
Finished May 12 02:13:47 PM PDT 24
Peak memory 216152 kb
Host smart-6ea7d0db-3335-4394-827f-2df321430d2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787162742 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2787162742
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1215882057
Short name T174
Test name
Test status
Simulation time 95027856 ps
CPU time 1.16 seconds
Started May 12 02:13:47 PM PDT 24
Finished May 12 02:13:49 PM PDT 24
Peak memory 219404 kb
Host smart-df6e8a77-fb33-4d33-91a2-d9e1481ca287
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215882057 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1215882057
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.663372189
Short name T551
Test name
Test status
Simulation time 28713556 ps
CPU time 1.4 seconds
Started May 12 02:13:48 PM PDT 24
Finished May 12 02:13:50 PM PDT 24
Peak memory 224584 kb
Host smart-811fd3ad-9414-46ed-8e5e-3027a8502dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663372189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.663372189
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.603937733
Short name T434
Test name
Test status
Simulation time 46230474 ps
CPU time 1.35 seconds
Started May 12 02:13:49 PM PDT 24
Finished May 12 02:13:51 PM PDT 24
Peak memory 217996 kb
Host smart-e091e9fd-c8c5-4ddc-beb4-9e305631179c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603937733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.603937733
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2887417335
Short name T583
Test name
Test status
Simulation time 24238596 ps
CPU time 1.08 seconds
Started May 12 02:13:45 PM PDT 24
Finished May 12 02:13:47 PM PDT 24
Peak memory 215312 kb
Host smart-d86381ee-e6c1-4ecf-9eaa-7c91cc9a7bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887417335 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2887417335
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2299229297
Short name T523
Test name
Test status
Simulation time 30608456 ps
CPU time 0.97 seconds
Started May 12 02:13:42 PM PDT 24
Finished May 12 02:13:44 PM PDT 24
Peak memory 215152 kb
Host smart-52323a71-6e69-4add-9288-383dd5f8a292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299229297 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2299229297
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.506420584
Short name T566
Test name
Test status
Simulation time 159419837 ps
CPU time 3.72 seconds
Started May 12 02:13:44 PM PDT 24
Finished May 12 02:13:48 PM PDT 24
Peak memory 216872 kb
Host smart-605faec2-6995-4c50-9f07-b9aa3d3644bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506420584 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.506420584
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_alert.1697212583
Short name T35
Test name
Test status
Simulation time 40165286 ps
CPU time 1.19 seconds
Started May 12 02:13:51 PM PDT 24
Finished May 12 02:13:53 PM PDT 24
Peak memory 215528 kb
Host smart-e849d817-6cf2-4344-86cd-9140dfb8a12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697212583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1697212583
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.579362285
Short name T338
Test name
Test status
Simulation time 14767947 ps
CPU time 0.86 seconds
Started May 12 02:13:50 PM PDT 24
Finished May 12 02:13:52 PM PDT 24
Peak memory 206520 kb
Host smart-7d99bdd2-e364-44a5-8126-6a1c7e44d252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579362285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.579362285
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.466648288
Short name T185
Test name
Test status
Simulation time 20152170 ps
CPU time 0.85 seconds
Started May 12 02:13:50 PM PDT 24
Finished May 12 02:13:52 PM PDT 24
Peak memory 215256 kb
Host smart-41358ff0-87e3-4eb8-8694-a39bc417f5d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466648288 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.466648288
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3184959716
Short name T549
Test name
Test status
Simulation time 73725640 ps
CPU time 0.93 seconds
Started May 12 02:13:51 PM PDT 24
Finished May 12 02:13:52 PM PDT 24
Peak memory 216568 kb
Host smart-a56762c8-e2a5-48e0-b7dc-792ccb16aa5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184959716 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3184959716
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3192556803
Short name T729
Test name
Test status
Simulation time 56147483 ps
CPU time 0.85 seconds
Started May 12 02:13:51 PM PDT 24
Finished May 12 02:13:52 PM PDT 24
Peak memory 218200 kb
Host smart-c9afedc6-de64-4b83-be26-bf296c7d2060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192556803 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3192556803
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3821897641
Short name T553
Test name
Test status
Simulation time 37339412 ps
CPU time 1.39 seconds
Started May 12 02:13:44 PM PDT 24
Finished May 12 02:13:46 PM PDT 24
Peak memory 216840 kb
Host smart-3248f98f-059f-4a18-90a4-227aa92589dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821897641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3821897641
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3466194063
Short name T138
Test name
Test status
Simulation time 27479819 ps
CPU time 0.93 seconds
Started May 12 02:13:51 PM PDT 24
Finished May 12 02:13:53 PM PDT 24
Peak memory 215812 kb
Host smart-7daf028c-5913-4907-bf92-6724d7059e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466194063 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3466194063
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.886501486
Short name T516
Test name
Test status
Simulation time 63282439 ps
CPU time 0.94 seconds
Started May 12 02:13:48 PM PDT 24
Finished May 12 02:13:50 PM PDT 24
Peak memory 215072 kb
Host smart-bf6ae978-3420-4c35-b55b-03207caff7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886501486 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.886501486
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2723765691
Short name T558
Test name
Test status
Simulation time 316984629 ps
CPU time 2.04 seconds
Started May 12 02:13:45 PM PDT 24
Finished May 12 02:13:48 PM PDT 24
Peak memory 216788 kb
Host smart-067cc61b-3f5a-4fcb-9125-c9d8c7e1d118
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723765691 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2723765691
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3798209888
Short name T195
Test name
Test status
Simulation time 59633965893 ps
CPU time 508.06 seconds
Started May 12 02:13:50 PM PDT 24
Finished May 12 02:22:19 PM PDT 24
Peak memory 217412 kb
Host smart-3f3fae8a-12f7-40df-bf24-8f4ab50700a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798209888 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3798209888
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.384197547
Short name T514
Test name
Test status
Simulation time 62779953 ps
CPU time 1.25 seconds
Started May 12 02:12:39 PM PDT 24
Finished May 12 02:12:41 PM PDT 24
Peak memory 215504 kb
Host smart-2a84822a-7c05-4d9b-aa23-7f50c223acc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384197547 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.384197547
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.711877198
Short name T372
Test name
Test status
Simulation time 13600256 ps
CPU time 0.92 seconds
Started May 12 02:12:44 PM PDT 24
Finished May 12 02:12:46 PM PDT 24
Peak memory 206520 kb
Host smart-7264909d-64b0-4e7d-8480-92c33fe75bd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711877198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.711877198
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1241610932
Short name T242
Test name
Test status
Simulation time 85009461 ps
CPU time 1.11 seconds
Started May 12 02:12:42 PM PDT 24
Finished May 12 02:12:45 PM PDT 24
Peak memory 216724 kb
Host smart-36df7477-35be-4d8a-a746-2dfcbd02a886
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241610932 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1241610932
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.756404959
Short name T52
Test name
Test status
Simulation time 19699781 ps
CPU time 1.22 seconds
Started May 12 02:12:44 PM PDT 24
Finished May 12 02:12:46 PM PDT 24
Peak memory 223840 kb
Host smart-a2eb099e-7c86-4a4b-837f-612c2291ac05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756404959 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.756404959
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2512899379
Short name T13
Test name
Test status
Simulation time 44785837 ps
CPU time 1.25 seconds
Started May 12 02:12:42 PM PDT 24
Finished May 12 02:12:44 PM PDT 24
Peak memory 219320 kb
Host smart-9d9868a9-e7a5-4f05-928c-e0478e16036e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512899379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2512899379
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.759836801
Short name T139
Test name
Test status
Simulation time 29194182 ps
CPU time 0.93 seconds
Started May 12 02:12:35 PM PDT 24
Finished May 12 02:12:36 PM PDT 24
Peak memory 215660 kb
Host smart-7a35a236-ef28-4e40-a28c-7959347f817e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759836801 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.759836801
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.158316562
Short name T572
Test name
Test status
Simulation time 14801183 ps
CPU time 0.98 seconds
Started May 12 02:12:39 PM PDT 24
Finished May 12 02:12:41 PM PDT 24
Peak memory 206952 kb
Host smart-a18f6c13-17b5-4c1d-b7b6-30b553b06dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158316562 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.158316562
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3965278489
Short name T324
Test name
Test status
Simulation time 16746426 ps
CPU time 0.98 seconds
Started May 12 02:12:41 PM PDT 24
Finished May 12 02:12:43 PM PDT 24
Peak memory 215176 kb
Host smart-021ff1f2-3059-485a-a06b-6b3720247da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965278489 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3965278489
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1228170915
Short name T543
Test name
Test status
Simulation time 334382283 ps
CPU time 2.25 seconds
Started May 12 02:12:42 PM PDT 24
Finished May 12 02:12:45 PM PDT 24
Peak memory 219384 kb
Host smart-8e3ea5c1-cefb-4f6e-adb5-bf9ac406a943
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228170915 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1228170915
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.140748618
Short name T843
Test name
Test status
Simulation time 77404631159 ps
CPU time 323.1 seconds
Started May 12 02:12:43 PM PDT 24
Finished May 12 02:18:08 PM PDT 24
Peak memory 223512 kb
Host smart-7b5aa7d5-e4fe-42d5-bcac-cc8373234f71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140748618 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.140748618
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.2641577185
Short name T486
Test name
Test status
Simulation time 31596769 ps
CPU time 0.85 seconds
Started May 12 02:13:53 PM PDT 24
Finished May 12 02:13:54 PM PDT 24
Peak memory 218012 kb
Host smart-3f5a4424-4964-4de4-b364-dc216c2858a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641577185 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2641577185
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3817098082
Short name T255
Test name
Test status
Simulation time 85632702 ps
CPU time 1.37 seconds
Started May 12 02:13:50 PM PDT 24
Finished May 12 02:13:52 PM PDT 24
Peak memory 218380 kb
Host smart-b070a271-cf43-4eea-a0b1-eec0795f72fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817098082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3817098082
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.330633274
Short name T569
Test name
Test status
Simulation time 49873348 ps
CPU time 1.01 seconds
Started May 12 02:13:49 PM PDT 24
Finished May 12 02:13:50 PM PDT 24
Peak memory 218320 kb
Host smart-40046a29-e1b2-49d2-b923-b8bb0ab5111d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330633274 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.330633274
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.651170350
Short name T129
Test name
Test status
Simulation time 71056859 ps
CPU time 1.62 seconds
Started May 12 02:13:57 PM PDT 24
Finished May 12 02:14:00 PM PDT 24
Peak memory 218160 kb
Host smart-332c7e3f-1bb0-42e6-8169-b6405ddb792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651170350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.651170350
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.1476912200
Short name T842
Test name
Test status
Simulation time 30677809 ps
CPU time 0.9 seconds
Started May 12 02:13:50 PM PDT 24
Finished May 12 02:13:52 PM PDT 24
Peak memory 218048 kb
Host smart-bd196191-9250-43a1-b97f-52f00e8d542d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476912200 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1476912200
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3735433629
Short name T608
Test name
Test status
Simulation time 96245462 ps
CPU time 1.11 seconds
Started May 12 02:13:50 PM PDT 24
Finished May 12 02:13:52 PM PDT 24
Peak memory 216720 kb
Host smart-cff3df55-04f2-4433-b9a9-56475afc67b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735433629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3735433629
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.2961569230
Short name T88
Test name
Test status
Simulation time 29754526 ps
CPU time 0.98 seconds
Started May 12 02:13:50 PM PDT 24
Finished May 12 02:13:51 PM PDT 24
Peak memory 223616 kb
Host smart-09dc4026-8d04-4b9f-b32c-d7add26bbfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961569230 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2961569230
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1023580505
Short name T638
Test name
Test status
Simulation time 77435123 ps
CPU time 1.15 seconds
Started May 12 02:13:49 PM PDT 24
Finished May 12 02:13:51 PM PDT 24
Peak memory 217032 kb
Host smart-27f9a58c-e8a3-47ab-b5b0-686c45749b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023580505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1023580505
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.3930639561
Short name T171
Test name
Test status
Simulation time 76736633 ps
CPU time 1.16 seconds
Started May 12 02:13:54 PM PDT 24
Finished May 12 02:13:57 PM PDT 24
Peak memory 219480 kb
Host smart-126c5d86-0269-4012-ac6f-3581536a617c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930639561 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3930639561
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3497220926
Short name T630
Test name
Test status
Simulation time 37114382 ps
CPU time 1.47 seconds
Started May 12 02:13:51 PM PDT 24
Finished May 12 02:13:53 PM PDT 24
Peak memory 218096 kb
Host smart-6479d9b5-a9d5-4ecf-b8bc-41ec2adfa49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497220926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3497220926
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.357155077
Short name T397
Test name
Test status
Simulation time 50911906 ps
CPU time 0.95 seconds
Started May 12 02:13:58 PM PDT 24
Finished May 12 02:14:00 PM PDT 24
Peak memory 218440 kb
Host smart-f48c6813-96ad-47d8-8da1-2af2cc37f756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357155077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.357155077
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3769456539
Short name T215
Test name
Test status
Simulation time 86674766 ps
CPU time 1.17 seconds
Started May 12 02:13:54 PM PDT 24
Finished May 12 02:13:57 PM PDT 24
Peak memory 216872 kb
Host smart-fece106c-75f3-4c33-8c04-259c4df7b00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769456539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3769456539
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.1507172709
Short name T846
Test name
Test status
Simulation time 38798509 ps
CPU time 1.06 seconds
Started May 12 02:13:58 PM PDT 24
Finished May 12 02:14:00 PM PDT 24
Peak memory 220508 kb
Host smart-93451ef6-709e-4741-ae73-78aa70997131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507172709 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1507172709
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1873324932
Short name T423
Test name
Test status
Simulation time 25333949 ps
CPU time 1.08 seconds
Started May 12 02:13:54 PM PDT 24
Finished May 12 02:13:56 PM PDT 24
Peak memory 217368 kb
Host smart-ef3a0fb2-b633-42b1-af82-2c9afe57b95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873324932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1873324932
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.783731302
Short name T54
Test name
Test status
Simulation time 32756627 ps
CPU time 1.04 seconds
Started May 12 02:13:55 PM PDT 24
Finished May 12 02:13:57 PM PDT 24
Peak memory 223876 kb
Host smart-a84e9ac2-aca5-4948-9a5d-06410df37271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783731302 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.783731302
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2952478500
Short name T375
Test name
Test status
Simulation time 101504536 ps
CPU time 1.51 seconds
Started May 12 02:13:56 PM PDT 24
Finished May 12 02:13:58 PM PDT 24
Peak memory 218648 kb
Host smart-97ffc04b-46bb-4daf-b3ad-5a44b85de503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952478500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2952478500
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2095907116
Short name T176
Test name
Test status
Simulation time 68241260 ps
CPU time 1.06 seconds
Started May 12 02:13:54 PM PDT 24
Finished May 12 02:13:56 PM PDT 24
Peak memory 219604 kb
Host smart-3bd90bae-6053-4577-ab96-5874d5028841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095907116 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2095907116
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2880027980
Short name T459
Test name
Test status
Simulation time 59101655 ps
CPU time 1.63 seconds
Started May 12 02:13:54 PM PDT 24
Finished May 12 02:13:56 PM PDT 24
Peak memory 216920 kb
Host smart-8074b89d-f3cd-47b9-bb49-620ab1ef0a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880027980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2880027980
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.4210413698
Short name T818
Test name
Test status
Simulation time 33028272 ps
CPU time 0.88 seconds
Started May 12 02:13:55 PM PDT 24
Finished May 12 02:13:57 PM PDT 24
Peak memory 218196 kb
Host smart-d2832f88-b8b4-4abf-8e7e-a3325029436e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210413698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.4210413698
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3714836515
Short name T547
Test name
Test status
Simulation time 45564557 ps
CPU time 1.16 seconds
Started May 12 02:13:58 PM PDT 24
Finished May 12 02:14:00 PM PDT 24
Peak memory 216936 kb
Host smart-530c80b3-d718-4999-944a-b9273020b3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714836515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3714836515
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3987511980
Short name T725
Test name
Test status
Simulation time 331761927 ps
CPU time 1.54 seconds
Started May 12 02:12:42 PM PDT 24
Finished May 12 02:12:45 PM PDT 24
Peak memory 215672 kb
Host smart-17957a66-77c7-4069-9a6a-8c90439ab75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987511980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3987511980
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.443527473
Short name T565
Test name
Test status
Simulation time 22444115 ps
CPU time 0.85 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 206492 kb
Host smart-411e54a0-33fa-43fb-ae7d-1479f6968844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443527473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.443527473
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1650775360
Short name T740
Test name
Test status
Simulation time 15935271 ps
CPU time 0.85 seconds
Started May 12 02:12:43 PM PDT 24
Finished May 12 02:12:46 PM PDT 24
Peak memory 216108 kb
Host smart-ff333657-549c-45ed-8ece-108c156fb920
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650775360 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1650775360
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1683629903
Short name T64
Test name
Test status
Simulation time 79849646 ps
CPU time 1.18 seconds
Started May 12 02:12:44 PM PDT 24
Finished May 12 02:12:47 PM PDT 24
Peak memory 216472 kb
Host smart-84dca1db-4d45-463b-9f26-30fb5bea3620
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683629903 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1683629903
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2927277184
Short name T83
Test name
Test status
Simulation time 28123117 ps
CPU time 0.95 seconds
Started May 12 02:12:45 PM PDT 24
Finished May 12 02:12:47 PM PDT 24
Peak memory 223656 kb
Host smart-f0597cad-1bf7-4e85-a23a-c7cb0be86a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927277184 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2927277184
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1123933576
Short name T501
Test name
Test status
Simulation time 31724588 ps
CPU time 1.05 seconds
Started May 12 02:12:44 PM PDT 24
Finished May 12 02:12:46 PM PDT 24
Peak memory 219448 kb
Host smart-81b9bf6e-7813-426a-8768-bbe164c5e83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123933576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1123933576
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1546482692
Short name T776
Test name
Test status
Simulation time 31769810 ps
CPU time 0.89 seconds
Started May 12 02:12:43 PM PDT 24
Finished May 12 02:12:45 PM PDT 24
Peak memory 215392 kb
Host smart-54071173-93eb-4e60-86bb-91f2eae9ddcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546482692 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1546482692
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.2712837608
Short name T302
Test name
Test status
Simulation time 47489774 ps
CPU time 0.97 seconds
Started May 12 02:12:42 PM PDT 24
Finished May 12 02:12:44 PM PDT 24
Peak memory 206988 kb
Host smart-26c0d46f-7480-49b4-af76-db5b37d15ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712837608 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2712837608
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3795944754
Short name T314
Test name
Test status
Simulation time 63111018 ps
CPU time 0.91 seconds
Started May 12 02:12:42 PM PDT 24
Finished May 12 02:12:44 PM PDT 24
Peak memory 215156 kb
Host smart-b660ac93-de13-4536-a366-dcb2de18eaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795944754 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3795944754
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3698819327
Short name T692
Test name
Test status
Simulation time 705070579 ps
CPU time 4.61 seconds
Started May 12 02:12:44 PM PDT 24
Finished May 12 02:12:50 PM PDT 24
Peak memory 216868 kb
Host smart-d4de6668-e256-4460-a447-d498c85f0e2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698819327 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3698819327
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3005510078
Short name T101
Test name
Test status
Simulation time 79948573405 ps
CPU time 1089.29 seconds
Started May 12 02:12:43 PM PDT 24
Finished May 12 02:30:54 PM PDT 24
Peak memory 223092 kb
Host smart-93d2602c-1c5d-44b5-8de0-64e811d19097
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005510078 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3005510078
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.883987009
Short name T708
Test name
Test status
Simulation time 27395487 ps
CPU time 1.29 seconds
Started May 12 02:13:53 PM PDT 24
Finished May 12 02:13:55 PM PDT 24
Peak memory 220452 kb
Host smart-ea0419b8-9acb-4249-b227-d351a3b12578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883987009 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.883987009
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3252203184
Short name T732
Test name
Test status
Simulation time 44776392 ps
CPU time 1.67 seconds
Started May 12 02:13:58 PM PDT 24
Finished May 12 02:14:00 PM PDT 24
Peak memory 217064 kb
Host smart-4b466f63-66e5-4855-b9b7-cb231013c19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252203184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3252203184
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.1951332538
Short name T68
Test name
Test status
Simulation time 20966022 ps
CPU time 1.08 seconds
Started May 12 02:13:54 PM PDT 24
Finished May 12 02:13:56 PM PDT 24
Peak memory 223816 kb
Host smart-c8f1aec1-b5b7-4be8-98e3-edd9a03f9501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951332538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1951332538
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1905725654
Short name T328
Test name
Test status
Simulation time 96361060 ps
CPU time 1.21 seconds
Started May 12 02:13:56 PM PDT 24
Finished May 12 02:13:59 PM PDT 24
Peak memory 216836 kb
Host smart-43ccfcc7-7104-4d7c-85bf-3cf2118ab314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905725654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1905725654
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.1116530664
Short name T4
Test name
Test status
Simulation time 31507005 ps
CPU time 0.98 seconds
Started May 12 02:13:54 PM PDT 24
Finished May 12 02:13:57 PM PDT 24
Peak memory 223684 kb
Host smart-6c2b51e8-a364-4376-bf2d-05728adf7a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116530664 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1116530664
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3257418375
Short name T269
Test name
Test status
Simulation time 71990033 ps
CPU time 1.11 seconds
Started May 12 02:13:59 PM PDT 24
Finished May 12 02:14:02 PM PDT 24
Peak memory 218348 kb
Host smart-d51cdbfa-dd1b-43e4-9d96-26a93180b89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257418375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3257418375
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.766654218
Short name T40
Test name
Test status
Simulation time 27574457 ps
CPU time 1.39 seconds
Started May 12 02:13:54 PM PDT 24
Finished May 12 02:13:56 PM PDT 24
Peak memory 229556 kb
Host smart-ab8ff83c-d0c8-45fa-9d7f-2fda96cfd3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766654218 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.766654218
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1986121611
Short name T282
Test name
Test status
Simulation time 66979422 ps
CPU time 1.1 seconds
Started May 12 02:13:57 PM PDT 24
Finished May 12 02:13:59 PM PDT 24
Peak memory 218096 kb
Host smart-2d3c43e3-06b2-44f6-bef3-b29f9266ddf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986121611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1986121611
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.263967850
Short name T44
Test name
Test status
Simulation time 20368298 ps
CPU time 1.11 seconds
Started May 12 02:13:54 PM PDT 24
Finished May 12 02:13:57 PM PDT 24
Peak memory 219528 kb
Host smart-273f9898-70cd-492b-930c-722c430375f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263967850 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.263967850
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.583539141
Short name T575
Test name
Test status
Simulation time 96653696 ps
CPU time 1.08 seconds
Started May 12 02:13:56 PM PDT 24
Finished May 12 02:13:58 PM PDT 24
Peak memory 216868 kb
Host smart-28479b22-46d3-4e40-bc85-e687d13feac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583539141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.583539141
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.2380132896
Short name T521
Test name
Test status
Simulation time 23339503 ps
CPU time 1.23 seconds
Started May 12 02:13:55 PM PDT 24
Finished May 12 02:13:57 PM PDT 24
Peak memory 220592 kb
Host smart-f5e2c3f2-6bf3-4045-8328-7e70480cf287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380132896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2380132896
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3657298390
Short name T396
Test name
Test status
Simulation time 62272698 ps
CPU time 1.55 seconds
Started May 12 02:13:54 PM PDT 24
Finished May 12 02:13:56 PM PDT 24
Peak memory 216812 kb
Host smart-6e30af0a-12b6-4ae7-b742-8ee828d3a6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657298390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3657298390
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.2580502159
Short name T522
Test name
Test status
Simulation time 44457003 ps
CPU time 1.09 seconds
Started May 12 02:13:54 PM PDT 24
Finished May 12 02:13:56 PM PDT 24
Peak memory 219208 kb
Host smart-97f741a9-d3c8-4091-9a40-5a5cd4556c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580502159 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2580502159
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3528830916
Short name T799
Test name
Test status
Simulation time 47367597 ps
CPU time 1.2 seconds
Started May 12 02:13:54 PM PDT 24
Finished May 12 02:13:56 PM PDT 24
Peak memory 218052 kb
Host smart-2cefbe4c-9bd2-4e80-82b3-c584ce4dd539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528830916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3528830916
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.1176940827
Short name T172
Test name
Test status
Simulation time 30608247 ps
CPU time 1.27 seconds
Started May 12 02:13:54 PM PDT 24
Finished May 12 02:13:57 PM PDT 24
Peak memory 219548 kb
Host smart-ff0778cf-d794-47bd-8b83-cf1df04e68ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176940827 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1176940827
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.4229267100
Short name T833
Test name
Test status
Simulation time 70035304 ps
CPU time 1.21 seconds
Started May 12 02:13:53 PM PDT 24
Finished May 12 02:13:55 PM PDT 24
Peak memory 216968 kb
Host smart-09ed9622-34ab-425f-8998-3075e6e1205f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229267100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.4229267100
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.4003664165
Short name T649
Test name
Test status
Simulation time 23293000 ps
CPU time 1.14 seconds
Started May 12 02:13:55 PM PDT 24
Finished May 12 02:13:57 PM PDT 24
Peak memory 218300 kb
Host smart-d8827ccb-7737-4d32-80a4-4d0d0a6bc922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003664165 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.4003664165
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1733205105
Short name T203
Test name
Test status
Simulation time 155608125 ps
CPU time 1.16 seconds
Started May 12 02:13:55 PM PDT 24
Finished May 12 02:13:57 PM PDT 24
Peak memory 216888 kb
Host smart-aa13688e-1db8-4eab-97b6-894f748d71b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733205105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1733205105
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.2724536915
Short name T527
Test name
Test status
Simulation time 19338297 ps
CPU time 1.12 seconds
Started May 12 02:13:55 PM PDT 24
Finished May 12 02:13:57 PM PDT 24
Peak memory 223856 kb
Host smart-e1848214-7015-4e94-9189-7c24a508596a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724536915 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2724536915
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1033705337
Short name T477
Test name
Test status
Simulation time 155022347 ps
CPU time 0.99 seconds
Started May 12 02:13:54 PM PDT 24
Finished May 12 02:13:56 PM PDT 24
Peak memory 216836 kb
Host smart-55c0840b-0aca-4d0c-b233-1fa090fe5fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033705337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1033705337
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1203434537
Short name T30
Test name
Test status
Simulation time 71874019 ps
CPU time 1.07 seconds
Started May 12 02:12:45 PM PDT 24
Finished May 12 02:12:47 PM PDT 24
Peak memory 215472 kb
Host smart-6fc9e1ed-10b5-439e-81b6-141188191077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203434537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1203434537
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1010554757
Short name T115
Test name
Test status
Simulation time 79401857 ps
CPU time 1.36 seconds
Started May 12 02:12:45 PM PDT 24
Finished May 12 02:12:48 PM PDT 24
Peak memory 214916 kb
Host smart-fdc1e7bd-930e-45b2-bc6a-5efd8ace76cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010554757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1010554757
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3131617346
Short name T377
Test name
Test status
Simulation time 19180866 ps
CPU time 0.87 seconds
Started May 12 02:12:44 PM PDT 24
Finished May 12 02:12:46 PM PDT 24
Peak memory 216040 kb
Host smart-a070038d-dabd-4da7-8335-0773346865d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131617346 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3131617346
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.4082388608
Short name T19
Test name
Test status
Simulation time 30933980 ps
CPU time 1.13 seconds
Started May 12 02:12:43 PM PDT 24
Finished May 12 02:12:45 PM PDT 24
Peak memory 216648 kb
Host smart-32c7fa92-10f5-4cd4-80bb-7c84e9b4a9c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082388608 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.4082388608
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3786173017
Short name T752
Test name
Test status
Simulation time 27719787 ps
CPU time 0.83 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 217776 kb
Host smart-4871946f-58ba-47c0-a004-b5aff24d2e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786173017 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3786173017
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2496082561
Short name T428
Test name
Test status
Simulation time 53283665 ps
CPU time 1.19 seconds
Started May 12 02:12:45 PM PDT 24
Finished May 12 02:12:48 PM PDT 24
Peak memory 218196 kb
Host smart-bcf5d52d-851b-4c1f-b0ac-2ec324dcb463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496082561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2496082561
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2263875559
Short name T536
Test name
Test status
Simulation time 20704166 ps
CPU time 1.13 seconds
Started May 12 02:12:46 PM PDT 24
Finished May 12 02:12:49 PM PDT 24
Peak memory 215868 kb
Host smart-f1e4da68-dd93-46ed-8719-ea48ce75677c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263875559 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2263875559
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.4191517326
Short name T300
Test name
Test status
Simulation time 48675556 ps
CPU time 0.9 seconds
Started May 12 02:12:42 PM PDT 24
Finished May 12 02:12:43 PM PDT 24
Peak memory 206984 kb
Host smart-c7ac2cd6-2193-46c7-892c-e534c11c2946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191517326 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.4191517326
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1670122863
Short name T587
Test name
Test status
Simulation time 41533175 ps
CPU time 0.92 seconds
Started May 12 02:12:44 PM PDT 24
Finished May 12 02:12:46 PM PDT 24
Peak memory 215092 kb
Host smart-ce456673-e2a2-4c22-9bea-8f944a4dccb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670122863 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1670122863
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2285665081
Short name T511
Test name
Test status
Simulation time 89009412 ps
CPU time 2.25 seconds
Started May 12 02:12:46 PM PDT 24
Finished May 12 02:12:50 PM PDT 24
Peak memory 216864 kb
Host smart-fdfc80bc-10f9-46e1-bc06-aad5bbe91103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285665081 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2285665081
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.4082013384
Short name T447
Test name
Test status
Simulation time 74698759954 ps
CPU time 1933.18 seconds
Started May 12 02:12:46 PM PDT 24
Finished May 12 02:45:00 PM PDT 24
Peak memory 227472 kb
Host smart-9579bed8-46c4-4708-85e0-e9d19d5fec0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082013384 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.4082013384
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.3458082248
Short name T65
Test name
Test status
Simulation time 19860977 ps
CPU time 1.24 seconds
Started May 12 02:14:00 PM PDT 24
Finished May 12 02:14:02 PM PDT 24
Peak memory 223820 kb
Host smart-ba8fab51-905c-40f7-baba-f3242722183d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458082248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3458082248
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.930101602
Short name T669
Test name
Test status
Simulation time 151745067 ps
CPU time 1.18 seconds
Started May 12 02:13:59 PM PDT 24
Finished May 12 02:14:01 PM PDT 24
Peak memory 216900 kb
Host smart-bdc29ee0-b70f-4b0e-969c-b4c6af7fd750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930101602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.930101602
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.2359649517
Short name T75
Test name
Test status
Simulation time 22632882 ps
CPU time 0.95 seconds
Started May 12 02:13:59 PM PDT 24
Finished May 12 02:14:01 PM PDT 24
Peak memory 218256 kb
Host smart-cd2aac62-8d39-4b89-ada9-20a037cd686d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359649517 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2359649517
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3940389042
Short name T733
Test name
Test status
Simulation time 26520887 ps
CPU time 1.39 seconds
Started May 12 02:14:01 PM PDT 24
Finished May 12 02:14:03 PM PDT 24
Peak memory 219416 kb
Host smart-8935d04f-3991-404f-897d-8cefb1fc7f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940389042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3940389042
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.3581278142
Short name T26
Test name
Test status
Simulation time 24431098 ps
CPU time 0.95 seconds
Started May 12 02:13:57 PM PDT 24
Finished May 12 02:14:00 PM PDT 24
Peak memory 218276 kb
Host smart-38796620-771a-45c7-b9b7-95bc7c31284d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581278142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3581278142
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3846799884
Short name T410
Test name
Test status
Simulation time 44519542 ps
CPU time 1.26 seconds
Started May 12 02:13:58 PM PDT 24
Finished May 12 02:14:00 PM PDT 24
Peak memory 219456 kb
Host smart-c3366807-c4eb-473a-8a6f-79b1983a5b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846799884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3846799884
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_genbits.396460531
Short name T530
Test name
Test status
Simulation time 68250927 ps
CPU time 1.15 seconds
Started May 12 02:14:00 PM PDT 24
Finished May 12 02:14:02 PM PDT 24
Peak memory 219092 kb
Host smart-57c6f6cc-4d68-41df-8d53-7229b3318043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396460531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.396460531
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.4205544860
Short name T761
Test name
Test status
Simulation time 67590763 ps
CPU time 0.86 seconds
Started May 12 02:13:57 PM PDT 24
Finished May 12 02:13:58 PM PDT 24
Peak memory 218264 kb
Host smart-a181fd9c-2d58-4114-b114-c0650ff6b424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205544860 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.4205544860
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1432682432
Short name T429
Test name
Test status
Simulation time 44254384 ps
CPU time 1.15 seconds
Started May 12 02:14:02 PM PDT 24
Finished May 12 02:14:04 PM PDT 24
Peak memory 217068 kb
Host smart-baf2267d-9ca4-48b4-9f8e-c858d1d55e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432682432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1432682432
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.3433101833
Short name T48
Test name
Test status
Simulation time 55597016 ps
CPU time 1.03 seconds
Started May 12 02:13:59 PM PDT 24
Finished May 12 02:14:01 PM PDT 24
Peak memory 219448 kb
Host smart-f3a00ace-37ec-48b2-802f-d64df1d0a5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433101833 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3433101833
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1069606024
Short name T342
Test name
Test status
Simulation time 51608201 ps
CPU time 1.2 seconds
Started May 12 02:14:00 PM PDT 24
Finished May 12 02:14:03 PM PDT 24
Peak memory 216808 kb
Host smart-5fd3976f-6aca-4b12-85fc-d25d176f9f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069606024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1069606024
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.2837165727
Short name T71
Test name
Test status
Simulation time 27276771 ps
CPU time 1.06 seconds
Started May 12 02:14:00 PM PDT 24
Finished May 12 02:14:02 PM PDT 24
Peak memory 218536 kb
Host smart-1a2cc166-f37d-4b18-b2f0-fcba4c246fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837165727 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2837165727
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3514504036
Short name T492
Test name
Test status
Simulation time 92347246 ps
CPU time 1.36 seconds
Started May 12 02:14:02 PM PDT 24
Finished May 12 02:14:05 PM PDT 24
Peak memory 217900 kb
Host smart-ef89e455-24ed-4302-98cb-f1abd953a841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514504036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3514504036
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.1859717617
Short name T55
Test name
Test status
Simulation time 45836347 ps
CPU time 1.02 seconds
Started May 12 02:13:58 PM PDT 24
Finished May 12 02:14:00 PM PDT 24
Peak memory 219652 kb
Host smart-6616c693-300d-4a50-a4ba-0a494fef19a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859717617 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1859717617
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1067264397
Short name T773
Test name
Test status
Simulation time 67823612 ps
CPU time 1.73 seconds
Started May 12 02:14:03 PM PDT 24
Finished May 12 02:14:05 PM PDT 24
Peak memory 218096 kb
Host smart-b01b8ed6-0172-44c2-bf79-05db1c4e979d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067264397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1067264397
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.3212900378
Short name T77
Test name
Test status
Simulation time 24947523 ps
CPU time 0.98 seconds
Started May 12 02:13:57 PM PDT 24
Finished May 12 02:13:59 PM PDT 24
Peak memory 218148 kb
Host smart-8112336c-3d36-4946-8b36-decd2db44e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212900378 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3212900378
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1823080869
Short name T392
Test name
Test status
Simulation time 60731611 ps
CPU time 2.12 seconds
Started May 12 02:13:59 PM PDT 24
Finished May 12 02:14:02 PM PDT 24
Peak memory 217112 kb
Host smart-6dbc88e1-7ff2-4d34-a60a-cf8db2b3a071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823080869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1823080869
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.3294214680
Short name T320
Test name
Test status
Simulation time 45105663 ps
CPU time 1 seconds
Started May 12 02:14:02 PM PDT 24
Finished May 12 02:14:04 PM PDT 24
Peak memory 219464 kb
Host smart-a06207a2-f6dd-437d-9d07-201c32e8b5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294214680 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3294214680
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2152480986
Short name T335
Test name
Test status
Simulation time 45592243 ps
CPU time 1.57 seconds
Started May 12 02:14:03 PM PDT 24
Finished May 12 02:14:06 PM PDT 24
Peak memory 218204 kb
Host smart-00f3d5a7-30ad-4dc4-87a0-2d692cb776b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152480986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2152480986
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3342299970
Short name T251
Test name
Test status
Simulation time 320955852 ps
CPU time 1.34 seconds
Started May 12 02:12:47 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 215500 kb
Host smart-81799000-c029-4a1b-a957-6a1d2d2dce53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342299970 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3342299970
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1648754162
Short name T322
Test name
Test status
Simulation time 32207633 ps
CPU time 1.03 seconds
Started May 12 02:12:45 PM PDT 24
Finished May 12 02:12:48 PM PDT 24
Peak memory 214872 kb
Host smart-7eadcffb-8348-4aa1-8cc3-89e6270afd0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648754162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1648754162
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3828747880
Short name T762
Test name
Test status
Simulation time 16553249 ps
CPU time 0.9 seconds
Started May 12 02:12:45 PM PDT 24
Finished May 12 02:12:47 PM PDT 24
Peak memory 216032 kb
Host smart-f2b9635b-5592-4671-bf3b-d4c9071e90e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828747880 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3828747880
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1833005051
Short name T794
Test name
Test status
Simulation time 102488626 ps
CPU time 1.12 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 218092 kb
Host smart-d2272d48-ec02-45f5-ad98-7d660760215f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833005051 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1833005051
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3168406595
Short name T310
Test name
Test status
Simulation time 31100975 ps
CPU time 0.91 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 217740 kb
Host smart-4dbec2e3-16d6-40d0-b0c1-cfef9ff7058d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168406595 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3168406595
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.530903548
Short name T346
Test name
Test status
Simulation time 34508273 ps
CPU time 1.56 seconds
Started May 12 02:12:42 PM PDT 24
Finished May 12 02:12:44 PM PDT 24
Peak memory 218000 kb
Host smart-b4de88d3-0bd1-4a1a-9288-91164e8e5b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530903548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.530903548
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3350279340
Short name T23
Test name
Test status
Simulation time 24774801 ps
CPU time 0.98 seconds
Started May 12 02:12:43 PM PDT 24
Finished May 12 02:12:45 PM PDT 24
Peak memory 215280 kb
Host smart-290707da-bcbd-4c27-8b06-bfb0f4a73547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350279340 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3350279340
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3224810050
Short name T103
Test name
Test status
Simulation time 22767070 ps
CPU time 0.92 seconds
Started May 12 02:12:45 PM PDT 24
Finished May 12 02:12:47 PM PDT 24
Peak memory 206896 kb
Host smart-2bf1c26c-ffb4-45db-a280-8d37be73e46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224810050 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3224810050
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1226064833
Short name T643
Test name
Test status
Simulation time 17677325 ps
CPU time 0.97 seconds
Started May 12 02:12:46 PM PDT 24
Finished May 12 02:12:48 PM PDT 24
Peak memory 215104 kb
Host smart-c119676e-4640-4c01-b102-c7451b3e27df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226064833 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1226064833
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.553162370
Short name T154
Test name
Test status
Simulation time 216054938 ps
CPU time 2.65 seconds
Started May 12 02:12:29 PM PDT 24
Finished May 12 02:12:32 PM PDT 24
Peak memory 216640 kb
Host smart-2f7f36a8-3a0a-464d-a8a1-a8200c7382df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553162370 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.553162370
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.733809055
Short name T188
Test name
Test status
Simulation time 12013106927 ps
CPU time 277.36 seconds
Started May 12 02:12:44 PM PDT 24
Finished May 12 02:17:22 PM PDT 24
Peak memory 222296 kb
Host smart-59ce12c2-2ada-443e-8323-1ee764d7b34f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733809055 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.733809055
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.3889788781
Short name T56
Test name
Test status
Simulation time 64211857 ps
CPU time 1.02 seconds
Started May 12 02:13:57 PM PDT 24
Finished May 12 02:13:59 PM PDT 24
Peak memory 219380 kb
Host smart-4b157e4e-f271-4b2f-b2e4-cb76e45b84df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889788781 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3889788781
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1831916419
Short name T529
Test name
Test status
Simulation time 28651579 ps
CPU time 1.44 seconds
Started May 12 02:13:58 PM PDT 24
Finished May 12 02:14:01 PM PDT 24
Peak memory 217892 kb
Host smart-42002edb-5d1b-4ac9-b2c6-d9a8860c3127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831916419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1831916419
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.614678814
Short name T39
Test name
Test status
Simulation time 34792106 ps
CPU time 1.09 seconds
Started May 12 02:13:59 PM PDT 24
Finished May 12 02:14:01 PM PDT 24
Peak memory 219376 kb
Host smart-39c78fa7-ed71-4ce1-94f1-d9a17288aad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614678814 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.614678814
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2975416035
Short name T789
Test name
Test status
Simulation time 82144913 ps
CPU time 1.16 seconds
Started May 12 02:14:00 PM PDT 24
Finished May 12 02:14:03 PM PDT 24
Peak memory 216964 kb
Host smart-e738d4a3-eacd-4dd4-8478-f31640d8c998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975416035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2975416035
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_genbits.1846080237
Short name T316
Test name
Test status
Simulation time 52366956 ps
CPU time 1.28 seconds
Started May 12 02:14:03 PM PDT 24
Finished May 12 02:14:06 PM PDT 24
Peak memory 216852 kb
Host smart-8e78936b-9e38-4d6c-bf3d-7f8fc4330c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846080237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1846080237
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.495174618
Short name T520
Test name
Test status
Simulation time 24599886 ps
CPU time 1.18 seconds
Started May 12 02:14:00 PM PDT 24
Finished May 12 02:14:03 PM PDT 24
Peak memory 219664 kb
Host smart-fa26259e-84d0-4d69-9839-e066b512da6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495174618 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.495174618
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3727132657
Short name T735
Test name
Test status
Simulation time 83385205 ps
CPU time 1.29 seconds
Started May 12 02:14:01 PM PDT 24
Finished May 12 02:14:03 PM PDT 24
Peak memory 215180 kb
Host smart-391b63d0-0c00-456b-ae0f-97abde2e6656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727132657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3727132657
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.76219658
Short name T45
Test name
Test status
Simulation time 39544131 ps
CPU time 1.24 seconds
Started May 12 02:14:04 PM PDT 24
Finished May 12 02:14:06 PM PDT 24
Peak memory 229420 kb
Host smart-eab5500f-fd82-4d8e-b347-dc6b2a58aed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76219658 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.76219658
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3968595592
Short name T722
Test name
Test status
Simulation time 68779751 ps
CPU time 1.43 seconds
Started May 12 02:13:58 PM PDT 24
Finished May 12 02:14:00 PM PDT 24
Peak memory 218404 kb
Host smart-358b6438-1a39-4a14-9123-497b37d70c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968595592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3968595592
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.3712706653
Short name T7
Test name
Test status
Simulation time 24514592 ps
CPU time 0.97 seconds
Started May 12 02:14:09 PM PDT 24
Finished May 12 02:14:12 PM PDT 24
Peak memory 219588 kb
Host smart-30aab67c-7f2c-4564-8af0-91223b00820e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712706653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3712706653
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.656656487
Short name T448
Test name
Test status
Simulation time 37320353 ps
CPU time 1.36 seconds
Started May 12 02:14:05 PM PDT 24
Finished May 12 02:14:08 PM PDT 24
Peak memory 218052 kb
Host smart-1204561b-8aa8-4419-b003-ef8efde7d832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656656487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.656656487
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.917120148
Short name T689
Test name
Test status
Simulation time 42109274 ps
CPU time 1.13 seconds
Started May 12 02:14:04 PM PDT 24
Finished May 12 02:14:06 PM PDT 24
Peak memory 220436 kb
Host smart-28123b6c-f374-43ab-a6c3-aca7a087f5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917120148 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.917120148
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3309869248
Short name T285
Test name
Test status
Simulation time 33887555 ps
CPU time 1.44 seconds
Started May 12 02:14:08 PM PDT 24
Finished May 12 02:14:11 PM PDT 24
Peak memory 217856 kb
Host smart-f1ba6307-66c6-4d08-abcc-f5847d01b20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309869248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3309869248
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.3355072521
Short name T831
Test name
Test status
Simulation time 55576513 ps
CPU time 1.16 seconds
Started May 12 02:14:01 PM PDT 24
Finished May 12 02:14:03 PM PDT 24
Peak memory 229492 kb
Host smart-0acdc23b-7306-4734-81bc-d0b5b926930a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355072521 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3355072521
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3119361785
Short name T749
Test name
Test status
Simulation time 46120472 ps
CPU time 1.98 seconds
Started May 12 02:14:02 PM PDT 24
Finished May 12 02:14:06 PM PDT 24
Peak memory 219844 kb
Host smart-a996bc07-7e61-4aa1-b844-7da3d06c920b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119361785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3119361785
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.469199374
Short name T61
Test name
Test status
Simulation time 54062414 ps
CPU time 1 seconds
Started May 12 02:14:05 PM PDT 24
Finished May 12 02:14:08 PM PDT 24
Peak memory 219296 kb
Host smart-11b5226b-ad4f-4363-beb6-744904e4bc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469199374 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.469199374
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.499980338
Short name T600
Test name
Test status
Simulation time 34871896 ps
CPU time 1.4 seconds
Started May 12 02:14:07 PM PDT 24
Finished May 12 02:14:10 PM PDT 24
Peak memory 216964 kb
Host smart-0e4d2cb9-5f1f-4265-bbc4-155b246b9ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499980338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.499980338
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.2313668858
Short name T435
Test name
Test status
Simulation time 30733448 ps
CPU time 0.87 seconds
Started May 12 02:14:01 PM PDT 24
Finished May 12 02:14:03 PM PDT 24
Peak memory 218032 kb
Host smart-4d8fa27d-6815-42a9-a51c-5f3953c4b642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313668858 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2313668858
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3971138955
Short name T589
Test name
Test status
Simulation time 169361208 ps
CPU time 1.31 seconds
Started May 12 02:14:05 PM PDT 24
Finished May 12 02:14:07 PM PDT 24
Peak memory 218640 kb
Host smart-f142786f-53d8-4ff4-bc78-5aa443c3087b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971138955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3971138955
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.4059260545
Short name T533
Test name
Test status
Simulation time 44992321 ps
CPU time 1.19 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 215468 kb
Host smart-ad2054a6-2573-41ae-8e39-1368a4f2901c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059260545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.4059260545
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.4024281454
Short name T311
Test name
Test status
Simulation time 46513021 ps
CPU time 0.92 seconds
Started May 12 02:12:46 PM PDT 24
Finished May 12 02:12:49 PM PDT 24
Peak memory 206504 kb
Host smart-cf66d7ef-064a-4dae-b710-794aa91424cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024281454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.4024281454
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2077483452
Short name T91
Test name
Test status
Simulation time 11591040 ps
CPU time 0.84 seconds
Started May 12 02:12:47 PM PDT 24
Finished May 12 02:12:50 PM PDT 24
Peak memory 215988 kb
Host smart-f72a3e10-7b4d-468a-88c6-9dec1a13c60a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077483452 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2077483452
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.36231281
Short name T37
Test name
Test status
Simulation time 275119354 ps
CPU time 1.09 seconds
Started May 12 02:12:34 PM PDT 24
Finished May 12 02:12:36 PM PDT 24
Peak memory 216596 kb
Host smart-743b4d65-ee2d-48d7-895b-09b0ca97e4f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36231281 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disa
ble_auto_req_mode.36231281
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.760113182
Short name T38
Test name
Test status
Simulation time 27253219 ps
CPU time 1.37 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 229556 kb
Host smart-cfcdc4b8-4581-41e9-88cf-8a8823b10c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760113182 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.760113182
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.12620934
Short name T820
Test name
Test status
Simulation time 149333990 ps
CPU time 1.13 seconds
Started May 12 02:12:48 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 216964 kb
Host smart-65c304c3-fd05-4537-9322-1b0547bc566e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12620934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.12620934
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.611880040
Short name T348
Test name
Test status
Simulation time 23681173 ps
CPU time 1.21 seconds
Started May 12 02:12:44 PM PDT 24
Finished May 12 02:12:47 PM PDT 24
Peak memory 223932 kb
Host smart-ba3c3d8f-250e-43f0-be22-e35bbd895764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611880040 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.611880040
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3300830850
Short name T293
Test name
Test status
Simulation time 54439004 ps
CPU time 0.95 seconds
Started May 12 02:12:38 PM PDT 24
Finished May 12 02:12:40 PM PDT 24
Peak memory 206864 kb
Host smart-67dfd7aa-e82c-4298-9084-25071fc12317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300830850 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3300830850
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2947766940
Short name T848
Test name
Test status
Simulation time 16583869 ps
CPU time 1 seconds
Started May 12 02:12:45 PM PDT 24
Finished May 12 02:12:47 PM PDT 24
Peak memory 215164 kb
Host smart-0496e93e-edc4-4389-9cbe-f24aa8c9b7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947766940 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2947766940
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3896333182
Short name T413
Test name
Test status
Simulation time 135035252 ps
CPU time 2.95 seconds
Started May 12 02:12:46 PM PDT 24
Finished May 12 02:12:51 PM PDT 24
Peak memory 216748 kb
Host smart-f430612e-7564-4275-adea-cee029474cb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896333182 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3896333182
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3895360430
Short name T379
Test name
Test status
Simulation time 56035510159 ps
CPU time 712.41 seconds
Started May 12 02:12:46 PM PDT 24
Finished May 12 02:24:41 PM PDT 24
Peak memory 219960 kb
Host smart-d783433a-36f1-466c-8a88-821496b2910a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895360430 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3895360430
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.3131139768
Short name T47
Test name
Test status
Simulation time 31308560 ps
CPU time 1.1 seconds
Started May 12 02:14:03 PM PDT 24
Finished May 12 02:14:05 PM PDT 24
Peak memory 219476 kb
Host smart-260b4671-9d04-4c48-b4ea-20f9cc6c59a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131139768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3131139768
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2157950129
Short name T274
Test name
Test status
Simulation time 235541374 ps
CPU time 1.12 seconds
Started May 12 02:14:02 PM PDT 24
Finished May 12 02:14:04 PM PDT 24
Peak memory 217028 kb
Host smart-8b24b5b9-e345-47f6-8e20-161ea675288b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157950129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2157950129
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.94926111
Short name T645
Test name
Test status
Simulation time 20980346 ps
CPU time 1.03 seconds
Started May 12 02:14:09 PM PDT 24
Finished May 12 02:14:12 PM PDT 24
Peak memory 232588 kb
Host smart-b1d66f14-c0bf-4a48-b7f0-7443156a0b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94926111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.94926111
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2797334365
Short name T422
Test name
Test status
Simulation time 56955326 ps
CPU time 1.38 seconds
Started May 12 02:14:03 PM PDT 24
Finished May 12 02:14:05 PM PDT 24
Peak memory 219588 kb
Host smart-e6162eea-1609-49f5-bbcc-d1730b2121d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797334365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2797334365
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.4280750276
Short name T412
Test name
Test status
Simulation time 21587885 ps
CPU time 1.02 seconds
Started May 12 02:14:08 PM PDT 24
Finished May 12 02:14:11 PM PDT 24
Peak memory 218400 kb
Host smart-11e8719a-9056-42c5-a32a-0741a5e7e3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280750276 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.4280750276
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3247831747
Short name T782
Test name
Test status
Simulation time 39035374 ps
CPU time 1.44 seconds
Started May 12 02:14:01 PM PDT 24
Finished May 12 02:14:04 PM PDT 24
Peak memory 218184 kb
Host smart-fbacbe6d-69c2-4037-b322-9dfe3e429c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247831747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3247831747
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.3049987560
Short name T117
Test name
Test status
Simulation time 27537980 ps
CPU time 1 seconds
Started May 12 02:14:00 PM PDT 24
Finished May 12 02:14:03 PM PDT 24
Peak memory 223596 kb
Host smart-b6b62dd3-0258-4da5-a58b-d756ece98135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049987560 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3049987560
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2615042856
Short name T333
Test name
Test status
Simulation time 37922524 ps
CPU time 1.28 seconds
Started May 12 02:14:01 PM PDT 24
Finished May 12 02:14:03 PM PDT 24
Peak memory 216984 kb
Host smart-287c3d52-c5a0-4808-bb28-9a92e6d15a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615042856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2615042856
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.1627750752
Short name T6
Test name
Test status
Simulation time 52044364 ps
CPU time 1.02 seconds
Started May 12 02:14:05 PM PDT 24
Finished May 12 02:14:08 PM PDT 24
Peak memory 219400 kb
Host smart-8cdf723d-bd55-42c5-adc0-82f937b18a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627750752 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1627750752
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3425600819
Short name T454
Test name
Test status
Simulation time 58577695 ps
CPU time 1.04 seconds
Started May 12 02:14:07 PM PDT 24
Finished May 12 02:14:09 PM PDT 24
Peak memory 216784 kb
Host smart-be69e28c-8952-47b3-8a0f-5e07447fa81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425600819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3425600819
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2771280334
Short name T398
Test name
Test status
Simulation time 21219509 ps
CPU time 0.99 seconds
Started May 12 02:14:09 PM PDT 24
Finished May 12 02:14:12 PM PDT 24
Peak memory 218448 kb
Host smart-17a4f4f9-dc12-460d-9d27-dd3ecb343b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771280334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2771280334
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3223682604
Short name T653
Test name
Test status
Simulation time 44733239 ps
CPU time 1.68 seconds
Started May 12 02:14:09 PM PDT 24
Finished May 12 02:14:13 PM PDT 24
Peak memory 216984 kb
Host smart-504cf832-50c5-43e2-b343-a8a74fd30514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223682604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3223682604
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.2465251243
Short name T93
Test name
Test status
Simulation time 57527223 ps
CPU time 0.97 seconds
Started May 12 02:14:02 PM PDT 24
Finished May 12 02:14:04 PM PDT 24
Peak memory 218380 kb
Host smart-5ede72be-ffd3-465f-be01-313d3b06a841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465251243 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2465251243
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3714525829
Short name T676
Test name
Test status
Simulation time 95842666 ps
CPU time 1.22 seconds
Started May 12 02:14:03 PM PDT 24
Finished May 12 02:14:05 PM PDT 24
Peak memory 215372 kb
Host smart-c23d2320-203e-4d06-9a63-b94aed569926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714525829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3714525829
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.2125789517
Short name T822
Test name
Test status
Simulation time 21840928 ps
CPU time 0.99 seconds
Started May 12 02:14:02 PM PDT 24
Finished May 12 02:14:04 PM PDT 24
Peak memory 218252 kb
Host smart-4223de3a-2f64-43ea-b2ec-6971035ad0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125789517 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2125789517
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3576349943
Short name T760
Test name
Test status
Simulation time 117667569 ps
CPU time 1.27 seconds
Started May 12 02:14:05 PM PDT 24
Finished May 12 02:14:07 PM PDT 24
Peak memory 218224 kb
Host smart-1377b9eb-f29e-4b14-a5a3-6b73cf098e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576349943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3576349943
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1130553957
Short name T411
Test name
Test status
Simulation time 74664446 ps
CPU time 1.12 seconds
Started May 12 02:14:09 PM PDT 24
Finished May 12 02:14:13 PM PDT 24
Peak memory 219648 kb
Host smart-2128237a-e91c-4a44-b6a0-b035b288d626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130553957 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1130553957
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2765676722
Short name T276
Test name
Test status
Simulation time 291986626 ps
CPU time 3.54 seconds
Started May 12 02:14:02 PM PDT 24
Finished May 12 02:14:06 PM PDT 24
Peak memory 219344 kb
Host smart-c38fde63-f4a2-4bb7-b81b-17865b2b50ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765676722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2765676722
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.1945961308
Short name T87
Test name
Test status
Simulation time 19088092 ps
CPU time 1.19 seconds
Started May 12 02:14:08 PM PDT 24
Finished May 12 02:14:11 PM PDT 24
Peak memory 223904 kb
Host smart-b95c0121-9045-43b4-9ffb-6f133b63fe53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945961308 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1945961308
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2784390633
Short name T416
Test name
Test status
Simulation time 53071784 ps
CPU time 1.61 seconds
Started May 12 02:14:05 PM PDT 24
Finished May 12 02:14:07 PM PDT 24
Peak memory 218128 kb
Host smart-8e9e497d-a9f8-47b7-aa2a-7cfdd4185335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784390633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2784390633
Directory /workspace/99.edn_genbits/latest
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