Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 2 0 2 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 7437 1 T99 33 T115 74 T124 22
all_values[1] 7437 1 T99 33 T115 74 T124 22


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7513 1 T99 29 T115 73 T124 21
auto[1] 7361 1 T99 37 T115 75 T124 23


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5799 1 T99 34 T115 52 T124 19
auto[1] 9075 1 T99 32 T115 96 T124 25


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8749 1 T99 45 T115 79 T124 24
auto[1] 6125 1 T99 21 T115 69 T124 20


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 12 0 12 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 1462 1 T99 9 T115 12 T124 4
all_values[0] auto[0] auto[0] auto[1] 734 1 T99 2 T115 4 T124 1
all_values[0] auto[0] auto[1] auto[0] 1401 1 T99 8 T115 11 T124 9
all_values[0] auto[0] auto[1] auto[1] 720 1 T99 4 T115 8 T150 2
all_values[0] auto[1] auto[0] auto[1] 1582 1 T99 3 T115 21 T124 5
all_values[0] auto[1] auto[1] auto[1] 1538 1 T99 7 T115 18 T124 3
all_values[1] auto[0] auto[0] auto[0] 1481 1 T99 6 T115 17 T124 1
all_values[1] auto[0] auto[0] auto[1] 724 1 T99 2 T115 7 T124 3
all_values[1] auto[0] auto[1] auto[0] 1455 1 T99 11 T115 12 T124 5
all_values[1] auto[0] auto[1] auto[1] 772 1 T99 3 T115 8 T124 1
all_values[1] auto[1] auto[0] auto[1] 1530 1 T99 7 T115 12 T124 7
all_values[1] auto[1] auto[1] auto[1] 1475 1 T99 4 T115 18 T124 5


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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