Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.33 98.24 93.80 97.02 83.72 96.62 99.77 91.12


Total test records in report: 980
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T297 /workspace/coverage/default/204.edn_genbits.4073929825 May 14 02:10:44 PM PDT 24 May 14 02:10:48 PM PDT 24 48017693 ps
T790 /workspace/coverage/default/89.edn_err.124444312 May 14 02:10:11 PM PDT 24 May 14 02:10:16 PM PDT 24 21284984 ps
T791 /workspace/coverage/default/44.edn_intr.514585296 May 14 02:09:30 PM PDT 24 May 14 02:09:34 PM PDT 24 22524102 ps
T792 /workspace/coverage/default/49.edn_intr.3240312686 May 14 02:09:40 PM PDT 24 May 14 02:09:43 PM PDT 24 38056319 ps
T77 /workspace/coverage/default/1.edn_err.2204466572 May 14 02:07:47 PM PDT 24 May 14 02:07:50 PM PDT 24 18146883 ps
T793 /workspace/coverage/default/26.edn_err.43844552 May 14 02:09:00 PM PDT 24 May 14 02:09:04 PM PDT 24 32596020 ps
T794 /workspace/coverage/default/44.edn_stress_all.1143068271 May 14 02:09:29 PM PDT 24 May 14 02:09:34 PM PDT 24 349163957 ps
T795 /workspace/coverage/default/13.edn_genbits.682630526 May 14 02:08:22 PM PDT 24 May 14 02:08:27 PM PDT 24 39225410 ps
T796 /workspace/coverage/default/121.edn_genbits.1933698119 May 14 02:10:12 PM PDT 24 May 14 02:10:17 PM PDT 24 128775122 ps
T797 /workspace/coverage/default/44.edn_err.2536360854 May 14 02:09:40 PM PDT 24 May 14 02:09:43 PM PDT 24 25997631 ps
T798 /workspace/coverage/default/87.edn_genbits.1268206809 May 14 02:10:11 PM PDT 24 May 14 02:10:16 PM PDT 24 29730470 ps
T799 /workspace/coverage/default/5.edn_err.1070266261 May 14 02:07:58 PM PDT 24 May 14 02:08:00 PM PDT 24 169301298 ps
T800 /workspace/coverage/default/142.edn_genbits.2791476792 May 14 02:10:22 PM PDT 24 May 14 02:10:25 PM PDT 24 33891955 ps
T801 /workspace/coverage/default/47.edn_disable_auto_req_mode.1392234922 May 14 02:09:40 PM PDT 24 May 14 02:09:44 PM PDT 24 41151844 ps
T802 /workspace/coverage/default/13.edn_alert_test.3537339306 May 14 02:08:27 PM PDT 24 May 14 02:08:29 PM PDT 24 18870675 ps
T803 /workspace/coverage/default/12.edn_smoke.2667904482 May 14 02:08:26 PM PDT 24 May 14 02:08:28 PM PDT 24 16237011 ps
T804 /workspace/coverage/default/100.edn_genbits.3361962115 May 14 02:10:13 PM PDT 24 May 14 02:10:17 PM PDT 24 76241348 ps
T805 /workspace/coverage/default/188.edn_genbits.3507771607 May 14 02:10:40 PM PDT 24 May 14 02:10:43 PM PDT 24 82286784 ps
T806 /workspace/coverage/default/18.edn_intr.951037746 May 14 02:08:37 PM PDT 24 May 14 02:08:41 PM PDT 24 29637965 ps
T807 /workspace/coverage/default/24.edn_alert_test.2314506411 May 14 02:08:51 PM PDT 24 May 14 02:08:56 PM PDT 24 17219619 ps
T808 /workspace/coverage/default/42.edn_disable.3902619567 May 14 02:09:28 PM PDT 24 May 14 02:09:32 PM PDT 24 10552669 ps
T809 /workspace/coverage/default/0.edn_disable.2047154281 May 14 02:07:38 PM PDT 24 May 14 02:07:41 PM PDT 24 91717471 ps
T810 /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1238709350 May 14 02:08:47 PM PDT 24 May 14 02:16:33 PM PDT 24 61973884493 ps
T811 /workspace/coverage/default/27.edn_err.3746269862 May 14 02:08:58 PM PDT 24 May 14 02:09:02 PM PDT 24 25057908 ps
T812 /workspace/coverage/default/292.edn_genbits.2694905088 May 14 02:11:01 PM PDT 24 May 14 02:11:05 PM PDT 24 77846327 ps
T813 /workspace/coverage/default/39.edn_alert_test.2475245095 May 14 02:09:24 PM PDT 24 May 14 02:09:29 PM PDT 24 11566575 ps
T814 /workspace/coverage/default/34.edn_genbits.1894431921 May 14 02:09:13 PM PDT 24 May 14 02:09:16 PM PDT 24 56143461 ps
T815 /workspace/coverage/default/33.edn_disable.3359959626 May 14 02:09:14 PM PDT 24 May 14 02:09:17 PM PDT 24 57983602 ps
T816 /workspace/coverage/default/13.edn_stress_all.3292517997 May 14 02:08:22 PM PDT 24 May 14 02:08:28 PM PDT 24 429718096 ps
T817 /workspace/coverage/default/17.edn_alert_test.3846104619 May 14 02:08:34 PM PDT 24 May 14 02:08:36 PM PDT 24 43351447 ps
T818 /workspace/coverage/default/41.edn_genbits.2933719478 May 14 02:09:25 PM PDT 24 May 14 02:09:32 PM PDT 24 334667667 ps
T819 /workspace/coverage/default/5.edn_alert.884858858 May 14 02:07:58 PM PDT 24 May 14 02:08:00 PM PDT 24 47043752 ps
T820 /workspace/coverage/default/270.edn_genbits.3348157759 May 14 02:10:57 PM PDT 24 May 14 02:11:00 PM PDT 24 20715096 ps
T821 /workspace/coverage/default/33.edn_stress_all.2257842699 May 14 02:09:04 PM PDT 24 May 14 02:09:13 PM PDT 24 268042716 ps
T822 /workspace/coverage/default/291.edn_genbits.3712342040 May 14 02:11:00 PM PDT 24 May 14 02:11:04 PM PDT 24 155788451 ps
T823 /workspace/coverage/default/2.edn_stress_all.2249155667 May 14 02:07:50 PM PDT 24 May 14 02:07:56 PM PDT 24 1063068006 ps
T824 /workspace/coverage/default/36.edn_err.4018870798 May 14 02:09:20 PM PDT 24 May 14 02:09:22 PM PDT 24 22005918 ps
T825 /workspace/coverage/default/55.edn_err.21044338 May 14 02:09:49 PM PDT 24 May 14 02:09:52 PM PDT 24 53616141 ps
T826 /workspace/coverage/default/102.edn_genbits.2936656833 May 14 02:10:08 PM PDT 24 May 14 02:10:10 PM PDT 24 59197446 ps
T827 /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2005388847 May 14 02:09:40 PM PDT 24 May 14 02:45:02 PM PDT 24 82328804417 ps
T828 /workspace/coverage/default/34.edn_alert.2644880220 May 14 02:09:13 PM PDT 24 May 14 02:09:16 PM PDT 24 38045078 ps
T829 /workspace/coverage/default/27.edn_genbits.3239794433 May 14 02:08:55 PM PDT 24 May 14 02:09:01 PM PDT 24 210035468 ps
T830 /workspace/coverage/default/68.edn_genbits.900838571 May 14 02:09:53 PM PDT 24 May 14 02:09:56 PM PDT 24 84607016 ps
T831 /workspace/coverage/default/3.edn_alert_test.1511079121 May 14 02:07:55 PM PDT 24 May 14 02:07:57 PM PDT 24 24667320 ps
T832 /workspace/coverage/default/35.edn_err.3670712069 May 14 02:09:13 PM PDT 24 May 14 02:09:17 PM PDT 24 23414461 ps
T833 /workspace/coverage/default/178.edn_genbits.1100600829 May 14 02:10:31 PM PDT 24 May 14 02:10:35 PM PDT 24 45818064 ps
T92 /workspace/coverage/default/41.edn_disable.115355023 May 14 02:09:29 PM PDT 24 May 14 02:09:32 PM PDT 24 10438263 ps
T834 /workspace/coverage/default/279.edn_genbits.435154635 May 14 02:10:54 PM PDT 24 May 14 02:10:57 PM PDT 24 48218095 ps
T835 /workspace/coverage/default/17.edn_alert.1127480806 May 14 02:08:34 PM PDT 24 May 14 02:08:37 PM PDT 24 64808759 ps
T836 /workspace/coverage/default/7.edn_disable_auto_req_mode.2168604090 May 14 02:08:00 PM PDT 24 May 14 02:08:02 PM PDT 24 433739719 ps
T837 /workspace/coverage/default/25.edn_intr.3109555874 May 14 02:08:50 PM PDT 24 May 14 02:08:55 PM PDT 24 25138428 ps
T838 /workspace/coverage/default/30.edn_intr.2484726720 May 14 02:09:00 PM PDT 24 May 14 02:09:05 PM PDT 24 20256929 ps
T839 /workspace/coverage/default/269.edn_genbits.671190954 May 14 02:11:02 PM PDT 24 May 14 02:11:06 PM PDT 24 108394314 ps
T840 /workspace/coverage/default/11.edn_smoke.1070128900 May 14 02:08:28 PM PDT 24 May 14 02:08:31 PM PDT 24 17834508 ps
T841 /workspace/coverage/default/8.edn_alert.2950808506 May 14 02:08:09 PM PDT 24 May 14 02:08:12 PM PDT 24 28836174 ps
T842 /workspace/coverage/default/164.edn_genbits.3756278265 May 14 02:10:18 PM PDT 24 May 14 02:10:23 PM PDT 24 46035332 ps
T843 /workspace/coverage/default/25.edn_alert_test.3699422887 May 14 02:08:52 PM PDT 24 May 14 02:08:57 PM PDT 24 12771693 ps
T844 /workspace/coverage/default/185.edn_genbits.864144988 May 14 02:10:40 PM PDT 24 May 14 02:10:43 PM PDT 24 42353567 ps
T845 /workspace/coverage/default/36.edn_stress_all.1670370255 May 14 02:09:19 PM PDT 24 May 14 02:09:24 PM PDT 24 578995362 ps
T846 /workspace/coverage/default/40.edn_alert_test.1544287572 May 14 02:09:22 PM PDT 24 May 14 02:09:26 PM PDT 24 36214086 ps
T847 /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2306908700 May 14 02:08:21 PM PDT 24 May 14 02:25:01 PM PDT 24 77343597768 ps
T848 /workspace/coverage/default/113.edn_genbits.4159016280 May 14 02:10:09 PM PDT 24 May 14 02:10:12 PM PDT 24 31704417 ps
T849 /workspace/coverage/default/271.edn_genbits.3577044327 May 14 02:11:00 PM PDT 24 May 14 02:11:04 PM PDT 24 33091656 ps
T93 /workspace/coverage/default/32.edn_err.3678747000 May 14 02:09:10 PM PDT 24 May 14 02:09:13 PM PDT 24 22919661 ps
T850 /workspace/coverage/default/91.edn_err.3639542664 May 14 02:10:09 PM PDT 24 May 14 02:10:11 PM PDT 24 25039131 ps
T851 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3733426727 May 14 01:58:27 PM PDT 24 May 14 01:58:29 PM PDT 24 19314612 ps
T852 /workspace/coverage/cover_reg_top/39.edn_intr_test.1929149597 May 14 01:58:44 PM PDT 24 May 14 01:58:45 PM PDT 24 12407175 ps
T238 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.793735541 May 14 01:57:10 PM PDT 24 May 14 01:57:12 PM PDT 24 382341881 ps
T853 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3134833313 May 14 01:58:05 PM PDT 24 May 14 01:58:08 PM PDT 24 126365395 ps
T230 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.627972886 May 14 01:57:18 PM PDT 24 May 14 01:57:20 PM PDT 24 36605440 ps
T212 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1354793764 May 14 01:57:28 PM PDT 24 May 14 01:57:30 PM PDT 24 64365560 ps
T854 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1881422867 May 14 01:57:33 PM PDT 24 May 14 01:57:38 PM PDT 24 182092832 ps
T234 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2049797670 May 14 01:57:33 PM PDT 24 May 14 01:57:37 PM PDT 24 368869203 ps
T239 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1207615996 May 14 01:57:40 PM PDT 24 May 14 01:57:43 PM PDT 24 44643693 ps
T855 /workspace/coverage/cover_reg_top/38.edn_intr_test.1023239845 May 14 01:58:55 PM PDT 24 May 14 01:58:57 PM PDT 24 41113478 ps
T856 /workspace/coverage/cover_reg_top/17.edn_tl_errors.405532524 May 14 01:58:28 PM PDT 24 May 14 01:58:31 PM PDT 24 48168258 ps
T857 /workspace/coverage/cover_reg_top/1.edn_intr_test.2360721739 May 14 01:57:25 PM PDT 24 May 14 01:57:27 PM PDT 24 11886258 ps
T213 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.505155418 May 14 01:57:42 PM PDT 24 May 14 01:57:45 PM PDT 24 47697860 ps
T231 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3442524887 May 14 01:57:59 PM PDT 24 May 14 01:58:01 PM PDT 24 74004107 ps
T240 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3799189461 May 14 01:58:22 PM PDT 24 May 14 01:58:25 PM PDT 24 98498081 ps
T235 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3870134625 May 14 01:57:43 PM PDT 24 May 14 01:57:46 PM PDT 24 23972235 ps
T858 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1085431672 May 14 01:57:26 PM PDT 24 May 14 01:57:28 PM PDT 24 23950838 ps
T214 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2599264726 May 14 01:58:05 PM PDT 24 May 14 01:58:07 PM PDT 24 30841856 ps
T859 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3412698829 May 14 01:58:36 PM PDT 24 May 14 01:58:38 PM PDT 24 56407323 ps
T860 /workspace/coverage/cover_reg_top/33.edn_intr_test.2641172050 May 14 01:58:44 PM PDT 24 May 14 01:58:46 PM PDT 24 15885976 ps
T861 /workspace/coverage/cover_reg_top/15.edn_intr_test.4001540114 May 14 01:58:19 PM PDT 24 May 14 01:58:20 PM PDT 24 12046106 ps
T862 /workspace/coverage/cover_reg_top/18.edn_intr_test.4293156951 May 14 01:58:26 PM PDT 24 May 14 01:58:28 PM PDT 24 81476171 ps
T215 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3265491105 May 14 01:58:28 PM PDT 24 May 14 01:58:30 PM PDT 24 60077700 ps
T244 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3171637079 May 14 01:58:26 PM PDT 24 May 14 01:58:28 PM PDT 24 174018307 ps
T236 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3820550664 May 14 01:57:33 PM PDT 24 May 14 01:57:35 PM PDT 24 21744645 ps
T863 /workspace/coverage/cover_reg_top/15.edn_tl_errors.4229712015 May 14 01:58:18 PM PDT 24 May 14 01:58:21 PM PDT 24 49588673 ps
T237 /workspace/coverage/cover_reg_top/8.edn_csr_rw.4168372820 May 14 01:57:59 PM PDT 24 May 14 01:58:01 PM PDT 24 22714475 ps
T864 /workspace/coverage/cover_reg_top/10.edn_tl_errors.4199652822 May 14 01:58:03 PM PDT 24 May 14 01:58:09 PM PDT 24 177891710 ps
T216 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1124969642 May 14 01:57:41 PM PDT 24 May 14 01:57:44 PM PDT 24 13138758 ps
T865 /workspace/coverage/cover_reg_top/14.edn_intr_test.1386102810 May 14 01:58:18 PM PDT 24 May 14 01:58:20 PM PDT 24 16695153 ps
T866 /workspace/coverage/cover_reg_top/13.edn_intr_test.2784267443 May 14 01:58:10 PM PDT 24 May 14 01:58:12 PM PDT 24 31068097 ps
T867 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1973448784 May 14 01:57:34 PM PDT 24 May 14 01:57:36 PM PDT 24 15928736 ps
T217 /workspace/coverage/cover_reg_top/15.edn_csr_rw.853492197 May 14 01:58:21 PM PDT 24 May 14 01:58:23 PM PDT 24 16355386 ps
T245 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3090499277 May 14 01:58:11 PM PDT 24 May 14 01:58:14 PM PDT 24 296159172 ps
T868 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3462035761 May 14 01:57:09 PM PDT 24 May 14 01:57:11 PM PDT 24 41722348 ps
T869 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3074391911 May 14 01:58:13 PM PDT 24 May 14 01:58:16 PM PDT 24 33114717 ps
T870 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2525159359 May 14 01:58:21 PM PDT 24 May 14 01:58:23 PM PDT 24 74636576 ps
T871 /workspace/coverage/cover_reg_top/31.edn_intr_test.2906354745 May 14 01:58:54 PM PDT 24 May 14 01:58:56 PM PDT 24 23627746 ps
T872 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.77279758 May 14 01:58:02 PM PDT 24 May 14 01:58:05 PM PDT 24 185545789 ps
T873 /workspace/coverage/cover_reg_top/7.edn_tl_errors.415555278 May 14 01:57:50 PM PDT 24 May 14 01:57:54 PM PDT 24 134513114 ps
T874 /workspace/coverage/cover_reg_top/40.edn_intr_test.839334747 May 14 01:58:46 PM PDT 24 May 14 01:58:49 PM PDT 24 16783853 ps
T875 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1587629849 May 14 01:58:10 PM PDT 24 May 14 01:58:14 PM PDT 24 39932114 ps
T876 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.934801346 May 14 01:57:26 PM PDT 24 May 14 01:57:30 PM PDT 24 368255841 ps
T877 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3119227638 May 14 01:57:34 PM PDT 24 May 14 01:57:39 PM PDT 24 233508036 ps
T218 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2722358137 May 14 01:58:33 PM PDT 24 May 14 01:58:35 PM PDT 24 31619845 ps
T219 /workspace/coverage/cover_reg_top/1.edn_csr_rw.1292857006 May 14 01:57:25 PM PDT 24 May 14 01:57:27 PM PDT 24 14624734 ps
T878 /workspace/coverage/cover_reg_top/24.edn_intr_test.2917974402 May 14 01:58:35 PM PDT 24 May 14 01:58:36 PM PDT 24 26230771 ps
T879 /workspace/coverage/cover_reg_top/17.edn_intr_test.117650403 May 14 01:58:30 PM PDT 24 May 14 01:58:31 PM PDT 24 12481682 ps
T880 /workspace/coverage/cover_reg_top/11.edn_intr_test.2167394626 May 14 01:58:11 PM PDT 24 May 14 01:58:13 PM PDT 24 29236351 ps
T881 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3575441726 May 14 01:57:53 PM PDT 24 May 14 01:57:55 PM PDT 24 25426937 ps
T220 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2532147507 May 14 01:58:21 PM PDT 24 May 14 01:58:23 PM PDT 24 57263792 ps
T882 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.926683005 May 14 01:57:49 PM PDT 24 May 14 01:57:51 PM PDT 24 24102124 ps
T883 /workspace/coverage/cover_reg_top/36.edn_intr_test.1398258847 May 14 01:58:52 PM PDT 24 May 14 01:58:54 PM PDT 24 23302116 ps
T884 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4257614849 May 14 01:57:25 PM PDT 24 May 14 01:57:28 PM PDT 24 131522396 ps
T885 /workspace/coverage/cover_reg_top/29.edn_intr_test.3933182158 May 14 01:58:46 PM PDT 24 May 14 01:58:48 PM PDT 24 24596822 ps
T886 /workspace/coverage/cover_reg_top/45.edn_intr_test.149313022 May 14 01:58:43 PM PDT 24 May 14 01:58:44 PM PDT 24 12510861 ps
T887 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3543557596 May 14 01:57:34 PM PDT 24 May 14 01:57:36 PM PDT 24 79545891 ps
T888 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.968587889 May 14 01:58:46 PM PDT 24 May 14 01:58:48 PM PDT 24 216331233 ps
T232 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1448447187 May 14 01:58:01 PM PDT 24 May 14 01:58:03 PM PDT 24 17935174 ps
T889 /workspace/coverage/cover_reg_top/25.edn_intr_test.2860827929 May 14 01:58:33 PM PDT 24 May 14 01:58:35 PM PDT 24 74866010 ps
T233 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.312839960 May 14 01:57:48 PM PDT 24 May 14 01:57:50 PM PDT 24 138338118 ps
T890 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3667243790 May 14 01:58:26 PM PDT 24 May 14 01:58:30 PM PDT 24 88078710 ps
T891 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3605902617 May 14 01:57:17 PM PDT 24 May 14 01:57:18 PM PDT 24 16368321 ps
T892 /workspace/coverage/cover_reg_top/23.edn_intr_test.2359987585 May 14 01:58:35 PM PDT 24 May 14 01:58:37 PM PDT 24 16800537 ps
T221 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.574583693 May 14 01:58:04 PM PDT 24 May 14 01:58:06 PM PDT 24 12349480 ps
T893 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.442825769 May 14 01:57:25 PM PDT 24 May 14 01:57:27 PM PDT 24 33921663 ps
T222 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1029201524 May 14 01:57:32 PM PDT 24 May 14 01:57:34 PM PDT 24 43722725 ps
T894 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4113082068 May 14 01:57:33 PM PDT 24 May 14 01:57:36 PM PDT 24 91179163 ps
T895 /workspace/coverage/cover_reg_top/20.edn_intr_test.2761536931 May 14 01:58:35 PM PDT 24 May 14 01:58:36 PM PDT 24 66284966 ps
T896 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.120455944 May 14 01:57:18 PM PDT 24 May 14 01:57:20 PM PDT 24 24060057 ps
T897 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3739407512 May 14 01:57:17 PM PDT 24 May 14 01:57:22 PM PDT 24 134323288 ps
T898 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3097787164 May 14 01:58:33 PM PDT 24 May 14 01:58:35 PM PDT 24 30295471 ps
T899 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1452359845 May 14 01:57:55 PM PDT 24 May 14 01:57:57 PM PDT 24 31510899 ps
T900 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2567831726 May 14 01:57:40 PM PDT 24 May 14 01:57:43 PM PDT 24 28194032 ps
T901 /workspace/coverage/cover_reg_top/2.edn_intr_test.1833075482 May 14 01:57:31 PM PDT 24 May 14 01:57:32 PM PDT 24 97501561 ps
T902 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2453246379 May 14 01:58:09 PM PDT 24 May 14 01:58:11 PM PDT 24 60283866 ps
T903 /workspace/coverage/cover_reg_top/32.edn_intr_test.52596247 May 14 01:58:44 PM PDT 24 May 14 01:58:46 PM PDT 24 36446506 ps
T904 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1615209982 May 14 01:57:30 PM PDT 24 May 14 01:57:32 PM PDT 24 17997462 ps
T905 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.99804114 May 14 01:58:28 PM PDT 24 May 14 01:58:30 PM PDT 24 24450479 ps
T906 /workspace/coverage/cover_reg_top/9.edn_intr_test.4042408345 May 14 01:58:01 PM PDT 24 May 14 01:58:03 PM PDT 24 23822988 ps
T907 /workspace/coverage/cover_reg_top/21.edn_intr_test.2452154406 May 14 01:58:33 PM PDT 24 May 14 01:58:35 PM PDT 24 13672373 ps
T908 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.247457428 May 14 01:57:43 PM PDT 24 May 14 01:57:47 PM PDT 24 20087146 ps
T909 /workspace/coverage/cover_reg_top/48.edn_intr_test.2017690918 May 14 01:58:42 PM PDT 24 May 14 01:58:44 PM PDT 24 71029891 ps
T910 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2798912411 May 14 01:58:11 PM PDT 24 May 14 01:58:14 PM PDT 24 51623723 ps
T911 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.519782590 May 14 01:57:58 PM PDT 24 May 14 01:58:01 PM PDT 24 29576516 ps
T912 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2172778866 May 14 01:57:50 PM PDT 24 May 14 01:57:53 PM PDT 24 184237883 ps
T913 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2388845642 May 14 01:58:36 PM PDT 24 May 14 01:58:39 PM PDT 24 341846529 ps
T914 /workspace/coverage/cover_reg_top/30.edn_intr_test.710441321 May 14 01:58:47 PM PDT 24 May 14 01:58:49 PM PDT 24 13276983 ps
T915 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1464871403 May 14 01:58:13 PM PDT 24 May 14 01:58:15 PM PDT 24 80705341 ps
T223 /workspace/coverage/cover_reg_top/0.edn_csr_rw.1011745707 May 14 01:57:18 PM PDT 24 May 14 01:57:20 PM PDT 24 27940965 ps
T916 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1963955200 May 14 01:58:11 PM PDT 24 May 14 01:58:13 PM PDT 24 23117565 ps
T917 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3644072867 May 14 01:57:25 PM PDT 24 May 14 01:57:28 PM PDT 24 377827789 ps
T918 /workspace/coverage/cover_reg_top/2.edn_csr_rw.416651965 May 14 01:57:31 PM PDT 24 May 14 01:57:33 PM PDT 24 17141296 ps
T919 /workspace/coverage/cover_reg_top/22.edn_intr_test.3219729034 May 14 01:58:33 PM PDT 24 May 14 01:58:35 PM PDT 24 39718629 ps
T920 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1051154744 May 14 01:58:09 PM PDT 24 May 14 01:58:11 PM PDT 24 19563470 ps
T246 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1630537068 May 14 01:58:03 PM PDT 24 May 14 01:58:06 PM PDT 24 177639105 ps
T921 /workspace/coverage/cover_reg_top/42.edn_intr_test.1259615658 May 14 01:58:46 PM PDT 24 May 14 01:58:48 PM PDT 24 28276082 ps
T922 /workspace/coverage/cover_reg_top/9.edn_csr_rw.4087393173 May 14 01:58:04 PM PDT 24 May 14 01:58:06 PM PDT 24 36072900 ps
T923 /workspace/coverage/cover_reg_top/0.edn_intr_test.2028704963 May 14 01:57:09 PM PDT 24 May 14 01:57:11 PM PDT 24 37978228 ps
T924 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3566554990 May 14 01:57:58 PM PDT 24 May 14 01:58:01 PM PDT 24 214583515 ps
T925 /workspace/coverage/cover_reg_top/10.edn_intr_test.484879986 May 14 01:58:04 PM PDT 24 May 14 01:58:06 PM PDT 24 23367011 ps
T926 /workspace/coverage/cover_reg_top/14.edn_tl_errors.4084866871 May 14 01:58:21 PM PDT 24 May 14 01:58:24 PM PDT 24 82539802 ps
T927 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.924393305 May 14 01:58:26 PM PDT 24 May 14 01:58:29 PM PDT 24 104819995 ps
T248 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3479045193 May 14 01:57:25 PM PDT 24 May 14 01:57:29 PM PDT 24 92909181 ps
T928 /workspace/coverage/cover_reg_top/5.edn_intr_test.1997477342 May 14 01:57:48 PM PDT 24 May 14 01:57:50 PM PDT 24 15221417 ps
T929 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1162669791 May 14 01:58:28 PM PDT 24 May 14 01:58:30 PM PDT 24 17249188 ps
T249 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1857914364 May 14 01:58:27 PM PDT 24 May 14 01:58:31 PM PDT 24 163356474 ps
T930 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2808411019 May 14 01:57:53 PM PDT 24 May 14 01:57:57 PM PDT 24 216116421 ps
T931 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.4200078861 May 14 01:57:58 PM PDT 24 May 14 01:58:01 PM PDT 24 142591491 ps
T932 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3979051415 May 14 01:57:24 PM PDT 24 May 14 01:57:26 PM PDT 24 26134868 ps
T933 /workspace/coverage/cover_reg_top/46.edn_intr_test.1103162078 May 14 01:58:55 PM PDT 24 May 14 01:58:57 PM PDT 24 64308986 ps
T934 /workspace/coverage/cover_reg_top/19.edn_intr_test.3784633772 May 14 01:58:46 PM PDT 24 May 14 01:58:48 PM PDT 24 17641577 ps
T247 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.515476839 May 14 01:57:49 PM PDT 24 May 14 01:57:52 PM PDT 24 86230145 ps
T935 /workspace/coverage/cover_reg_top/8.edn_tl_errors.2717354946 May 14 01:57:59 PM PDT 24 May 14 01:58:02 PM PDT 24 37475809 ps
T936 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1856240258 May 14 01:58:20 PM PDT 24 May 14 01:58:22 PM PDT 24 37775945 ps
T937 /workspace/coverage/cover_reg_top/41.edn_intr_test.2346388357 May 14 01:58:45 PM PDT 24 May 14 01:58:46 PM PDT 24 135459481 ps
T938 /workspace/coverage/cover_reg_top/8.edn_intr_test.3434260565 May 14 01:57:58 PM PDT 24 May 14 01:58:00 PM PDT 24 134904081 ps
T939 /workspace/coverage/cover_reg_top/35.edn_intr_test.563645184 May 14 01:58:44 PM PDT 24 May 14 01:58:46 PM PDT 24 43817215 ps
T940 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2023360201 May 14 01:58:28 PM PDT 24 May 14 01:58:30 PM PDT 24 75126058 ps
T941 /workspace/coverage/cover_reg_top/12.edn_csr_rw.3693211862 May 14 01:58:09 PM PDT 24 May 14 01:58:11 PM PDT 24 33266382 ps
T942 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2695801821 May 14 01:58:28 PM PDT 24 May 14 01:58:31 PM PDT 24 63428183 ps
T943 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2159710041 May 14 01:58:12 PM PDT 24 May 14 01:58:14 PM PDT 24 357335311 ps
T944 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2027978414 May 14 01:58:26 PM PDT 24 May 14 01:58:28 PM PDT 24 57556940 ps
T945 /workspace/coverage/cover_reg_top/3.edn_intr_test.1124896974 May 14 01:57:32 PM PDT 24 May 14 01:57:34 PM PDT 24 21713399 ps
T946 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2801045911 May 14 01:57:16 PM PDT 24 May 14 01:57:18 PM PDT 24 67307707 ps
T947 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.647467047 May 14 01:57:41 PM PDT 24 May 14 01:57:46 PM PDT 24 114700246 ps
T224 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2317049757 May 14 01:58:09 PM PDT 24 May 14 01:58:11 PM PDT 24 45333680 ps
T948 /workspace/coverage/cover_reg_top/7.edn_intr_test.1080784307 May 14 01:57:56 PM PDT 24 May 14 01:57:58 PM PDT 24 24820219 ps
T225 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1346224616 May 14 01:58:34 PM PDT 24 May 14 01:58:35 PM PDT 24 28124458 ps
T949 /workspace/coverage/cover_reg_top/16.edn_intr_test.3069867876 May 14 01:58:26 PM PDT 24 May 14 01:58:28 PM PDT 24 16551799 ps
T950 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1300443173 May 14 01:58:35 PM PDT 24 May 14 01:58:38 PM PDT 24 231643452 ps
T951 /workspace/coverage/cover_reg_top/26.edn_intr_test.3781487304 May 14 01:58:46 PM PDT 24 May 14 01:58:49 PM PDT 24 39685741 ps
T952 /workspace/coverage/cover_reg_top/17.edn_csr_rw.821756674 May 14 01:58:25 PM PDT 24 May 14 01:58:26 PM PDT 24 41494854 ps
T226 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.705901423 May 14 01:57:36 PM PDT 24 May 14 01:57:38 PM PDT 24 23634479 ps
T953 /workspace/coverage/cover_reg_top/44.edn_intr_test.1206938838 May 14 01:58:43 PM PDT 24 May 14 01:58:45 PM PDT 24 20069607 ps
T954 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3560431686 May 14 01:57:54 PM PDT 24 May 14 01:57:56 PM PDT 24 15173829 ps
T955 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.4156388114 May 14 01:58:19 PM PDT 24 May 14 01:58:21 PM PDT 24 69011371 ps
T956 /workspace/coverage/cover_reg_top/27.edn_intr_test.2019137567 May 14 01:58:34 PM PDT 24 May 14 01:58:36 PM PDT 24 65609143 ps
T957 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3063682803 May 14 01:58:13 PM PDT 24 May 14 01:58:17 PM PDT 24 396102023 ps
T958 /workspace/coverage/cover_reg_top/7.edn_csr_rw.129864933 May 14 01:57:57 PM PDT 24 May 14 01:57:59 PM PDT 24 17070013 ps
T959 /workspace/coverage/cover_reg_top/12.edn_tl_errors.121155188 May 14 01:58:11 PM PDT 24 May 14 01:58:14 PM PDT 24 55670963 ps
T960 /workspace/coverage/cover_reg_top/4.edn_intr_test.1114303445 May 14 01:57:41 PM PDT 24 May 14 01:57:44 PM PDT 24 34099733 ps
T961 /workspace/coverage/cover_reg_top/12.edn_intr_test.137065448 May 14 01:58:10 PM PDT 24 May 14 01:58:12 PM PDT 24 12050597 ps
T962 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.54518818 May 14 01:57:48 PM PDT 24 May 14 01:57:50 PM PDT 24 76407154 ps
T963 /workspace/coverage/cover_reg_top/47.edn_intr_test.1225875770 May 14 01:58:43 PM PDT 24 May 14 01:58:45 PM PDT 24 38387187 ps
T964 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3067913623 May 14 01:57:54 PM PDT 24 May 14 01:57:56 PM PDT 24 29246518 ps
T965 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3193312607 May 14 01:57:33 PM PDT 24 May 14 01:57:36 PM PDT 24 1125738595 ps
T966 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.81328105 May 14 01:57:57 PM PDT 24 May 14 01:58:00 PM PDT 24 319329040 ps
T227 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1948871096 May 14 01:58:19 PM PDT 24 May 14 01:58:20 PM PDT 24 16849957 ps
T967 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2872888310 May 14 01:58:21 PM PDT 24 May 14 01:58:23 PM PDT 24 96906721 ps
T228 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2931498622 May 14 01:57:49 PM PDT 24 May 14 01:57:51 PM PDT 24 14003331 ps
T968 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.794912869 May 14 01:58:10 PM PDT 24 May 14 01:58:12 PM PDT 24 21080214 ps
T969 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3516406955 May 14 01:57:44 PM PDT 24 May 14 01:57:49 PM PDT 24 608446533 ps
T970 /workspace/coverage/cover_reg_top/28.edn_intr_test.3994612619 May 14 01:58:47 PM PDT 24 May 14 01:58:49 PM PDT 24 15919143 ps
T971 /workspace/coverage/cover_reg_top/37.edn_intr_test.1002016397 May 14 01:58:45 PM PDT 24 May 14 01:58:47 PM PDT 24 16464395 ps
T972 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1860328631 May 14 01:57:26 PM PDT 24 May 14 01:57:28 PM PDT 24 77752937 ps
T973 /workspace/coverage/cover_reg_top/49.edn_intr_test.915681340 May 14 01:58:51 PM PDT 24 May 14 01:58:53 PM PDT 24 11737695 ps
T974 /workspace/coverage/cover_reg_top/6.edn_intr_test.3189597030 May 14 01:57:52 PM PDT 24 May 14 01:57:54 PM PDT 24 48044660 ps
T975 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3816108561 May 14 01:58:10 PM PDT 24 May 14 01:58:12 PM PDT 24 103782863 ps
T976 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3149406887 May 14 01:57:48 PM PDT 24 May 14 01:57:52 PM PDT 24 186018713 ps
T229 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3629998891 May 14 01:57:49 PM PDT 24 May 14 01:57:51 PM PDT 24 41135077 ps
T977 /workspace/coverage/cover_reg_top/43.edn_intr_test.696435282 May 14 01:58:44 PM PDT 24 May 14 01:58:46 PM PDT 24 13324421 ps
T978 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3415198750 May 14 01:57:50 PM PDT 24 May 14 01:57:53 PM PDT 24 90898517 ps
T979 /workspace/coverage/cover_reg_top/34.edn_intr_test.1794258847 May 14 01:58:44 PM PDT 24 May 14 01:58:46 PM PDT 24 74939719 ps
T980 /workspace/coverage/cover_reg_top/18.edn_csr_rw.2618664062 May 14 01:58:26 PM PDT 24 May 14 01:58:28 PM PDT 24 12800267 ps

Test location /workspace/coverage/default/83.edn_genbits.3037214835
Short name T10
Test name
Test status
Simulation time 73710440 ps
CPU time 1.7 seconds
Started May 14 02:10:08 PM PDT 24
Finished May 14 02:10:10 PM PDT 24
Peak memory 214984 kb
Host smart-4d960203-d4c5-458e-af35-803706f2609a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037214835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3037214835
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1374247871
Short name T115
Test name
Test status
Simulation time 52030506546 ps
CPU time 1335.42 seconds
Started May 14 02:08:35 PM PDT 24
Finished May 14 02:30:53 PM PDT 24
Peak memory 221416 kb
Host smart-43854639-a3d4-4a73-8412-5560c2c720e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374247871 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1374247871
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.edn_alert.2857984128
Short name T21
Test name
Test status
Simulation time 26959564 ps
CPU time 1.22 seconds
Started May 14 02:08:58 PM PDT 24
Finished May 14 02:09:03 PM PDT 24
Peak memory 215336 kb
Host smart-a8c815b6-2dd7-4afd-8b1e-c8139b5518b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857984128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2857984128
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3727839581
Short name T16
Test name
Test status
Simulation time 951088689 ps
CPU time 8.51 seconds
Started May 14 02:07:46 PM PDT 24
Finished May 14 02:07:55 PM PDT 24
Peak memory 238056 kb
Host smart-c4344f4d-fa97-4680-9a70-1e35b69d3da0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727839581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3727839581
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_err.1419577212
Short name T6
Test name
Test status
Simulation time 35776847 ps
CPU time 1.25 seconds
Started May 14 02:07:40 PM PDT 24
Finished May 14 02:07:43 PM PDT 24
Peak memory 229104 kb
Host smart-87301985-f3a5-4e6c-885e-905f6915c5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419577212 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1419577212
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/22.edn_stress_all.3874474167
Short name T149
Test name
Test status
Simulation time 220250487 ps
CPU time 4.58 seconds
Started May 14 02:08:46 PM PDT 24
Finished May 14 02:08:53 PM PDT 24
Peak memory 214992 kb
Host smart-b8bda652-c98e-4cef-9b84-c856e90b151f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874474167 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3874474167
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/88.edn_genbits.2415541000
Short name T20
Test name
Test status
Simulation time 97786786 ps
CPU time 1.49 seconds
Started May 14 02:10:10 PM PDT 24
Finished May 14 02:10:15 PM PDT 24
Peak memory 218436 kb
Host smart-9c720d71-d642-470b-98f6-c2656853f068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415541000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2415541000
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.4079453851
Short name T23
Test name
Test status
Simulation time 49465959 ps
CPU time 1.26 seconds
Started May 14 02:08:22 PM PDT 24
Finished May 14 02:08:27 PM PDT 24
Peak memory 215280 kb
Host smart-a100a211-92b7-4e73-8264-67a9f9896fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079453851 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.4079453851
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.4108938974
Short name T190
Test name
Test status
Simulation time 95496424674 ps
CPU time 257.76 seconds
Started May 14 02:09:22 PM PDT 24
Finished May 14 02:13:42 PM PDT 24
Peak memory 217592 kb
Host smart-f64f79cf-1f7f-480b-9117-c79e135df83a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108938974 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.4108938974
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.103199687
Short name T32
Test name
Test status
Simulation time 52977045 ps
CPU time 1 seconds
Started May 14 02:08:50 PM PDT 24
Finished May 14 02:08:55 PM PDT 24
Peak memory 216352 kb
Host smart-645ca169-4e3e-4bbb-b66b-9fa88929f31c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103199687 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.103199687
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_regwen.1504210177
Short name T106
Test name
Test status
Simulation time 30410521 ps
CPU time 0.98 seconds
Started May 14 02:08:01 PM PDT 24
Finished May 14 02:08:03 PM PDT 24
Peak memory 206728 kb
Host smart-bf26cc0e-afbb-4a02-bd1a-ee15dc878755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504210177 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1504210177
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/267.edn_genbits.440467123
Short name T119
Test name
Test status
Simulation time 82543509 ps
CPU time 1.4 seconds
Started May 14 02:11:04 PM PDT 24
Finished May 14 02:11:08 PM PDT 24
Peak memory 216728 kb
Host smart-acc46550-0d9a-4845-be37-4ebbbdf83310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440467123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.440467123
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1981766799
Short name T69
Test name
Test status
Simulation time 22456834 ps
CPU time 1.13 seconds
Started May 14 02:08:07 PM PDT 24
Finished May 14 02:08:09 PM PDT 24
Peak memory 215312 kb
Host smart-d9040cc2-69c0-4410-9934-f3ef346835c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981766799 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1981766799
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1354793764
Short name T212
Test name
Test status
Simulation time 64365560 ps
CPU time 1.52 seconds
Started May 14 01:57:28 PM PDT 24
Finished May 14 01:57:30 PM PDT 24
Peak memory 206128 kb
Host smart-029051b7-be2b-4ef5-8fc2-44d2e4501339
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354793764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1354793764
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/default/96.edn_err.2402508155
Short name T85
Test name
Test status
Simulation time 25668878 ps
CPU time 1.08 seconds
Started May 14 02:10:10 PM PDT 24
Finished May 14 02:10:14 PM PDT 24
Peak memory 223488 kb
Host smart-15925953-ccd6-4e33-9b24-54c47bfbb3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402508155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2402508155
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1630537068
Short name T246
Test name
Test status
Simulation time 177639105 ps
CPU time 1.64 seconds
Started May 14 01:58:03 PM PDT 24
Finished May 14 01:58:06 PM PDT 24
Peak memory 206168 kb
Host smart-3d26ec03-8065-45e7-88c1-e846ab42cf3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630537068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1630537068
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3836704780
Short name T722
Test name
Test status
Simulation time 53631957 ps
CPU time 1.17 seconds
Started May 14 02:07:49 PM PDT 24
Finished May 14 02:07:51 PM PDT 24
Peak memory 216572 kb
Host smart-14af5eb3-664d-402b-a967-f7a49fc7e981
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836704780 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3836704780
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_disable.1882560783
Short name T162
Test name
Test status
Simulation time 21122949 ps
CPU time 0.86 seconds
Started May 14 02:08:39 PM PDT 24
Finished May 14 02:08:43 PM PDT 24
Peak memory 216024 kb
Host smart-a4489068-8cd8-4598-be0e-8e2dae128622
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882560783 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1882560783
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable.4203637380
Short name T80
Test name
Test status
Simulation time 17832979 ps
CPU time 0.86 seconds
Started May 14 02:08:37 PM PDT 24
Finished May 14 02:08:41 PM PDT 24
Peak memory 216036 kb
Host smart-ea8415ec-0629-473b-bb5d-45e31f888856
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203637380 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.4203637380
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable.1567235828
Short name T91
Test name
Test status
Simulation time 34506876 ps
CPU time 0.88 seconds
Started May 14 02:09:22 PM PDT 24
Finished May 14 02:09:25 PM PDT 24
Peak memory 215980 kb
Host smart-e4f07535-e34d-4394-b2b1-b65efb1610d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567235828 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1567235828
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/86.edn_err.2299610578
Short name T97
Test name
Test status
Simulation time 34732249 ps
CPU time 0.87 seconds
Started May 14 02:10:10 PM PDT 24
Finished May 14 02:10:13 PM PDT 24
Peak memory 218852 kb
Host smart-d212c919-9b57-49c2-bcf1-1f2ca268ec91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299610578 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2299610578
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.935961687
Short name T116
Test name
Test status
Simulation time 67399402231 ps
CPU time 1700.53 seconds
Started May 14 02:09:06 PM PDT 24
Finished May 14 02:37:30 PM PDT 24
Peak memory 225332 kb
Host smart-81879719-1dba-4393-ac2b-9fbcf3251052
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935961687 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.935961687
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.121619413
Short name T260
Test name
Test status
Simulation time 26043062 ps
CPU time 1.23 seconds
Started May 14 02:08:10 PM PDT 24
Finished May 14 02:08:14 PM PDT 24
Peak memory 215360 kb
Host smart-d9c78b01-8d80-45e4-9360-73dbb2d6a4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121619413 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.121619413
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/13.edn_intr.94472440
Short name T109
Test name
Test status
Simulation time 31844694 ps
CPU time 0.88 seconds
Started May 14 02:08:22 PM PDT 24
Finished May 14 02:08:25 PM PDT 24
Peak memory 215180 kb
Host smart-224b6024-887a-48ec-b677-ab6479cdc0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94472440 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.94472440
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.977438290
Short name T29
Test name
Test status
Simulation time 52771558 ps
CPU time 1.17 seconds
Started May 14 02:08:40 PM PDT 24
Finished May 14 02:08:43 PM PDT 24
Peak memory 216552 kb
Host smart-83e65be8-afc0-47d2-a346-9284e93a2703
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977438290 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.977438290
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_alert.401565298
Short name T265
Test name
Test status
Simulation time 37698302 ps
CPU time 1.41 seconds
Started May 14 02:07:47 PM PDT 24
Finished May 14 02:07:50 PM PDT 24
Peak memory 215356 kb
Host smart-8d82f1fd-b15e-42d7-9c45-bf9a7360272d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401565298 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.401565298
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/208.edn_genbits.397508936
Short name T139
Test name
Test status
Simulation time 25763507 ps
CPU time 1.33 seconds
Started May 14 02:10:45 PM PDT 24
Finished May 14 02:10:48 PM PDT 24
Peak memory 218040 kb
Host smart-1dff3ecb-52b8-43bd-ac05-25034c9f7031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397508936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.397508936
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_genbits.3735657081
Short name T273
Test name
Test status
Simulation time 64211273 ps
CPU time 1.72 seconds
Started May 14 02:09:52 PM PDT 24
Finished May 14 02:09:56 PM PDT 24
Peak memory 218488 kb
Host smart-e372af47-5e9f-4f19-9221-b51c1e6fcdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735657081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3735657081
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_disable.4068635090
Short name T60
Test name
Test status
Simulation time 11160877 ps
CPU time 0.87 seconds
Started May 14 02:07:47 PM PDT 24
Finished May 14 02:07:49 PM PDT 24
Peak memory 215112 kb
Host smart-e01702c1-cbeb-4e08-ad01-980da6008df0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068635090 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.4068635090
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2704784320
Short name T22
Test name
Test status
Simulation time 29033071 ps
CPU time 1.09 seconds
Started May 14 02:09:31 PM PDT 24
Finished May 14 02:09:35 PM PDT 24
Peak memory 216728 kb
Host smart-bbd2434c-6b5d-463c-8bfe-d082f60b7052
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704784320 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2704784320
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_intr.1438569235
Short name T615
Test name
Test status
Simulation time 22604568 ps
CPU time 1.11 seconds
Started May 14 02:07:39 PM PDT 24
Finished May 14 02:07:42 PM PDT 24
Peak memory 215300 kb
Host smart-1e519b57-1aa0-4623-8b4f-506778618904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438569235 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1438569235
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2875461956
Short name T55
Test name
Test status
Simulation time 109355637 ps
CPU time 1.32 seconds
Started May 14 02:07:39 PM PDT 24
Finished May 14 02:07:42 PM PDT 24
Peak memory 216668 kb
Host smart-77ec9c72-85d7-47c6-9d18-cea6d5e60e61
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875461956 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2875461956
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_disable.531089095
Short name T82
Test name
Test status
Simulation time 10505797 ps
CPU time 0.86 seconds
Started May 14 02:08:22 PM PDT 24
Finished May 14 02:08:26 PM PDT 24
Peak memory 216116 kb
Host smart-55bea3ad-2114-4a44-afdd-f3f1c46540f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531089095 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.531089095
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3402657716
Short name T431
Test name
Test status
Simulation time 35252905 ps
CPU time 1.24 seconds
Started May 14 02:08:20 PM PDT 24
Finished May 14 02:08:22 PM PDT 24
Peak memory 219384 kb
Host smart-f6fd9688-0b88-45fe-bff2-358027942c5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402657716 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3402657716
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3678747000
Short name T93
Test name
Test status
Simulation time 22919661 ps
CPU time 1.02 seconds
Started May 14 02:09:10 PM PDT 24
Finished May 14 02:09:13 PM PDT 24
Peak memory 217920 kb
Host smart-b947e907-2959-4121-a5c0-902033c22ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678747000 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3678747000
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/40.edn_disable.1847911439
Short name T90
Test name
Test status
Simulation time 23365857 ps
CPU time 0.94 seconds
Started May 14 02:09:26 PM PDT 24
Finished May 14 02:09:30 PM PDT 24
Peak memory 216020 kb
Host smart-5b32ba44-4155-4fca-903f-9d0d8ceabd0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847911439 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1847911439
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1697010573
Short name T35
Test name
Test status
Simulation time 62545703 ps
CPU time 1.08 seconds
Started May 14 02:09:40 PM PDT 24
Finished May 14 02:09:44 PM PDT 24
Peak memory 216548 kb
Host smart-8e59e231-823a-4586-9a4d-a96f78c957df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697010573 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1697010573
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_alert_test.3754142880
Short name T335
Test name
Test status
Simulation time 11146533 ps
CPU time 0.86 seconds
Started May 14 02:07:50 PM PDT 24
Finished May 14 02:07:52 PM PDT 24
Peak memory 206528 kb
Host smart-be7aad27-536f-4b5b-b817-43992ced737f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754142880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3754142880
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/261.edn_genbits.1959236858
Short name T267
Test name
Test status
Simulation time 110721001 ps
CPU time 2.54 seconds
Started May 14 02:10:50 PM PDT 24
Finished May 14 02:10:56 PM PDT 24
Peak memory 216740 kb
Host smart-e53105c0-4230-4c85-a1e6-0d723e5cfe99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959236858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1959236858
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.4141316806
Short name T203
Test name
Test status
Simulation time 197861397 ps
CPU time 3.58 seconds
Started May 14 02:10:59 PM PDT 24
Finished May 14 02:11:05 PM PDT 24
Peak memory 218312 kb
Host smart-fb3e7ea5-794e-4ecd-8beb-747c6a977006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141316806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.4141316806
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_alert.3591428137
Short name T158
Test name
Test status
Simulation time 28040564 ps
CPU time 1.27 seconds
Started May 14 02:09:02 PM PDT 24
Finished May 14 02:09:07 PM PDT 24
Peak memory 215320 kb
Host smart-ee452b08-ad8a-4a3f-92f7-d9e995a4b3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591428137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3591428137
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3479045193
Short name T248
Test name
Test status
Simulation time 92909181 ps
CPU time 2.61 seconds
Started May 14 01:57:25 PM PDT 24
Finished May 14 01:57:29 PM PDT 24
Peak memory 206340 kb
Host smart-881e0330-8be6-43bb-a2e4-903874d419bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479045193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3479045193
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_regwen.3432471350
Short name T711
Test name
Test status
Simulation time 49877292 ps
CPU time 0.98 seconds
Started May 14 02:07:47 PM PDT 24
Finished May 14 02:07:49 PM PDT 24
Peak memory 206728 kb
Host smart-909a5d1a-4ecd-4eca-b79a-871364bba9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432471350 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3432471350
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/122.edn_genbits.3155680312
Short name T696
Test name
Test status
Simulation time 88267005 ps
CPU time 1.09 seconds
Started May 14 02:10:21 PM PDT 24
Finished May 14 02:10:25 PM PDT 24
Peak memory 218684 kb
Host smart-f3a3673e-045b-4b98-b2fc-27523c8cb04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155680312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3155680312
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_regwen.424070872
Short name T258
Test name
Test status
Simulation time 20060008 ps
CPU time 1.07 seconds
Started May 14 02:07:54 PM PDT 24
Finished May 14 02:07:57 PM PDT 24
Peak memory 206768 kb
Host smart-62f0d6a8-0097-49bc-8816-ca1a6d9feebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424070872 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.424070872
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/61.edn_genbits.3312897906
Short name T274
Test name
Test status
Simulation time 70745055 ps
CPU time 1.05 seconds
Started May 14 02:09:49 PM PDT 24
Finished May 14 02:09:51 PM PDT 24
Peak memory 216764 kb
Host smart-c8c30182-3599-4557-a8f5-fb384e983aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312897906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3312897906
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1655217365
Short name T144
Test name
Test status
Simulation time 22374073 ps
CPU time 1.09 seconds
Started May 14 02:08:35 PM PDT 24
Finished May 14 02:08:39 PM PDT 24
Peak memory 215304 kb
Host smart-74f8b53a-17d7-476b-a038-bd18c0763603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655217365 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1655217365
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/6.edn_intr.4115512428
Short name T103
Test name
Test status
Simulation time 30254236 ps
CPU time 1.05 seconds
Started May 14 02:08:01 PM PDT 24
Finished May 14 02:08:03 PM PDT 24
Peak memory 215296 kb
Host smart-ad2b1db0-b15e-4013-9795-b47d35ffa413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115512428 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.4115512428
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/173.edn_genbits.2061611670
Short name T300
Test name
Test status
Simulation time 112151519 ps
CPU time 1.46 seconds
Started May 14 02:10:31 PM PDT 24
Finished May 14 02:10:33 PM PDT 24
Peak memory 216872 kb
Host smart-5ec538ce-fd42-4ac0-a586-1d56950fbe62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061611670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2061611670
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.627972886
Short name T230
Test name
Test status
Simulation time 36605440 ps
CPU time 1.08 seconds
Started May 14 01:57:18 PM PDT 24
Finished May 14 01:57:20 PM PDT 24
Peak memory 206172 kb
Host smart-dced2aa8-9063-469a-b163-07e7e1597376
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627972886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.627972886
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2581260139
Short name T781
Test name
Test status
Simulation time 87240744209 ps
CPU time 2137.95 seconds
Started May 14 02:07:40 PM PDT 24
Finished May 14 02:43:20 PM PDT 24
Peak memory 226368 kb
Host smart-fdd066c9-47b2-4a4c-956c-94371aa7f63d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581260139 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2581260139
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_genbits.2655698909
Short name T277
Test name
Test status
Simulation time 35832827 ps
CPU time 1.03 seconds
Started May 14 02:07:46 PM PDT 24
Finished May 14 02:07:49 PM PDT 24
Peak memory 216856 kb
Host smart-c06b8c08-7995-44a9-838b-8c8b032af842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655698909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2655698909
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2210915340
Short name T280
Test name
Test status
Simulation time 43860894564 ps
CPU time 1166.05 seconds
Started May 14 02:07:46 PM PDT 24
Finished May 14 02:27:13 PM PDT 24
Peak memory 223304 kb
Host smart-e96d1520-b556-479d-868a-7a19421746da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210915340 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2210915340
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/124.edn_genbits.2992084734
Short name T303
Test name
Test status
Simulation time 98522601 ps
CPU time 1.41 seconds
Started May 14 02:10:12 PM PDT 24
Finished May 14 02:10:17 PM PDT 24
Peak memory 219380 kb
Host smart-5c9fd45b-e805-45bb-ab11-7516464e1fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992084734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2992084734
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.3017993409
Short name T354
Test name
Test status
Simulation time 169378399 ps
CPU time 1.51 seconds
Started May 14 02:10:19 PM PDT 24
Finished May 14 02:10:24 PM PDT 24
Peak memory 218128 kb
Host smart-352e1b2a-c32e-4150-89d4-969bb25bbda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017993409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3017993409
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/130.edn_genbits.966735723
Short name T785
Test name
Test status
Simulation time 83989579 ps
CPU time 1.13 seconds
Started May 14 02:10:22 PM PDT 24
Finished May 14 02:10:25 PM PDT 24
Peak memory 216680 kb
Host smart-2c4cc17f-08a5-444f-a301-95758efd7fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966735723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.966735723
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.4176005828
Short name T287
Test name
Test status
Simulation time 57717996 ps
CPU time 1.19 seconds
Started May 14 02:10:22 PM PDT 24
Finished May 14 02:10:26 PM PDT 24
Peak memory 218156 kb
Host smart-a75256a6-1f50-4d3e-b47a-72262e6471ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176005828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.4176005828
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.864144988
Short name T844
Test name
Test status
Simulation time 42353567 ps
CPU time 1.09 seconds
Started May 14 02:10:40 PM PDT 24
Finished May 14 02:10:43 PM PDT 24
Peak memory 216680 kb
Host smart-ac14885f-21a0-49a5-869c-92b61bf6a375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864144988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.864144988
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.4015379008
Short name T283
Test name
Test status
Simulation time 68771828 ps
CPU time 1.73 seconds
Started May 14 02:10:40 PM PDT 24
Finished May 14 02:10:43 PM PDT 24
Peak memory 218060 kb
Host smart-d964dc83-d371-4432-886d-d326c0172cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015379008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.4015379008
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3604647114
Short name T263
Test name
Test status
Simulation time 236877877 ps
CPU time 1.47 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:41 PM PDT 24
Peak memory 215404 kb
Host smart-f5f9a8e5-f83a-49e8-9fec-5d9fc84e9986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604647114 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3604647114
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/218.edn_genbits.2035994931
Short name T292
Test name
Test status
Simulation time 38851549 ps
CPU time 1.51 seconds
Started May 14 02:10:47 PM PDT 24
Finished May 14 02:10:52 PM PDT 24
Peak memory 219400 kb
Host smart-833b285e-4c46-40ec-843f-0936d08b4265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035994931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2035994931
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_alert.2526417988
Short name T256
Test name
Test status
Simulation time 30494382 ps
CPU time 1.27 seconds
Started May 14 02:09:37 PM PDT 24
Finished May 14 02:09:40 PM PDT 24
Peak memory 215400 kb
Host smart-8d6843c3-2600-4fd4-9f26-1b0fd8f2b116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526417988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2526417988
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/14.edn_intr.1247209251
Short name T114
Test name
Test status
Simulation time 25601434 ps
CPU time 0.94 seconds
Started May 14 02:08:34 PM PDT 24
Finished May 14 02:08:37 PM PDT 24
Peak memory 215220 kb
Host smart-3d81ca9c-0b9c-485c-ac94-6f469c53bda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247209251 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1247209251
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/10.edn_disable.943727990
Short name T167
Test name
Test status
Simulation time 21860506 ps
CPU time 0.89 seconds
Started May 14 02:08:13 PM PDT 24
Finished May 14 02:08:15 PM PDT 24
Peak memory 216008 kb
Host smart-cb3aca41-ff3d-4dca-bbba-34c98fe9abd9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943727990 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.943727990
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/20.edn_alert.2187704294
Short name T715
Test name
Test status
Simulation time 40578447 ps
CPU time 1.2 seconds
Started May 14 02:08:37 PM PDT 24
Finished May 14 02:08:42 PM PDT 24
Peak memory 215340 kb
Host smart-ab37c0b0-7f11-415b-8d87-1dc587b4ed3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187704294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2187704294
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.1602082248
Short name T732
Test name
Test status
Simulation time 50198038 ps
CPU time 1.59 seconds
Started May 14 02:10:17 PM PDT 24
Finished May 14 02:10:21 PM PDT 24
Peak memory 219456 kb
Host smart-8b601784-7262-4645-82ca-25b466f79f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602082248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1602082248
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2801045911
Short name T946
Test name
Test status
Simulation time 67307707 ps
CPU time 1.22 seconds
Started May 14 01:57:16 PM PDT 24
Finished May 14 01:57:18 PM PDT 24
Peak memory 206152 kb
Host smart-66c88276-8afa-4ad4-8750-6a58e7df6939
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801045911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2801045911
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3739407512
Short name T897
Test name
Test status
Simulation time 134323288 ps
CPU time 3.79 seconds
Started May 14 01:57:17 PM PDT 24
Finished May 14 01:57:22 PM PDT 24
Peak memory 206252 kb
Host smart-f625603d-e02e-4da6-bcc2-d4cdd26c9a74
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739407512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3739407512
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3605902617
Short name T891
Test name
Test status
Simulation time 16368321 ps
CPU time 0.9 seconds
Started May 14 01:57:17 PM PDT 24
Finished May 14 01:57:18 PM PDT 24
Peak memory 206176 kb
Host smart-ae99d0f7-c69a-4b19-bf30-49023a3ca9df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605902617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3605902617
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.120455944
Short name T896
Test name
Test status
Simulation time 24060057 ps
CPU time 1.62 seconds
Started May 14 01:57:18 PM PDT 24
Finished May 14 01:57:20 PM PDT 24
Peak memory 214440 kb
Host smart-2b957148-39df-4192-a7e0-0cf05ebf0fbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120455944 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.120455944
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1011745707
Short name T223
Test name
Test status
Simulation time 27940965 ps
CPU time 0.93 seconds
Started May 14 01:57:18 PM PDT 24
Finished May 14 01:57:20 PM PDT 24
Peak memory 206128 kb
Host smart-88236acb-1044-4078-9c31-af13840e8603
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011745707 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1011745707
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2028704963
Short name T923
Test name
Test status
Simulation time 37978228 ps
CPU time 0.84 seconds
Started May 14 01:57:09 PM PDT 24
Finished May 14 01:57:11 PM PDT 24
Peak memory 205912 kb
Host smart-2667098a-3634-41b5-95a9-7b9df6302317
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028704963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2028704963
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3462035761
Short name T868
Test name
Test status
Simulation time 41722348 ps
CPU time 1.62 seconds
Started May 14 01:57:09 PM PDT 24
Finished May 14 01:57:11 PM PDT 24
Peak memory 214508 kb
Host smart-bb56ba74-0836-4f3d-89ef-900d42ee8de5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462035761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3462035761
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.793735541
Short name T238
Test name
Test status
Simulation time 382341881 ps
CPU time 1.54 seconds
Started May 14 01:57:10 PM PDT 24
Finished May 14 01:57:12 PM PDT 24
Peak memory 206144 kb
Host smart-1104dfaf-b28d-4512-b68e-bce9837d21c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793735541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.793735541
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.934801346
Short name T876
Test name
Test status
Simulation time 368255841 ps
CPU time 3.19 seconds
Started May 14 01:57:26 PM PDT 24
Finished May 14 01:57:30 PM PDT 24
Peak memory 206144 kb
Host smart-3e8138c8-f5ba-4db6-a063-f50e124ccef1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934801346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.934801346
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.442825769
Short name T893
Test name
Test status
Simulation time 33921663 ps
CPU time 0.99 seconds
Started May 14 01:57:25 PM PDT 24
Finished May 14 01:57:27 PM PDT 24
Peak memory 206204 kb
Host smart-3e6bb9f2-3c77-4cb8-94e5-def2658d8ab5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442825769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.442825769
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1860328631
Short name T972
Test name
Test status
Simulation time 77752937 ps
CPU time 1.61 seconds
Started May 14 01:57:26 PM PDT 24
Finished May 14 01:57:28 PM PDT 24
Peak memory 214388 kb
Host smart-681c5bb6-23f7-401b-9446-faf6068fa6cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860328631 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1860328631
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1292857006
Short name T219
Test name
Test status
Simulation time 14624734 ps
CPU time 0.94 seconds
Started May 14 01:57:25 PM PDT 24
Finished May 14 01:57:27 PM PDT 24
Peak memory 206156 kb
Host smart-92d84b20-f96f-4827-a1f3-f0382c3c8de9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292857006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1292857006
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2360721739
Short name T857
Test name
Test status
Simulation time 11886258 ps
CPU time 0.87 seconds
Started May 14 01:57:25 PM PDT 24
Finished May 14 01:57:27 PM PDT 24
Peak memory 206004 kb
Host smart-75b42505-c3d4-484c-a8a8-f0ee0b6537cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360721739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2360721739
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3644072867
Short name T917
Test name
Test status
Simulation time 377827789 ps
CPU time 1.52 seconds
Started May 14 01:57:25 PM PDT 24
Finished May 14 01:57:28 PM PDT 24
Peak memory 206184 kb
Host smart-d830dc52-35f7-47dc-8a5a-bb1c319f0fce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644072867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3644072867
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3979051415
Short name T932
Test name
Test status
Simulation time 26134868 ps
CPU time 1.87 seconds
Started May 14 01:57:24 PM PDT 24
Finished May 14 01:57:26 PM PDT 24
Peak memory 214320 kb
Host smart-8b93a786-656e-4ac2-abfc-17c70b1f3bd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979051415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3979051415
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2453246379
Short name T902
Test name
Test status
Simulation time 60283866 ps
CPU time 1.23 seconds
Started May 14 01:58:09 PM PDT 24
Finished May 14 01:58:11 PM PDT 24
Peak memory 214556 kb
Host smart-fb4e353e-b2c3-4e34-bd0d-6a85c51dbbf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453246379 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2453246379
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1448447187
Short name T232
Test name
Test status
Simulation time 17935174 ps
CPU time 0.95 seconds
Started May 14 01:58:01 PM PDT 24
Finished May 14 01:58:03 PM PDT 24
Peak memory 206180 kb
Host smart-0e6a2da0-e728-48b8-bdbf-e0c8937c5a60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448447187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1448447187
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.484879986
Short name T925
Test name
Test status
Simulation time 23367011 ps
CPU time 0.84 seconds
Started May 14 01:58:04 PM PDT 24
Finished May 14 01:58:06 PM PDT 24
Peak memory 206008 kb
Host smart-d76fd914-7712-4ad8-9890-5fc2e81b65a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484879986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.484879986
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2599264726
Short name T214
Test name
Test status
Simulation time 30841856 ps
CPU time 1.11 seconds
Started May 14 01:58:05 PM PDT 24
Finished May 14 01:58:07 PM PDT 24
Peak memory 206228 kb
Host smart-12d0030a-4806-4d28-bb5e-b19115a35b7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599264726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2599264726
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.4199652822
Short name T864
Test name
Test status
Simulation time 177891710 ps
CPU time 5.6 seconds
Started May 14 01:58:03 PM PDT 24
Finished May 14 01:58:09 PM PDT 24
Peak memory 214444 kb
Host smart-b7aa6ba6-5b4f-4f5b-ac87-3355d8acbb59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199652822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.4199652822
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3074391911
Short name T869
Test name
Test status
Simulation time 33114717 ps
CPU time 1.48 seconds
Started May 14 01:58:13 PM PDT 24
Finished May 14 01:58:16 PM PDT 24
Peak memory 214484 kb
Host smart-1e331708-446f-4bf9-a691-94997deb9775
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074391911 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3074391911
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2317049757
Short name T224
Test name
Test status
Simulation time 45333680 ps
CPU time 0.89 seconds
Started May 14 01:58:09 PM PDT 24
Finished May 14 01:58:11 PM PDT 24
Peak memory 206084 kb
Host smart-fb22cb29-d0ad-478b-bf67-7f9b7f61dc59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317049757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2317049757
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2167394626
Short name T880
Test name
Test status
Simulation time 29236351 ps
CPU time 0.81 seconds
Started May 14 01:58:11 PM PDT 24
Finished May 14 01:58:13 PM PDT 24
Peak memory 205888 kb
Host smart-82e5c0a9-fef3-484e-ad42-536cb847d3b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167394626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2167394626
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3816108561
Short name T975
Test name
Test status
Simulation time 103782863 ps
CPU time 1.38 seconds
Started May 14 01:58:10 PM PDT 24
Finished May 14 01:58:12 PM PDT 24
Peak memory 206212 kb
Host smart-6d021757-fc3a-4c72-adc6-3b6ce3c7fa63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816108561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3816108561
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2798912411
Short name T910
Test name
Test status
Simulation time 51623723 ps
CPU time 2.22 seconds
Started May 14 01:58:11 PM PDT 24
Finished May 14 01:58:14 PM PDT 24
Peak memory 214480 kb
Host smart-b774c8a8-a2b0-47fd-aa51-acf5dc9f38aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798912411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2798912411
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3090499277
Short name T245
Test name
Test status
Simulation time 296159172 ps
CPU time 2.38 seconds
Started May 14 01:58:11 PM PDT 24
Finished May 14 01:58:14 PM PDT 24
Peak memory 214352 kb
Host smart-64712d4f-cc53-4b74-a05a-10ddfca5382a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090499277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3090499277
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1051154744
Short name T920
Test name
Test status
Simulation time 19563470 ps
CPU time 1.48 seconds
Started May 14 01:58:09 PM PDT 24
Finished May 14 01:58:11 PM PDT 24
Peak memory 214392 kb
Host smart-011e9993-829e-4027-bb54-2a0017e61803
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051154744 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1051154744
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3693211862
Short name T941
Test name
Test status
Simulation time 33266382 ps
CPU time 0.9 seconds
Started May 14 01:58:09 PM PDT 24
Finished May 14 01:58:11 PM PDT 24
Peak memory 206204 kb
Host smart-dd5fe788-42e0-4368-879d-c1d0f9341d91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693211862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3693211862
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.137065448
Short name T961
Test name
Test status
Simulation time 12050597 ps
CPU time 0.88 seconds
Started May 14 01:58:10 PM PDT 24
Finished May 14 01:58:12 PM PDT 24
Peak memory 206032 kb
Host smart-8ed10979-9aa4-4995-8041-662bbf85ab5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137065448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.137065448
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.794912869
Short name T968
Test name
Test status
Simulation time 21080214 ps
CPU time 0.91 seconds
Started May 14 01:58:10 PM PDT 24
Finished May 14 01:58:12 PM PDT 24
Peak memory 206148 kb
Host smart-f579e205-64d9-4550-9104-06bafc99bac4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794912869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.794912869
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.121155188
Short name T959
Test name
Test status
Simulation time 55670963 ps
CPU time 2.06 seconds
Started May 14 01:58:11 PM PDT 24
Finished May 14 01:58:14 PM PDT 24
Peak memory 214392 kb
Host smart-89f820a1-4cc8-4434-83d5-8a0597ce3b1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121155188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.121155188
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3063682803
Short name T957
Test name
Test status
Simulation time 396102023 ps
CPU time 2.32 seconds
Started May 14 01:58:13 PM PDT 24
Finished May 14 01:58:17 PM PDT 24
Peak memory 214388 kb
Host smart-24a8aea2-f573-4448-b493-2a3085d0cffc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063682803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3063682803
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.4156388114
Short name T955
Test name
Test status
Simulation time 69011371 ps
CPU time 1.29 seconds
Started May 14 01:58:19 PM PDT 24
Finished May 14 01:58:21 PM PDT 24
Peak memory 214488 kb
Host smart-08d29046-4b84-47cc-a075-82d958e9aa63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156388114 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.4156388114
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1963955200
Short name T916
Test name
Test status
Simulation time 23117565 ps
CPU time 0.89 seconds
Started May 14 01:58:11 PM PDT 24
Finished May 14 01:58:13 PM PDT 24
Peak memory 206168 kb
Host smart-950c8752-0ae6-4b04-9519-7127fdcf7b08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963955200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1963955200
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2784267443
Short name T866
Test name
Test status
Simulation time 31068097 ps
CPU time 0.79 seconds
Started May 14 01:58:10 PM PDT 24
Finished May 14 01:58:12 PM PDT 24
Peak memory 205912 kb
Host smart-07171003-4b06-4005-bd6e-5266fffba150
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784267443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2784267443
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2159710041
Short name T943
Test name
Test status
Simulation time 357335311 ps
CPU time 1.09 seconds
Started May 14 01:58:12 PM PDT 24
Finished May 14 01:58:14 PM PDT 24
Peak memory 206156 kb
Host smart-0953d881-3a52-4db4-b0cc-e5c51b3a933e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159710041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2159710041
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1587629849
Short name T875
Test name
Test status
Simulation time 39932114 ps
CPU time 2.75 seconds
Started May 14 01:58:10 PM PDT 24
Finished May 14 01:58:14 PM PDT 24
Peak memory 214368 kb
Host smart-0802fec7-426c-4189-bddc-188ca5d6c48f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587629849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1587629849
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1464871403
Short name T915
Test name
Test status
Simulation time 80705341 ps
CPU time 1.53 seconds
Started May 14 01:58:13 PM PDT 24
Finished May 14 01:58:15 PM PDT 24
Peak memory 206188 kb
Host smart-19dd4964-45e6-49be-99ba-219b0d13f427
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464871403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1464871403
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2525159359
Short name T870
Test name
Test status
Simulation time 74636576 ps
CPU time 1.1 seconds
Started May 14 01:58:21 PM PDT 24
Finished May 14 01:58:23 PM PDT 24
Peak memory 214480 kb
Host smart-6e56ae66-37ff-4bb7-a62c-4a51685a8005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525159359 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2525159359
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1948871096
Short name T227
Test name
Test status
Simulation time 16849957 ps
CPU time 0.98 seconds
Started May 14 01:58:19 PM PDT 24
Finished May 14 01:58:20 PM PDT 24
Peak memory 206184 kb
Host smart-8c01784e-1c1e-429f-8618-631b236e37c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948871096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1948871096
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1386102810
Short name T865
Test name
Test status
Simulation time 16695153 ps
CPU time 0.88 seconds
Started May 14 01:58:18 PM PDT 24
Finished May 14 01:58:20 PM PDT 24
Peak memory 206016 kb
Host smart-d878c7e6-ebb3-44e1-b90c-dbc94af6cddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386102810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1386102810
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2532147507
Short name T220
Test name
Test status
Simulation time 57263792 ps
CPU time 1.12 seconds
Started May 14 01:58:21 PM PDT 24
Finished May 14 01:58:23 PM PDT 24
Peak memory 206132 kb
Host smart-19a9d6ae-7f9c-46ce-b4a7-5ccc49b9377a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532147507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2532147507
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.4084866871
Short name T926
Test name
Test status
Simulation time 82539802 ps
CPU time 1.89 seconds
Started May 14 01:58:21 PM PDT 24
Finished May 14 01:58:24 PM PDT 24
Peak memory 214400 kb
Host smart-386903f8-26bb-4dd6-b9b6-aa683cee29cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084866871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.4084866871
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3799189461
Short name T240
Test name
Test status
Simulation time 98498081 ps
CPU time 2.33 seconds
Started May 14 01:58:22 PM PDT 24
Finished May 14 01:58:25 PM PDT 24
Peak memory 206172 kb
Host smart-68b123f8-74d6-44fe-a81c-b5bcdd44a45c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799189461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3799189461
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2023360201
Short name T940
Test name
Test status
Simulation time 75126058 ps
CPU time 1.2 seconds
Started May 14 01:58:28 PM PDT 24
Finished May 14 01:58:30 PM PDT 24
Peak memory 214444 kb
Host smart-1493e0e6-8283-4578-8297-6019b87b398b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023360201 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2023360201
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.853492197
Short name T217
Test name
Test status
Simulation time 16355386 ps
CPU time 0.94 seconds
Started May 14 01:58:21 PM PDT 24
Finished May 14 01:58:23 PM PDT 24
Peak memory 206124 kb
Host smart-1c8c14d2-5187-4026-b445-a4ad6eac0010
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853492197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.853492197
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.4001540114
Short name T861
Test name
Test status
Simulation time 12046106 ps
CPU time 0.84 seconds
Started May 14 01:58:19 PM PDT 24
Finished May 14 01:58:20 PM PDT 24
Peak memory 206036 kb
Host smart-2bfe87d3-4f01-44d5-8328-3201c48f367f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001540114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.4001540114
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1856240258
Short name T936
Test name
Test status
Simulation time 37775945 ps
CPU time 1.48 seconds
Started May 14 01:58:20 PM PDT 24
Finished May 14 01:58:22 PM PDT 24
Peak memory 206172 kb
Host smart-55c8016d-744a-4e09-9327-d0c135c5e426
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856240258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1856240258
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.4229712015
Short name T863
Test name
Test status
Simulation time 49588673 ps
CPU time 2.22 seconds
Started May 14 01:58:18 PM PDT 24
Finished May 14 01:58:21 PM PDT 24
Peak memory 214356 kb
Host smart-30335c4d-6efe-46a6-a649-25788174d82f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229712015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.4229712015
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2872888310
Short name T967
Test name
Test status
Simulation time 96906721 ps
CPU time 1.75 seconds
Started May 14 01:58:21 PM PDT 24
Finished May 14 01:58:23 PM PDT 24
Peak memory 206172 kb
Host smart-4b2c4355-70fe-4a9a-8e0f-f7ccc432a3c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872888310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2872888310
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.99804114
Short name T905
Test name
Test status
Simulation time 24450479 ps
CPU time 1.25 seconds
Started May 14 01:58:28 PM PDT 24
Finished May 14 01:58:30 PM PDT 24
Peak memory 206252 kb
Host smart-2bf017b5-bfb8-4c97-921a-e1660d8a75c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99804114 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.99804114
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3265491105
Short name T215
Test name
Test status
Simulation time 60077700 ps
CPU time 0.9 seconds
Started May 14 01:58:28 PM PDT 24
Finished May 14 01:58:30 PM PDT 24
Peak memory 206228 kb
Host smart-41b9aa9b-a4b7-4625-8b42-1a31ff5d927e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265491105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3265491105
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3069867876
Short name T949
Test name
Test status
Simulation time 16551799 ps
CPU time 0.94 seconds
Started May 14 01:58:26 PM PDT 24
Finished May 14 01:58:28 PM PDT 24
Peak memory 206052 kb
Host smart-55c863ab-c5c8-4e2a-899a-eaed58848993
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069867876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3069867876
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2027978414
Short name T944
Test name
Test status
Simulation time 57556940 ps
CPU time 1.19 seconds
Started May 14 01:58:26 PM PDT 24
Finished May 14 01:58:28 PM PDT 24
Peak memory 206200 kb
Host smart-243a0dc3-5341-4148-807a-97b074ea3601
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027978414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2027978414
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2695801821
Short name T942
Test name
Test status
Simulation time 63428183 ps
CPU time 2.45 seconds
Started May 14 01:58:28 PM PDT 24
Finished May 14 01:58:31 PM PDT 24
Peak memory 214460 kb
Host smart-dc1543ce-65ce-49fb-b719-57a43dd8fa91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695801821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2695801821
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3171637079
Short name T244
Test name
Test status
Simulation time 174018307 ps
CPU time 1.74 seconds
Started May 14 01:58:26 PM PDT 24
Finished May 14 01:58:28 PM PDT 24
Peak memory 206512 kb
Host smart-2d1cc6e2-2b5b-4887-bdb9-6d055977db3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171637079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3171637079
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3733426727
Short name T851
Test name
Test status
Simulation time 19314612 ps
CPU time 1.37 seconds
Started May 14 01:58:27 PM PDT 24
Finished May 14 01:58:29 PM PDT 24
Peak memory 214440 kb
Host smart-0d7fd026-a9e2-4f20-8908-e8364b210ed8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733426727 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3733426727
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.821756674
Short name T952
Test name
Test status
Simulation time 41494854 ps
CPU time 0.8 seconds
Started May 14 01:58:25 PM PDT 24
Finished May 14 01:58:26 PM PDT 24
Peak memory 205952 kb
Host smart-c4778397-47d6-412a-8bcb-aafa3f3c8458
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821756674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.821756674
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.117650403
Short name T879
Test name
Test status
Simulation time 12481682 ps
CPU time 0.85 seconds
Started May 14 01:58:30 PM PDT 24
Finished May 14 01:58:31 PM PDT 24
Peak memory 206036 kb
Host smart-b52c0014-e2a5-46f5-8cdf-8c7dd5fe18ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117650403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.117650403
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1162669791
Short name T929
Test name
Test status
Simulation time 17249188 ps
CPU time 1.06 seconds
Started May 14 01:58:28 PM PDT 24
Finished May 14 01:58:30 PM PDT 24
Peak memory 206172 kb
Host smart-99d576d3-8428-4839-8501-d08344657f32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162669791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1162669791
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.405532524
Short name T856
Test name
Test status
Simulation time 48168258 ps
CPU time 2.18 seconds
Started May 14 01:58:28 PM PDT 24
Finished May 14 01:58:31 PM PDT 24
Peak memory 214600 kb
Host smart-61edcc5a-219e-498b-9081-e853b8506dbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405532524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.405532524
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.924393305
Short name T927
Test name
Test status
Simulation time 104819995 ps
CPU time 2.79 seconds
Started May 14 01:58:26 PM PDT 24
Finished May 14 01:58:29 PM PDT 24
Peak memory 206180 kb
Host smart-d836a284-89bf-4e72-8ad8-d95175afe65d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924393305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.924393305
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.968587889
Short name T888
Test name
Test status
Simulation time 216331233 ps
CPU time 0.96 seconds
Started May 14 01:58:46 PM PDT 24
Finished May 14 01:58:48 PM PDT 24
Peak memory 206208 kb
Host smart-077b46df-d7e2-455f-a59a-457b3d57f530
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968587889 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.968587889
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2618664062
Short name T980
Test name
Test status
Simulation time 12800267 ps
CPU time 0.88 seconds
Started May 14 01:58:26 PM PDT 24
Finished May 14 01:58:28 PM PDT 24
Peak memory 206184 kb
Host smart-b0aedf4d-5882-45bc-b2cb-9aef124bf3e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618664062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2618664062
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.4293156951
Short name T862
Test name
Test status
Simulation time 81476171 ps
CPU time 0.87 seconds
Started May 14 01:58:26 PM PDT 24
Finished May 14 01:58:28 PM PDT 24
Peak memory 205960 kb
Host smart-a945ed0a-9ebd-4114-903d-5a16f5520822
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293156951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.4293156951
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2722358137
Short name T218
Test name
Test status
Simulation time 31619845 ps
CPU time 0.95 seconds
Started May 14 01:58:33 PM PDT 24
Finished May 14 01:58:35 PM PDT 24
Peak memory 206216 kb
Host smart-7aec37bb-f66b-4db9-91e2-b5cabf4b6b10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722358137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2722358137
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3667243790
Short name T890
Test name
Test status
Simulation time 88078710 ps
CPU time 3.01 seconds
Started May 14 01:58:26 PM PDT 24
Finished May 14 01:58:30 PM PDT 24
Peak memory 214364 kb
Host smart-9ffada9a-e68b-447a-8514-c44028c04a77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667243790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3667243790
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1857914364
Short name T249
Test name
Test status
Simulation time 163356474 ps
CPU time 2.41 seconds
Started May 14 01:58:27 PM PDT 24
Finished May 14 01:58:31 PM PDT 24
Peak memory 206184 kb
Host smart-05b79ba9-90c0-4f28-9144-59cfb7cd35de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857914364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1857914364
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3412698829
Short name T859
Test name
Test status
Simulation time 56407323 ps
CPU time 1.33 seconds
Started May 14 01:58:36 PM PDT 24
Finished May 14 01:58:38 PM PDT 24
Peak memory 214508 kb
Host smart-6650ffa5-1f95-4ec6-a41e-5db7499e9717
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412698829 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3412698829
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1346224616
Short name T225
Test name
Test status
Simulation time 28124458 ps
CPU time 0.83 seconds
Started May 14 01:58:34 PM PDT 24
Finished May 14 01:58:35 PM PDT 24
Peak memory 206000 kb
Host smart-cb772d1b-a968-4d06-b6b2-2b1dabeb6848
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346224616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1346224616
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3784633772
Short name T934
Test name
Test status
Simulation time 17641577 ps
CPU time 0.84 seconds
Started May 14 01:58:46 PM PDT 24
Finished May 14 01:58:48 PM PDT 24
Peak memory 206012 kb
Host smart-39b30fdf-332e-4327-adf7-b93fc262861e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784633772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3784633772
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3097787164
Short name T898
Test name
Test status
Simulation time 30295471 ps
CPU time 1.13 seconds
Started May 14 01:58:33 PM PDT 24
Finished May 14 01:58:35 PM PDT 24
Peak memory 206168 kb
Host smart-cf28fd3c-ffb9-49e5-829a-e82026d58d80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097787164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3097787164
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1300443173
Short name T950
Test name
Test status
Simulation time 231643452 ps
CPU time 2.2 seconds
Started May 14 01:58:35 PM PDT 24
Finished May 14 01:58:38 PM PDT 24
Peak memory 214260 kb
Host smart-8af04878-f0f7-4c2f-a2f1-f08055ec142c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300443173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1300443173
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2388845642
Short name T913
Test name
Test status
Simulation time 341846529 ps
CPU time 2.36 seconds
Started May 14 01:58:36 PM PDT 24
Finished May 14 01:58:39 PM PDT 24
Peak memory 206276 kb
Host smart-37b4d3d1-0469-40c3-be38-5bbc9922596b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388845642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2388845642
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3543557596
Short name T887
Test name
Test status
Simulation time 79545891 ps
CPU time 1.2 seconds
Started May 14 01:57:34 PM PDT 24
Finished May 14 01:57:36 PM PDT 24
Peak memory 206180 kb
Host smart-07dcf77e-3d9d-46bb-85a5-bbef4477d300
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543557596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3543557596
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2049797670
Short name T234
Test name
Test status
Simulation time 368869203 ps
CPU time 3.05 seconds
Started May 14 01:57:33 PM PDT 24
Finished May 14 01:57:37 PM PDT 24
Peak memory 206160 kb
Host smart-194aa94f-dcb7-40a8-bb71-cdaceec3530c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049797670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2049797670
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1973448784
Short name T867
Test name
Test status
Simulation time 15928736 ps
CPU time 0.95 seconds
Started May 14 01:57:34 PM PDT 24
Finished May 14 01:57:36 PM PDT 24
Peak memory 206164 kb
Host smart-af7c742e-1327-4fbe-88a2-db7cf526bc8a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973448784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1973448784
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4113082068
Short name T894
Test name
Test status
Simulation time 91179163 ps
CPU time 1.42 seconds
Started May 14 01:57:33 PM PDT 24
Finished May 14 01:57:36 PM PDT 24
Peak memory 214364 kb
Host smart-8377a864-f432-4016-a7ef-6d74a19a5cfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113082068 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.4113082068
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.416651965
Short name T918
Test name
Test status
Simulation time 17141296 ps
CPU time 0.83 seconds
Started May 14 01:57:31 PM PDT 24
Finished May 14 01:57:33 PM PDT 24
Peak memory 206048 kb
Host smart-93426dd2-56d2-4c20-94ae-9623cbdaff21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416651965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.416651965
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1833075482
Short name T901
Test name
Test status
Simulation time 97501561 ps
CPU time 0.84 seconds
Started May 14 01:57:31 PM PDT 24
Finished May 14 01:57:32 PM PDT 24
Peak memory 206060 kb
Host smart-b0a72aab-1537-47f1-8c2d-9edfec75e316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833075482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1833075482
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1615209982
Short name T904
Test name
Test status
Simulation time 17997462 ps
CPU time 0.97 seconds
Started May 14 01:57:30 PM PDT 24
Finished May 14 01:57:32 PM PDT 24
Peak memory 206208 kb
Host smart-3cf7d69a-aa2f-4e08-b54b-a359f91ce1d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615209982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1615209982
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1085431672
Short name T858
Test name
Test status
Simulation time 23950838 ps
CPU time 1.73 seconds
Started May 14 01:57:26 PM PDT 24
Finished May 14 01:57:28 PM PDT 24
Peak memory 214384 kb
Host smart-b2c95eca-e680-46fd-84b0-fae478c67b87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085431672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1085431672
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4257614849
Short name T884
Test name
Test status
Simulation time 131522396 ps
CPU time 2.3 seconds
Started May 14 01:57:25 PM PDT 24
Finished May 14 01:57:28 PM PDT 24
Peak memory 206176 kb
Host smart-c3c897a1-aa0c-4ca0-9ac1-8a35e4bfaa85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257614849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.4257614849
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2761536931
Short name T895
Test name
Test status
Simulation time 66284966 ps
CPU time 0.82 seconds
Started May 14 01:58:35 PM PDT 24
Finished May 14 01:58:36 PM PDT 24
Peak memory 205892 kb
Host smart-c39aba66-130d-4a47-b411-dc8f653d8f06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761536931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2761536931
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2452154406
Short name T907
Test name
Test status
Simulation time 13672373 ps
CPU time 0.88 seconds
Started May 14 01:58:33 PM PDT 24
Finished May 14 01:58:35 PM PDT 24
Peak memory 206032 kb
Host smart-5911c362-691c-43f0-a745-0d35c33bbd61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452154406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2452154406
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3219729034
Short name T919
Test name
Test status
Simulation time 39718629 ps
CPU time 0.79 seconds
Started May 14 01:58:33 PM PDT 24
Finished May 14 01:58:35 PM PDT 24
Peak memory 205960 kb
Host smart-c0f05063-33fd-4ecd-8793-c1224fcb380a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219729034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3219729034
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2359987585
Short name T892
Test name
Test status
Simulation time 16800537 ps
CPU time 0.94 seconds
Started May 14 01:58:35 PM PDT 24
Finished May 14 01:58:37 PM PDT 24
Peak memory 206064 kb
Host smart-220d2427-a6b6-4046-83b1-3e45f3c62fbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359987585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2359987585
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2917974402
Short name T878
Test name
Test status
Simulation time 26230771 ps
CPU time 0.9 seconds
Started May 14 01:58:35 PM PDT 24
Finished May 14 01:58:36 PM PDT 24
Peak memory 206076 kb
Host smart-575ba7a5-b747-44e9-9526-9faa25b6c568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917974402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2917974402
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2860827929
Short name T889
Test name
Test status
Simulation time 74866010 ps
CPU time 0.82 seconds
Started May 14 01:58:33 PM PDT 24
Finished May 14 01:58:35 PM PDT 24
Peak memory 205992 kb
Host smart-03c54d27-694e-4413-925e-2a1a93061f18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860827929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2860827929
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3781487304
Short name T951
Test name
Test status
Simulation time 39685741 ps
CPU time 0.91 seconds
Started May 14 01:58:46 PM PDT 24
Finished May 14 01:58:49 PM PDT 24
Peak memory 205916 kb
Host smart-0aac8f1e-9934-4552-a1d7-7cb5355ef93e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781487304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3781487304
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2019137567
Short name T956
Test name
Test status
Simulation time 65609143 ps
CPU time 0.81 seconds
Started May 14 01:58:34 PM PDT 24
Finished May 14 01:58:36 PM PDT 24
Peak memory 205960 kb
Host smart-00492159-0a34-4583-a415-aa77bb0dad2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019137567 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2019137567
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3994612619
Short name T970
Test name
Test status
Simulation time 15919143 ps
CPU time 0.91 seconds
Started May 14 01:58:47 PM PDT 24
Finished May 14 01:58:49 PM PDT 24
Peak memory 206008 kb
Host smart-29701081-6dbc-4315-95bc-8338930ae738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994612619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3994612619
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3933182158
Short name T885
Test name
Test status
Simulation time 24596822 ps
CPU time 0.81 seconds
Started May 14 01:58:46 PM PDT 24
Finished May 14 01:58:48 PM PDT 24
Peak memory 206008 kb
Host smart-ab0e0391-cf6f-4cba-a125-813396b12f00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933182158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3933182158
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.705901423
Short name T226
Test name
Test status
Simulation time 23634479 ps
CPU time 1.05 seconds
Started May 14 01:57:36 PM PDT 24
Finished May 14 01:57:38 PM PDT 24
Peak memory 206236 kb
Host smart-ddaae009-c2f2-401f-aec1-af0fb564a212
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705901423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.705901423
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3119227638
Short name T877
Test name
Test status
Simulation time 233508036 ps
CPU time 3.62 seconds
Started May 14 01:57:34 PM PDT 24
Finished May 14 01:57:39 PM PDT 24
Peak memory 206140 kb
Host smart-09d6d372-391f-4968-920e-0b73ea3cec81
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119227638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3119227638
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3820550664
Short name T236
Test name
Test status
Simulation time 21744645 ps
CPU time 0.87 seconds
Started May 14 01:57:33 PM PDT 24
Finished May 14 01:57:35 PM PDT 24
Peak memory 206100 kb
Host smart-817e3b90-3404-47dc-8bf5-51cca2e7cfac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820550664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3820550664
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.247457428
Short name T908
Test name
Test status
Simulation time 20087146 ps
CPU time 1.24 seconds
Started May 14 01:57:43 PM PDT 24
Finished May 14 01:57:47 PM PDT 24
Peak memory 214552 kb
Host smart-337a6ccf-6931-4f64-85b9-12f4b3aa080a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247457428 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.247457428
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1029201524
Short name T222
Test name
Test status
Simulation time 43722725 ps
CPU time 0.93 seconds
Started May 14 01:57:32 PM PDT 24
Finished May 14 01:57:34 PM PDT 24
Peak memory 206144 kb
Host smart-daa5d76b-d42e-40bd-abb5-dc9f9b5f4bf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029201524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1029201524
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1124896974
Short name T945
Test name
Test status
Simulation time 21713399 ps
CPU time 0.84 seconds
Started May 14 01:57:32 PM PDT 24
Finished May 14 01:57:34 PM PDT 24
Peak memory 205980 kb
Host smart-9b825912-e646-47bc-8fd9-36fc14f7bf5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124896974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1124896974
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2567831726
Short name T900
Test name
Test status
Simulation time 28194032 ps
CPU time 1.32 seconds
Started May 14 01:57:40 PM PDT 24
Finished May 14 01:57:43 PM PDT 24
Peak memory 206132 kb
Host smart-19edd046-9456-4847-bf74-c8327ae2a7d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567831726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2567831726
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1881422867
Short name T854
Test name
Test status
Simulation time 182092832 ps
CPU time 3.7 seconds
Started May 14 01:57:33 PM PDT 24
Finished May 14 01:57:38 PM PDT 24
Peak memory 214392 kb
Host smart-13270173-3773-4a99-a8f3-c3d111589851
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881422867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1881422867
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3193312607
Short name T965
Test name
Test status
Simulation time 1125738595 ps
CPU time 2.23 seconds
Started May 14 01:57:33 PM PDT 24
Finished May 14 01:57:36 PM PDT 24
Peak memory 206328 kb
Host smart-75c84fb6-f81d-4773-9d70-b93c09616d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193312607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3193312607
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.710441321
Short name T914
Test name
Test status
Simulation time 13276983 ps
CPU time 0.82 seconds
Started May 14 01:58:47 PM PDT 24
Finished May 14 01:58:49 PM PDT 24
Peak memory 206004 kb
Host smart-2f234ea8-fd17-4a25-bdc5-68ea0c50e7b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710441321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.710441321
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2906354745
Short name T871
Test name
Test status
Simulation time 23627746 ps
CPU time 0.82 seconds
Started May 14 01:58:54 PM PDT 24
Finished May 14 01:58:56 PM PDT 24
Peak memory 206012 kb
Host smart-21a7b000-df5d-4853-8a3a-0146a660f4fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906354745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2906354745
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.52596247
Short name T903
Test name
Test status
Simulation time 36446506 ps
CPU time 0.8 seconds
Started May 14 01:58:44 PM PDT 24
Finished May 14 01:58:46 PM PDT 24
Peak memory 205980 kb
Host smart-23276dda-e8b4-4708-916a-bafeaab0e56f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52596247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.52596247
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2641172050
Short name T860
Test name
Test status
Simulation time 15885976 ps
CPU time 0.92 seconds
Started May 14 01:58:44 PM PDT 24
Finished May 14 01:58:46 PM PDT 24
Peak memory 206056 kb
Host smart-6b7a936a-2d04-425a-883a-c779e78b6103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641172050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2641172050
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1794258847
Short name T979
Test name
Test status
Simulation time 74939719 ps
CPU time 0.89 seconds
Started May 14 01:58:44 PM PDT 24
Finished May 14 01:58:46 PM PDT 24
Peak memory 206032 kb
Host smart-dc22eac6-8051-42c7-967c-b12347f697c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794258847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1794258847
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.563645184
Short name T939
Test name
Test status
Simulation time 43817215 ps
CPU time 0.85 seconds
Started May 14 01:58:44 PM PDT 24
Finished May 14 01:58:46 PM PDT 24
Peak memory 205976 kb
Host smart-dcabb1d0-49ba-48ef-abb0-280b09ab5fcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563645184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.563645184
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1398258847
Short name T883
Test name
Test status
Simulation time 23302116 ps
CPU time 0.86 seconds
Started May 14 01:58:52 PM PDT 24
Finished May 14 01:58:54 PM PDT 24
Peak memory 206008 kb
Host smart-8e4894d6-8b06-4a2c-8ff6-76ace4fc6537
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398258847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1398258847
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1002016397
Short name T971
Test name
Test status
Simulation time 16464395 ps
CPU time 0.88 seconds
Started May 14 01:58:45 PM PDT 24
Finished May 14 01:58:47 PM PDT 24
Peak memory 206012 kb
Host smart-60763753-52ff-41a1-8743-61b339e3d2fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002016397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1002016397
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1023239845
Short name T855
Test name
Test status
Simulation time 41113478 ps
CPU time 0.8 seconds
Started May 14 01:58:55 PM PDT 24
Finished May 14 01:58:57 PM PDT 24
Peak memory 205916 kb
Host smart-a4eee082-4f05-468a-9190-7e66430998a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023239845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1023239845
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1929149597
Short name T852
Test name
Test status
Simulation time 12407175 ps
CPU time 0.87 seconds
Started May 14 01:58:44 PM PDT 24
Finished May 14 01:58:45 PM PDT 24
Peak memory 206032 kb
Host smart-71547542-31d6-477e-a872-e9aa87486f35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929149597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1929149597
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.505155418
Short name T213
Test name
Test status
Simulation time 47697860 ps
CPU time 1.2 seconds
Started May 14 01:57:42 PM PDT 24
Finished May 14 01:57:45 PM PDT 24
Peak memory 206216 kb
Host smart-0f2e1941-928a-464e-8f17-ba3cfc113de0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505155418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.505155418
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.647467047
Short name T947
Test name
Test status
Simulation time 114700246 ps
CPU time 3.34 seconds
Started May 14 01:57:41 PM PDT 24
Finished May 14 01:57:46 PM PDT 24
Peak memory 206152 kb
Host smart-124f63bc-fb16-45a5-9378-ef9c8962d6dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647467047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.647467047
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3870134625
Short name T235
Test name
Test status
Simulation time 23972235 ps
CPU time 1.09 seconds
Started May 14 01:57:43 PM PDT 24
Finished May 14 01:57:46 PM PDT 24
Peak memory 206164 kb
Host smart-a6da4449-fd78-4859-a938-9f4e2c9ac580
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870134625 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3870134625
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3575441726
Short name T881
Test name
Test status
Simulation time 25426937 ps
CPU time 1.2 seconds
Started May 14 01:57:53 PM PDT 24
Finished May 14 01:57:55 PM PDT 24
Peak memory 214508 kb
Host smart-e23c2465-d450-4e87-bb8e-cd0e5887a7ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575441726 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3575441726
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1124969642
Short name T216
Test name
Test status
Simulation time 13138758 ps
CPU time 0.88 seconds
Started May 14 01:57:41 PM PDT 24
Finished May 14 01:57:44 PM PDT 24
Peak memory 206352 kb
Host smart-777a8fef-28e6-4587-873b-b663191ee7c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124969642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1124969642
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1114303445
Short name T960
Test name
Test status
Simulation time 34099733 ps
CPU time 0.85 seconds
Started May 14 01:57:41 PM PDT 24
Finished May 14 01:57:44 PM PDT 24
Peak memory 205888 kb
Host smart-1dc8c548-f835-463b-af99-17443edd0725
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114303445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1114303445
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3067913623
Short name T964
Test name
Test status
Simulation time 29246518 ps
CPU time 1.24 seconds
Started May 14 01:57:54 PM PDT 24
Finished May 14 01:57:56 PM PDT 24
Peak memory 206236 kb
Host smart-6bae8ae5-3f94-46bb-a51d-ed2a7fff7aad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067913623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3067913623
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3516406955
Short name T969
Test name
Test status
Simulation time 608446533 ps
CPU time 3.7 seconds
Started May 14 01:57:44 PM PDT 24
Finished May 14 01:57:49 PM PDT 24
Peak memory 214436 kb
Host smart-5aa05c5c-1fb3-4049-b945-2a207be39353
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516406955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3516406955
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1207615996
Short name T239
Test name
Test status
Simulation time 44643693 ps
CPU time 1.45 seconds
Started May 14 01:57:40 PM PDT 24
Finished May 14 01:57:43 PM PDT 24
Peak memory 214336 kb
Host smart-f35ddd31-fd50-4399-9a88-44f4cc4b3b0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207615996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1207615996
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.839334747
Short name T874
Test name
Test status
Simulation time 16783853 ps
CPU time 0.98 seconds
Started May 14 01:58:46 PM PDT 24
Finished May 14 01:58:49 PM PDT 24
Peak memory 205920 kb
Host smart-76fdba9e-e5ae-4997-9a99-ea5bbb0be5f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839334747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.839334747
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2346388357
Short name T937
Test name
Test status
Simulation time 135459481 ps
CPU time 0.83 seconds
Started May 14 01:58:45 PM PDT 24
Finished May 14 01:58:46 PM PDT 24
Peak memory 205924 kb
Host smart-aa6f51b0-12be-4f0e-b120-589313c1e857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346388357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2346388357
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1259615658
Short name T921
Test name
Test status
Simulation time 28276082 ps
CPU time 0.85 seconds
Started May 14 01:58:46 PM PDT 24
Finished May 14 01:58:48 PM PDT 24
Peak memory 205988 kb
Host smart-a6e65017-6c36-438b-9e35-25cb2a19558c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259615658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1259615658
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.696435282
Short name T977
Test name
Test status
Simulation time 13324421 ps
CPU time 0.89 seconds
Started May 14 01:58:44 PM PDT 24
Finished May 14 01:58:46 PM PDT 24
Peak memory 206040 kb
Host smart-1f6620d9-7636-4ece-8bf9-b36cc1c10549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696435282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.696435282
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1206938838
Short name T953
Test name
Test status
Simulation time 20069607 ps
CPU time 0.84 seconds
Started May 14 01:58:43 PM PDT 24
Finished May 14 01:58:45 PM PDT 24
Peak memory 205924 kb
Host smart-0a920800-20e0-4197-b8cf-87d21e1cf728
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206938838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1206938838
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.149313022
Short name T886
Test name
Test status
Simulation time 12510861 ps
CPU time 0.87 seconds
Started May 14 01:58:43 PM PDT 24
Finished May 14 01:58:44 PM PDT 24
Peak memory 206004 kb
Host smart-179c10b5-851b-4d56-9d28-1a173636c118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149313022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.149313022
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1103162078
Short name T933
Test name
Test status
Simulation time 64308986 ps
CPU time 0.87 seconds
Started May 14 01:58:55 PM PDT 24
Finished May 14 01:58:57 PM PDT 24
Peak memory 206008 kb
Host smart-bee900ab-e1dd-4790-b32f-e52e3654bfc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103162078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1103162078
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1225875770
Short name T963
Test name
Test status
Simulation time 38387187 ps
CPU time 0.85 seconds
Started May 14 01:58:43 PM PDT 24
Finished May 14 01:58:45 PM PDT 24
Peak memory 206016 kb
Host smart-ed4b4aba-0900-4ef4-aa86-56e794be5518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225875770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1225875770
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2017690918
Short name T909
Test name
Test status
Simulation time 71029891 ps
CPU time 0.81 seconds
Started May 14 01:58:42 PM PDT 24
Finished May 14 01:58:44 PM PDT 24
Peak memory 205920 kb
Host smart-f92414bd-e7fe-44dd-aea3-56ce2041520f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017690918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2017690918
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.915681340
Short name T973
Test name
Test status
Simulation time 11737695 ps
CPU time 0.85 seconds
Started May 14 01:58:51 PM PDT 24
Finished May 14 01:58:53 PM PDT 24
Peak memory 206048 kb
Host smart-c3799ada-8be5-4ed6-8bbe-d00a848270eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915681340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.915681340
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2172778866
Short name T912
Test name
Test status
Simulation time 184237883 ps
CPU time 1.4 seconds
Started May 14 01:57:50 PM PDT 24
Finished May 14 01:57:53 PM PDT 24
Peak memory 214436 kb
Host smart-cc1bed83-2e9b-41be-9f3f-db9e5663fb31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172778866 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2172778866
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3629998891
Short name T229
Test name
Test status
Simulation time 41135077 ps
CPU time 0.88 seconds
Started May 14 01:57:49 PM PDT 24
Finished May 14 01:57:51 PM PDT 24
Peak memory 206188 kb
Host smart-c4a1b2a9-b34c-4358-95c3-d87785ed9570
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629998891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3629998891
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1997477342
Short name T928
Test name
Test status
Simulation time 15221417 ps
CPU time 0.91 seconds
Started May 14 01:57:48 PM PDT 24
Finished May 14 01:57:50 PM PDT 24
Peak memory 205984 kb
Host smart-3d638c85-93d7-4608-9754-e4787af4be76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997477342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1997477342
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.54518818
Short name T962
Test name
Test status
Simulation time 76407154 ps
CPU time 1.07 seconds
Started May 14 01:57:48 PM PDT 24
Finished May 14 01:57:50 PM PDT 24
Peak memory 206144 kb
Host smart-acd8a4e0-8811-4511-b00c-ac36bc695dba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54518818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outs
tanding.54518818
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3149406887
Short name T976
Test name
Test status
Simulation time 186018713 ps
CPU time 3.31 seconds
Started May 14 01:57:48 PM PDT 24
Finished May 14 01:57:52 PM PDT 24
Peak memory 214432 kb
Host smart-65699e86-7559-4bc0-835f-c4a7a42ff7c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149406887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3149406887
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.515476839
Short name T247
Test name
Test status
Simulation time 86230145 ps
CPU time 2.41 seconds
Started May 14 01:57:49 PM PDT 24
Finished May 14 01:57:52 PM PDT 24
Peak memory 206180 kb
Host smart-665ee087-a765-4b7d-b310-8175d1a0341a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515476839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.515476839
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.926683005
Short name T882
Test name
Test status
Simulation time 24102124 ps
CPU time 1.7 seconds
Started May 14 01:57:49 PM PDT 24
Finished May 14 01:57:51 PM PDT 24
Peak memory 214424 kb
Host smart-5973f0fe-74d0-4c9b-8654-0baf7250b78b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926683005 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.926683005
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2931498622
Short name T228
Test name
Test status
Simulation time 14003331 ps
CPU time 0.91 seconds
Started May 14 01:57:49 PM PDT 24
Finished May 14 01:57:51 PM PDT 24
Peak memory 206180 kb
Host smart-a7fb1b9e-6c26-436f-812a-dadf121f670a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931498622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2931498622
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3189597030
Short name T974
Test name
Test status
Simulation time 48044660 ps
CPU time 0.75 seconds
Started May 14 01:57:52 PM PDT 24
Finished May 14 01:57:54 PM PDT 24
Peak memory 205904 kb
Host smart-64e14d08-c588-4f63-a81a-8e25046c7ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189597030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3189597030
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.312839960
Short name T233
Test name
Test status
Simulation time 138338118 ps
CPU time 1.44 seconds
Started May 14 01:57:48 PM PDT 24
Finished May 14 01:57:50 PM PDT 24
Peak memory 206184 kb
Host smart-ee62353b-7895-41db-a6a8-7f3f294fe7a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312839960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.312839960
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2808411019
Short name T930
Test name
Test status
Simulation time 216116421 ps
CPU time 3.7 seconds
Started May 14 01:57:53 PM PDT 24
Finished May 14 01:57:57 PM PDT 24
Peak memory 214400 kb
Host smart-e6370c0a-f1ce-4532-a941-59298fa0d8e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808411019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2808411019
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3415198750
Short name T978
Test name
Test status
Simulation time 90898517 ps
CPU time 1.54 seconds
Started May 14 01:57:50 PM PDT 24
Finished May 14 01:57:53 PM PDT 24
Peak memory 206480 kb
Host smart-3ae83187-3d5a-450f-91bd-425be2e19ace
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415198750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3415198750
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.519782590
Short name T911
Test name
Test status
Simulation time 29576516 ps
CPU time 1.47 seconds
Started May 14 01:57:58 PM PDT 24
Finished May 14 01:58:01 PM PDT 24
Peak memory 214412 kb
Host smart-3485a766-da00-467b-bdd8-bc6bf875ddb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519782590 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.519782590
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.129864933
Short name T958
Test name
Test status
Simulation time 17070013 ps
CPU time 0.9 seconds
Started May 14 01:57:57 PM PDT 24
Finished May 14 01:57:59 PM PDT 24
Peak memory 206148 kb
Host smart-f7a3639b-70ca-492b-8f84-959aa695cb2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129864933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.129864933
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1080784307
Short name T948
Test name
Test status
Simulation time 24820219 ps
CPU time 0.83 seconds
Started May 14 01:57:56 PM PDT 24
Finished May 14 01:57:58 PM PDT 24
Peak memory 206028 kb
Host smart-318bc912-6aa5-4348-849d-f9ff1da9d377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080784307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1080784307
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3560431686
Short name T954
Test name
Test status
Simulation time 15173829 ps
CPU time 0.98 seconds
Started May 14 01:57:54 PM PDT 24
Finished May 14 01:57:56 PM PDT 24
Peak memory 206256 kb
Host smart-f7431b5f-4d66-4126-9164-75b573ce64c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560431686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3560431686
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.415555278
Short name T873
Test name
Test status
Simulation time 134513114 ps
CPU time 2.9 seconds
Started May 14 01:57:50 PM PDT 24
Finished May 14 01:57:54 PM PDT 24
Peak memory 214392 kb
Host smart-f8a159e2-7179-429b-9e17-b9a13c9c6651
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415555278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.415555278
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.4200078861
Short name T931
Test name
Test status
Simulation time 142591491 ps
CPU time 1.6 seconds
Started May 14 01:57:58 PM PDT 24
Finished May 14 01:58:01 PM PDT 24
Peak memory 206196 kb
Host smart-8a46f7b8-19ef-4040-b688-1970c00dcd12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200078861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.4200078861
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1452359845
Short name T899
Test name
Test status
Simulation time 31510899 ps
CPU time 1.41 seconds
Started May 14 01:57:55 PM PDT 24
Finished May 14 01:57:57 PM PDT 24
Peak memory 214448 kb
Host smart-2788b3e5-c07c-49f7-9044-ce5393e044c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452359845 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1452359845
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.4168372820
Short name T237
Test name
Test status
Simulation time 22714475 ps
CPU time 0.89 seconds
Started May 14 01:57:59 PM PDT 24
Finished May 14 01:58:01 PM PDT 24
Peak memory 206144 kb
Host smart-f8980903-667f-4aa7-8e86-38e74597199e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168372820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.4168372820
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3434260565
Short name T938
Test name
Test status
Simulation time 134904081 ps
CPU time 0.92 seconds
Started May 14 01:57:58 PM PDT 24
Finished May 14 01:58:00 PM PDT 24
Peak memory 206012 kb
Host smart-227b2d69-0dc3-4dad-94dd-e7664f75af55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434260565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3434260565
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3442524887
Short name T231
Test name
Test status
Simulation time 74004107 ps
CPU time 1.46 seconds
Started May 14 01:57:59 PM PDT 24
Finished May 14 01:58:01 PM PDT 24
Peak memory 206140 kb
Host smart-06c766e4-15fd-48b8-8f0e-c88ffa8e759f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442524887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3442524887
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2717354946
Short name T935
Test name
Test status
Simulation time 37475809 ps
CPU time 2.35 seconds
Started May 14 01:57:59 PM PDT 24
Finished May 14 01:58:02 PM PDT 24
Peak memory 214416 kb
Host smart-6cc219ba-c01d-48a4-b18b-d08cbb979e8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717354946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2717354946
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.81328105
Short name T966
Test name
Test status
Simulation time 319329040 ps
CPU time 2.5 seconds
Started May 14 01:57:57 PM PDT 24
Finished May 14 01:58:00 PM PDT 24
Peak memory 214436 kb
Host smart-c0dde956-20bc-487f-84be-728cd5b4a732
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81328105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.81328105
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3134833313
Short name T853
Test name
Test status
Simulation time 126365395 ps
CPU time 1.6 seconds
Started May 14 01:58:05 PM PDT 24
Finished May 14 01:58:08 PM PDT 24
Peak memory 214384 kb
Host smart-60e7e78c-81e9-48a3-9d3a-295063b964ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134833313 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3134833313
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.4087393173
Short name T922
Test name
Test status
Simulation time 36072900 ps
CPU time 0.86 seconds
Started May 14 01:58:04 PM PDT 24
Finished May 14 01:58:06 PM PDT 24
Peak memory 206176 kb
Host smart-9b380ead-8f7c-400b-b8a9-8ff841fc19e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087393173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.4087393173
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.4042408345
Short name T906
Test name
Test status
Simulation time 23822988 ps
CPU time 0.87 seconds
Started May 14 01:58:01 PM PDT 24
Finished May 14 01:58:03 PM PDT 24
Peak memory 206064 kb
Host smart-c18762ad-97af-4f05-b35d-6159d9cca51f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042408345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.4042408345
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.574583693
Short name T221
Test name
Test status
Simulation time 12349480 ps
CPU time 0.94 seconds
Started May 14 01:58:04 PM PDT 24
Finished May 14 01:58:06 PM PDT 24
Peak memory 206100 kb
Host smart-5bd2aecc-2a56-4163-97b3-9b97fb95f8c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574583693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.574583693
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3566554990
Short name T924
Test name
Test status
Simulation time 214583515 ps
CPU time 1.89 seconds
Started May 14 01:57:58 PM PDT 24
Finished May 14 01:58:01 PM PDT 24
Peak memory 214348 kb
Host smart-026cb162-8d13-46a9-af02-51bb7bf50536
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566554990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3566554990
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.77279758
Short name T872
Test name
Test status
Simulation time 185545789 ps
CPU time 1.72 seconds
Started May 14 01:58:02 PM PDT 24
Finished May 14 01:58:05 PM PDT 24
Peak memory 206176 kb
Host smart-37fd150b-99e5-40d5-a36d-e0e9bf6f543e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77279758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.77279758
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.1465521500
Short name T700
Test name
Test status
Simulation time 49445529 ps
CPU time 1.22 seconds
Started May 14 02:07:40 PM PDT 24
Finished May 14 02:07:43 PM PDT 24
Peak memory 215320 kb
Host smart-acf46d0e-f0aa-454c-89f0-ae80ef938ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465521500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1465521500
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable.2047154281
Short name T809
Test name
Test status
Simulation time 91717471 ps
CPU time 0.88 seconds
Started May 14 02:07:38 PM PDT 24
Finished May 14 02:07:41 PM PDT 24
Peak memory 216148 kb
Host smart-b3e10cb2-5fa5-4697-9e65-f2f359a22085
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047154281 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2047154281
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_genbits.1319715689
Short name T668
Test name
Test status
Simulation time 544885765 ps
CPU time 3.58 seconds
Started May 14 02:07:38 PM PDT 24
Finished May 14 02:07:44 PM PDT 24
Peak memory 216808 kb
Host smart-ec6a38c3-c446-4111-b1b4-02b9103c340a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319715689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1319715689
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.3989867226
Short name T107
Test name
Test status
Simulation time 17534238 ps
CPU time 0.99 seconds
Started May 14 02:07:42 PM PDT 24
Finished May 14 02:07:44 PM PDT 24
Peak memory 206800 kb
Host smart-6b871909-932c-4c69-8bef-29f3a3fac000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989867226 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3989867226
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.4003784115
Short name T432
Test name
Test status
Simulation time 149195705 ps
CPU time 0.95 seconds
Started May 14 02:07:38 PM PDT 24
Finished May 14 02:07:40 PM PDT 24
Peak memory 214896 kb
Host smart-da47a2a2-1aa3-4aa5-8060-3277f3531911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003784115 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.4003784115
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3591407942
Short name T161
Test name
Test status
Simulation time 241813904 ps
CPU time 1.74 seconds
Started May 14 02:07:41 PM PDT 24
Finished May 14 02:07:45 PM PDT 24
Peak memory 214912 kb
Host smart-85603d9c-f7ee-43a9-ab79-b20b251058fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591407942 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3591407942
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert_test.21520070
Short name T664
Test name
Test status
Simulation time 18437631 ps
CPU time 0.99 seconds
Started May 14 02:07:47 PM PDT 24
Finished May 14 02:07:49 PM PDT 24
Peak memory 206312 kb
Host smart-7cd29797-dfbe-4720-ad25-57c35f1de2d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21520070 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.21520070
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_err.2204466572
Short name T77
Test name
Test status
Simulation time 18146883 ps
CPU time 1.08 seconds
Started May 14 02:07:47 PM PDT 24
Finished May 14 02:07:50 PM PDT 24
Peak memory 217944 kb
Host smart-993b0391-163c-4dbe-b56e-e64bda80ebb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204466572 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2204466572
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_intr.1967706753
Short name T143
Test name
Test status
Simulation time 26886885 ps
CPU time 0.95 seconds
Started May 14 02:07:49 PM PDT 24
Finished May 14 02:07:51 PM PDT 24
Peak memory 215404 kb
Host smart-071a6625-a82f-4ff0-a21a-e04ad5c4a45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967706753 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1967706753
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3383874683
Short name T15
Test name
Test status
Simulation time 1800684646 ps
CPU time 7.51 seconds
Started May 14 02:07:46 PM PDT 24
Finished May 14 02:07:55 PM PDT 24
Peak memory 235828 kb
Host smart-16cda31c-b48b-4a6b-a163-2150de387d0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383874683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3383874683
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2974482499
Short name T328
Test name
Test status
Simulation time 27659724 ps
CPU time 0.96 seconds
Started May 14 02:07:45 PM PDT 24
Finished May 14 02:07:47 PM PDT 24
Peak memory 214964 kb
Host smart-163b481b-b1e2-428c-ab96-e6b6de58eddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974482499 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2974482499
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3378093148
Short name T566
Test name
Test status
Simulation time 296177731 ps
CPU time 5.98 seconds
Started May 14 02:07:49 PM PDT 24
Finished May 14 02:07:56 PM PDT 24
Peak memory 216688 kb
Host smart-f3f202a5-4f13-40d4-8304-360840f508b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378093148 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3378093148
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert_test.1932772052
Short name T136
Test name
Test status
Simulation time 56397067 ps
CPU time 0.82 seconds
Started May 14 02:08:28 PM PDT 24
Finished May 14 02:08:30 PM PDT 24
Peak memory 206484 kb
Host smart-2823bd1c-b9d3-4dfa-94dd-4dcd0b172c52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932772052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1932772052
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.604317923
Short name T423
Test name
Test status
Simulation time 35836899 ps
CPU time 1.26 seconds
Started May 14 02:08:28 PM PDT 24
Finished May 14 02:08:30 PM PDT 24
Peak memory 218080 kb
Host smart-4fd23fd8-4ded-4cfe-a859-497c342e8ef7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604317923 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.604317923
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.2804654459
Short name T173
Test name
Test status
Simulation time 28949684 ps
CPU time 1.35 seconds
Started May 14 02:08:12 PM PDT 24
Finished May 14 02:08:15 PM PDT 24
Peak memory 225220 kb
Host smart-285141bc-cca7-46a3-84ea-d33466cbfbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804654459 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2804654459
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3062320061
Short name T716
Test name
Test status
Simulation time 19577530 ps
CPU time 1.09 seconds
Started May 14 02:08:08 PM PDT 24
Finished May 14 02:08:10 PM PDT 24
Peak memory 216872 kb
Host smart-e3e80ffb-dab3-4262-85fa-31569f71dbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062320061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3062320061
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1269178182
Short name T654
Test name
Test status
Simulation time 25657832 ps
CPU time 0.95 seconds
Started May 14 02:08:08 PM PDT 24
Finished May 14 02:08:11 PM PDT 24
Peak memory 215328 kb
Host smart-41126b0b-c359-49bb-9051-4d41e30f8429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269178182 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1269178182
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.162604606
Short name T789
Test name
Test status
Simulation time 14833006 ps
CPU time 0.92 seconds
Started May 14 02:08:09 PM PDT 24
Finished May 14 02:08:12 PM PDT 24
Peak memory 214964 kb
Host smart-b94af2e1-df92-4f95-b9f4-c54142b1cb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162604606 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.162604606
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1136392569
Short name T605
Test name
Test status
Simulation time 847202488 ps
CPU time 4.98 seconds
Started May 14 02:08:10 PM PDT 24
Finished May 14 02:08:17 PM PDT 24
Peak memory 216596 kb
Host smart-95516536-4ef0-4269-84b5-b218f72507ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136392569 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1136392569
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.980016217
Short name T197
Test name
Test status
Simulation time 446545868310 ps
CPU time 2577.02 seconds
Started May 14 02:08:09 PM PDT 24
Finished May 14 02:51:08 PM PDT 24
Peak memory 227544 kb
Host smart-eaefa57b-dfc2-47c0-9c6c-61357011c72c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980016217 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.980016217
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.3361962115
Short name T804
Test name
Test status
Simulation time 76241348 ps
CPU time 1.1 seconds
Started May 14 02:10:13 PM PDT 24
Finished May 14 02:10:17 PM PDT 24
Peak memory 218600 kb
Host smart-6a0083ec-aa0d-4747-99fb-eb5818c84e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361962115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3361962115
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.4108619304
Short name T614
Test name
Test status
Simulation time 37498599 ps
CPU time 1.11 seconds
Started May 14 02:10:11 PM PDT 24
Finished May 14 02:10:15 PM PDT 24
Peak memory 216616 kb
Host smart-4a9f5d62-f650-4386-944a-0b06fa44839b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108619304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.4108619304
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.2936656833
Short name T826
Test name
Test status
Simulation time 59197446 ps
CPU time 1.12 seconds
Started May 14 02:10:08 PM PDT 24
Finished May 14 02:10:10 PM PDT 24
Peak memory 219448 kb
Host smart-9114ef03-ca5a-44dd-96fa-e4df56194bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936656833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2936656833
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.2025642111
Short name T759
Test name
Test status
Simulation time 46673120 ps
CPU time 1.67 seconds
Started May 14 02:10:09 PM PDT 24
Finished May 14 02:10:13 PM PDT 24
Peak memory 218828 kb
Host smart-429675da-e065-4b07-94d7-08791703ded3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025642111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2025642111
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.2767295052
Short name T390
Test name
Test status
Simulation time 125551974 ps
CPU time 1.27 seconds
Started May 14 02:10:09 PM PDT 24
Finished May 14 02:10:12 PM PDT 24
Peak memory 218060 kb
Host smart-77edad3b-0ea8-4f4c-894c-3596dc1c604d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767295052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2767295052
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1145749429
Short name T589
Test name
Test status
Simulation time 80695604 ps
CPU time 1.23 seconds
Started May 14 02:10:22 PM PDT 24
Finished May 14 02:10:25 PM PDT 24
Peak memory 216640 kb
Host smart-141c734e-b4a9-494b-a563-ab88968cd35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145749429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1145749429
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.226677511
Short name T746
Test name
Test status
Simulation time 98469241 ps
CPU time 1.54 seconds
Started May 14 02:10:21 PM PDT 24
Finished May 14 02:10:25 PM PDT 24
Peak memory 216820 kb
Host smart-ca679188-d6d2-4d5a-bbb3-af6fc26068dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226677511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.226677511
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.2357068711
Short name T242
Test name
Test status
Simulation time 24904461 ps
CPU time 1.11 seconds
Started May 14 02:10:09 PM PDT 24
Finished May 14 02:10:13 PM PDT 24
Peak memory 216464 kb
Host smart-5896d03c-9481-4817-9b25-06b095ed4b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357068711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2357068711
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.3936259854
Short name T298
Test name
Test status
Simulation time 568474290 ps
CPU time 6.05 seconds
Started May 14 02:10:09 PM PDT 24
Finished May 14 02:10:16 PM PDT 24
Peak memory 219248 kb
Host smart-ec2ecc2c-1201-42c8-8165-6b6cfd1e805a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936259854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3936259854
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3367384734
Short name T541
Test name
Test status
Simulation time 75590574 ps
CPU time 1.13 seconds
Started May 14 02:10:10 PM PDT 24
Finished May 14 02:10:14 PM PDT 24
Peak memory 216588 kb
Host smart-016dd577-93a7-4692-806d-10ac2b62b11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367384734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3367384734
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2969744702
Short name T710
Test name
Test status
Simulation time 86590803 ps
CPU time 1.16 seconds
Started May 14 02:08:27 PM PDT 24
Finished May 14 02:08:29 PM PDT 24
Peak memory 215352 kb
Host smart-aa2da4b5-e2f7-40ca-b7c7-428eae812869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969744702 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2969744702
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.113015076
Short name T766
Test name
Test status
Simulation time 17473984 ps
CPU time 0.91 seconds
Started May 14 02:08:27 PM PDT 24
Finished May 14 02:08:30 PM PDT 24
Peak memory 206276 kb
Host smart-0924c462-df1d-469a-9d27-06da4435a73c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113015076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.113015076
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.301725567
Short name T658
Test name
Test status
Simulation time 371231325 ps
CPU time 1.15 seconds
Started May 14 02:08:22 PM PDT 24
Finished May 14 02:08:26 PM PDT 24
Peak memory 219552 kb
Host smart-4d2568c2-bbb4-4cb2-a609-aa02ef689be4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301725567 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.301725567
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.388001530
Short name T572
Test name
Test status
Simulation time 32392209 ps
CPU time 0.94 seconds
Started May 14 02:08:21 PM PDT 24
Finished May 14 02:08:23 PM PDT 24
Peak memory 218164 kb
Host smart-96116447-dde0-4462-998f-5cef9d61ddef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388001530 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.388001530
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.767368598
Short name T753
Test name
Test status
Simulation time 69136598 ps
CPU time 1.15 seconds
Started May 14 02:08:22 PM PDT 24
Finished May 14 02:08:26 PM PDT 24
Peak memory 219360 kb
Host smart-6bfec37c-784b-4dce-86f9-ca86ff692dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767368598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.767368598
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.956616494
Short name T769
Test name
Test status
Simulation time 24818873 ps
CPU time 0.98 seconds
Started May 14 02:08:19 PM PDT 24
Finished May 14 02:08:21 PM PDT 24
Peak memory 215268 kb
Host smart-b994020a-aa1a-42aa-9e57-0e1ebb160cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956616494 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.956616494
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1070128900
Short name T840
Test name
Test status
Simulation time 17834508 ps
CPU time 0.96 seconds
Started May 14 02:08:28 PM PDT 24
Finished May 14 02:08:31 PM PDT 24
Peak memory 214936 kb
Host smart-425b8d66-f390-46a0-9cc4-e26b86d695f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070128900 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1070128900
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.407873071
Short name T1
Test name
Test status
Simulation time 261098773 ps
CPU time 1.19 seconds
Started May 14 02:08:22 PM PDT 24
Finished May 14 02:08:26 PM PDT 24
Peak memory 216648 kb
Host smart-8a9d8b82-ffb8-4400-8a37-6f0512b717c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407873071 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.407873071
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2951481872
Short name T659
Test name
Test status
Simulation time 35516667919 ps
CPU time 403.53 seconds
Started May 14 02:08:26 PM PDT 24
Finished May 14 02:15:11 PM PDT 24
Peak memory 217384 kb
Host smart-cf183dc4-44a0-43a0-8aa8-f288505ad33f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951481872 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2951481872
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.1768818881
Short name T399
Test name
Test status
Simulation time 36312043 ps
CPU time 1.54 seconds
Started May 14 02:10:22 PM PDT 24
Finished May 14 02:10:26 PM PDT 24
Peak memory 217864 kb
Host smart-c93b767f-1ed9-437e-a628-6c4433cdb837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768818881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1768818881
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.1695866198
Short name T426
Test name
Test status
Simulation time 67831138 ps
CPU time 1.39 seconds
Started May 14 02:10:11 PM PDT 24
Finished May 14 02:10:16 PM PDT 24
Peak memory 217880 kb
Host smart-b4dec0fd-3ca4-404e-9361-711f5d734c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695866198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1695866198
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.3574897016
Short name T266
Test name
Test status
Simulation time 106781998 ps
CPU time 1.21 seconds
Started May 14 02:10:22 PM PDT 24
Finished May 14 02:10:25 PM PDT 24
Peak memory 216492 kb
Host smart-6ae78ead-2378-41c0-b4e8-27e6f0c15b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574897016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3574897016
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.4159016280
Short name T848
Test name
Test status
Simulation time 31704417 ps
CPU time 1.28 seconds
Started May 14 02:10:09 PM PDT 24
Finished May 14 02:10:12 PM PDT 24
Peak memory 217776 kb
Host smart-9f99dff6-4220-4598-a82a-c633d8307f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159016280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.4159016280
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.2918777150
Short name T205
Test name
Test status
Simulation time 168616031 ps
CPU time 2.46 seconds
Started May 14 02:10:11 PM PDT 24
Finished May 14 02:10:17 PM PDT 24
Peak memory 219612 kb
Host smart-affe8a52-2bc3-4d9a-9fcd-a90f85ecb7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918777150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2918777150
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.3324422947
Short name T479
Test name
Test status
Simulation time 117117894 ps
CPU time 0.96 seconds
Started May 14 02:10:10 PM PDT 24
Finished May 14 02:10:13 PM PDT 24
Peak memory 216748 kb
Host smart-86dc137b-efa6-4173-b4a7-b40a078a9105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324422947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3324422947
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.1385627301
Short name T350
Test name
Test status
Simulation time 118251716 ps
CPU time 1.13 seconds
Started May 14 02:10:21 PM PDT 24
Finished May 14 02:10:25 PM PDT 24
Peak memory 218824 kb
Host smart-1034770d-5bc2-4fa7-9bd8-57b7dea7013c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385627301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1385627301
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.555459672
Short name T511
Test name
Test status
Simulation time 205293519 ps
CPU time 3.22 seconds
Started May 14 02:10:12 PM PDT 24
Finished May 14 02:10:18 PM PDT 24
Peak memory 218164 kb
Host smart-d805fab0-72c3-4b63-9863-595026e8dc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555459672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.555459672
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.2832990887
Short name T737
Test name
Test status
Simulation time 92826315 ps
CPU time 1.22 seconds
Started May 14 02:10:04 PM PDT 24
Finished May 14 02:10:06 PM PDT 24
Peak memory 216808 kb
Host smart-50fbdfa6-0223-485a-a686-bae5ec8fff69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832990887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2832990887
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.2350082236
Short name T493
Test name
Test status
Simulation time 40354155 ps
CPU time 1.57 seconds
Started May 14 02:10:07 PM PDT 24
Finished May 14 02:10:10 PM PDT 24
Peak memory 216932 kb
Host smart-bae47271-6712-4dea-8bbe-aba3d9e1dd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350082236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2350082236
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.641306507
Short name T259
Test name
Test status
Simulation time 156172669 ps
CPU time 1.14 seconds
Started May 14 02:08:28 PM PDT 24
Finished May 14 02:08:30 PM PDT 24
Peak memory 215304 kb
Host smart-bb4fee78-cb9a-4a1d-904c-bab50f440372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641306507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.641306507
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.1830836583
Short name T418
Test name
Test status
Simulation time 42163681 ps
CPU time 0.89 seconds
Started May 14 02:08:21 PM PDT 24
Finished May 14 02:08:25 PM PDT 24
Peak memory 206116 kb
Host smart-23a495b7-5931-4b69-8135-b2a0e85ef9f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830836583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1830836583
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.579604989
Short name T594
Test name
Test status
Simulation time 10720339 ps
CPU time 0.92 seconds
Started May 14 02:08:26 PM PDT 24
Finished May 14 02:08:28 PM PDT 24
Peak memory 215760 kb
Host smart-cd8e3be9-a3e8-4a69-99c0-d3e6f3502d3e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579604989 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.579604989
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1154666990
Short name T647
Test name
Test status
Simulation time 115152059 ps
CPU time 1.29 seconds
Started May 14 02:08:21 PM PDT 24
Finished May 14 02:08:24 PM PDT 24
Peak memory 216696 kb
Host smart-5938b9bf-7ea8-48d0-bb63-397066b9fa8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154666990 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1154666990
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.2966304496
Short name T37
Test name
Test status
Simulation time 25836664 ps
CPU time 1.37 seconds
Started May 14 02:08:29 PM PDT 24
Finished May 14 02:08:32 PM PDT 24
Peak memory 229112 kb
Host smart-5d0834b1-9224-4bed-958e-6b165c683856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966304496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2966304496
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.73595749
Short name T202
Test name
Test status
Simulation time 96560656 ps
CPU time 1.24 seconds
Started May 14 02:08:23 PM PDT 24
Finished May 14 02:08:27 PM PDT 24
Peak memory 216772 kb
Host smart-56ea1234-f1d0-4d3b-ba36-2b0eef36a8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73595749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.73595749
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3412922533
Short name T563
Test name
Test status
Simulation time 40037824 ps
CPU time 1 seconds
Started May 14 02:08:28 PM PDT 24
Finished May 14 02:08:31 PM PDT 24
Peak memory 223388 kb
Host smart-009187fd-f12f-4e59-8c60-d35926ea3545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412922533 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3412922533
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2667904482
Short name T803
Test name
Test status
Simulation time 16237011 ps
CPU time 1.03 seconds
Started May 14 02:08:26 PM PDT 24
Finished May 14 02:08:28 PM PDT 24
Peak memory 214956 kb
Host smart-ba91510e-233b-4cc9-8b17-036d09679ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667904482 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2667904482
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3956661695
Short name T151
Test name
Test status
Simulation time 366512867 ps
CPU time 6.38 seconds
Started May 14 02:08:21 PM PDT 24
Finished May 14 02:08:30 PM PDT 24
Peak memory 216736 kb
Host smart-468c0681-dfd6-49ca-a5bd-53eb5d4e95bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956661695 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3956661695
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2168423914
Short name T164
Test name
Test status
Simulation time 30775650068 ps
CPU time 782.49 seconds
Started May 14 02:08:30 PM PDT 24
Finished May 14 02:21:34 PM PDT 24
Peak memory 218352 kb
Host smart-c6915645-d139-4081-940c-9316553ac0a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168423914 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2168423914
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.247097557
Short name T384
Test name
Test status
Simulation time 105591980 ps
CPU time 1.46 seconds
Started May 14 02:10:12 PM PDT 24
Finished May 14 02:10:17 PM PDT 24
Peak memory 218156 kb
Host smart-17408932-ac70-43f1-adbb-495f0f86b5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247097557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.247097557
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.1933698119
Short name T796
Test name
Test status
Simulation time 128775122 ps
CPU time 1.8 seconds
Started May 14 02:10:12 PM PDT 24
Finished May 14 02:10:17 PM PDT 24
Peak memory 218280 kb
Host smart-723cff53-e0dd-42ce-897c-e3e612d75fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933698119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1933698119
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.1210015720
Short name T296
Test name
Test status
Simulation time 291220076 ps
CPU time 1.48 seconds
Started May 14 02:10:22 PM PDT 24
Finished May 14 02:10:26 PM PDT 24
Peak memory 218024 kb
Host smart-1b54017e-0266-40a8-a9f1-c3d4b4c72c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210015720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1210015720
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.1840957737
Short name T376
Test name
Test status
Simulation time 64506222 ps
CPU time 1.28 seconds
Started May 14 02:10:20 PM PDT 24
Finished May 14 02:10:24 PM PDT 24
Peak memory 218096 kb
Host smart-21eda402-28d0-4cad-bfb8-6da7df1e99f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840957737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1840957737
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3129201099
Short name T326
Test name
Test status
Simulation time 96055380 ps
CPU time 2.89 seconds
Started May 14 02:10:18 PM PDT 24
Finished May 14 02:10:24 PM PDT 24
Peak memory 219476 kb
Host smart-34965821-f319-40a0-8eb1-1f971625ab35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129201099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3129201099
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.3219460313
Short name T562
Test name
Test status
Simulation time 108955085 ps
CPU time 2.36 seconds
Started May 14 02:10:19 PM PDT 24
Finished May 14 02:10:24 PM PDT 24
Peak memory 218904 kb
Host smart-1dc3f877-0d94-429e-bf48-702e6dfbbaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219460313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3219460313
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.1954180843
Short name T293
Test name
Test status
Simulation time 34181344 ps
CPU time 1.24 seconds
Started May 14 02:10:17 PM PDT 24
Finished May 14 02:10:21 PM PDT 24
Peak memory 216600 kb
Host smart-45759560-bf24-4cb6-9d88-f3b9fe6bb049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954180843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1954180843
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.3537339306
Short name T802
Test name
Test status
Simulation time 18870675 ps
CPU time 0.8 seconds
Started May 14 02:08:27 PM PDT 24
Finished May 14 02:08:29 PM PDT 24
Peak memory 206528 kb
Host smart-91f85e26-42eb-4c23-a982-87e14d2ce956
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537339306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3537339306
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.945012702
Short name T176
Test name
Test status
Simulation time 31684038 ps
CPU time 0.87 seconds
Started May 14 02:08:24 PM PDT 24
Finished May 14 02:08:26 PM PDT 24
Peak memory 215124 kb
Host smart-0d3da06b-aac4-4932-8fdd-d45c7f5f8751
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945012702 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.945012702
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.605632462
Short name T44
Test name
Test status
Simulation time 81873131 ps
CPU time 1.05 seconds
Started May 14 02:08:21 PM PDT 24
Finished May 14 02:08:24 PM PDT 24
Peak memory 217788 kb
Host smart-e594a494-0e0e-4437-90d5-28baa0c30f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605632462 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.605632462
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.682630526
Short name T795
Test name
Test status
Simulation time 39225410 ps
CPU time 1.65 seconds
Started May 14 02:08:22 PM PDT 24
Finished May 14 02:08:27 PM PDT 24
Peak memory 217948 kb
Host smart-a6677219-e2ba-43b2-b160-acdbc53c4bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682630526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.682630526
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.1386016728
Short name T628
Test name
Test status
Simulation time 96913470 ps
CPU time 1.01 seconds
Started May 14 02:08:21 PM PDT 24
Finished May 14 02:08:24 PM PDT 24
Peak memory 214932 kb
Host smart-6c68862c-8fd1-4ba2-b3cc-d15a73b5ceff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386016728 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1386016728
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3292517997
Short name T816
Test name
Test status
Simulation time 429718096 ps
CPU time 2.77 seconds
Started May 14 02:08:22 PM PDT 24
Finished May 14 02:08:28 PM PDT 24
Peak memory 215008 kb
Host smart-0d71fc1f-16b6-4dbb-a277-60d9beea0eb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292517997 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3292517997
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2306908700
Short name T847
Test name
Test status
Simulation time 77343597768 ps
CPU time 996.8 seconds
Started May 14 02:08:21 PM PDT 24
Finished May 14 02:25:01 PM PDT 24
Peak memory 222472 kb
Host smart-0c9e90fa-3768-485c-a7f9-673406d67e30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306908700 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2306908700
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.edn_genbits.176710634
Short name T131
Test name
Test status
Simulation time 100020717 ps
CPU time 1.27 seconds
Started May 14 02:10:18 PM PDT 24
Finished May 14 02:10:22 PM PDT 24
Peak memory 216584 kb
Host smart-b6f0fecd-aefb-49c8-b13e-16f7172ac6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176710634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.176710634
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.3715529474
Short name T356
Test name
Test status
Simulation time 42066235 ps
CPU time 1.93 seconds
Started May 14 02:10:21 PM PDT 24
Finished May 14 02:10:26 PM PDT 24
Peak memory 217672 kb
Host smart-6517a776-494d-4eaf-867b-b4c28faee9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715529474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3715529474
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.4172565315
Short name T394
Test name
Test status
Simulation time 27663049 ps
CPU time 1.28 seconds
Started May 14 02:10:20 PM PDT 24
Finished May 14 02:10:24 PM PDT 24
Peak memory 217924 kb
Host smart-0612a4a3-a955-47c4-8f16-fc3d9a9c220c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172565315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.4172565315
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2931298280
Short name T542
Test name
Test status
Simulation time 200842133 ps
CPU time 1.23 seconds
Started May 14 02:10:31 PM PDT 24
Finished May 14 02:10:34 PM PDT 24
Peak memory 219152 kb
Host smart-72d7e6ed-6527-43cf-a015-a365496d5c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931298280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2931298280
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.4009072604
Short name T538
Test name
Test status
Simulation time 63654103 ps
CPU time 1.36 seconds
Started May 14 02:10:21 PM PDT 24
Finished May 14 02:10:25 PM PDT 24
Peak memory 217716 kb
Host smart-328aaaec-5b43-459b-a735-40ea9ce5e48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009072604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.4009072604
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.689194642
Short name T666
Test name
Test status
Simulation time 117241045 ps
CPU time 2.7 seconds
Started May 14 02:10:19 PM PDT 24
Finished May 14 02:10:25 PM PDT 24
Peak memory 216960 kb
Host smart-577dba85-8a13-4c8b-b879-7cf78a3e2b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689194642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.689194642
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1353401925
Short name T363
Test name
Test status
Simulation time 90931503 ps
CPU time 1.01 seconds
Started May 14 02:10:19 PM PDT 24
Finished May 14 02:10:23 PM PDT 24
Peak memory 216624 kb
Host smart-fd79ba8f-4f59-456a-883f-cf08bfd77a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353401925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1353401925
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.997853655
Short name T304
Test name
Test status
Simulation time 115092060 ps
CPU time 1.54 seconds
Started May 14 02:10:17 PM PDT 24
Finished May 14 02:10:21 PM PDT 24
Peak memory 219816 kb
Host smart-0b3cdc12-6d01-436e-ba04-97eb4e1202b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997853655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.997853655
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.860864834
Short name T617
Test name
Test status
Simulation time 50086351 ps
CPU time 0.98 seconds
Started May 14 02:10:29 PM PDT 24
Finished May 14 02:10:30 PM PDT 24
Peak memory 216588 kb
Host smart-74d50d02-efe4-41c4-8111-6352ab700021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860864834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.860864834
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1126422894
Short name T684
Test name
Test status
Simulation time 24525862 ps
CPU time 1.22 seconds
Started May 14 02:08:35 PM PDT 24
Finished May 14 02:08:39 PM PDT 24
Peak memory 215340 kb
Host smart-58839ddd-775b-4443-a2bd-d97f4426df06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126422894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1126422894
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.2895407229
Short name T135
Test name
Test status
Simulation time 30758904 ps
CPU time 1.07 seconds
Started May 14 02:08:35 PM PDT 24
Finished May 14 02:08:38 PM PDT 24
Peak memory 206220 kb
Host smart-af03f3a0-f211-4b4e-b356-969d453f27a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895407229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2895407229
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.2762138298
Short name T2
Test name
Test status
Simulation time 16917008 ps
CPU time 0.92 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:40 PM PDT 24
Peak memory 216192 kb
Host smart-31c8177a-aba4-4647-848c-0683ec807dd4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762138298 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2762138298
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1119651927
Short name T174
Test name
Test status
Simulation time 53897623 ps
CPU time 1.01 seconds
Started May 14 02:08:34 PM PDT 24
Finished May 14 02:08:36 PM PDT 24
Peak memory 216776 kb
Host smart-188fc59b-559d-43b1-949a-7f20069ef908
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119651927 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1119651927
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.1756171655
Short name T71
Test name
Test status
Simulation time 76077197 ps
CPU time 0.9 seconds
Started May 14 02:08:34 PM PDT 24
Finished May 14 02:08:37 PM PDT 24
Peak memory 217868 kb
Host smart-f5c31ec3-f1c8-41a2-afdf-6f03b1983d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756171655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1756171655
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3657293133
Short name T120
Test name
Test status
Simulation time 232313590 ps
CPU time 3.36 seconds
Started May 14 02:08:22 PM PDT 24
Finished May 14 02:08:28 PM PDT 24
Peak memory 216832 kb
Host smart-5e74ec6a-d39c-403f-88ba-88d79300a542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657293133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3657293133
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.650415755
Short name T507
Test name
Test status
Simulation time 25395255 ps
CPU time 0.96 seconds
Started May 14 02:08:23 PM PDT 24
Finished May 14 02:08:26 PM PDT 24
Peak memory 214912 kb
Host smart-5a6ffdba-ad3d-4dc2-9409-6f7d6a910010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650415755 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.650415755
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1947771131
Short name T536
Test name
Test status
Simulation time 74667763 ps
CPU time 2.08 seconds
Started May 14 02:08:21 PM PDT 24
Finished May 14 02:08:25 PM PDT 24
Peak memory 216688 kb
Host smart-63b7c91f-e0fe-42f3-b741-cf9e8a1f5365
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947771131 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1947771131
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3507967814
Short name T600
Test name
Test status
Simulation time 24196338418 ps
CPU time 529.73 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:17:29 PM PDT 24
Peak memory 217220 kb
Host smart-5cec52e8-3649-4c00-9ecb-13a26acf07fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507967814 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3507967814
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.2998800477
Short name T747
Test name
Test status
Simulation time 158512906 ps
CPU time 1.44 seconds
Started May 14 02:10:18 PM PDT 24
Finished May 14 02:10:22 PM PDT 24
Peak memory 216712 kb
Host smart-13b772fe-e802-4819-ac18-b8e668d05efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998800477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2998800477
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.3824879113
Short name T661
Test name
Test status
Simulation time 57676080 ps
CPU time 1.6 seconds
Started May 14 02:10:18 PM PDT 24
Finished May 14 02:10:23 PM PDT 24
Peak memory 216644 kb
Host smart-75922db5-d23c-4ff3-8bbc-db7806ce7f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824879113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3824879113
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.2791476792
Short name T800
Test name
Test status
Simulation time 33891955 ps
CPU time 1.37 seconds
Started May 14 02:10:22 PM PDT 24
Finished May 14 02:10:25 PM PDT 24
Peak memory 217780 kb
Host smart-62b4670a-980d-466d-9d01-e45d2afd79cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791476792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2791476792
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.3478671611
Short name T571
Test name
Test status
Simulation time 160305914 ps
CPU time 1.47 seconds
Started May 14 02:10:31 PM PDT 24
Finished May 14 02:10:35 PM PDT 24
Peak memory 218180 kb
Host smart-462b16d7-5ae2-4db8-8483-579c4c30e22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478671611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3478671611
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.752712040
Short name T730
Test name
Test status
Simulation time 18311957 ps
CPU time 1.02 seconds
Started May 14 02:10:22 PM PDT 24
Finished May 14 02:10:25 PM PDT 24
Peak memory 216716 kb
Host smart-68ec6d21-6f5f-4563-af73-0c88a5b5f3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752712040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.752712040
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.2850089779
Short name T473
Test name
Test status
Simulation time 29709059 ps
CPU time 1.42 seconds
Started May 14 02:10:18 PM PDT 24
Finished May 14 02:10:22 PM PDT 24
Peak memory 217772 kb
Host smart-63c78c74-ca7b-4ef4-b6be-314b0e2aca8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850089779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2850089779
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.2673061457
Short name T469
Test name
Test status
Simulation time 83680242 ps
CPU time 1.43 seconds
Started May 14 02:10:22 PM PDT 24
Finished May 14 02:10:26 PM PDT 24
Peak memory 218392 kb
Host smart-96c78547-bc2a-44dd-9547-4dc140f7ffb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673061457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2673061457
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.4253954079
Short name T487
Test name
Test status
Simulation time 234373566 ps
CPU time 1.2 seconds
Started May 14 02:10:19 PM PDT 24
Finished May 14 02:10:22 PM PDT 24
Peak memory 216872 kb
Host smart-bb6a27ce-7727-493b-90d4-c73c401f0b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253954079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.4253954079
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.105683807
Short name T606
Test name
Test status
Simulation time 96235302 ps
CPU time 1.55 seconds
Started May 14 02:10:31 PM PDT 24
Finished May 14 02:10:34 PM PDT 24
Peak memory 218348 kb
Host smart-5304484a-e0d4-45b4-8cc1-9679df4c9f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105683807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.105683807
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3969527903
Short name T75
Test name
Test status
Simulation time 73806754 ps
CPU time 1.18 seconds
Started May 14 02:08:35 PM PDT 24
Finished May 14 02:08:39 PM PDT 24
Peak memory 215292 kb
Host smart-913863d3-f4c3-40da-a82b-e765659b35d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969527903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3969527903
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.655593250
Short name T784
Test name
Test status
Simulation time 15357128 ps
CPU time 0.84 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:40 PM PDT 24
Peak memory 206488 kb
Host smart-cd8eb8ba-1da7-49c5-8515-55c42452786f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655593250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.655593250
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2945376978
Short name T351
Test name
Test status
Simulation time 20975817 ps
CPU time 0.89 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:39 PM PDT 24
Peak memory 215644 kb
Host smart-1982b4de-9cf0-4246-af88-f0e2b02dc321
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945376978 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2945376978
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.4052352473
Short name T465
Test name
Test status
Simulation time 32022221 ps
CPU time 1.15 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:40 PM PDT 24
Peak memory 218104 kb
Host smart-1cd70bce-b6d5-489d-a8bd-bb07ca21af69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052352473 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.4052352473
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.33356151
Short name T72
Test name
Test status
Simulation time 19573685 ps
CPU time 1.12 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:40 PM PDT 24
Peak memory 217940 kb
Host smart-c16ece0c-e861-4469-bf04-370c6351d77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33356151 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.33356151
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.153660584
Short name T380
Test name
Test status
Simulation time 43512481 ps
CPU time 1.55 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:41 PM PDT 24
Peak memory 216576 kb
Host smart-81b5337e-bb9f-496d-9f28-7c0b97df965e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153660584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.153660584
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.998885692
Short name T653
Test name
Test status
Simulation time 27618156 ps
CPU time 0.92 seconds
Started May 14 02:08:35 PM PDT 24
Finished May 14 02:08:38 PM PDT 24
Peak memory 215428 kb
Host smart-574ac3de-9a0c-441c-a97d-3da924842861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998885692 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.998885692
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3136669607
Short name T325
Test name
Test status
Simulation time 25639692 ps
CPU time 0.93 seconds
Started May 14 02:08:34 PM PDT 24
Finished May 14 02:08:37 PM PDT 24
Peak memory 214908 kb
Host smart-52937893-0ae6-4439-bbf8-e64b9a478c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136669607 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3136669607
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1379001867
Short name T291
Test name
Test status
Simulation time 171806471 ps
CPU time 3.65 seconds
Started May 14 02:08:37 PM PDT 24
Finished May 14 02:08:44 PM PDT 24
Peak memory 216420 kb
Host smart-bf872be5-e48f-401f-a9d3-1ff8896e998d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379001867 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1379001867
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.504154472
Short name T377
Test name
Test status
Simulation time 20967886786 ps
CPU time 369.28 seconds
Started May 14 02:08:33 PM PDT 24
Finished May 14 02:14:43 PM PDT 24
Peak memory 218372 kb
Host smart-f8fbb09a-735e-4f26-92e8-aa485d14c9b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504154472 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.504154472
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.771830806
Short name T736
Test name
Test status
Simulation time 283692716 ps
CPU time 3.3 seconds
Started May 14 02:10:19 PM PDT 24
Finished May 14 02:10:25 PM PDT 24
Peak memory 219260 kb
Host smart-2c60d666-4f86-4292-aec1-b316bc2e1851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771830806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.771830806
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.925178448
Short name T531
Test name
Test status
Simulation time 26642047 ps
CPU time 1.34 seconds
Started May 14 02:10:20 PM PDT 24
Finished May 14 02:10:24 PM PDT 24
Peak memory 216796 kb
Host smart-99b607e9-ce0b-48da-8953-ce4d64a12abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925178448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.925178448
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.875979758
Short name T362
Test name
Test status
Simulation time 74475604 ps
CPU time 1.15 seconds
Started May 14 02:10:20 PM PDT 24
Finished May 14 02:10:24 PM PDT 24
Peak memory 216944 kb
Host smart-4184807b-e9e4-489a-89ee-30fba2d56c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875979758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.875979758
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.1198416243
Short name T393
Test name
Test status
Simulation time 94076384 ps
CPU time 1.47 seconds
Started May 14 02:10:17 PM PDT 24
Finished May 14 02:10:21 PM PDT 24
Peak memory 218408 kb
Host smart-81ef9ca0-4e4c-40d1-ae23-d95167df1b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198416243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1198416243
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.2180943455
Short name T422
Test name
Test status
Simulation time 76053576 ps
CPU time 2.68 seconds
Started May 14 02:10:18 PM PDT 24
Finished May 14 02:10:24 PM PDT 24
Peak memory 217896 kb
Host smart-f007fb4a-e85b-4974-9a23-b56e4afce525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180943455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2180943455
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.1579148200
Short name T444
Test name
Test status
Simulation time 49581896 ps
CPU time 1.27 seconds
Started May 14 02:10:20 PM PDT 24
Finished May 14 02:10:24 PM PDT 24
Peak memory 216764 kb
Host smart-a30a6af6-ab5e-459f-84ef-df9ab2826529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579148200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1579148200
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.324469588
Short name T360
Test name
Test status
Simulation time 27251593 ps
CPU time 1.18 seconds
Started May 14 02:10:29 PM PDT 24
Finished May 14 02:10:31 PM PDT 24
Peak memory 217068 kb
Host smart-9115bbfe-57b6-4869-a395-7436e7147fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324469588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.324469588
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.1436499980
Short name T357
Test name
Test status
Simulation time 58983348 ps
CPU time 1.25 seconds
Started May 14 02:10:19 PM PDT 24
Finished May 14 02:10:23 PM PDT 24
Peak memory 216696 kb
Host smart-be682832-fffd-4347-a11e-27c2d151289e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436499980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1436499980
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.367489836
Short name T578
Test name
Test status
Simulation time 45403500 ps
CPU time 1.17 seconds
Started May 14 02:10:17 PM PDT 24
Finished May 14 02:10:20 PM PDT 24
Peak memory 214960 kb
Host smart-24f92d39-59d1-45db-9746-546341ed2dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367489836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.367489836
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.4105807864
Short name T704
Test name
Test status
Simulation time 67157865 ps
CPU time 1.15 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:41 PM PDT 24
Peak memory 215264 kb
Host smart-9e48ae49-5015-497a-a3b9-9ecc076ba33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105807864 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.4105807864
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.127194515
Short name T137
Test name
Test status
Simulation time 13332925 ps
CPU time 0.9 seconds
Started May 14 02:08:37 PM PDT 24
Finished May 14 02:08:42 PM PDT 24
Peak memory 206244 kb
Host smart-6957815c-c456-4c6e-ad42-3c5f5df9620b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127194515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.127194515
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.700968394
Short name T359
Test name
Test status
Simulation time 43570304 ps
CPU time 0.87 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:40 PM PDT 24
Peak memory 215644 kb
Host smart-b7a88d5e-ba24-40ba-b4d7-023c502e1dda
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700968394 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.700968394
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1942707000
Short name T53
Test name
Test status
Simulation time 43318852 ps
CPU time 1.26 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:40 PM PDT 24
Peak memory 216460 kb
Host smart-8dace7e6-4f85-4e2a-b2e4-63fb93c12a16
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942707000 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1942707000
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.564208870
Short name T405
Test name
Test status
Simulation time 63110271 ps
CPU time 1.11 seconds
Started May 14 02:08:40 PM PDT 24
Finished May 14 02:08:43 PM PDT 24
Peak memory 218496 kb
Host smart-9862007f-6767-48b4-be88-c6eaca640ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564208870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.564208870
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2556488030
Short name T461
Test name
Test status
Simulation time 46223986 ps
CPU time 1.5 seconds
Started May 14 02:08:34 PM PDT 24
Finished May 14 02:08:37 PM PDT 24
Peak memory 217844 kb
Host smart-b9f08666-b5c8-43a1-9c76-9fffb5c903e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556488030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2556488030
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1891678140
Short name T24
Test name
Test status
Simulation time 32117111 ps
CPU time 0.91 seconds
Started May 14 02:08:37 PM PDT 24
Finished May 14 02:08:41 PM PDT 24
Peak memory 215260 kb
Host smart-5f4da1ec-1150-4017-a802-a1e66ecddfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891678140 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1891678140
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1193014430
Short name T675
Test name
Test status
Simulation time 15576977 ps
CPU time 0.93 seconds
Started May 14 02:08:34 PM PDT 24
Finished May 14 02:08:36 PM PDT 24
Peak memory 214924 kb
Host smart-ac2a27fb-66bd-46c5-87ce-61bc7c05ac7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193014430 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1193014430
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1994493033
Short name T714
Test name
Test status
Simulation time 358881815 ps
CPU time 2.01 seconds
Started May 14 02:08:37 PM PDT 24
Finished May 14 02:08:42 PM PDT 24
Peak memory 216436 kb
Host smart-ca977886-ee32-4d1a-abe8-014699234793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994493033 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1994493033
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_genbits.2454100582
Short name T569
Test name
Test status
Simulation time 30602277 ps
CPU time 1.27 seconds
Started May 14 02:10:19 PM PDT 24
Finished May 14 02:10:23 PM PDT 24
Peak memory 219200 kb
Host smart-bc898262-c57d-4d93-9731-8564c09722e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454100582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2454100582
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.1685717
Short name T767
Test name
Test status
Simulation time 49185899 ps
CPU time 1.53 seconds
Started May 14 02:10:17 PM PDT 24
Finished May 14 02:10:20 PM PDT 24
Peak memory 217812 kb
Host smart-95bc1ae3-0b81-49f4-be9a-58738fa480e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1685717
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.1925453512
Short name T302
Test name
Test status
Simulation time 38467573 ps
CPU time 1.36 seconds
Started May 14 02:10:32 PM PDT 24
Finished May 14 02:10:35 PM PDT 24
Peak memory 219536 kb
Host smart-d270054d-a634-4372-84e8-4c0702ab9fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925453512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1925453512
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.472033817
Short name T510
Test name
Test status
Simulation time 68146329 ps
CPU time 1.1 seconds
Started May 14 02:10:17 PM PDT 24
Finished May 14 02:10:20 PM PDT 24
Peak memory 216628 kb
Host smart-f714198b-2530-43a7-b35c-584ff07c099c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472033817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.472033817
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.3756278265
Short name T842
Test name
Test status
Simulation time 46035332 ps
CPU time 1.89 seconds
Started May 14 02:10:18 PM PDT 24
Finished May 14 02:10:23 PM PDT 24
Peak memory 216676 kb
Host smart-1bee1278-30ec-4b46-b66b-2458efc2d212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756278265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3756278265
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3497083292
Short name T516
Test name
Test status
Simulation time 189381654 ps
CPU time 1.41 seconds
Started May 14 02:10:33 PM PDT 24
Finished May 14 02:10:35 PM PDT 24
Peak memory 218108 kb
Host smart-71e47760-17f5-4379-8976-d5fb6e04bbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497083292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3497083292
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.2734103145
Short name T619
Test name
Test status
Simulation time 46597520 ps
CPU time 1.41 seconds
Started May 14 02:10:31 PM PDT 24
Finished May 14 02:10:33 PM PDT 24
Peak memory 217884 kb
Host smart-f724d4e1-7525-49e5-9393-ade3ff6e5efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734103145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2734103145
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.3223672169
Short name T289
Test name
Test status
Simulation time 106004576 ps
CPU time 2.42 seconds
Started May 14 02:10:32 PM PDT 24
Finished May 14 02:10:36 PM PDT 24
Peak memory 219652 kb
Host smart-ec5829a9-659a-404c-b650-2cfe81c6aaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223672169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3223672169
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.1936316952
Short name T632
Test name
Test status
Simulation time 79089909 ps
CPU time 1.25 seconds
Started May 14 02:10:32 PM PDT 24
Finished May 14 02:10:35 PM PDT 24
Peak memory 219592 kb
Host smart-53da2dac-31ab-47a9-8180-47695ace39b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936316952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1936316952
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.947735663
Short name T776
Test name
Test status
Simulation time 64140980 ps
CPU time 2.22 seconds
Started May 14 02:10:32 PM PDT 24
Finished May 14 02:10:36 PM PDT 24
Peak memory 218088 kb
Host smart-aa8827bb-6905-4c51-841b-6826c0ab656c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947735663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.947735663
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1127480806
Short name T835
Test name
Test status
Simulation time 64808759 ps
CPU time 1.15 seconds
Started May 14 02:08:34 PM PDT 24
Finished May 14 02:08:37 PM PDT 24
Peak memory 215324 kb
Host smart-8b5dd325-784e-45bf-b8fb-de81a45bf7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127480806 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1127480806
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3846104619
Short name T817
Test name
Test status
Simulation time 43351447 ps
CPU time 0.91 seconds
Started May 14 02:08:34 PM PDT 24
Finished May 14 02:08:36 PM PDT 24
Peak memory 206252 kb
Host smart-94e0a638-e949-40c9-a311-507972648e94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846104619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3846104619
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.2119078292
Short name T66
Test name
Test status
Simulation time 16301397 ps
CPU time 0.92 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:40 PM PDT 24
Peak memory 216188 kb
Host smart-d2fd30ea-e1bd-4f99-92f3-28c496bf0556
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119078292 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2119078292
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3286232435
Short name T42
Test name
Test status
Simulation time 71523259 ps
CPU time 0.93 seconds
Started May 14 02:08:39 PM PDT 24
Finished May 14 02:08:43 PM PDT 24
Peak memory 216476 kb
Host smart-125be864-4ac2-4d63-8d71-1aac3e58ccdd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286232435 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3286232435
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.4283017502
Short name T470
Test name
Test status
Simulation time 20588838 ps
CPU time 1.08 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:40 PM PDT 24
Peak memory 218064 kb
Host smart-2ef8b247-6f7b-483e-857b-c90f06f541e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283017502 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.4283017502
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.440620783
Short name T134
Test name
Test status
Simulation time 31013197 ps
CPU time 1.27 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:40 PM PDT 24
Peak memory 216576 kb
Host smart-56402e9c-7612-48a3-bca2-148bc86ffb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440620783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.440620783
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.2080973075
Short name T556
Test name
Test status
Simulation time 34972578 ps
CPU time 0.91 seconds
Started May 14 02:08:37 PM PDT 24
Finished May 14 02:08:41 PM PDT 24
Peak memory 215204 kb
Host smart-78b8ee0e-6d77-4aae-a6f2-b2fcc8587e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080973075 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2080973075
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3295059228
Short name T398
Test name
Test status
Simulation time 30132010 ps
CPU time 1.01 seconds
Started May 14 02:08:37 PM PDT 24
Finished May 14 02:08:41 PM PDT 24
Peak memory 215124 kb
Host smart-53ce21d0-cd57-4f56-8953-51022b46b2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295059228 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3295059228
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.181271929
Short name T454
Test name
Test status
Simulation time 184692953 ps
CPU time 4.31 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:43 PM PDT 24
Peak memory 214972 kb
Host smart-3ace6cca-8ef0-4a61-82ba-45e12c2612b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181271929 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.181271929
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3281114926
Short name T549
Test name
Test status
Simulation time 29000217157 ps
CPU time 623.5 seconds
Started May 14 02:08:38 PM PDT 24
Finished May 14 02:19:05 PM PDT 24
Peak memory 217460 kb
Host smart-29683017-2f25-4834-a7ef-28f0d9b5223e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281114926 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3281114926
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.2268958176
Short name T140
Test name
Test status
Simulation time 88370702 ps
CPU time 1.44 seconds
Started May 14 02:10:31 PM PDT 24
Finished May 14 02:10:33 PM PDT 24
Peak memory 218332 kb
Host smart-ce7a01fc-344e-493c-89f7-7373bfbcb59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268958176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2268958176
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.1536493708
Short name T515
Test name
Test status
Simulation time 887576278 ps
CPU time 7.48 seconds
Started May 14 02:10:32 PM PDT 24
Finished May 14 02:10:41 PM PDT 24
Peak memory 219520 kb
Host smart-cbe5019b-8c3f-4749-87e1-1ba9e0f1bcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536493708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1536493708
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2366164158
Short name T786
Test name
Test status
Simulation time 68212474 ps
CPU time 1.21 seconds
Started May 14 02:10:31 PM PDT 24
Finished May 14 02:10:34 PM PDT 24
Peak memory 218404 kb
Host smart-e9a4d8c6-58e8-4d4b-aa12-4b956656d74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366164158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2366164158
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.3347298088
Short name T687
Test name
Test status
Simulation time 44146910 ps
CPU time 1.89 seconds
Started May 14 02:10:31 PM PDT 24
Finished May 14 02:10:34 PM PDT 24
Peak memory 217936 kb
Host smart-549612cf-0746-4231-bced-3b57f37d4c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347298088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3347298088
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.575320975
Short name T495
Test name
Test status
Simulation time 48366946 ps
CPU time 1.76 seconds
Started May 14 02:10:30 PM PDT 24
Finished May 14 02:10:32 PM PDT 24
Peak memory 217952 kb
Host smart-cdeeec4e-a52f-4c0a-b563-b91876630efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575320975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.575320975
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.1145098803
Short name T669
Test name
Test status
Simulation time 35683815 ps
CPU time 1.56 seconds
Started May 14 02:10:32 PM PDT 24
Finished May 14 02:10:35 PM PDT 24
Peak memory 216704 kb
Host smart-ddf3ccdd-5e02-483e-b4d9-aefd77cadeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145098803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1145098803
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.1539824503
Short name T347
Test name
Test status
Simulation time 37662646 ps
CPU time 1.32 seconds
Started May 14 02:10:35 PM PDT 24
Finished May 14 02:10:37 PM PDT 24
Peak memory 218024 kb
Host smart-7a4ebf27-2a14-4333-ba39-da0fb76a9dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539824503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1539824503
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1100600829
Short name T833
Test name
Test status
Simulation time 45818064 ps
CPU time 1.65 seconds
Started May 14 02:10:31 PM PDT 24
Finished May 14 02:10:35 PM PDT 24
Peak memory 218088 kb
Host smart-b1bfe34c-a35d-4960-bd30-7a75a89b024c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100600829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1100600829
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.3819722970
Short name T122
Test name
Test status
Simulation time 140445475 ps
CPU time 3.21 seconds
Started May 14 02:10:31 PM PDT 24
Finished May 14 02:10:35 PM PDT 24
Peak memory 216964 kb
Host smart-5bb6cdb0-9adb-4237-9659-b4d4986f752a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819722970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3819722970
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.2770776981
Short name T643
Test name
Test status
Simulation time 82048527 ps
CPU time 1.21 seconds
Started May 14 02:08:37 PM PDT 24
Finished May 14 02:08:42 PM PDT 24
Peak memory 215304 kb
Host smart-4e9077d5-0a2e-4f24-b620-2e21367d0323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770776981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2770776981
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3583738547
Short name T596
Test name
Test status
Simulation time 30179971 ps
CPU time 1.05 seconds
Started May 14 02:08:39 PM PDT 24
Finished May 14 02:08:43 PM PDT 24
Peak memory 214484 kb
Host smart-d461d3d2-f50c-4c28-b77a-ef81c58c4ac5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583738547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3583738547
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1821448843
Short name T625
Test name
Test status
Simulation time 78708174 ps
CPU time 1.15 seconds
Started May 14 02:08:35 PM PDT 24
Finished May 14 02:08:39 PM PDT 24
Peak memory 217936 kb
Host smart-dd7f0377-11dc-4652-837a-6fc7c82b2274
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821448843 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1821448843
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.3801954524
Short name T4
Test name
Test status
Simulation time 33327928 ps
CPU time 1.03 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:40 PM PDT 24
Peak memory 218392 kb
Host smart-11769c7c-a21a-477d-aa45-4c26cb9fdbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801954524 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3801954524
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3046174085
Short name T485
Test name
Test status
Simulation time 49359289 ps
CPU time 1.47 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:40 PM PDT 24
Peak memory 217772 kb
Host smart-bd519c2f-325e-4082-b5af-0dd77d922f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046174085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3046174085
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.951037746
Short name T806
Test name
Test status
Simulation time 29637965 ps
CPU time 0.91 seconds
Started May 14 02:08:37 PM PDT 24
Finished May 14 02:08:41 PM PDT 24
Peak memory 215060 kb
Host smart-10993e15-98ba-4ec2-a645-e9f73145c1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951037746 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.951037746
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2167037815
Short name T459
Test name
Test status
Simulation time 38003875 ps
CPU time 0.82 seconds
Started May 14 02:08:34 PM PDT 24
Finished May 14 02:08:36 PM PDT 24
Peak memory 214828 kb
Host smart-3a2353e5-90ac-45a6-b3f5-35321b250199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167037815 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2167037815
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.129733339
Short name T209
Test name
Test status
Simulation time 354022648 ps
CPU time 3.74 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:42 PM PDT 24
Peak memory 216552 kb
Host smart-4fccba24-1f49-4ed2-b8f6-54ed8bf642c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129733339 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.129733339
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1300852989
Short name T530
Test name
Test status
Simulation time 333491477578 ps
CPU time 1970.68 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:41:30 PM PDT 24
Peak memory 225308 kb
Host smart-83577837-28ce-456c-b3ce-770b9bdff523
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300852989 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1300852989
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.1742842599
Short name T285
Test name
Test status
Simulation time 57726578 ps
CPU time 1.04 seconds
Started May 14 02:10:32 PM PDT 24
Finished May 14 02:10:35 PM PDT 24
Peak memory 216764 kb
Host smart-b2f8b3ad-c05e-43f4-acfc-a7afe91ba397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742842599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1742842599
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.1247385003
Short name T551
Test name
Test status
Simulation time 37982129 ps
CPU time 1.65 seconds
Started May 14 02:10:32 PM PDT 24
Finished May 14 02:10:35 PM PDT 24
Peak memory 218048 kb
Host smart-c9b544a8-d857-4b93-b8f1-d224f577d81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247385003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1247385003
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.139907052
Short name T379
Test name
Test status
Simulation time 67327893 ps
CPU time 1.12 seconds
Started May 14 02:10:35 PM PDT 24
Finished May 14 02:10:37 PM PDT 24
Peak memory 216736 kb
Host smart-7ae7f736-78de-4a12-bf43-f35a8db5d179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139907052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.139907052
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.2003818425
Short name T385
Test name
Test status
Simulation time 53564533 ps
CPU time 1.05 seconds
Started May 14 02:10:32 PM PDT 24
Finished May 14 02:10:34 PM PDT 24
Peak memory 218068 kb
Host smart-57bdca45-69b6-4257-aba9-409189e78968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003818425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2003818425
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.2738160300
Short name T744
Test name
Test status
Simulation time 48999778 ps
CPU time 1.31 seconds
Started May 14 02:10:31 PM PDT 24
Finished May 14 02:10:35 PM PDT 24
Peak memory 216608 kb
Host smart-e6fd301f-f4bd-4556-9e00-961ad106fa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738160300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2738160300
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.3998676958
Short name T130
Test name
Test status
Simulation time 68077904 ps
CPU time 1.62 seconds
Started May 14 02:10:39 PM PDT 24
Finished May 14 02:10:42 PM PDT 24
Peak memory 218128 kb
Host smart-919bd74d-df2c-423f-8211-d27d04a6be6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998676958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3998676958
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.3507771607
Short name T805
Test name
Test status
Simulation time 82286784 ps
CPU time 1.55 seconds
Started May 14 02:10:40 PM PDT 24
Finished May 14 02:10:43 PM PDT 24
Peak memory 218540 kb
Host smart-111c1f62-82aa-432e-92f7-ce69172c167b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507771607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3507771607
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.1014548564
Short name T391
Test name
Test status
Simulation time 100749243 ps
CPU time 1.06 seconds
Started May 14 02:10:42 PM PDT 24
Finished May 14 02:10:44 PM PDT 24
Peak memory 216620 kb
Host smart-b6e9d559-8e96-47b3-974c-7ab7ea5e4deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014548564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1014548564
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert_test.3149394055
Short name T689
Test name
Test status
Simulation time 49838362 ps
CPU time 0.82 seconds
Started May 14 02:08:37 PM PDT 24
Finished May 14 02:08:41 PM PDT 24
Peak memory 206544 kb
Host smart-b6fca0b9-4fe3-410c-8ddf-2d8ae9641783
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149394055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3149394055
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2713346127
Short name T455
Test name
Test status
Simulation time 27459081 ps
CPU time 0.82 seconds
Started May 14 02:08:37 PM PDT 24
Finished May 14 02:08:41 PM PDT 24
Peak memory 215164 kb
Host smart-a5f46bd1-d06f-4d03-98fa-94b29ff6fbe1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713346127 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2713346127
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.1184752276
Short name T87
Test name
Test status
Simulation time 36673492 ps
CPU time 0.89 seconds
Started May 14 02:08:37 PM PDT 24
Finished May 14 02:08:41 PM PDT 24
Peak memory 217740 kb
Host smart-34f433ce-6dd3-43d1-8224-a5f3ab6ac71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184752276 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1184752276
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.290146447
Short name T127
Test name
Test status
Simulation time 60301218 ps
CPU time 1.07 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:40 PM PDT 24
Peak memory 219468 kb
Host smart-02f3348d-c2e2-4ad2-8927-80e5edf51a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290146447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.290146447
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_smoke.3366928860
Short name T635
Test name
Test status
Simulation time 49204608 ps
CPU time 0.92 seconds
Started May 14 02:08:37 PM PDT 24
Finished May 14 02:08:41 PM PDT 24
Peak memory 214876 kb
Host smart-fd11bcb3-06bd-4559-ae02-73ede9c569a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366928860 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3366928860
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.4111855462
Short name T211
Test name
Test status
Simulation time 66324915 ps
CPU time 1.77 seconds
Started May 14 02:08:40 PM PDT 24
Finished May 14 02:08:44 PM PDT 24
Peak memory 206732 kb
Host smart-71dcfe7b-3230-42e9-bfd7-9bc8788bfec8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111855462 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.4111855462
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.4054994449
Short name T610
Test name
Test status
Simulation time 128830161405 ps
CPU time 1413.78 seconds
Started May 14 02:08:39 PM PDT 24
Finished May 14 02:32:16 PM PDT 24
Peak memory 224020 kb
Host smart-0e6925cb-d10f-46df-b1db-fc81d6845dbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054994449 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.4054994449
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.4146547664
Short name T609
Test name
Test status
Simulation time 291248377 ps
CPU time 4.17 seconds
Started May 14 02:10:40 PM PDT 24
Finished May 14 02:10:46 PM PDT 24
Peak memory 219716 kb
Host smart-e297b1c0-6add-4c3b-ba36-f26f9f64bb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146547664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.4146547664
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.975123730
Short name T11
Test name
Test status
Simulation time 86108640 ps
CPU time 1.31 seconds
Started May 14 02:10:42 PM PDT 24
Finished May 14 02:10:45 PM PDT 24
Peak memory 218104 kb
Host smart-fd6d073b-fa80-401d-b6f5-ba18b5015466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975123730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.975123730
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.3693938431
Short name T652
Test name
Test status
Simulation time 67698091 ps
CPU time 1.63 seconds
Started May 14 02:10:42 PM PDT 24
Finished May 14 02:10:45 PM PDT 24
Peak memory 218052 kb
Host smart-0b8ca84d-9adb-4bd9-8b84-5da5cfdfc2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693938431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3693938431
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.1592540070
Short name T492
Test name
Test status
Simulation time 114279779 ps
CPU time 1.68 seconds
Started May 14 02:10:42 PM PDT 24
Finished May 14 02:10:45 PM PDT 24
Peak memory 218472 kb
Host smart-8353fc86-7b46-4f9c-9173-2562423bc238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592540070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1592540070
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.561793845
Short name T517
Test name
Test status
Simulation time 31103584 ps
CPU time 1.51 seconds
Started May 14 02:10:41 PM PDT 24
Finished May 14 02:10:44 PM PDT 24
Peak memory 219360 kb
Host smart-403067cd-a1d4-484f-8732-baaae099075d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561793845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.561793845
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.3963723370
Short name T782
Test name
Test status
Simulation time 290377155 ps
CPU time 1.27 seconds
Started May 14 02:10:41 PM PDT 24
Finished May 14 02:10:44 PM PDT 24
Peak memory 219300 kb
Host smart-40cba762-4555-489c-8a76-1b58e12aaa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963723370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3963723370
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.3535356109
Short name T488
Test name
Test status
Simulation time 95411015 ps
CPU time 1.17 seconds
Started May 14 02:10:39 PM PDT 24
Finished May 14 02:10:41 PM PDT 24
Peak memory 216672 kb
Host smart-d3799b3c-0103-4e5d-bd38-188c6d7abe93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535356109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3535356109
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.1012760041
Short name T761
Test name
Test status
Simulation time 233339496 ps
CPU time 3.35 seconds
Started May 14 02:10:40 PM PDT 24
Finished May 14 02:10:45 PM PDT 24
Peak memory 219800 kb
Host smart-db919b2e-689f-4d7d-9121-c00df8b0eb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012760041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1012760041
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.158895957
Short name T680
Test name
Test status
Simulation time 34958482 ps
CPU time 1.26 seconds
Started May 14 02:10:39 PM PDT 24
Finished May 14 02:10:41 PM PDT 24
Peak memory 216788 kb
Host smart-4ba6588d-31da-4b22-aa39-d383e32b71df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158895957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.158895957
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.2652173673
Short name T520
Test name
Test status
Simulation time 92814874 ps
CPU time 1.34 seconds
Started May 14 02:10:43 PM PDT 24
Finished May 14 02:10:46 PM PDT 24
Peak memory 218180 kb
Host smart-3056133b-1ca9-4dd7-837c-822ad13ecb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652173673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2652173673
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1427984388
Short name T184
Test name
Test status
Simulation time 48364188 ps
CPU time 1.2 seconds
Started May 14 02:07:50 PM PDT 24
Finished May 14 02:07:52 PM PDT 24
Peak memory 215336 kb
Host smart-906d0e87-80b8-4aac-be04-2c67fd7ba0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427984388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1427984388
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2434826767
Short name T381
Test name
Test status
Simulation time 29167597 ps
CPU time 0.96 seconds
Started May 14 02:07:47 PM PDT 24
Finished May 14 02:07:49 PM PDT 24
Peak memory 206264 kb
Host smart-f18971e5-e403-482f-9177-ca9d7eed8eed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434826767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2434826767
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1376976141
Short name T342
Test name
Test status
Simulation time 18492035 ps
CPU time 0.84 seconds
Started May 14 02:07:51 PM PDT 24
Finished May 14 02:07:52 PM PDT 24
Peak memory 215620 kb
Host smart-2c5c174f-09b5-4ec7-9042-44afa90769a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376976141 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1376976141
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.801803303
Short name T622
Test name
Test status
Simulation time 68189068 ps
CPU time 1.23 seconds
Started May 14 02:07:46 PM PDT 24
Finished May 14 02:07:48 PM PDT 24
Peak memory 216520 kb
Host smart-270b93e9-9a84-42eb-9a9a-df1ea7445b51
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801803303 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.801803303
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.2350650172
Short name T165
Test name
Test status
Simulation time 28017695 ps
CPU time 1.3 seconds
Started May 14 02:07:47 PM PDT 24
Finished May 14 02:07:50 PM PDT 24
Peak memory 219472 kb
Host smart-49d79f11-eccc-4296-98a0-4863834d8b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350650172 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2350650172
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1148790874
Short name T154
Test name
Test status
Simulation time 55167064 ps
CPU time 2.15 seconds
Started May 14 02:07:47 PM PDT 24
Finished May 14 02:07:51 PM PDT 24
Peak memory 216872 kb
Host smart-022500cd-b6f0-4786-9fbe-c5f45c6637ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148790874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1148790874
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3214026004
Short name T113
Test name
Test status
Simulation time 43367705 ps
CPU time 0.88 seconds
Started May 14 02:07:49 PM PDT 24
Finished May 14 02:07:51 PM PDT 24
Peak memory 215248 kb
Host smart-f49a0403-9d00-4f6b-b02c-37ff99a524ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214026004 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3214026004
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2891923216
Short name T264
Test name
Test status
Simulation time 18027162 ps
CPU time 1.05 seconds
Started May 14 02:07:48 PM PDT 24
Finished May 14 02:07:50 PM PDT 24
Peak memory 206812 kb
Host smart-6e1d3233-e707-4836-b737-d5eb66e4032b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891923216 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2891923216
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1423806544
Short name T132
Test name
Test status
Simulation time 469404724 ps
CPU time 4.6 seconds
Started May 14 02:07:46 PM PDT 24
Finished May 14 02:07:52 PM PDT 24
Peak memory 236652 kb
Host smart-7a59185c-f4a9-449f-832c-b38ef2bae182
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423806544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1423806544
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.2942669501
Short name T607
Test name
Test status
Simulation time 48192980 ps
CPU time 0.91 seconds
Started May 14 02:07:47 PM PDT 24
Finished May 14 02:07:49 PM PDT 24
Peak memory 214964 kb
Host smart-336102dd-bc28-4184-b18f-7185526a41a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942669501 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2942669501
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2249155667
Short name T823
Test name
Test status
Simulation time 1063068006 ps
CPU time 5.78 seconds
Started May 14 02:07:50 PM PDT 24
Finished May 14 02:07:56 PM PDT 24
Peak memory 216732 kb
Host smart-5a90de0a-8078-49fb-bb91-9fa56e6ca740
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249155667 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2249155667
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2296138318
Short name T662
Test name
Test status
Simulation time 220128312415 ps
CPU time 1539.59 seconds
Started May 14 02:07:47 PM PDT 24
Finished May 14 02:33:28 PM PDT 24
Peak memory 225748 kb
Host smart-31a479dd-9435-4e64-bbfe-afc44d74e85a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296138318 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2296138318
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert_test.642391815
Short name T547
Test name
Test status
Simulation time 29343171 ps
CPU time 0.91 seconds
Started May 14 02:08:47 PM PDT 24
Finished May 14 02:08:52 PM PDT 24
Peak memory 215120 kb
Host smart-dca2737b-401f-4923-97af-359a94630a18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642391815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.642391815
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.28506938
Short name T40
Test name
Test status
Simulation time 26717773 ps
CPU time 1.15 seconds
Started May 14 02:08:48 PM PDT 24
Finished May 14 02:08:54 PM PDT 24
Peak memory 219300 kb
Host smart-598f6554-2978-4ed2-a531-62c62222801f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28506938 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_dis
able_auto_req_mode.28506938
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2944223112
Short name T506
Test name
Test status
Simulation time 24591914 ps
CPU time 1.01 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:39 PM PDT 24
Peak memory 218260 kb
Host smart-ccfd1cc9-cb35-44f9-abad-979cf04df911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944223112 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2944223112
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3761998963
Short name T474
Test name
Test status
Simulation time 74364677 ps
CPU time 1.24 seconds
Started May 14 02:08:34 PM PDT 24
Finished May 14 02:08:37 PM PDT 24
Peak memory 219416 kb
Host smart-f0ac153f-0027-4b0e-beea-4ebd3ed41ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761998963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3761998963
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3187072245
Short name T750
Test name
Test status
Simulation time 22725414 ps
CPU time 1.23 seconds
Started May 14 02:08:37 PM PDT 24
Finished May 14 02:08:42 PM PDT 24
Peak memory 223588 kb
Host smart-d323d2d3-ccf3-48f1-809c-b0d448ee721f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187072245 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3187072245
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.984651296
Short name T306
Test name
Test status
Simulation time 28306737 ps
CPU time 0.99 seconds
Started May 14 02:08:38 PM PDT 24
Finished May 14 02:08:42 PM PDT 24
Peak memory 214972 kb
Host smart-a887457b-f616-40f2-9fac-f68bb8f0d456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984651296 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.984651296
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2823121410
Short name T505
Test name
Test status
Simulation time 485254250 ps
CPU time 5.61 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:08:45 PM PDT 24
Peak memory 216508 kb
Host smart-2bec5912-aa35-437b-92bf-ef5e07d54bfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823121410 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2823121410
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1941336446
Short name T638
Test name
Test status
Simulation time 134721788995 ps
CPU time 686.38 seconds
Started May 14 02:08:36 PM PDT 24
Finished May 14 02:20:06 PM PDT 24
Peak memory 223336 kb
Host smart-1053c9f4-f45f-415d-89d4-f4909a3f27ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941336446 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1941336446
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2936026233
Short name T332
Test name
Test status
Simulation time 49142014 ps
CPU time 1.46 seconds
Started May 14 02:10:40 PM PDT 24
Finished May 14 02:10:44 PM PDT 24
Peak memory 218056 kb
Host smart-601466bb-8940-4ad9-8f65-71448b7df873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936026233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2936026233
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.735684772
Short name T276
Test name
Test status
Simulation time 182204439 ps
CPU time 1.43 seconds
Started May 14 02:10:43 PM PDT 24
Finished May 14 02:10:46 PM PDT 24
Peak memory 218316 kb
Host smart-831c64db-9006-4af4-acee-4ad2c85a42f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735684772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.735684772
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.880658798
Short name T104
Test name
Test status
Simulation time 44419444 ps
CPU time 1.37 seconds
Started May 14 02:10:44 PM PDT 24
Finished May 14 02:10:48 PM PDT 24
Peak memory 216596 kb
Host smart-931246f2-0bc1-4a0a-b048-1a19b16ed452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880658798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.880658798
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.4216495556
Short name T288
Test name
Test status
Simulation time 45085571 ps
CPU time 1.9 seconds
Started May 14 02:10:42 PM PDT 24
Finished May 14 02:10:46 PM PDT 24
Peak memory 217740 kb
Host smart-571abd81-98e4-4820-b8a7-152a1069fed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216495556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.4216495556
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.4073929825
Short name T297
Test name
Test status
Simulation time 48017693 ps
CPU time 1.28 seconds
Started May 14 02:10:44 PM PDT 24
Finished May 14 02:10:48 PM PDT 24
Peak memory 217900 kb
Host smart-b5134e82-0c53-4e84-a415-be358ab56724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073929825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.4073929825
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.255252850
Short name T636
Test name
Test status
Simulation time 29693978 ps
CPU time 1.03 seconds
Started May 14 02:10:44 PM PDT 24
Finished May 14 02:10:47 PM PDT 24
Peak memory 216712 kb
Host smart-a79feaee-8a48-4eb9-a114-f0db2f6a19da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255252850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.255252850
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.334311205
Short name T278
Test name
Test status
Simulation time 296210076 ps
CPU time 3.2 seconds
Started May 14 02:10:42 PM PDT 24
Finished May 14 02:10:47 PM PDT 24
Peak memory 219016 kb
Host smart-f4d74300-46f4-43a9-ba01-ab37fc650fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334311205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.334311205
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2989408969
Short name T681
Test name
Test status
Simulation time 99912827 ps
CPU time 1.12 seconds
Started May 14 02:10:43 PM PDT 24
Finished May 14 02:10:46 PM PDT 24
Peak memory 216852 kb
Host smart-a7f9d7cb-f77b-40a1-9c45-526d97f29b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989408969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2989408969
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3174736911
Short name T449
Test name
Test status
Simulation time 243644890 ps
CPU time 3.96 seconds
Started May 14 02:10:41 PM PDT 24
Finished May 14 02:10:47 PM PDT 24
Peak memory 219928 kb
Host smart-7d7d0115-a3af-4d0d-853d-9a41e1fcb2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174736911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3174736911
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.890900044
Short name T640
Test name
Test status
Simulation time 348093096 ps
CPU time 1.49 seconds
Started May 14 02:08:46 PM PDT 24
Finished May 14 02:08:51 PM PDT 24
Peak memory 215304 kb
Host smart-23dcfff1-62ae-457e-abfc-febf0405ca34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890900044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.890900044
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2524159405
Short name T543
Test name
Test status
Simulation time 56397216 ps
CPU time 0.95 seconds
Started May 14 02:08:48 PM PDT 24
Finished May 14 02:08:53 PM PDT 24
Peak memory 206264 kb
Host smart-bb255148-4336-49b0-b83c-25c02e47fefb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524159405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2524159405
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2842640422
Short name T611
Test name
Test status
Simulation time 88375926 ps
CPU time 0.87 seconds
Started May 14 02:08:47 PM PDT 24
Finished May 14 02:08:51 PM PDT 24
Peak memory 215632 kb
Host smart-99765a9a-481a-4889-aaef-2bd4e596e459
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842640422 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2842640422
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2227634052
Short name T478
Test name
Test status
Simulation time 33836503 ps
CPU time 1.29 seconds
Started May 14 02:08:46 PM PDT 24
Finished May 14 02:08:49 PM PDT 24
Peak memory 219256 kb
Host smart-e41a0729-8e45-445f-870c-d604c1457e14
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227634052 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2227634052
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.2515030898
Short name T27
Test name
Test status
Simulation time 25814342 ps
CPU time 1.22 seconds
Started May 14 02:08:47 PM PDT 24
Finished May 14 02:08:52 PM PDT 24
Peak memory 220308 kb
Host smart-1fcd7afb-9324-48db-b10f-b0f955ca45b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515030898 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2515030898
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3665049334
Short name T657
Test name
Test status
Simulation time 53417609 ps
CPU time 1.4 seconds
Started May 14 02:08:47 PM PDT 24
Finished May 14 02:08:51 PM PDT 24
Peak memory 217896 kb
Host smart-51e742b0-ac46-41f9-912f-39ee3329df2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665049334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3665049334
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.630885353
Short name T100
Test name
Test status
Simulation time 33355314 ps
CPU time 0.86 seconds
Started May 14 02:08:47 PM PDT 24
Finished May 14 02:08:52 PM PDT 24
Peak memory 215168 kb
Host smart-6062b8ce-3b92-4db1-ba6c-8bd38e82fb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630885353 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.630885353
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3007606694
Short name T523
Test name
Test status
Simulation time 46901611 ps
CPU time 0.91 seconds
Started May 14 02:08:47 PM PDT 24
Finished May 14 02:08:52 PM PDT 24
Peak memory 214924 kb
Host smart-31738d9e-844f-46d4-bc28-0eb5fdd5e7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007606694 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3007606694
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3671323403
Short name T344
Test name
Test status
Simulation time 2953366996 ps
CPU time 5.05 seconds
Started May 14 02:08:49 PM PDT 24
Finished May 14 02:08:59 PM PDT 24
Peak memory 216908 kb
Host smart-d0d0666e-b3cf-4ae8-9eb1-6c9283f90d62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671323403 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3671323403
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3964120625
Short name T374
Test name
Test status
Simulation time 222540629030 ps
CPU time 1143.31 seconds
Started May 14 02:08:51 PM PDT 24
Finished May 14 02:27:59 PM PDT 24
Peak memory 221336 kb
Host smart-f3653918-c04b-4bd4-ae90-ccd0e3d8dcd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964120625 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3964120625
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1936319441
Short name T316
Test name
Test status
Simulation time 41185205 ps
CPU time 1.28 seconds
Started May 14 02:10:47 PM PDT 24
Finished May 14 02:10:52 PM PDT 24
Peak memory 219324 kb
Host smart-fa3f54a4-0ade-4e93-a961-3a67cbcc9aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936319441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1936319441
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1085376807
Short name T429
Test name
Test status
Simulation time 61161343 ps
CPU time 1.15 seconds
Started May 14 02:10:41 PM PDT 24
Finished May 14 02:10:43 PM PDT 24
Peak memory 215040 kb
Host smart-bcbd6867-382d-4b45-8399-52d868df408f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085376807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1085376807
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2545200246
Short name T327
Test name
Test status
Simulation time 36841205 ps
CPU time 1.13 seconds
Started May 14 02:10:47 PM PDT 24
Finished May 14 02:10:51 PM PDT 24
Peak memory 216588 kb
Host smart-784c6473-1a20-480b-a61a-25a57b003992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545200246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2545200246
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1648128557
Short name T779
Test name
Test status
Simulation time 234658206 ps
CPU time 2.4 seconds
Started May 14 02:10:40 PM PDT 24
Finished May 14 02:10:44 PM PDT 24
Peak memory 219404 kb
Host smart-4de6651c-2245-4ff8-8db5-ae1d01ec9cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648128557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1648128557
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3371660841
Short name T580
Test name
Test status
Simulation time 49255583 ps
CPU time 1.6 seconds
Started May 14 02:10:46 PM PDT 24
Finished May 14 02:10:51 PM PDT 24
Peak memory 217848 kb
Host smart-3773b709-7a7e-46ab-a2c2-0c7356b01516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371660841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3371660841
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.904109539
Short name T745
Test name
Test status
Simulation time 76130652 ps
CPU time 1.16 seconds
Started May 14 02:10:40 PM PDT 24
Finished May 14 02:10:43 PM PDT 24
Peak memory 216852 kb
Host smart-550dd9cc-30aa-47fa-bda3-7516eab46d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904109539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.904109539
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1530810795
Short name T269
Test name
Test status
Simulation time 50842767 ps
CPU time 1.23 seconds
Started May 14 02:10:47 PM PDT 24
Finished May 14 02:10:51 PM PDT 24
Peak memory 217840 kb
Host smart-338dbdb6-a447-459f-aea2-409a187374ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530810795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1530810795
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1148612474
Short name T644
Test name
Test status
Simulation time 24547794 ps
CPU time 1.23 seconds
Started May 14 02:10:46 PM PDT 24
Finished May 14 02:10:49 PM PDT 24
Peak memory 218940 kb
Host smart-e6b01507-f1eb-45bf-8c7a-cd876f492f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148612474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1148612474
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.941713789
Short name T414
Test name
Test status
Simulation time 45798549 ps
CPU time 1.64 seconds
Started May 14 02:10:48 PM PDT 24
Finished May 14 02:10:53 PM PDT 24
Peak memory 214960 kb
Host smart-d61ff666-8dca-4306-a0b8-e163503c0b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941713789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.941713789
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3246530148
Short name T770
Test name
Test status
Simulation time 44862596 ps
CPU time 1.18 seconds
Started May 14 02:08:47 PM PDT 24
Finished May 14 02:08:52 PM PDT 24
Peak memory 215360 kb
Host smart-2b3ce67b-5456-428e-b063-305762aade53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246530148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3246530148
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3137668156
Short name T788
Test name
Test status
Simulation time 20426729 ps
CPU time 0.85 seconds
Started May 14 02:08:45 PM PDT 24
Finished May 14 02:08:48 PM PDT 24
Peak memory 206168 kb
Host smart-1b8dc1c7-e372-437c-91ae-2501de9ec81b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137668156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3137668156
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3018408484
Short name T187
Test name
Test status
Simulation time 63807700 ps
CPU time 0.92 seconds
Started May 14 02:08:46 PM PDT 24
Finished May 14 02:08:50 PM PDT 24
Peak memory 215068 kb
Host smart-9957c11d-131b-4028-bd43-0f4faaf57154
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018408484 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3018408484
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2497704952
Short name T497
Test name
Test status
Simulation time 26833996 ps
CPU time 1.11 seconds
Started May 14 02:08:48 PM PDT 24
Finished May 14 02:08:54 PM PDT 24
Peak memory 219260 kb
Host smart-6c8fa22c-5803-4c23-aac5-c42a845290c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497704952 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2497704952
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2490114893
Short name T73
Test name
Test status
Simulation time 21679062 ps
CPU time 1.05 seconds
Started May 14 02:08:48 PM PDT 24
Finished May 14 02:08:54 PM PDT 24
Peak memory 223416 kb
Host smart-ce09074d-0d67-4e1e-9ff6-31f324feca87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490114893 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2490114893
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2794849576
Short name T618
Test name
Test status
Simulation time 52825961 ps
CPU time 1.59 seconds
Started May 14 02:08:45 PM PDT 24
Finished May 14 02:08:49 PM PDT 24
Peak memory 217928 kb
Host smart-1cb95405-9e6d-42ee-bfc4-04fc9a87e28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794849576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2794849576
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1389790748
Short name T126
Test name
Test status
Simulation time 26237902 ps
CPU time 1.27 seconds
Started May 14 02:08:47 PM PDT 24
Finished May 14 02:08:51 PM PDT 24
Peak memory 223520 kb
Host smart-c3949133-7661-445a-b65e-a0a3c8f85e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389790748 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1389790748
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2206107536
Short name T466
Test name
Test status
Simulation time 15406550 ps
CPU time 0.99 seconds
Started May 14 02:08:48 PM PDT 24
Finished May 14 02:08:53 PM PDT 24
Peak memory 214936 kb
Host smart-9f033bdd-82cb-42df-96ba-19fcd544fef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206107536 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2206107536
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2504387846
Short name T195
Test name
Test status
Simulation time 102658785140 ps
CPU time 1175.89 seconds
Started May 14 02:08:46 PM PDT 24
Finished May 14 02:28:24 PM PDT 24
Peak memory 222300 kb
Host smart-16cc0f1b-93c4-4d9a-9306-6bfa29df5e1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504387846 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2504387846
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1038702075
Short name T372
Test name
Test status
Simulation time 72581215 ps
CPU time 1.08 seconds
Started May 14 02:10:48 PM PDT 24
Finished May 14 02:10:52 PM PDT 24
Peak memory 217912 kb
Host smart-ce3a0512-cb6d-4ec7-a4ee-9c57fbe1b373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038702075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1038702075
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2595166289
Short name T450
Test name
Test status
Simulation time 46987673 ps
CPU time 1.03 seconds
Started May 14 02:10:43 PM PDT 24
Finished May 14 02:10:46 PM PDT 24
Peak memory 219100 kb
Host smart-c9c60ef5-ee82-4d47-ab96-4208e85b5d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595166289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2595166289
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1854598593
Short name T740
Test name
Test status
Simulation time 145027836 ps
CPU time 1.69 seconds
Started May 14 02:10:46 PM PDT 24
Finished May 14 02:10:52 PM PDT 24
Peak memory 218188 kb
Host smart-8f726a17-936d-4d15-9511-43a9a2b0d0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854598593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1854598593
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2091423601
Short name T667
Test name
Test status
Simulation time 42586716 ps
CPU time 1.72 seconds
Started May 14 02:10:48 PM PDT 24
Finished May 14 02:10:54 PM PDT 24
Peak memory 218052 kb
Host smart-f6c24ac9-2a06-4c73-a188-7057e6e1565d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091423601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2091423601
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1722338045
Short name T307
Test name
Test status
Simulation time 38518275 ps
CPU time 1.51 seconds
Started May 14 02:10:46 PM PDT 24
Finished May 14 02:10:50 PM PDT 24
Peak memory 219388 kb
Host smart-cb058410-b40c-4017-89d9-92ca0c990dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722338045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1722338045
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3292695214
Short name T738
Test name
Test status
Simulation time 66937395 ps
CPU time 1.32 seconds
Started May 14 02:10:44 PM PDT 24
Finished May 14 02:10:47 PM PDT 24
Peak memory 218152 kb
Host smart-dca9ee6e-7178-45ac-a04c-1a763bf7a388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292695214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3292695214
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1090518961
Short name T94
Test name
Test status
Simulation time 28235344 ps
CPU time 1.36 seconds
Started May 14 02:10:48 PM PDT 24
Finished May 14 02:10:54 PM PDT 24
Peak memory 217960 kb
Host smart-b38d698f-06d6-4931-bba5-2de61df1d72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090518961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1090518961
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2197550078
Short name T314
Test name
Test status
Simulation time 178548591 ps
CPU time 1.78 seconds
Started May 14 02:10:44 PM PDT 24
Finished May 14 02:10:47 PM PDT 24
Peak memory 218172 kb
Host smart-f4203a69-8fbd-4fcd-b88f-33bfde479734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197550078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2197550078
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3590046013
Short name T518
Test name
Test status
Simulation time 41369992 ps
CPU time 1.31 seconds
Started May 14 02:10:47 PM PDT 24
Finished May 14 02:10:52 PM PDT 24
Peak memory 216932 kb
Host smart-eaeded51-0aa4-4a29-b76f-7fbf2a331780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590046013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3590046013
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1800725149
Short name T339
Test name
Test status
Simulation time 61701956 ps
CPU time 1.42 seconds
Started May 14 02:10:45 PM PDT 24
Finished May 14 02:10:49 PM PDT 24
Peak memory 218220 kb
Host smart-e7add504-798a-4d1b-9783-22bc356eb8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800725149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1800725149
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3595638195
Short name T250
Test name
Test status
Simulation time 26941216 ps
CPU time 1.34 seconds
Started May 14 02:08:47 PM PDT 24
Finished May 14 02:08:53 PM PDT 24
Peak memory 215344 kb
Host smart-c9f213a8-eef1-403d-b6a7-9cbede7788dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595638195 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3595638195
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3222253171
Short name T584
Test name
Test status
Simulation time 38729685 ps
CPU time 0.81 seconds
Started May 14 02:08:50 PM PDT 24
Finished May 14 02:08:55 PM PDT 24
Peak memory 206536 kb
Host smart-83a3aeec-a5d1-45a3-953a-359bfe792907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222253171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3222253171
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.924244410
Short name T534
Test name
Test status
Simulation time 33270320 ps
CPU time 0.86 seconds
Started May 14 02:08:48 PM PDT 24
Finished May 14 02:08:53 PM PDT 24
Peak memory 215144 kb
Host smart-dc5d1177-fe67-41df-be65-2a8e8a8ef7c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924244410 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.924244410
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.526021405
Short name T559
Test name
Test status
Simulation time 26373865 ps
CPU time 1.39 seconds
Started May 14 02:08:50 PM PDT 24
Finished May 14 02:08:56 PM PDT 24
Peak memory 216720 kb
Host smart-b2bf3ede-7686-4965-a84f-2be206414e04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526021405 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.526021405
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1986650242
Short name T52
Test name
Test status
Simulation time 26747780 ps
CPU time 1.12 seconds
Started May 14 02:08:49 PM PDT 24
Finished May 14 02:08:54 PM PDT 24
Peak memory 229124 kb
Host smart-9ea81937-6883-4b47-8f5d-b2206936127d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986650242 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1986650242
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2851830233
Short name T502
Test name
Test status
Simulation time 43835680 ps
CPU time 1.66 seconds
Started May 14 02:08:44 PM PDT 24
Finished May 14 02:08:47 PM PDT 24
Peak memory 217996 kb
Host smart-cd63959d-12f8-4c8c-b537-fc592d00bea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851830233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2851830233
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.970214158
Short name T695
Test name
Test status
Simulation time 20999368 ps
CPU time 1.11 seconds
Started May 14 02:08:47 PM PDT 24
Finished May 14 02:08:51 PM PDT 24
Peak memory 215048 kb
Host smart-ea7ebc6f-440b-455f-aa6a-970ae8cbe64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970214158 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.970214158
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.4236583875
Short name T670
Test name
Test status
Simulation time 62816193 ps
CPU time 0.95 seconds
Started May 14 02:08:47 PM PDT 24
Finished May 14 02:08:51 PM PDT 24
Peak memory 214956 kb
Host smart-8eec1e79-a2b6-4252-8d39-ba3a3e981011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236583875 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.4236583875
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3870298051
Short name T458
Test name
Test status
Simulation time 372012714 ps
CPU time 1.87 seconds
Started May 14 02:08:52 PM PDT 24
Finished May 14 02:08:58 PM PDT 24
Peak memory 218488 kb
Host smart-655483da-2afc-450b-9bc6-e4e6a91f5afd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870298051 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3870298051
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2087092645
Short name T200
Test name
Test status
Simulation time 42080732798 ps
CPU time 902.9 seconds
Started May 14 02:08:45 PM PDT 24
Finished May 14 02:23:49 PM PDT 24
Peak memory 223236 kb
Host smart-02ab9f2e-5e30-4632-a769-de945c89ec69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087092645 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2087092645
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1073448736
Short name T282
Test name
Test status
Simulation time 75939748 ps
CPU time 1.47 seconds
Started May 14 02:10:45 PM PDT 24
Finished May 14 02:10:49 PM PDT 24
Peak memory 218484 kb
Host smart-950720e4-4723-4e95-82f2-5bba834bce33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073448736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1073448736
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.582740757
Short name T313
Test name
Test status
Simulation time 101976244 ps
CPU time 1.3 seconds
Started May 14 02:10:46 PM PDT 24
Finished May 14 02:10:51 PM PDT 24
Peak memory 218164 kb
Host smart-c1db7ebc-c08b-4482-bf74-6eb6e08a4c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582740757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.582740757
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2074380769
Short name T123
Test name
Test status
Simulation time 79679178 ps
CPU time 1.11 seconds
Started May 14 02:10:48 PM PDT 24
Finished May 14 02:10:53 PM PDT 24
Peak memory 216840 kb
Host smart-d0e9f149-8bf3-4126-9a8b-ff55a7578b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074380769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2074380769
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1114075929
Short name T290
Test name
Test status
Simulation time 58666815 ps
CPU time 1.34 seconds
Started May 14 02:10:45 PM PDT 24
Finished May 14 02:10:49 PM PDT 24
Peak memory 219040 kb
Host smart-2c7e0c0b-8bd0-40bd-8976-bd9d5f635455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114075929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1114075929
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2117127091
Short name T395
Test name
Test status
Simulation time 63669093 ps
CPU time 1.08 seconds
Started May 14 02:10:48 PM PDT 24
Finished May 14 02:10:53 PM PDT 24
Peak memory 216588 kb
Host smart-f8a7d1ad-54b6-4814-859a-ad408d444bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117127091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2117127091
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1500480746
Short name T508
Test name
Test status
Simulation time 94375751 ps
CPU time 1.13 seconds
Started May 14 02:10:45 PM PDT 24
Finished May 14 02:10:48 PM PDT 24
Peak memory 216724 kb
Host smart-d7e59624-d654-4b94-b05d-ce07ad98fd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500480746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1500480746
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.4205374094
Short name T25
Test name
Test status
Simulation time 164638364 ps
CPU time 1.85 seconds
Started May 14 02:10:45 PM PDT 24
Finished May 14 02:10:49 PM PDT 24
Peak memory 218052 kb
Host smart-f552442b-4adc-476b-84fb-34985b66f6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205374094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.4205374094
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1243962713
Short name T270
Test name
Test status
Simulation time 32551411 ps
CPU time 1.01 seconds
Started May 14 02:10:48 PM PDT 24
Finished May 14 02:10:53 PM PDT 24
Peak memory 216888 kb
Host smart-bc9e779a-85ae-49fa-8b02-44efcbce3bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243962713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1243962713
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1451293831
Short name T585
Test name
Test status
Simulation time 99310745 ps
CPU time 1.13 seconds
Started May 14 02:10:48 PM PDT 24
Finished May 14 02:10:53 PM PDT 24
Peak memory 216832 kb
Host smart-03ffbed4-c945-4c3c-a16e-f3f1fdb661f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451293831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1451293831
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.348307922
Short name T621
Test name
Test status
Simulation time 41917569 ps
CPU time 1.55 seconds
Started May 14 02:10:43 PM PDT 24
Finished May 14 02:10:47 PM PDT 24
Peak memory 217760 kb
Host smart-0aa74fcb-8d8d-4aad-99e5-60afb408bf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348307922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.348307922
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.957447147
Short name T30
Test name
Test status
Simulation time 94701413 ps
CPU time 1.23 seconds
Started May 14 02:08:46 PM PDT 24
Finished May 14 02:08:51 PM PDT 24
Peak memory 215300 kb
Host smart-380d1371-6f59-4c8a-a427-da8bcc3bed55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957447147 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.957447147
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2314506411
Short name T807
Test name
Test status
Simulation time 17219619 ps
CPU time 0.96 seconds
Started May 14 02:08:51 PM PDT 24
Finished May 14 02:08:56 PM PDT 24
Peak memory 214516 kb
Host smart-86a5be27-6ec4-4c7a-8aa2-42252e764b38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314506411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2314506411
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2486974711
Short name T698
Test name
Test status
Simulation time 126467635 ps
CPU time 0.8 seconds
Started May 14 02:08:50 PM PDT 24
Finished May 14 02:08:55 PM PDT 24
Peak memory 215992 kb
Host smart-ff6b696d-668e-4114-8470-b6ae865e03aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486974711 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2486974711
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.1930047420
Short name T171
Test name
Test status
Simulation time 49655800 ps
CPU time 0.97 seconds
Started May 14 02:08:49 PM PDT 24
Finished May 14 02:08:54 PM PDT 24
Peak memory 219936 kb
Host smart-7e596cdc-16f1-4696-b0fe-b1a940653dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930047420 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1930047420
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2567367331
Short name T388
Test name
Test status
Simulation time 236758886 ps
CPU time 3.2 seconds
Started May 14 02:08:52 PM PDT 24
Finished May 14 02:08:59 PM PDT 24
Peak memory 219116 kb
Host smart-c198f426-c2b4-4846-a9be-7d21f5ece218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567367331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2567367331
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3004952379
Short name T483
Test name
Test status
Simulation time 35158973 ps
CPU time 0.99 seconds
Started May 14 02:08:50 PM PDT 24
Finished May 14 02:08:55 PM PDT 24
Peak memory 223376 kb
Host smart-62ebb1ff-4c56-4e2c-95e8-d77961da3230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004952379 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3004952379
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.554157875
Short name T3
Test name
Test status
Simulation time 27947866 ps
CPU time 0.97 seconds
Started May 14 02:08:50 PM PDT 24
Finished May 14 02:08:56 PM PDT 24
Peak memory 214956 kb
Host smart-c01eb88f-ec6a-4414-b212-c9f639d4cb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554157875 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.554157875
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.312334400
Short name T448
Test name
Test status
Simulation time 237948140 ps
CPU time 1.78 seconds
Started May 14 02:08:50 PM PDT 24
Finished May 14 02:08:56 PM PDT 24
Peak memory 216676 kb
Host smart-43e22561-8e9c-4dfc-afe1-4e2d54c105e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312334400 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.312334400
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3493895053
Short name T196
Test name
Test status
Simulation time 81171136278 ps
CPU time 1724.9 seconds
Started May 14 02:08:50 PM PDT 24
Finished May 14 02:37:39 PM PDT 24
Peak memory 225016 kb
Host smart-dabd2c3e-d239-4a31-81ad-13a7d3943d38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493895053 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3493895053
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1667062302
Short name T121
Test name
Test status
Simulation time 55770487 ps
CPU time 1.49 seconds
Started May 14 02:10:51 PM PDT 24
Finished May 14 02:10:56 PM PDT 24
Peak memory 217980 kb
Host smart-e64db851-9f6b-4b3e-ba0d-06feb808f5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667062302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1667062302
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3600056948
Short name T743
Test name
Test status
Simulation time 26106139 ps
CPU time 1.24 seconds
Started May 14 02:10:51 PM PDT 24
Finished May 14 02:10:55 PM PDT 24
Peak memory 216848 kb
Host smart-53cf188f-aea7-450e-be41-ff2aa2ffa541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600056948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3600056948
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.4146699317
Short name T751
Test name
Test status
Simulation time 85777338 ps
CPU time 1.21 seconds
Started May 14 02:10:49 PM PDT 24
Finished May 14 02:10:54 PM PDT 24
Peak memory 216524 kb
Host smart-3172cd13-d0b4-448d-9c91-eeb17796e00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146699317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.4146699317
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1364023831
Short name T443
Test name
Test status
Simulation time 41966384 ps
CPU time 1.5 seconds
Started May 14 02:10:48 PM PDT 24
Finished May 14 02:10:53 PM PDT 24
Peak memory 216536 kb
Host smart-1ef78302-96e8-427a-a93f-55282064374a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364023831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1364023831
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.965857461
Short name T330
Test name
Test status
Simulation time 76110836 ps
CPU time 1.3 seconds
Started May 14 02:10:51 PM PDT 24
Finished May 14 02:10:55 PM PDT 24
Peak memory 219536 kb
Host smart-d7bc84dd-b9ec-45c8-9b45-edcf30e512d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965857461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.965857461
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3315996232
Short name T723
Test name
Test status
Simulation time 45048489 ps
CPU time 1.37 seconds
Started May 14 02:10:48 PM PDT 24
Finished May 14 02:10:53 PM PDT 24
Peak memory 218172 kb
Host smart-6af55b3d-a027-46ec-a026-e720c7d0a2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315996232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3315996232
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2638015578
Short name T12
Test name
Test status
Simulation time 44541024 ps
CPU time 1.5 seconds
Started May 14 02:10:48 PM PDT 24
Finished May 14 02:10:54 PM PDT 24
Peak memory 219356 kb
Host smart-2ff6d010-5667-4acf-aad8-4c1752e493af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638015578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2638015578
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3650874513
Short name T533
Test name
Test status
Simulation time 97584079 ps
CPU time 1.18 seconds
Started May 14 02:10:50 PM PDT 24
Finished May 14 02:10:55 PM PDT 24
Peak memory 217832 kb
Host smart-5040d253-422e-4ed2-8765-fec5c6485336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650874513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3650874513
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3577882227
Short name T500
Test name
Test status
Simulation time 42776627 ps
CPU time 1.51 seconds
Started May 14 02:10:48 PM PDT 24
Finished May 14 02:10:53 PM PDT 24
Peak memory 217868 kb
Host smart-bd9ec314-bcae-42d3-82f1-98c996d75aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577882227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3577882227
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2607639708
Short name T243
Test name
Test status
Simulation time 65375982 ps
CPU time 1.16 seconds
Started May 14 02:10:47 PM PDT 24
Finished May 14 02:10:52 PM PDT 24
Peak memory 216540 kb
Host smart-033e06ce-6b5e-4881-9c30-703e6dba15c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607639708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2607639708
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3310402688
Short name T709
Test name
Test status
Simulation time 231932708 ps
CPU time 1.36 seconds
Started May 14 02:08:49 PM PDT 24
Finished May 14 02:08:55 PM PDT 24
Peak memory 215268 kb
Host smart-73d221e7-f5b6-49c1-bc27-cf3a0cff41da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310402688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3310402688
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3699422887
Short name T843
Test name
Test status
Simulation time 12771693 ps
CPU time 0.91 seconds
Started May 14 02:08:52 PM PDT 24
Finished May 14 02:08:57 PM PDT 24
Peak memory 214456 kb
Host smart-c7a013e3-1b08-4b38-b07c-fde3b5a2fc90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699422887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3699422887
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.192530203
Short name T425
Test name
Test status
Simulation time 18640698 ps
CPU time 0.84 seconds
Started May 14 02:08:47 PM PDT 24
Finished May 14 02:08:51 PM PDT 24
Peak memory 215628 kb
Host smart-dfcb06d8-fe48-4de4-8cbd-175e30c62ccf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192530203 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.192530203
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3565133531
Short name T441
Test name
Test status
Simulation time 68772122 ps
CPU time 1.16 seconds
Started May 14 02:08:50 PM PDT 24
Finished May 14 02:08:55 PM PDT 24
Peak memory 216736 kb
Host smart-bee38317-c615-4a3b-a17b-bc7c41b07cb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565133531 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3565133531
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1767528256
Short name T762
Test name
Test status
Simulation time 38730616 ps
CPU time 0.98 seconds
Started May 14 02:08:48 PM PDT 24
Finished May 14 02:08:53 PM PDT 24
Peak memory 218244 kb
Host smart-65e0c58d-9f93-44d6-8ef2-9216994cb294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767528256 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1767528256
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1659983093
Short name T404
Test name
Test status
Simulation time 53515756 ps
CPU time 1.02 seconds
Started May 14 02:08:50 PM PDT 24
Finished May 14 02:08:55 PM PDT 24
Peak memory 216840 kb
Host smart-87784199-5aca-408e-857e-a09c0f446f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659983093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1659983093
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3109555874
Short name T837
Test name
Test status
Simulation time 25138428 ps
CPU time 0.98 seconds
Started May 14 02:08:50 PM PDT 24
Finished May 14 02:08:55 PM PDT 24
Peak memory 214788 kb
Host smart-9814a613-fcdd-4a81-aba9-7488c716e26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109555874 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3109555874
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3852063475
Short name T535
Test name
Test status
Simulation time 28641508 ps
CPU time 0.95 seconds
Started May 14 02:08:52 PM PDT 24
Finished May 14 02:08:57 PM PDT 24
Peak memory 214988 kb
Host smart-1f2cc7ce-9498-4332-a365-eda592c3a2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852063475 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3852063475
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2716715029
Short name T630
Test name
Test status
Simulation time 284572711 ps
CPU time 3.46 seconds
Started May 14 02:08:51 PM PDT 24
Finished May 14 02:08:58 PM PDT 24
Peak memory 219096 kb
Host smart-305cc870-a800-4cc8-87f8-45561fc6c9aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716715029 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2716715029
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1238709350
Short name T810
Test name
Test status
Simulation time 61973884493 ps
CPU time 462.69 seconds
Started May 14 02:08:47 PM PDT 24
Finished May 14 02:16:33 PM PDT 24
Peak memory 218472 kb
Host smart-4d8cbc11-a478-4d43-a90b-da25164336dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238709350 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1238709350
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3248268908
Short name T576
Test name
Test status
Simulation time 25437891 ps
CPU time 1.3 seconds
Started May 14 02:10:49 PM PDT 24
Finished May 14 02:10:54 PM PDT 24
Peak memory 218064 kb
Host smart-a08bb82b-0b8d-4c1a-927a-004eb03eabdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248268908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3248268908
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.751184837
Short name T686
Test name
Test status
Simulation time 80581679 ps
CPU time 1.2 seconds
Started May 14 02:10:51 PM PDT 24
Finished May 14 02:10:55 PM PDT 24
Peak memory 216584 kb
Host smart-025ae189-a70a-4b40-90ec-06c1d30489c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751184837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.751184837
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2802671646
Short name T694
Test name
Test status
Simulation time 30842205 ps
CPU time 1.38 seconds
Started May 14 02:10:48 PM PDT 24
Finished May 14 02:10:53 PM PDT 24
Peak memory 217960 kb
Host smart-ace0c489-af7d-4e1f-8693-acc802c8f817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802671646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2802671646
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3924397388
Short name T338
Test name
Test status
Simulation time 149275547 ps
CPU time 1 seconds
Started May 14 02:10:48 PM PDT 24
Finished May 14 02:10:52 PM PDT 24
Peak memory 216848 kb
Host smart-a5cd6c7a-de40-4c09-aab1-f9db508aeaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924397388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3924397388
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2663760343
Short name T754
Test name
Test status
Simulation time 108849575 ps
CPU time 1.13 seconds
Started May 14 02:10:51 PM PDT 24
Finished May 14 02:10:55 PM PDT 24
Peak memory 216624 kb
Host smart-9943cc49-6c6d-4b2e-b66f-0493c0107049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663760343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2663760343
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3398773191
Short name T146
Test name
Test status
Simulation time 44789962 ps
CPU time 1.43 seconds
Started May 14 02:10:48 PM PDT 24
Finished May 14 02:10:53 PM PDT 24
Peak memory 218108 kb
Host smart-651bc48c-8f38-450c-a655-6de89fc2d757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398773191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3398773191
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1467271662
Short name T331
Test name
Test status
Simulation time 157181792 ps
CPU time 3.27 seconds
Started May 14 02:10:50 PM PDT 24
Finished May 14 02:10:57 PM PDT 24
Peak memory 219324 kb
Host smart-9987f269-7b5b-4829-83bb-b79e4e85e90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467271662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1467271662
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3704176496
Short name T579
Test name
Test status
Simulation time 36559251 ps
CPU time 1.45 seconds
Started May 14 02:10:46 PM PDT 24
Finished May 14 02:10:51 PM PDT 24
Peak memory 216928 kb
Host smart-e07d2b87-851d-4bd2-a189-af6348b30012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704176496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3704176496
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3319547458
Short name T783
Test name
Test status
Simulation time 52731977 ps
CPU time 1.91 seconds
Started May 14 02:10:47 PM PDT 24
Finished May 14 02:10:52 PM PDT 24
Peak memory 217980 kb
Host smart-0d360521-db82-4243-9530-d2aa53659985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319547458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3319547458
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1920257710
Short name T334
Test name
Test status
Simulation time 76745886 ps
CPU time 1.48 seconds
Started May 14 02:10:48 PM PDT 24
Finished May 14 02:10:54 PM PDT 24
Peak memory 217816 kb
Host smart-6055b11d-936c-4b6c-bcab-168312198301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920257710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1920257710
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3849461482
Short name T96
Test name
Test status
Simulation time 245772310 ps
CPU time 1.34 seconds
Started May 14 02:08:55 PM PDT 24
Finished May 14 02:08:59 PM PDT 24
Peak memory 215404 kb
Host smart-7c346d5e-2626-44b0-b698-161e9e9cb960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849461482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3849461482
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.622985813
Short name T537
Test name
Test status
Simulation time 15366163 ps
CPU time 1.01 seconds
Started May 14 02:09:00 PM PDT 24
Finished May 14 02:09:04 PM PDT 24
Peak memory 214504 kb
Host smart-285e1a4f-9af1-4125-96c7-ed5b5bfbcd2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622985813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.622985813
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3859268373
Short name T525
Test name
Test status
Simulation time 19551729 ps
CPU time 0.85 seconds
Started May 14 02:09:00 PM PDT 24
Finished May 14 02:09:04 PM PDT 24
Peak memory 215656 kb
Host smart-f47e8d95-e70a-4109-bd6e-4934b613a60a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859268373 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3859268373
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2461542266
Short name T774
Test name
Test status
Simulation time 125545136 ps
CPU time 1.17 seconds
Started May 14 02:08:58 PM PDT 24
Finished May 14 02:09:02 PM PDT 24
Peak memory 216416 kb
Host smart-ef62d5b1-e8bd-4d81-bffd-70f7c7bed88a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461542266 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2461542266
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.43844552
Short name T793
Test name
Test status
Simulation time 32596020 ps
CPU time 0.9 seconds
Started May 14 02:09:00 PM PDT 24
Finished May 14 02:09:04 PM PDT 24
Peak memory 218104 kb
Host smart-eab58b41-92b6-4705-9753-3b98cdd53321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43844552 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.43844552
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3891290219
Short name T317
Test name
Test status
Simulation time 38686172 ps
CPU time 1.58 seconds
Started May 14 02:08:49 PM PDT 24
Finished May 14 02:08:55 PM PDT 24
Peak memory 219556 kb
Host smart-57070c31-6f07-47ef-b7fe-fec33ddaefdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891290219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3891290219
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2030663151
Short name T382
Test name
Test status
Simulation time 33657577 ps
CPU time 0.95 seconds
Started May 14 02:08:56 PM PDT 24
Finished May 14 02:08:59 PM PDT 24
Peak memory 215260 kb
Host smart-6225dbb1-615d-446e-b932-2dd8ab48479a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030663151 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2030663151
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.1971878181
Short name T412
Test name
Test status
Simulation time 42568685 ps
CPU time 0.91 seconds
Started May 14 02:08:50 PM PDT 24
Finished May 14 02:08:55 PM PDT 24
Peak memory 214928 kb
Host smart-c897c276-46d9-45a5-92e0-34b87faa334b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971878181 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1971878181
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2070351939
Short name T124
Test name
Test status
Simulation time 285236918 ps
CPU time 5.8 seconds
Started May 14 02:08:49 PM PDT 24
Finished May 14 02:08:59 PM PDT 24
Peak memory 216604 kb
Host smart-b9ada5c5-7ad7-49fe-b821-9104b26d4df5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070351939 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2070351939
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.963704664
Short name T117
Test name
Test status
Simulation time 282298866597 ps
CPU time 1612.33 seconds
Started May 14 02:08:53 PM PDT 24
Finished May 14 02:35:49 PM PDT 24
Peak memory 223500 kb
Host smart-aab2b8d9-2b12-404c-87c0-08e3ca0ea2d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963704664 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.963704664
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.4160220426
Short name T673
Test name
Test status
Simulation time 69948161 ps
CPU time 2.11 seconds
Started May 14 02:10:51 PM PDT 24
Finished May 14 02:10:56 PM PDT 24
Peak memory 219436 kb
Host smart-e2b7f3a0-edc0-4351-beab-23bd5aa4846a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160220426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.4160220426
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1018508504
Short name T460
Test name
Test status
Simulation time 60589466 ps
CPU time 1.33 seconds
Started May 14 02:10:48 PM PDT 24
Finished May 14 02:10:53 PM PDT 24
Peak memory 216736 kb
Host smart-2acd4478-f62f-4ff6-9792-17a9d7acd252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018508504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1018508504
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1957738822
Short name T583
Test name
Test status
Simulation time 37727748 ps
CPU time 1.37 seconds
Started May 14 02:10:51 PM PDT 24
Finished May 14 02:10:56 PM PDT 24
Peak memory 217804 kb
Host smart-808ec5f0-4c75-43b2-8435-97c47360064a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957738822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1957738822
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.383484577
Short name T471
Test name
Test status
Simulation time 83146515 ps
CPU time 1.14 seconds
Started May 14 02:10:51 PM PDT 24
Finished May 14 02:10:55 PM PDT 24
Peak memory 216568 kb
Host smart-09423423-01dc-43ac-924c-bd5ad99995f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383484577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.383484577
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3499194939
Short name T294
Test name
Test status
Simulation time 41115348 ps
CPU time 1.46 seconds
Started May 14 02:10:46 PM PDT 24
Finished May 14 02:10:51 PM PDT 24
Peak memory 216512 kb
Host smart-dca9df14-b490-4412-a1f9-2b254b73e397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499194939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3499194939
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3756575273
Short name T712
Test name
Test status
Simulation time 37452563 ps
CPU time 1.5 seconds
Started May 14 02:10:49 PM PDT 24
Finished May 14 02:10:54 PM PDT 24
Peak memory 216704 kb
Host smart-d8d3c68f-d068-47a5-9e01-ade31dbac626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756575273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3756575273
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2002104168
Short name T155
Test name
Test status
Simulation time 60225881 ps
CPU time 1.2 seconds
Started May 14 02:10:55 PM PDT 24
Finished May 14 02:10:58 PM PDT 24
Peak memory 216860 kb
Host smart-76b0219d-e9b1-4317-a108-648bd52f79a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002104168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2002104168
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.671190954
Short name T839
Test name
Test status
Simulation time 108394314 ps
CPU time 1.37 seconds
Started May 14 02:11:02 PM PDT 24
Finished May 14 02:11:06 PM PDT 24
Peak memory 217844 kb
Host smart-c75b8cba-5a86-4012-aa0c-fe5cb49a9fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671190954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.671190954
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert_test.1367343194
Short name T315
Test name
Test status
Simulation time 32510487 ps
CPU time 0.8 seconds
Started May 14 02:08:55 PM PDT 24
Finished May 14 02:08:58 PM PDT 24
Peak memory 206556 kb
Host smart-449e53fc-0530-4ca4-9283-bb9a7d324600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367343194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1367343194
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3102580576
Short name T369
Test name
Test status
Simulation time 39646616 ps
CPU time 0.91 seconds
Started May 14 02:08:55 PM PDT 24
Finished May 14 02:08:59 PM PDT 24
Peak memory 215684 kb
Host smart-7488c705-ba87-4bd5-bd5e-6a9de26612b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102580576 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3102580576
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2129666183
Short name T178
Test name
Test status
Simulation time 194582103 ps
CPU time 1.13 seconds
Started May 14 02:09:04 PM PDT 24
Finished May 14 02:09:09 PM PDT 24
Peak memory 216504 kb
Host smart-f6fe3bb4-e9c4-4749-a970-08222896d5ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129666183 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2129666183
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3746269862
Short name T811
Test name
Test status
Simulation time 25057908 ps
CPU time 1.01 seconds
Started May 14 02:08:58 PM PDT 24
Finished May 14 02:09:02 PM PDT 24
Peak memory 223264 kb
Host smart-c5996302-dbe0-4c5d-bab9-d08dfc36954d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746269862 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3746269862
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3239794433
Short name T829
Test name
Test status
Simulation time 210035468 ps
CPU time 3.09 seconds
Started May 14 02:08:55 PM PDT 24
Finished May 14 02:09:01 PM PDT 24
Peak memory 219676 kb
Host smart-fae195b1-a8d1-475d-94b3-5367ea467798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239794433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3239794433
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.578549904
Short name T5
Test name
Test status
Simulation time 20716575 ps
CPU time 1.1 seconds
Started May 14 02:09:07 PM PDT 24
Finished May 14 02:09:11 PM PDT 24
Peak memory 215288 kb
Host smart-47ba842c-a81d-45b9-9bee-3d142fd10bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578549904 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.578549904
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2770661650
Short name T373
Test name
Test status
Simulation time 15643168 ps
CPU time 1 seconds
Started May 14 02:08:55 PM PDT 24
Finished May 14 02:08:59 PM PDT 24
Peak memory 214900 kb
Host smart-b602b0c0-4a64-4ff5-8324-4320cbbafac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770661650 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2770661650
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2290932862
Short name T417
Test name
Test status
Simulation time 93571328 ps
CPU time 1.08 seconds
Started May 14 02:08:59 PM PDT 24
Finished May 14 02:09:03 PM PDT 24
Peak memory 206696 kb
Host smart-f063aa98-a60b-4fc2-bfb4-0b81b52f75a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290932862 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2290932862
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1298334765
Short name T386
Test name
Test status
Simulation time 16982353798 ps
CPU time 425.06 seconds
Started May 14 02:09:01 PM PDT 24
Finished May 14 02:16:10 PM PDT 24
Peak memory 217604 kb
Host smart-2bb9d3ff-cbd8-46e7-a47d-e906eb5f192e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298334765 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1298334765
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3348157759
Short name T820
Test name
Test status
Simulation time 20715096 ps
CPU time 1.08 seconds
Started May 14 02:10:57 PM PDT 24
Finished May 14 02:11:00 PM PDT 24
Peak memory 216584 kb
Host smart-4785b0ce-9c3a-470b-9e59-266a373ffd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348157759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3348157759
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3577044327
Short name T849
Test name
Test status
Simulation time 33091656 ps
CPU time 1.27 seconds
Started May 14 02:11:00 PM PDT 24
Finished May 14 02:11:04 PM PDT 24
Peak memory 216792 kb
Host smart-c7b50e57-3780-4724-b713-0567d5844e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577044327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3577044327
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3434359377
Short name T153
Test name
Test status
Simulation time 44045724 ps
CPU time 1.9 seconds
Started May 14 02:10:58 PM PDT 24
Finished May 14 02:11:02 PM PDT 24
Peak memory 219264 kb
Host smart-aa8cc0ef-dd0a-4d69-a521-9115ead53cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434359377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3434359377
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3068651457
Short name T642
Test name
Test status
Simulation time 45097290 ps
CPU time 1.14 seconds
Started May 14 02:11:00 PM PDT 24
Finished May 14 02:11:04 PM PDT 24
Peak memory 216732 kb
Host smart-80ed760c-757e-451b-80f2-47f2f282ae2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068651457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3068651457
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.4182192305
Short name T279
Test name
Test status
Simulation time 75682374 ps
CPU time 2.33 seconds
Started May 14 02:10:55 PM PDT 24
Finished May 14 02:10:59 PM PDT 24
Peak memory 219492 kb
Host smart-35bfb539-7a61-4952-bac7-680247b499e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182192305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.4182192305
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3802572068
Short name T720
Test name
Test status
Simulation time 111745672 ps
CPU time 1.26 seconds
Started May 14 02:10:58 PM PDT 24
Finished May 14 02:11:02 PM PDT 24
Peak memory 216652 kb
Host smart-58985036-e0dd-463a-b9c4-6cc005733f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802572068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3802572068
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1149133129
Short name T440
Test name
Test status
Simulation time 96057326 ps
CPU time 1.43 seconds
Started May 14 02:10:57 PM PDT 24
Finished May 14 02:11:00 PM PDT 24
Peak memory 218728 kb
Host smart-aef46297-e2c8-4503-91ec-916bb4da69b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149133129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1149133129
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1455367174
Short name T655
Test name
Test status
Simulation time 38463017 ps
CPU time 1.64 seconds
Started May 14 02:10:56 PM PDT 24
Finished May 14 02:11:00 PM PDT 24
Peak memory 217676 kb
Host smart-ace83278-0d6d-4654-9012-7ce36d42b5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455367174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1455367174
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.155480308
Short name T491
Test name
Test status
Simulation time 319749476 ps
CPU time 2.07 seconds
Started May 14 02:11:01 PM PDT 24
Finished May 14 02:11:06 PM PDT 24
Peak memory 218428 kb
Host smart-92d61e84-7497-4c1b-ae3e-aea03c1795ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155480308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.155480308
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.435154635
Short name T834
Test name
Test status
Simulation time 48218095 ps
CPU time 1.72 seconds
Started May 14 02:10:54 PM PDT 24
Finished May 14 02:10:57 PM PDT 24
Peak memory 219308 kb
Host smart-d3806f61-fecb-42b9-a338-6012c73cb68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435154635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.435154635
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3563389025
Short name T67
Test name
Test status
Simulation time 61291684 ps
CPU time 1.16 seconds
Started May 14 02:08:59 PM PDT 24
Finished May 14 02:09:03 PM PDT 24
Peak memory 215288 kb
Host smart-71fe1d39-c0f2-42ff-a177-5c74d7bafb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563389025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3563389025
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3454654650
Short name T558
Test name
Test status
Simulation time 15412812 ps
CPU time 0.91 seconds
Started May 14 02:09:03 PM PDT 24
Finished May 14 02:09:08 PM PDT 24
Peak memory 206232 kb
Host smart-7c748874-3256-4a23-9f24-9e9072ff20d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454654650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3454654650
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.244298080
Short name T59
Test name
Test status
Simulation time 35379936 ps
CPU time 0.9 seconds
Started May 14 02:09:04 PM PDT 24
Finished May 14 02:09:09 PM PDT 24
Peak memory 215148 kb
Host smart-0a6fae9f-9161-4231-8165-cdd3b68d6eec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244298080 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.244298080
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.732467771
Short name T612
Test name
Test status
Simulation time 27887750 ps
CPU time 1.15 seconds
Started May 14 02:09:03 PM PDT 24
Finished May 14 02:09:08 PM PDT 24
Peak memory 219040 kb
Host smart-0cd3b5c7-603b-4359-b2fc-84660c22b929
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732467771 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.732467771
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1488200336
Short name T434
Test name
Test status
Simulation time 22732999 ps
CPU time 1 seconds
Started May 14 02:09:00 PM PDT 24
Finished May 14 02:09:04 PM PDT 24
Peak memory 217980 kb
Host smart-c724cb8f-f614-48c0-b913-75101403b7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488200336 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1488200336
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2934399995
Short name T318
Test name
Test status
Simulation time 280265470 ps
CPU time 1.91 seconds
Started May 14 02:09:03 PM PDT 24
Finished May 14 02:09:09 PM PDT 24
Peak memory 218172 kb
Host smart-01a6a4d4-cf03-4f87-baf3-49254892714e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934399995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2934399995
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.481769745
Short name T726
Test name
Test status
Simulation time 21705256 ps
CPU time 1.11 seconds
Started May 14 02:09:03 PM PDT 24
Finished May 14 02:09:08 PM PDT 24
Peak memory 215032 kb
Host smart-155923be-0937-4c06-a1be-b1b01280cd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481769745 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.481769745
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1907568718
Short name T598
Test name
Test status
Simulation time 27755486 ps
CPU time 1.01 seconds
Started May 14 02:08:56 PM PDT 24
Finished May 14 02:09:00 PM PDT 24
Peak memory 214952 kb
Host smart-c41a4f3c-b898-421e-8b2f-645f5eb42bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907568718 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1907568718
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2426064169
Short name T787
Test name
Test status
Simulation time 1096737857 ps
CPU time 6.22 seconds
Started May 14 02:08:57 PM PDT 24
Finished May 14 02:09:06 PM PDT 24
Peak memory 216744 kb
Host smart-cfc49fd6-493f-4bcf-b592-f5a3df585aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426064169 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2426064169
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.128255612
Short name T602
Test name
Test status
Simulation time 64413229649 ps
CPU time 1446.2 seconds
Started May 14 02:09:03 PM PDT 24
Finished May 14 02:33:13 PM PDT 24
Peak memory 222412 kb
Host smart-dc225478-a5de-47e8-93b4-2d02212babc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128255612 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.128255612
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1075261941
Short name T688
Test name
Test status
Simulation time 47936959 ps
CPU time 1.92 seconds
Started May 14 02:11:01 PM PDT 24
Finished May 14 02:11:06 PM PDT 24
Peak memory 218044 kb
Host smart-91f5ef44-bffb-42a1-aac4-b3f94f98b9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075261941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1075261941
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1833993708
Short name T509
Test name
Test status
Simulation time 35962598 ps
CPU time 1.34 seconds
Started May 14 02:11:01 PM PDT 24
Finished May 14 02:11:05 PM PDT 24
Peak memory 217780 kb
Host smart-a5a69521-10ac-408e-b39c-2fdbaecee209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833993708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1833993708
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2681736727
Short name T595
Test name
Test status
Simulation time 72156210 ps
CPU time 1.61 seconds
Started May 14 02:11:00 PM PDT 24
Finished May 14 02:11:04 PM PDT 24
Peak memory 217880 kb
Host smart-0946761e-c513-4c2e-a271-3400a0bfff38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681736727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2681736727
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2538215757
Short name T383
Test name
Test status
Simulation time 50507039 ps
CPU time 1.25 seconds
Started May 14 02:10:58 PM PDT 24
Finished May 14 02:11:02 PM PDT 24
Peak memory 215104 kb
Host smart-0f0ba94e-1799-4953-b036-7a9ae8826a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538215757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2538215757
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3954125013
Short name T447
Test name
Test status
Simulation time 136222153 ps
CPU time 1.36 seconds
Started May 14 02:10:59 PM PDT 24
Finished May 14 02:11:03 PM PDT 24
Peak memory 217864 kb
Host smart-6840d883-de3d-4577-8aa9-63e36a4860ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954125013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3954125013
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1665855592
Short name T570
Test name
Test status
Simulation time 58370175 ps
CPU time 1.28 seconds
Started May 14 02:10:55 PM PDT 24
Finished May 14 02:10:58 PM PDT 24
Peak memory 216904 kb
Host smart-fdf2be81-e5c3-4f1f-8d34-7fd559992309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665855592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1665855592
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2101663014
Short name T320
Test name
Test status
Simulation time 48091318 ps
CPU time 1.3 seconds
Started May 14 02:11:00 PM PDT 24
Finished May 14 02:11:04 PM PDT 24
Peak memory 217776 kb
Host smart-8bb4c3cb-5ec7-49fb-b8d8-f0d03cdbc499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101663014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2101663014
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2348188962
Short name T601
Test name
Test status
Simulation time 39581518 ps
CPU time 1.33 seconds
Started May 14 02:10:56 PM PDT 24
Finished May 14 02:11:00 PM PDT 24
Peak memory 217952 kb
Host smart-0a361610-45c6-4795-b80b-2a0baeab8fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348188962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2348188962
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3355108715
Short name T427
Test name
Test status
Simulation time 41287023 ps
CPU time 1.41 seconds
Started May 14 02:11:01 PM PDT 24
Finished May 14 02:11:06 PM PDT 24
Peak memory 217940 kb
Host smart-d60c2879-7341-4d71-9f34-c0377185cb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355108715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3355108715
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1952331990
Short name T254
Test name
Test status
Simulation time 232529150 ps
CPU time 1.26 seconds
Started May 14 02:09:00 PM PDT 24
Finished May 14 02:09:05 PM PDT 24
Peak memory 215340 kb
Host smart-8739c5a5-9ac7-4ce5-9a07-c3917de43777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952331990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1952331990
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.867822116
Short name T345
Test name
Test status
Simulation time 28616540 ps
CPU time 0.97 seconds
Started May 14 02:08:59 PM PDT 24
Finished May 14 02:09:03 PM PDT 24
Peak memory 214504 kb
Host smart-77a34b51-591e-43eb-816a-1cbcd77016f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867822116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.867822116
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3127805952
Short name T772
Test name
Test status
Simulation time 16886897 ps
CPU time 0.84 seconds
Started May 14 02:08:56 PM PDT 24
Finished May 14 02:08:59 PM PDT 24
Peak memory 215204 kb
Host smart-89e2ef5e-152d-42ae-bd72-67a40e06f9de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127805952 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3127805952
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.974354379
Short name T368
Test name
Test status
Simulation time 137015396 ps
CPU time 1.13 seconds
Started May 14 02:08:59 PM PDT 24
Finished May 14 02:09:03 PM PDT 24
Peak memory 217896 kb
Host smart-31b6ba0f-6846-4a99-b9ca-22c610e2ab3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974354379 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.974354379
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2114319731
Short name T50
Test name
Test status
Simulation time 49991434 ps
CPU time 1.01 seconds
Started May 14 02:08:59 PM PDT 24
Finished May 14 02:09:04 PM PDT 24
Peak memory 219472 kb
Host smart-004c8157-117c-436c-bb2a-12d3fb194014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114319731 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2114319731
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1182807553
Short name T771
Test name
Test status
Simulation time 72388243 ps
CPU time 1.47 seconds
Started May 14 02:08:57 PM PDT 24
Finished May 14 02:09:02 PM PDT 24
Peak memory 214984 kb
Host smart-e94aaf6b-a2c9-4b0b-8f4c-8592522fd0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182807553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1182807553
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2333223882
Short name T468
Test name
Test status
Simulation time 26349192 ps
CPU time 0.95 seconds
Started May 14 02:09:00 PM PDT 24
Finished May 14 02:09:05 PM PDT 24
Peak memory 215076 kb
Host smart-559f0c0d-92e0-403d-bafb-edfd5ea843d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333223882 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2333223882
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2103432481
Short name T406
Test name
Test status
Simulation time 44757320 ps
CPU time 0.92 seconds
Started May 14 02:08:55 PM PDT 24
Finished May 14 02:08:59 PM PDT 24
Peak memory 214948 kb
Host smart-38d3b032-f8c7-4754-b577-d0dc1320bd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103432481 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2103432481
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3096151473
Short name T588
Test name
Test status
Simulation time 490946912 ps
CPU time 2.95 seconds
Started May 14 02:09:04 PM PDT 24
Finished May 14 02:09:11 PM PDT 24
Peak memory 214944 kb
Host smart-389a10de-8a35-4841-afbe-511c256fe558
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096151473 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3096151473
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.950072826
Short name T189
Test name
Test status
Simulation time 25292372922 ps
CPU time 137.81 seconds
Started May 14 02:09:04 PM PDT 24
Finished May 14 02:11:26 PM PDT 24
Peak memory 217412 kb
Host smart-72614543-a3c6-4500-a58f-ec0239317ad3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950072826 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.950072826
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.842926842
Short name T679
Test name
Test status
Simulation time 85928652 ps
CPU time 2.91 seconds
Started May 14 02:10:56 PM PDT 24
Finished May 14 02:11:01 PM PDT 24
Peak memory 219648 kb
Host smart-c8cd9407-b571-462b-8c38-46136c715ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842926842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.842926842
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3712342040
Short name T822
Test name
Test status
Simulation time 155788451 ps
CPU time 1.39 seconds
Started May 14 02:11:00 PM PDT 24
Finished May 14 02:11:04 PM PDT 24
Peak memory 218268 kb
Host smart-8e3f0427-1231-4272-bd72-048406fe36aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712342040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3712342040
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2694905088
Short name T812
Test name
Test status
Simulation time 77846327 ps
CPU time 1.44 seconds
Started May 14 02:11:01 PM PDT 24
Finished May 14 02:11:05 PM PDT 24
Peak memory 218304 kb
Host smart-5e407841-4d98-44cb-97ec-14c1ed71a59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694905088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2694905088
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1416745485
Short name T763
Test name
Test status
Simulation time 28574575 ps
CPU time 1.51 seconds
Started May 14 02:10:58 PM PDT 24
Finished May 14 02:11:02 PM PDT 24
Peak memory 216832 kb
Host smart-7ed71e5f-4646-4053-84c7-4731d153aa32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416745485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1416745485
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1084444367
Short name T275
Test name
Test status
Simulation time 38672438 ps
CPU time 1.48 seconds
Started May 14 02:10:58 PM PDT 24
Finished May 14 02:11:02 PM PDT 24
Peak memory 217740 kb
Host smart-8ec2543c-b0f7-41cf-9d0c-233d359a8b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084444367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1084444367
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2554962297
Short name T616
Test name
Test status
Simulation time 104837033 ps
CPU time 1.27 seconds
Started May 14 02:10:57 PM PDT 24
Finished May 14 02:11:01 PM PDT 24
Peak memory 217884 kb
Host smart-0a0830d2-8b7c-49a7-a396-c6f6a960219f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554962297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2554962297
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.4163884290
Short name T775
Test name
Test status
Simulation time 226436753 ps
CPU time 3.09 seconds
Started May 14 02:11:01 PM PDT 24
Finished May 14 02:11:08 PM PDT 24
Peak memory 217932 kb
Host smart-117a66f7-d34f-41b0-84e2-c48083a515af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163884290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.4163884290
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2878893318
Short name T501
Test name
Test status
Simulation time 57376522 ps
CPU time 1.71 seconds
Started May 14 02:10:59 PM PDT 24
Finished May 14 02:11:04 PM PDT 24
Peak memory 218104 kb
Host smart-8aae4cac-29c5-4d66-ab9a-5dfbe8fb86b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878893318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2878893318
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.655739265
Short name T9
Test name
Test status
Simulation time 225310898 ps
CPU time 1.67 seconds
Started May 14 02:10:59 PM PDT 24
Finished May 14 02:11:04 PM PDT 24
Peak memory 219528 kb
Host smart-b98b30e0-5a56-40b4-866f-1a8fbc863409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655739265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.655739265
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2804797233
Short name T529
Test name
Test status
Simulation time 277664548 ps
CPU time 4.22 seconds
Started May 14 02:10:57 PM PDT 24
Finished May 14 02:11:03 PM PDT 24
Peak memory 219600 kb
Host smart-b27b8589-7905-4991-a5b3-efdc959d3a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804797233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2804797233
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3190667202
Short name T76
Test name
Test status
Simulation time 36411018 ps
CPU time 1.14 seconds
Started May 14 02:07:50 PM PDT 24
Finished May 14 02:07:52 PM PDT 24
Peak memory 215260 kb
Host smart-41e3fe8f-15a4-47f7-b800-47f4bb77f032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190667202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3190667202
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1511079121
Short name T831
Test name
Test status
Simulation time 24667320 ps
CPU time 0.86 seconds
Started May 14 02:07:55 PM PDT 24
Finished May 14 02:07:57 PM PDT 24
Peak memory 206220 kb
Host smart-392e0df3-4ac1-4313-bd5d-0b094eecfda4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511079121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1511079121
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.4170388093
Short name T183
Test name
Test status
Simulation time 18790383 ps
CPU time 0.87 seconds
Started May 14 02:07:49 PM PDT 24
Finished May 14 02:07:51 PM PDT 24
Peak memory 216404 kb
Host smart-9b11d700-853f-4092-811a-e2119b930bfa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170388093 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.4170388093
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2318286412
Short name T741
Test name
Test status
Simulation time 30414978 ps
CPU time 1.1 seconds
Started May 14 02:07:51 PM PDT 24
Finished May 14 02:07:53 PM PDT 24
Peak memory 217892 kb
Host smart-58ad9cab-8fd9-4950-b50f-a58e102c3115
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318286412 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2318286412
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3706088182
Short name T207
Test name
Test status
Simulation time 19669383 ps
CPU time 1.1 seconds
Started May 14 02:07:51 PM PDT 24
Finished May 14 02:07:53 PM PDT 24
Peak memory 218016 kb
Host smart-f95c0757-8f21-48c2-81ac-63376527eeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706088182 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3706088182
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1537820583
Short name T361
Test name
Test status
Simulation time 36850838 ps
CPU time 1.44 seconds
Started May 14 02:07:46 PM PDT 24
Finished May 14 02:07:48 PM PDT 24
Peak memory 216772 kb
Host smart-8fc79647-0779-4302-97f2-cc5c00a94b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537820583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1537820583
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1243091998
Short name T409
Test name
Test status
Simulation time 20782189 ps
CPU time 1.1 seconds
Started May 14 02:07:47 PM PDT 24
Finished May 14 02:07:49 PM PDT 24
Peak memory 215176 kb
Host smart-6897bf4c-43bf-421a-9ac8-e48062e09c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243091998 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1243091998
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1378072297
Short name T257
Test name
Test status
Simulation time 26561566 ps
CPU time 0.98 seconds
Started May 14 02:07:50 PM PDT 24
Finished May 14 02:07:52 PM PDT 24
Peak memory 206792 kb
Host smart-e7372b5b-2c01-49ed-a5d6-9e807a8add3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378072297 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1378072297
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.775995084
Short name T17
Test name
Test status
Simulation time 696676992 ps
CPU time 7.63 seconds
Started May 14 02:07:55 PM PDT 24
Finished May 14 02:08:04 PM PDT 24
Peak memory 235716 kb
Host smart-e2b92bb2-6d5d-4ab4-9c59-3fc5d0d29c55
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775995084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.775995084
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2297576160
Short name T310
Test name
Test status
Simulation time 22054950 ps
CPU time 0.97 seconds
Started May 14 02:07:48 PM PDT 24
Finished May 14 02:07:50 PM PDT 24
Peak memory 206744 kb
Host smart-1ace39b8-6170-4686-9f66-68c8f21704fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297576160 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2297576160
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1759799602
Short name T519
Test name
Test status
Simulation time 821223095 ps
CPU time 5.25 seconds
Started May 14 02:07:46 PM PDT 24
Finished May 14 02:07:52 PM PDT 24
Peak memory 216664 kb
Host smart-b9438305-3a25-49ab-92ef-30d83b0dae5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759799602 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1759799602
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3776263064
Short name T692
Test name
Test status
Simulation time 57620108499 ps
CPU time 1341.34 seconds
Started May 14 02:07:45 PM PDT 24
Finished May 14 02:30:08 PM PDT 24
Peak memory 222820 kb
Host smart-1c1921be-a7fc-4131-ba41-bb0cff55f524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776263064 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3776263064
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.715299427
Short name T19
Test name
Test status
Simulation time 30245455 ps
CPU time 1.33 seconds
Started May 14 02:09:00 PM PDT 24
Finished May 14 02:09:05 PM PDT 24
Peak memory 215340 kb
Host smart-b93ddad1-ce1b-47bf-ae8a-579aef8a30bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715299427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.715299427
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3334620499
Short name T545
Test name
Test status
Simulation time 52427016 ps
CPU time 0.87 seconds
Started May 14 02:08:58 PM PDT 24
Finished May 14 02:09:02 PM PDT 24
Peak memory 205920 kb
Host smart-5ffcbb57-8128-4210-9124-ac35d8bbd91e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334620499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3334620499
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1951705310
Short name T718
Test name
Test status
Simulation time 36875337 ps
CPU time 0.89 seconds
Started May 14 02:08:56 PM PDT 24
Finished May 14 02:09:00 PM PDT 24
Peak memory 215660 kb
Host smart-23f99611-0530-400f-bb1e-aefac2020f6c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951705310 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1951705310
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.22115110
Short name T613
Test name
Test status
Simulation time 24006784 ps
CPU time 1.07 seconds
Started May 14 02:09:01 PM PDT 24
Finished May 14 02:09:06 PM PDT 24
Peak memory 216484 kb
Host smart-ae97628d-4c05-47b3-8fda-aa975af927fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22115110 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_dis
able_auto_req_mode.22115110
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3521917188
Short name T170
Test name
Test status
Simulation time 30028308 ps
CPU time 1.39 seconds
Started May 14 02:08:56 PM PDT 24
Finished May 14 02:09:00 PM PDT 24
Peak memory 219280 kb
Host smart-4904415e-49ac-4f7a-8682-2d8e192f6aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521917188 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3521917188
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.542163714
Short name T498
Test name
Test status
Simulation time 39287751 ps
CPU time 1.69 seconds
Started May 14 02:09:03 PM PDT 24
Finished May 14 02:09:09 PM PDT 24
Peak memory 217920 kb
Host smart-ce51abf0-0793-4160-b83e-bafeb02c64da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542163714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.542163714
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2484726720
Short name T838
Test name
Test status
Simulation time 20256929 ps
CPU time 1.08 seconds
Started May 14 02:09:00 PM PDT 24
Finished May 14 02:09:05 PM PDT 24
Peak memory 215364 kb
Host smart-cadd6743-e4e8-443a-933d-8defdf6b7b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484726720 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2484726720
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2703679805
Short name T439
Test name
Test status
Simulation time 44508700 ps
CPU time 1.04 seconds
Started May 14 02:09:04 PM PDT 24
Finished May 14 02:09:09 PM PDT 24
Peak memory 214748 kb
Host smart-4755df66-e4b9-4578-a8fd-5bb996220f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703679805 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2703679805
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3338575997
Short name T343
Test name
Test status
Simulation time 282731964 ps
CPU time 3.16 seconds
Started May 14 02:09:01 PM PDT 24
Finished May 14 02:09:08 PM PDT 24
Peak memory 216636 kb
Host smart-98390f40-f50c-4a44-bdf4-478c340f4069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338575997 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3338575997
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2721839661
Short name T555
Test name
Test status
Simulation time 209140973924 ps
CPU time 1406.01 seconds
Started May 14 02:09:00 PM PDT 24
Finished May 14 02:32:30 PM PDT 24
Peak memory 225752 kb
Host smart-de9ebdc2-6632-4e5c-81c2-033640fecd99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721839661 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2721839661
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1617121964
Short name T253
Test name
Test status
Simulation time 27027813 ps
CPU time 1.33 seconds
Started May 14 02:09:05 PM PDT 24
Finished May 14 02:09:10 PM PDT 24
Peak memory 215396 kb
Host smart-e192c783-499c-44d6-b5a1-9f023105c5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617121964 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1617121964
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2402227309
Short name T552
Test name
Test status
Simulation time 28166234 ps
CPU time 0.96 seconds
Started May 14 02:09:02 PM PDT 24
Finished May 14 02:09:07 PM PDT 24
Peak memory 206240 kb
Host smart-81f7d4fb-cf54-445e-9223-eab0f92843bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402227309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2402227309
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2222165738
Short name T548
Test name
Test status
Simulation time 29970418 ps
CPU time 0.88 seconds
Started May 14 02:09:11 PM PDT 24
Finished May 14 02:09:14 PM PDT 24
Peak memory 206972 kb
Host smart-baa078b9-884d-4f9e-b0aa-fb8d9d5f0f4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222165738 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2222165738
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3988691065
Short name T436
Test name
Test status
Simulation time 36203791 ps
CPU time 1.67 seconds
Started May 14 02:09:03 PM PDT 24
Finished May 14 02:09:09 PM PDT 24
Peak memory 216512 kb
Host smart-f351b71e-c158-40ea-8729-a94b2d8fc161
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988691065 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3988691065
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2979681951
Short name T61
Test name
Test status
Simulation time 19624293 ps
CPU time 1.12 seconds
Started May 14 02:09:03 PM PDT 24
Finished May 14 02:09:08 PM PDT 24
Peak memory 218248 kb
Host smart-2b099f3d-c258-45db-b2d5-10e8ee528cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979681951 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2979681951
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3043940109
Short name T286
Test name
Test status
Simulation time 133087011 ps
CPU time 1.96 seconds
Started May 14 02:09:11 PM PDT 24
Finished May 14 02:09:15 PM PDT 24
Peak memory 216900 kb
Host smart-4088aabb-523f-409a-827e-467747b65ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043940109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3043940109
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.4053922725
Short name T620
Test name
Test status
Simulation time 24129437 ps
CPU time 1.01 seconds
Started May 14 02:09:03 PM PDT 24
Finished May 14 02:09:08 PM PDT 24
Peak memory 215040 kb
Host smart-9ef6bb54-c781-47ff-a98d-c969da0a3447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053922725 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.4053922725
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2226913095
Short name T574
Test name
Test status
Simulation time 18599290 ps
CPU time 0.97 seconds
Started May 14 02:09:03 PM PDT 24
Finished May 14 02:09:07 PM PDT 24
Peak memory 214924 kb
Host smart-7f9c205b-3a01-42e4-b608-64c177113b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226913095 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2226913095
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.127906864
Short name T210
Test name
Test status
Simulation time 316732734 ps
CPU time 3.65 seconds
Started May 14 02:09:10 PM PDT 24
Finished May 14 02:09:15 PM PDT 24
Peak memory 216588 kb
Host smart-d91c173c-32b0-439d-a720-28c25d466b27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127906864 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.127906864
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3958118921
Short name T401
Test name
Test status
Simulation time 212069772972 ps
CPU time 1251.5 seconds
Started May 14 02:09:05 PM PDT 24
Finished May 14 02:30:00 PM PDT 24
Peak memory 222968 kb
Host smart-0841363a-212b-4df2-b8d9-3229b62421e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958118921 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3958118921
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert_test.3443295124
Short name T366
Test name
Test status
Simulation time 87232482 ps
CPU time 0.98 seconds
Started May 14 02:09:07 PM PDT 24
Finished May 14 02:09:11 PM PDT 24
Peak memory 214556 kb
Host smart-3032f093-9777-4edb-bb8c-5c110af9e5e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443295124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3443295124
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.624599750
Short name T646
Test name
Test status
Simulation time 12831961 ps
CPU time 0.92 seconds
Started May 14 02:09:03 PM PDT 24
Finished May 14 02:09:08 PM PDT 24
Peak memory 215796 kb
Host smart-82c1c5f1-769b-4f2a-91df-ef71cc8de914
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624599750 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.624599750
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2245515861
Short name T8
Test name
Test status
Simulation time 472948300 ps
CPU time 1.23 seconds
Started May 14 02:09:11 PM PDT 24
Finished May 14 02:09:15 PM PDT 24
Peak memory 216724 kb
Host smart-796e1a7d-befd-4750-9db5-3f412e9dce78
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245515861 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2245515861
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_genbits.3212471554
Short name T408
Test name
Test status
Simulation time 38007789 ps
CPU time 1.4 seconds
Started May 14 02:09:03 PM PDT 24
Finished May 14 02:09:08 PM PDT 24
Peak memory 216636 kb
Host smart-1dd85ad5-9fa4-4b45-a6cf-380bb574ad10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212471554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3212471554
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3457280256
Short name T544
Test name
Test status
Simulation time 41017091 ps
CPU time 0.93 seconds
Started May 14 02:09:03 PM PDT 24
Finished May 14 02:09:08 PM PDT 24
Peak memory 215200 kb
Host smart-d3c90220-3b61-475f-a991-fc8e7fdea19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457280256 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3457280256
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2055870164
Short name T641
Test name
Test status
Simulation time 30844428 ps
CPU time 1.01 seconds
Started May 14 02:09:04 PM PDT 24
Finished May 14 02:09:08 PM PDT 24
Peak memory 215016 kb
Host smart-0772d8e1-b02d-4da0-ae7f-efa059927053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055870164 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2055870164
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.607417493
Short name T241
Test name
Test status
Simulation time 377117755 ps
CPU time 7.5 seconds
Started May 14 02:09:11 PM PDT 24
Finished May 14 02:09:20 PM PDT 24
Peak memory 216808 kb
Host smart-10af406b-20ba-47af-9c10-761edae1e18c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607417493 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.607417493
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1183929853
Short name T567
Test name
Test status
Simulation time 23520699896 ps
CPU time 537.81 seconds
Started May 14 02:09:11 PM PDT 24
Finished May 14 02:18:11 PM PDT 24
Peak memory 217720 kb
Host smart-590dadaf-ba72-47dd-b505-96ad4b788eb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183929853 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1183929853
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1208396073
Short name T185
Test name
Test status
Simulation time 51362867 ps
CPU time 1.2 seconds
Started May 14 02:09:11 PM PDT 24
Finished May 14 02:09:14 PM PDT 24
Peak memory 215324 kb
Host smart-b1bf852f-3590-4b30-8526-846fc874068a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208396073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1208396073
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.268913417
Short name T546
Test name
Test status
Simulation time 44092159 ps
CPU time 1.36 seconds
Started May 14 02:09:12 PM PDT 24
Finished May 14 02:09:16 PM PDT 24
Peak memory 214600 kb
Host smart-1e581a13-f319-40cf-b488-a7f7920460e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268913417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.268913417
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3359959626
Short name T815
Test name
Test status
Simulation time 57983602 ps
CPU time 0.88 seconds
Started May 14 02:09:14 PM PDT 24
Finished May 14 02:09:17 PM PDT 24
Peak memory 215556 kb
Host smart-ffee3d48-c65f-4784-89ad-0696bd520a38
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359959626 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3359959626
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2002019991
Short name T765
Test name
Test status
Simulation time 64213359 ps
CPU time 1.2 seconds
Started May 14 02:09:16 PM PDT 24
Finished May 14 02:09:19 PM PDT 24
Peak memory 216452 kb
Host smart-78478be2-cf60-4eb1-b916-12ab85471829
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002019991 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2002019991
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1693908547
Short name T45
Test name
Test status
Simulation time 19381416 ps
CPU time 1.14 seconds
Started May 14 02:09:11 PM PDT 24
Finished May 14 02:09:15 PM PDT 24
Peak memory 217888 kb
Host smart-dcc49e66-d439-4510-b567-9c04bbbbb0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693908547 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1693908547
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3177218056
Short name T341
Test name
Test status
Simulation time 39601615 ps
CPU time 1.16 seconds
Started May 14 02:09:03 PM PDT 24
Finished May 14 02:09:08 PM PDT 24
Peak memory 217064 kb
Host smart-55e34a88-707a-45a0-826c-9ae1842bfab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177218056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3177218056
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3108355998
Short name T403
Test name
Test status
Simulation time 24340175 ps
CPU time 1.06 seconds
Started May 14 02:09:03 PM PDT 24
Finished May 14 02:09:09 PM PDT 24
Peak memory 223536 kb
Host smart-ac949322-4a43-43e9-9600-183dfd37367f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108355998 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3108355998
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2559068105
Short name T420
Test name
Test status
Simulation time 86477643 ps
CPU time 0.96 seconds
Started May 14 02:09:05 PM PDT 24
Finished May 14 02:09:10 PM PDT 24
Peak memory 215020 kb
Host smart-aa239841-504f-4d61-ae1d-79111f5e8d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559068105 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2559068105
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2257842699
Short name T821
Test name
Test status
Simulation time 268042716 ps
CPU time 5.38 seconds
Started May 14 02:09:04 PM PDT 24
Finished May 14 02:09:13 PM PDT 24
Peak memory 216588 kb
Host smart-47cb12d2-3e45-49b4-b3f3-661ee3cb81b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257842699 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2257842699
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_alert.2644880220
Short name T828
Test name
Test status
Simulation time 38045078 ps
CPU time 1.15 seconds
Started May 14 02:09:13 PM PDT 24
Finished May 14 02:09:16 PM PDT 24
Peak memory 215320 kb
Host smart-0394b50b-3115-47dd-a53f-2d378553cd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644880220 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2644880220
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2044339453
Short name T445
Test name
Test status
Simulation time 16116190 ps
CPU time 0.99 seconds
Started May 14 02:09:13 PM PDT 24
Finished May 14 02:09:17 PM PDT 24
Peak memory 214460 kb
Host smart-5ad4bc91-42b2-4924-8a8f-19fda7864b97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044339453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2044339453
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2698172668
Short name T586
Test name
Test status
Simulation time 31402136 ps
CPU time 0.94 seconds
Started May 14 02:09:14 PM PDT 24
Finished May 14 02:09:17 PM PDT 24
Peak memory 206996 kb
Host smart-7b84ea9b-f255-4b7d-a47a-4473a1640820
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698172668 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2698172668
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1821999754
Short name T41
Test name
Test status
Simulation time 28402370 ps
CPU time 1.07 seconds
Started May 14 02:09:10 PM PDT 24
Finished May 14 02:09:13 PM PDT 24
Peak memory 216444 kb
Host smart-99402e78-e837-45c1-881f-0298d2167700
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821999754 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1821999754
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.1475497561
Short name T651
Test name
Test status
Simulation time 19899284 ps
CPU time 1.08 seconds
Started May 14 02:09:14 PM PDT 24
Finished May 14 02:09:17 PM PDT 24
Peak memory 217848 kb
Host smart-0407feb0-56be-4fef-b38e-2e3c8434005f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475497561 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1475497561
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1894431921
Short name T814
Test name
Test status
Simulation time 56143461 ps
CPU time 1.29 seconds
Started May 14 02:09:13 PM PDT 24
Finished May 14 02:09:16 PM PDT 24
Peak memory 216600 kb
Host smart-f3f7d74c-bea5-458a-a784-733d92d2868d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894431921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1894431921
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2913392784
Short name T577
Test name
Test status
Simulation time 36927413 ps
CPU time 0.98 seconds
Started May 14 02:09:13 PM PDT 24
Finished May 14 02:09:17 PM PDT 24
Peak memory 215216 kb
Host smart-9cdef07e-b8c5-42ad-b8ac-b89270e529ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913392784 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2913392784
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2182456569
Short name T402
Test name
Test status
Simulation time 15198329 ps
CPU time 1 seconds
Started May 14 02:09:12 PM PDT 24
Finished May 14 02:09:15 PM PDT 24
Peak memory 214956 kb
Host smart-7ac4a5cb-d4fb-4acb-96c2-aabcba91d4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182456569 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2182456569
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1493348881
Short name T424
Test name
Test status
Simulation time 308604722 ps
CPU time 5.06 seconds
Started May 14 02:09:10 PM PDT 24
Finished May 14 02:09:17 PM PDT 24
Peak memory 216856 kb
Host smart-24a19c91-c9bf-43b7-84e6-bd49a2ac6ecf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493348881 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1493348881
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3000108455
Short name T554
Test name
Test status
Simulation time 25360690441 ps
CPU time 685.65 seconds
Started May 14 02:09:10 PM PDT 24
Finished May 14 02:20:38 PM PDT 24
Peak memory 223400 kb
Host smart-a8927e2e-943a-4844-9dae-8c987354857b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000108455 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3000108455
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2325327064
Short name T527
Test name
Test status
Simulation time 66760417 ps
CPU time 1.14 seconds
Started May 14 02:09:14 PM PDT 24
Finished May 14 02:09:17 PM PDT 24
Peak memory 215284 kb
Host smart-b1f8abf4-c023-453e-9edd-08fc858f0ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325327064 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2325327064
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2894257510
Short name T749
Test name
Test status
Simulation time 49787067 ps
CPU time 1.15 seconds
Started May 14 02:09:12 PM PDT 24
Finished May 14 02:09:15 PM PDT 24
Peak memory 214512 kb
Host smart-c084d92e-023c-4689-9fae-7bda41b00551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894257510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2894257510
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2778262251
Short name T387
Test name
Test status
Simulation time 39194097 ps
CPU time 0.92 seconds
Started May 14 02:09:12 PM PDT 24
Finished May 14 02:09:15 PM PDT 24
Peak memory 215420 kb
Host smart-51103d72-a1ea-4bd2-b230-837512ddd918
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778262251 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2778262251
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.329039623
Short name T727
Test name
Test status
Simulation time 86835848 ps
CPU time 1.04 seconds
Started May 14 02:09:14 PM PDT 24
Finished May 14 02:09:18 PM PDT 24
Peak memory 217860 kb
Host smart-9f873d39-82ba-4566-8177-34ce30d6a833
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329039623 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.329039623
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3670712069
Short name T832
Test name
Test status
Simulation time 23414461 ps
CPU time 1.08 seconds
Started May 14 02:09:13 PM PDT 24
Finished May 14 02:09:17 PM PDT 24
Peak memory 223368 kb
Host smart-6b92cf0f-a3ca-41c3-a2d7-84f1ec467556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670712069 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3670712069
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1716583939
Short name T333
Test name
Test status
Simulation time 97909890 ps
CPU time 1.16 seconds
Started May 14 02:09:12 PM PDT 24
Finished May 14 02:09:15 PM PDT 24
Peak memory 216852 kb
Host smart-ff0c5e66-41b3-4be6-85a1-6e1f999a3b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716583939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1716583939
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1876707703
Short name T110
Test name
Test status
Simulation time 23246271 ps
CPU time 1 seconds
Started May 14 02:09:14 PM PDT 24
Finished May 14 02:09:17 PM PDT 24
Peak memory 215380 kb
Host smart-f0dfbde4-adbd-4014-b0f3-5e6ecd4f2417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876707703 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1876707703
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3874550936
Short name T308
Test name
Test status
Simulation time 27522239 ps
CPU time 0.97 seconds
Started May 14 02:09:12 PM PDT 24
Finished May 14 02:09:15 PM PDT 24
Peak memory 214976 kb
Host smart-20ceb5f4-cc94-479a-94fb-1a455c54844b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874550936 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3874550936
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.3374002095
Short name T206
Test name
Test status
Simulation time 278009928 ps
CPU time 2.15 seconds
Started May 14 02:09:11 PM PDT 24
Finished May 14 02:09:15 PM PDT 24
Peak memory 219136 kb
Host smart-10956e50-c7e6-47cc-a941-e39284dc39a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374002095 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3374002095
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3283014455
Short name T193
Test name
Test status
Simulation time 92566325564 ps
CPU time 653.31 seconds
Started May 14 02:09:12 PM PDT 24
Finished May 14 02:20:08 PM PDT 24
Peak memory 219756 kb
Host smart-d3d81aa0-6eb5-4a10-a278-2189951c8332
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283014455 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3283014455
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2022646564
Short name T262
Test name
Test status
Simulation time 56703779 ps
CPU time 1.33 seconds
Started May 14 02:09:21 PM PDT 24
Finished May 14 02:09:25 PM PDT 24
Peak memory 215328 kb
Host smart-0cf3eed8-4df4-4095-ba34-7ec8750b283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022646564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2022646564
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1048940668
Short name T676
Test name
Test status
Simulation time 21508904 ps
CPU time 1 seconds
Started May 14 02:09:21 PM PDT 24
Finished May 14 02:09:24 PM PDT 24
Peak memory 206268 kb
Host smart-8108833c-1de6-4076-81f6-8c7f716a8fbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048940668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1048940668
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.857228333
Short name T172
Test name
Test status
Simulation time 28711811 ps
CPU time 0.86 seconds
Started May 14 02:09:21 PM PDT 24
Finished May 14 02:09:25 PM PDT 24
Peak memory 216140 kb
Host smart-584f6828-a82a-4054-b8aa-bb94acf052ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857228333 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.857228333
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1958783294
Short name T169
Test name
Test status
Simulation time 153091148 ps
CPU time 1.24 seconds
Started May 14 02:09:23 PM PDT 24
Finished May 14 02:09:27 PM PDT 24
Peak memory 216476 kb
Host smart-6dc3a407-16d8-4bf4-81a9-2f91358b67ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958783294 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1958783294
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.4018870798
Short name T824
Test name
Test status
Simulation time 22005918 ps
CPU time 1.01 seconds
Started May 14 02:09:20 PM PDT 24
Finished May 14 02:09:22 PM PDT 24
Peak memory 223448 kb
Host smart-8b34457d-05a4-4292-bf56-86fed0ef172e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018870798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.4018870798
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2243933878
Short name T453
Test name
Test status
Simulation time 58703358 ps
CPU time 1.27 seconds
Started May 14 02:09:19 PM PDT 24
Finished May 14 02:09:22 PM PDT 24
Peak memory 217692 kb
Host smart-775f3e6b-6d27-47d9-bddc-ec7addc053ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243933878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2243933878
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3009433251
Short name T411
Test name
Test status
Simulation time 30100318 ps
CPU time 1.13 seconds
Started May 14 02:09:20 PM PDT 24
Finished May 14 02:09:23 PM PDT 24
Peak memory 223568 kb
Host smart-73c09262-1070-4569-9784-01b3d197c1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009433251 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3009433251
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1574912343
Short name T724
Test name
Test status
Simulation time 32917518 ps
CPU time 0.98 seconds
Started May 14 02:09:22 PM PDT 24
Finished May 14 02:09:25 PM PDT 24
Peak memory 214908 kb
Host smart-9eb08556-3857-4395-a86d-3f0cf8253a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574912343 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1574912343
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1670370255
Short name T845
Test name
Test status
Simulation time 578995362 ps
CPU time 3.53 seconds
Started May 14 02:09:19 PM PDT 24
Finished May 14 02:09:24 PM PDT 24
Peak memory 216700 kb
Host smart-2628cc99-cb5d-4afd-bb90-414604536b61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670370255 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1670370255
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_alert.3598931654
Short name T252
Test name
Test status
Simulation time 87167004 ps
CPU time 1.29 seconds
Started May 14 02:09:21 PM PDT 24
Finished May 14 02:09:25 PM PDT 24
Peak memory 215336 kb
Host smart-f74fb711-9895-44c9-b311-a3613785c422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598931654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3598931654
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.299251433
Short name T340
Test name
Test status
Simulation time 46297042 ps
CPU time 1.03 seconds
Started May 14 02:09:20 PM PDT 24
Finished May 14 02:09:22 PM PDT 24
Peak memory 206196 kb
Host smart-96642b6e-2dda-4dca-a4e4-1f400ba40214
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299251433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.299251433
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2157604074
Short name T79
Test name
Test status
Simulation time 85540847 ps
CPU time 0.88 seconds
Started May 14 02:09:20 PM PDT 24
Finished May 14 02:09:22 PM PDT 24
Peak memory 215996 kb
Host smart-12de2ec1-4f50-48bf-9aa7-a7899efff6ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157604074 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2157604074
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2417901475
Short name T701
Test name
Test status
Simulation time 80281131 ps
CPU time 1.16 seconds
Started May 14 02:09:24 PM PDT 24
Finished May 14 02:09:29 PM PDT 24
Peak memory 219212 kb
Host smart-02f75278-15b6-4137-b4fa-381e3f65dc4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417901475 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2417901475
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3963886748
Short name T46
Test name
Test status
Simulation time 32408996 ps
CPU time 1.09 seconds
Started May 14 02:09:20 PM PDT 24
Finished May 14 02:09:22 PM PDT 24
Peak memory 219340 kb
Host smart-e7a59732-f8f6-4f33-92cf-a8b4b4f8ddfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963886748 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3963886748
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.4109699850
Short name T557
Test name
Test status
Simulation time 195156716 ps
CPU time 2.77 seconds
Started May 14 02:09:20 PM PDT 24
Finished May 14 02:09:24 PM PDT 24
Peak memory 217968 kb
Host smart-919a57c9-6614-4aaa-83cd-18d983e0fbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109699850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.4109699850
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1188500823
Short name T764
Test name
Test status
Simulation time 36231246 ps
CPU time 0.92 seconds
Started May 14 02:09:22 PM PDT 24
Finished May 14 02:09:25 PM PDT 24
Peak memory 215296 kb
Host smart-c43f35c5-aa63-4074-bb93-1d8eb3fb4eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188500823 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1188500823
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.424624515
Short name T105
Test name
Test status
Simulation time 17703113 ps
CPU time 0.97 seconds
Started May 14 02:09:20 PM PDT 24
Finished May 14 02:09:22 PM PDT 24
Peak memory 214928 kb
Host smart-ef46a8c3-5bd9-4c65-9847-262591b9de75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424624515 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.424624515
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2265566782
Short name T147
Test name
Test status
Simulation time 265243984 ps
CPU time 2.11 seconds
Started May 14 02:09:21 PM PDT 24
Finished May 14 02:09:26 PM PDT 24
Peak memory 216788 kb
Host smart-2caf897f-d2e6-4f72-8e2c-27a036d0602c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265566782 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2265566782
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2881136036
Short name T484
Test name
Test status
Simulation time 33627244642 ps
CPU time 241.64 seconds
Started May 14 02:09:20 PM PDT 24
Finished May 14 02:13:23 PM PDT 24
Peak memory 218492 kb
Host smart-f3660da4-17d0-4746-9632-54649ce6fb17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881136036 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2881136036
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.777352985
Short name T181
Test name
Test status
Simulation time 30563421 ps
CPU time 1.27 seconds
Started May 14 02:09:22 PM PDT 24
Finished May 14 02:09:25 PM PDT 24
Peak memory 215344 kb
Host smart-9ddd54de-e076-4d8e-97b3-241d00bf3944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777352985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.777352985
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1153772004
Short name T604
Test name
Test status
Simulation time 27456520 ps
CPU time 0.87 seconds
Started May 14 02:09:23 PM PDT 24
Finished May 14 02:09:28 PM PDT 24
Peak memory 206248 kb
Host smart-16d236ba-5750-4cb4-9b8a-3f6f9f42a9ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153772004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1153772004
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.681543854
Short name T375
Test name
Test status
Simulation time 75828688 ps
CPU time 1.07 seconds
Started May 14 02:09:24 PM PDT 24
Finished May 14 02:09:29 PM PDT 24
Peak memory 218960 kb
Host smart-c02686d6-4d3c-4af3-bfa9-105de13eaa54
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681543854 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.681543854
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3634345730
Short name T34
Test name
Test status
Simulation time 34149210 ps
CPU time 1.18 seconds
Started May 14 02:09:21 PM PDT 24
Finished May 14 02:09:24 PM PDT 24
Peak memory 220052 kb
Host smart-895e5070-b8d9-4c42-a010-13acbd295719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634345730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3634345730
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3599485229
Short name T634
Test name
Test status
Simulation time 47088588 ps
CPU time 1.12 seconds
Started May 14 02:09:20 PM PDT 24
Finished May 14 02:09:23 PM PDT 24
Peak memory 216780 kb
Host smart-1f7899cc-372d-45f2-9ef6-56a6c75e60f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599485229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3599485229
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3092363602
Short name T656
Test name
Test status
Simulation time 27821519 ps
CPU time 1.02 seconds
Started May 14 02:09:22 PM PDT 24
Finished May 14 02:09:25 PM PDT 24
Peak memory 215524 kb
Host smart-652b9c84-5ad4-4e39-a676-7aa2928d40c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092363602 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3092363602
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1550095556
Short name T337
Test name
Test status
Simulation time 53744517 ps
CPU time 0.96 seconds
Started May 14 02:09:21 PM PDT 24
Finished May 14 02:09:25 PM PDT 24
Peak memory 214956 kb
Host smart-29ed3611-72a3-4eed-8b7a-20b07447c13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550095556 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1550095556
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3419397358
Short name T512
Test name
Test status
Simulation time 271036394 ps
CPU time 3.02 seconds
Started May 14 02:09:22 PM PDT 24
Finished May 14 02:09:28 PM PDT 24
Peak memory 215072 kb
Host smart-1ef5c95d-f548-4b84-92d7-fc64d8a8f0b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419397358 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3419397358
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.509883459
Short name T188
Test name
Test status
Simulation time 403982787376 ps
CPU time 2474.45 seconds
Started May 14 02:09:20 PM PDT 24
Finished May 14 02:50:37 PM PDT 24
Peak memory 227896 kb
Host smart-20e2aeeb-0396-47f4-8bb3-54c3a47157ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509883459 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.509883459
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3361234314
Short name T156
Test name
Test status
Simulation time 72829820 ps
CPU time 1.28 seconds
Started May 14 02:09:23 PM PDT 24
Finished May 14 02:09:27 PM PDT 24
Peak memory 215288 kb
Host smart-8aa32060-fc68-4922-9b45-3e7fceb6800d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361234314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3361234314
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2475245095
Short name T813
Test name
Test status
Simulation time 11566575 ps
CPU time 0.9 seconds
Started May 14 02:09:24 PM PDT 24
Finished May 14 02:09:29 PM PDT 24
Peak memory 206280 kb
Host smart-5b5e65e0-eb40-4b78-a160-7f854449ec29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475245095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2475245095
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3512091343
Short name T101
Test name
Test status
Simulation time 33716309 ps
CPU time 0.91 seconds
Started May 14 02:09:24 PM PDT 24
Finished May 14 02:09:29 PM PDT 24
Peak memory 215744 kb
Host smart-2ce07db8-4966-403d-a317-ad99b10fe49e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512091343 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3512091343
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3853509950
Short name T639
Test name
Test status
Simulation time 180836447 ps
CPU time 1 seconds
Started May 14 02:09:23 PM PDT 24
Finished May 14 02:09:27 PM PDT 24
Peak memory 216764 kb
Host smart-8ec75668-31df-41a0-993c-48fc5e0659a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853509950 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3853509950
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3986801863
Short name T539
Test name
Test status
Simulation time 25774168 ps
CPU time 0.98 seconds
Started May 14 02:09:22 PM PDT 24
Finished May 14 02:09:26 PM PDT 24
Peak memory 219292 kb
Host smart-700396d1-226c-4e3c-97c8-c2b19a2dc516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986801863 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3986801863
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.4019120667
Short name T348
Test name
Test status
Simulation time 57020031 ps
CPU time 1.3 seconds
Started May 14 02:09:22 PM PDT 24
Finished May 14 02:09:26 PM PDT 24
Peak memory 218120 kb
Host smart-13eb8b3a-46fb-4bfa-a42d-768957392582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019120667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.4019120667
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3086317117
Short name T112
Test name
Test status
Simulation time 24200063 ps
CPU time 1.03 seconds
Started May 14 02:09:21 PM PDT 24
Finished May 14 02:09:25 PM PDT 24
Peak memory 215504 kb
Host smart-0e0457f9-bb62-441f-9854-a64cde1d7cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086317117 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3086317117
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1147564588
Short name T442
Test name
Test status
Simulation time 15303985 ps
CPU time 0.98 seconds
Started May 14 02:09:20 PM PDT 24
Finished May 14 02:09:23 PM PDT 24
Peak memory 215000 kb
Host smart-20c93090-23e5-4d52-97d8-638121560ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147564588 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1147564588
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3848130709
Short name T201
Test name
Test status
Simulation time 408568134 ps
CPU time 1.86 seconds
Started May 14 02:09:22 PM PDT 24
Finished May 14 02:09:27 PM PDT 24
Peak memory 206816 kb
Host smart-60f39df8-36d6-4db4-aeaf-f17fe57e3726
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848130709 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3848130709
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2781329614
Short name T152
Test name
Test status
Simulation time 84875361611 ps
CPU time 2143.54 seconds
Started May 14 02:09:22 PM PDT 24
Finished May 14 02:45:09 PM PDT 24
Peak memory 230040 kb
Host smart-7318ab1d-4d2b-49ab-87f6-cfe10285eab1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781329614 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2781329614
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3455942542
Short name T157
Test name
Test status
Simulation time 54314411 ps
CPU time 1.28 seconds
Started May 14 02:07:54 PM PDT 24
Finished May 14 02:07:57 PM PDT 24
Peak memory 215340 kb
Host smart-9a8a3b00-fc87-4281-9a51-19202a5847e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455942542 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3455942542
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3373176557
Short name T522
Test name
Test status
Simulation time 38108604 ps
CPU time 0.92 seconds
Started May 14 02:07:53 PM PDT 24
Finished May 14 02:07:55 PM PDT 24
Peak memory 214560 kb
Host smart-d46271f2-9a6a-499e-b4b7-160597e2a3b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373176557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3373176557
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2357753373
Short name T683
Test name
Test status
Simulation time 34338639 ps
CPU time 0.85 seconds
Started May 14 02:07:54 PM PDT 24
Finished May 14 02:07:56 PM PDT 24
Peak memory 215604 kb
Host smart-53e853d0-ff7a-41dd-8006-a45efdabd0ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357753373 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2357753373
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1707023018
Short name T54
Test name
Test status
Simulation time 24738900 ps
CPU time 1.06 seconds
Started May 14 02:07:56 PM PDT 24
Finished May 14 02:07:58 PM PDT 24
Peak memory 216596 kb
Host smart-a9766f82-6271-4dd4-b0c7-c760e777f8e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707023018 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1707023018
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3711738066
Short name T707
Test name
Test status
Simulation time 23921037 ps
CPU time 1 seconds
Started May 14 02:07:54 PM PDT 24
Finished May 14 02:07:56 PM PDT 24
Peak memory 219452 kb
Host smart-af78c882-ad13-4bd0-a2cd-ac69f16f3fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711738066 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3711738066
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1961441780
Short name T728
Test name
Test status
Simulation time 151810490 ps
CPU time 3.21 seconds
Started May 14 02:07:53 PM PDT 24
Finished May 14 02:07:57 PM PDT 24
Peak memory 219616 kb
Host smart-ba0ffdee-178f-47ec-a300-48160cb2220d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961441780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1961441780
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2637598233
Short name T690
Test name
Test status
Simulation time 22089709 ps
CPU time 1.16 seconds
Started May 14 02:07:54 PM PDT 24
Finished May 14 02:07:57 PM PDT 24
Peak memory 215380 kb
Host smart-405634ea-92b7-4d4f-aaa3-05b3cb33208b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637598233 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2637598233
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.3341295528
Short name T255
Test name
Test status
Simulation time 24012318 ps
CPU time 0.94 seconds
Started May 14 02:07:57 PM PDT 24
Finished May 14 02:07:59 PM PDT 24
Peak memory 206348 kb
Host smart-5066eebc-6f0a-496b-9362-c9cedd8282ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341295528 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3341295528
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.4278034476
Short name T133
Test name
Test status
Simulation time 4283222337 ps
CPU time 5.01 seconds
Started May 14 02:07:55 PM PDT 24
Finished May 14 02:08:01 PM PDT 24
Peak memory 236148 kb
Host smart-44084076-834d-4d6e-a291-c266d6fe703f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278034476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.4278034476
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3135543764
Short name T739
Test name
Test status
Simulation time 69437664 ps
CPU time 0.87 seconds
Started May 14 02:07:56 PM PDT 24
Finished May 14 02:07:58 PM PDT 24
Peak memory 214764 kb
Host smart-1b790cc0-a404-4e8a-ab68-0be9a3883af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135543764 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3135543764
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2912460469
Short name T582
Test name
Test status
Simulation time 559412981 ps
CPU time 6.71 seconds
Started May 14 02:07:54 PM PDT 24
Finished May 14 02:08:02 PM PDT 24
Peak memory 217780 kb
Host smart-c76dd5c6-a5c0-4333-8b28-f380c1f2d40d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912460469 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2912460469
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2957071822
Short name T268
Test name
Test status
Simulation time 101836487369 ps
CPU time 1253.33 seconds
Started May 14 02:07:53 PM PDT 24
Finished May 14 02:28:47 PM PDT 24
Peak memory 222560 kb
Host smart-3f09ca2b-cebf-49d1-902d-ca02a6d25a17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957071822 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2957071822
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2436150663
Short name T650
Test name
Test status
Simulation time 29278507 ps
CPU time 1.2 seconds
Started May 14 02:09:24 PM PDT 24
Finished May 14 02:09:29 PM PDT 24
Peak memory 215324 kb
Host smart-1f056e1a-bf70-4a95-a779-9717ba504a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436150663 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2436150663
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1544287572
Short name T846
Test name
Test status
Simulation time 36214086 ps
CPU time 0.99 seconds
Started May 14 02:09:22 PM PDT 24
Finished May 14 02:09:26 PM PDT 24
Peak memory 206248 kb
Host smart-0cf6cf9f-246d-4756-8874-5add7835d62d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544287572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1544287572
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3884621144
Short name T47
Test name
Test status
Simulation time 85182409 ps
CPU time 1.09 seconds
Started May 14 02:09:22 PM PDT 24
Finished May 14 02:09:26 PM PDT 24
Peak memory 216652 kb
Host smart-6c10224d-e45a-487a-adc7-00475017acf5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884621144 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3884621144
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1901160561
Short name T58
Test name
Test status
Simulation time 22532593 ps
CPU time 1 seconds
Started May 14 02:09:23 PM PDT 24
Finished May 14 02:09:28 PM PDT 24
Peak memory 218080 kb
Host smart-219f8fc8-6651-49fb-bef4-4bea96c90b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901160561 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1901160561
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1862887439
Short name T346
Test name
Test status
Simulation time 77743142 ps
CPU time 2.96 seconds
Started May 14 02:09:24 PM PDT 24
Finished May 14 02:09:31 PM PDT 24
Peak memory 219580 kb
Host smart-ea563b97-2ce4-4a38-840d-ff33027e0c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862887439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1862887439
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.659160114
Short name T482
Test name
Test status
Simulation time 22404972 ps
CPU time 1.14 seconds
Started May 14 02:09:24 PM PDT 24
Finished May 14 02:09:29 PM PDT 24
Peak memory 215032 kb
Host smart-b6d82f21-2ae0-4279-b929-c28f6513d045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659160114 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.659160114
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3612347630
Short name T367
Test name
Test status
Simulation time 16149766 ps
CPU time 0.99 seconds
Started May 14 02:09:24 PM PDT 24
Finished May 14 02:09:29 PM PDT 24
Peak memory 215004 kb
Host smart-95d72bd8-68f4-4f2b-8ad1-c69d2ba1c92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612347630 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3612347630
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3929266828
Short name T645
Test name
Test status
Simulation time 264875378 ps
CPU time 3.2 seconds
Started May 14 02:09:23 PM PDT 24
Finished May 14 02:09:30 PM PDT 24
Peak memory 216788 kb
Host smart-07f0b609-5ac6-4eee-a491-d60a7836a350
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929266828 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3929266828
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.606632702
Short name T194
Test name
Test status
Simulation time 775775595417 ps
CPU time 1963.6 seconds
Started May 14 02:09:22 PM PDT 24
Finished May 14 02:42:08 PM PDT 24
Peak memory 225504 kb
Host smart-db4d4d5f-b65a-43e7-ab01-709eab46d08b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606632702 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.606632702
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.273652959
Short name T721
Test name
Test status
Simulation time 24849501 ps
CPU time 1.16 seconds
Started May 14 02:09:25 PM PDT 24
Finished May 14 02:09:30 PM PDT 24
Peak memory 215328 kb
Host smart-5d8fc370-723e-4268-adcf-42a8f86ee333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273652959 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.273652959
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.308422172
Short name T665
Test name
Test status
Simulation time 45564429 ps
CPU time 0.97 seconds
Started May 14 02:09:32 PM PDT 24
Finished May 14 02:09:35 PM PDT 24
Peak memory 206312 kb
Host smart-31592ea5-5f48-4f91-af42-bbe7344829ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308422172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.308422172
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.115355023
Short name T92
Test name
Test status
Simulation time 10438263 ps
CPU time 0.85 seconds
Started May 14 02:09:29 PM PDT 24
Finished May 14 02:09:32 PM PDT 24
Peak memory 216032 kb
Host smart-e4dabb82-1183-452a-bee3-feb208b1fb0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115355023 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.115355023
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1090481588
Short name T352
Test name
Test status
Simulation time 54572144 ps
CPU time 1.07 seconds
Started May 14 02:09:29 PM PDT 24
Finished May 14 02:09:32 PM PDT 24
Peak memory 216464 kb
Host smart-36e1c3dd-9c97-468e-82ab-4cb0c0419394
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090481588 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1090481588
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.1374452572
Short name T208
Test name
Test status
Simulation time 20492894 ps
CPU time 1.15 seconds
Started May 14 02:09:20 PM PDT 24
Finished May 14 02:09:23 PM PDT 24
Peak memory 223424 kb
Host smart-e83a58d9-fb15-4531-8a77-28f7312cbd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374452572 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1374452572
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2933719478
Short name T818
Test name
Test status
Simulation time 334667667 ps
CPU time 3.58 seconds
Started May 14 02:09:25 PM PDT 24
Finished May 14 02:09:32 PM PDT 24
Peak memory 219156 kb
Host smart-939e786b-a939-44c3-9e18-f32a01cf3e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933719478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2933719478
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2076325976
Short name T13
Test name
Test status
Simulation time 23110708 ps
CPU time 1.25 seconds
Started May 14 02:09:25 PM PDT 24
Finished May 14 02:09:30 PM PDT 24
Peak memory 223548 kb
Host smart-57bf26b3-a4ce-4cc0-b991-1e2b048b88ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076325976 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2076325976
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.456036648
Short name T305
Test name
Test status
Simulation time 42914845 ps
CPU time 0.93 seconds
Started May 14 02:09:20 PM PDT 24
Finished May 14 02:09:23 PM PDT 24
Peak memory 214976 kb
Host smart-6170e1f9-b8b5-4b97-84d5-278ca265dbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456036648 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.456036648
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.685560023
Short name T561
Test name
Test status
Simulation time 308412238 ps
CPU time 6.43 seconds
Started May 14 02:09:23 PM PDT 24
Finished May 14 02:09:32 PM PDT 24
Peak memory 214900 kb
Host smart-fdd1e68a-4e46-461b-98e1-dae2f9c6823c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685560023 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.685560023
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.692633255
Short name T192
Test name
Test status
Simulation time 88928121754 ps
CPU time 487.24 seconds
Started May 14 02:09:25 PM PDT 24
Finished May 14 02:17:36 PM PDT 24
Peak memory 218620 kb
Host smart-bd6f39b6-5665-434b-9b85-59b3220a161f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692633255 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.692633255
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.104114302
Short name T456
Test name
Test status
Simulation time 28527899 ps
CPU time 1.28 seconds
Started May 14 02:09:30 PM PDT 24
Finished May 14 02:09:34 PM PDT 24
Peak memory 215340 kb
Host smart-dab448b9-6f2f-489b-a25d-7d4d8d5a94b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104114302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.104114302
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1441972110
Short name T321
Test name
Test status
Simulation time 71780760 ps
CPU time 0.89 seconds
Started May 14 02:09:29 PM PDT 24
Finished May 14 02:09:32 PM PDT 24
Peak memory 206204 kb
Host smart-08b1a50b-73fc-4383-8640-e9a8dcb89039
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441972110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1441972110
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3902619567
Short name T808
Test name
Test status
Simulation time 10552669 ps
CPU time 0.89 seconds
Started May 14 02:09:28 PM PDT 24
Finished May 14 02:09:32 PM PDT 24
Peak memory 216024 kb
Host smart-cf05aedd-0ad6-4d55-93c6-0b173d2fcf87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902619567 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3902619567
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3731650802
Short name T649
Test name
Test status
Simulation time 51285963 ps
CPU time 1.23 seconds
Started May 14 02:09:31 PM PDT 24
Finished May 14 02:09:35 PM PDT 24
Peak memory 216480 kb
Host smart-91f3d590-0051-4b63-b63c-ac79e6138e22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731650802 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3731650802
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1911983044
Short name T102
Test name
Test status
Simulation time 18289621 ps
CPU time 1.02 seconds
Started May 14 02:09:29 PM PDT 24
Finished May 14 02:09:32 PM PDT 24
Peak memory 218052 kb
Host smart-86f09468-54be-45c1-a2ed-be168dbb4a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911983044 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1911983044
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2858164476
Short name T336
Test name
Test status
Simulation time 91380458 ps
CPU time 1.36 seconds
Started May 14 02:09:30 PM PDT 24
Finished May 14 02:09:33 PM PDT 24
Peak memory 218252 kb
Host smart-d59bd1d1-508b-4397-8787-443426be2e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858164476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2858164476
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3661675538
Short name T160
Test name
Test status
Simulation time 26602416 ps
CPU time 0.98 seconds
Started May 14 02:09:29 PM PDT 24
Finished May 14 02:09:32 PM PDT 24
Peak memory 215404 kb
Host smart-96100c82-02b9-4661-9921-52c169af300e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661675538 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3661675538
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3327577073
Short name T204
Test name
Test status
Simulation time 19152347 ps
CPU time 1.01 seconds
Started May 14 02:09:30 PM PDT 24
Finished May 14 02:09:33 PM PDT 24
Peak memory 214948 kb
Host smart-794a82b1-957c-4dd5-826e-ab9c54c93dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327577073 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3327577073
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2705822096
Short name T637
Test name
Test status
Simulation time 144939891 ps
CPU time 1.34 seconds
Started May 14 02:09:28 PM PDT 24
Finished May 14 02:09:32 PM PDT 24
Peak memory 214868 kb
Host smart-17111633-56eb-4c80-94e0-ff653a964f4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705822096 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2705822096
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2205068992
Short name T702
Test name
Test status
Simulation time 242619130986 ps
CPU time 1523.54 seconds
Started May 14 02:09:27 PM PDT 24
Finished May 14 02:34:54 PM PDT 24
Peak memory 223904 kb
Host smart-2e4a4ead-c5e5-4bce-823b-31441d323fba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205068992 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2205068992
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2822087308
Short name T713
Test name
Test status
Simulation time 75160994 ps
CPU time 1.1 seconds
Started May 14 02:09:28 PM PDT 24
Finished May 14 02:09:32 PM PDT 24
Peak memory 215356 kb
Host smart-24389e70-bd01-4efc-984b-76e9d6d7dfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822087308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2822087308
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.4226024547
Short name T734
Test name
Test status
Simulation time 15582001 ps
CPU time 0.91 seconds
Started May 14 02:09:29 PM PDT 24
Finished May 14 02:09:32 PM PDT 24
Peak memory 206216 kb
Host smart-a8321ad6-5839-4cdb-8afa-814cffc0b5d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226024547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.4226024547
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.495780103
Short name T168
Test name
Test status
Simulation time 28318890 ps
CPU time 0.85 seconds
Started May 14 02:09:30 PM PDT 24
Finished May 14 02:09:33 PM PDT 24
Peak memory 215976 kb
Host smart-bc2b644f-f039-433b-8105-6d845701ce09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495780103 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.495780103
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_err.735872615
Short name T755
Test name
Test status
Simulation time 32283690 ps
CPU time 0.89 seconds
Started May 14 02:09:30 PM PDT 24
Finished May 14 02:09:33 PM PDT 24
Peak memory 218004 kb
Host smart-9a06e03d-695a-4a53-9575-9bc3776286d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735872615 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.735872615
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1756878615
Short name T138
Test name
Test status
Simulation time 55519091 ps
CPU time 1.27 seconds
Started May 14 02:09:29 PM PDT 24
Finished May 14 02:09:33 PM PDT 24
Peak memory 219136 kb
Host smart-2e385920-d6c5-441e-918c-f42895af4be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756878615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1756878615
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2883122840
Short name T145
Test name
Test status
Simulation time 21156045 ps
CPU time 1.07 seconds
Started May 14 02:09:30 PM PDT 24
Finished May 14 02:09:33 PM PDT 24
Peak memory 215332 kb
Host smart-110fee6c-a2ef-41af-9ca6-f0d259bca8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883122840 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2883122840
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.507560328
Short name T778
Test name
Test status
Simulation time 48336403 ps
CPU time 0.95 seconds
Started May 14 02:09:30 PM PDT 24
Finished May 14 02:09:33 PM PDT 24
Peak memory 214956 kb
Host smart-a1b83d2e-8d90-4a26-9f90-13ea40e1f29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507560328 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.507560328
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.477193675
Short name T150
Test name
Test status
Simulation time 402762341 ps
CPU time 6.12 seconds
Started May 14 02:09:32 PM PDT 24
Finished May 14 02:09:41 PM PDT 24
Peak memory 216716 kb
Host smart-7dffb694-79bb-43be-a309-67eca7966caf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477193675 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.477193675
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1403404397
Short name T575
Test name
Test status
Simulation time 297828029569 ps
CPU time 891.13 seconds
Started May 14 02:09:29 PM PDT 24
Finished May 14 02:24:23 PM PDT 24
Peak memory 221232 kb
Host smart-7d224114-f9be-4b6f-98ed-b753225082e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403404397 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1403404397
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.775446474
Short name T633
Test name
Test status
Simulation time 342424685 ps
CPU time 1.4 seconds
Started May 14 02:09:39 PM PDT 24
Finished May 14 02:09:42 PM PDT 24
Peak memory 215340 kb
Host smart-8f64b1b9-b383-4ab7-8ce1-93691e346ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775446474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.775446474
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2644467750
Short name T472
Test name
Test status
Simulation time 65459142 ps
CPU time 0.88 seconds
Started May 14 02:09:40 PM PDT 24
Finished May 14 02:09:44 PM PDT 24
Peak memory 206260 kb
Host smart-2484ad81-c0ff-4f49-bff5-09ab7f1d3490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644467750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2644467750
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1195300155
Short name T626
Test name
Test status
Simulation time 26077170 ps
CPU time 0.91 seconds
Started May 14 02:09:42 PM PDT 24
Finished May 14 02:09:46 PM PDT 24
Peak memory 216172 kb
Host smart-1097af1c-027f-4afc-87e1-6ddd858ed5cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195300155 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1195300155
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1692086390
Short name T697
Test name
Test status
Simulation time 63068622 ps
CPU time 1.13 seconds
Started May 14 02:09:40 PM PDT 24
Finished May 14 02:09:44 PM PDT 24
Peak memory 215304 kb
Host smart-9fffd82b-ae7a-4631-95dd-2773eae9f94e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692086390 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1692086390
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2536360854
Short name T797
Test name
Test status
Simulation time 25997631 ps
CPU time 0.96 seconds
Started May 14 02:09:40 PM PDT 24
Finished May 14 02:09:43 PM PDT 24
Peak memory 219392 kb
Host smart-0e931d96-d294-42ba-9dcb-2b3fd5761907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536360854 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2536360854
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.430441414
Short name T706
Test name
Test status
Simulation time 38989329 ps
CPU time 1.58 seconds
Started May 14 02:09:31 PM PDT 24
Finished May 14 02:09:36 PM PDT 24
Peak memory 216668 kb
Host smart-d3b3974f-e890-4062-904a-c48428a5821b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430441414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.430441414
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.514585296
Short name T791
Test name
Test status
Simulation time 22524102 ps
CPU time 1.13 seconds
Started May 14 02:09:30 PM PDT 24
Finished May 14 02:09:34 PM PDT 24
Peak memory 215244 kb
Host smart-feea9d26-953a-4f7a-afc2-823de87af8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514585296 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.514585296
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.820873202
Short name T757
Test name
Test status
Simulation time 19898624 ps
CPU time 0.97 seconds
Started May 14 02:09:29 PM PDT 24
Finished May 14 02:09:33 PM PDT 24
Peak memory 214972 kb
Host smart-df166e0e-03a2-4c26-9e54-d50e08557108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820873202 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.820873202
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1143068271
Short name T794
Test name
Test status
Simulation time 349163957 ps
CPU time 2.37 seconds
Started May 14 02:09:29 PM PDT 24
Finished May 14 02:09:34 PM PDT 24
Peak memory 216656 kb
Host smart-4369040f-b283-4070-b8a6-d7004487fc72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143068271 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1143068271
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1449854955
Short name T191
Test name
Test status
Simulation time 116803774892 ps
CPU time 1369.84 seconds
Started May 14 02:09:30 PM PDT 24
Finished May 14 02:32:22 PM PDT 24
Peak memory 225812 kb
Host smart-a7b1654d-b6cd-46e3-9894-3a24dd2a717a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449854955 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1449854955
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2292663791
Short name T699
Test name
Test status
Simulation time 50002740 ps
CPU time 1.15 seconds
Started May 14 02:09:38 PM PDT 24
Finished May 14 02:09:40 PM PDT 24
Peak memory 215344 kb
Host smart-f5e560c6-cb36-44ae-9192-a991f9ecff57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292663791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2292663791
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3523490022
Short name T415
Test name
Test status
Simulation time 14213777 ps
CPU time 0.96 seconds
Started May 14 02:09:42 PM PDT 24
Finished May 14 02:09:45 PM PDT 24
Peak memory 214448 kb
Host smart-28a9099f-445a-441b-b61d-122642d7d68c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523490022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3523490022
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.812996765
Short name T163
Test name
Test status
Simulation time 15774261 ps
CPU time 0.92 seconds
Started May 14 02:09:37 PM PDT 24
Finished May 14 02:09:39 PM PDT 24
Peak memory 216156 kb
Host smart-9e52f3df-8f15-477b-9cde-cb8b7f7ae929
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812996765 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.812996765
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_err.203758248
Short name T672
Test name
Test status
Simulation time 33907910 ps
CPU time 0.98 seconds
Started May 14 02:09:42 PM PDT 24
Finished May 14 02:09:45 PM PDT 24
Peak memory 223260 kb
Host smart-30a99bf3-5da7-42b8-a91c-f01bf7d7d49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203758248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.203758248
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.4291220018
Short name T370
Test name
Test status
Simulation time 27756482 ps
CPU time 1.25 seconds
Started May 14 02:09:42 PM PDT 24
Finished May 14 02:09:46 PM PDT 24
Peak memory 217896 kb
Host smart-9b55c3d8-259f-466f-bf4c-2806adb1c33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291220018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.4291220018
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.951635504
Short name T142
Test name
Test status
Simulation time 21004058 ps
CPU time 1.12 seconds
Started May 14 02:09:39 PM PDT 24
Finished May 14 02:09:42 PM PDT 24
Peak memory 215304 kb
Host smart-b50c2403-5762-4990-ba78-6aba7067493e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951635504 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.951635504
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.4123015061
Short name T691
Test name
Test status
Simulation time 16768565 ps
CPU time 0.98 seconds
Started May 14 02:09:39 PM PDT 24
Finished May 14 02:09:42 PM PDT 24
Peak memory 214932 kb
Host smart-daeff079-ce31-4f46-8305-53df8d1aa77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123015061 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.4123015061
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.18617467
Short name T481
Test name
Test status
Simulation time 531301800 ps
CPU time 1.41 seconds
Started May 14 02:09:38 PM PDT 24
Finished May 14 02:09:41 PM PDT 24
Peak memory 214952 kb
Host smart-8b3f6032-2ae9-4df7-a2b2-a194740394ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18617467 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.18617467
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.704399567
Short name T756
Test name
Test status
Simulation time 60607497898 ps
CPU time 1614.13 seconds
Started May 14 02:09:40 PM PDT 24
Finished May 14 02:36:37 PM PDT 24
Peak memory 224416 kb
Host smart-41ef6b86-d391-4c7c-8ebe-187337ff9161
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704399567 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.704399567
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.4102612003
Short name T68
Test name
Test status
Simulation time 75685998 ps
CPU time 1.21 seconds
Started May 14 02:09:41 PM PDT 24
Finished May 14 02:09:45 PM PDT 24
Peak memory 215320 kb
Host smart-6afb7f1f-fe3e-4bc0-8a89-be1903816dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102612003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.4102612003
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1954186705
Short name T591
Test name
Test status
Simulation time 17139149 ps
CPU time 0.82 seconds
Started May 14 02:09:43 PM PDT 24
Finished May 14 02:09:46 PM PDT 24
Peak memory 205972 kb
Host smart-b05d7a86-1e19-4a36-ac88-47c0ecf10666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954186705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1954186705
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1040965846
Short name T84
Test name
Test status
Simulation time 47840359 ps
CPU time 0.88 seconds
Started May 14 02:09:41 PM PDT 24
Finished May 14 02:09:44 PM PDT 24
Peak memory 216052 kb
Host smart-dac2fb2f-7b74-41e0-8d38-7d03c6594d7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040965846 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1040965846
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.634069789
Short name T49
Test name
Test status
Simulation time 83268427 ps
CPU time 1.03 seconds
Started May 14 02:09:38 PM PDT 24
Finished May 14 02:09:40 PM PDT 24
Peak memory 216604 kb
Host smart-ff024c99-3b06-4715-9f73-5a136abd7ba2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634069789 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.634069789
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1575855164
Short name T708
Test name
Test status
Simulation time 61076271 ps
CPU time 0.89 seconds
Started May 14 02:09:40 PM PDT 24
Finished May 14 02:09:43 PM PDT 24
Peak memory 218024 kb
Host smart-cccffc69-3784-4d77-b245-d6db81af285b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575855164 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1575855164
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2177854037
Short name T503
Test name
Test status
Simulation time 68422800 ps
CPU time 1.32 seconds
Started May 14 02:09:43 PM PDT 24
Finished May 14 02:09:47 PM PDT 24
Peak memory 216976 kb
Host smart-b6518550-0ff5-4268-8894-e80cac9fdafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177854037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2177854037
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.12384347
Short name T597
Test name
Test status
Simulation time 89370484 ps
CPU time 0.95 seconds
Started May 14 02:09:41 PM PDT 24
Finished May 14 02:09:44 PM PDT 24
Peak memory 214868 kb
Host smart-2279b987-a919-4559-97fb-02a05f1149dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12384347 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.12384347
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1180292830
Short name T451
Test name
Test status
Simulation time 34213679 ps
CPU time 0.94 seconds
Started May 14 02:09:39 PM PDT 24
Finished May 14 02:09:42 PM PDT 24
Peak memory 214956 kb
Host smart-1a81652c-3f1a-4a3d-a058-2abd240fd561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180292830 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1180292830
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.665754888
Short name T660
Test name
Test status
Simulation time 827985605 ps
CPU time 5.9 seconds
Started May 14 02:09:40 PM PDT 24
Finished May 14 02:09:49 PM PDT 24
Peak memory 216700 kb
Host smart-e8f57268-010e-4a1c-b39e-3d4aa17a8950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665754888 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.665754888
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3070639447
Short name T199
Test name
Test status
Simulation time 24896365722 ps
CPU time 567.4 seconds
Started May 14 02:09:39 PM PDT 24
Finished May 14 02:19:08 PM PDT 24
Peak memory 219216 kb
Host smart-0a3f259a-1fcb-4980-a9b7-2cdd07f79bb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070639447 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3070639447
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert_test.1232250247
Short name T705
Test name
Test status
Simulation time 14000855 ps
CPU time 0.96 seconds
Started May 14 02:09:41 PM PDT 24
Finished May 14 02:09:44 PM PDT 24
Peak memory 214408 kb
Host smart-72592999-444b-44a9-8234-6f5d5b0d6dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232250247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1232250247
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.711053647
Short name T521
Test name
Test status
Simulation time 16214952 ps
CPU time 0.98 seconds
Started May 14 02:09:41 PM PDT 24
Finished May 14 02:09:45 PM PDT 24
Peak memory 215848 kb
Host smart-1ae91c7a-00c8-4e06-b3d7-ddb057e85e07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711053647 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.711053647
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1392234922
Short name T801
Test name
Test status
Simulation time 41151844 ps
CPU time 1.08 seconds
Started May 14 02:09:40 PM PDT 24
Finished May 14 02:09:44 PM PDT 24
Peak memory 217720 kb
Host smart-d14ea34a-1a5b-4ad2-971f-5da08240667e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392234922 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1392234922
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.364373011
Short name T175
Test name
Test status
Simulation time 32718419 ps
CPU time 1.44 seconds
Started May 14 02:09:37 PM PDT 24
Finished May 14 02:09:40 PM PDT 24
Peak memory 225136 kb
Host smart-632318e2-7204-4b06-8fda-6068ae04898e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364373011 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.364373011
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.232687003
Short name T378
Test name
Test status
Simulation time 66866411 ps
CPU time 2.4 seconds
Started May 14 02:09:43 PM PDT 24
Finished May 14 02:09:48 PM PDT 24
Peak memory 219616 kb
Host smart-402d45ad-4954-4b3e-861f-98e2cee10a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232687003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.232687003
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.836659604
Short name T685
Test name
Test status
Simulation time 23877910 ps
CPU time 1.16 seconds
Started May 14 02:09:38 PM PDT 24
Finished May 14 02:09:41 PM PDT 24
Peak memory 215324 kb
Host smart-72f9e813-81fd-4d4b-88fc-52623d2758be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836659604 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.836659604
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1356967031
Short name T430
Test name
Test status
Simulation time 19070386 ps
CPU time 1.01 seconds
Started May 14 02:09:40 PM PDT 24
Finished May 14 02:09:43 PM PDT 24
Peak memory 214964 kb
Host smart-c6ac8b27-99ab-4273-a1c3-bd61f45d1f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356967031 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1356967031
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.389563640
Short name T663
Test name
Test status
Simulation time 424127422 ps
CPU time 4.76 seconds
Started May 14 02:09:38 PM PDT 24
Finished May 14 02:09:45 PM PDT 24
Peak memory 215112 kb
Host smart-e0aa3016-a32d-4e67-83f2-9735845bd254
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389563640 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.389563640
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.998821980
Short name T437
Test name
Test status
Simulation time 589269467277 ps
CPU time 1929.75 seconds
Started May 14 02:09:39 PM PDT 24
Finished May 14 02:41:51 PM PDT 24
Peak memory 227036 kb
Host smart-f00c8843-f1bf-4aa4-9acd-fe071656ff0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998821980 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.998821980
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1555700168
Short name T182
Test name
Test status
Simulation time 85885687 ps
CPU time 1.12 seconds
Started May 14 02:09:40 PM PDT 24
Finished May 14 02:09:43 PM PDT 24
Peak memory 215324 kb
Host smart-f58c25b9-d499-4b6e-89b9-697cd554bdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555700168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1555700168
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.575012268
Short name T433
Test name
Test status
Simulation time 55886104 ps
CPU time 0.92 seconds
Started May 14 02:09:39 PM PDT 24
Finished May 14 02:09:43 PM PDT 24
Peak memory 206268 kb
Host smart-826529fe-24c8-49ee-aefb-97ec69ad2f08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575012268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.575012268
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.61320137
Short name T83
Test name
Test status
Simulation time 14331877 ps
CPU time 0.96 seconds
Started May 14 02:09:41 PM PDT 24
Finished May 14 02:09:45 PM PDT 24
Peak memory 216208 kb
Host smart-9e4187d1-8cb0-46b2-8d40-e6f9baede147
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61320137 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.61320137
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2484312667
Short name T758
Test name
Test status
Simulation time 34791918 ps
CPU time 1.24 seconds
Started May 14 02:09:43 PM PDT 24
Finished May 14 02:09:47 PM PDT 24
Peak memory 218284 kb
Host smart-423fbddc-9bcc-418e-a77c-d8cd53ff22a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484312667 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2484312667
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3255017833
Short name T26
Test name
Test status
Simulation time 22395502 ps
CPU time 1.04 seconds
Started May 14 02:09:42 PM PDT 24
Finished May 14 02:09:45 PM PDT 24
Peak memory 219112 kb
Host smart-1c794ee9-b38c-4c22-bfb5-3d562c215b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255017833 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3255017833
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2800168142
Short name T773
Test name
Test status
Simulation time 57240872 ps
CPU time 2.29 seconds
Started May 14 02:09:43 PM PDT 24
Finished May 14 02:09:48 PM PDT 24
Peak memory 219168 kb
Host smart-60669b6e-767b-463f-be3a-3d55ff81a809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800168142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2800168142
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2759653464
Short name T464
Test name
Test status
Simulation time 39338584 ps
CPU time 1.02 seconds
Started May 14 02:09:36 PM PDT 24
Finished May 14 02:09:38 PM PDT 24
Peak memory 215024 kb
Host smart-5d7a8c48-28fc-4793-b077-f29f4d7bb901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759653464 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2759653464
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2909182096
Short name T355
Test name
Test status
Simulation time 49379379 ps
CPU time 0.94 seconds
Started May 14 02:09:44 PM PDT 24
Finished May 14 02:09:46 PM PDT 24
Peak memory 214900 kb
Host smart-11718d6d-e982-42b7-9510-bc5795c43990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909182096 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2909182096
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.4188494330
Short name T99
Test name
Test status
Simulation time 977739561 ps
CPU time 4.51 seconds
Started May 14 02:09:40 PM PDT 24
Finished May 14 02:09:47 PM PDT 24
Peak memory 216692 kb
Host smart-86440863-f8ce-436f-911f-a1ca6f04eceb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188494330 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.4188494330
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.4215081297
Short name T198
Test name
Test status
Simulation time 30882171115 ps
CPU time 645.8 seconds
Started May 14 02:09:40 PM PDT 24
Finished May 14 02:20:29 PM PDT 24
Peak memory 218584 kb
Host smart-f4af1619-2578-4e5b-9fea-a25eb7423360
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215081297 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.4215081297
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2886751052
Short name T251
Test name
Test status
Simulation time 101962220 ps
CPU time 1.28 seconds
Started May 14 02:09:41 PM PDT 24
Finished May 14 02:09:45 PM PDT 24
Peak memory 215328 kb
Host smart-2a1ec047-caca-4cff-8580-03b070cf716f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886751052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2886751052
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.440153764
Short name T777
Test name
Test status
Simulation time 24065170 ps
CPU time 0.91 seconds
Started May 14 02:09:49 PM PDT 24
Finished May 14 02:09:52 PM PDT 24
Peak memory 206248 kb
Host smart-b953055d-5e6c-4212-b5d8-a0166c70d200
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440153764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.440153764
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3660464527
Short name T78
Test name
Test status
Simulation time 25578407 ps
CPU time 0.83 seconds
Started May 14 02:09:40 PM PDT 24
Finished May 14 02:09:43 PM PDT 24
Peak memory 215996 kb
Host smart-de2db524-ae75-4720-9818-6f0619b04aa8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660464527 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3660464527
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1267747890
Short name T438
Test name
Test status
Simulation time 156582418 ps
CPU time 1.01 seconds
Started May 14 02:09:49 PM PDT 24
Finished May 14 02:09:52 PM PDT 24
Peak memory 217956 kb
Host smart-028934b4-c89b-44c4-b387-2d78f8815053
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267747890 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1267747890
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1190170999
Short name T43
Test name
Test status
Simulation time 24020324 ps
CPU time 1 seconds
Started May 14 02:09:38 PM PDT 24
Finished May 14 02:09:40 PM PDT 24
Peak memory 218068 kb
Host smart-806fa36c-ad82-4733-a901-cd526a3cfb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190170999 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1190170999
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.4055243748
Short name T486
Test name
Test status
Simulation time 29608324 ps
CPU time 1.48 seconds
Started May 14 02:09:44 PM PDT 24
Finished May 14 02:09:47 PM PDT 24
Peak memory 216680 kb
Host smart-9898220b-2d7a-4e52-b97f-5607bc4f9b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055243748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.4055243748
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3240312686
Short name T792
Test name
Test status
Simulation time 38056319 ps
CPU time 0.91 seconds
Started May 14 02:09:40 PM PDT 24
Finished May 14 02:09:43 PM PDT 24
Peak memory 215224 kb
Host smart-91ecc324-239f-43a8-b9e2-ffdb6b9971d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240312686 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3240312686
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2540052135
Short name T319
Test name
Test status
Simulation time 22440528 ps
CPU time 1 seconds
Started May 14 02:09:39 PM PDT 24
Finished May 14 02:09:43 PM PDT 24
Peak memory 214996 kb
Host smart-0c62c369-bbc8-4226-8c63-0839f1fab4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540052135 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2540052135
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.72474260
Short name T532
Test name
Test status
Simulation time 205619416 ps
CPU time 4.38 seconds
Started May 14 02:09:40 PM PDT 24
Finished May 14 02:09:47 PM PDT 24
Peak memory 216600 kb
Host smart-953a95b4-093f-4d39-80d4-7fa94d18dfdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72474260 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.72474260
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2005388847
Short name T827
Test name
Test status
Simulation time 82328804417 ps
CPU time 2118.92 seconds
Started May 14 02:09:40 PM PDT 24
Finished May 14 02:45:02 PM PDT 24
Peak memory 229608 kb
Host smart-30d496fb-6786-4056-971e-27345250ce80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005388847 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2005388847
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.884858858
Short name T819
Test name
Test status
Simulation time 47043752 ps
CPU time 1.22 seconds
Started May 14 02:07:58 PM PDT 24
Finished May 14 02:08:00 PM PDT 24
Peak memory 215388 kb
Host smart-cd9ebd4a-09c7-4410-a9e9-f0f79b4274f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884858858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.884858858
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1150241615
Short name T397
Test name
Test status
Simulation time 64727078 ps
CPU time 1.02 seconds
Started May 14 02:07:53 PM PDT 24
Finished May 14 02:07:54 PM PDT 24
Peak memory 214508 kb
Host smart-48e0afb3-a163-4bd4-9612-96299cbbed8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150241615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1150241615
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3992716420
Short name T457
Test name
Test status
Simulation time 13038836 ps
CPU time 0.91 seconds
Started May 14 02:07:57 PM PDT 24
Finished May 14 02:07:59 PM PDT 24
Peak memory 215432 kb
Host smart-89aea792-ff8a-45f7-810d-36869ce61f09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992716420 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3992716420
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.83081712
Short name T48
Test name
Test status
Simulation time 42941904 ps
CPU time 1.33 seconds
Started May 14 02:07:58 PM PDT 24
Finished May 14 02:08:00 PM PDT 24
Peak memory 216696 kb
Host smart-531eb039-ab32-4f50-a9a1-21c3469dd6b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83081712 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disa
ble_auto_req_mode.83081712
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1070266261
Short name T799
Test name
Test status
Simulation time 169301298 ps
CPU time 1.03 seconds
Started May 14 02:07:58 PM PDT 24
Finished May 14 02:08:00 PM PDT 24
Peak memory 218596 kb
Host smart-d508f1b4-f57b-4b94-8db8-56323034b07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070266261 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1070266261
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3163496982
Short name T128
Test name
Test status
Simulation time 57682258 ps
CPU time 1.98 seconds
Started May 14 02:07:56 PM PDT 24
Finished May 14 02:07:59 PM PDT 24
Peak memory 218008 kb
Host smart-2f153f9a-bea8-4e0e-b8e2-a5556a90a69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163496982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3163496982
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3686409253
Short name T311
Test name
Test status
Simulation time 39266448 ps
CPU time 0.89 seconds
Started May 14 02:07:56 PM PDT 24
Finished May 14 02:07:58 PM PDT 24
Peak memory 215244 kb
Host smart-d94a0e77-bb1b-469c-86f6-e23ee4ffe82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686409253 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3686409253
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_smoke.4008854983
Short name T148
Test name
Test status
Simulation time 17558032 ps
CPU time 1 seconds
Started May 14 02:07:54 PM PDT 24
Finished May 14 02:07:56 PM PDT 24
Peak memory 214952 kb
Host smart-4316b830-37ea-4ade-8d4c-adf26e99a1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008854983 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.4008854983
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.4078922891
Short name T446
Test name
Test status
Simulation time 309969305 ps
CPU time 3.58 seconds
Started May 14 02:07:54 PM PDT 24
Finished May 14 02:07:59 PM PDT 24
Peak memory 215020 kb
Host smart-95bbb2c4-04c5-444e-bb06-041638131d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078922891 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.4078922891
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.521232630
Short name T407
Test name
Test status
Simulation time 462383618510 ps
CPU time 1260.27 seconds
Started May 14 02:07:56 PM PDT 24
Finished May 14 02:28:57 PM PDT 24
Peak memory 223152 kb
Host smart-7c30b0bb-8797-492b-aa7e-9c317f2481e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521232630 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.521232630
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.4107300953
Short name T7
Test name
Test status
Simulation time 49502712 ps
CPU time 0.9 seconds
Started May 14 02:09:53 PM PDT 24
Finished May 14 02:09:56 PM PDT 24
Peak memory 219476 kb
Host smart-d9676812-6a1c-4c94-9a74-6f3cf4e05761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107300953 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.4107300953
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.822468872
Short name T141
Test name
Test status
Simulation time 32973660 ps
CPU time 1.29 seconds
Started May 14 02:09:48 PM PDT 24
Finished May 14 02:09:51 PM PDT 24
Peak memory 216544 kb
Host smart-d7c5bfec-1638-4994-acf9-7e9074da3d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822468872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.822468872
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.3715048776
Short name T573
Test name
Test status
Simulation time 111866003 ps
CPU time 1.1 seconds
Started May 14 02:09:52 PM PDT 24
Finished May 14 02:09:55 PM PDT 24
Peak memory 220284 kb
Host smart-09fb695d-0f03-45ee-a078-a9c495b60b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715048776 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3715048776
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.4217458201
Short name T780
Test name
Test status
Simulation time 78887200 ps
CPU time 1.7 seconds
Started May 14 02:09:49 PM PDT 24
Finished May 14 02:09:52 PM PDT 24
Peak memory 218096 kb
Host smart-c098612d-7005-4447-a22a-438afc59cb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217458201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.4217458201
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.976135543
Short name T725
Test name
Test status
Simulation time 62240729 ps
CPU time 1.14 seconds
Started May 14 02:09:50 PM PDT 24
Finished May 14 02:09:54 PM PDT 24
Peak memory 217260 kb
Host smart-705ceea6-2d36-4892-8590-e678d6db9858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976135543 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.976135543
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.644782976
Short name T271
Test name
Test status
Simulation time 111751530 ps
CPU time 1.53 seconds
Started May 14 02:09:49 PM PDT 24
Finished May 14 02:09:52 PM PDT 24
Peak memory 217932 kb
Host smart-2d339330-f970-4f0b-89ed-2a5397127451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644782976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.644782976
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.2597738287
Short name T159
Test name
Test status
Simulation time 25428254 ps
CPU time 0.95 seconds
Started May 14 02:09:49 PM PDT 24
Finished May 14 02:09:52 PM PDT 24
Peak memory 218228 kb
Host smart-21521345-b900-4299-83a9-93a06e039507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597738287 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2597738287
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.875455424
Short name T428
Test name
Test status
Simulation time 166953701 ps
CPU time 1.76 seconds
Started May 14 02:09:52 PM PDT 24
Finished May 14 02:09:56 PM PDT 24
Peak memory 219188 kb
Host smart-47474046-dd30-4396-972d-108f07de6ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875455424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.875455424
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.434609928
Short name T309
Test name
Test status
Simulation time 35077771 ps
CPU time 1.16 seconds
Started May 14 02:09:50 PM PDT 24
Finished May 14 02:09:53 PM PDT 24
Peak memory 218408 kb
Host smart-42bf97c1-39a1-462a-bd19-8b7b88a74227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434609928 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.434609928
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3501324002
Short name T494
Test name
Test status
Simulation time 99203148 ps
CPU time 1.56 seconds
Started May 14 02:09:49 PM PDT 24
Finished May 14 02:09:53 PM PDT 24
Peak memory 218040 kb
Host smart-e9e91e89-f726-4ca0-85aa-4dae339182cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501324002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3501324002
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.21044338
Short name T825
Test name
Test status
Simulation time 53616141 ps
CPU time 1.23 seconds
Started May 14 02:09:49 PM PDT 24
Finished May 14 02:09:52 PM PDT 24
Peak memory 219100 kb
Host smart-496de0a3-cfb5-405a-88aa-c37fb22345bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21044338 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.21044338
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2369030654
Short name T475
Test name
Test status
Simulation time 2193285975 ps
CPU time 71.9 seconds
Started May 14 02:09:53 PM PDT 24
Finished May 14 02:11:07 PM PDT 24
Peak memory 219684 kb
Host smart-c11ebc60-8652-44dd-90ad-960289c301ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369030654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2369030654
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.3883189245
Short name T590
Test name
Test status
Simulation time 29328813 ps
CPU time 0.9 seconds
Started May 14 02:09:50 PM PDT 24
Finished May 14 02:09:53 PM PDT 24
Peak memory 218000 kb
Host smart-6653ef08-bb67-48d1-a1a7-3ddbc81fdfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883189245 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3883189245
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2660068211
Short name T524
Test name
Test status
Simulation time 55001017 ps
CPU time 1.46 seconds
Started May 14 02:09:49 PM PDT 24
Finished May 14 02:09:52 PM PDT 24
Peak memory 218112 kb
Host smart-c871d57c-5f28-43bc-bfa5-f11d37c7d523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660068211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2660068211
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.3840336111
Short name T526
Test name
Test status
Simulation time 258723258 ps
CPU time 1.27 seconds
Started May 14 02:09:50 PM PDT 24
Finished May 14 02:09:53 PM PDT 24
Peak memory 224948 kb
Host smart-ec72f66e-3fa1-4cf4-be98-6daf3e891514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840336111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3840336111
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.4067648922
Short name T272
Test name
Test status
Simulation time 72921822 ps
CPU time 1.35 seconds
Started May 14 02:09:53 PM PDT 24
Finished May 14 02:09:56 PM PDT 24
Peak memory 218220 kb
Host smart-4ec28f0a-d757-486a-837a-9b54d830653e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067648922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.4067648922
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2295763251
Short name T39
Test name
Test status
Simulation time 23678623 ps
CPU time 1.18 seconds
Started May 14 02:09:52 PM PDT 24
Finished May 14 02:09:55 PM PDT 24
Peak memory 228904 kb
Host smart-73c60c1c-fd15-4d41-992c-2df77b057ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295763251 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2295763251
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3549039298
Short name T629
Test name
Test status
Simulation time 146524159 ps
CPU time 1.27 seconds
Started May 14 02:09:54 PM PDT 24
Finished May 14 02:09:57 PM PDT 24
Peak memory 218360 kb
Host smart-4f18dd40-fd3b-463b-b2c7-0a7b3646a4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549039298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3549039298
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.3716691997
Short name T389
Test name
Test status
Simulation time 25267472 ps
CPU time 1.17 seconds
Started May 14 02:09:48 PM PDT 24
Finished May 14 02:09:51 PM PDT 24
Peak memory 218240 kb
Host smart-8bbc5877-2e74-46ae-8382-4768f258cf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716691997 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3716691997
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3067175293
Short name T299
Test name
Test status
Simulation time 27449836 ps
CPU time 1.27 seconds
Started May 14 02:09:48 PM PDT 24
Finished May 14 02:09:51 PM PDT 24
Peak memory 216932 kb
Host smart-c3eab739-87b9-4280-9f95-788e22ffe586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067175293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3067175293
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.1673015585
Short name T74
Test name
Test status
Simulation time 316251948 ps
CPU time 1.35 seconds
Started May 14 02:08:02 PM PDT 24
Finished May 14 02:08:04 PM PDT 24
Peak memory 215616 kb
Host smart-dbf5ea7d-93ff-4a41-b7e3-554a1ca89715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673015585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1673015585
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3763827727
Short name T735
Test name
Test status
Simulation time 23919722 ps
CPU time 1.06 seconds
Started May 14 02:08:05 PM PDT 24
Finished May 14 02:08:07 PM PDT 24
Peak memory 206320 kb
Host smart-f89db7ab-d453-4069-b35f-69d1fcd86e95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763827727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3763827727
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.4263536855
Short name T678
Test name
Test status
Simulation time 14145007 ps
CPU time 0.95 seconds
Started May 14 02:08:03 PM PDT 24
Finished May 14 02:08:05 PM PDT 24
Peak memory 215256 kb
Host smart-70fc34eb-aea3-438c-a8b0-c725d021a564
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263536855 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.4263536855
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.108885170
Short name T36
Test name
Test status
Simulation time 74548738 ps
CPU time 1.14 seconds
Started May 14 02:08:03 PM PDT 24
Finished May 14 02:08:06 PM PDT 24
Peak memory 216712 kb
Host smart-e6a52c2f-ee5e-4416-bec7-1275cdd68061
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108885170 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.108885170
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2860479714
Short name T28
Test name
Test status
Simulation time 34634677 ps
CPU time 1.18 seconds
Started May 14 02:08:00 PM PDT 24
Finished May 14 02:08:03 PM PDT 24
Peak memory 229204 kb
Host smart-e63fcc8e-065f-4364-8cd7-9dec780e2fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860479714 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2860479714
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3567022608
Short name T400
Test name
Test status
Simulation time 82571284 ps
CPU time 2.89 seconds
Started May 14 02:08:05 PM PDT 24
Finished May 14 02:08:09 PM PDT 24
Peak memory 219336 kb
Host smart-77c7302b-4233-4b76-912f-009c1e2b59ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567022608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3567022608
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_regwen.351308045
Short name T108
Test name
Test status
Simulation time 31529345 ps
CPU time 0.99 seconds
Started May 14 02:08:02 PM PDT 24
Finished May 14 02:08:04 PM PDT 24
Peak memory 206712 kb
Host smart-25a278cf-6b3f-43ec-9b3d-6a7d44436f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351308045 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.351308045
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3639211516
Short name T603
Test name
Test status
Simulation time 68827993 ps
CPU time 0.94 seconds
Started May 14 02:08:07 PM PDT 24
Finished May 14 02:08:09 PM PDT 24
Peak memory 214948 kb
Host smart-cd299242-19fa-45b9-9480-2cde1e6bfa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639211516 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3639211516
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3760720605
Short name T435
Test name
Test status
Simulation time 684936391 ps
CPU time 2.25 seconds
Started May 14 02:08:08 PM PDT 24
Finished May 14 02:08:11 PM PDT 24
Peak memory 214968 kb
Host smart-e8e62637-0b30-46ae-a94d-af4eeaae836b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760720605 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3760720605
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2269417912
Short name T463
Test name
Test status
Simulation time 44207807167 ps
CPU time 1172.06 seconds
Started May 14 02:08:05 PM PDT 24
Finished May 14 02:27:38 PM PDT 24
Peak memory 220180 kb
Host smart-d8e8be27-74cc-49c3-a57a-0ada5686aa61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269417912 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2269417912
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.3766873791
Short name T64
Test name
Test status
Simulation time 25217648 ps
CPU time 1.08 seconds
Started May 14 02:09:54 PM PDT 24
Finished May 14 02:09:57 PM PDT 24
Peak memory 223480 kb
Host smart-306cdab2-836c-4fad-bb7c-5010f1b419ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766873791 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3766873791
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1668084992
Short name T490
Test name
Test status
Simulation time 2257892136 ps
CPU time 74.37 seconds
Started May 14 02:09:48 PM PDT 24
Finished May 14 02:11:04 PM PDT 24
Peak memory 219436 kb
Host smart-06ff460d-c13d-4f1c-aebe-f4119658932b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668084992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1668084992
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.2122784484
Short name T38
Test name
Test status
Simulation time 33274850 ps
CPU time 1.06 seconds
Started May 14 02:09:51 PM PDT 24
Finished May 14 02:09:54 PM PDT 24
Peak memory 229064 kb
Host smart-17ca6025-6101-4199-8bb2-97c1b3f3ed62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122784484 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2122784484
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/62.edn_err.3419363618
Short name T31
Test name
Test status
Simulation time 49828751 ps
CPU time 1.15 seconds
Started May 14 02:09:53 PM PDT 24
Finished May 14 02:09:56 PM PDT 24
Peak memory 229072 kb
Host smart-fda55897-fb1e-411f-81cc-7c3f46ebacfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419363618 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3419363618
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2586684993
Short name T416
Test name
Test status
Simulation time 74358343 ps
CPU time 0.99 seconds
Started May 14 02:09:50 PM PDT 24
Finished May 14 02:09:53 PM PDT 24
Peak memory 216668 kb
Host smart-5fa0019b-007a-49f3-b65d-7249da49f467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586684993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2586684993
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.4115529269
Short name T682
Test name
Test status
Simulation time 29223115 ps
CPU time 1.41 seconds
Started May 14 02:09:49 PM PDT 24
Finished May 14 02:09:52 PM PDT 24
Peak memory 225156 kb
Host smart-4f1957fe-5665-4ddf-b09b-25552848f7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115529269 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.4115529269
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2054216349
Short name T118
Test name
Test status
Simulation time 78351024 ps
CPU time 1.45 seconds
Started May 14 02:09:54 PM PDT 24
Finished May 14 02:09:57 PM PDT 24
Peak memory 217648 kb
Host smart-62fd4fe8-6ac8-4460-98c4-fb29856f7c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054216349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2054216349
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.3586998600
Short name T592
Test name
Test status
Simulation time 18178537 ps
CPU time 1.05 seconds
Started May 14 02:09:52 PM PDT 24
Finished May 14 02:09:55 PM PDT 24
Peak memory 218056 kb
Host smart-30239bd3-7403-4ec0-9ff9-a0d0988aa1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586998600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3586998600
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3065212097
Short name T349
Test name
Test status
Simulation time 48596612 ps
CPU time 1.25 seconds
Started May 14 02:09:48 PM PDT 24
Finished May 14 02:09:51 PM PDT 24
Peak memory 219092 kb
Host smart-57e9f2b2-7eb6-4ffe-be43-2f2466e475b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065212097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3065212097
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.1286772880
Short name T70
Test name
Test status
Simulation time 18587229 ps
CPU time 1.22 seconds
Started May 14 02:09:52 PM PDT 24
Finished May 14 02:09:55 PM PDT 24
Peak memory 223344 kb
Host smart-4e1e8a8c-e145-40b4-8458-4c6939c0c064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286772880 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1286772880
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.524168008
Short name T674
Test name
Test status
Simulation time 56397969 ps
CPU time 1.36 seconds
Started May 14 02:09:50 PM PDT 24
Finished May 14 02:09:53 PM PDT 24
Peak memory 217916 kb
Host smart-d310ef97-ec09-497c-8191-6435beecaeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524168008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.524168008
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.1083385107
Short name T462
Test name
Test status
Simulation time 33812315 ps
CPU time 0.87 seconds
Started May 14 02:09:51 PM PDT 24
Finished May 14 02:09:54 PM PDT 24
Peak memory 214940 kb
Host smart-02e573b6-2036-468b-bea3-cdc938c031d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083385107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1083385107
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3228579213
Short name T322
Test name
Test status
Simulation time 62304220 ps
CPU time 1.51 seconds
Started May 14 02:09:50 PM PDT 24
Finished May 14 02:09:54 PM PDT 24
Peak memory 218456 kb
Host smart-4b6208d6-24d2-49f7-b7f1-305d3a1a9e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228579213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3228579213
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.2543367287
Short name T57
Test name
Test status
Simulation time 19454009 ps
CPU time 1.09 seconds
Started May 14 02:09:52 PM PDT 24
Finished May 14 02:09:55 PM PDT 24
Peak memory 217928 kb
Host smart-e7e27b27-5bc9-494e-87e7-18a31a6f0b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543367287 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2543367287
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2083932653
Short name T504
Test name
Test status
Simulation time 31621315 ps
CPU time 1.34 seconds
Started May 14 02:09:52 PM PDT 24
Finished May 14 02:09:55 PM PDT 24
Peak memory 214964 kb
Host smart-e2fa97bd-16a6-4658-ac0e-2fc80b50369f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083932653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2083932653
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1798890396
Short name T703
Test name
Test status
Simulation time 29267060 ps
CPU time 1.24 seconds
Started May 14 02:09:47 PM PDT 24
Finished May 14 02:09:50 PM PDT 24
Peak memory 219456 kb
Host smart-81e6dd23-2dd7-4e4d-806a-956b1a3a787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798890396 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1798890396
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.900838571
Short name T830
Test name
Test status
Simulation time 84607016 ps
CPU time 1.23 seconds
Started May 14 02:09:53 PM PDT 24
Finished May 14 02:09:56 PM PDT 24
Peak memory 217820 kb
Host smart-0ccaf670-63b1-43d0-b80d-801e2a5c663c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900838571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.900838571
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.3259991233
Short name T63
Test name
Test status
Simulation time 18803779 ps
CPU time 1.05 seconds
Started May 14 02:09:50 PM PDT 24
Finished May 14 02:09:53 PM PDT 24
Peak memory 217980 kb
Host smart-3e22b8a5-424a-44c0-859c-3774ca44debd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259991233 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3259991233
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/7.edn_alert.3524098494
Short name T95
Test name
Test status
Simulation time 46372233 ps
CPU time 1.25 seconds
Started May 14 02:08:00 PM PDT 24
Finished May 14 02:08:02 PM PDT 24
Peak memory 215204 kb
Host smart-f97a6d2c-984f-4228-a899-002af37590a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524098494 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3524098494
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.4028971796
Short name T358
Test name
Test status
Simulation time 14619262 ps
CPU time 0.94 seconds
Started May 14 02:07:59 PM PDT 24
Finished May 14 02:08:01 PM PDT 24
Peak memory 206272 kb
Host smart-e5144f04-de23-4ce9-bbe7-01df6c0c9261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028971796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.4028971796
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2076354715
Short name T186
Test name
Test status
Simulation time 52983281 ps
CPU time 0.82 seconds
Started May 14 02:08:00 PM PDT 24
Finished May 14 02:08:02 PM PDT 24
Peak memory 215184 kb
Host smart-437de379-6ed9-454d-be52-2664e99c6171
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076354715 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2076354715
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2168604090
Short name T836
Test name
Test status
Simulation time 433739719 ps
CPU time 1.15 seconds
Started May 14 02:08:00 PM PDT 24
Finished May 14 02:08:02 PM PDT 24
Peak memory 216660 kb
Host smart-acc6af31-2fcd-4772-a26b-54be3803ab23
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168604090 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2168604090
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1312007370
Short name T62
Test name
Test status
Simulation time 22942255 ps
CPU time 1.08 seconds
Started May 14 02:08:08 PM PDT 24
Finished May 14 02:08:10 PM PDT 24
Peak memory 223520 kb
Host smart-f6f53c25-27e5-4ce6-82e4-cd4af30eb285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312007370 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1312007370
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.633056662
Short name T281
Test name
Test status
Simulation time 97760550 ps
CPU time 1.41 seconds
Started May 14 02:08:08 PM PDT 24
Finished May 14 02:08:11 PM PDT 24
Peak memory 218284 kb
Host smart-ba6fe747-6079-45da-b10f-328918bc9835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633056662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.633056662
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3645613452
Short name T671
Test name
Test status
Simulation time 63537692 ps
CPU time 0.87 seconds
Started May 14 02:07:59 PM PDT 24
Finished May 14 02:08:01 PM PDT 24
Peak memory 214868 kb
Host smart-f6f5e809-10fa-4f14-9216-f2fd46d719ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645613452 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3645613452
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_smoke.3388784966
Short name T476
Test name
Test status
Simulation time 91840348 ps
CPU time 1.04 seconds
Started May 14 02:08:00 PM PDT 24
Finished May 14 02:08:02 PM PDT 24
Peak memory 214944 kb
Host smart-eab378b8-1fbb-4cf5-b26c-cafef49142a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388784966 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3388784966
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.4010275477
Short name T295
Test name
Test status
Simulation time 137340569 ps
CPU time 3.25 seconds
Started May 14 02:08:01 PM PDT 24
Finished May 14 02:08:06 PM PDT 24
Peak memory 216500 kb
Host smart-6a535f2b-3d96-4d67-9aa3-2ca32ecc9447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010275477 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4010275477
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2857396467
Short name T719
Test name
Test status
Simulation time 148370003329 ps
CPU time 951.4 seconds
Started May 14 02:08:00 PM PDT 24
Finished May 14 02:23:52 PM PDT 24
Peak memory 221696 kb
Host smart-3ac888aa-59f9-4b75-9c47-5830c9ddcca6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857396467 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2857396467
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.2740502903
Short name T89
Test name
Test status
Simulation time 18750902 ps
CPU time 1.08 seconds
Started May 14 02:09:48 PM PDT 24
Finished May 14 02:09:50 PM PDT 24
Peak memory 218004 kb
Host smart-76c87040-9277-4465-9bd8-a936f263168d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740502903 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2740502903
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2865850986
Short name T396
Test name
Test status
Simulation time 58726196 ps
CPU time 1.08 seconds
Started May 14 02:09:50 PM PDT 24
Finished May 14 02:09:53 PM PDT 24
Peak memory 218312 kb
Host smart-e9547811-4491-4b5c-83af-88c943d29489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865850986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2865850986
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.1081813033
Short name T733
Test name
Test status
Simulation time 27212714 ps
CPU time 0.98 seconds
Started May 14 02:09:54 PM PDT 24
Finished May 14 02:09:57 PM PDT 24
Peak memory 218928 kb
Host smart-669fa5f0-aad7-4c2c-ab40-58f0a454a493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081813033 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1081813033
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3462839980
Short name T301
Test name
Test status
Simulation time 44151453 ps
CPU time 1.09 seconds
Started May 14 02:09:52 PM PDT 24
Finished May 14 02:09:55 PM PDT 24
Peak memory 216848 kb
Host smart-99ecad22-d21e-445f-87e6-cbfb88055e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462839980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3462839980
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.239286787
Short name T467
Test name
Test status
Simulation time 77857243 ps
CPU time 0.85 seconds
Started May 14 02:09:52 PM PDT 24
Finished May 14 02:09:55 PM PDT 24
Peak memory 218032 kb
Host smart-f6a31bf6-9a34-4104-80d5-f1cf617ea069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239286787 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.239286787
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2112976785
Short name T129
Test name
Test status
Simulation time 123193323 ps
CPU time 1.5 seconds
Started May 14 02:09:53 PM PDT 24
Finished May 14 02:09:56 PM PDT 24
Peak memory 216744 kb
Host smart-1ed423f9-863e-4308-99d1-0d9ea4be44b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112976785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2112976785
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.912322471
Short name T489
Test name
Test status
Simulation time 49846619 ps
CPU time 1.04 seconds
Started May 14 02:09:59 PM PDT 24
Finished May 14 02:10:02 PM PDT 24
Peak memory 218264 kb
Host smart-da94f32d-2034-468f-9489-a052ee2a0e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912322471 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.912322471
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.825745017
Short name T623
Test name
Test status
Simulation time 121137372 ps
CPU time 1.72 seconds
Started May 14 02:10:01 PM PDT 24
Finished May 14 02:10:04 PM PDT 24
Peak memory 219192 kb
Host smart-d826d391-9679-4505-8ead-ba9c93f1a515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825745017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.825745017
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.763840656
Short name T98
Test name
Test status
Simulation time 48678980 ps
CPU time 0.9 seconds
Started May 14 02:09:57 PM PDT 24
Finished May 14 02:09:59 PM PDT 24
Peak memory 223220 kb
Host smart-5ac8fef2-be87-45ed-805d-5a2ef2f0cbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763840656 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.763840656
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2555512455
Short name T553
Test name
Test status
Simulation time 27012170 ps
CPU time 1.16 seconds
Started May 14 02:10:00 PM PDT 24
Finished May 14 02:10:03 PM PDT 24
Peak memory 218012 kb
Host smart-366b4fa0-63a5-45e4-932c-9c9c2ae7721d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555512455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2555512455
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.2284607559
Short name T88
Test name
Test status
Simulation time 23218892 ps
CPU time 0.89 seconds
Started May 14 02:10:00 PM PDT 24
Finished May 14 02:10:03 PM PDT 24
Peak memory 217964 kb
Host smart-0908db53-469b-4029-9ec6-36cd3b3341a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284607559 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2284607559
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2590695256
Short name T353
Test name
Test status
Simulation time 78790435 ps
CPU time 1.23 seconds
Started May 14 02:09:58 PM PDT 24
Finished May 14 02:10:01 PM PDT 24
Peak memory 216884 kb
Host smart-6663d9f8-30bf-497e-9d96-6b22b663d3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590695256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2590695256
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3794991187
Short name T65
Test name
Test status
Simulation time 20808630 ps
CPU time 1.09 seconds
Started May 14 02:10:05 PM PDT 24
Finished May 14 02:10:07 PM PDT 24
Peak memory 218068 kb
Host smart-d2200e30-aaaf-43b1-b7ce-6368360cb619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794991187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3794991187
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1377460125
Short name T742
Test name
Test status
Simulation time 42184381 ps
CPU time 1.57 seconds
Started May 14 02:10:05 PM PDT 24
Finished May 14 02:10:08 PM PDT 24
Peak memory 217948 kb
Host smart-5a3f55e2-dee7-43bf-b164-406310ed1d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377460125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1377460125
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.2314558747
Short name T177
Test name
Test status
Simulation time 28055258 ps
CPU time 1.16 seconds
Started May 14 02:10:01 PM PDT 24
Finished May 14 02:10:03 PM PDT 24
Peak memory 218152 kb
Host smart-2312d4c0-b8e0-4ee9-8a9e-b962496ceb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314558747 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2314558747
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3649848953
Short name T568
Test name
Test status
Simulation time 28535757 ps
CPU time 1.34 seconds
Started May 14 02:09:57 PM PDT 24
Finished May 14 02:10:00 PM PDT 24
Peak memory 217824 kb
Host smart-db09faf3-b283-4dbc-ad6a-c03bf8079778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649848953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3649848953
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.3383446644
Short name T528
Test name
Test status
Simulation time 27802464 ps
CPU time 1.26 seconds
Started May 14 02:10:01 PM PDT 24
Finished May 14 02:10:04 PM PDT 24
Peak memory 219208 kb
Host smart-38dc4dc0-0acc-4d8e-a8b6-b2f27e1e2365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383446644 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3383446644
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2420833645
Short name T599
Test name
Test status
Simulation time 50317033 ps
CPU time 1.65 seconds
Started May 14 02:09:58 PM PDT 24
Finished May 14 02:10:02 PM PDT 24
Peak memory 217736 kb
Host smart-fb696789-3120-4db5-b39b-6d31188eec9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420833645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2420833645
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.2528418698
Short name T33
Test name
Test status
Simulation time 46096951 ps
CPU time 1.18 seconds
Started May 14 02:10:00 PM PDT 24
Finished May 14 02:10:03 PM PDT 24
Peak memory 217212 kb
Host smart-f17115e3-c0bd-4d24-829a-d52c2bcb74cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528418698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2528418698
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3546296562
Short name T564
Test name
Test status
Simulation time 45268139 ps
CPU time 1.31 seconds
Started May 14 02:10:01 PM PDT 24
Finished May 14 02:10:03 PM PDT 24
Peak memory 219124 kb
Host smart-eb8b5c34-6980-41d6-8896-42d06dc3f0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546296562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3546296562
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2950808506
Short name T841
Test name
Test status
Simulation time 28836174 ps
CPU time 1.39 seconds
Started May 14 02:08:09 PM PDT 24
Finished May 14 02:08:12 PM PDT 24
Peak memory 215328 kb
Host smart-fc5193a4-76ed-416f-a8ec-1d0385458525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950808506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2950808506
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1943121909
Short name T18
Test name
Test status
Simulation time 14105062 ps
CPU time 0.9 seconds
Started May 14 02:08:09 PM PDT 24
Finished May 14 02:08:12 PM PDT 24
Peak memory 206260 kb
Host smart-c162774f-8306-4225-8c7c-5cd6bcca8438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943121909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1943121909
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3538156962
Short name T631
Test name
Test status
Simulation time 13308994 ps
CPU time 0.94 seconds
Started May 14 02:08:09 PM PDT 24
Finished May 14 02:08:12 PM PDT 24
Peak memory 215288 kb
Host smart-83dbc8a0-3768-42a4-85dc-7988d6b7652b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538156962 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3538156962
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.945608135
Short name T729
Test name
Test status
Simulation time 66332586 ps
CPU time 1.31 seconds
Started May 14 02:08:10 PM PDT 24
Finished May 14 02:08:14 PM PDT 24
Peak memory 216548 kb
Host smart-97735281-0c8f-4ee9-ac87-dd6efb2d8386
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945608135 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.945608135
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.247886760
Short name T365
Test name
Test status
Simulation time 36081895 ps
CPU time 1.01 seconds
Started May 14 02:08:10 PM PDT 24
Finished May 14 02:08:13 PM PDT 24
Peak memory 223248 kb
Host smart-accb2577-4c9b-4225-8ab5-d3108915888c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247886760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.247886760
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.4276771116
Short name T550
Test name
Test status
Simulation time 246280021 ps
CPU time 3.21 seconds
Started May 14 02:08:02 PM PDT 24
Finished May 14 02:08:07 PM PDT 24
Peak memory 219700 kb
Host smart-ccd812e9-f900-4c32-a131-9f537a97f52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276771116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.4276771116
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.687501992
Short name T111
Test name
Test status
Simulation time 64653193 ps
CPU time 0.88 seconds
Started May 14 02:08:09 PM PDT 24
Finished May 14 02:08:12 PM PDT 24
Peak memory 215060 kb
Host smart-325b9dee-0503-44c9-83d8-181797a50c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687501992 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.687501992
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1705045314
Short name T261
Test name
Test status
Simulation time 32596772 ps
CPU time 0.94 seconds
Started May 14 02:08:01 PM PDT 24
Finished May 14 02:08:03 PM PDT 24
Peak memory 206804 kb
Host smart-b2f005d7-0308-49e6-9386-b3ca911dec59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705045314 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1705045314
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1477883297
Short name T514
Test name
Test status
Simulation time 17207971 ps
CPU time 1.03 seconds
Started May 14 02:08:02 PM PDT 24
Finished May 14 02:08:04 PM PDT 24
Peak memory 214936 kb
Host smart-7cf59a35-cb7d-4a5c-a418-859a311f5866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477883297 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1477883297
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3810083679
Short name T477
Test name
Test status
Simulation time 104434282 ps
CPU time 2.67 seconds
Started May 14 02:08:08 PM PDT 24
Finished May 14 02:08:12 PM PDT 24
Peak memory 216800 kb
Host smart-94fae4ff-4c9e-4711-b09a-db39fd42fa55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810083679 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3810083679
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3466451937
Short name T513
Test name
Test status
Simulation time 89630845823 ps
CPU time 1212.24 seconds
Started May 14 02:08:09 PM PDT 24
Finished May 14 02:28:23 PM PDT 24
Peak memory 224124 kb
Host smart-46cc8a62-d98e-41f5-aca0-9f5de064dbe0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466451937 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3466451937
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.4216403429
Short name T180
Test name
Test status
Simulation time 39572411 ps
CPU time 1.02 seconds
Started May 14 02:09:58 PM PDT 24
Finished May 14 02:10:01 PM PDT 24
Peak memory 219316 kb
Host smart-3acde14e-6eec-4c12-a9f6-b44379c70b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216403429 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.4216403429
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1094912608
Short name T312
Test name
Test status
Simulation time 84749662 ps
CPU time 1.7 seconds
Started May 14 02:10:05 PM PDT 24
Finished May 14 02:10:08 PM PDT 24
Peak memory 216660 kb
Host smart-cf293556-2160-4c2c-aef4-1f2802ca7303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094912608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1094912608
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.3656928623
Short name T760
Test name
Test status
Simulation time 21926049 ps
CPU time 1.01 seconds
Started May 14 02:10:22 PM PDT 24
Finished May 14 02:10:25 PM PDT 24
Peak memory 223340 kb
Host smart-c5b63db9-a63d-45a8-9154-247908ea9ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656928623 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3656928623
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3196419854
Short name T560
Test name
Test status
Simulation time 32757973 ps
CPU time 1.13 seconds
Started May 14 02:09:59 PM PDT 24
Finished May 14 02:10:02 PM PDT 24
Peak memory 216852 kb
Host smart-bf6affd7-7a14-4e3b-94d7-fbbe2360e67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196419854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3196419854
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.194365612
Short name T565
Test name
Test status
Simulation time 30781208 ps
CPU time 0.89 seconds
Started May 14 02:10:13 PM PDT 24
Finished May 14 02:10:17 PM PDT 24
Peak memory 217768 kb
Host smart-72d1d092-7729-400f-9c4d-19bf4a25a893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194365612 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.194365612
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2668586331
Short name T324
Test name
Test status
Simulation time 38995383 ps
CPU time 1.6 seconds
Started May 14 02:10:10 PM PDT 24
Finished May 14 02:10:14 PM PDT 24
Peak memory 216896 kb
Host smart-0ca11c06-0064-4ae6-b8f1-3ccf5bdd5bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668586331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2668586331
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.2544712868
Short name T166
Test name
Test status
Simulation time 144434820 ps
CPU time 0.98 seconds
Started May 14 02:10:10 PM PDT 24
Finished May 14 02:10:13 PM PDT 24
Peak memory 219140 kb
Host smart-ded57dc3-58f2-49ce-86a5-c40fbb3e9bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544712868 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2544712868
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/84.edn_err.1754991950
Short name T179
Test name
Test status
Simulation time 94708112 ps
CPU time 1.08 seconds
Started May 14 02:10:09 PM PDT 24
Finished May 14 02:10:12 PM PDT 24
Peak memory 219268 kb
Host smart-b46d86ea-9de3-426c-95fc-b56710e686eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754991950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1754991950
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2947846286
Short name T452
Test name
Test status
Simulation time 34498862 ps
CPU time 1.49 seconds
Started May 14 02:10:10 PM PDT 24
Finished May 14 02:10:14 PM PDT 24
Peak memory 218132 kb
Host smart-13033e6f-820e-47bc-b8c7-699025f86022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947846286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2947846286
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.2803842450
Short name T593
Test name
Test status
Simulation time 22901936 ps
CPU time 0.89 seconds
Started May 14 02:10:10 PM PDT 24
Finished May 14 02:10:14 PM PDT 24
Peak memory 217624 kb
Host smart-9a24fa57-86f7-4a06-b027-ce008b6e4839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803842450 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2803842450
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2612899534
Short name T731
Test name
Test status
Simulation time 63330071 ps
CPU time 1.02 seconds
Started May 14 02:10:09 PM PDT 24
Finished May 14 02:10:12 PM PDT 24
Peak memory 216732 kb
Host smart-3e959141-fbcc-4725-8fd1-e1e94e4e3a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612899534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2612899534
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_genbits.3754871428
Short name T581
Test name
Test status
Simulation time 59501397 ps
CPU time 1.46 seconds
Started May 14 02:10:08 PM PDT 24
Finished May 14 02:10:11 PM PDT 24
Peak memory 217916 kb
Host smart-2f7f938b-8058-4eec-8dff-e75e93f10ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754871428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3754871428
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.2286945591
Short name T677
Test name
Test status
Simulation time 47317226 ps
CPU time 1.21 seconds
Started May 14 02:10:11 PM PDT 24
Finished May 14 02:10:15 PM PDT 24
Peak memory 219208 kb
Host smart-f46db2ec-2c9e-45b7-8977-811d9b881608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286945591 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2286945591
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.1268206809
Short name T798
Test name
Test status
Simulation time 29730470 ps
CPU time 1.43 seconds
Started May 14 02:10:11 PM PDT 24
Finished May 14 02:10:16 PM PDT 24
Peak memory 216592 kb
Host smart-6d6e484b-ffb1-4878-b6ba-6db131f2439c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268206809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1268206809
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.1126097008
Short name T624
Test name
Test status
Simulation time 35496880 ps
CPU time 1.09 seconds
Started May 14 02:10:11 PM PDT 24
Finished May 14 02:10:15 PM PDT 24
Peak memory 220564 kb
Host smart-7857d645-1a97-43a1-b9d8-827e4c081879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126097008 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1126097008
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/89.edn_err.124444312
Short name T790
Test name
Test status
Simulation time 21284984 ps
CPU time 1.09 seconds
Started May 14 02:10:11 PM PDT 24
Finished May 14 02:10:16 PM PDT 24
Peak memory 223452 kb
Host smart-60456a94-e87a-4a1f-ba05-d0a3ebf72387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124444312 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.124444312
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1513510133
Short name T329
Test name
Test status
Simulation time 58243102 ps
CPU time 1.27 seconds
Started May 14 02:10:10 PM PDT 24
Finished May 14 02:10:14 PM PDT 24
Peak memory 218228 kb
Host smart-c86479f6-3929-4489-9606-fb7ae11855b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513510133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1513510133
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert_test.3939649871
Short name T413
Test name
Test status
Simulation time 51013547 ps
CPU time 0.86 seconds
Started May 14 02:08:09 PM PDT 24
Finished May 14 02:08:12 PM PDT 24
Peak memory 214256 kb
Host smart-eacda365-f670-487e-9f39-2c3d604f6cc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939649871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3939649871
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2082010053
Short name T748
Test name
Test status
Simulation time 30130195 ps
CPU time 0.83 seconds
Started May 14 02:08:10 PM PDT 24
Finished May 14 02:08:13 PM PDT 24
Peak memory 215940 kb
Host smart-347036d7-e59b-4792-945c-6cd0c61f94dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082010053 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2082010053
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3810165811
Short name T627
Test name
Test status
Simulation time 75861243 ps
CPU time 1.03 seconds
Started May 14 02:08:09 PM PDT 24
Finished May 14 02:08:12 PM PDT 24
Peak memory 216768 kb
Host smart-15f93ff8-09cf-4aa0-b3e8-0178632b860e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810165811 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3810165811
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.4136379760
Short name T587
Test name
Test status
Simulation time 27262215 ps
CPU time 0.98 seconds
Started May 14 02:08:13 PM PDT 24
Finished May 14 02:08:15 PM PDT 24
Peak memory 223284 kb
Host smart-dfbaa1cc-96c7-4e7f-8d61-c40116a3aa6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136379760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.4136379760
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.4128183244
Short name T410
Test name
Test status
Simulation time 42986260 ps
CPU time 1.21 seconds
Started May 14 02:08:10 PM PDT 24
Finished May 14 02:08:13 PM PDT 24
Peak memory 215072 kb
Host smart-67e58127-a0b8-405c-bedc-cd35adcc96d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128183244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.4128183244
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1612524947
Short name T419
Test name
Test status
Simulation time 23087133 ps
CPU time 1.08 seconds
Started May 14 02:08:07 PM PDT 24
Finished May 14 02:08:08 PM PDT 24
Peak memory 215036 kb
Host smart-bfaad29f-4362-436d-84a7-9e76212f1e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612524947 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1612524947
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3120921390
Short name T540
Test name
Test status
Simulation time 61643105 ps
CPU time 0.93 seconds
Started May 14 02:08:09 PM PDT 24
Finished May 14 02:08:12 PM PDT 24
Peak memory 206744 kb
Host smart-cdf0e6ea-9c53-4994-a318-771f695d43f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120921390 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3120921390
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2004696367
Short name T392
Test name
Test status
Simulation time 20832997 ps
CPU time 1.17 seconds
Started May 14 02:08:11 PM PDT 24
Finished May 14 02:08:14 PM PDT 24
Peak memory 214900 kb
Host smart-50cdb250-2a28-430c-97c3-54af50c11bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004696367 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2004696367
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3462386113
Short name T364
Test name
Test status
Simulation time 337258053 ps
CPU time 5.5 seconds
Started May 14 02:08:10 PM PDT 24
Finished May 14 02:08:17 PM PDT 24
Peak memory 219464 kb
Host smart-35b15c0c-383f-4964-bef7-8be81660ae1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462386113 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3462386113
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3097903454
Short name T608
Test name
Test status
Simulation time 76656166809 ps
CPU time 381.01 seconds
Started May 14 02:08:09 PM PDT 24
Finished May 14 02:14:32 PM PDT 24
Peak memory 221076 kb
Host smart-97360cfb-2137-476c-b1ad-520eb4be85cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097903454 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3097903454
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.779825428
Short name T125
Test name
Test status
Simulation time 23959821 ps
CPU time 1.05 seconds
Started May 14 02:10:11 PM PDT 24
Finished May 14 02:10:16 PM PDT 24
Peak memory 223440 kb
Host smart-0ca082b7-2d08-4614-ab36-b804c593c030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779825428 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.779825428
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.273006342
Short name T752
Test name
Test status
Simulation time 129502295 ps
CPU time 1.58 seconds
Started May 14 02:10:09 PM PDT 24
Finished May 14 02:10:13 PM PDT 24
Peak memory 218364 kb
Host smart-a970adf1-e08f-448d-890f-ad682e8d90fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273006342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.273006342
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.3639542664
Short name T850
Test name
Test status
Simulation time 25039131 ps
CPU time 0.95 seconds
Started May 14 02:10:09 PM PDT 24
Finished May 14 02:10:11 PM PDT 24
Peak memory 217716 kb
Host smart-d9188e6c-2b3b-4105-8bf5-9b02a27ac832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639542664 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3639542664
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3648142962
Short name T717
Test name
Test status
Simulation time 57731681 ps
CPU time 1.51 seconds
Started May 14 02:10:09 PM PDT 24
Finished May 14 02:10:11 PM PDT 24
Peak memory 219452 kb
Host smart-cb48308c-ee5c-4e76-ad4e-89f3ecb8fe80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648142962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3648142962
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.1207523671
Short name T496
Test name
Test status
Simulation time 22761628 ps
CPU time 1 seconds
Started May 14 02:10:08 PM PDT 24
Finished May 14 02:10:10 PM PDT 24
Peak memory 218192 kb
Host smart-4ac3a653-1302-443f-8940-a3e759f5557a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207523671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1207523671
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3117397657
Short name T323
Test name
Test status
Simulation time 43717955 ps
CPU time 1.75 seconds
Started May 14 02:10:08 PM PDT 24
Finished May 14 02:10:11 PM PDT 24
Peak memory 217900 kb
Host smart-c48f57d4-70e7-4de8-a6a4-9fe3aa439ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117397657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3117397657
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.1782009869
Short name T51
Test name
Test status
Simulation time 29317568 ps
CPU time 1.02 seconds
Started May 14 02:10:10 PM PDT 24
Finished May 14 02:10:13 PM PDT 24
Peak memory 219248 kb
Host smart-b87646ed-60f6-4290-a66f-8ac32640db25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782009869 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1782009869
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2091918008
Short name T499
Test name
Test status
Simulation time 29330616 ps
CPU time 1.29 seconds
Started May 14 02:10:10 PM PDT 24
Finished May 14 02:10:14 PM PDT 24
Peak memory 219048 kb
Host smart-634e5d6c-817c-48d4-84fc-59dca19ea4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091918008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2091918008
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.1388982367
Short name T56
Test name
Test status
Simulation time 45500153 ps
CPU time 1.32 seconds
Started May 14 02:10:12 PM PDT 24
Finished May 14 02:10:17 PM PDT 24
Peak memory 225196 kb
Host smart-ff52c2b4-153e-46d8-aca8-090eeefee33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388982367 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1388982367
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2285768790
Short name T648
Test name
Test status
Simulation time 99662864 ps
CPU time 1.21 seconds
Started May 14 02:10:09 PM PDT 24
Finished May 14 02:10:12 PM PDT 24
Peak memory 217932 kb
Host smart-c100a3b2-0f5b-48f9-9698-50eddf6efd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285768790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2285768790
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.3040264319
Short name T81
Test name
Test status
Simulation time 28239040 ps
CPU time 0.96 seconds
Started May 14 02:10:11 PM PDT 24
Finished May 14 02:10:16 PM PDT 24
Peak memory 223280 kb
Host smart-c8ec2415-1621-4184-b079-49ff40dff258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040264319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3040264319
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2198554546
Short name T371
Test name
Test status
Simulation time 29737996 ps
CPU time 1.38 seconds
Started May 14 02:10:10 PM PDT 24
Finished May 14 02:10:13 PM PDT 24
Peak memory 219004 kb
Host smart-e0fcb06b-18dc-4323-bfd4-b54ee02f296f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198554546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2198554546
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_genbits.4224970405
Short name T284
Test name
Test status
Simulation time 53187451 ps
CPU time 1.08 seconds
Started May 14 02:10:10 PM PDT 24
Finished May 14 02:10:13 PM PDT 24
Peak memory 216888 kb
Host smart-30f0993d-b3de-4798-93cd-ccdffeef0190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224970405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.4224970405
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.3922877069
Short name T86
Test name
Test status
Simulation time 22014346 ps
CPU time 1.04 seconds
Started May 14 02:10:07 PM PDT 24
Finished May 14 02:10:09 PM PDT 24
Peak memory 223420 kb
Host smart-04b5b533-e2e6-4bbe-8083-8b2f08ddccea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922877069 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3922877069
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3337515627
Short name T480
Test name
Test status
Simulation time 50962525 ps
CPU time 1.8 seconds
Started May 14 02:10:13 PM PDT 24
Finished May 14 02:10:18 PM PDT 24
Peak memory 218016 kb
Host smart-019094ed-675d-4cc6-ad44-d3545344b86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337515627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3337515627
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.2747336142
Short name T14
Test name
Test status
Simulation time 20022608 ps
CPU time 1.17 seconds
Started May 14 02:10:10 PM PDT 24
Finished May 14 02:10:14 PM PDT 24
Peak memory 223460 kb
Host smart-6663ded2-1f2c-4b3e-a36b-1323fdecafaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747336142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2747336142
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3187568885
Short name T768
Test name
Test status
Simulation time 47651965 ps
CPU time 1.56 seconds
Started May 14 02:10:10 PM PDT 24
Finished May 14 02:10:15 PM PDT 24
Peak memory 219472 kb
Host smart-4822216e-989c-49bd-b352-6091a005f9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187568885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3187568885
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.3032518152
Short name T693
Test name
Test status
Simulation time 25429952 ps
CPU time 1.03 seconds
Started May 14 02:10:10 PM PDT 24
Finished May 14 02:10:13 PM PDT 24
Peak memory 219064 kb
Host smart-c6f3f54a-cc61-4a54-8580-239203c76a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032518152 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3032518152
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2362989859
Short name T421
Test name
Test status
Simulation time 50227490 ps
CPU time 1.65 seconds
Started May 14 02:10:10 PM PDT 24
Finished May 14 02:10:15 PM PDT 24
Peak memory 217788 kb
Host smart-9d0b63f2-87ad-4537-a7ce-63dbdc2b158f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362989859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2362989859
Directory /workspace/99.edn_genbits/latest
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