Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.33 98.24 93.80 97.02 83.72 96.62 99.77 91.12


Total test records in report: 980
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T795 /workspace/coverage/default/171.edn_genbits.4115285420 May 16 02:05:00 PM PDT 24 May 16 02:05:04 PM PDT 24 79542417 ps
T198 /workspace/coverage/default/4.edn_disable_auto_req_mode.3489675618 May 16 02:01:36 PM PDT 24 May 16 02:01:39 PM PDT 24 195616105 ps
T796 /workspace/coverage/default/29.edn_genbits.3984082264 May 16 02:03:11 PM PDT 24 May 16 02:03:14 PM PDT 24 56759882 ps
T797 /workspace/coverage/default/29.edn_disable_auto_req_mode.680968961 May 16 02:03:11 PM PDT 24 May 16 02:03:15 PM PDT 24 54091765 ps
T798 /workspace/coverage/default/2.edn_smoke.1324953995 May 16 02:01:25 PM PDT 24 May 16 02:01:27 PM PDT 24 57544424 ps
T799 /workspace/coverage/default/25.edn_stress_all.1464683766 May 16 02:02:47 PM PDT 24 May 16 02:02:54 PM PDT 24 157149478 ps
T800 /workspace/coverage/default/5.edn_alert.1176266376 May 16 02:01:35 PM PDT 24 May 16 02:01:38 PM PDT 24 141536126 ps
T801 /workspace/coverage/default/37.edn_alert.3672208468 May 16 02:03:21 PM PDT 24 May 16 02:03:26 PM PDT 24 58843545 ps
T274 /workspace/coverage/default/4.edn_regwen.3460772846 May 16 02:01:34 PM PDT 24 May 16 02:01:36 PM PDT 24 55366936 ps
T802 /workspace/coverage/default/21.edn_err.761151704 May 16 02:02:44 PM PDT 24 May 16 02:02:47 PM PDT 24 30528718 ps
T803 /workspace/coverage/default/19.edn_disable_auto_req_mode.3356947811 May 16 02:02:29 PM PDT 24 May 16 02:02:33 PM PDT 24 28448194 ps
T804 /workspace/coverage/default/160.edn_genbits.703804398 May 16 02:04:59 PM PDT 24 May 16 02:05:04 PM PDT 24 78426459 ps
T805 /workspace/coverage/default/28.edn_err.930790604 May 16 02:03:00 PM PDT 24 May 16 02:03:03 PM PDT 24 32045676 ps
T806 /workspace/coverage/default/268.edn_genbits.1093942547 May 16 02:05:20 PM PDT 24 May 16 02:05:26 PM PDT 24 32430842 ps
T807 /workspace/coverage/default/56.edn_err.2108255827 May 16 02:04:03 PM PDT 24 May 16 02:04:09 PM PDT 24 23283129 ps
T808 /workspace/coverage/default/78.edn_genbits.1621221818 May 16 02:04:15 PM PDT 24 May 16 02:04:19 PM PDT 24 21300476 ps
T809 /workspace/coverage/default/185.edn_genbits.2466684727 May 16 02:05:04 PM PDT 24 May 16 02:05:07 PM PDT 24 65513198 ps
T810 /workspace/coverage/default/31.edn_alert.3911689056 May 16 02:03:11 PM PDT 24 May 16 02:03:15 PM PDT 24 47717404 ps
T811 /workspace/coverage/default/180.edn_genbits.2477525909 May 16 02:04:58 PM PDT 24 May 16 02:05:03 PM PDT 24 66186648 ps
T812 /workspace/coverage/default/18.edn_smoke.1115742345 May 16 02:02:33 PM PDT 24 May 16 02:02:38 PM PDT 24 22334836 ps
T813 /workspace/coverage/default/4.edn_alert.2285368742 May 16 02:01:34 PM PDT 24 May 16 02:01:37 PM PDT 24 154589648 ps
T294 /workspace/coverage/default/179.edn_genbits.2158783588 May 16 02:05:00 PM PDT 24 May 16 02:05:04 PM PDT 24 68225405 ps
T295 /workspace/coverage/default/195.edn_genbits.1193475932 May 16 02:05:03 PM PDT 24 May 16 02:05:06 PM PDT 24 35965035 ps
T814 /workspace/coverage/default/27.edn_err.3701811517 May 16 02:02:59 PM PDT 24 May 16 02:03:02 PM PDT 24 89712912 ps
T815 /workspace/coverage/default/13.edn_alert.386855737 May 16 02:02:18 PM PDT 24 May 16 02:02:21 PM PDT 24 88721056 ps
T252 /workspace/coverage/default/18.edn_disable_auto_req_mode.3542693809 May 16 02:02:32 PM PDT 24 May 16 02:02:38 PM PDT 24 26219307 ps
T816 /workspace/coverage/default/46.edn_disable_auto_req_mode.2062685984 May 16 02:04:01 PM PDT 24 May 16 02:04:05 PM PDT 24 40527218 ps
T817 /workspace/coverage/default/59.edn_genbits.2245966044 May 16 02:04:13 PM PDT 24 May 16 02:04:15 PM PDT 24 34750498 ps
T818 /workspace/coverage/default/4.edn_intr.1464122889 May 16 02:01:34 PM PDT 24 May 16 02:01:36 PM PDT 24 23141523 ps
T819 /workspace/coverage/default/208.edn_genbits.391272137 May 16 02:05:11 PM PDT 24 May 16 02:05:15 PM PDT 24 32995098 ps
T820 /workspace/coverage/default/246.edn_genbits.331963307 May 16 02:05:17 PM PDT 24 May 16 02:05:22 PM PDT 24 63894399 ps
T200 /workspace/coverage/default/42.edn_disable.3713882835 May 16 02:03:47 PM PDT 24 May 16 02:03:49 PM PDT 24 11777275 ps
T821 /workspace/coverage/default/126.edn_genbits.2200433387 May 16 02:04:35 PM PDT 24 May 16 02:04:39 PM PDT 24 77854192 ps
T822 /workspace/coverage/default/219.edn_genbits.3234954271 May 16 02:05:12 PM PDT 24 May 16 02:05:17 PM PDT 24 54106018 ps
T823 /workspace/coverage/default/31.edn_intr.1326745115 May 16 02:03:12 PM PDT 24 May 16 02:03:15 PM PDT 24 36568575 ps
T824 /workspace/coverage/default/113.edn_genbits.1180533129 May 16 02:04:36 PM PDT 24 May 16 02:04:40 PM PDT 24 51425357 ps
T825 /workspace/coverage/default/87.edn_genbits.2684651159 May 16 02:04:25 PM PDT 24 May 16 02:04:27 PM PDT 24 91589577 ps
T826 /workspace/coverage/default/253.edn_genbits.4085340113 May 16 02:05:13 PM PDT 24 May 16 02:05:17 PM PDT 24 65719449 ps
T827 /workspace/coverage/default/38.edn_smoke.1247265725 May 16 02:03:24 PM PDT 24 May 16 02:03:29 PM PDT 24 27800003 ps
T828 /workspace/coverage/default/9.edn_err.3099490922 May 16 02:01:54 PM PDT 24 May 16 02:01:57 PM PDT 24 28751992 ps
T829 /workspace/coverage/default/79.edn_err.396092031 May 16 02:04:18 PM PDT 24 May 16 02:04:23 PM PDT 24 20735698 ps
T830 /workspace/coverage/default/147.edn_genbits.3989104556 May 16 02:04:46 PM PDT 24 May 16 02:04:52 PM PDT 24 149195142 ps
T831 /workspace/coverage/default/173.edn_genbits.3298954140 May 16 02:04:59 PM PDT 24 May 16 02:05:04 PM PDT 24 41999900 ps
T832 /workspace/coverage/default/0.edn_genbits.1132882919 May 16 02:01:09 PM PDT 24 May 16 02:01:12 PM PDT 24 72742937 ps
T833 /workspace/coverage/default/272.edn_genbits.1805884487 May 16 02:05:24 PM PDT 24 May 16 02:05:29 PM PDT 24 29658556 ps
T834 /workspace/coverage/default/12.edn_disable.1830804143 May 16 02:02:07 PM PDT 24 May 16 02:02:11 PM PDT 24 18527390 ps
T835 /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1507743313 May 16 02:01:45 PM PDT 24 May 16 02:33:26 PM PDT 24 72274146847 ps
T836 /workspace/coverage/default/13.edn_intr.1977793040 May 16 02:02:19 PM PDT 24 May 16 02:02:22 PM PDT 24 36844444 ps
T837 /workspace/coverage/default/82.edn_err.1828324120 May 16 02:04:37 PM PDT 24 May 16 02:04:41 PM PDT 24 25139250 ps
T838 /workspace/coverage/default/233.edn_genbits.2097329724 May 16 02:05:08 PM PDT 24 May 16 02:05:11 PM PDT 24 41394767 ps
T839 /workspace/coverage/default/43.edn_err.1660445073 May 16 02:03:46 PM PDT 24 May 16 02:03:48 PM PDT 24 32362147 ps
T840 /workspace/coverage/default/199.edn_genbits.232574533 May 16 02:04:59 PM PDT 24 May 16 02:05:03 PM PDT 24 51624275 ps
T841 /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1181136188 May 16 02:02:32 PM PDT 24 May 16 02:20:07 PM PDT 24 385409672103 ps
T842 /workspace/coverage/default/8.edn_err.2738504263 May 16 02:01:55 PM PDT 24 May 16 02:01:58 PM PDT 24 22767776 ps
T843 /workspace/coverage/default/79.edn_genbits.2384273177 May 16 02:04:16 PM PDT 24 May 16 02:04:22 PM PDT 24 237561565 ps
T844 /workspace/coverage/default/8.edn_disable_auto_req_mode.4133362849 May 16 02:01:56 PM PDT 24 May 16 02:02:01 PM PDT 24 108899186 ps
T845 /workspace/coverage/default/51.edn_genbits.511028220 May 16 02:04:00 PM PDT 24 May 16 02:04:04 PM PDT 24 49245230 ps
T317 /workspace/coverage/default/41.edn_genbits.2651944810 May 16 02:03:31 PM PDT 24 May 16 02:03:35 PM PDT 24 47041286 ps
T846 /workspace/coverage/default/27.edn_alert.3950611195 May 16 02:02:58 PM PDT 24 May 16 02:03:01 PM PDT 24 77625248 ps
T847 /workspace/coverage/default/95.edn_err.1503017733 May 16 02:04:30 PM PDT 24 May 16 02:04:33 PM PDT 24 66351295 ps
T848 /workspace/coverage/default/16.edn_disable.2949709165 May 16 02:02:32 PM PDT 24 May 16 02:02:38 PM PDT 24 22282554 ps
T849 /workspace/coverage/default/9.edn_disable.4016662921 May 16 02:01:55 PM PDT 24 May 16 02:01:58 PM PDT 24 49782790 ps
T850 /workspace/coverage/default/36.edn_alert_test.3525878723 May 16 02:03:22 PM PDT 24 May 16 02:03:27 PM PDT 24 61264666 ps
T851 /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1134168157 May 16 02:02:58 PM PDT 24 May 16 02:28:05 PM PDT 24 148417747377 ps
T852 /workspace/coverage/default/29.edn_smoke.1724407258 May 16 02:03:15 PM PDT 24 May 16 02:03:18 PM PDT 24 73802279 ps
T853 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2948695246 May 16 02:38:41 PM PDT 24 May 16 02:38:47 PM PDT 24 530149643 ps
T854 /workspace/coverage/cover_reg_top/24.edn_intr_test.1490108175 May 16 02:38:58 PM PDT 24 May 16 02:39:02 PM PDT 24 121628400 ps
T855 /workspace/coverage/cover_reg_top/46.edn_intr_test.4001190933 May 16 02:39:09 PM PDT 24 May 16 02:39:14 PM PDT 24 38313865 ps
T856 /workspace/coverage/cover_reg_top/27.edn_intr_test.1119402611 May 16 02:39:09 PM PDT 24 May 16 02:39:13 PM PDT 24 11838050 ps
T255 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2243356963 May 16 02:38:29 PM PDT 24 May 16 02:38:36 PM PDT 24 334720695 ps
T256 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2142500943 May 16 02:38:27 PM PDT 24 May 16 02:38:32 PM PDT 24 262038176 ps
T857 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.447795661 May 16 02:38:20 PM PDT 24 May 16 02:38:26 PM PDT 24 20388267 ps
T257 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4228194732 May 16 02:38:57 PM PDT 24 May 16 02:39:01 PM PDT 24 55867062 ps
T241 /workspace/coverage/cover_reg_top/2.edn_csr_rw.291298070 May 16 02:38:20 PM PDT 24 May 16 02:38:25 PM PDT 24 23072015 ps
T242 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2552725840 May 16 02:38:19 PM PDT 24 May 16 02:38:24 PM PDT 24 75681495 ps
T219 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3265461427 May 16 02:38:08 PM PDT 24 May 16 02:38:13 PM PDT 24 21083566 ps
T858 /workspace/coverage/cover_reg_top/44.edn_intr_test.522478756 May 16 02:39:08 PM PDT 24 May 16 02:39:12 PM PDT 24 45117762 ps
T253 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.191270309 May 16 02:38:09 PM PDT 24 May 16 02:38:14 PM PDT 24 51302327 ps
T220 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3889755239 May 16 02:38:19 PM PDT 24 May 16 02:38:24 PM PDT 24 136965194 ps
T859 /workspace/coverage/cover_reg_top/18.edn_intr_test.4064669502 May 16 02:38:58 PM PDT 24 May 16 02:39:03 PM PDT 24 43129722 ps
T860 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2151283989 May 16 02:38:26 PM PDT 24 May 16 02:38:31 PM PDT 24 25824596 ps
T861 /workspace/coverage/cover_reg_top/26.edn_intr_test.1388895798 May 16 02:39:09 PM PDT 24 May 16 02:39:13 PM PDT 24 42427203 ps
T243 /workspace/coverage/cover_reg_top/16.edn_csr_rw.984847867 May 16 02:38:58 PM PDT 24 May 16 02:39:02 PM PDT 24 22516025 ps
T221 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3200980494 May 16 02:38:11 PM PDT 24 May 16 02:38:16 PM PDT 24 207440468 ps
T254 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3298010449 May 16 02:38:27 PM PDT 24 May 16 02:38:31 PM PDT 24 38013332 ps
T259 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3294875879 May 16 02:38:19 PM PDT 24 May 16 02:38:25 PM PDT 24 235654115 ps
T862 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1568721646 May 16 02:38:58 PM PDT 24 May 16 02:39:03 PM PDT 24 54821574 ps
T863 /workspace/coverage/cover_reg_top/34.edn_intr_test.2927569415 May 16 02:39:10 PM PDT 24 May 16 02:39:15 PM PDT 24 24356662 ps
T864 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3521159131 May 16 02:38:18 PM PDT 24 May 16 02:38:22 PM PDT 24 17343133 ps
T865 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3665459840 May 16 02:38:57 PM PDT 24 May 16 02:39:05 PM PDT 24 1129896924 ps
T866 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.657481788 May 16 02:38:59 PM PDT 24 May 16 02:39:04 PM PDT 24 50001396 ps
T260 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2038645660 May 16 02:38:41 PM PDT 24 May 16 02:38:45 PM PDT 24 183552086 ps
T867 /workspace/coverage/cover_reg_top/33.edn_intr_test.1135058605 May 16 02:39:08 PM PDT 24 May 16 02:39:11 PM PDT 24 11692213 ps
T868 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.581963766 May 16 02:38:09 PM PDT 24 May 16 02:38:14 PM PDT 24 42378794 ps
T244 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2548564479 May 16 02:38:37 PM PDT 24 May 16 02:38:40 PM PDT 24 28713859 ps
T869 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4087541988 May 16 02:38:09 PM PDT 24 May 16 02:38:14 PM PDT 24 112546715 ps
T870 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2140201206 May 16 02:38:20 PM PDT 24 May 16 02:38:27 PM PDT 24 79747724 ps
T222 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3568359122 May 16 02:38:28 PM PDT 24 May 16 02:38:33 PM PDT 24 36880447 ps
T871 /workspace/coverage/cover_reg_top/19.edn_tl_errors.345101616 May 16 02:38:56 PM PDT 24 May 16 02:39:03 PM PDT 24 94114287 ps
T245 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2908052402 May 16 02:38:57 PM PDT 24 May 16 02:39:01 PM PDT 24 30673776 ps
T223 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.763534111 May 16 02:38:28 PM PDT 24 May 16 02:38:34 PM PDT 24 36595458 ps
T872 /workspace/coverage/cover_reg_top/41.edn_intr_test.499009857 May 16 02:39:08 PM PDT 24 May 16 02:39:11 PM PDT 24 11501240 ps
T873 /workspace/coverage/cover_reg_top/39.edn_intr_test.2097425111 May 16 02:39:08 PM PDT 24 May 16 02:39:12 PM PDT 24 33309264 ps
T224 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.4237673347 May 16 02:38:31 PM PDT 24 May 16 02:38:36 PM PDT 24 32685114 ps
T874 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1489819764 May 16 02:38:48 PM PDT 24 May 16 02:38:52 PM PDT 24 420162762 ps
T875 /workspace/coverage/cover_reg_top/30.edn_intr_test.3930137652 May 16 02:39:07 PM PDT 24 May 16 02:39:10 PM PDT 24 18422353 ps
T876 /workspace/coverage/cover_reg_top/17.edn_intr_test.327581585 May 16 02:38:57 PM PDT 24 May 16 02:39:01 PM PDT 24 14244740 ps
T877 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1856022668 May 16 02:38:32 PM PDT 24 May 16 02:38:39 PM PDT 24 567015776 ps
T878 /workspace/coverage/cover_reg_top/42.edn_intr_test.820867767 May 16 02:39:09 PM PDT 24 May 16 02:39:13 PM PDT 24 19201802 ps
T879 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1490321979 May 16 02:38:37 PM PDT 24 May 16 02:38:40 PM PDT 24 44832529 ps
T880 /workspace/coverage/cover_reg_top/25.edn_intr_test.4254170629 May 16 02:39:07 PM PDT 24 May 16 02:39:09 PM PDT 24 12750585 ps
T881 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2541261857 May 16 02:38:57 PM PDT 24 May 16 02:39:02 PM PDT 24 28875870 ps
T225 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1259052849 May 16 02:38:20 PM PDT 24 May 16 02:38:25 PM PDT 24 14937923 ps
T226 /workspace/coverage/cover_reg_top/18.edn_csr_rw.3018355990 May 16 02:38:57 PM PDT 24 May 16 02:39:01 PM PDT 24 23190750 ps
T882 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2248060060 May 16 02:38:10 PM PDT 24 May 16 02:38:15 PM PDT 24 33447960 ps
T227 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3394699561 May 16 02:38:26 PM PDT 24 May 16 02:38:30 PM PDT 24 13862092 ps
T883 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3223616392 May 16 02:38:28 PM PDT 24 May 16 02:38:33 PM PDT 24 42477536 ps
T884 /workspace/coverage/cover_reg_top/0.edn_intr_test.2134514400 May 16 02:38:09 PM PDT 24 May 16 02:38:14 PM PDT 24 23640704 ps
T885 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3992541697 May 16 02:38:26 PM PDT 24 May 16 02:38:30 PM PDT 24 133004296 ps
T886 /workspace/coverage/cover_reg_top/6.edn_intr_test.3941738985 May 16 02:38:28 PM PDT 24 May 16 02:38:34 PM PDT 24 21828282 ps
T887 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2052845627 May 16 02:38:58 PM PDT 24 May 16 02:39:02 PM PDT 24 31244070 ps
T888 /workspace/coverage/cover_reg_top/3.edn_csr_rw.4252574469 May 16 02:38:19 PM PDT 24 May 16 02:38:24 PM PDT 24 48935574 ps
T889 /workspace/coverage/cover_reg_top/1.edn_tl_errors.2934840145 May 16 02:38:08 PM PDT 24 May 16 02:38:15 PM PDT 24 291510345 ps
T890 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1383620212 May 16 02:38:32 PM PDT 24 May 16 02:38:38 PM PDT 24 95899173 ps
T891 /workspace/coverage/cover_reg_top/11.edn_intr_test.489139858 May 16 02:38:30 PM PDT 24 May 16 02:38:36 PM PDT 24 40639367 ps
T228 /workspace/coverage/cover_reg_top/8.edn_csr_rw.2747816559 May 16 02:38:28 PM PDT 24 May 16 02:38:34 PM PDT 24 41035221 ps
T892 /workspace/coverage/cover_reg_top/40.edn_intr_test.1338821292 May 16 02:39:08 PM PDT 24 May 16 02:39:10 PM PDT 24 11918409 ps
T893 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1921123374 May 16 02:38:19 PM PDT 24 May 16 02:38:27 PM PDT 24 155201911 ps
T894 /workspace/coverage/cover_reg_top/0.edn_csr_rw.1813817106 May 16 02:38:11 PM PDT 24 May 16 02:38:16 PM PDT 24 12252891 ps
T895 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1267172419 May 16 02:38:11 PM PDT 24 May 16 02:38:16 PM PDT 24 33838816 ps
T896 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.811685191 May 16 02:38:28 PM PDT 24 May 16 02:38:36 PM PDT 24 171889163 ps
T263 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.616038354 May 16 02:38:29 PM PDT 24 May 16 02:38:36 PM PDT 24 234391366 ps
T229 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3842222859 May 16 02:38:28 PM PDT 24 May 16 02:38:34 PM PDT 24 13628871 ps
T897 /workspace/coverage/cover_reg_top/48.edn_intr_test.252250494 May 16 02:39:09 PM PDT 24 May 16 02:39:14 PM PDT 24 47002747 ps
T898 /workspace/coverage/cover_reg_top/37.edn_intr_test.2374802161 May 16 02:39:10 PM PDT 24 May 16 02:39:15 PM PDT 24 29541074 ps
T899 /workspace/coverage/cover_reg_top/8.edn_tl_errors.750096902 May 16 02:38:30 PM PDT 24 May 16 02:38:39 PM PDT 24 516774686 ps
T230 /workspace/coverage/cover_reg_top/13.edn_csr_rw.788813398 May 16 02:38:39 PM PDT 24 May 16 02:38:41 PM PDT 24 114451864 ps
T900 /workspace/coverage/cover_reg_top/49.edn_intr_test.631028799 May 16 02:39:11 PM PDT 24 May 16 02:39:16 PM PDT 24 23077264 ps
T901 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3669075079 May 16 02:38:19 PM PDT 24 May 16 02:38:25 PM PDT 24 159708641 ps
T902 /workspace/coverage/cover_reg_top/10.edn_tl_errors.759711362 May 16 02:38:32 PM PDT 24 May 16 02:38:38 PM PDT 24 110915278 ps
T903 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3691475297 May 16 02:38:30 PM PDT 24 May 16 02:38:36 PM PDT 24 17896841 ps
T261 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1286591052 May 16 02:38:59 PM PDT 24 May 16 02:39:04 PM PDT 24 93143214 ps
T904 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1457726246 May 16 02:38:27 PM PDT 24 May 16 02:38:35 PM PDT 24 492741694 ps
T905 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2060582391 May 16 02:38:29 PM PDT 24 May 16 02:38:35 PM PDT 24 53268829 ps
T906 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2375968620 May 16 02:38:17 PM PDT 24 May 16 02:38:22 PM PDT 24 52211085 ps
T907 /workspace/coverage/cover_reg_top/29.edn_intr_test.686086632 May 16 02:39:09 PM PDT 24 May 16 02:39:14 PM PDT 24 43751659 ps
T908 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.249609051 May 16 02:38:19 PM PDT 24 May 16 02:38:25 PM PDT 24 25510064 ps
T909 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3362477217 May 16 02:38:59 PM PDT 24 May 16 02:39:03 PM PDT 24 59759387 ps
T910 /workspace/coverage/cover_reg_top/3.edn_intr_test.3321120425 May 16 02:38:20 PM PDT 24 May 16 02:38:25 PM PDT 24 21255496 ps
T911 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3241390951 May 16 02:38:18 PM PDT 24 May 16 02:38:24 PM PDT 24 24248248 ps
T231 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3946395147 May 16 02:38:08 PM PDT 24 May 16 02:38:13 PM PDT 24 17169089 ps
T912 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1748627602 May 16 02:38:59 PM PDT 24 May 16 02:39:04 PM PDT 24 269173056 ps
T913 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.4031910116 May 16 02:38:17 PM PDT 24 May 16 02:38:21 PM PDT 24 25858068 ps
T914 /workspace/coverage/cover_reg_top/47.edn_intr_test.1457980515 May 16 02:39:08 PM PDT 24 May 16 02:39:12 PM PDT 24 55047529 ps
T915 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2181833816 May 16 02:38:27 PM PDT 24 May 16 02:38:33 PM PDT 24 79484728 ps
T916 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.4002926246 May 16 02:38:27 PM PDT 24 May 16 02:38:32 PM PDT 24 74193552 ps
T917 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3601816521 May 16 02:38:09 PM PDT 24 May 16 02:38:19 PM PDT 24 262927010 ps
T918 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.300510112 May 16 02:38:07 PM PDT 24 May 16 02:38:16 PM PDT 24 682806717 ps
T232 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2227276361 May 16 02:38:41 PM PDT 24 May 16 02:38:43 PM PDT 24 104159750 ps
T919 /workspace/coverage/cover_reg_top/5.edn_intr_test.4182167615 May 16 02:38:19 PM PDT 24 May 16 02:38:24 PM PDT 24 20651846 ps
T920 /workspace/coverage/cover_reg_top/15.edn_intr_test.766175894 May 16 02:38:57 PM PDT 24 May 16 02:39:01 PM PDT 24 33873183 ps
T921 /workspace/coverage/cover_reg_top/3.edn_tl_errors.991581273 May 16 02:38:20 PM PDT 24 May 16 02:38:26 PM PDT 24 25748127 ps
T922 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1995858763 May 16 02:38:10 PM PDT 24 May 16 02:38:16 PM PDT 24 57704598 ps
T233 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1538968239 May 16 02:38:57 PM PDT 24 May 16 02:39:01 PM PDT 24 24088850 ps
T923 /workspace/coverage/cover_reg_top/2.edn_intr_test.1155685503 May 16 02:38:17 PM PDT 24 May 16 02:38:21 PM PDT 24 12979022 ps
T924 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3483940076 May 16 02:38:08 PM PDT 24 May 16 02:38:14 PM PDT 24 314079896 ps
T925 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.4054917911 May 16 02:38:26 PM PDT 24 May 16 02:38:31 PM PDT 24 30860646 ps
T926 /workspace/coverage/cover_reg_top/38.edn_intr_test.3732823616 May 16 02:39:08 PM PDT 24 May 16 02:39:11 PM PDT 24 49921844 ps
T927 /workspace/coverage/cover_reg_top/1.edn_intr_test.3716912560 May 16 02:38:10 PM PDT 24 May 16 02:38:15 PM PDT 24 20033118 ps
T928 /workspace/coverage/cover_reg_top/45.edn_intr_test.2626550215 May 16 02:39:09 PM PDT 24 May 16 02:39:13 PM PDT 24 29680158 ps
T929 /workspace/coverage/cover_reg_top/31.edn_intr_test.3254906703 May 16 02:39:10 PM PDT 24 May 16 02:39:14 PM PDT 24 37081250 ps
T930 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3815807297 May 16 02:38:18 PM PDT 24 May 16 02:38:24 PM PDT 24 41870753 ps
T931 /workspace/coverage/cover_reg_top/21.edn_intr_test.2955345206 May 16 02:38:58 PM PDT 24 May 16 02:39:02 PM PDT 24 30697043 ps
T932 /workspace/coverage/cover_reg_top/32.edn_intr_test.1377221328 May 16 02:39:11 PM PDT 24 May 16 02:39:15 PM PDT 24 20365777 ps
T234 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2126201201 May 16 02:38:17 PM PDT 24 May 16 02:38:22 PM PDT 24 12608123 ps
T235 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3305363830 May 16 02:38:10 PM PDT 24 May 16 02:38:15 PM PDT 24 17995870 ps
T933 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2672964773 May 16 02:38:58 PM PDT 24 May 16 02:39:02 PM PDT 24 46428963 ps
T934 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4231939216 May 16 02:38:58 PM PDT 24 May 16 02:39:04 PM PDT 24 150902534 ps
T935 /workspace/coverage/cover_reg_top/4.edn_intr_test.3849972621 May 16 02:38:21 PM PDT 24 May 16 02:38:25 PM PDT 24 19790783 ps
T936 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2732457295 May 16 02:38:19 PM PDT 24 May 16 02:38:23 PM PDT 24 50758255 ps
T937 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1461164136 May 16 02:38:48 PM PDT 24 May 16 02:38:53 PM PDT 24 74024738 ps
T938 /workspace/coverage/cover_reg_top/12.edn_intr_test.4011881660 May 16 02:38:38 PM PDT 24 May 16 02:38:40 PM PDT 24 16880066 ps
T939 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2961952462 May 16 02:39:00 PM PDT 24 May 16 02:39:04 PM PDT 24 45412815 ps
T940 /workspace/coverage/cover_reg_top/16.edn_intr_test.2967819442 May 16 02:38:57 PM PDT 24 May 16 02:39:00 PM PDT 24 15034073 ps
T941 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3902726400 May 16 02:38:28 PM PDT 24 May 16 02:38:33 PM PDT 24 46066858 ps
T942 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.593433036 May 16 02:38:39 PM PDT 24 May 16 02:38:41 PM PDT 24 56280866 ps
T943 /workspace/coverage/cover_reg_top/23.edn_intr_test.3445438597 May 16 02:38:58 PM PDT 24 May 16 02:39:01 PM PDT 24 27032934 ps
T944 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1512931583 May 16 02:38:58 PM PDT 24 May 16 02:39:04 PM PDT 24 84761726 ps
T236 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2760120389 May 16 02:38:19 PM PDT 24 May 16 02:38:24 PM PDT 24 27807983 ps
T945 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.335069786 May 16 02:38:17 PM PDT 24 May 16 02:38:22 PM PDT 24 25218670 ps
T946 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.151060578 May 16 02:38:19 PM PDT 24 May 16 02:38:24 PM PDT 24 107915324 ps
T947 /workspace/coverage/cover_reg_top/7.edn_intr_test.1317776747 May 16 02:38:27 PM PDT 24 May 16 02:38:32 PM PDT 24 20213658 ps
T948 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3323949615 May 16 02:38:48 PM PDT 24 May 16 02:38:51 PM PDT 24 75348201 ps
T949 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3609426584 May 16 02:38:27 PM PDT 24 May 16 02:38:32 PM PDT 24 78721882 ps
T950 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1560069919 May 16 02:38:57 PM PDT 24 May 16 02:39:02 PM PDT 24 58332420 ps
T951 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3754050044 May 16 02:38:27 PM PDT 24 May 16 02:38:35 PM PDT 24 115445254 ps
T952 /workspace/coverage/cover_reg_top/13.edn_intr_test.949984689 May 16 02:38:36 PM PDT 24 May 16 02:38:39 PM PDT 24 11586601 ps
T953 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2105005453 May 16 02:38:58 PM PDT 24 May 16 02:39:02 PM PDT 24 43724352 ps
T954 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2520078535 May 16 02:38:19 PM PDT 24 May 16 02:38:28 PM PDT 24 196674514 ps
T239 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2341255786 May 16 02:38:47 PM PDT 24 May 16 02:38:48 PM PDT 24 12841948 ps
T955 /workspace/coverage/cover_reg_top/14.edn_intr_test.1686508565 May 16 02:38:48 PM PDT 24 May 16 02:38:51 PM PDT 24 67064339 ps
T956 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3405111272 May 16 02:38:50 PM PDT 24 May 16 02:38:53 PM PDT 24 20273909 ps
T957 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3930720400 May 16 02:38:48 PM PDT 24 May 16 02:38:51 PM PDT 24 282355401 ps
T958 /workspace/coverage/cover_reg_top/35.edn_intr_test.1507180040 May 16 02:39:09 PM PDT 24 May 16 02:39:13 PM PDT 24 14204001 ps
T237 /workspace/coverage/cover_reg_top/17.edn_csr_rw.408947419 May 16 02:38:58 PM PDT 24 May 16 02:39:01 PM PDT 24 38743479 ps
T240 /workspace/coverage/cover_reg_top/7.edn_csr_rw.802795209 May 16 02:38:28 PM PDT 24 May 16 02:38:34 PM PDT 24 44947443 ps
T959 /workspace/coverage/cover_reg_top/28.edn_intr_test.1905000550 May 16 02:39:08 PM PDT 24 May 16 02:39:11 PM PDT 24 14894832 ps
T960 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1069715506 May 16 02:38:11 PM PDT 24 May 16 02:38:17 PM PDT 24 84949211 ps
T961 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1590021702 May 16 02:38:31 PM PDT 24 May 16 02:38:37 PM PDT 24 40404464 ps
T962 /workspace/coverage/cover_reg_top/8.edn_intr_test.2783505051 May 16 02:38:27 PM PDT 24 May 16 02:38:32 PM PDT 24 13568618 ps
T963 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2826618355 May 16 02:38:10 PM PDT 24 May 16 02:38:17 PM PDT 24 268584314 ps
T964 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.633151495 May 16 02:38:19 PM PDT 24 May 16 02:38:25 PM PDT 24 97995054 ps
T238 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3120504133 May 16 02:38:58 PM PDT 24 May 16 02:39:02 PM PDT 24 56756925 ps
T965 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2541448746 May 16 02:38:59 PM PDT 24 May 16 02:39:04 PM PDT 24 33043054 ps
T966 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.286067103 May 16 02:38:17 PM PDT 24 May 16 02:38:21 PM PDT 24 270217570 ps
T967 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2914499731 May 16 02:38:49 PM PDT 24 May 16 02:38:53 PM PDT 24 71254810 ps
T968 /workspace/coverage/cover_reg_top/20.edn_intr_test.2105660235 May 16 02:38:57 PM PDT 24 May 16 02:39:01 PM PDT 24 29013621 ps
T969 /workspace/coverage/cover_reg_top/10.edn_intr_test.4085489852 May 16 02:38:30 PM PDT 24 May 16 02:38:36 PM PDT 24 41313690 ps
T970 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2380510036 May 16 02:38:29 PM PDT 24 May 16 02:38:37 PM PDT 24 273921038 ps
T971 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.794672439 May 16 02:38:20 PM PDT 24 May 16 02:38:28 PM PDT 24 1206572194 ps
T972 /workspace/coverage/cover_reg_top/9.edn_intr_test.1770769148 May 16 02:38:29 PM PDT 24 May 16 02:38:35 PM PDT 24 32648868 ps
T973 /workspace/coverage/cover_reg_top/22.edn_intr_test.3300259954 May 16 02:38:57 PM PDT 24 May 16 02:39:00 PM PDT 24 23066647 ps
T974 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3199218764 May 16 02:38:19 PM PDT 24 May 16 02:38:25 PM PDT 24 80305159 ps
T975 /workspace/coverage/cover_reg_top/4.edn_tl_errors.603268006 May 16 02:38:19 PM PDT 24 May 16 02:38:25 PM PDT 24 354113324 ps
T976 /workspace/coverage/cover_reg_top/19.edn_intr_test.528109597 May 16 02:38:58 PM PDT 24 May 16 02:39:02 PM PDT 24 91158370 ps
T977 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3074272778 May 16 02:38:58 PM PDT 24 May 16 02:39:03 PM PDT 24 249285829 ps
T978 /workspace/coverage/cover_reg_top/36.edn_intr_test.4001830219 May 16 02:39:10 PM PDT 24 May 16 02:39:14 PM PDT 24 48183868 ps
T262 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1139404317 May 16 02:38:41 PM PDT 24 May 16 02:38:45 PM PDT 24 499377890 ps
T979 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1271532027 May 16 02:38:35 PM PDT 24 May 16 02:38:40 PM PDT 24 76620237 ps
T980 /workspace/coverage/cover_reg_top/43.edn_intr_test.692868375 May 16 02:39:11 PM PDT 24 May 16 02:39:16 PM PDT 24 36970920 ps

Test location /workspace/coverage/default/124.edn_genbits.2672682959
Short name T8
Test name
Test status
Simulation time 249684007 ps
CPU time 3.63 seconds
Started May 16 02:04:35 PM PDT 24
Finished May 16 02:04:41 PM PDT 24
Peak memory 218780 kb
Host smart-d1e6869f-7ba7-4369-853a-c3de14e20253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672682959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2672682959
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2668266294
Short name T99
Test name
Test status
Simulation time 6781608202 ps
CPU time 140.69 seconds
Started May 16 02:01:14 PM PDT 24
Finished May 16 02:03:37 PM PDT 24
Peak memory 216920 kb
Host smart-8639729e-91f6-4d32-a1e8-05e38425bd6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668266294 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2668266294
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.edn_genbits.3356884539
Short name T124
Test name
Test status
Simulation time 93455324 ps
CPU time 1.52 seconds
Started May 16 02:01:25 PM PDT 24
Finished May 16 02:01:28 PM PDT 24
Peak memory 218392 kb
Host smart-42d507b1-b0d8-46f0-82d9-b4b751500347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356884539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3356884539
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_err.1611962662
Short name T24
Test name
Test status
Simulation time 20131881 ps
CPU time 1.12 seconds
Started May 16 02:01:36 PM PDT 24
Finished May 16 02:01:39 PM PDT 24
Peak memory 218116 kb
Host smart-a8d93f56-d704-4629-a343-38a49ffd383f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611962662 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1611962662
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2341637912
Short name T16
Test name
Test status
Simulation time 221654453 ps
CPU time 4.01 seconds
Started May 16 02:01:24 PM PDT 24
Finished May 16 02:01:29 PM PDT 24
Peak memory 234760 kb
Host smart-4a70cb08-0936-4b64-9fb6-af2033ea73d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341637912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2341637912
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/49.edn_alert.2502733075
Short name T25
Test name
Test status
Simulation time 57350556 ps
CPU time 1.31 seconds
Started May 16 02:04:01 PM PDT 24
Finished May 16 02:04:04 PM PDT 24
Peak memory 215352 kb
Host smart-08126b67-5fc3-4393-b543-b54871ddf2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502733075 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2502733075
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.762055729
Short name T11
Test name
Test status
Simulation time 90251337 ps
CPU time 1.39 seconds
Started May 16 02:04:41 PM PDT 24
Finished May 16 02:04:45 PM PDT 24
Peak memory 219496 kb
Host smart-f417bc4f-58b5-41da-8148-9f640c73fd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762055729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.762055729
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_disable.3319243579
Short name T22
Test name
Test status
Simulation time 10900688 ps
CPU time 0.91 seconds
Started May 16 02:03:32 PM PDT 24
Finished May 16 02:03:35 PM PDT 24
Peak memory 215984 kb
Host smart-0ac3e11d-bf85-4e4b-94e6-448a74a6b2e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319243579 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3319243579
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/37.edn_err.397590715
Short name T14
Test name
Test status
Simulation time 29957389 ps
CPU time 1 seconds
Started May 16 02:03:22 PM PDT 24
Finished May 16 02:03:27 PM PDT 24
Peak memory 228884 kb
Host smart-331a0fc3-5747-41ed-800a-7da1526673fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397590715 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.397590715
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.439570732
Short name T28
Test name
Test status
Simulation time 109405186 ps
CPU time 1.31 seconds
Started May 16 02:03:20 PM PDT 24
Finished May 16 02:03:24 PM PDT 24
Peak memory 216496 kb
Host smart-455c31f1-6971-4961-a621-69831c1c06c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439570732 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.439570732
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_regwen.507236324
Short name T102
Test name
Test status
Simulation time 19540561 ps
CPU time 1.01 seconds
Started May 16 02:01:30 PM PDT 24
Finished May 16 02:01:32 PM PDT 24
Peak memory 206776 kb
Host smart-b9823ffb-d3bf-43bb-a6b4-cd304c771044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507236324 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.507236324
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/20.edn_alert.143129477
Short name T94
Test name
Test status
Simulation time 50716167 ps
CPU time 1.29 seconds
Started May 16 02:02:32 PM PDT 24
Finished May 16 02:02:37 PM PDT 24
Peak memory 215372 kb
Host smart-8f43353d-5f84-4775-8ca4-0ee8a456e78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143129477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.143129477
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1286591052
Short name T261
Test name
Test status
Simulation time 93143214 ps
CPU time 2.51 seconds
Started May 16 02:38:59 PM PDT 24
Finished May 16 02:39:04 PM PDT 24
Peak memory 206200 kb
Host smart-dba519fa-ba3b-48b1-924d-5fed6ebe6bc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286591052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1286591052
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3200980494
Short name T221
Test name
Test status
Simulation time 207440468 ps
CPU time 1.19 seconds
Started May 16 02:38:11 PM PDT 24
Finished May 16 02:38:16 PM PDT 24
Peak memory 206240 kb
Host smart-c67df211-c373-409c-96dd-c0f63f664ea2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200980494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3200980494
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/default/46.edn_alert.1694406358
Short name T66
Test name
Test status
Simulation time 38971768 ps
CPU time 1.13 seconds
Started May 16 02:04:00 PM PDT 24
Finished May 16 02:04:02 PM PDT 24
Peak memory 215308 kb
Host smart-18cf3348-d53a-4994-8b47-180d67e785bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694406358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1694406358
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/81.edn_genbits.4019430444
Short name T118
Test name
Test status
Simulation time 65817825 ps
CPU time 1.39 seconds
Started May 16 02:04:17 PM PDT 24
Finished May 16 02:04:22 PM PDT 24
Peak memory 219360 kb
Host smart-04c1da53-e08c-43b4-8734-750dff036e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019430444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.4019430444
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2797488952
Short name T34
Test name
Test status
Simulation time 43277172 ps
CPU time 1.17 seconds
Started May 16 02:03:32 PM PDT 24
Finished May 16 02:03:36 PM PDT 24
Peak memory 216524 kb
Host smart-7169198b-736a-4782-bed2-848be2cdb58e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797488952 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2797488952
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_disable.505655599
Short name T80
Test name
Test status
Simulation time 10901599 ps
CPU time 0.91 seconds
Started May 16 02:01:44 PM PDT 24
Finished May 16 02:01:46 PM PDT 24
Peak memory 215936 kb
Host smart-ad7d2f8b-05e3-478b-91b3-60c44fcaf02f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505655599 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.505655599
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/29.edn_alert.519634492
Short name T72
Test name
Test status
Simulation time 40674263 ps
CPU time 1.18 seconds
Started May 16 02:03:11 PM PDT 24
Finished May 16 02:03:14 PM PDT 24
Peak memory 215284 kb
Host smart-aa37ed70-49cd-4c1d-acc8-46402ef6f727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519634492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.519634492
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/19.edn_disable.1340515324
Short name T89
Test name
Test status
Simulation time 34808402 ps
CPU time 0.87 seconds
Started May 16 02:02:32 PM PDT 24
Finished May 16 02:02:37 PM PDT 24
Peak memory 216032 kb
Host smart-9cb4d55e-22ca-4166-9622-6c627af0e4b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340515324 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1340515324
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable.3182756132
Short name T176
Test name
Test status
Simulation time 38593158 ps
CPU time 0.81 seconds
Started May 16 02:02:37 PM PDT 24
Finished May 16 02:02:42 PM PDT 24
Peak memory 216144 kb
Host smart-dbc5114f-8ae4-4a54-a488-3ba06736d983
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182756132 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3182756132
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2845474323
Short name T40
Test name
Test status
Simulation time 30179064 ps
CPU time 1.16 seconds
Started May 16 02:03:30 PM PDT 24
Finished May 16 02:03:33 PM PDT 24
Peak memory 216584 kb
Host smart-9c366a94-1ee3-4558-9324-7e7f7206ace2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845474323 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2845474323
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2974519275
Short name T113
Test name
Test status
Simulation time 165949661885 ps
CPU time 1065.66 seconds
Started May 16 02:02:20 PM PDT 24
Finished May 16 02:20:09 PM PDT 24
Peak memory 223768 kb
Host smart-05669b0c-8d6e-48cb-b6ab-10695221b1ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974519275 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2974519275
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.edn_intr.1462316008
Short name T110
Test name
Test status
Simulation time 50070353 ps
CPU time 0.89 seconds
Started May 16 02:02:58 PM PDT 24
Finished May 16 02:03:01 PM PDT 24
Peak memory 214992 kb
Host smart-d00f502d-65db-421b-ae4a-f575d579fab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462316008 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1462316008
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/5.edn_disable.4226043290
Short name T60
Test name
Test status
Simulation time 16072067 ps
CPU time 0.86 seconds
Started May 16 02:01:43 PM PDT 24
Finished May 16 02:01:45 PM PDT 24
Peak memory 215200 kb
Host smart-dcf6bf1d-b664-4b6e-a3d9-84b8f7ca79c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226043290 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.4226043290
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/48.edn_intr.1590258837
Short name T98
Test name
Test status
Simulation time 19562115 ps
CPU time 1.11 seconds
Started May 16 02:04:02 PM PDT 24
Finished May 16 02:04:07 PM PDT 24
Peak memory 215372 kb
Host smart-319e337f-9749-47f5-be61-1ceace670a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590258837 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1590258837
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.4110564266
Short name T266
Test name
Test status
Simulation time 52782426 ps
CPU time 0.96 seconds
Started May 16 02:01:04 PM PDT 24
Finished May 16 02:01:06 PM PDT 24
Peak memory 206780 kb
Host smart-400e166e-99fc-49b1-b25f-068b9c88d9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110564266 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.4110564266
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/134.edn_genbits.2422232497
Short name T251
Test name
Test status
Simulation time 52550273 ps
CPU time 2.15 seconds
Started May 16 02:04:36 PM PDT 24
Finished May 16 02:04:41 PM PDT 24
Peak memory 219504 kb
Host smart-21dd7009-ba29-48e2-9394-e13254a587f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422232497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2422232497
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1297682734
Short name T173
Test name
Test status
Simulation time 39493514 ps
CPU time 1.28 seconds
Started May 16 02:01:33 PM PDT 24
Finished May 16 02:01:35 PM PDT 24
Peak memory 219192 kb
Host smart-da88ea9f-9069-4976-94ee-5f883409741f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297682734 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1297682734
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/130.edn_genbits.1389964539
Short name T12
Test name
Test status
Simulation time 44683178 ps
CPU time 1.66 seconds
Started May 16 02:04:35 PM PDT 24
Finished May 16 02:04:39 PM PDT 24
Peak memory 219572 kb
Host smart-6c0e88a5-0c94-4a9d-a981-588fcf2aaef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389964539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1389964539
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2233579229
Short name T563
Test name
Test status
Simulation time 31687914 ps
CPU time 1.23 seconds
Started May 16 02:01:17 PM PDT 24
Finished May 16 02:01:20 PM PDT 24
Peak memory 216584 kb
Host smart-0894e810-d496-47e4-92b8-144e5b17d1ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233579229 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2233579229
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.900534358
Short name T717
Test name
Test status
Simulation time 32967332 ps
CPU time 1.26 seconds
Started May 16 02:02:08 PM PDT 24
Finished May 16 02:02:12 PM PDT 24
Peak memory 219380 kb
Host smart-37f3886a-63cf-4381-a86c-f6f5ebcf1892
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900534358 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.900534358
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_disable.5165069
Short name T182
Test name
Test status
Simulation time 10988051 ps
CPU time 0.89 seconds
Started May 16 02:02:19 PM PDT 24
Finished May 16 02:02:22 PM PDT 24
Peak memory 216148 kb
Host smart-9a7d8c92-7466-4e5a-ae5b-25da83d89dd4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5165069 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.5165069
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.835952322
Short name T90
Test name
Test status
Simulation time 28879254 ps
CPU time 0.95 seconds
Started May 16 02:02:18 PM PDT 24
Finished May 16 02:02:20 PM PDT 24
Peak memory 218100 kb
Host smart-1bfb88d7-fc56-4f4a-bb5e-4ac02af1ddf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835952322 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.835952322
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/18.edn_err.334653268
Short name T85
Test name
Test status
Simulation time 53303569 ps
CPU time 1.01 seconds
Started May 16 02:02:31 PM PDT 24
Finished May 16 02:02:36 PM PDT 24
Peak memory 223352 kb
Host smart-07b42b02-327e-4c60-aadb-cbd62facd6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334653268 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.334653268
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/27.edn_disable.2835582432
Short name T190
Test name
Test status
Simulation time 38961107 ps
CPU time 0.87 seconds
Started May 16 02:03:03 PM PDT 24
Finished May 16 02:03:05 PM PDT 24
Peak memory 216020 kb
Host smart-5d867b56-f146-46a2-80e4-8dbb0da15026
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835582432 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2835582432
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable.632114385
Short name T183
Test name
Test status
Simulation time 57049797 ps
CPU time 0.86 seconds
Started May 16 02:03:20 PM PDT 24
Finished May 16 02:03:24 PM PDT 24
Peak memory 216016 kb
Host smart-d7aec786-f7d5-4a61-ab34-691ec8c5e268
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632114385 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.632114385
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/7.edn_alert.3722293555
Short name T167
Test name
Test status
Simulation time 40974687 ps
CPU time 1.14 seconds
Started May 16 02:01:43 PM PDT 24
Finished May 16 02:01:46 PM PDT 24
Peak memory 215336 kb
Host smart-b200f210-13d1-4f75-ad67-058f5c981369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722293555 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3722293555
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.1606138246
Short name T142
Test name
Test status
Simulation time 179425512 ps
CPU time 0.95 seconds
Started May 16 02:02:08 PM PDT 24
Finished May 16 02:02:12 PM PDT 24
Peak memory 206068 kb
Host smart-451415e6-832d-418a-acb8-7e3775e710d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606138246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1606138246
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/251.edn_genbits.1120127682
Short name T305
Test name
Test status
Simulation time 46405677 ps
CPU time 1.31 seconds
Started May 16 02:05:09 PM PDT 24
Finished May 16 02:05:13 PM PDT 24
Peak memory 219136 kb
Host smart-c601d095-7e8c-4a73-87b0-b2a84622203e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120127682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1120127682
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_regwen.3460772846
Short name T274
Test name
Test status
Simulation time 55366936 ps
CPU time 0.92 seconds
Started May 16 02:01:34 PM PDT 24
Finished May 16 02:01:36 PM PDT 24
Peak memory 206836 kb
Host smart-6a8db2cd-2490-4bfb-89bb-d20d15f5544c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460772846 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3460772846
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/89.edn_genbits.3474163606
Short name T309
Test name
Test status
Simulation time 49933095 ps
CPU time 1.62 seconds
Started May 16 02:04:26 PM PDT 24
Finished May 16 02:04:28 PM PDT 24
Peak memory 219236 kb
Host smart-859dcb44-908c-4e56-95c2-0e1add8b683e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474163606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3474163606
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_genbits.4036582173
Short name T281
Test name
Test status
Simulation time 180537778 ps
CPU time 1.09 seconds
Started May 16 02:01:56 PM PDT 24
Finished May 16 02:02:01 PM PDT 24
Peak memory 216856 kb
Host smart-8b4e5dc4-3f4a-4136-908d-dbe25e18dc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036582173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.4036582173
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1435328099
Short name T157
Test name
Test status
Simulation time 103292959 ps
CPU time 0.84 seconds
Started May 16 02:03:32 PM PDT 24
Finished May 16 02:03:35 PM PDT 24
Peak memory 215128 kb
Host smart-5752158a-cf1d-48c6-8156-d6c2e9d7005d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435328099 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1435328099
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/24.edn_err.4007374391
Short name T191
Test name
Test status
Simulation time 66911908 ps
CPU time 1.01 seconds
Started May 16 02:02:47 PM PDT 24
Finished May 16 02:02:51 PM PDT 24
Peak memory 220296 kb
Host smart-b7652c73-2982-4664-848d-2d0a74b33ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007374391 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.4007374391
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3265461427
Short name T219
Test name
Test status
Simulation time 21083566 ps
CPU time 0.92 seconds
Started May 16 02:38:08 PM PDT 24
Finished May 16 02:38:13 PM PDT 24
Peak memory 206216 kb
Host smart-6ad493b4-6bd0-4787-b17d-69300d9dc9c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265461427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3265461427
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.edn_genbits.1132882919
Short name T832
Test name
Test status
Simulation time 72742937 ps
CPU time 1.2 seconds
Started May 16 02:01:09 PM PDT 24
Finished May 16 02:01:12 PM PDT 24
Peak memory 216548 kb
Host smart-832dc5d5-206e-4265-bcbb-e58ab074da53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132882919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1132882919
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_stress_all.216863226
Short name T301
Test name
Test status
Simulation time 78857407 ps
CPU time 2.02 seconds
Started May 16 02:02:08 PM PDT 24
Finished May 16 02:02:13 PM PDT 24
Peak memory 216684 kb
Host smart-eee7a8fa-5074-412c-a4ce-935a22b0f48a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216863226 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.216863226
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_genbits.2287394184
Short name T287
Test name
Test status
Simulation time 53266767 ps
CPU time 1.15 seconds
Started May 16 02:04:36 PM PDT 24
Finished May 16 02:04:41 PM PDT 24
Peak memory 216796 kb
Host smart-5116935c-1d51-4e83-8ab0-936e9647ceb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287394184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2287394184
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.2970553114
Short name T297
Test name
Test status
Simulation time 60825786 ps
CPU time 1.56 seconds
Started May 16 02:04:38 PM PDT 24
Finished May 16 02:04:43 PM PDT 24
Peak memory 217960 kb
Host smart-5112ca23-ea75-43d9-8d19-e3d6c663d51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970553114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2970553114
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.1340409776
Short name T306
Test name
Test status
Simulation time 42041866 ps
CPU time 1.67 seconds
Started May 16 02:04:38 PM PDT 24
Finished May 16 02:04:42 PM PDT 24
Peak memory 218152 kb
Host smart-661caf4a-9e52-4d84-826d-2df2b71eb9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340409776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1340409776
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.3629057492
Short name T292
Test name
Test status
Simulation time 59326940 ps
CPU time 1.34 seconds
Started May 16 02:04:39 PM PDT 24
Finished May 16 02:04:44 PM PDT 24
Peak memory 217940 kb
Host smart-7bc693ea-9a4a-4109-a4d4-ca727cf78a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629057492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3629057492
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.1665813669
Short name T439
Test name
Test status
Simulation time 197668576 ps
CPU time 1.39 seconds
Started May 16 02:04:59 PM PDT 24
Finished May 16 02:05:03 PM PDT 24
Peak memory 218160 kb
Host smart-b4a3265b-4e7e-43fc-9a53-e8f231610b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665813669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1665813669
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_genbits.2595045956
Short name T316
Test name
Test status
Simulation time 24426327 ps
CPU time 1.25 seconds
Started May 16 02:02:20 PM PDT 24
Finished May 16 02:02:24 PM PDT 24
Peak memory 216452 kb
Host smart-f8be0481-d204-4f8d-8646-9442b76c485d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595045956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2595045956
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.2158783588
Short name T294
Test name
Test status
Simulation time 68225405 ps
CPU time 1.23 seconds
Started May 16 02:05:00 PM PDT 24
Finished May 16 02:05:04 PM PDT 24
Peak memory 219316 kb
Host smart-03096694-3c58-4b3e-a712-18d530913649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158783588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2158783588
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_genbits.4085059343
Short name T304
Test name
Test status
Simulation time 74510861 ps
CPU time 1.56 seconds
Started May 16 02:02:46 PM PDT 24
Finished May 16 02:02:51 PM PDT 24
Peak memory 218228 kb
Host smart-24a871f7-b0ba-4809-8365-80479efd7999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085059343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.4085059343
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1993548325
Short name T158
Test name
Test status
Simulation time 27609581 ps
CPU time 0.87 seconds
Started May 16 02:03:22 PM PDT 24
Finished May 16 02:03:27 PM PDT 24
Peak memory 215292 kb
Host smart-21f7e6a1-04ff-4093-94c9-f4768470645c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993548325 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1993548325
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/244.edn_genbits.3111985406
Short name T119
Test name
Test status
Simulation time 43799437 ps
CPU time 1.88 seconds
Started May 16 02:05:11 PM PDT 24
Finished May 16 02:05:16 PM PDT 24
Peak memory 219676 kb
Host smart-df0390fc-1c81-4f02-b8d6-dd43e87ddc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111985406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3111985406
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1938173016
Short name T709
Test name
Test status
Simulation time 112055255 ps
CPU time 1.24 seconds
Started May 16 02:02:10 PM PDT 24
Finished May 16 02:02:14 PM PDT 24
Peak memory 215352 kb
Host smart-310fad50-4273-42c7-9975-545cc92c6ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938173016 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1938173016
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/3.edn_disable.2484768299
Short name T197
Test name
Test status
Simulation time 37694966 ps
CPU time 0.91 seconds
Started May 16 02:01:34 PM PDT 24
Finished May 16 02:01:37 PM PDT 24
Peak memory 215160 kb
Host smart-4ac7b89f-9562-49ef-8eff-126546a32817
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484768299 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2484768299
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable.1087038671
Short name T64
Test name
Test status
Simulation time 29320737 ps
CPU time 0.78 seconds
Started May 16 02:04:05 PM PDT 24
Finished May 16 02:04:10 PM PDT 24
Peak memory 216112 kb
Host smart-3d483bd1-e42e-49fd-98ba-ee2d31e877cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087038671 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1087038671
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3946395147
Short name T231
Test name
Test status
Simulation time 17169089 ps
CPU time 1.11 seconds
Started May 16 02:38:08 PM PDT 24
Finished May 16 02:38:13 PM PDT 24
Peak memory 206344 kb
Host smart-90008582-174e-476c-a162-a4e814d63664
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946395147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3946395147
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3601816521
Short name T917
Test name
Test status
Simulation time 262927010 ps
CPU time 6.5 seconds
Started May 16 02:38:09 PM PDT 24
Finished May 16 02:38:19 PM PDT 24
Peak memory 206180 kb
Host smart-05b68e9a-d341-4826-a162-e6c19e8b4511
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601816521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3601816521
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2248060060
Short name T882
Test name
Test status
Simulation time 33447960 ps
CPU time 0.93 seconds
Started May 16 02:38:10 PM PDT 24
Finished May 16 02:38:15 PM PDT 24
Peak memory 206152 kb
Host smart-cad53381-be84-4e29-89f7-de1dacdede02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248060060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2248060060
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.581963766
Short name T868
Test name
Test status
Simulation time 42378794 ps
CPU time 1.1 seconds
Started May 16 02:38:09 PM PDT 24
Finished May 16 02:38:14 PM PDT 24
Peak memory 214504 kb
Host smart-d4300622-b336-4b00-a803-693431921fd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581963766 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.581963766
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1813817106
Short name T894
Test name
Test status
Simulation time 12252891 ps
CPU time 0.88 seconds
Started May 16 02:38:11 PM PDT 24
Finished May 16 02:38:16 PM PDT 24
Peak memory 206084 kb
Host smart-81b6103a-0465-461f-b849-6c149071d9a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813817106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1813817106
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2134514400
Short name T884
Test name
Test status
Simulation time 23640704 ps
CPU time 0.87 seconds
Started May 16 02:38:09 PM PDT 24
Finished May 16 02:38:14 PM PDT 24
Peak memory 205996 kb
Host smart-3b51e01d-4ff1-426d-85a4-561702ae0e8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134514400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2134514400
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1995858763
Short name T922
Test name
Test status
Simulation time 57704598 ps
CPU time 2.44 seconds
Started May 16 02:38:10 PM PDT 24
Finished May 16 02:38:16 PM PDT 24
Peak memory 214420 kb
Host smart-a3f009e0-879f-4c41-9441-4fe1606daf19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995858763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1995858763
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2826618355
Short name T963
Test name
Test status
Simulation time 268584314 ps
CPU time 2.76 seconds
Started May 16 02:38:10 PM PDT 24
Finished May 16 02:38:17 PM PDT 24
Peak memory 206184 kb
Host smart-84d95c87-c457-4193-befa-43f7b1982031
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826618355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2826618355
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.300510112
Short name T918
Test name
Test status
Simulation time 682806717 ps
CPU time 5.27 seconds
Started May 16 02:38:07 PM PDT 24
Finished May 16 02:38:16 PM PDT 24
Peak memory 206184 kb
Host smart-9707c017-17de-4c49-a390-79f91cd16f53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300510112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.300510112
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.191270309
Short name T253
Test name
Test status
Simulation time 51302327 ps
CPU time 0.89 seconds
Started May 16 02:38:09 PM PDT 24
Finished May 16 02:38:14 PM PDT 24
Peak memory 206164 kb
Host smart-fce7a628-0fa3-45f6-b947-4c2e0f7eb11b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191270309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.191270309
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4087541988
Short name T869
Test name
Test status
Simulation time 112546715 ps
CPU time 1.31 seconds
Started May 16 02:38:09 PM PDT 24
Finished May 16 02:38:14 PM PDT 24
Peak memory 214564 kb
Host smart-d7b2c1f7-fef8-4c60-8509-8fce19f7ba51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087541988 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.4087541988
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3305363830
Short name T235
Test name
Test status
Simulation time 17995870 ps
CPU time 0.95 seconds
Started May 16 02:38:10 PM PDT 24
Finished May 16 02:38:15 PM PDT 24
Peak memory 206196 kb
Host smart-50c965d9-b758-4458-ad4c-c28fbc00dd4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305363830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3305363830
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3716912560
Short name T927
Test name
Test status
Simulation time 20033118 ps
CPU time 0.83 seconds
Started May 16 02:38:10 PM PDT 24
Finished May 16 02:38:15 PM PDT 24
Peak memory 205956 kb
Host smart-dd198550-0a7f-4507-bb63-6e20da710eef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716912560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3716912560
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1267172419
Short name T895
Test name
Test status
Simulation time 33838816 ps
CPU time 1.47 seconds
Started May 16 02:38:11 PM PDT 24
Finished May 16 02:38:16 PM PDT 24
Peak memory 206188 kb
Host smart-5aeec3d8-9d45-457f-8466-342b8a1bbce5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267172419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1267172419
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2934840145
Short name T889
Test name
Test status
Simulation time 291510345 ps
CPU time 3.19 seconds
Started May 16 02:38:08 PM PDT 24
Finished May 16 02:38:15 PM PDT 24
Peak memory 214464 kb
Host smart-9dfae084-d94d-4900-a9ff-d6b5e65aa214
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934840145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2934840145
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3483940076
Short name T924
Test name
Test status
Simulation time 314079896 ps
CPU time 2.4 seconds
Started May 16 02:38:08 PM PDT 24
Finished May 16 02:38:14 PM PDT 24
Peak memory 206224 kb
Host smart-2da8e3c9-8a37-41cf-be2b-fd3fd210edb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483940076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3483940076
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3223616392
Short name T883
Test name
Test status
Simulation time 42477536 ps
CPU time 1.24 seconds
Started May 16 02:38:28 PM PDT 24
Finished May 16 02:38:33 PM PDT 24
Peak memory 214412 kb
Host smart-d0f5d965-08dc-4740-8494-a8975d3d1377
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223616392 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3223616392
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3298010449
Short name T254
Test name
Test status
Simulation time 38013332 ps
CPU time 0.84 seconds
Started May 16 02:38:27 PM PDT 24
Finished May 16 02:38:31 PM PDT 24
Peak memory 206096 kb
Host smart-495107fd-2a2f-424b-9fd5-0867023a360a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298010449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3298010449
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.4085489852
Short name T969
Test name
Test status
Simulation time 41313690 ps
CPU time 0.85 seconds
Started May 16 02:38:30 PM PDT 24
Finished May 16 02:38:36 PM PDT 24
Peak memory 205956 kb
Host smart-f32a7254-a012-4300-b12d-745a4ba18723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085489852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.4085489852
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2060582391
Short name T905
Test name
Test status
Simulation time 53268829 ps
CPU time 1.31 seconds
Started May 16 02:38:29 PM PDT 24
Finished May 16 02:38:35 PM PDT 24
Peak memory 206124 kb
Host smart-cf111c20-80f4-46d5-ae42-7bf0e8968002
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060582391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2060582391
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.759711362
Short name T902
Test name
Test status
Simulation time 110915278 ps
CPU time 2.43 seconds
Started May 16 02:38:32 PM PDT 24
Finished May 16 02:38:38 PM PDT 24
Peak memory 214464 kb
Host smart-f67af13e-aeb6-473a-bbe1-437faf700021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759711362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.759711362
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2038645660
Short name T260
Test name
Test status
Simulation time 183552086 ps
CPU time 2.32 seconds
Started May 16 02:38:41 PM PDT 24
Finished May 16 02:38:45 PM PDT 24
Peak memory 206260 kb
Host smart-b7259a55-2141-4bfd-aefe-c47ec850eaa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038645660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2038645660
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3609426584
Short name T949
Test name
Test status
Simulation time 78721882 ps
CPU time 1.22 seconds
Started May 16 02:38:27 PM PDT 24
Finished May 16 02:38:32 PM PDT 24
Peak memory 216076 kb
Host smart-28e2d6d3-0df3-4cfd-bbfb-35e588f58d3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609426584 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3609426584
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3842222859
Short name T229
Test name
Test status
Simulation time 13628871 ps
CPU time 0.94 seconds
Started May 16 02:38:28 PM PDT 24
Finished May 16 02:38:34 PM PDT 24
Peak memory 206148 kb
Host smart-802bfb84-4c96-4bfa-813a-ebffb77eff89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842222859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3842222859
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.489139858
Short name T891
Test name
Test status
Simulation time 40639367 ps
CPU time 0.92 seconds
Started May 16 02:38:30 PM PDT 24
Finished May 16 02:38:36 PM PDT 24
Peak memory 206016 kb
Host smart-7e817f76-5bea-4735-9929-20acbab333bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489139858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.489139858
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1590021702
Short name T961
Test name
Test status
Simulation time 40404464 ps
CPU time 1.39 seconds
Started May 16 02:38:31 PM PDT 24
Finished May 16 02:38:37 PM PDT 24
Peak memory 206172 kb
Host smart-dc2ab465-4ca4-4fe8-bbf7-3888484460bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590021702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1590021702
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1457726246
Short name T904
Test name
Test status
Simulation time 492741694 ps
CPU time 3.82 seconds
Started May 16 02:38:27 PM PDT 24
Finished May 16 02:38:35 PM PDT 24
Peak memory 214380 kb
Host smart-ba3d52a2-e263-4253-a663-ea7c69aa6316
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457726246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1457726246
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2142500943
Short name T256
Test name
Test status
Simulation time 262038176 ps
CPU time 1.94 seconds
Started May 16 02:38:27 PM PDT 24
Finished May 16 02:38:32 PM PDT 24
Peak memory 214308 kb
Host smart-ebf3643f-b888-4a2f-b23e-8c5df2157885
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142500943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2142500943
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1490321979
Short name T879
Test name
Test status
Simulation time 44832529 ps
CPU time 1.13 seconds
Started May 16 02:38:37 PM PDT 24
Finished May 16 02:38:40 PM PDT 24
Peak memory 222740 kb
Host smart-7284f766-65df-49f0-b991-874b5dd00668
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490321979 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1490321979
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2227276361
Short name T232
Test name
Test status
Simulation time 104159750 ps
CPU time 0.84 seconds
Started May 16 02:38:41 PM PDT 24
Finished May 16 02:38:43 PM PDT 24
Peak memory 206084 kb
Host smart-a3715ebe-ddf1-4137-9034-d33f9146d31a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227276361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2227276361
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.4011881660
Short name T938
Test name
Test status
Simulation time 16880066 ps
CPU time 0.79 seconds
Started May 16 02:38:38 PM PDT 24
Finished May 16 02:38:40 PM PDT 24
Peak memory 205980 kb
Host smart-d81cf3c8-3a19-4b5d-a532-20fa7c9f09ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011881660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.4011881660
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2548564479
Short name T244
Test name
Test status
Simulation time 28713859 ps
CPU time 1.35 seconds
Started May 16 02:38:37 PM PDT 24
Finished May 16 02:38:40 PM PDT 24
Peak memory 206224 kb
Host smart-0d1022bf-1d60-48cf-9dce-abadd2b9037c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548564479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2548564479
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3754050044
Short name T951
Test name
Test status
Simulation time 115445254 ps
CPU time 4.09 seconds
Started May 16 02:38:27 PM PDT 24
Finished May 16 02:38:35 PM PDT 24
Peak memory 214380 kb
Host smart-a0491a69-541e-45e0-833c-05a99d20b6bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754050044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3754050044
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1271532027
Short name T979
Test name
Test status
Simulation time 76620237 ps
CPU time 2.32 seconds
Started May 16 02:38:35 PM PDT 24
Finished May 16 02:38:40 PM PDT 24
Peak memory 206352 kb
Host smart-b97ac5fa-e1a1-4566-9769-fd5acdb149b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271532027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1271532027
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3930720400
Short name T957
Test name
Test status
Simulation time 282355401 ps
CPU time 1.23 seconds
Started May 16 02:38:48 PM PDT 24
Finished May 16 02:38:51 PM PDT 24
Peak memory 216108 kb
Host smart-e282a8e6-78f9-4aec-bb98-438430f38f2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930720400 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3930720400
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.788813398
Short name T230
Test name
Test status
Simulation time 114451864 ps
CPU time 0.9 seconds
Started May 16 02:38:39 PM PDT 24
Finished May 16 02:38:41 PM PDT 24
Peak memory 206104 kb
Host smart-3cd24108-b6a5-4304-92ef-6bc516bdd0b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788813398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.788813398
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.949984689
Short name T952
Test name
Test status
Simulation time 11586601 ps
CPU time 0.86 seconds
Started May 16 02:38:36 PM PDT 24
Finished May 16 02:38:39 PM PDT 24
Peak memory 206120 kb
Host smart-6b4a74f4-9919-4fce-835b-9dd07141d67e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949984689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.949984689
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.593433036
Short name T942
Test name
Test status
Simulation time 56280866 ps
CPU time 0.95 seconds
Started May 16 02:38:39 PM PDT 24
Finished May 16 02:38:41 PM PDT 24
Peak memory 206156 kb
Host smart-d29fe215-7f8c-46d9-8d5b-942fb7f2ea82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593433036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.593433036
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2948695246
Short name T853
Test name
Test status
Simulation time 530149643 ps
CPU time 4.85 seconds
Started May 16 02:38:41 PM PDT 24
Finished May 16 02:38:47 PM PDT 24
Peak memory 214380 kb
Host smart-f5aaa257-7128-405e-9d62-8b83b691ce9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948695246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2948695246
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1139404317
Short name T262
Test name
Test status
Simulation time 499377890 ps
CPU time 2.56 seconds
Started May 16 02:38:41 PM PDT 24
Finished May 16 02:38:45 PM PDT 24
Peak memory 206180 kb
Host smart-0b560034-17b7-40c9-9f50-84b17ec0628a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139404317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1139404317
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1489819764
Short name T874
Test name
Test status
Simulation time 420162762 ps
CPU time 1.95 seconds
Started May 16 02:38:48 PM PDT 24
Finished May 16 02:38:52 PM PDT 24
Peak memory 214416 kb
Host smart-88ca55e0-fea4-4b88-ad7e-bda33fc7cc2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489819764 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1489819764
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2341255786
Short name T239
Test name
Test status
Simulation time 12841948 ps
CPU time 0.91 seconds
Started May 16 02:38:47 PM PDT 24
Finished May 16 02:38:48 PM PDT 24
Peak memory 206160 kb
Host smart-f063bf7c-5164-4398-928e-2da952d9b816
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341255786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2341255786
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1686508565
Short name T955
Test name
Test status
Simulation time 67064339 ps
CPU time 0.92 seconds
Started May 16 02:38:48 PM PDT 24
Finished May 16 02:38:51 PM PDT 24
Peak memory 206048 kb
Host smart-82fbcf95-15b8-440a-b042-0be359a38fcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686508565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1686508565
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3405111272
Short name T956
Test name
Test status
Simulation time 20273909 ps
CPU time 1.14 seconds
Started May 16 02:38:50 PM PDT 24
Finished May 16 02:38:53 PM PDT 24
Peak memory 206248 kb
Host smart-6db5a32a-eba4-42d3-a126-c859e8f52118
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405111272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3405111272
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1461164136
Short name T937
Test name
Test status
Simulation time 74024738 ps
CPU time 3.09 seconds
Started May 16 02:38:48 PM PDT 24
Finished May 16 02:38:53 PM PDT 24
Peak memory 214460 kb
Host smart-6b5b3010-4d90-4202-b02a-0518761767c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461164136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1461164136
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3323949615
Short name T948
Test name
Test status
Simulation time 75348201 ps
CPU time 1.46 seconds
Started May 16 02:38:48 PM PDT 24
Finished May 16 02:38:51 PM PDT 24
Peak memory 206284 kb
Host smart-57305f46-f19c-42dc-970b-42ea4f788c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323949615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3323949615
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.657481788
Short name T866
Test name
Test status
Simulation time 50001396 ps
CPU time 1.07 seconds
Started May 16 02:38:59 PM PDT 24
Finished May 16 02:39:04 PM PDT 24
Peak memory 214416 kb
Host smart-5065c1bb-46f3-4bfb-86a1-4d1c96900493
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657481788 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.657481788
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1538968239
Short name T233
Test name
Test status
Simulation time 24088850 ps
CPU time 0.94 seconds
Started May 16 02:38:57 PM PDT 24
Finished May 16 02:39:01 PM PDT 24
Peak memory 206152 kb
Host smart-d344dd1d-2402-4a2f-9bb8-b3d12c53caf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538968239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1538968239
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.766175894
Short name T920
Test name
Test status
Simulation time 33873183 ps
CPU time 0.88 seconds
Started May 16 02:38:57 PM PDT 24
Finished May 16 02:39:01 PM PDT 24
Peak memory 206064 kb
Host smart-f1f57c32-4228-4614-98b2-b1fce459dd03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766175894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.766175894
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2908052402
Short name T245
Test name
Test status
Simulation time 30673776 ps
CPU time 1.34 seconds
Started May 16 02:38:57 PM PDT 24
Finished May 16 02:39:01 PM PDT 24
Peak memory 206268 kb
Host smart-5b4060f3-f4f2-4bf8-a120-ef371f833ee8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908052402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2908052402
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2914499731
Short name T967
Test name
Test status
Simulation time 71254810 ps
CPU time 2.18 seconds
Started May 16 02:38:49 PM PDT 24
Finished May 16 02:38:53 PM PDT 24
Peak memory 214400 kb
Host smart-8ec48678-bef4-4de8-a803-045a6fed3e99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914499731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2914499731
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4228194732
Short name T257
Test name
Test status
Simulation time 55867062 ps
CPU time 1.56 seconds
Started May 16 02:38:57 PM PDT 24
Finished May 16 02:39:01 PM PDT 24
Peak memory 206268 kb
Host smart-4413e1fd-7fcf-40b1-ac5f-ec611a41caa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228194732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.4228194732
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2105005453
Short name T953
Test name
Test status
Simulation time 43724352 ps
CPU time 1.19 seconds
Started May 16 02:38:58 PM PDT 24
Finished May 16 02:39:02 PM PDT 24
Peak memory 206288 kb
Host smart-e1e4d2c8-5494-40e3-a015-75a4bb4b6666
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105005453 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2105005453
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.984847867
Short name T243
Test name
Test status
Simulation time 22516025 ps
CPU time 0.9 seconds
Started May 16 02:38:58 PM PDT 24
Finished May 16 02:39:02 PM PDT 24
Peak memory 206108 kb
Host smart-4792ff5b-4c18-4da1-a92d-cbcacb498b5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984847867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.984847867
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2967819442
Short name T940
Test name
Test status
Simulation time 15034073 ps
CPU time 0.88 seconds
Started May 16 02:38:57 PM PDT 24
Finished May 16 02:39:00 PM PDT 24
Peak memory 206056 kb
Host smart-010d9f05-48cb-4073-befd-1e7bb0311f90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967819442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2967819442
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1560069919
Short name T950
Test name
Test status
Simulation time 58332420 ps
CPU time 1.19 seconds
Started May 16 02:38:57 PM PDT 24
Finished May 16 02:39:02 PM PDT 24
Peak memory 206148 kb
Host smart-12212140-d628-4666-8f00-87bd2cc0ac5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560069919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1560069919
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3665459840
Short name T865
Test name
Test status
Simulation time 1129896924 ps
CPU time 4.52 seconds
Started May 16 02:38:57 PM PDT 24
Finished May 16 02:39:05 PM PDT 24
Peak memory 214480 kb
Host smart-ba9f11e3-85b0-4bd5-a555-c3ee7a44a4ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665459840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3665459840
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1512931583
Short name T944
Test name
Test status
Simulation time 84761726 ps
CPU time 2.41 seconds
Started May 16 02:38:58 PM PDT 24
Finished May 16 02:39:04 PM PDT 24
Peak memory 206500 kb
Host smart-f2d85060-01c3-48f7-8491-c4ed6c8bc677
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512931583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1512931583
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2961952462
Short name T939
Test name
Test status
Simulation time 45412815 ps
CPU time 1.31 seconds
Started May 16 02:39:00 PM PDT 24
Finished May 16 02:39:04 PM PDT 24
Peak memory 214392 kb
Host smart-04465ae5-cca1-4106-9e17-4864b9c741f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961952462 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2961952462
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.408947419
Short name T237
Test name
Test status
Simulation time 38743479 ps
CPU time 0.89 seconds
Started May 16 02:38:58 PM PDT 24
Finished May 16 02:39:01 PM PDT 24
Peak memory 206160 kb
Host smart-cea12396-84b5-438a-b893-64df6bc04f3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408947419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.408947419
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.327581585
Short name T876
Test name
Test status
Simulation time 14244740 ps
CPU time 0.9 seconds
Started May 16 02:38:57 PM PDT 24
Finished May 16 02:39:01 PM PDT 24
Peak memory 205956 kb
Host smart-c5766c39-1a8f-43a8-801f-bab84e4cf5e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327581585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.327581585
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2672964773
Short name T933
Test name
Test status
Simulation time 46428963 ps
CPU time 1.35 seconds
Started May 16 02:38:58 PM PDT 24
Finished May 16 02:39:02 PM PDT 24
Peak memory 206224 kb
Host smart-6e3bdae4-83db-4a42-8f18-9411d23d0ef5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672964773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2672964773
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2541261857
Short name T881
Test name
Test status
Simulation time 28875870 ps
CPU time 1.85 seconds
Started May 16 02:38:57 PM PDT 24
Finished May 16 02:39:02 PM PDT 24
Peak memory 222616 kb
Host smart-42aa9c65-fb5d-4d81-aacc-b6b0a692776a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541261857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2541261857
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1568721646
Short name T862
Test name
Test status
Simulation time 54821574 ps
CPU time 1.88 seconds
Started May 16 02:38:58 PM PDT 24
Finished May 16 02:39:03 PM PDT 24
Peak memory 214332 kb
Host smart-a61d9bdf-fcd2-44d2-b805-0e0003786c49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568721646 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1568721646
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3018355990
Short name T226
Test name
Test status
Simulation time 23190750 ps
CPU time 0.87 seconds
Started May 16 02:38:57 PM PDT 24
Finished May 16 02:39:01 PM PDT 24
Peak memory 206132 kb
Host smart-2d745931-56e3-4c0e-950a-c7c52f9ea433
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018355990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3018355990
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.4064669502
Short name T859
Test name
Test status
Simulation time 43129722 ps
CPU time 0.93 seconds
Started May 16 02:38:58 PM PDT 24
Finished May 16 02:39:03 PM PDT 24
Peak memory 206016 kb
Host smart-2ba3dfd2-c2b4-4654-bb94-a48e508f6046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064669502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.4064669502
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3362477217
Short name T909
Test name
Test status
Simulation time 59759387 ps
CPU time 1.35 seconds
Started May 16 02:38:59 PM PDT 24
Finished May 16 02:39:03 PM PDT 24
Peak memory 206172 kb
Host smart-ced819e7-41ea-4a73-a925-34bc51b6a941
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362477217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3362477217
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1748627602
Short name T912
Test name
Test status
Simulation time 269173056 ps
CPU time 2.04 seconds
Started May 16 02:38:59 PM PDT 24
Finished May 16 02:39:04 PM PDT 24
Peak memory 214384 kb
Host smart-27bf7c23-b2c2-4280-bf24-764f8add321a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748627602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1748627602
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4231939216
Short name T934
Test name
Test status
Simulation time 150902534 ps
CPU time 2.36 seconds
Started May 16 02:38:58 PM PDT 24
Finished May 16 02:39:04 PM PDT 24
Peak memory 206128 kb
Host smart-eea63469-5dd8-4a6e-bd08-022b7071dc45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231939216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.4231939216
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2541448746
Short name T965
Test name
Test status
Simulation time 33043054 ps
CPU time 1.61 seconds
Started May 16 02:38:59 PM PDT 24
Finished May 16 02:39:04 PM PDT 24
Peak memory 214384 kb
Host smart-fe756b4c-96be-4ca4-b0a6-bb9fc9893b77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541448746 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2541448746
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3120504133
Short name T238
Test name
Test status
Simulation time 56756925 ps
CPU time 0.86 seconds
Started May 16 02:38:58 PM PDT 24
Finished May 16 02:39:02 PM PDT 24
Peak memory 205956 kb
Host smart-7f20dc6f-fa17-40e0-8439-497f5ea82f7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120504133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3120504133
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.528109597
Short name T976
Test name
Test status
Simulation time 91158370 ps
CPU time 0.9 seconds
Started May 16 02:38:58 PM PDT 24
Finished May 16 02:39:02 PM PDT 24
Peak memory 206040 kb
Host smart-6dd6935e-7486-4144-ab1a-29fe80d8ecc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528109597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.528109597
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2052845627
Short name T887
Test name
Test status
Simulation time 31244070 ps
CPU time 1.38 seconds
Started May 16 02:38:58 PM PDT 24
Finished May 16 02:39:02 PM PDT 24
Peak memory 206196 kb
Host smart-7d9c5004-60e6-4c2c-a3f3-5f6f75cc7365
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052845627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2052845627
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.345101616
Short name T871
Test name
Test status
Simulation time 94114287 ps
CPU time 3.7 seconds
Started May 16 02:38:56 PM PDT 24
Finished May 16 02:39:03 PM PDT 24
Peak memory 214356 kb
Host smart-e0c53009-d054-4bd7-b853-f9a32117f371
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345101616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.345101616
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3074272778
Short name T977
Test name
Test status
Simulation time 249285829 ps
CPU time 2.38 seconds
Started May 16 02:38:58 PM PDT 24
Finished May 16 02:39:03 PM PDT 24
Peak memory 206140 kb
Host smart-4a06bac1-58a4-44d6-8f6f-2af8767dbad0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074272778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3074272778
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2760120389
Short name T236
Test name
Test status
Simulation time 27807983 ps
CPU time 1.28 seconds
Started May 16 02:38:19 PM PDT 24
Finished May 16 02:38:24 PM PDT 24
Peak memory 206176 kb
Host smart-98000ca8-4ff0-4a48-b0a8-3c0a091c1fc9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760120389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2760120389
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2520078535
Short name T954
Test name
Test status
Simulation time 196674514 ps
CPU time 5.1 seconds
Started May 16 02:38:19 PM PDT 24
Finished May 16 02:38:28 PM PDT 24
Peak memory 206192 kb
Host smart-07415d00-1580-455e-84ae-990fb9a29719
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520078535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2520078535
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2375968620
Short name T906
Test name
Test status
Simulation time 52211085 ps
CPU time 0.98 seconds
Started May 16 02:38:17 PM PDT 24
Finished May 16 02:38:22 PM PDT 24
Peak memory 206116 kb
Host smart-a9f4b1a4-c575-4e10-afa8-831c5d6d7df0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375968620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2375968620
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2140201206
Short name T870
Test name
Test status
Simulation time 79747724 ps
CPU time 2.08 seconds
Started May 16 02:38:20 PM PDT 24
Finished May 16 02:38:27 PM PDT 24
Peak memory 214472 kb
Host smart-640aa9ed-8f2e-41b3-80b3-216bddee0a33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140201206 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2140201206
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.291298070
Short name T241
Test name
Test status
Simulation time 23072015 ps
CPU time 0.9 seconds
Started May 16 02:38:20 PM PDT 24
Finished May 16 02:38:25 PM PDT 24
Peak memory 206188 kb
Host smart-0383fdf9-d543-4252-a63a-23706bb00eb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291298070 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.291298070
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1155685503
Short name T923
Test name
Test status
Simulation time 12979022 ps
CPU time 0.88 seconds
Started May 16 02:38:17 PM PDT 24
Finished May 16 02:38:21 PM PDT 24
Peak memory 206040 kb
Host smart-ba356b78-2661-4e41-9796-26db136ecd72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155685503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1155685503
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.249609051
Short name T908
Test name
Test status
Simulation time 25510064 ps
CPU time 1.18 seconds
Started May 16 02:38:19 PM PDT 24
Finished May 16 02:38:25 PM PDT 24
Peak memory 206168 kb
Host smart-ec1254cd-06e1-4b5e-9854-c94894d525cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249609051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out
standing.249609051
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1069715506
Short name T960
Test name
Test status
Simulation time 84949211 ps
CPU time 2.01 seconds
Started May 16 02:38:11 PM PDT 24
Finished May 16 02:38:17 PM PDT 24
Peak memory 214364 kb
Host smart-16592fd8-88ac-4ec7-8c7f-2ddee490078e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069715506 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1069715506
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3669075079
Short name T901
Test name
Test status
Simulation time 159708641 ps
CPU time 2.33 seconds
Started May 16 02:38:19 PM PDT 24
Finished May 16 02:38:25 PM PDT 24
Peak memory 206188 kb
Host smart-8bfd9631-6417-4aa2-b36c-b36a766c995d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669075079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3669075079
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2105660235
Short name T968
Test name
Test status
Simulation time 29013621 ps
CPU time 0.95 seconds
Started May 16 02:38:57 PM PDT 24
Finished May 16 02:39:01 PM PDT 24
Peak memory 205984 kb
Host smart-92908003-ef48-4e2a-9a45-e16ef2b72daf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105660235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2105660235
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2955345206
Short name T931
Test name
Test status
Simulation time 30697043 ps
CPU time 0.85 seconds
Started May 16 02:38:58 PM PDT 24
Finished May 16 02:39:02 PM PDT 24
Peak memory 205976 kb
Host smart-54cbff89-1d9c-4690-94a3-1bf2c8cb4be9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955345206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2955345206
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3300259954
Short name T973
Test name
Test status
Simulation time 23066647 ps
CPU time 0.87 seconds
Started May 16 02:38:57 PM PDT 24
Finished May 16 02:39:00 PM PDT 24
Peak memory 205988 kb
Host smart-75013cfa-3fcd-4abd-a850-2b3195c6bf7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300259954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3300259954
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3445438597
Short name T943
Test name
Test status
Simulation time 27032934 ps
CPU time 0.85 seconds
Started May 16 02:38:58 PM PDT 24
Finished May 16 02:39:01 PM PDT 24
Peak memory 206016 kb
Host smart-f87eff24-19cc-49ff-8e16-68568ba25e52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445438597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3445438597
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1490108175
Short name T854
Test name
Test status
Simulation time 121628400 ps
CPU time 0.94 seconds
Started May 16 02:38:58 PM PDT 24
Finished May 16 02:39:02 PM PDT 24
Peak memory 206156 kb
Host smart-78c0be98-9f28-4939-bfb0-c7340b2c4ab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490108175 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1490108175
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.4254170629
Short name T880
Test name
Test status
Simulation time 12750585 ps
CPU time 0.87 seconds
Started May 16 02:39:07 PM PDT 24
Finished May 16 02:39:09 PM PDT 24
Peak memory 206016 kb
Host smart-c7ccd52b-78ac-4342-bb8a-df4998c1ad4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254170629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.4254170629
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1388895798
Short name T861
Test name
Test status
Simulation time 42427203 ps
CPU time 0.89 seconds
Started May 16 02:39:09 PM PDT 24
Finished May 16 02:39:13 PM PDT 24
Peak memory 206100 kb
Host smart-871bfa44-be04-4eab-bca4-8d2773491816
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388895798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1388895798
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1119402611
Short name T856
Test name
Test status
Simulation time 11838050 ps
CPU time 0.87 seconds
Started May 16 02:39:09 PM PDT 24
Finished May 16 02:39:13 PM PDT 24
Peak memory 206028 kb
Host smart-da3cc197-781f-4818-b4b0-d9d9d08d3b04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119402611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1119402611
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1905000550
Short name T959
Test name
Test status
Simulation time 14894832 ps
CPU time 0.91 seconds
Started May 16 02:39:08 PM PDT 24
Finished May 16 02:39:11 PM PDT 24
Peak memory 206076 kb
Host smart-953161fe-791b-4433-a238-4f0111c28522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905000550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1905000550
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.686086632
Short name T907
Test name
Test status
Simulation time 43751659 ps
CPU time 0.86 seconds
Started May 16 02:39:09 PM PDT 24
Finished May 16 02:39:14 PM PDT 24
Peak memory 206052 kb
Host smart-c5d56558-02ff-4f56-94b7-5b679eaf5eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686086632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.686086632
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3521159131
Short name T864
Test name
Test status
Simulation time 17343133 ps
CPU time 1.06 seconds
Started May 16 02:38:18 PM PDT 24
Finished May 16 02:38:22 PM PDT 24
Peak memory 206132 kb
Host smart-6c2d146f-5693-428d-8971-ebb01609ed19
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521159131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3521159131
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1921123374
Short name T893
Test name
Test status
Simulation time 155201911 ps
CPU time 3.08 seconds
Started May 16 02:38:19 PM PDT 24
Finished May 16 02:38:27 PM PDT 24
Peak memory 206120 kb
Host smart-d7274c7b-e2a1-4a78-beaf-43577dca7f6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921123374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1921123374
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2126201201
Short name T234
Test name
Test status
Simulation time 12608123 ps
CPU time 0.89 seconds
Started May 16 02:38:17 PM PDT 24
Finished May 16 02:38:22 PM PDT 24
Peak memory 206192 kb
Host smart-2c2e018c-3381-48a2-ad53-950afe2ea457
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126201201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2126201201
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.4031910116
Short name T913
Test name
Test status
Simulation time 25858068 ps
CPU time 1.26 seconds
Started May 16 02:38:17 PM PDT 24
Finished May 16 02:38:21 PM PDT 24
Peak memory 214388 kb
Host smart-a09850b7-eb44-4b98-abd8-24f45c4bfd28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031910116 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.4031910116
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.4252574469
Short name T888
Test name
Test status
Simulation time 48935574 ps
CPU time 0.88 seconds
Started May 16 02:38:19 PM PDT 24
Finished May 16 02:38:24 PM PDT 24
Peak memory 206120 kb
Host smart-fec5f5f3-47d2-4d81-9e01-a650820fdf0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252574469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.4252574469
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3321120425
Short name T910
Test name
Test status
Simulation time 21255496 ps
CPU time 0.86 seconds
Started May 16 02:38:20 PM PDT 24
Finished May 16 02:38:25 PM PDT 24
Peak memory 205936 kb
Host smart-143853b7-5a2a-436e-8c42-7c8310e31074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321120425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3321120425
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2732457295
Short name T936
Test name
Test status
Simulation time 50758255 ps
CPU time 1 seconds
Started May 16 02:38:19 PM PDT 24
Finished May 16 02:38:23 PM PDT 24
Peak memory 206216 kb
Host smart-bacd6b22-d128-45b9-9fff-e773603c848a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732457295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2732457295
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.991581273
Short name T921
Test name
Test status
Simulation time 25748127 ps
CPU time 1.88 seconds
Started May 16 02:38:20 PM PDT 24
Finished May 16 02:38:26 PM PDT 24
Peak memory 214484 kb
Host smart-42fe0a6d-64ef-4808-9f0f-f70770e5b56d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991581273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.991581273
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3199218764
Short name T974
Test name
Test status
Simulation time 80305159 ps
CPU time 1.53 seconds
Started May 16 02:38:19 PM PDT 24
Finished May 16 02:38:25 PM PDT 24
Peak memory 206060 kb
Host smart-0745d9e5-0e3d-40a7-b73f-c6822b504cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199218764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3199218764
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3930137652
Short name T875
Test name
Test status
Simulation time 18422353 ps
CPU time 0.84 seconds
Started May 16 02:39:07 PM PDT 24
Finished May 16 02:39:10 PM PDT 24
Peak memory 205948 kb
Host smart-a5f6455f-622b-4ab4-9a0e-82234be22d59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930137652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3930137652
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3254906703
Short name T929
Test name
Test status
Simulation time 37081250 ps
CPU time 0.82 seconds
Started May 16 02:39:10 PM PDT 24
Finished May 16 02:39:14 PM PDT 24
Peak memory 205964 kb
Host smart-b3fe6f8c-aeae-4ed8-a8b1-495dfa70ee0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254906703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3254906703
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1377221328
Short name T932
Test name
Test status
Simulation time 20365777 ps
CPU time 0.86 seconds
Started May 16 02:39:11 PM PDT 24
Finished May 16 02:39:15 PM PDT 24
Peak memory 206012 kb
Host smart-f1767653-bf12-4e81-80ae-34d5486a4ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377221328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1377221328
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1135058605
Short name T867
Test name
Test status
Simulation time 11692213 ps
CPU time 0.86 seconds
Started May 16 02:39:08 PM PDT 24
Finished May 16 02:39:11 PM PDT 24
Peak memory 206068 kb
Host smart-1a619a22-efa9-4315-af29-660a030bf176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135058605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1135058605
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2927569415
Short name T863
Test name
Test status
Simulation time 24356662 ps
CPU time 0.87 seconds
Started May 16 02:39:10 PM PDT 24
Finished May 16 02:39:15 PM PDT 24
Peak memory 206036 kb
Host smart-1f4e80b2-0b67-4b7b-a358-8abca2f5ce2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927569415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2927569415
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1507180040
Short name T958
Test name
Test status
Simulation time 14204001 ps
CPU time 0.89 seconds
Started May 16 02:39:09 PM PDT 24
Finished May 16 02:39:13 PM PDT 24
Peak memory 206060 kb
Host smart-13532ac7-fd58-4f34-b629-5a90b665d634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507180040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1507180040
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.4001830219
Short name T978
Test name
Test status
Simulation time 48183868 ps
CPU time 0.89 seconds
Started May 16 02:39:10 PM PDT 24
Finished May 16 02:39:14 PM PDT 24
Peak memory 206040 kb
Host smart-6eb8a765-2d76-45a9-8ed5-253272ca74de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001830219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.4001830219
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2374802161
Short name T898
Test name
Test status
Simulation time 29541074 ps
CPU time 0.89 seconds
Started May 16 02:39:10 PM PDT 24
Finished May 16 02:39:15 PM PDT 24
Peak memory 206128 kb
Host smart-f9c29a00-4ffc-4f7e-90da-95b04f565806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374802161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2374802161
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3732823616
Short name T926
Test name
Test status
Simulation time 49921844 ps
CPU time 0.89 seconds
Started May 16 02:39:08 PM PDT 24
Finished May 16 02:39:11 PM PDT 24
Peak memory 206064 kb
Host smart-4ad4ea8d-3553-4b66-a25b-195383db5ae3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732823616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3732823616
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2097425111
Short name T873
Test name
Test status
Simulation time 33309264 ps
CPU time 0.86 seconds
Started May 16 02:39:08 PM PDT 24
Finished May 16 02:39:12 PM PDT 24
Peak memory 205944 kb
Host smart-4e7dfa57-0a92-48fa-81d3-39d6094da47a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097425111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2097425111
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.286067103
Short name T966
Test name
Test status
Simulation time 270217570 ps
CPU time 1.63 seconds
Started May 16 02:38:17 PM PDT 24
Finished May 16 02:38:21 PM PDT 24
Peak memory 206120 kb
Host smart-9f0af269-17aa-410a-b0c5-b79020e17020
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286067103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.286067103
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.794672439
Short name T971
Test name
Test status
Simulation time 1206572194 ps
CPU time 3.91 seconds
Started May 16 02:38:20 PM PDT 24
Finished May 16 02:38:28 PM PDT 24
Peak memory 206272 kb
Host smart-762acbd4-c9ac-4d6e-88e6-c8a9f50856c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794672439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.794672439
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.335069786
Short name T945
Test name
Test status
Simulation time 25218670 ps
CPU time 0.91 seconds
Started May 16 02:38:17 PM PDT 24
Finished May 16 02:38:22 PM PDT 24
Peak memory 206120 kb
Host smart-e56d70a3-3292-4038-aadf-7c4f23057834
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335069786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.335069786
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3241390951
Short name T911
Test name
Test status
Simulation time 24248248 ps
CPU time 1.59 seconds
Started May 16 02:38:18 PM PDT 24
Finished May 16 02:38:24 PM PDT 24
Peak memory 214496 kb
Host smart-fcffb924-2dcd-40ff-85c6-88af926a0101
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241390951 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3241390951
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1259052849
Short name T225
Test name
Test status
Simulation time 14937923 ps
CPU time 0.96 seconds
Started May 16 02:38:20 PM PDT 24
Finished May 16 02:38:25 PM PDT 24
Peak memory 206200 kb
Host smart-cb835900-0355-45a6-899b-87ba738889db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259052849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1259052849
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3849972621
Short name T935
Test name
Test status
Simulation time 19790783 ps
CPU time 0.83 seconds
Started May 16 02:38:21 PM PDT 24
Finished May 16 02:38:25 PM PDT 24
Peak memory 205960 kb
Host smart-70701cb9-f2a6-472c-a8ef-907b6c9f5d93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849972621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3849972621
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.151060578
Short name T946
Test name
Test status
Simulation time 107915324 ps
CPU time 1.07 seconds
Started May 16 02:38:19 PM PDT 24
Finished May 16 02:38:24 PM PDT 24
Peak memory 206104 kb
Host smart-f7f0465d-ffc4-4a29-b009-1e7a0dac3122
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151060578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.151060578
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.603268006
Short name T975
Test name
Test status
Simulation time 354113324 ps
CPU time 2.3 seconds
Started May 16 02:38:19 PM PDT 24
Finished May 16 02:38:25 PM PDT 24
Peak memory 214436 kb
Host smart-57004c02-bd0b-453e-969d-931d1f7ac3e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603268006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.603268006
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.633151495
Short name T964
Test name
Test status
Simulation time 97995054 ps
CPU time 2.72 seconds
Started May 16 02:38:19 PM PDT 24
Finished May 16 02:38:25 PM PDT 24
Peak memory 206448 kb
Host smart-68bfb34d-10dc-4c95-b7a1-0ae74134eadc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633151495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.633151495
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1338821292
Short name T892
Test name
Test status
Simulation time 11918409 ps
CPU time 0.88 seconds
Started May 16 02:39:08 PM PDT 24
Finished May 16 02:39:10 PM PDT 24
Peak memory 206040 kb
Host smart-ab124421-2880-44a6-bef6-56a9bd59f860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338821292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1338821292
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.499009857
Short name T872
Test name
Test status
Simulation time 11501240 ps
CPU time 0.92 seconds
Started May 16 02:39:08 PM PDT 24
Finished May 16 02:39:11 PM PDT 24
Peak memory 205920 kb
Host smart-fe991be1-d64c-4fe7-a0ac-9d2c1a048580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499009857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.499009857
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.820867767
Short name T878
Test name
Test status
Simulation time 19201802 ps
CPU time 0.82 seconds
Started May 16 02:39:09 PM PDT 24
Finished May 16 02:39:13 PM PDT 24
Peak memory 205924 kb
Host smart-298e1761-ce00-41c6-a52d-63a6cab5ffc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820867767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.820867767
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.692868375
Short name T980
Test name
Test status
Simulation time 36970920 ps
CPU time 0.81 seconds
Started May 16 02:39:11 PM PDT 24
Finished May 16 02:39:16 PM PDT 24
Peak memory 205860 kb
Host smart-da4d1877-d56e-4b23-b8aa-06ccbdd7fbb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692868375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.692868375
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.522478756
Short name T858
Test name
Test status
Simulation time 45117762 ps
CPU time 0.91 seconds
Started May 16 02:39:08 PM PDT 24
Finished May 16 02:39:12 PM PDT 24
Peak memory 206044 kb
Host smart-fe0d9e51-adaf-43ea-ae03-bf8d764c07bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522478756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.522478756
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2626550215
Short name T928
Test name
Test status
Simulation time 29680158 ps
CPU time 0.81 seconds
Started May 16 02:39:09 PM PDT 24
Finished May 16 02:39:13 PM PDT 24
Peak memory 205948 kb
Host smart-064e451d-f721-4935-a83f-c45bdbb1d9fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626550215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2626550215
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.4001190933
Short name T855
Test name
Test status
Simulation time 38313865 ps
CPU time 0.83 seconds
Started May 16 02:39:09 PM PDT 24
Finished May 16 02:39:14 PM PDT 24
Peak memory 205948 kb
Host smart-a810512f-23d1-4678-b942-4449c67b2b0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001190933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.4001190933
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1457980515
Short name T914
Test name
Test status
Simulation time 55047529 ps
CPU time 0.91 seconds
Started May 16 02:39:08 PM PDT 24
Finished May 16 02:39:12 PM PDT 24
Peak memory 206000 kb
Host smart-b99be6ca-54c1-4a7a-86df-6e7f478113a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457980515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1457980515
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.252250494
Short name T897
Test name
Test status
Simulation time 47002747 ps
CPU time 0.91 seconds
Started May 16 02:39:09 PM PDT 24
Finished May 16 02:39:14 PM PDT 24
Peak memory 206048 kb
Host smart-aa179796-8fc4-4dd1-be62-ce8cab26583a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252250494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.252250494
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.631028799
Short name T900
Test name
Test status
Simulation time 23077264 ps
CPU time 0.84 seconds
Started May 16 02:39:11 PM PDT 24
Finished May 16 02:39:16 PM PDT 24
Peak memory 205948 kb
Host smart-651ae172-a0ad-4af1-95a2-afadcf83222c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631028799 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.631028799
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.447795661
Short name T857
Test name
Test status
Simulation time 20388267 ps
CPU time 1.13 seconds
Started May 16 02:38:20 PM PDT 24
Finished May 16 02:38:26 PM PDT 24
Peak memory 214392 kb
Host smart-aa1b6d01-ba89-4d33-a135-c3bc220dd066
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447795661 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.447795661
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3889755239
Short name T220
Test name
Test status
Simulation time 136965194 ps
CPU time 0.9 seconds
Started May 16 02:38:19 PM PDT 24
Finished May 16 02:38:24 PM PDT 24
Peak memory 206168 kb
Host smart-2eac2b1d-47a5-4102-a567-10c0feca2709
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889755239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3889755239
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.4182167615
Short name T919
Test name
Test status
Simulation time 20651846 ps
CPU time 0.92 seconds
Started May 16 02:38:19 PM PDT 24
Finished May 16 02:38:24 PM PDT 24
Peak memory 206008 kb
Host smart-f6360c52-bc1f-49a0-bf27-767c05b4e05b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182167615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.4182167615
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2552725840
Short name T242
Test name
Test status
Simulation time 75681495 ps
CPU time 1.11 seconds
Started May 16 02:38:19 PM PDT 24
Finished May 16 02:38:24 PM PDT 24
Peak memory 206128 kb
Host smart-7fe4dde8-7e47-40bb-aeab-d4ad8d0ee5ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552725840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2552725840
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3815807297
Short name T930
Test name
Test status
Simulation time 41870753 ps
CPU time 2.58 seconds
Started May 16 02:38:18 PM PDT 24
Finished May 16 02:38:24 PM PDT 24
Peak memory 214340 kb
Host smart-cb89056b-09c8-457a-a60d-f23a541fbbc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815807297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3815807297
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3294875879
Short name T259
Test name
Test status
Simulation time 235654115 ps
CPU time 2.06 seconds
Started May 16 02:38:19 PM PDT 24
Finished May 16 02:38:25 PM PDT 24
Peak memory 206184 kb
Host smart-97d8fad0-4e7e-45c5-abc6-7cc29e836dc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294875879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3294875879
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3992541697
Short name T885
Test name
Test status
Simulation time 133004296 ps
CPU time 1.26 seconds
Started May 16 02:38:26 PM PDT 24
Finished May 16 02:38:30 PM PDT 24
Peak memory 214476 kb
Host smart-f86c4ac9-ae56-4bae-bf9e-9b71114eea6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992541697 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3992541697
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3568359122
Short name T222
Test name
Test status
Simulation time 36880447 ps
CPU time 0.8 seconds
Started May 16 02:38:28 PM PDT 24
Finished May 16 02:38:33 PM PDT 24
Peak memory 206076 kb
Host smart-a608f6d7-afbb-403a-bd6a-b97c26a53596
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568359122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3568359122
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3941738985
Short name T886
Test name
Test status
Simulation time 21828282 ps
CPU time 0.88 seconds
Started May 16 02:38:28 PM PDT 24
Finished May 16 02:38:34 PM PDT 24
Peak memory 205996 kb
Host smart-7c9b30c1-b22a-4fab-967f-9f199ab739bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941738985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3941738985
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3691475297
Short name T903
Test name
Test status
Simulation time 17896841 ps
CPU time 1.14 seconds
Started May 16 02:38:30 PM PDT 24
Finished May 16 02:38:36 PM PDT 24
Peak memory 206280 kb
Host smart-8c7ba871-6443-41ca-b958-08b94b091b69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691475297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3691475297
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2151283989
Short name T860
Test name
Test status
Simulation time 25824596 ps
CPU time 1.62 seconds
Started May 16 02:38:26 PM PDT 24
Finished May 16 02:38:31 PM PDT 24
Peak memory 214444 kb
Host smart-364d7e42-cd00-4911-b780-7a3ebd5a714d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151283989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2151283989
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2380510036
Short name T970
Test name
Test status
Simulation time 273921038 ps
CPU time 2.1 seconds
Started May 16 02:38:29 PM PDT 24
Finished May 16 02:38:37 PM PDT 24
Peak memory 206512 kb
Host smart-bfcff96d-791b-4bd3-81db-09791687bfa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380510036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2380510036
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3902726400
Short name T941
Test name
Test status
Simulation time 46066858 ps
CPU time 1.18 seconds
Started May 16 02:38:28 PM PDT 24
Finished May 16 02:38:33 PM PDT 24
Peak memory 214492 kb
Host smart-894f5d5b-0071-4fe3-a7b2-81ac1ad08aa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902726400 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3902726400
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.802795209
Short name T240
Test name
Test status
Simulation time 44947443 ps
CPU time 0.92 seconds
Started May 16 02:38:28 PM PDT 24
Finished May 16 02:38:34 PM PDT 24
Peak memory 206024 kb
Host smart-06012aef-d7c5-42db-97bf-c32f7bc76947
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802795209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.802795209
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1317776747
Short name T947
Test name
Test status
Simulation time 20213658 ps
CPU time 0.83 seconds
Started May 16 02:38:27 PM PDT 24
Finished May 16 02:38:32 PM PDT 24
Peak memory 205960 kb
Host smart-72588e15-6895-4265-b860-422063aa6ca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317776747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1317776747
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.763534111
Short name T223
Test name
Test status
Simulation time 36595458 ps
CPU time 1.02 seconds
Started May 16 02:38:28 PM PDT 24
Finished May 16 02:38:34 PM PDT 24
Peak memory 206120 kb
Host smart-35404858-4239-4088-894c-a002803e504b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763534111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.763534111
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1383620212
Short name T890
Test name
Test status
Simulation time 95899173 ps
CPU time 2.02 seconds
Started May 16 02:38:32 PM PDT 24
Finished May 16 02:38:38 PM PDT 24
Peak memory 214376 kb
Host smart-f2079c3b-a4d9-4008-a79c-c626af04cc86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383620212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1383620212
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2243356963
Short name T255
Test name
Test status
Simulation time 334720695 ps
CPU time 1.59 seconds
Started May 16 02:38:29 PM PDT 24
Finished May 16 02:38:36 PM PDT 24
Peak memory 206276 kb
Host smart-2be46b34-0758-4a9e-878b-8d77eec13927
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243356963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2243356963
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.4002926246
Short name T916
Test name
Test status
Simulation time 74193552 ps
CPU time 1.12 seconds
Started May 16 02:38:27 PM PDT 24
Finished May 16 02:38:32 PM PDT 24
Peak memory 214492 kb
Host smart-4d4d17d6-ce57-4663-a981-b36540ea9578
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002926246 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.4002926246
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2747816559
Short name T228
Test name
Test status
Simulation time 41035221 ps
CPU time 0.91 seconds
Started May 16 02:38:28 PM PDT 24
Finished May 16 02:38:34 PM PDT 24
Peak memory 206180 kb
Host smart-e484e330-5042-4fdc-b786-478b28824278
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747816559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2747816559
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2783505051
Short name T962
Test name
Test status
Simulation time 13568618 ps
CPU time 0.88 seconds
Started May 16 02:38:27 PM PDT 24
Finished May 16 02:38:32 PM PDT 24
Peak memory 206000 kb
Host smart-837e2527-ebbf-4dc9-b65a-37f0fc1937b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783505051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2783505051
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.4237673347
Short name T224
Test name
Test status
Simulation time 32685114 ps
CPU time 1.08 seconds
Started May 16 02:38:31 PM PDT 24
Finished May 16 02:38:36 PM PDT 24
Peak memory 206148 kb
Host smart-04fd94ab-5581-42d2-81cf-d22349b4c030
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237673347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.4237673347
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.750096902
Short name T899
Test name
Test status
Simulation time 516774686 ps
CPU time 4.31 seconds
Started May 16 02:38:30 PM PDT 24
Finished May 16 02:38:39 PM PDT 24
Peak memory 214452 kb
Host smart-264a1a11-17c4-4eed-bdc5-38b2adf66d95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750096902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.750096902
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.811685191
Short name T896
Test name
Test status
Simulation time 171889163 ps
CPU time 2.57 seconds
Started May 16 02:38:28 PM PDT 24
Finished May 16 02:38:36 PM PDT 24
Peak memory 214368 kb
Host smart-2e1baa57-25b2-4c1a-bd1d-32dd28156ba7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811685191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.811685191
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2181833816
Short name T915
Test name
Test status
Simulation time 79484728 ps
CPU time 1.57 seconds
Started May 16 02:38:27 PM PDT 24
Finished May 16 02:38:33 PM PDT 24
Peak memory 214440 kb
Host smart-0cd76b0d-1106-44f7-94d7-c18e8a859349
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181833816 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2181833816
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3394699561
Short name T227
Test name
Test status
Simulation time 13862092 ps
CPU time 0.89 seconds
Started May 16 02:38:26 PM PDT 24
Finished May 16 02:38:30 PM PDT 24
Peak memory 206180 kb
Host smart-75ae30e8-694e-44e8-8fac-98ea469ee92a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394699561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3394699561
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1770769148
Short name T972
Test name
Test status
Simulation time 32648868 ps
CPU time 0.85 seconds
Started May 16 02:38:29 PM PDT 24
Finished May 16 02:38:35 PM PDT 24
Peak memory 206048 kb
Host smart-eaf881fd-7049-4132-b1af-c35dd3720cff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770769148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1770769148
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.4054917911
Short name T925
Test name
Test status
Simulation time 30860646 ps
CPU time 1.27 seconds
Started May 16 02:38:26 PM PDT 24
Finished May 16 02:38:31 PM PDT 24
Peak memory 206156 kb
Host smart-e30b23a5-5a05-4a6e-93fa-7102d3556100
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054917911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.4054917911
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1856022668
Short name T877
Test name
Test status
Simulation time 567015776 ps
CPU time 2.89 seconds
Started May 16 02:38:32 PM PDT 24
Finished May 16 02:38:39 PM PDT 24
Peak memory 214476 kb
Host smart-a79612c9-5a24-43ad-93cf-53d01c822b7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856022668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1856022668
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.616038354
Short name T263
Test name
Test status
Simulation time 234391366 ps
CPU time 1.61 seconds
Started May 16 02:38:29 PM PDT 24
Finished May 16 02:38:36 PM PDT 24
Peak memory 214380 kb
Host smart-032f6b30-4dcc-47f9-9b31-3b9ebda65801
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616038354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.616038354
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.1906041712
Short name T65
Test name
Test status
Simulation time 29431651 ps
CPU time 1.27 seconds
Started May 16 02:01:17 PM PDT 24
Finished May 16 02:01:20 PM PDT 24
Peak memory 215348 kb
Host smart-455e8505-e62e-4560-8a55-d83ea126a1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906041712 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1906041712
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.743686742
Short name T615
Test name
Test status
Simulation time 16027041 ps
CPU time 0.91 seconds
Started May 16 02:01:14 PM PDT 24
Finished May 16 02:01:17 PM PDT 24
Peak memory 206288 kb
Host smart-c3257b1d-a683-4a16-8012-47d5a67f5676
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743686742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.743686742
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.3971746121
Short name T83
Test name
Test status
Simulation time 11157163 ps
CPU time 0.88 seconds
Started May 16 02:01:14 PM PDT 24
Finished May 16 02:01:17 PM PDT 24
Peak memory 216100 kb
Host smart-aa0f6088-7e36-4318-a757-f145b418229a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971746121 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3971746121
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.1653808444
Short name T720
Test name
Test status
Simulation time 24359504 ps
CPU time 0.92 seconds
Started May 16 02:01:13 PM PDT 24
Finished May 16 02:01:16 PM PDT 24
Peak memory 218132 kb
Host smart-0278d3e2-c7c5-43d0-99c7-abc22e257c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653808444 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1653808444
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.615646820
Short name T774
Test name
Test status
Simulation time 25247048 ps
CPU time 1.05 seconds
Started May 16 02:01:14 PM PDT 24
Finished May 16 02:01:17 PM PDT 24
Peak memory 215060 kb
Host smart-393a57ba-a3f1-447e-8c17-44c1d5a2ced7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615646820 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.615646820
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.859564484
Short name T18
Test name
Test status
Simulation time 478112779 ps
CPU time 7.77 seconds
Started May 16 02:01:18 PM PDT 24
Finished May 16 02:01:27 PM PDT 24
Peak memory 237044 kb
Host smart-65c09d8c-b681-4f7d-bad3-b6cb5fe3a1fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859564484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.859564484
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.1143179665
Short name T755
Test name
Test status
Simulation time 19170695 ps
CPU time 1.04 seconds
Started May 16 02:01:03 PM PDT 24
Finished May 16 02:01:05 PM PDT 24
Peak memory 214968 kb
Host smart-8f0c2421-2fd7-4ded-950a-7be163459498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143179665 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1143179665
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.437730371
Short name T637
Test name
Test status
Simulation time 34680102 ps
CPU time 1.23 seconds
Started May 16 02:01:14 PM PDT 24
Finished May 16 02:01:17 PM PDT 24
Peak memory 205996 kb
Host smart-720efd40-f232-4f84-a674-52c0609244bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437730371 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.437730371
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2976329550
Short name T373
Test name
Test status
Simulation time 58665320505 ps
CPU time 1448.17 seconds
Started May 16 02:01:13 PM PDT 24
Finished May 16 02:25:24 PM PDT 24
Peak memory 223860 kb
Host smart-e540b936-7d36-4d83-a7c7-16c2279d83bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976329550 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2976329550
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1880107751
Short name T520
Test name
Test status
Simulation time 49079932 ps
CPU time 1.18 seconds
Started May 16 02:01:17 PM PDT 24
Finished May 16 02:01:20 PM PDT 24
Peak memory 215360 kb
Host smart-99f99f1a-3d9c-48fe-8f8f-cd7eea2a8c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880107751 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1880107751
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1700979031
Short name T546
Test name
Test status
Simulation time 15290821 ps
CPU time 0.91 seconds
Started May 16 02:01:25 PM PDT 24
Finished May 16 02:01:27 PM PDT 24
Peak memory 206244 kb
Host smart-64d28d0e-a100-4299-97ab-1b7642932f53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700979031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1700979031
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.1962499552
Short name T722
Test name
Test status
Simulation time 14170796 ps
CPU time 0.94 seconds
Started May 16 02:01:32 PM PDT 24
Finished May 16 02:01:34 PM PDT 24
Peak memory 215812 kb
Host smart-348e9700-a17b-46ca-9bc0-0311dd2cc8b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962499552 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1962499552
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1292726620
Short name T55
Test name
Test status
Simulation time 333540265 ps
CPU time 1.22 seconds
Started May 16 02:01:24 PM PDT 24
Finished May 16 02:01:27 PM PDT 24
Peak memory 216568 kb
Host smart-7cac3d2b-4110-48eb-9463-e2e622de2d36
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292726620 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1292726620
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.1081185761
Short name T184
Test name
Test status
Simulation time 19344385 ps
CPU time 1.05 seconds
Started May 16 02:01:32 PM PDT 24
Finished May 16 02:01:34 PM PDT 24
Peak memory 218180 kb
Host smart-4d4b8016-b3c6-4491-9824-16045080ff5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081185761 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1081185761
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.47883570
Short name T116
Test name
Test status
Simulation time 34365969 ps
CPU time 1.29 seconds
Started May 16 02:01:15 PM PDT 24
Finished May 16 02:01:18 PM PDT 24
Peak memory 216640 kb
Host smart-73a7c835-c2a6-4635-b07c-2dd736e4d45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47883570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.47883570
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.4099079135
Short name T361
Test name
Test status
Simulation time 21146336 ps
CPU time 1.11 seconds
Started May 16 02:01:17 PM PDT 24
Finished May 16 02:01:20 PM PDT 24
Peak memory 215052 kb
Host smart-c2bca1d9-a754-421a-b6a4-1187b194edd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099079135 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.4099079135
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.1333516460
Short name T276
Test name
Test status
Simulation time 38547252 ps
CPU time 0.91 seconds
Started May 16 02:01:15 PM PDT 24
Finished May 16 02:01:18 PM PDT 24
Peak memory 206752 kb
Host smart-fdd91160-9948-41fb-82d6-665c809b0ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333516460 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1333516460
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.1589664093
Short name T707
Test name
Test status
Simulation time 24237278 ps
CPU time 0.88 seconds
Started May 16 02:01:14 PM PDT 24
Finished May 16 02:01:17 PM PDT 24
Peak memory 214920 kb
Host smart-063efbc6-2afa-4b42-81f1-95f9b389c37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589664093 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1589664093
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2849755260
Short name T336
Test name
Test status
Simulation time 26052974 ps
CPU time 1.14 seconds
Started May 16 02:01:14 PM PDT 24
Finished May 16 02:01:18 PM PDT 24
Peak memory 206368 kb
Host smart-c2c90476-0c69-4d74-b5b8-cd1d00b3b0d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849755260 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2849755260
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.3800306890
Short name T272
Test name
Test status
Simulation time 44531008 ps
CPU time 1.23 seconds
Started May 16 02:02:09 PM PDT 24
Finished May 16 02:02:13 PM PDT 24
Peak memory 215272 kb
Host smart-5d9f4c50-59e2-428d-b68a-7c32b32ab576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800306890 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3800306890
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.3832320990
Short name T664
Test name
Test status
Simulation time 83877469 ps
CPU time 1.07 seconds
Started May 16 02:02:09 PM PDT 24
Finished May 16 02:02:13 PM PDT 24
Peak memory 206368 kb
Host smart-09ae98b7-83fc-4136-83ce-36808100d6f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832320990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3832320990
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.584937521
Short name T727
Test name
Test status
Simulation time 14437950 ps
CPU time 0.91 seconds
Started May 16 02:02:07 PM PDT 24
Finished May 16 02:02:11 PM PDT 24
Peak memory 215772 kb
Host smart-3092c6a9-bc68-4c0f-89fe-e57df5ce7a45
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584937521 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.584937521
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.2880543476
Short name T606
Test name
Test status
Simulation time 84862365 ps
CPU time 1.12 seconds
Started May 16 02:02:08 PM PDT 24
Finished May 16 02:02:12 PM PDT 24
Peak memory 217868 kb
Host smart-76dad04e-fe90-4cf4-81e5-2006ca7104eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880543476 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.2880543476
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.3061164228
Short name T425
Test name
Test status
Simulation time 22557642 ps
CPU time 1.08 seconds
Started May 16 02:02:09 PM PDT 24
Finished May 16 02:02:13 PM PDT 24
Peak memory 223448 kb
Host smart-c21ada98-afa7-4c47-b927-a02f40ba25aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061164228 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3061164228
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.591657182
Short name T535
Test name
Test status
Simulation time 59817635 ps
CPU time 1.24 seconds
Started May 16 02:02:09 PM PDT 24
Finished May 16 02:02:14 PM PDT 24
Peak memory 218132 kb
Host smart-0f967ceb-d809-44c4-890c-71f237b32605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591657182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.591657182
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1978321103
Short name T780
Test name
Test status
Simulation time 32295413 ps
CPU time 1.02 seconds
Started May 16 02:02:07 PM PDT 24
Finished May 16 02:02:11 PM PDT 24
Peak memory 223400 kb
Host smart-d09a8091-6918-47f5-8a4e-b857d2a157e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978321103 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1978321103
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2122632304
Short name T433
Test name
Test status
Simulation time 18094033 ps
CPU time 1.07 seconds
Started May 16 02:02:09 PM PDT 24
Finished May 16 02:02:13 PM PDT 24
Peak memory 214992 kb
Host smart-d87e48f0-122a-4142-a7c9-bc775b6b2f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122632304 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2122632304
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3450597367
Short name T479
Test name
Test status
Simulation time 61364852144 ps
CPU time 1601.5 seconds
Started May 16 02:02:09 PM PDT 24
Finished May 16 02:28:54 PM PDT 24
Peak memory 225228 kb
Host smart-aa4f6f67-18f6-4200-a8bb-a4fc4890077a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450597367 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3450597367
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.edn_genbits.77757019
Short name T138
Test name
Test status
Simulation time 69870801 ps
CPU time 1.2 seconds
Started May 16 02:04:36 PM PDT 24
Finished May 16 02:04:40 PM PDT 24
Peak memory 216640 kb
Host smart-28d8274f-73de-4ce2-b5bf-87d79ad361d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77757019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.77757019
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.2253069202
Short name T352
Test name
Test status
Simulation time 44824816 ps
CPU time 1.54 seconds
Started May 16 02:04:36 PM PDT 24
Finished May 16 02:04:41 PM PDT 24
Peak memory 219392 kb
Host smart-b196b6fa-08e7-4ef4-9d50-a4208b630588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253069202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2253069202
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.642532208
Short name T418
Test name
Test status
Simulation time 72075943 ps
CPU time 1.04 seconds
Started May 16 02:04:40 PM PDT 24
Finished May 16 02:04:45 PM PDT 24
Peak memory 216756 kb
Host smart-bc175f2c-8645-458e-b9f1-0517d6b128a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642532208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.642532208
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.3165027383
Short name T367
Test name
Test status
Simulation time 31373610 ps
CPU time 1.31 seconds
Started May 16 02:04:38 PM PDT 24
Finished May 16 02:04:42 PM PDT 24
Peak memory 217900 kb
Host smart-e5eb30c9-f390-4b2f-9fe1-4c32f86f5517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165027383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3165027383
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.2398583915
Short name T730
Test name
Test status
Simulation time 33702266 ps
CPU time 1.3 seconds
Started May 16 02:04:34 PM PDT 24
Finished May 16 02:04:38 PM PDT 24
Peak memory 216584 kb
Host smart-fec4e6b1-96a7-40f8-ab47-1b46244d443d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398583915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2398583915
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.2667510806
Short name T553
Test name
Test status
Simulation time 54821188 ps
CPU time 1.91 seconds
Started May 16 02:04:39 PM PDT 24
Finished May 16 02:04:44 PM PDT 24
Peak memory 217988 kb
Host smart-fee87907-b6e2-4c63-a3b1-3b6f3f8aac58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667510806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2667510806
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.2174604848
Short name T761
Test name
Test status
Simulation time 43000463 ps
CPU time 1.67 seconds
Started May 16 02:04:42 PM PDT 24
Finished May 16 02:04:46 PM PDT 24
Peak memory 217880 kb
Host smart-61a6dd3f-3d9f-450c-a1f5-e168f01c6477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174604848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2174604848
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.3505249642
Short name T362
Test name
Test status
Simulation time 78467349 ps
CPU time 1.29 seconds
Started May 16 02:04:36 PM PDT 24
Finished May 16 02:04:40 PM PDT 24
Peak memory 218264 kb
Host smart-ec994e61-7d78-4b78-8c16-ae24bc508f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505249642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3505249642
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3739115058
Short name T493
Test name
Test status
Simulation time 50788548 ps
CPU time 1.63 seconds
Started May 16 02:04:42 PM PDT 24
Finished May 16 02:04:46 PM PDT 24
Peak memory 218768 kb
Host smart-d3f930c3-9cc7-4712-85c8-d59923bcb31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739115058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3739115058
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.691028814
Short name T624
Test name
Test status
Simulation time 23095299 ps
CPU time 1.18 seconds
Started May 16 02:02:10 PM PDT 24
Finished May 16 02:02:14 PM PDT 24
Peak memory 215468 kb
Host smart-eb819b9b-1ed7-476f-a79f-7fe23fa97e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691028814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.691028814
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.3876588692
Short name T392
Test name
Test status
Simulation time 12241505 ps
CPU time 0.91 seconds
Started May 16 02:02:12 PM PDT 24
Finished May 16 02:02:14 PM PDT 24
Peak memory 215808 kb
Host smart-b4e508df-c0e2-432f-9014-742a3de2d99b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876588692 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3876588692
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3806056609
Short name T29
Test name
Test status
Simulation time 81815223 ps
CPU time 1.04 seconds
Started May 16 02:02:07 PM PDT 24
Finished May 16 02:02:11 PM PDT 24
Peak memory 216524 kb
Host smart-261e5f11-01ee-4278-85a2-728e397c93b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806056609 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3806056609
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1222270385
Short name T81
Test name
Test status
Simulation time 24747106 ps
CPU time 1.18 seconds
Started May 16 02:02:08 PM PDT 24
Finished May 16 02:02:12 PM PDT 24
Peak memory 217880 kb
Host smart-8b194d6d-7ef4-43b6-999d-0862587a51f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222270385 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1222270385
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2252115136
Short name T359
Test name
Test status
Simulation time 101741921 ps
CPU time 1.41 seconds
Started May 16 02:02:07 PM PDT 24
Finished May 16 02:02:12 PM PDT 24
Peak memory 218564 kb
Host smart-452ed978-9ad7-48a6-9c0a-b1f75ebbc285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252115136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2252115136
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1863835633
Short name T161
Test name
Test status
Simulation time 57015095 ps
CPU time 0.87 seconds
Started May 16 02:02:08 PM PDT 24
Finished May 16 02:02:12 PM PDT 24
Peak memory 215064 kb
Host smart-291eba43-94a2-4b64-bc80-7e4be48ba588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863835633 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1863835633
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1927419213
Short name T390
Test name
Test status
Simulation time 38201749 ps
CPU time 0.92 seconds
Started May 16 02:02:08 PM PDT 24
Finished May 16 02:02:12 PM PDT 24
Peak memory 214980 kb
Host smart-312c65d7-e8d9-4042-b163-c45dae93d75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927419213 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1927419213
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.648016383
Short name T218
Test name
Test status
Simulation time 249651613 ps
CPU time 5.24 seconds
Started May 16 02:02:09 PM PDT 24
Finished May 16 02:02:17 PM PDT 24
Peak memory 217960 kb
Host smart-d7d49881-a657-450d-9d7d-852a2ac4f587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648016383 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.648016383
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3079193540
Short name T658
Test name
Test status
Simulation time 91987589956 ps
CPU time 952.57 seconds
Started May 16 02:02:07 PM PDT 24
Finished May 16 02:18:02 PM PDT 24
Peak memory 221920 kb
Host smart-8cdf8041-4616-4b18-925f-6274779007e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079193540 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3079193540
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.222372481
Short name T148
Test name
Test status
Simulation time 111910593 ps
CPU time 1.3 seconds
Started May 16 02:04:34 PM PDT 24
Finished May 16 02:04:38 PM PDT 24
Peak memory 218112 kb
Host smart-d7706c2b-fd00-417e-a85a-b89daad5f366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222372481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.222372481
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.3883710520
Short name T580
Test name
Test status
Simulation time 55136089 ps
CPU time 1.19 seconds
Started May 16 02:04:35 PM PDT 24
Finished May 16 02:04:39 PM PDT 24
Peak memory 216748 kb
Host smart-aba767e7-db5c-4953-9216-329c8a481371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883710520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3883710520
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2137481852
Short name T415
Test name
Test status
Simulation time 77549859 ps
CPU time 1.48 seconds
Started May 16 02:04:40 PM PDT 24
Finished May 16 02:04:45 PM PDT 24
Peak memory 218268 kb
Host smart-bc1d31ca-e355-4a1d-9efb-fd7218bc41f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137481852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2137481852
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.1180533129
Short name T824
Test name
Test status
Simulation time 51425357 ps
CPU time 1.49 seconds
Started May 16 02:04:36 PM PDT 24
Finished May 16 02:04:40 PM PDT 24
Peak memory 217936 kb
Host smart-b36e6f07-fafa-421e-82e4-09028cbd9dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180533129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1180533129
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.315251583
Short name T538
Test name
Test status
Simulation time 52696712 ps
CPU time 1.58 seconds
Started May 16 02:04:36 PM PDT 24
Finished May 16 02:04:40 PM PDT 24
Peak memory 217908 kb
Host smart-a5cb72ef-6710-4838-b7f6-18b02974546e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315251583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.315251583
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.347912898
Short name T334
Test name
Test status
Simulation time 82225407 ps
CPU time 1.02 seconds
Started May 16 02:04:38 PM PDT 24
Finished May 16 02:04:43 PM PDT 24
Peak memory 216736 kb
Host smart-d9d3db08-f662-4514-907a-edbda3ba4a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347912898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.347912898
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.728403894
Short name T364
Test name
Test status
Simulation time 51931820 ps
CPU time 1.54 seconds
Started May 16 02:04:35 PM PDT 24
Finished May 16 02:04:39 PM PDT 24
Peak memory 217748 kb
Host smart-703b0df6-9a98-4a40-9dca-ce6e45c82674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728403894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.728403894
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.2062258423
Short name T388
Test name
Test status
Simulation time 30573764 ps
CPU time 1.34 seconds
Started May 16 02:04:40 PM PDT 24
Finished May 16 02:04:44 PM PDT 24
Peak memory 217868 kb
Host smart-f23daa9c-2e42-4779-8ce7-f2ef59b356d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062258423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2062258423
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.2297557036
Short name T308
Test name
Test status
Simulation time 72786793 ps
CPU time 1.3 seconds
Started May 16 02:04:41 PM PDT 24
Finished May 16 02:04:45 PM PDT 24
Peak memory 219160 kb
Host smart-732d94a3-4a9e-41c3-b326-f03496512675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297557036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2297557036
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.4289626638
Short name T486
Test name
Test status
Simulation time 15145671 ps
CPU time 0.93 seconds
Started May 16 02:02:07 PM PDT 24
Finished May 16 02:02:11 PM PDT 24
Peak memory 214528 kb
Host smart-570a9f12-3ad9-416a-a670-7b7cec1ffd86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289626638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.4289626638
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.1830804143
Short name T834
Test name
Test status
Simulation time 18527390 ps
CPU time 0.89 seconds
Started May 16 02:02:07 PM PDT 24
Finished May 16 02:02:11 PM PDT 24
Peak memory 215620 kb
Host smart-9a19c244-1ae9-4ff3-b538-923b2261d388
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830804143 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1830804143
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.2465740640
Short name T75
Test name
Test status
Simulation time 41380059 ps
CPU time 0.81 seconds
Started May 16 02:02:08 PM PDT 24
Finished May 16 02:02:12 PM PDT 24
Peak memory 217744 kb
Host smart-0ec096b7-33ea-4cea-96fd-c1434cbd8eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465740640 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2465740640
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.853016322
Short name T625
Test name
Test status
Simulation time 56158575 ps
CPU time 2.08 seconds
Started May 16 02:02:10 PM PDT 24
Finished May 16 02:02:14 PM PDT 24
Peak memory 219648 kb
Host smart-57f9488d-79d0-4be6-8678-2dcabe0dd440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853016322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.853016322
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3876368388
Short name T551
Test name
Test status
Simulation time 22738600 ps
CPU time 1.13 seconds
Started May 16 02:02:07 PM PDT 24
Finished May 16 02:02:11 PM PDT 24
Peak memory 215232 kb
Host smart-6e7b7acd-d78e-4f29-8cf1-87a1fb98b346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876368388 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3876368388
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.4214332450
Short name T604
Test name
Test status
Simulation time 24151973 ps
CPU time 0.97 seconds
Started May 16 02:02:10 PM PDT 24
Finished May 16 02:02:14 PM PDT 24
Peak memory 214968 kb
Host smart-46782f5f-e55e-46f7-a6b1-538e1ee9fb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214332450 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.4214332450
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1091615057
Short name T793
Test name
Test status
Simulation time 195021022 ps
CPU time 2.56 seconds
Started May 16 02:02:09 PM PDT 24
Finished May 16 02:02:14 PM PDT 24
Peak memory 216612 kb
Host smart-22f821f4-7f5b-496e-adef-89d0e6644c4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091615057 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1091615057
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3753020801
Short name T391
Test name
Test status
Simulation time 23796848546 ps
CPU time 542.23 seconds
Started May 16 02:02:08 PM PDT 24
Finished May 16 02:11:13 PM PDT 24
Peak memory 216920 kb
Host smart-ee1007c3-918a-4d79-aa98-7a7868bf07fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753020801 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3753020801
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.379244834
Short name T358
Test name
Test status
Simulation time 55627177 ps
CPU time 1.34 seconds
Started May 16 02:04:41 PM PDT 24
Finished May 16 02:04:46 PM PDT 24
Peak memory 218096 kb
Host smart-6f397ddf-71d1-4099-8fac-1a5f43f0a205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379244834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.379244834
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.3607335013
Short name T589
Test name
Test status
Simulation time 29852125 ps
CPU time 1.29 seconds
Started May 16 02:04:41 PM PDT 24
Finished May 16 02:04:45 PM PDT 24
Peak memory 216628 kb
Host smart-96b4f948-1de2-46a6-b893-b3ddd69b8b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607335013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3607335013
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.2352535031
Short name T639
Test name
Test status
Simulation time 68332887 ps
CPU time 1.41 seconds
Started May 16 02:04:38 PM PDT 24
Finished May 16 02:04:43 PM PDT 24
Peak memory 218024 kb
Host smart-1b4630fa-e1ee-41f3-83aa-7a59994a3b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352535031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2352535031
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.476591098
Short name T525
Test name
Test status
Simulation time 37250265 ps
CPU time 1.53 seconds
Started May 16 02:04:36 PM PDT 24
Finished May 16 02:04:41 PM PDT 24
Peak memory 219268 kb
Host smart-764dbd01-3558-4202-8dc8-4fe9da9d2db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476591098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.476591098
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.681469612
Short name T407
Test name
Test status
Simulation time 59236431 ps
CPU time 1.09 seconds
Started May 16 02:04:41 PM PDT 24
Finished May 16 02:04:45 PM PDT 24
Peak memory 216480 kb
Host smart-a2191c56-39fe-4d6f-a1d2-3e999de4b370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681469612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.681469612
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.2200433387
Short name T821
Test name
Test status
Simulation time 77854192 ps
CPU time 1.18 seconds
Started May 16 02:04:35 PM PDT 24
Finished May 16 02:04:39 PM PDT 24
Peak memory 218320 kb
Host smart-e7d27516-5ad2-4142-a96b-61257d5c91a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200433387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2200433387
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.4144934307
Short name T726
Test name
Test status
Simulation time 52808656 ps
CPU time 1.78 seconds
Started May 16 02:04:40 PM PDT 24
Finished May 16 02:04:45 PM PDT 24
Peak memory 216856 kb
Host smart-a4e3202a-687a-4c6d-bc1e-bab35873382f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144934307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.4144934307
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.386855737
Short name T815
Test name
Test status
Simulation time 88721056 ps
CPU time 1.19 seconds
Started May 16 02:02:18 PM PDT 24
Finished May 16 02:02:21 PM PDT 24
Peak memory 215348 kb
Host smart-21471a3a-4dee-48cd-8186-1baf9cbdcd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386855737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.386855737
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2993645344
Short name T723
Test name
Test status
Simulation time 36567692 ps
CPU time 1 seconds
Started May 16 02:02:23 PM PDT 24
Finished May 16 02:02:26 PM PDT 24
Peak memory 214880 kb
Host smart-afea1e47-fef8-4441-a637-5d31a1031b16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993645344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2993645344
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.628363700
Short name T33
Test name
Test status
Simulation time 57368329 ps
CPU time 1.23 seconds
Started May 16 02:02:20 PM PDT 24
Finished May 16 02:02:24 PM PDT 24
Peak memory 218912 kb
Host smart-879a3b0f-3da5-4eae-8925-132c4793d8d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628363700 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.628363700
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1553758071
Short name T440
Test name
Test status
Simulation time 25996469 ps
CPU time 1.13 seconds
Started May 16 02:02:20 PM PDT 24
Finished May 16 02:02:23 PM PDT 24
Peak memory 220252 kb
Host smart-ad945cc5-1611-4b6d-ad9e-eb958555fc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553758071 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1553758071
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.4151652620
Short name T500
Test name
Test status
Simulation time 77920355 ps
CPU time 2.07 seconds
Started May 16 02:02:07 PM PDT 24
Finished May 16 02:02:12 PM PDT 24
Peak memory 218060 kb
Host smart-a163ffc2-0868-49c0-9055-2bede796e34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151652620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.4151652620
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1977793040
Short name T836
Test name
Test status
Simulation time 36844444 ps
CPU time 0.9 seconds
Started May 16 02:02:19 PM PDT 24
Finished May 16 02:02:22 PM PDT 24
Peak memory 214920 kb
Host smart-99031c68-c1a5-4008-b75c-9af40fc5905e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977793040 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1977793040
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2246128124
Short name T768
Test name
Test status
Simulation time 76133467 ps
CPU time 0.95 seconds
Started May 16 02:02:10 PM PDT 24
Finished May 16 02:02:14 PM PDT 24
Peak memory 206792 kb
Host smart-29e08045-33be-416e-9e4a-f3d8f8496565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246128124 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2246128124
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.558862784
Short name T501
Test name
Test status
Simulation time 443085663 ps
CPU time 2.11 seconds
Started May 16 02:02:11 PM PDT 24
Finished May 16 02:02:15 PM PDT 24
Peak memory 216560 kb
Host smart-332c57a3-e743-4924-9b97-49ec6b676fd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558862784 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.558862784
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1564684034
Short name T436
Test name
Test status
Simulation time 62811876021 ps
CPU time 1684.82 seconds
Started May 16 02:02:20 PM PDT 24
Finished May 16 02:30:28 PM PDT 24
Peak memory 225016 kb
Host smart-a2edeba9-d012-4e7f-9443-57512a3927c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564684034 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1564684034
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.edn_genbits.1527748118
Short name T597
Test name
Test status
Simulation time 26841377 ps
CPU time 1.18 seconds
Started May 16 02:04:40 PM PDT 24
Finished May 16 02:04:44 PM PDT 24
Peak memory 216916 kb
Host smart-de7ddb12-0a18-4d0a-b7e9-811bf840dcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527748118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1527748118
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1197910462
Short name T400
Test name
Test status
Simulation time 31450455 ps
CPU time 1.31 seconds
Started May 16 02:04:38 PM PDT 24
Finished May 16 02:04:42 PM PDT 24
Peak memory 216752 kb
Host smart-185f3866-7049-467e-b3fe-7d5c689d1862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197910462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1197910462
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.636314031
Short name T144
Test name
Test status
Simulation time 47257556 ps
CPU time 1.44 seconds
Started May 16 02:04:39 PM PDT 24
Finished May 16 02:04:43 PM PDT 24
Peak memory 219348 kb
Host smart-186386c5-e762-44f2-bed1-ddde2f7a809a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636314031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.636314031
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.3224813986
Short name T328
Test name
Test status
Simulation time 34804698 ps
CPU time 1.36 seconds
Started May 16 02:04:38 PM PDT 24
Finished May 16 02:04:42 PM PDT 24
Peak memory 216672 kb
Host smart-20f118fd-a4c0-4f65-b93f-4598b12727db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224813986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3224813986
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.2751746921
Short name T445
Test name
Test status
Simulation time 35926028 ps
CPU time 1.55 seconds
Started May 16 02:04:39 PM PDT 24
Finished May 16 02:04:43 PM PDT 24
Peak memory 217916 kb
Host smart-5a3231e4-6065-49d9-bd36-0408fb9f8ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751746921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2751746921
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2704269547
Short name T622
Test name
Test status
Simulation time 330105544 ps
CPU time 3.29 seconds
Started May 16 02:04:46 PM PDT 24
Finished May 16 02:04:52 PM PDT 24
Peak memory 215088 kb
Host smart-c9e1679c-12f7-4a11-a41a-d90f7a08c663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704269547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2704269547
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.3966154600
Short name T652
Test name
Test status
Simulation time 58427723 ps
CPU time 1.77 seconds
Started May 16 02:04:46 PM PDT 24
Finished May 16 02:04:50 PM PDT 24
Peak memory 217916 kb
Host smart-38a634db-ef34-4272-84c2-9de50bb61cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966154600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3966154600
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.655649977
Short name T686
Test name
Test status
Simulation time 42470708 ps
CPU time 1.18 seconds
Started May 16 02:02:31 PM PDT 24
Finished May 16 02:02:37 PM PDT 24
Peak memory 215308 kb
Host smart-75e0ca77-ee30-4396-964e-f8a6ebe70694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655649977 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.655649977
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3756481371
Short name T786
Test name
Test status
Simulation time 25788165 ps
CPU time 0.88 seconds
Started May 16 02:02:21 PM PDT 24
Finished May 16 02:02:25 PM PDT 24
Peak memory 206224 kb
Host smart-7cfa4bf5-1068-4678-a3cb-7565acadff93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756481371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3756481371
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.3730231470
Short name T61
Test name
Test status
Simulation time 40465208 ps
CPU time 0.89 seconds
Started May 16 02:02:18 PM PDT 24
Finished May 16 02:02:19 PM PDT 24
Peak memory 215196 kb
Host smart-9bcc6949-027c-478a-bfc2-5a8319a6e660
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730231470 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3730231470
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.4144477039
Short name T10
Test name
Test status
Simulation time 60798484 ps
CPU time 1.26 seconds
Started May 16 02:02:20 PM PDT 24
Finished May 16 02:02:24 PM PDT 24
Peak memory 216612 kb
Host smart-7738aed5-4163-465f-8a03-d35769214e12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144477039 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.4144477039
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3639791051
Short name T51
Test name
Test status
Simulation time 53962780 ps
CPU time 1.37 seconds
Started May 16 02:02:21 PM PDT 24
Finished May 16 02:02:25 PM PDT 24
Peak memory 225104 kb
Host smart-67a5b2d4-4dca-4a6a-8324-9833544e5dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639791051 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3639791051
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3380182865
Short name T387
Test name
Test status
Simulation time 102554492 ps
CPU time 1.2 seconds
Started May 16 02:02:23 PM PDT 24
Finished May 16 02:02:26 PM PDT 24
Peak memory 219084 kb
Host smart-1a681209-e1c8-45ac-85a0-ec18207902a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380182865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3380182865
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1468912733
Short name T483
Test name
Test status
Simulation time 63590538 ps
CPU time 0.99 seconds
Started May 16 02:02:20 PM PDT 24
Finished May 16 02:02:23 PM PDT 24
Peak memory 223444 kb
Host smart-83a0fbfb-acdd-4b74-95ac-0ea2bd838109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468912733 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1468912733
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.900567262
Short name T346
Test name
Test status
Simulation time 18905906 ps
CPU time 1.05 seconds
Started May 16 02:02:19 PM PDT 24
Finished May 16 02:02:23 PM PDT 24
Peak memory 215032 kb
Host smart-e8185870-46bf-43d3-b208-e94a385baa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900567262 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.900567262
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.409854755
Short name T465
Test name
Test status
Simulation time 291765938 ps
CPU time 3.56 seconds
Started May 16 02:02:22 PM PDT 24
Finished May 16 02:02:28 PM PDT 24
Peak memory 216644 kb
Host smart-8c265a11-47c7-4970-bee2-5e4eb69b1f91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409854755 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.409854755
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.696633515
Short name T213
Test name
Test status
Simulation time 25993845347 ps
CPU time 574.2 seconds
Started May 16 02:02:32 PM PDT 24
Finished May 16 02:12:11 PM PDT 24
Peak memory 217316 kb
Host smart-2b9cd866-24ee-434a-bc5b-060831c173d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696633515 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.696633515
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.2078690479
Short name T593
Test name
Test status
Simulation time 146833423 ps
CPU time 1.35 seconds
Started May 16 02:04:46 PM PDT 24
Finished May 16 02:04:50 PM PDT 24
Peak memory 216720 kb
Host smart-2f4ba5f2-6da1-4184-ab8c-371319ce6be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078690479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2078690479
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.4178596368
Short name T566
Test name
Test status
Simulation time 96045675 ps
CPU time 1.19 seconds
Started May 16 02:04:46 PM PDT 24
Finished May 16 02:04:49 PM PDT 24
Peak memory 218904 kb
Host smart-6f81f667-2a92-4716-8b81-c0f209a0af9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178596368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.4178596368
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.614699700
Short name T555
Test name
Test status
Simulation time 69462597 ps
CPU time 1.25 seconds
Started May 16 02:04:46 PM PDT 24
Finished May 16 02:04:49 PM PDT 24
Peak memory 218156 kb
Host smart-fb568b74-b9da-45e1-bda6-6099db05cc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614699700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.614699700
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.726412509
Short name T350
Test name
Test status
Simulation time 141847446 ps
CPU time 2.73 seconds
Started May 16 02:04:46 PM PDT 24
Finished May 16 02:04:51 PM PDT 24
Peak memory 217916 kb
Host smart-215f5602-12d7-4dc8-8c1c-299a79755cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726412509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.726412509
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.2034695576
Short name T557
Test name
Test status
Simulation time 87434051 ps
CPU time 1.14 seconds
Started May 16 02:04:51 PM PDT 24
Finished May 16 02:04:53 PM PDT 24
Peak memory 216896 kb
Host smart-67c08f39-f4f1-4419-ae93-4eba723cbd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034695576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2034695576
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.1465184854
Short name T698
Test name
Test status
Simulation time 92862043 ps
CPU time 1.38 seconds
Started May 16 02:04:48 PM PDT 24
Finished May 16 02:04:51 PM PDT 24
Peak memory 217852 kb
Host smart-f89167a7-1aea-4ad5-b474-bc26e0ee1269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465184854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1465184854
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.2985404088
Short name T770
Test name
Test status
Simulation time 49367989 ps
CPU time 1.48 seconds
Started May 16 02:04:48 PM PDT 24
Finished May 16 02:04:52 PM PDT 24
Peak memory 217000 kb
Host smart-2282b9ff-1bb7-460f-95e5-7f56a5d77036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985404088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2985404088
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.3989104556
Short name T830
Test name
Test status
Simulation time 149195142 ps
CPU time 3.31 seconds
Started May 16 02:04:46 PM PDT 24
Finished May 16 02:04:52 PM PDT 24
Peak memory 217952 kb
Host smart-9744d384-d53d-4a70-84d4-e4d4dabc3076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989104556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3989104556
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.1216500060
Short name T470
Test name
Test status
Simulation time 102275503 ps
CPU time 1.34 seconds
Started May 16 02:04:46 PM PDT 24
Finished May 16 02:04:50 PM PDT 24
Peak memory 216804 kb
Host smart-751490d4-7354-4b63-b087-18869c94d0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216500060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1216500060
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1070380434
Short name T431
Test name
Test status
Simulation time 51128930 ps
CPU time 1.31 seconds
Started May 16 02:04:47 PM PDT 24
Finished May 16 02:04:51 PM PDT 24
Peak memory 218008 kb
Host smart-446651af-07d7-4b5e-8924-6c7afd444abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070380434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1070380434
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3368722409
Short name T169
Test name
Test status
Simulation time 26474258 ps
CPU time 1.23 seconds
Started May 16 02:02:32 PM PDT 24
Finished May 16 02:02:38 PM PDT 24
Peak memory 215304 kb
Host smart-63371078-ff77-48fe-9360-4769900c3e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368722409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3368722409
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1320455164
Short name T532
Test name
Test status
Simulation time 14209816 ps
CPU time 0.9 seconds
Started May 16 02:02:19 PM PDT 24
Finished May 16 02:02:21 PM PDT 24
Peak memory 206288 kb
Host smart-3f84857d-6d27-4659-bf11-a861d98d0271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320455164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1320455164
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3677074974
Short name T79
Test name
Test status
Simulation time 13687991 ps
CPU time 0.91 seconds
Started May 16 02:02:20 PM PDT 24
Finished May 16 02:02:23 PM PDT 24
Peak memory 216192 kb
Host smart-5760a5b1-492a-43d5-a52b-f3ba2faed056
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677074974 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3677074974
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3557439852
Short name T47
Test name
Test status
Simulation time 114265207 ps
CPU time 1.07 seconds
Started May 16 02:02:18 PM PDT 24
Finished May 16 02:02:20 PM PDT 24
Peak memory 217900 kb
Host smart-797ab7d0-a13d-4b66-97c1-36215cd4af4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557439852 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3557439852
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.3066887987
Short name T411
Test name
Test status
Simulation time 19048693 ps
CPU time 1.08 seconds
Started May 16 02:02:21 PM PDT 24
Finished May 16 02:02:25 PM PDT 24
Peak memory 218280 kb
Host smart-48b625a8-58db-45b5-811a-5e4368996d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066887987 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3066887987
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1020203881
Short name T763
Test name
Test status
Simulation time 55472045 ps
CPU time 1.36 seconds
Started May 16 02:02:18 PM PDT 24
Finished May 16 02:02:21 PM PDT 24
Peak memory 218044 kb
Host smart-1e6daa2c-ec2c-4ad5-9b39-0b7d6040f772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020203881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1020203881
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1117206458
Short name T369
Test name
Test status
Simulation time 25162104 ps
CPU time 0.97 seconds
Started May 16 02:02:19 PM PDT 24
Finished May 16 02:02:22 PM PDT 24
Peak memory 215288 kb
Host smart-bfc9c8e8-fe51-43bb-9efc-5e86736ce7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117206458 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1117206458
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.955497879
Short name T450
Test name
Test status
Simulation time 20169219 ps
CPU time 1.04 seconds
Started May 16 02:02:20 PM PDT 24
Finished May 16 02:02:24 PM PDT 24
Peak memory 214948 kb
Host smart-d3b92876-fe7b-42a7-a030-ef2dbd7bfef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955497879 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.955497879
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.35833575
Short name T215
Test name
Test status
Simulation time 387669855 ps
CPU time 2.92 seconds
Started May 16 02:02:32 PM PDT 24
Finished May 16 02:02:40 PM PDT 24
Peak memory 214932 kb
Host smart-d58b0e37-f788-4e44-9249-1dbd8f468ed0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35833575 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.35833575
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1181136188
Short name T841
Test name
Test status
Simulation time 385409672103 ps
CPU time 1050.89 seconds
Started May 16 02:02:32 PM PDT 24
Finished May 16 02:20:07 PM PDT 24
Peak memory 221616 kb
Host smart-84a648bc-c5a4-4177-b2a2-ae267c461894
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181136188 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1181136188
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.576454424
Short name T787
Test name
Test status
Simulation time 74807075 ps
CPU time 2.42 seconds
Started May 16 02:04:44 PM PDT 24
Finished May 16 02:04:48 PM PDT 24
Peak memory 216780 kb
Host smart-fb055ee7-e548-4ece-ae58-51eee9ed9d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576454424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.576454424
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.105636255
Short name T283
Test name
Test status
Simulation time 122598898 ps
CPU time 1.03 seconds
Started May 16 02:04:44 PM PDT 24
Finished May 16 02:04:47 PM PDT 24
Peak memory 216828 kb
Host smart-85468abe-2bcc-4b04-976b-eb0665af7069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105636255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.105636255
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.497764216
Short name T721
Test name
Test status
Simulation time 45361092 ps
CPU time 1.47 seconds
Started May 16 02:04:46 PM PDT 24
Finished May 16 02:04:50 PM PDT 24
Peak memory 218056 kb
Host smart-d989e8a3-174b-48ab-93a4-1f4e4a4aa07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497764216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.497764216
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.2842400965
Short name T383
Test name
Test status
Simulation time 34073527 ps
CPU time 1.39 seconds
Started May 16 02:04:47 PM PDT 24
Finished May 16 02:04:51 PM PDT 24
Peak memory 216708 kb
Host smart-e896ad94-68b8-42d2-a7cb-a07ad03b60d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842400965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2842400965
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.4287156954
Short name T307
Test name
Test status
Simulation time 217614632 ps
CPU time 1.76 seconds
Started May 16 02:04:44 PM PDT 24
Finished May 16 02:04:48 PM PDT 24
Peak memory 218104 kb
Host smart-739dfb40-83e6-4400-a508-ca96bbc4a4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287156954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.4287156954
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.3169926172
Short name T351
Test name
Test status
Simulation time 46889487 ps
CPU time 1.69 seconds
Started May 16 02:04:45 PM PDT 24
Finished May 16 02:04:49 PM PDT 24
Peak memory 217968 kb
Host smart-4b49e86a-e1a0-4faf-9ea8-44d48957dea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169926172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3169926172
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.3920144281
Short name T600
Test name
Test status
Simulation time 67622810 ps
CPU time 1.58 seconds
Started May 16 02:04:46 PM PDT 24
Finished May 16 02:04:51 PM PDT 24
Peak memory 217916 kb
Host smart-3390fd71-5e5e-4f82-8345-fed73c4d2150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920144281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3920144281
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.284328930
Short name T569
Test name
Test status
Simulation time 31554446 ps
CPU time 1.26 seconds
Started May 16 02:04:45 PM PDT 24
Finished May 16 02:04:49 PM PDT 24
Peak memory 216740 kb
Host smart-011c9098-72b7-428c-85d4-430e236ef48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284328930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.284328930
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.3590209842
Short name T474
Test name
Test status
Simulation time 96666920 ps
CPU time 1.49 seconds
Started May 16 02:04:45 PM PDT 24
Finished May 16 02:04:49 PM PDT 24
Peak memory 219608 kb
Host smart-9433ae81-4672-4590-b328-a784615b6806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590209842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3590209842
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.2781397835
Short name T446
Test name
Test status
Simulation time 49888005 ps
CPU time 1.9 seconds
Started May 16 02:04:45 PM PDT 24
Finished May 16 02:04:49 PM PDT 24
Peak memory 217968 kb
Host smart-7906e85c-3705-4271-a24a-e50844c50a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781397835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2781397835
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3016026487
Short name T127
Test name
Test status
Simulation time 28740259 ps
CPU time 1.2 seconds
Started May 16 02:02:18 PM PDT 24
Finished May 16 02:02:20 PM PDT 24
Peak memory 215348 kb
Host smart-98343f12-37c8-4f83-b785-68f6e0480b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016026487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3016026487
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3252859574
Short name T690
Test name
Test status
Simulation time 142236723 ps
CPU time 1.77 seconds
Started May 16 02:02:20 PM PDT 24
Finished May 16 02:02:24 PM PDT 24
Peak memory 206444 kb
Host smart-41f9d2e6-9e94-4e7e-976a-e620180bb3b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252859574 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3252859574
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2949709165
Short name T848
Test name
Test status
Simulation time 22282554 ps
CPU time 0.93 seconds
Started May 16 02:02:32 PM PDT 24
Finished May 16 02:02:38 PM PDT 24
Peak memory 215176 kb
Host smart-dc2a3a33-934a-4ab9-b00f-04927fcce4f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949709165 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2949709165
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1851480137
Short name T39
Test name
Test status
Simulation time 61319781 ps
CPU time 1.19 seconds
Started May 16 02:02:19 PM PDT 24
Finished May 16 02:02:23 PM PDT 24
Peak memory 216464 kb
Host smart-1c9533e7-4284-4dd7-af3c-e6e345749c50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851480137 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1851480137
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_genbits.1466436779
Short name T655
Test name
Test status
Simulation time 49225991 ps
CPU time 1.63 seconds
Started May 16 02:02:31 PM PDT 24
Finished May 16 02:02:38 PM PDT 24
Peak memory 219600 kb
Host smart-601ef923-7d11-4bc0-ae47-db7e531e01e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466436779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1466436779
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3553872863
Short name T760
Test name
Test status
Simulation time 27378409 ps
CPU time 1.08 seconds
Started May 16 02:02:21 PM PDT 24
Finished May 16 02:02:25 PM PDT 24
Peak memory 223528 kb
Host smart-b539522c-1fe6-4f49-aae7-0d6961ed4c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553872863 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3553872863
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1671539282
Short name T629
Test name
Test status
Simulation time 19360797 ps
CPU time 0.98 seconds
Started May 16 02:02:22 PM PDT 24
Finished May 16 02:02:25 PM PDT 24
Peak memory 214952 kb
Host smart-ebcccffb-02e9-45ec-b679-a57dbe7f64dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671539282 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1671539282
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.735130512
Short name T540
Test name
Test status
Simulation time 263860708 ps
CPU time 2.61 seconds
Started May 16 02:02:23 PM PDT 24
Finished May 16 02:02:28 PM PDT 24
Peak memory 216408 kb
Host smart-60eead01-0af8-4658-8eb7-0c5736f543a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735130512 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.735130512
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_genbits.703804398
Short name T804
Test name
Test status
Simulation time 78426459 ps
CPU time 1.9 seconds
Started May 16 02:04:59 PM PDT 24
Finished May 16 02:05:04 PM PDT 24
Peak memory 218016 kb
Host smart-49198e4b-4074-4deb-9344-66c9dab972e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703804398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.703804398
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.4147763478
Short name T503
Test name
Test status
Simulation time 78701158 ps
CPU time 1.4 seconds
Started May 16 02:04:59 PM PDT 24
Finished May 16 02:05:03 PM PDT 24
Peak memory 218300 kb
Host smart-26ebf554-88f5-4d25-a50a-4cf96b6586ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147763478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.4147763478
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.733289984
Short name T285
Test name
Test status
Simulation time 128446401 ps
CPU time 1.3 seconds
Started May 16 02:04:58 PM PDT 24
Finished May 16 02:05:01 PM PDT 24
Peak memory 218164 kb
Host smart-21aaf1b8-4cbb-4989-9c2e-b0f94145f687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733289984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.733289984
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.4082417348
Short name T412
Test name
Test status
Simulation time 76158369 ps
CPU time 1.42 seconds
Started May 16 02:04:59 PM PDT 24
Finished May 16 02:05:03 PM PDT 24
Peak memory 217656 kb
Host smart-4c0e2728-eb61-4481-a42c-adfb78af54a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082417348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.4082417348
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.2449303305
Short name T568
Test name
Test status
Simulation time 41833107 ps
CPU time 1.56 seconds
Started May 16 02:04:58 PM PDT 24
Finished May 16 02:05:01 PM PDT 24
Peak memory 216916 kb
Host smart-0e2c3289-3960-4702-9dfb-619ff7bd3f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449303305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2449303305
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.2271127948
Short name T544
Test name
Test status
Simulation time 173423354 ps
CPU time 2.6 seconds
Started May 16 02:04:57 PM PDT 24
Finished May 16 02:05:01 PM PDT 24
Peak memory 218504 kb
Host smart-8bfbecc6-ffb9-453e-a5e2-5030fb176768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271127948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2271127948
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.2176844681
Short name T733
Test name
Test status
Simulation time 56888765 ps
CPU time 1.16 seconds
Started May 16 02:04:57 PM PDT 24
Finished May 16 02:05:00 PM PDT 24
Peak memory 216516 kb
Host smart-7adcafe1-abf9-4535-b2a7-6bc342ff47bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176844681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2176844681
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.464532317
Short name T561
Test name
Test status
Simulation time 38889321 ps
CPU time 1.44 seconds
Started May 16 02:04:59 PM PDT 24
Finished May 16 02:05:03 PM PDT 24
Peak memory 219156 kb
Host smart-74d2a0b4-f1b9-48d7-a0d5-d30212006256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464532317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.464532317
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.2891447645
Short name T662
Test name
Test status
Simulation time 52190078 ps
CPU time 1.19 seconds
Started May 16 02:05:19 PM PDT 24
Finished May 16 02:05:23 PM PDT 24
Peak memory 216680 kb
Host smart-8a9f9d32-4463-4c71-aca0-099a4f77c7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891447645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2891447645
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2155234248
Short name T704
Test name
Test status
Simulation time 83841089 ps
CPU time 1.3 seconds
Started May 16 02:02:29 PM PDT 24
Finished May 16 02:02:32 PM PDT 24
Peak memory 215348 kb
Host smart-f9338d54-856a-44f6-b316-34b74727e045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155234248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2155234248
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2420930704
Short name T416
Test name
Test status
Simulation time 63320335 ps
CPU time 1.04 seconds
Started May 16 02:02:31 PM PDT 24
Finished May 16 02:02:37 PM PDT 24
Peak memory 214440 kb
Host smart-d9aa5be7-0442-4afb-9421-7380daa5d35a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420930704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2420930704
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3010906338
Short name T84
Test name
Test status
Simulation time 31302777 ps
CPU time 0.82 seconds
Started May 16 02:02:30 PM PDT 24
Finished May 16 02:02:34 PM PDT 24
Peak memory 216000 kb
Host smart-944649a4-d681-41ae-ae13-07705d4abf7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010906338 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3010906338
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2901361359
Short name T175
Test name
Test status
Simulation time 41180080 ps
CPU time 1.18 seconds
Started May 16 02:02:28 PM PDT 24
Finished May 16 02:02:31 PM PDT 24
Peak memory 218100 kb
Host smart-481f3e38-d705-448b-887a-ea5066d97555
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901361359 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2901361359
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.2831354422
Short name T91
Test name
Test status
Simulation time 23343912 ps
CPU time 0.92 seconds
Started May 16 02:02:29 PM PDT 24
Finished May 16 02:02:34 PM PDT 24
Peak memory 217912 kb
Host smart-adcc474a-e956-4ee1-a4d7-2ab3835031e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831354422 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2831354422
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_intr.63776810
Short name T160
Test name
Test status
Simulation time 27891970 ps
CPU time 0.95 seconds
Started May 16 02:02:31 PM PDT 24
Finished May 16 02:02:36 PM PDT 24
Peak memory 215188 kb
Host smart-98d76b30-f1fc-43b6-b909-665e9e19e0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63776810 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.63776810
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1329395585
Short name T531
Test name
Test status
Simulation time 53206736 ps
CPU time 0.89 seconds
Started May 16 02:02:23 PM PDT 24
Finished May 16 02:02:26 PM PDT 24
Peak memory 214976 kb
Host smart-f6014b9c-8c55-40a2-ab75-7af5ac4844d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329395585 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1329395585
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.390257026
Short name T579
Test name
Test status
Simulation time 84125466 ps
CPU time 1.46 seconds
Started May 16 02:02:32 PM PDT 24
Finished May 16 02:02:38 PM PDT 24
Peak memory 214960 kb
Host smart-e9606705-74a9-46e2-8694-4147d1540ffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390257026 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.390257026
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.366587669
Short name T201
Test name
Test status
Simulation time 31444905270 ps
CPU time 359.3 seconds
Started May 16 02:02:21 PM PDT 24
Finished May 16 02:08:23 PM PDT 24
Peak memory 217504 kb
Host smart-f3e4acd1-e17a-4430-b2b1-db829d68f291
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366587669 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.366587669
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.1765180253
Short name T123
Test name
Test status
Simulation time 48127167 ps
CPU time 1.83 seconds
Started May 16 02:04:58 PM PDT 24
Finished May 16 02:05:01 PM PDT 24
Peak memory 218072 kb
Host smart-a0196f8f-be45-4cfe-b3f0-e2eddc9bf9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765180253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1765180253
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.4115285420
Short name T795
Test name
Test status
Simulation time 79542417 ps
CPU time 1.1 seconds
Started May 16 02:05:00 PM PDT 24
Finished May 16 02:05:04 PM PDT 24
Peak memory 216772 kb
Host smart-ac7c41ec-7f62-4896-bd29-05961e9a4af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115285420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.4115285420
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2443491651
Short name T636
Test name
Test status
Simulation time 24297874 ps
CPU time 1.19 seconds
Started May 16 02:04:58 PM PDT 24
Finished May 16 02:05:00 PM PDT 24
Peak memory 218120 kb
Host smart-9cb9fe9e-97f2-43d7-91f9-1e0c6cf9b8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443491651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2443491651
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.3298954140
Short name T831
Test name
Test status
Simulation time 41999900 ps
CPU time 1.82 seconds
Started May 16 02:04:59 PM PDT 24
Finished May 16 02:05:04 PM PDT 24
Peak memory 218016 kb
Host smart-c7040ccd-a791-4dd5-9eb9-3367676d7473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298954140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3298954140
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.778503873
Short name T171
Test name
Test status
Simulation time 21826670 ps
CPU time 1.22 seconds
Started May 16 02:04:59 PM PDT 24
Finished May 16 02:05:03 PM PDT 24
Peak memory 219168 kb
Host smart-7dc1bc89-dec8-4f96-a4fd-f458f8a9dec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778503873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.778503873
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.1822866478
Short name T510
Test name
Test status
Simulation time 23132261 ps
CPU time 1.2 seconds
Started May 16 02:05:03 PM PDT 24
Finished May 16 02:05:06 PM PDT 24
Peak memory 217672 kb
Host smart-64e6e7c8-2ceb-4e47-843c-e4e5dc6f3b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822866478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1822866478
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.3542760760
Short name T471
Test name
Test status
Simulation time 102237539 ps
CPU time 1.06 seconds
Started May 16 02:04:59 PM PDT 24
Finished May 16 02:05:03 PM PDT 24
Peak memory 216856 kb
Host smart-8592da10-f227-4480-9ff4-bde54ff7ae17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542760760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3542760760
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.451344197
Short name T149
Test name
Test status
Simulation time 54482811 ps
CPU time 2.33 seconds
Started May 16 02:04:59 PM PDT 24
Finished May 16 02:05:04 PM PDT 24
Peak memory 218056 kb
Host smart-9ff83a5c-99d3-476d-a0ca-ec95bf61f5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451344197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.451344197
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1957338834
Short name T665
Test name
Test status
Simulation time 58685676 ps
CPU time 1.81 seconds
Started May 16 02:05:00 PM PDT 24
Finished May 16 02:05:04 PM PDT 24
Peak memory 216688 kb
Host smart-8ca10e8a-5283-4a5a-ad34-57dc09666988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957338834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1957338834
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.4211594921
Short name T264
Test name
Test status
Simulation time 222597079 ps
CPU time 1.32 seconds
Started May 16 02:02:31 PM PDT 24
Finished May 16 02:02:36 PM PDT 24
Peak memory 215344 kb
Host smart-a9276fa8-f3e6-4d91-9288-578a926d7a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211594921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.4211594921
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3570083717
Short name T331
Test name
Test status
Simulation time 19645935 ps
CPU time 0.96 seconds
Started May 16 02:02:32 PM PDT 24
Finished May 16 02:02:37 PM PDT 24
Peak memory 214476 kb
Host smart-d744de06-cf84-4a94-be37-20595ac783ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570083717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3570083717
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.169790816
Short name T87
Test name
Test status
Simulation time 30345212 ps
CPU time 0.85 seconds
Started May 16 02:02:29 PM PDT 24
Finished May 16 02:02:33 PM PDT 24
Peak memory 215980 kb
Host smart-fd90d2ee-aa74-4300-be1a-5ae63336300f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169790816 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.169790816
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3542693809
Short name T252
Test name
Test status
Simulation time 26219307 ps
CPU time 1.1 seconds
Started May 16 02:02:32 PM PDT 24
Finished May 16 02:02:38 PM PDT 24
Peak memory 217952 kb
Host smart-092d67bd-6820-4731-a873-3dd3e159f6e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542693809 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3542693809
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_genbits.483011281
Short name T133
Test name
Test status
Simulation time 59495902 ps
CPU time 1.22 seconds
Started May 16 02:02:31 PM PDT 24
Finished May 16 02:02:36 PM PDT 24
Peak memory 218336 kb
Host smart-3f4f3f40-36be-4528-a6e5-e0b8e34793b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483011281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.483011281
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1598860125
Short name T382
Test name
Test status
Simulation time 72367570 ps
CPU time 1.01 seconds
Started May 16 02:02:33 PM PDT 24
Finished May 16 02:02:38 PM PDT 24
Peak memory 223428 kb
Host smart-7486926a-72db-4c39-aa6c-99b575cccec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598860125 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1598860125
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1115742345
Short name T812
Test name
Test status
Simulation time 22334836 ps
CPU time 0.93 seconds
Started May 16 02:02:33 PM PDT 24
Finished May 16 02:02:38 PM PDT 24
Peak memory 215000 kb
Host smart-34839424-b139-446b-a61b-e51ee5a232f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115742345 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1115742345
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2954093490
Short name T517
Test name
Test status
Simulation time 388733902 ps
CPU time 4.17 seconds
Started May 16 02:02:31 PM PDT 24
Finished May 16 02:02:40 PM PDT 24
Peak memory 214988 kb
Host smart-4538b2dd-d26f-4057-a235-b155fdc21e68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954093490 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2954093490
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.47631988
Short name T311
Test name
Test status
Simulation time 95372219004 ps
CPU time 681.08 seconds
Started May 16 02:02:28 PM PDT 24
Finished May 16 02:13:51 PM PDT 24
Peak memory 220488 kb
Host smart-551c397c-47ae-474e-b497-79435a266ac5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47631988 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.47631988
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.2477525909
Short name T811
Test name
Test status
Simulation time 66186648 ps
CPU time 2.21 seconds
Started May 16 02:04:58 PM PDT 24
Finished May 16 02:05:03 PM PDT 24
Peak memory 219364 kb
Host smart-fb49676d-e9db-48fc-8184-d451f56220ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477525909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2477525909
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.1502616056
Short name T455
Test name
Test status
Simulation time 61203219 ps
CPU time 1.5 seconds
Started May 16 02:04:57 PM PDT 24
Finished May 16 02:04:59 PM PDT 24
Peak memory 217848 kb
Host smart-23b777cb-0341-4bd2-bc3b-636cdd7e0891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502616056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1502616056
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.1086588109
Short name T663
Test name
Test status
Simulation time 31000240 ps
CPU time 1.28 seconds
Started May 16 02:04:57 PM PDT 24
Finished May 16 02:04:59 PM PDT 24
Peak memory 217076 kb
Host smart-88ca8a2d-f5d1-4a3e-bd9a-75007dad05a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086588109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1086588109
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.4065092893
Short name T427
Test name
Test status
Simulation time 31813630 ps
CPU time 1.36 seconds
Started May 16 02:04:57 PM PDT 24
Finished May 16 02:05:00 PM PDT 24
Peak memory 217856 kb
Host smart-3503fe34-1f31-41d9-8cc8-ec751c207234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065092893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.4065092893
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.1835765282
Short name T379
Test name
Test status
Simulation time 97399607 ps
CPU time 1.1 seconds
Started May 16 02:05:04 PM PDT 24
Finished May 16 02:05:07 PM PDT 24
Peak memory 219496 kb
Host smart-1b88164b-0260-4f0b-b781-9b67b85dbe10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835765282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1835765282
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.2466684727
Short name T809
Test name
Test status
Simulation time 65513198 ps
CPU time 0.96 seconds
Started May 16 02:05:04 PM PDT 24
Finished May 16 02:05:07 PM PDT 24
Peak memory 216880 kb
Host smart-e77348c3-e35a-499d-ae2c-278ee866c52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466684727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2466684727
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.324669925
Short name T644
Test name
Test status
Simulation time 47333743 ps
CPU time 1 seconds
Started May 16 02:04:58 PM PDT 24
Finished May 16 02:05:01 PM PDT 24
Peak memory 216604 kb
Host smart-68c70525-1ba2-439f-9b35-03df93ef8716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324669925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.324669925
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.2983811053
Short name T649
Test name
Test status
Simulation time 93620654 ps
CPU time 1.51 seconds
Started May 16 02:04:58 PM PDT 24
Finished May 16 02:05:01 PM PDT 24
Peak memory 217872 kb
Host smart-52ba8899-47fb-4a88-97ff-fd75a0370026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983811053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2983811053
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.2737444336
Short name T409
Test name
Test status
Simulation time 83952192 ps
CPU time 1.33 seconds
Started May 16 02:05:00 PM PDT 24
Finished May 16 02:05:04 PM PDT 24
Peak memory 218128 kb
Host smart-5b4aa8ca-648b-47d6-ab2e-454e2903b100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737444336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2737444336
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.377985721
Short name T758
Test name
Test status
Simulation time 79000569 ps
CPU time 1.53 seconds
Started May 16 02:05:00 PM PDT 24
Finished May 16 02:05:05 PM PDT 24
Peak memory 218240 kb
Host smart-9c2af336-fe43-4a65-8a05-01dfd984fd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377985721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.377985721
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2527020835
Short name T268
Test name
Test status
Simulation time 69507284 ps
CPU time 1.12 seconds
Started May 16 02:02:28 PM PDT 24
Finished May 16 02:02:31 PM PDT 24
Peak memory 215336 kb
Host smart-9ec4ca10-8b16-4b4f-af75-3705b1b1e762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527020835 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2527020835
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1221800900
Short name T587
Test name
Test status
Simulation time 38186285 ps
CPU time 0.88 seconds
Started May 16 02:02:29 PM PDT 24
Finished May 16 02:02:33 PM PDT 24
Peak memory 206036 kb
Host smart-9b397060-cde8-4807-92f4-ad3a54956452
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221800900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1221800900
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3356947811
Short name T803
Test name
Test status
Simulation time 28448194 ps
CPU time 1.05 seconds
Started May 16 02:02:29 PM PDT 24
Finished May 16 02:02:33 PM PDT 24
Peak memory 217884 kb
Host smart-e52921e3-e340-49f6-a502-07dc95fb5862
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356947811 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3356947811
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2457372856
Short name T63
Test name
Test status
Simulation time 53217581 ps
CPU time 1.2 seconds
Started May 16 02:02:31 PM PDT 24
Finished May 16 02:02:36 PM PDT 24
Peak memory 224948 kb
Host smart-7b40bcf7-0fe2-455d-acc4-030c848dd832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457372856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2457372856
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3000608650
Short name T782
Test name
Test status
Simulation time 133833791 ps
CPU time 2.98 seconds
Started May 16 02:02:29 PM PDT 24
Finished May 16 02:02:34 PM PDT 24
Peak memory 218720 kb
Host smart-d91a09c5-f649-405c-845a-f81a0b033241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000608650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3000608650
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1626790573
Short name T467
Test name
Test status
Simulation time 31240360 ps
CPU time 0.9 seconds
Started May 16 02:02:29 PM PDT 24
Finished May 16 02:02:32 PM PDT 24
Peak memory 214908 kb
Host smart-f2461e54-a296-4c7c-a738-afb59ea13ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626790573 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1626790573
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.987591252
Short name T376
Test name
Test status
Simulation time 23264528 ps
CPU time 0.96 seconds
Started May 16 02:02:31 PM PDT 24
Finished May 16 02:02:36 PM PDT 24
Peak memory 206684 kb
Host smart-a29a9239-52a7-4200-bcd5-0545766d2cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987591252 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.987591252
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.371670108
Short name T692
Test name
Test status
Simulation time 409842500 ps
CPU time 4.99 seconds
Started May 16 02:02:32 PM PDT 24
Finished May 16 02:02:42 PM PDT 24
Peak memory 216780 kb
Host smart-c2bc3bd1-1208-45f1-8860-377a02758d41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371670108 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.371670108
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1467017386
Short name T476
Test name
Test status
Simulation time 40814357309 ps
CPU time 499.01 seconds
Started May 16 02:02:32 PM PDT 24
Finished May 16 02:10:56 PM PDT 24
Peak memory 218000 kb
Host smart-2c253600-40e8-47df-94df-613f1b568be7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467017386 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1467017386
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.1411955046
Short name T145
Test name
Test status
Simulation time 56016352 ps
CPU time 1.5 seconds
Started May 16 02:04:59 PM PDT 24
Finished May 16 02:05:04 PM PDT 24
Peak memory 218152 kb
Host smart-3aa94fde-d3d0-4c08-b43b-86d5b10753da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411955046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1411955046
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.2269287514
Short name T775
Test name
Test status
Simulation time 63030271 ps
CPU time 1.28 seconds
Started May 16 02:04:59 PM PDT 24
Finished May 16 02:05:03 PM PDT 24
Peak memory 216828 kb
Host smart-6e7fca41-ee9a-4296-ab03-d2d79c2eeee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269287514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2269287514
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.2073015430
Short name T729
Test name
Test status
Simulation time 46039381 ps
CPU time 1.56 seconds
Started May 16 02:04:57 PM PDT 24
Finished May 16 02:05:00 PM PDT 24
Peak memory 214992 kb
Host smart-1897f59c-31f8-4cb8-b152-2f1765a8965f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073015430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2073015430
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3986092265
Short name T150
Test name
Test status
Simulation time 57001609 ps
CPU time 2.23 seconds
Started May 16 02:04:58 PM PDT 24
Finished May 16 02:05:02 PM PDT 24
Peak memory 218244 kb
Host smart-7e1f2a01-57a6-46ad-b0be-d2311df6ba1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986092265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3986092265
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.4212834535
Short name T172
Test name
Test status
Simulation time 158330749 ps
CPU time 2.48 seconds
Started May 16 02:04:57 PM PDT 24
Finished May 16 02:05:00 PM PDT 24
Peak memory 219448 kb
Host smart-aaa6d4e8-845d-47ab-9354-11390c5ae77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212834535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.4212834535
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.1193475932
Short name T295
Test name
Test status
Simulation time 35965035 ps
CPU time 1.37 seconds
Started May 16 02:05:03 PM PDT 24
Finished May 16 02:05:06 PM PDT 24
Peak memory 217912 kb
Host smart-abed7ad2-6e20-4f4a-bcbe-2272693a73a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193475932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1193475932
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.2543934883
Short name T300
Test name
Test status
Simulation time 71368695 ps
CPU time 1.17 seconds
Started May 16 02:04:59 PM PDT 24
Finished May 16 02:05:03 PM PDT 24
Peak memory 216740 kb
Host smart-976dd46e-0619-4554-b65f-4c483b5d5058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543934883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2543934883
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3309999516
Short name T685
Test name
Test status
Simulation time 34087380 ps
CPU time 1.6 seconds
Started May 16 02:05:00 PM PDT 24
Finished May 16 02:05:04 PM PDT 24
Peak memory 218024 kb
Host smart-f6e9169c-2a2e-4d99-9cce-b517b64bc001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309999516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3309999516
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.3573009636
Short name T454
Test name
Test status
Simulation time 29891434 ps
CPU time 1.4 seconds
Started May 16 02:04:59 PM PDT 24
Finished May 16 02:05:04 PM PDT 24
Peak memory 217936 kb
Host smart-3e729e31-5678-4bf0-b8fd-5f37cb40cff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573009636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3573009636
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.232574533
Short name T840
Test name
Test status
Simulation time 51624275 ps
CPU time 1.57 seconds
Started May 16 02:04:59 PM PDT 24
Finished May 16 02:05:03 PM PDT 24
Peak memory 217616 kb
Host smart-530485e3-4d88-4a7a-a420-d06ee70a331e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232574533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.232574533
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.344977777
Short name T73
Test name
Test status
Simulation time 154523627 ps
CPU time 1.21 seconds
Started May 16 02:01:26 PM PDT 24
Finished May 16 02:01:29 PM PDT 24
Peak memory 215368 kb
Host smart-ef775b5a-066a-4bb6-abab-19611de96f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344977777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.344977777
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3599246187
Short name T578
Test name
Test status
Simulation time 26140638 ps
CPU time 0.97 seconds
Started May 16 02:01:24 PM PDT 24
Finished May 16 02:01:27 PM PDT 24
Peak memory 206200 kb
Host smart-43779d70-6911-4a99-b57a-db5d1435e001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599246187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3599246187
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1710531631
Short name T638
Test name
Test status
Simulation time 71294576 ps
CPU time 0.83 seconds
Started May 16 02:01:25 PM PDT 24
Finished May 16 02:01:28 PM PDT 24
Peak memory 216108 kb
Host smart-853cc76a-62e4-4ee9-8ecf-6ef474bb03fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710531631 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1710531631
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2375388379
Short name T48
Test name
Test status
Simulation time 32476387 ps
CPU time 1.27 seconds
Started May 16 02:01:24 PM PDT 24
Finished May 16 02:01:27 PM PDT 24
Peak memory 219248 kb
Host smart-ec3d5774-7086-4b75-8333-75e8218c50ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375388379 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2375388379
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3787153644
Short name T769
Test name
Test status
Simulation time 20238488 ps
CPU time 1.15 seconds
Started May 16 02:01:24 PM PDT 24
Finished May 16 02:01:27 PM PDT 24
Peak memory 219292 kb
Host smart-4d3c0275-7182-4a6f-98f7-322cc0890b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787153644 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3787153644
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_intr.143199342
Short name T485
Test name
Test status
Simulation time 35039724 ps
CPU time 0.87 seconds
Started May 16 02:01:24 PM PDT 24
Finished May 16 02:01:27 PM PDT 24
Peak memory 214740 kb
Host smart-b4a6486b-33fe-4911-889f-fcad905f7556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143199342 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.143199342
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3963195255
Short name T104
Test name
Test status
Simulation time 20530687 ps
CPU time 1.04 seconds
Started May 16 02:01:25 PM PDT 24
Finished May 16 02:01:28 PM PDT 24
Peak memory 206760 kb
Host smart-6180a9b8-6ac4-4030-a078-0f66e6faf2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963195255 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3963195255
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.742814650
Short name T135
Test name
Test status
Simulation time 1830428934 ps
CPU time 7.88 seconds
Started May 16 02:01:25 PM PDT 24
Finished May 16 02:01:35 PM PDT 24
Peak memory 236516 kb
Host smart-c6bd7e7e-f7d6-48f7-b10c-3045e1c1e563
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742814650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.742814650
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1324953995
Short name T798
Test name
Test status
Simulation time 57544424 ps
CPU time 0.91 seconds
Started May 16 02:01:25 PM PDT 24
Finished May 16 02:01:27 PM PDT 24
Peak memory 206756 kb
Host smart-a5fb26c8-e285-41fe-9f36-d0424ae17fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324953995 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1324953995
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1617402769
Short name T247
Test name
Test status
Simulation time 238135721 ps
CPU time 5 seconds
Started May 16 02:01:25 PM PDT 24
Finished May 16 02:01:32 PM PDT 24
Peak memory 216680 kb
Host smart-3a0ee0dc-5079-4369-96ec-4bdcd329c967
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617402769 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1617402769
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3971271994
Short name T209
Test name
Test status
Simulation time 58821733778 ps
CPU time 1336.71 seconds
Started May 16 02:01:32 PM PDT 24
Finished May 16 02:23:50 PM PDT 24
Peak memory 220932 kb
Host smart-dc540e43-5870-4913-9fcc-81b3137de2a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971271994 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3971271994
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert_test.440417949
Short name T381
Test name
Test status
Simulation time 15833277 ps
CPU time 1.01 seconds
Started May 16 02:02:41 PM PDT 24
Finished May 16 02:02:46 PM PDT 24
Peak memory 206244 kb
Host smart-f8d9bc7b-9e51-48f2-a989-fb051f7dd301
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440417949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.440417949
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1684423985
Short name T186
Test name
Test status
Simulation time 67732538 ps
CPU time 0.82 seconds
Started May 16 02:02:30 PM PDT 24
Finished May 16 02:02:35 PM PDT 24
Peak memory 215984 kb
Host smart-df29349c-5dda-435a-a08f-c6e0f808a14f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684423985 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1684423985
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1544550179
Short name T598
Test name
Test status
Simulation time 76685314 ps
CPU time 1.08 seconds
Started May 16 02:02:42 PM PDT 24
Finished May 16 02:02:47 PM PDT 24
Peak memory 216488 kb
Host smart-4ec10148-26f6-4893-b761-549cfb081ba4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544550179 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1544550179
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.3417688753
Short name T785
Test name
Test status
Simulation time 70051238 ps
CPU time 1.2 seconds
Started May 16 02:02:31 PM PDT 24
Finished May 16 02:02:36 PM PDT 24
Peak memory 225016 kb
Host smart-4a11bbbf-0fbd-43f8-bddf-7e1ec9f45c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417688753 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3417688753
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2550850918
Short name T298
Test name
Test status
Simulation time 48227555 ps
CPU time 1.29 seconds
Started May 16 02:02:32 PM PDT 24
Finished May 16 02:02:37 PM PDT 24
Peak memory 217928 kb
Host smart-bb455303-366b-476c-b600-c8133da6c679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550850918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2550850918
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1919255350
Short name T660
Test name
Test status
Simulation time 20920764 ps
CPU time 1.12 seconds
Started May 16 02:02:31 PM PDT 24
Finished May 16 02:02:36 PM PDT 24
Peak memory 215040 kb
Host smart-0714f266-90ae-4b31-a5f7-4eb43780c118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919255350 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1919255350
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2632339952
Short name T434
Test name
Test status
Simulation time 18633684 ps
CPU time 0.91 seconds
Started May 16 02:02:32 PM PDT 24
Finished May 16 02:02:37 PM PDT 24
Peak memory 214972 kb
Host smart-71c515a2-c990-488c-a597-cac317263213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632339952 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2632339952
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.925159644
Short name T452
Test name
Test status
Simulation time 190672221 ps
CPU time 1.75 seconds
Started May 16 02:02:31 PM PDT 24
Finished May 16 02:02:38 PM PDT 24
Peak memory 216536 kb
Host smart-7e41f8d8-95e3-436d-b972-c3949113ad31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925159644 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.925159644
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2456495059
Short name T713
Test name
Test status
Simulation time 84625139327 ps
CPU time 1899.27 seconds
Started May 16 02:02:29 PM PDT 24
Finished May 16 02:34:10 PM PDT 24
Peak memory 225052 kb
Host smart-859b1379-330b-4f57-a26d-7e5fbf155e64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456495059 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2456495059
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2703914852
Short name T122
Test name
Test status
Simulation time 69257932 ps
CPU time 1.52 seconds
Started May 16 02:05:00 PM PDT 24
Finished May 16 02:05:04 PM PDT 24
Peak memory 218148 kb
Host smart-e6424ae9-5fd7-4631-a2fc-8272b05c5af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703914852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2703914852
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3081101340
Short name T482
Test name
Test status
Simulation time 45485328 ps
CPU time 1.22 seconds
Started May 16 02:05:00 PM PDT 24
Finished May 16 02:05:04 PM PDT 24
Peak memory 219352 kb
Host smart-e1eccbd4-e45b-4f94-af6e-c413c3288e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081101340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3081101340
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.4062815016
Short name T548
Test name
Test status
Simulation time 88917891 ps
CPU time 1.27 seconds
Started May 16 02:05:00 PM PDT 24
Finished May 16 02:05:04 PM PDT 24
Peak memory 216604 kb
Host smart-145faca8-f55d-4dc2-9fe9-0ee62e0ee697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062815016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.4062815016
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2785771004
Short name T286
Test name
Test status
Simulation time 70832362 ps
CPU time 1.17 seconds
Started May 16 02:04:58 PM PDT 24
Finished May 16 02:05:02 PM PDT 24
Peak memory 216788 kb
Host smart-a2261d2f-06fe-41c0-8818-5169977bea47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785771004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2785771004
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1147648023
Short name T9
Test name
Test status
Simulation time 100864081 ps
CPU time 1.39 seconds
Started May 16 02:04:59 PM PDT 24
Finished May 16 02:05:03 PM PDT 24
Peak memory 217980 kb
Host smart-d02ac3c5-de09-46d7-9081-0fca5b364b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147648023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1147648023
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1168515129
Short name T248
Test name
Test status
Simulation time 55713959 ps
CPU time 1.47 seconds
Started May 16 02:05:16 PM PDT 24
Finished May 16 02:05:21 PM PDT 24
Peak memory 218124 kb
Host smart-f52fe752-38f9-43dd-b38e-cd9fd259cf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168515129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1168515129
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3709149785
Short name T368
Test name
Test status
Simulation time 105777312 ps
CPU time 1.47 seconds
Started May 16 02:05:09 PM PDT 24
Finished May 16 02:05:11 PM PDT 24
Peak memory 217856 kb
Host smart-5ceec9a9-4d75-4397-8b7a-becf076686b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709149785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3709149785
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2602356964
Short name T349
Test name
Test status
Simulation time 95838182 ps
CPU time 1.33 seconds
Started May 16 02:05:11 PM PDT 24
Finished May 16 02:05:16 PM PDT 24
Peak memory 218156 kb
Host smart-3460921c-8ddd-4125-bc92-f2fb5671ccda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602356964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2602356964
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.391272137
Short name T819
Test name
Test status
Simulation time 32995098 ps
CPU time 1.1 seconds
Started May 16 02:05:11 PM PDT 24
Finished May 16 02:05:15 PM PDT 24
Peak memory 216588 kb
Host smart-a3cc902b-6073-4a70-88c9-d39e0bef47c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391272137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.391272137
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2031318260
Short name T718
Test name
Test status
Simulation time 118559972 ps
CPU time 1.12 seconds
Started May 16 02:05:12 PM PDT 24
Finished May 16 02:05:16 PM PDT 24
Peak memory 219016 kb
Host smart-6bd46aee-fcdf-482b-9ff8-ba3369ca39bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031318260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2031318260
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3997134616
Short name T279
Test name
Test status
Simulation time 23528992 ps
CPU time 1.23 seconds
Started May 16 02:02:38 PM PDT 24
Finished May 16 02:02:43 PM PDT 24
Peak memory 215284 kb
Host smart-52764c3b-ef12-48e5-81dc-0b7703df67c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997134616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3997134616
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.65848835
Short name T140
Test name
Test status
Simulation time 28171916 ps
CPU time 0.76 seconds
Started May 16 02:02:39 PM PDT 24
Finished May 16 02:02:43 PM PDT 24
Peak memory 205608 kb
Host smart-0a370baf-358d-41f8-a6df-a43b1def5a8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65848835 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.65848835
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1698890199
Short name T185
Test name
Test status
Simulation time 12422433 ps
CPU time 0.96 seconds
Started May 16 02:02:34 PM PDT 24
Finished May 16 02:02:40 PM PDT 24
Peak memory 216012 kb
Host smart-4a1a4c8e-dc31-488b-a101-040e56cdcd81
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698890199 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1698890199
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.891186507
Short name T746
Test name
Test status
Simulation time 36673225 ps
CPU time 1.12 seconds
Started May 16 02:02:38 PM PDT 24
Finished May 16 02:02:43 PM PDT 24
Peak memory 216528 kb
Host smart-077f1c62-05f8-4456-a6ef-195af675f0b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891186507 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.891186507
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.761151704
Short name T802
Test name
Test status
Simulation time 30528718 ps
CPU time 0.9 seconds
Started May 16 02:02:44 PM PDT 24
Finished May 16 02:02:47 PM PDT 24
Peak memory 217980 kb
Host smart-b6b07a36-f93d-4a60-a830-1d7e664af590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761151704 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.761151704
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3479678159
Short name T586
Test name
Test status
Simulation time 61358509 ps
CPU time 1.37 seconds
Started May 16 02:02:39 PM PDT 24
Finished May 16 02:02:44 PM PDT 24
Peak memory 216600 kb
Host smart-7903d516-4a21-4c05-a443-78ed36438245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479678159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3479678159
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.95325963
Short name T385
Test name
Test status
Simulation time 21006166 ps
CPU time 1.13 seconds
Started May 16 02:02:39 PM PDT 24
Finished May 16 02:02:43 PM PDT 24
Peak memory 223516 kb
Host smart-f5613121-dc10-440f-ae2d-a2e212a9ae75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95325963 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.95325963
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1451031072
Short name T719
Test name
Test status
Simulation time 25325974 ps
CPU time 0.99 seconds
Started May 16 02:02:38 PM PDT 24
Finished May 16 02:02:43 PM PDT 24
Peak memory 206768 kb
Host smart-30e059e9-d649-480f-b82e-c0945b205418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451031072 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1451031072
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2956986000
Short name T380
Test name
Test status
Simulation time 686895056 ps
CPU time 4.13 seconds
Started May 16 02:02:38 PM PDT 24
Finished May 16 02:02:46 PM PDT 24
Peak memory 216768 kb
Host smart-33255d5f-c893-4ba7-8be0-455de0c67475
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956986000 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2956986000
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.294795150
Short name T732
Test name
Test status
Simulation time 238642645222 ps
CPU time 1044.89 seconds
Started May 16 02:02:39 PM PDT 24
Finished May 16 02:20:07 PM PDT 24
Peak memory 221668 kb
Host smart-b45e0cca-9fc2-48a2-8e47-a10e33fb15ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294795150 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.294795150
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2002023909
Short name T469
Test name
Test status
Simulation time 44384257 ps
CPU time 1.57 seconds
Started May 16 02:05:12 PM PDT 24
Finished May 16 02:05:17 PM PDT 24
Peak memory 219236 kb
Host smart-2895ba6d-0ec3-4a1e-a7f6-c88c744e8c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002023909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2002023909
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2704206883
Short name T344
Test name
Test status
Simulation time 79481876 ps
CPU time 2.74 seconds
Started May 16 02:05:10 PM PDT 24
Finished May 16 02:05:15 PM PDT 24
Peak memory 219516 kb
Host smart-a06a5140-622c-4701-8d5f-ca396ec903dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704206883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2704206883
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3021429092
Short name T126
Test name
Test status
Simulation time 51890826 ps
CPU time 1.78 seconds
Started May 16 02:05:09 PM PDT 24
Finished May 16 02:05:13 PM PDT 24
Peak memory 217904 kb
Host smart-e5c4ac44-ec63-47fc-8cda-a6c03355e4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021429092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3021429092
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3201403009
Short name T556
Test name
Test status
Simulation time 114138630 ps
CPU time 1.57 seconds
Started May 16 02:05:18 PM PDT 24
Finished May 16 02:05:23 PM PDT 24
Peak memory 218356 kb
Host smart-c19a4d13-c9c5-4a07-ad41-c6dee363ac7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201403009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3201403009
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2311970693
Short name T613
Test name
Test status
Simulation time 51471393 ps
CPU time 2.04 seconds
Started May 16 02:05:09 PM PDT 24
Finished May 16 02:05:14 PM PDT 24
Peak memory 217788 kb
Host smart-1d3a821a-3206-4084-b46b-4e354c13e627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311970693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2311970693
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.375832321
Short name T441
Test name
Test status
Simulation time 72956096 ps
CPU time 1.27 seconds
Started May 16 02:05:09 PM PDT 24
Finished May 16 02:05:13 PM PDT 24
Peak memory 218124 kb
Host smart-54236192-f28e-401c-b5a8-5e12c6177951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375832321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.375832321
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.4102609685
Short name T136
Test name
Test status
Simulation time 73472738 ps
CPU time 1.46 seconds
Started May 16 02:05:13 PM PDT 24
Finished May 16 02:05:18 PM PDT 24
Peak memory 219240 kb
Host smart-7a12bd64-0f88-4121-87be-603e3affb590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102609685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.4102609685
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1575876014
Short name T1
Test name
Test status
Simulation time 93648004 ps
CPU time 1.4 seconds
Started May 16 02:05:10 PM PDT 24
Finished May 16 02:05:14 PM PDT 24
Peak memory 218148 kb
Host smart-4ea65bc3-f536-4138-b454-50b2744b4bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575876014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1575876014
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2146582876
Short name T299
Test name
Test status
Simulation time 38773678 ps
CPU time 1.44 seconds
Started May 16 02:05:10 PM PDT 24
Finished May 16 02:05:14 PM PDT 24
Peak memory 219356 kb
Host smart-614afc87-9bcc-4aba-9921-881c63076599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146582876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2146582876
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3234954271
Short name T822
Test name
Test status
Simulation time 54106018 ps
CPU time 1.57 seconds
Started May 16 02:05:12 PM PDT 24
Finished May 16 02:05:17 PM PDT 24
Peak memory 219348 kb
Host smart-5b9005a3-39eb-44fe-8427-d8bb492bd0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234954271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3234954271
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.124578681
Short name T267
Test name
Test status
Simulation time 24629092 ps
CPU time 1.21 seconds
Started May 16 02:02:44 PM PDT 24
Finished May 16 02:02:48 PM PDT 24
Peak memory 215356 kb
Host smart-343675de-f4d1-4f3e-b37d-20eac7630233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124578681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.124578681
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3756073323
Short name T594
Test name
Test status
Simulation time 18567549 ps
CPU time 0.99 seconds
Started May 16 02:02:44 PM PDT 24
Finished May 16 02:02:47 PM PDT 24
Peak memory 206280 kb
Host smart-28ba0654-6dd6-456d-bf9a-a3dcf566b1fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756073323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3756073323
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3321154265
Short name T560
Test name
Test status
Simulation time 64145511 ps
CPU time 1.02 seconds
Started May 16 02:02:42 PM PDT 24
Finished May 16 02:02:47 PM PDT 24
Peak memory 217952 kb
Host smart-5a566121-35fd-4efb-8200-adc9ccee129c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321154265 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3321154265
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3629655572
Short name T70
Test name
Test status
Simulation time 97026111 ps
CPU time 1.08 seconds
Started May 16 02:02:39 PM PDT 24
Finished May 16 02:02:44 PM PDT 24
Peak memory 219384 kb
Host smart-7a936f75-9281-4ecf-b30a-da80c2845e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629655572 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3629655572
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.4222989767
Short name T141
Test name
Test status
Simulation time 73004129 ps
CPU time 1.39 seconds
Started May 16 02:02:40 PM PDT 24
Finished May 16 02:02:45 PM PDT 24
Peak memory 217932 kb
Host smart-9cf0f537-9360-40da-a6d2-5e6b27d3408c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222989767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.4222989767
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.553461845
Short name T111
Test name
Test status
Simulation time 19804909 ps
CPU time 1.1 seconds
Started May 16 02:02:39 PM PDT 24
Finished May 16 02:02:45 PM PDT 24
Peak memory 215452 kb
Host smart-9c7561c2-d3e0-4fa1-b3e3-f50542831de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553461845 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.553461845
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1825568483
Short name T139
Test name
Test status
Simulation time 61032524 ps
CPU time 1.02 seconds
Started May 16 02:02:37 PM PDT 24
Finished May 16 02:02:42 PM PDT 24
Peak memory 214920 kb
Host smart-8e93e223-0559-40b2-b30a-f5963ac321e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825568483 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1825568483
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.533165080
Short name T163
Test name
Test status
Simulation time 65844225 ps
CPU time 1.35 seconds
Started May 16 02:02:37 PM PDT 24
Finished May 16 02:02:42 PM PDT 24
Peak memory 215004 kb
Host smart-7145f803-ad00-4120-b9ed-1a572c7e3056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533165080 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.533165080
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2148304871
Short name T210
Test name
Test status
Simulation time 339227272441 ps
CPU time 737.67 seconds
Started May 16 02:02:46 PM PDT 24
Finished May 16 02:15:07 PM PDT 24
Peak memory 219492 kb
Host smart-8a04fbfd-364b-4e75-9dc6-cda84189de98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148304871 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2148304871
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.963751391
Short name T534
Test name
Test status
Simulation time 97929571 ps
CPU time 1.62 seconds
Started May 16 02:05:09 PM PDT 24
Finished May 16 02:05:13 PM PDT 24
Peak memory 218260 kb
Host smart-5f9105d5-a4f0-4fd8-ac57-50a9913e9aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963751391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.963751391
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2292549960
Short name T654
Test name
Test status
Simulation time 112793541 ps
CPU time 1.57 seconds
Started May 16 02:05:11 PM PDT 24
Finished May 16 02:05:16 PM PDT 24
Peak memory 218216 kb
Host smart-1de91c13-007c-4d97-99fd-470edff81195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292549960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2292549960
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.469901653
Short name T337
Test name
Test status
Simulation time 71127240 ps
CPU time 1.07 seconds
Started May 16 02:05:13 PM PDT 24
Finished May 16 02:05:18 PM PDT 24
Peak memory 216796 kb
Host smart-f3521156-b642-4639-8d6f-d4a7d701c79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469901653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.469901653
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2719717967
Short name T554
Test name
Test status
Simulation time 44570736 ps
CPU time 1.17 seconds
Started May 16 02:05:12 PM PDT 24
Finished May 16 02:05:16 PM PDT 24
Peak memory 219136 kb
Host smart-01bddd3b-0460-4d3f-8bd3-3d38e7377a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719717967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2719717967
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1014463641
Short name T152
Test name
Test status
Simulation time 94529299 ps
CPU time 1.53 seconds
Started May 16 02:05:12 PM PDT 24
Finished May 16 02:05:17 PM PDT 24
Peak memory 218132 kb
Host smart-67afa0f9-45a9-451f-9d66-22ca362fe950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014463641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1014463641
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1921602629
Short name T393
Test name
Test status
Simulation time 255024009 ps
CPU time 3.72 seconds
Started May 16 02:05:11 PM PDT 24
Finished May 16 02:05:18 PM PDT 24
Peak memory 218616 kb
Host smart-d656c842-5159-408f-b92d-0c26bc7e6ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921602629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1921602629
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1244884068
Short name T115
Test name
Test status
Simulation time 58440278 ps
CPU time 1.19 seconds
Started May 16 02:05:17 PM PDT 24
Finished May 16 02:05:21 PM PDT 24
Peak memory 218028 kb
Host smart-ed3b4732-6b81-4c4a-a75c-28f3e94a3ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244884068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1244884068
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3457759136
Short name T398
Test name
Test status
Simulation time 69692514 ps
CPU time 1.3 seconds
Started May 16 02:05:09 PM PDT 24
Finished May 16 02:05:13 PM PDT 24
Peak memory 218216 kb
Host smart-36e47d51-0e2f-4eca-b6ec-5f9edc895b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457759136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3457759136
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.178112216
Short name T697
Test name
Test status
Simulation time 31375620 ps
CPU time 1.19 seconds
Started May 16 02:05:12 PM PDT 24
Finished May 16 02:05:17 PM PDT 24
Peak memory 216660 kb
Host smart-bc966755-6fd4-4443-b538-a743cd4324eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178112216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.178112216
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3244834763
Short name T596
Test name
Test status
Simulation time 96693790 ps
CPU time 2.79 seconds
Started May 16 02:05:13 PM PDT 24
Finished May 16 02:05:19 PM PDT 24
Peak memory 217944 kb
Host smart-8d50d1c8-f00d-4d18-8bd5-8b7c364396f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244834763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3244834763
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3439445041
Short name T716
Test name
Test status
Simulation time 46292005 ps
CPU time 1.14 seconds
Started May 16 02:02:38 PM PDT 24
Finished May 16 02:02:43 PM PDT 24
Peak memory 215332 kb
Host smart-128e183d-98b7-4d21-bd77-92582dfc60ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439445041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3439445041
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3747516453
Short name T509
Test name
Test status
Simulation time 107892357 ps
CPU time 0.78 seconds
Started May 16 02:02:46 PM PDT 24
Finished May 16 02:02:51 PM PDT 24
Peak memory 205988 kb
Host smart-0f0c634b-334b-4ed3-b936-49f8a80d1e2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747516453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3747516453
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3501143118
Short name T693
Test name
Test status
Simulation time 34019132 ps
CPU time 0.86 seconds
Started May 16 02:02:47 PM PDT 24
Finished May 16 02:02:51 PM PDT 24
Peak memory 215160 kb
Host smart-7b7f2bcd-f5bf-4260-b87e-04f5c1b2b23d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501143118 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3501143118
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2952264734
Short name T757
Test name
Test status
Simulation time 34202672 ps
CPU time 1.25 seconds
Started May 16 02:02:47 PM PDT 24
Finished May 16 02:02:52 PM PDT 24
Peak memory 216620 kb
Host smart-497701cb-e846-4c4b-8036-ed7f83756d24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952264734 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2952264734
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.2696201456
Short name T52
Test name
Test status
Simulation time 35646061 ps
CPU time 0.96 seconds
Started May 16 02:02:38 PM PDT 24
Finished May 16 02:02:43 PM PDT 24
Peak memory 219364 kb
Host smart-c81154f3-09b4-4dc9-a8e2-e7edd1b8e0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696201456 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2696201456
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3090529547
Short name T120
Test name
Test status
Simulation time 45367839 ps
CPU time 1.14 seconds
Started May 16 02:02:39 PM PDT 24
Finished May 16 02:02:44 PM PDT 24
Peak memory 216688 kb
Host smart-bcf77173-0f58-4816-8f57-09aff8b115ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090529547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3090529547
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.446524176
Short name T756
Test name
Test status
Simulation time 25534187 ps
CPU time 0.99 seconds
Started May 16 02:02:43 PM PDT 24
Finished May 16 02:02:47 PM PDT 24
Peak memory 214960 kb
Host smart-c9c9d26d-7e83-40de-b593-977e3dfb53d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446524176 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.446524176
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3362186129
Short name T348
Test name
Test status
Simulation time 24880028 ps
CPU time 0.91 seconds
Started May 16 02:02:38 PM PDT 24
Finished May 16 02:02:43 PM PDT 24
Peak memory 214960 kb
Host smart-4c668379-f412-49cc-a28f-5e4645fdd6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362186129 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3362186129
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3366222114
Short name T214
Test name
Test status
Simulation time 279594399 ps
CPU time 5.57 seconds
Started May 16 02:02:39 PM PDT 24
Finished May 16 02:02:48 PM PDT 24
Peak memory 214868 kb
Host smart-1f325cad-9401-441e-a644-85837b187db2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366222114 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3366222114
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.656911805
Short name T384
Test name
Test status
Simulation time 97929843172 ps
CPU time 1150.08 seconds
Started May 16 02:02:41 PM PDT 24
Finished May 16 02:21:55 PM PDT 24
Peak memory 222980 kb
Host smart-df69903c-3cd9-4a85-92a2-0590a6d01474
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656911805 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.656911805
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1690279033
Short name T477
Test name
Test status
Simulation time 31410555 ps
CPU time 1.29 seconds
Started May 16 02:05:12 PM PDT 24
Finished May 16 02:05:16 PM PDT 24
Peak memory 217920 kb
Host smart-13ad7b92-7931-4452-adf1-3012008a2976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690279033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1690279033
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.145981490
Short name T206
Test name
Test status
Simulation time 76472561 ps
CPU time 1.1 seconds
Started May 16 02:05:09 PM PDT 24
Finished May 16 02:05:12 PM PDT 24
Peak memory 216676 kb
Host smart-d7730e3b-0d1d-42cc-a2ae-2043a3b7b2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145981490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.145981490
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2645749355
Short name T675
Test name
Test status
Simulation time 45038937 ps
CPU time 1.2 seconds
Started May 16 02:05:13 PM PDT 24
Finished May 16 02:05:18 PM PDT 24
Peak memory 219012 kb
Host smart-58c84ebe-8fbe-4dd9-aaee-c29e5abe374e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645749355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2645749355
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2097329724
Short name T838
Test name
Test status
Simulation time 41394767 ps
CPU time 1.72 seconds
Started May 16 02:05:08 PM PDT 24
Finished May 16 02:05:11 PM PDT 24
Peak memory 217856 kb
Host smart-9cda4fb3-3645-4f28-9f38-ea838e662424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097329724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2097329724
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.956406549
Short name T516
Test name
Test status
Simulation time 248032131 ps
CPU time 3.52 seconds
Started May 16 02:05:18 PM PDT 24
Finished May 16 02:05:25 PM PDT 24
Peak memory 218760 kb
Host smart-3ee3d9dd-6bbe-4cb3-9225-3af332bc090f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956406549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.956406549
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2271630255
Short name T588
Test name
Test status
Simulation time 46790341 ps
CPU time 1.73 seconds
Started May 16 02:05:17 PM PDT 24
Finished May 16 02:05:22 PM PDT 24
Peak memory 217764 kb
Host smart-b34a6685-e279-40f9-a2ef-21f14616a5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271630255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2271630255
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2674880178
Short name T19
Test name
Test status
Simulation time 43029149 ps
CPU time 1.12 seconds
Started May 16 02:05:10 PM PDT 24
Finished May 16 02:05:14 PM PDT 24
Peak memory 216724 kb
Host smart-0d36b1af-6363-4ebf-874b-e2c3ffc8ea1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674880178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2674880178
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1599930345
Short name T125
Test name
Test status
Simulation time 90062394 ps
CPU time 1.34 seconds
Started May 16 02:05:11 PM PDT 24
Finished May 16 02:05:16 PM PDT 24
Peak memory 216856 kb
Host smart-ff2760a0-5e94-42dd-8325-364b4558f85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599930345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1599930345
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3220948276
Short name T773
Test name
Test status
Simulation time 50564034 ps
CPU time 1.05 seconds
Started May 16 02:05:18 PM PDT 24
Finished May 16 02:05:22 PM PDT 24
Peak memory 218080 kb
Host smart-7704f5d4-c958-4511-b5f1-4a43b6188b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220948276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3220948276
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.4291231351
Short name T659
Test name
Test status
Simulation time 45186915 ps
CPU time 1.18 seconds
Started May 16 02:05:12 PM PDT 24
Finished May 16 02:05:17 PM PDT 24
Peak memory 219272 kb
Host smart-32d27fce-9959-4c73-8fdb-1fd4c308872b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291231351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.4291231351
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.4084187681
Short name T93
Test name
Test status
Simulation time 24103937 ps
CPU time 1.27 seconds
Started May 16 02:02:46 PM PDT 24
Finished May 16 02:02:51 PM PDT 24
Peak memory 215364 kb
Host smart-cbc128b7-04b0-42da-b1f8-0b25cedd3735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084187681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.4084187681
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3625618741
Short name T497
Test name
Test status
Simulation time 40751938 ps
CPU time 0.89 seconds
Started May 16 02:02:46 PM PDT 24
Finished May 16 02:02:51 PM PDT 24
Peak memory 206228 kb
Host smart-77365ec6-7bbf-4d3d-82ac-69db4b4dd73e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625618741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3625618741
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1004191351
Short name T424
Test name
Test status
Simulation time 13176742 ps
CPU time 0.88 seconds
Started May 16 02:02:46 PM PDT 24
Finished May 16 02:02:51 PM PDT 24
Peak memory 216044 kb
Host smart-48e49bca-c87c-47db-9447-9efb299be44b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004191351 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1004191351
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2160775336
Short name T56
Test name
Test status
Simulation time 72854684 ps
CPU time 1.08 seconds
Started May 16 02:02:46 PM PDT 24
Finished May 16 02:02:51 PM PDT 24
Peak memory 216404 kb
Host smart-0a1ea844-0cb4-4358-beb6-f2b300e0764a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160775336 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2160775336
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_intr.1284359622
Short name T558
Test name
Test status
Simulation time 30075908 ps
CPU time 0.99 seconds
Started May 16 02:02:47 PM PDT 24
Finished May 16 02:02:51 PM PDT 24
Peak memory 215272 kb
Host smart-afbb4438-c84d-4b33-8ff0-42cb6c54369d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284359622 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1284359622
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2817390775
Short name T748
Test name
Test status
Simulation time 22338563 ps
CPU time 0.93 seconds
Started May 16 02:02:46 PM PDT 24
Finished May 16 02:02:51 PM PDT 24
Peak memory 214980 kb
Host smart-199530d9-9827-4f94-89de-b2ef7d912531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817390775 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2817390775
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1465181602
Short name T550
Test name
Test status
Simulation time 89300352 ps
CPU time 2.18 seconds
Started May 16 02:02:47 PM PDT 24
Finished May 16 02:02:53 PM PDT 24
Peak memory 214820 kb
Host smart-1e98484f-63a3-49ea-862b-3c5e266826b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465181602 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1465181602
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2973108853
Short name T202
Test name
Test status
Simulation time 53298591985 ps
CPU time 1386.29 seconds
Started May 16 02:02:47 PM PDT 24
Finished May 16 02:25:57 PM PDT 24
Peak memory 222860 kb
Host smart-96535d85-bd57-49ce-b500-f0a3f2fd7539
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973108853 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2973108853
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2072171161
Short name T429
Test name
Test status
Simulation time 34174322 ps
CPU time 1.01 seconds
Started May 16 02:05:13 PM PDT 24
Finished May 16 02:05:17 PM PDT 24
Peak memory 216320 kb
Host smart-4d002f25-4713-4fed-95c9-d90e233cdf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072171161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2072171161
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1903436836
Short name T583
Test name
Test status
Simulation time 30079105 ps
CPU time 1.29 seconds
Started May 16 02:05:13 PM PDT 24
Finished May 16 02:05:18 PM PDT 24
Peak memory 218904 kb
Host smart-71798694-9491-478c-b158-ca0ad89d5042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903436836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1903436836
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1000509950
Short name T293
Test name
Test status
Simulation time 76063548 ps
CPU time 1.18 seconds
Started May 16 02:05:09 PM PDT 24
Finished May 16 02:05:12 PM PDT 24
Peak memory 219180 kb
Host smart-4ede9d8e-76fd-4cad-8444-38baea59960d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000509950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1000509950
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2199407533
Short name T524
Test name
Test status
Simulation time 28683427 ps
CPU time 1.27 seconds
Started May 16 02:05:12 PM PDT 24
Finished May 16 02:05:17 PM PDT 24
Peak memory 216508 kb
Host smart-b63ee7f4-39cb-4240-b4dc-3639fbf8c4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199407533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2199407533
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2674754483
Short name T614
Test name
Test status
Simulation time 132757934 ps
CPU time 1.18 seconds
Started May 16 02:05:12 PM PDT 24
Finished May 16 02:05:17 PM PDT 24
Peak memory 216588 kb
Host smart-b6da4411-96f0-4c48-9ba4-c599e76f6056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674754483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2674754483
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.331963307
Short name T820
Test name
Test status
Simulation time 63894399 ps
CPU time 1.39 seconds
Started May 16 02:05:17 PM PDT 24
Finished May 16 02:05:22 PM PDT 24
Peak memory 218036 kb
Host smart-d2cf601c-0229-4d3a-a275-85a84b2a587c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331963307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.331963307
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2007068046
Short name T406
Test name
Test status
Simulation time 150785324 ps
CPU time 1.55 seconds
Started May 16 02:05:18 PM PDT 24
Finished May 16 02:05:23 PM PDT 24
Peak memory 218116 kb
Host smart-975ac55d-de20-440f-bbfc-0710e20821a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007068046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2007068046
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1920896988
Short name T549
Test name
Test status
Simulation time 51383017 ps
CPU time 1.14 seconds
Started May 16 02:05:13 PM PDT 24
Finished May 16 02:05:17 PM PDT 24
Peak memory 217784 kb
Host smart-2ee59644-6c5e-432d-8ec3-506097bf0c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920896988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1920896988
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3378353969
Short name T302
Test name
Test status
Simulation time 34039936 ps
CPU time 1.47 seconds
Started May 16 02:05:12 PM PDT 24
Finished May 16 02:05:17 PM PDT 24
Peak memory 216748 kb
Host smart-e8b659fb-0580-46a6-8da7-2552f14d56d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378353969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3378353969
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1475098995
Short name T67
Test name
Test status
Simulation time 84774153 ps
CPU time 1.19 seconds
Started May 16 02:02:59 PM PDT 24
Finished May 16 02:03:02 PM PDT 24
Peak memory 215352 kb
Host smart-0afabc97-917d-442d-8ab0-0add608b69fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475098995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1475098995
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2995247948
Short name T545
Test name
Test status
Simulation time 59034925 ps
CPU time 0.99 seconds
Started May 16 02:02:58 PM PDT 24
Finished May 16 02:03:01 PM PDT 24
Peak memory 206292 kb
Host smart-5089a5a7-976e-4257-be83-a8c8d9fff2d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995247948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2995247948
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3595104982
Short name T633
Test name
Test status
Simulation time 13973262 ps
CPU time 0.93 seconds
Started May 16 02:02:58 PM PDT 24
Finished May 16 02:03:01 PM PDT 24
Peak memory 215328 kb
Host smart-8b308854-32db-4bf0-abad-892ebed6469e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595104982 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3595104982
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1184956278
Short name T38
Test name
Test status
Simulation time 79135051 ps
CPU time 1.01 seconds
Started May 16 02:02:59 PM PDT 24
Finished May 16 02:03:03 PM PDT 24
Peak memory 216552 kb
Host smart-b241a73c-f399-4978-aa6a-3a47601a9437
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184956278 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1184956278
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.4115465721
Short name T187
Test name
Test status
Simulation time 125709972 ps
CPU time 1.13 seconds
Started May 16 02:02:59 PM PDT 24
Finished May 16 02:03:02 PM PDT 24
Peak memory 219284 kb
Host smart-5d996c53-5344-478c-bd9c-ea50bf7a6e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115465721 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.4115465721
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.119653908
Short name T357
Test name
Test status
Simulation time 39662139 ps
CPU time 1.27 seconds
Started May 16 02:02:47 PM PDT 24
Finished May 16 02:02:51 PM PDT 24
Peak memory 216516 kb
Host smart-7c28da3f-bda5-48cc-8fcb-16f8d4ef6c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119653908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.119653908
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_smoke.1265634629
Short name T725
Test name
Test status
Simulation time 32658394 ps
CPU time 0.95 seconds
Started May 16 02:02:48 PM PDT 24
Finished May 16 02:02:52 PM PDT 24
Peak memory 214964 kb
Host smart-3554d2a2-57d3-43d1-bef5-cf52b2ec7652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265634629 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1265634629
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1464683766
Short name T799
Test name
Test status
Simulation time 157149478 ps
CPU time 3.45 seconds
Started May 16 02:02:47 PM PDT 24
Finished May 16 02:02:54 PM PDT 24
Peak memory 216728 kb
Host smart-49fcf155-0ac4-446c-a985-097255efa9ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464683766 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1464683766
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.756529591
Short name T162
Test name
Test status
Simulation time 22835882902 ps
CPU time 613.21 seconds
Started May 16 02:02:49 PM PDT 24
Finished May 16 02:13:04 PM PDT 24
Peak memory 218124 kb
Host smart-84da0a39-8b06-4d5c-932e-69b179f87dfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756529591 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.756529591
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2026180957
Short name T741
Test name
Test status
Simulation time 43405214 ps
CPU time 1.6 seconds
Started May 16 02:05:12 PM PDT 24
Finished May 16 02:05:17 PM PDT 24
Peak memory 217828 kb
Host smart-2569626a-9450-411c-be65-408447a6d2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026180957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2026180957
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2566041139
Short name T647
Test name
Test status
Simulation time 27637601 ps
CPU time 1.23 seconds
Started May 16 02:05:11 PM PDT 24
Finished May 16 02:05:15 PM PDT 24
Peak memory 219284 kb
Host smart-fdd62770-096e-482a-a232-b7d4e60b94c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566041139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2566041139
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.4085340113
Short name T826
Test name
Test status
Simulation time 65719449 ps
CPU time 1.25 seconds
Started May 16 02:05:13 PM PDT 24
Finished May 16 02:05:17 PM PDT 24
Peak memory 216812 kb
Host smart-f60031ff-260e-4e9f-a5f8-ffc1116bb339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085340113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.4085340113
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.524647759
Short name T290
Test name
Test status
Simulation time 58604329 ps
CPU time 1.59 seconds
Started May 16 02:05:18 PM PDT 24
Finished May 16 02:05:23 PM PDT 24
Peak memory 216696 kb
Host smart-6513bbd8-bf52-4ac2-8354-42528f4f1eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524647759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.524647759
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1475948359
Short name T146
Test name
Test status
Simulation time 59516699 ps
CPU time 1.16 seconds
Started May 16 02:05:11 PM PDT 24
Finished May 16 02:05:16 PM PDT 24
Peak memory 216704 kb
Host smart-d5e7a90e-86d6-4b39-be23-52a3f1716bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475948359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1475948359
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.289659654
Short name T343
Test name
Test status
Simulation time 52195157 ps
CPU time 1.27 seconds
Started May 16 02:05:18 PM PDT 24
Finished May 16 02:05:23 PM PDT 24
Peak memory 216680 kb
Host smart-a681eab1-90d5-44c3-b23b-67df12c3cbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289659654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.289659654
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.4151906603
Short name T313
Test name
Test status
Simulation time 140726659 ps
CPU time 1.73 seconds
Started May 16 02:05:18 PM PDT 24
Finished May 16 02:05:23 PM PDT 24
Peak memory 218164 kb
Host smart-e12697ae-244f-4dab-9ccf-23242507349b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151906603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.4151906603
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1038790249
Short name T310
Test name
Test status
Simulation time 243128928 ps
CPU time 3.46 seconds
Started May 16 02:05:10 PM PDT 24
Finished May 16 02:05:16 PM PDT 24
Peak memory 219560 kb
Host smart-f0049033-2bbf-40c6-bf12-97841d0e5b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038790249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1038790249
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.4069803584
Short name T2
Test name
Test status
Simulation time 142175746 ps
CPU time 0.98 seconds
Started May 16 02:05:17 PM PDT 24
Finished May 16 02:05:21 PM PDT 24
Peak memory 216572 kb
Host smart-bf1de87c-3307-4c18-9c0a-5f9bd40f4864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069803584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.4069803584
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1436800415
Short name T670
Test name
Test status
Simulation time 357791665 ps
CPU time 1.33 seconds
Started May 16 02:02:57 PM PDT 24
Finished May 16 02:02:59 PM PDT 24
Peak memory 215348 kb
Host smart-5c134d7f-e973-47e6-bf7f-a001ff9a9a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436800415 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1436800415
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3964673376
Short name T577
Test name
Test status
Simulation time 19016567 ps
CPU time 0.98 seconds
Started May 16 02:02:58 PM PDT 24
Finished May 16 02:03:01 PM PDT 24
Peak memory 206284 kb
Host smart-5cbc1684-5bd2-49f1-ae66-43f20c6778ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964673376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3964673376
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1127668902
Short name T71
Test name
Test status
Simulation time 26479214 ps
CPU time 0.83 seconds
Started May 16 02:02:59 PM PDT 24
Finished May 16 02:03:02 PM PDT 24
Peak memory 216040 kb
Host smart-40981459-4f7d-4e66-a2aa-32f7b2cd0734
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127668902 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1127668902
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3008472059
Short name T475
Test name
Test status
Simulation time 87713572 ps
CPU time 1.12 seconds
Started May 16 02:03:01 PM PDT 24
Finished May 16 02:03:04 PM PDT 24
Peak memory 216548 kb
Host smart-51d67356-9315-498c-b22f-7389f21a8dd3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008472059 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3008472059
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.141770415
Short name T15
Test name
Test status
Simulation time 18963719 ps
CPU time 1.16 seconds
Started May 16 02:03:00 PM PDT 24
Finished May 16 02:03:04 PM PDT 24
Peak memory 223416 kb
Host smart-eda3f257-18aa-4a49-a0cc-aa5c8eb1ea8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141770415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.141770415
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.977403589
Short name T611
Test name
Test status
Simulation time 81781573 ps
CPU time 1.4 seconds
Started May 16 02:02:58 PM PDT 24
Finished May 16 02:03:02 PM PDT 24
Peak memory 218032 kb
Host smart-f301c3b4-ac51-4d3e-8929-baa32b0a80e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977403589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.977403589
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2485077083
Short name T645
Test name
Test status
Simulation time 37003061 ps
CPU time 0.92 seconds
Started May 16 02:02:58 PM PDT 24
Finished May 16 02:03:01 PM PDT 24
Peak memory 215120 kb
Host smart-fcbb3a72-41fc-4b32-9952-e4878617fb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485077083 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2485077083
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.1730213185
Short name T766
Test name
Test status
Simulation time 18317649 ps
CPU time 1.02 seconds
Started May 16 02:02:59 PM PDT 24
Finished May 16 02:03:02 PM PDT 24
Peak memory 214980 kb
Host smart-a45e4a3c-3d03-4328-aa74-277d54ab6819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730213185 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1730213185
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.4085271982
Short name T657
Test name
Test status
Simulation time 418168968 ps
CPU time 4.47 seconds
Started May 16 02:02:58 PM PDT 24
Finished May 16 02:03:05 PM PDT 24
Peak memory 217988 kb
Host smart-b254b4f0-4636-4dbc-b59e-3082b37b921a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085271982 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.4085271982
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1134168157
Short name T851
Test name
Test status
Simulation time 148417747377 ps
CPU time 1505.5 seconds
Started May 16 02:02:58 PM PDT 24
Finished May 16 02:28:05 PM PDT 24
Peak memory 225960 kb
Host smart-8b96e225-bad9-4caa-bc37-dd680d4b4244
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134168157 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1134168157
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1583317994
Short name T314
Test name
Test status
Simulation time 192166652 ps
CPU time 2.08 seconds
Started May 16 02:05:18 PM PDT 24
Finished May 16 02:05:24 PM PDT 24
Peak memory 218448 kb
Host smart-f04d2d1c-96c7-45d8-9bb2-5a63e1217d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583317994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1583317994
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3748805605
Short name T667
Test name
Test status
Simulation time 81411223 ps
CPU time 1.8 seconds
Started May 16 02:05:18 PM PDT 24
Finished May 16 02:05:23 PM PDT 24
Peak memory 218336 kb
Host smart-91cb00ed-a1e7-4290-b3c9-c6fbcdbccff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748805605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3748805605
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1236184703
Short name T27
Test name
Test status
Simulation time 230063357 ps
CPU time 1.44 seconds
Started May 16 02:05:20 PM PDT 24
Finished May 16 02:05:25 PM PDT 24
Peak memory 218012 kb
Host smart-69738958-80e2-480b-babf-58d6ae0bcded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236184703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1236184703
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.463225165
Short name T489
Test name
Test status
Simulation time 57612142 ps
CPU time 1.15 seconds
Started May 16 02:05:19 PM PDT 24
Finished May 16 02:05:23 PM PDT 24
Peak memory 218312 kb
Host smart-afbf59c5-6ff0-4bff-a666-0abc08d246ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463225165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.463225165
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3420221581
Short name T284
Test name
Test status
Simulation time 44336365 ps
CPU time 1.4 seconds
Started May 16 02:05:20 PM PDT 24
Finished May 16 02:05:24 PM PDT 24
Peak memory 218932 kb
Host smart-3d740d13-0e78-42c1-9b81-d3bfdb27e77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420221581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3420221581
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2266145218
Short name T519
Test name
Test status
Simulation time 153739675 ps
CPU time 1.19 seconds
Started May 16 02:05:20 PM PDT 24
Finished May 16 02:05:26 PM PDT 24
Peak memory 219188 kb
Host smart-6dcf7424-3f40-4113-bc09-57c18796bf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266145218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2266145218
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1651389569
Short name T696
Test name
Test status
Simulation time 43642912 ps
CPU time 1.45 seconds
Started May 16 02:05:19 PM PDT 24
Finished May 16 02:05:24 PM PDT 24
Peak memory 217848 kb
Host smart-b24b2d6e-9f4c-46b6-9c73-1feed4c0c7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651389569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1651389569
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.4100850808
Short name T703
Test name
Test status
Simulation time 86794039 ps
CPU time 1.2 seconds
Started May 16 02:05:22 PM PDT 24
Finished May 16 02:05:27 PM PDT 24
Peak memory 219304 kb
Host smart-da5a0f04-1e0e-4fc3-8e19-c079f9b39663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100850808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.4100850808
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1093942547
Short name T806
Test name
Test status
Simulation time 32430842 ps
CPU time 1.28 seconds
Started May 16 02:05:20 PM PDT 24
Finished May 16 02:05:26 PM PDT 24
Peak memory 218032 kb
Host smart-6cbf197b-22bc-4a27-8d09-e55fd13a8d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093942547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1093942547
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.84893690
Short name T435
Test name
Test status
Simulation time 45659835 ps
CPU time 1.03 seconds
Started May 16 02:05:18 PM PDT 24
Finished May 16 02:05:23 PM PDT 24
Peak memory 216832 kb
Host smart-843cf483-5d5f-419a-8e99-6e7e791be7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84893690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.84893690
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3950611195
Short name T846
Test name
Test status
Simulation time 77625248 ps
CPU time 1.24 seconds
Started May 16 02:02:58 PM PDT 24
Finished May 16 02:03:01 PM PDT 24
Peak memory 215380 kb
Host smart-4b088d69-2158-4e45-be5c-e35e09f00e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950611195 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3950611195
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1246024405
Short name T396
Test name
Test status
Simulation time 20652366 ps
CPU time 0.85 seconds
Started May 16 02:03:00 PM PDT 24
Finished May 16 02:03:03 PM PDT 24
Peak memory 206528 kb
Host smart-678dfd58-0fd6-412d-856e-ff3102107185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246024405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1246024405
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.4199018136
Short name T708
Test name
Test status
Simulation time 42948774 ps
CPU time 1.22 seconds
Started May 16 02:02:57 PM PDT 24
Finished May 16 02:02:59 PM PDT 24
Peak memory 216576 kb
Host smart-5d4c3998-c706-45f8-a3bb-5945f1238c23
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199018136 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.4199018136
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3701811517
Short name T814
Test name
Test status
Simulation time 89712912 ps
CPU time 1.05 seconds
Started May 16 02:02:59 PM PDT 24
Finished May 16 02:03:02 PM PDT 24
Peak memory 219072 kb
Host smart-2db579ea-6013-492b-9617-8097e107d3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701811517 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3701811517
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1491066528
Short name T612
Test name
Test status
Simulation time 56904789 ps
CPU time 1.89 seconds
Started May 16 02:02:59 PM PDT 24
Finished May 16 02:03:04 PM PDT 24
Peak memory 217988 kb
Host smart-633a9c10-b848-48b2-8085-a9eb8580c54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491066528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1491066528
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1378559193
Short name T131
Test name
Test status
Simulation time 92043549 ps
CPU time 0.96 seconds
Started May 16 02:02:59 PM PDT 24
Finished May 16 02:03:03 PM PDT 24
Peak memory 223264 kb
Host smart-e981a203-bc29-4521-a514-ba246b798a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378559193 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1378559193
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1657619005
Short name T365
Test name
Test status
Simulation time 26364284 ps
CPU time 1.01 seconds
Started May 16 02:03:00 PM PDT 24
Finished May 16 02:03:04 PM PDT 24
Peak memory 214884 kb
Host smart-aef3df1d-ff01-4d44-b574-ad804bfd3f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657619005 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1657619005
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3945557557
Short name T490
Test name
Test status
Simulation time 168961772 ps
CPU time 3.64 seconds
Started May 16 02:02:58 PM PDT 24
Finished May 16 02:03:03 PM PDT 24
Peak memory 214968 kb
Host smart-59c37de3-1e49-4140-88cc-20f8f8c0dc42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945557557 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3945557557
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2290895092
Short name T468
Test name
Test status
Simulation time 28730195140 ps
CPU time 378.64 seconds
Started May 16 02:02:59 PM PDT 24
Finished May 16 02:09:21 PM PDT 24
Peak memory 218780 kb
Host smart-da04fe5a-5b1a-4ad5-8c64-c086880d6a10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290895092 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2290895092
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1465246080
Short name T405
Test name
Test status
Simulation time 45001422 ps
CPU time 1.29 seconds
Started May 16 02:05:20 PM PDT 24
Finished May 16 02:05:25 PM PDT 24
Peak memory 216820 kb
Host smart-cb56cb96-cac4-4ef3-9894-d8b621090ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465246080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1465246080
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3000612184
Short name T627
Test name
Test status
Simulation time 161504849 ps
CPU time 1.49 seconds
Started May 16 02:05:22 PM PDT 24
Finished May 16 02:05:28 PM PDT 24
Peak memory 218812 kb
Host smart-046bcb0c-0bd4-4f0a-b6db-03744e6b6f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000612184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3000612184
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1805884487
Short name T833
Test name
Test status
Simulation time 29658556 ps
CPU time 1.25 seconds
Started May 16 02:05:24 PM PDT 24
Finished May 16 02:05:29 PM PDT 24
Peak memory 219304 kb
Host smart-8ebb077c-0845-4190-9ed7-a59d15f95fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805884487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1805884487
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3649267407
Short name T700
Test name
Test status
Simulation time 22311971 ps
CPU time 1.16 seconds
Started May 16 02:05:20 PM PDT 24
Finished May 16 02:05:25 PM PDT 24
Peak memory 218688 kb
Host smart-e894ee26-43d7-4ac3-95fe-673dcb75f9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649267407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3649267407
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.184181819
Short name T530
Test name
Test status
Simulation time 78513180 ps
CPU time 2.7 seconds
Started May 16 02:05:23 PM PDT 24
Finished May 16 02:05:30 PM PDT 24
Peak memory 217212 kb
Host smart-45308b4c-6657-4124-8951-60abe909ee77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184181819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.184181819
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2835267177
Short name T117
Test name
Test status
Simulation time 54922519 ps
CPU time 1.33 seconds
Started May 16 02:05:22 PM PDT 24
Finished May 16 02:05:28 PM PDT 24
Peak memory 219376 kb
Host smart-aef742d4-7821-47d7-bfad-59da9c4ee5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835267177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2835267177
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3313378034
Short name T473
Test name
Test status
Simulation time 122234465 ps
CPU time 1.19 seconds
Started May 16 02:05:22 PM PDT 24
Finished May 16 02:05:28 PM PDT 24
Peak memory 219068 kb
Host smart-a480de93-4aa2-4304-9f1b-02455a050323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313378034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3313378034
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.192977044
Short name T562
Test name
Test status
Simulation time 55379552 ps
CPU time 1.68 seconds
Started May 16 02:05:23 PM PDT 24
Finished May 16 02:05:29 PM PDT 24
Peak memory 217860 kb
Host smart-78274925-bd60-450a-82e2-821316e8e7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192977044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.192977044
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.4093013047
Short name T258
Test name
Test status
Simulation time 145948965 ps
CPU time 2.54 seconds
Started May 16 02:05:20 PM PDT 24
Finished May 16 02:05:26 PM PDT 24
Peak memory 218944 kb
Host smart-f5ec2aa1-1c96-4dac-81f0-72d69d949b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093013047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.4093013047
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.601347327
Short name T288
Test name
Test status
Simulation time 53107375 ps
CPU time 1.82 seconds
Started May 16 02:05:20 PM PDT 24
Finished May 16 02:05:25 PM PDT 24
Peak memory 217800 kb
Host smart-9a5e9876-f6bb-4ef1-bc64-e0a667e1d4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601347327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.601347327
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.129210383
Short name T273
Test name
Test status
Simulation time 213773927 ps
CPU time 1.25 seconds
Started May 16 02:03:01 PM PDT 24
Finished May 16 02:03:04 PM PDT 24
Peak memory 215368 kb
Host smart-3acc0aed-9629-44a6-8d1d-553b99a807c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129210383 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.129210383
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.4146497698
Short name T724
Test name
Test status
Simulation time 27650309 ps
CPU time 0.91 seconds
Started May 16 02:03:11 PM PDT 24
Finished May 16 02:03:14 PM PDT 24
Peak memory 206252 kb
Host smart-739a017c-e52c-4dde-8cc5-8abbf567e210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146497698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.4146497698
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.3660992405
Short name T394
Test name
Test status
Simulation time 10699427 ps
CPU time 0.86 seconds
Started May 16 02:02:58 PM PDT 24
Finished May 16 02:03:01 PM PDT 24
Peak memory 215796 kb
Host smart-3dc0a0d2-af68-4834-8e1e-29fc9094a840
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660992405 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3660992405
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2100883499
Short name T318
Test name
Test status
Simulation time 305939257 ps
CPU time 1.41 seconds
Started May 16 02:02:59 PM PDT 24
Finished May 16 02:03:03 PM PDT 24
Peak memory 216588 kb
Host smart-c97e03b7-d9b4-431b-a6f2-554cbf97ad02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100883499 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2100883499
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.930790604
Short name T805
Test name
Test status
Simulation time 32045676 ps
CPU time 0.91 seconds
Started May 16 02:03:00 PM PDT 24
Finished May 16 02:03:03 PM PDT 24
Peak memory 218044 kb
Host smart-7554c806-2922-48b9-8499-f6112c4ce991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930790604 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.930790604
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3665940226
Short name T706
Test name
Test status
Simulation time 163118420 ps
CPU time 1.22 seconds
Started May 16 02:03:00 PM PDT 24
Finished May 16 02:03:04 PM PDT 24
Peak memory 216664 kb
Host smart-4e514188-878e-49ac-81dc-de16a626f315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665940226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3665940226
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3490177208
Short name T105
Test name
Test status
Simulation time 28842808 ps
CPU time 0.89 seconds
Started May 16 02:03:00 PM PDT 24
Finished May 16 02:03:03 PM PDT 24
Peak memory 215336 kb
Host smart-ed97b2a7-ceab-48a4-a04e-616dd4259162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490177208 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3490177208
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1152985157
Short name T399
Test name
Test status
Simulation time 62625020 ps
CPU time 0.99 seconds
Started May 16 02:02:59 PM PDT 24
Finished May 16 02:03:02 PM PDT 24
Peak memory 214808 kb
Host smart-206c84eb-0778-4d92-a573-71971bbf5660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152985157 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1152985157
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3673563035
Short name T330
Test name
Test status
Simulation time 1313618440 ps
CPU time 4.36 seconds
Started May 16 02:02:58 PM PDT 24
Finished May 16 02:03:04 PM PDT 24
Peak memory 219712 kb
Host smart-8b32b95a-9f7f-4d35-8c43-000ce0d9af51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673563035 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3673563035
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.380535092
Short name T461
Test name
Test status
Simulation time 95605208121 ps
CPU time 1235.7 seconds
Started May 16 02:03:00 PM PDT 24
Finished May 16 02:23:38 PM PDT 24
Peak memory 224384 kb
Host smart-2f609c0b-37cc-4732-bb64-d9d417892026
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380535092 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.380535092
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.4094932188
Short name T13
Test name
Test status
Simulation time 35531743 ps
CPU time 1.52 seconds
Started May 16 02:05:19 PM PDT 24
Finished May 16 02:05:24 PM PDT 24
Peak memory 218708 kb
Host smart-45f979be-3403-4c74-9732-94dc69a96619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094932188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.4094932188
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.290461866
Short name T356
Test name
Test status
Simulation time 38045609 ps
CPU time 1.39 seconds
Started May 16 02:05:22 PM PDT 24
Finished May 16 02:05:27 PM PDT 24
Peak memory 217988 kb
Host smart-2ac36ee7-081a-4977-96de-e86b8adf6249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290461866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.290461866
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2838231627
Short name T778
Test name
Test status
Simulation time 57584956 ps
CPU time 1.32 seconds
Started May 16 02:05:23 PM PDT 24
Finished May 16 02:05:28 PM PDT 24
Peak memory 217948 kb
Host smart-f661e23b-7596-45f7-83c1-937c971d1509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838231627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2838231627
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3810151411
Short name T743
Test name
Test status
Simulation time 33290964 ps
CPU time 1.36 seconds
Started May 16 02:05:20 PM PDT 24
Finished May 16 02:05:25 PM PDT 24
Peak memory 217840 kb
Host smart-438a3a99-4bba-4aeb-bcd0-394487af45ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810151411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3810151411
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1232556224
Short name T419
Test name
Test status
Simulation time 51898438 ps
CPU time 1.51 seconds
Started May 16 02:05:22 PM PDT 24
Finished May 16 02:05:27 PM PDT 24
Peak memory 218116 kb
Host smart-0ee95327-5cfb-464b-8329-6a6b7f969ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232556224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1232556224
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2049062479
Short name T749
Test name
Test status
Simulation time 50658749 ps
CPU time 1.4 seconds
Started May 16 02:05:21 PM PDT 24
Finished May 16 02:05:26 PM PDT 24
Peak memory 218012 kb
Host smart-64757598-55b4-40c6-914b-7d6afa0ddf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049062479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2049062479
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.34852752
Short name T444
Test name
Test status
Simulation time 130501797 ps
CPU time 1.74 seconds
Started May 16 02:05:24 PM PDT 24
Finished May 16 02:05:30 PM PDT 24
Peak memory 217860 kb
Host smart-d1932274-02ed-49af-b045-272918e0c1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34852752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.34852752
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2524390731
Short name T677
Test name
Test status
Simulation time 74694746 ps
CPU time 1.12 seconds
Started May 16 02:05:22 PM PDT 24
Finished May 16 02:05:27 PM PDT 24
Peak memory 216548 kb
Host smart-edb22e41-1e04-4b95-a354-be4ff71659b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524390731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2524390731
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.657110313
Short name T303
Test name
Test status
Simulation time 149554073 ps
CPU time 1.68 seconds
Started May 16 02:05:21 PM PDT 24
Finished May 16 02:05:27 PM PDT 24
Peak memory 217964 kb
Host smart-4f1cda06-0da6-4e00-8afa-0e229e0441e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657110313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.657110313
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2797469995
Short name T506
Test name
Test status
Simulation time 118019670 ps
CPU time 1.56 seconds
Started May 16 02:05:21 PM PDT 24
Finished May 16 02:05:27 PM PDT 24
Peak memory 218312 kb
Host smart-53876bec-975c-49c1-ab72-b244bd88184f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797469995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2797469995
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert_test.3426803744
Short name T128
Test name
Test status
Simulation time 47554162 ps
CPU time 0.84 seconds
Started May 16 02:03:11 PM PDT 24
Finished May 16 02:03:15 PM PDT 24
Peak memory 206268 kb
Host smart-a6394fa2-fb78-4967-b75d-893305c7fc2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426803744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3426803744
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.399131142
Short name T522
Test name
Test status
Simulation time 26211709 ps
CPU time 0.87 seconds
Started May 16 02:03:12 PM PDT 24
Finished May 16 02:03:16 PM PDT 24
Peak memory 206976 kb
Host smart-77b5b876-aa9a-49b6-98e6-64e8c2b9bd3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399131142 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.399131142
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.680968961
Short name T797
Test name
Test status
Simulation time 54091765 ps
CPU time 1.2 seconds
Started May 16 02:03:11 PM PDT 24
Finished May 16 02:03:15 PM PDT 24
Peak memory 216460 kb
Host smart-fdede7a4-d08a-43c4-b01b-9f6d07b093af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680968961 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.680968961
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.533033025
Short name T679
Test name
Test status
Simulation time 25662663 ps
CPU time 1.05 seconds
Started May 16 02:03:13 PM PDT 24
Finished May 16 02:03:18 PM PDT 24
Peak memory 219396 kb
Host smart-e456e3d4-57b0-482a-8e9b-8c0557553a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533033025 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.533033025
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3984082264
Short name T796
Test name
Test status
Simulation time 56759882 ps
CPU time 1.29 seconds
Started May 16 02:03:11 PM PDT 24
Finished May 16 02:03:14 PM PDT 24
Peak memory 218080 kb
Host smart-e27cb79e-a910-4d91-855a-0933dd9d1dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984082264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3984082264
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.99780619
Short name T715
Test name
Test status
Simulation time 35108306 ps
CPU time 0.92 seconds
Started May 16 02:03:11 PM PDT 24
Finished May 16 02:03:14 PM PDT 24
Peak memory 215284 kb
Host smart-94a8573f-e8e0-42d1-a057-7d36dfb2d4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99780619 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.99780619
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1724407258
Short name T852
Test name
Test status
Simulation time 73802279 ps
CPU time 0.91 seconds
Started May 16 02:03:15 PM PDT 24
Finished May 16 02:03:18 PM PDT 24
Peak memory 214976 kb
Host smart-8433dd0d-05c3-4f15-b1f7-3e540dabd1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724407258 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1724407258
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3143579463
Short name T591
Test name
Test status
Simulation time 534318337 ps
CPU time 3.31 seconds
Started May 16 02:03:18 PM PDT 24
Finished May 16 02:03:22 PM PDT 24
Peak memory 215008 kb
Host smart-2fcc35fb-911a-4f3a-982f-709853a8a2cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143579463 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3143579463
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3043208679
Short name T114
Test name
Test status
Simulation time 44740114128 ps
CPU time 519.01 seconds
Started May 16 02:03:12 PM PDT 24
Finished May 16 02:11:54 PM PDT 24
Peak memory 219408 kb
Host smart-4874764c-b672-4a7b-b749-2e90aa05d4cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043208679 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3043208679
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.3794400786
Short name T740
Test name
Test status
Simulation time 138252186 ps
CPU time 2.94 seconds
Started May 16 02:05:21 PM PDT 24
Finished May 16 02:05:29 PM PDT 24
Peak memory 219488 kb
Host smart-58c6ba64-d75f-4927-8d50-ddc70be230f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794400786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3794400786
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1359548776
Short name T791
Test name
Test status
Simulation time 63040193 ps
CPU time 0.99 seconds
Started May 16 02:05:20 PM PDT 24
Finished May 16 02:05:25 PM PDT 24
Peak memory 216680 kb
Host smart-80ba1b29-c725-493d-9dbb-476cf92636da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359548776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1359548776
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3569899661
Short name T329
Test name
Test status
Simulation time 46018580 ps
CPU time 1.27 seconds
Started May 16 02:05:24 PM PDT 24
Finished May 16 02:05:29 PM PDT 24
Peak memory 216764 kb
Host smart-69176b5d-ed34-4e4c-9a0d-2c0d729225c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569899661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3569899661
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.475236140
Short name T640
Test name
Test status
Simulation time 18695731 ps
CPU time 1.1 seconds
Started May 16 02:05:20 PM PDT 24
Finished May 16 02:05:25 PM PDT 24
Peak memory 216856 kb
Host smart-0ad234de-73d7-43ea-8ba2-49f901764f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475236140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.475236140
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3696702953
Short name T370
Test name
Test status
Simulation time 106261073 ps
CPU time 1.21 seconds
Started May 16 02:05:24 PM PDT 24
Finished May 16 02:05:29 PM PDT 24
Peak memory 216660 kb
Host smart-fb5854b7-dd79-404b-87f2-1c7dc8d2ef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696702953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3696702953
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.161717733
Short name T771
Test name
Test status
Simulation time 88896794 ps
CPU time 2.35 seconds
Started May 16 02:05:24 PM PDT 24
Finished May 16 02:05:30 PM PDT 24
Peak memory 219080 kb
Host smart-4ee4c0e6-c59d-4679-bf6c-98d682110cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161717733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.161717733
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1357673743
Short name T683
Test name
Test status
Simulation time 46450355 ps
CPU time 1.4 seconds
Started May 16 02:05:23 PM PDT 24
Finished May 16 02:05:28 PM PDT 24
Peak memory 216580 kb
Host smart-334fa855-07f8-4a06-ab97-8281b9e20728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357673743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1357673743
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3417171416
Short name T414
Test name
Test status
Simulation time 109724863 ps
CPU time 1.35 seconds
Started May 16 02:05:22 PM PDT 24
Finished May 16 02:05:28 PM PDT 24
Peak memory 218240 kb
Host smart-b93211fd-fad7-4b36-81b0-cbe11cbdfa05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417171416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3417171416
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2733169083
Short name T691
Test name
Test status
Simulation time 47894344 ps
CPU time 1.24 seconds
Started May 16 02:05:21 PM PDT 24
Finished May 16 02:05:26 PM PDT 24
Peak memory 218056 kb
Host smart-18b6e81c-d569-475a-867a-de752975db43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733169083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2733169083
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.953885881
Short name T428
Test name
Test status
Simulation time 74875075 ps
CPU time 1.13 seconds
Started May 16 02:05:21 PM PDT 24
Finished May 16 02:05:27 PM PDT 24
Peak memory 216752 kb
Host smart-599b99be-1459-4045-85e0-51be85e3fcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953885881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.953885881
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2718970480
Short name T280
Test name
Test status
Simulation time 36731177 ps
CPU time 1.13 seconds
Started May 16 02:01:36 PM PDT 24
Finished May 16 02:01:40 PM PDT 24
Peak memory 215420 kb
Host smart-591bf1a9-034f-49a9-8b65-4dd3d9c3da4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718970480 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2718970480
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3199484710
Short name T480
Test name
Test status
Simulation time 14303723 ps
CPU time 0.9 seconds
Started May 16 02:01:37 PM PDT 24
Finished May 16 02:01:40 PM PDT 24
Peak memory 206256 kb
Host smart-8e7613c5-f54d-4e81-ace2-127a7ad66ae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199484710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3199484710
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_genbits.3106737148
Short name T408
Test name
Test status
Simulation time 98403050 ps
CPU time 1 seconds
Started May 16 02:01:24 PM PDT 24
Finished May 16 02:01:27 PM PDT 24
Peak memory 216568 kb
Host smart-9dce00d7-750c-4ef5-a59b-b77d57f17bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106737148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3106737148
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2559060898
Short name T632
Test name
Test status
Simulation time 21312447 ps
CPU time 1.23 seconds
Started May 16 02:01:24 PM PDT 24
Finished May 16 02:01:28 PM PDT 24
Peak memory 223524 kb
Host smart-1fe2bd1a-c36a-4bd2-ade3-85efd50b3422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559060898 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2559060898
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_sec_cm.4032957414
Short name T134
Test name
Test status
Simulation time 514220601 ps
CPU time 4.38 seconds
Started May 16 02:01:36 PM PDT 24
Finished May 16 02:01:42 PM PDT 24
Peak memory 234908 kb
Host smart-543dc865-7d64-411e-820e-f2dfe16409fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032957414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.4032957414
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2505734948
Short name T559
Test name
Test status
Simulation time 41694660 ps
CPU time 0.91 seconds
Started May 16 02:01:25 PM PDT 24
Finished May 16 02:01:27 PM PDT 24
Peak memory 206712 kb
Host smart-047bbe0e-4018-4c68-9427-6aa613602e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505734948 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2505734948
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3126554682
Short name T347
Test name
Test status
Simulation time 301939657 ps
CPU time 6.28 seconds
Started May 16 02:01:24 PM PDT 24
Finished May 16 02:01:32 PM PDT 24
Peak memory 214908 kb
Host smart-0a336550-e57c-448e-b0ff-610d80898a8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126554682 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3126554682
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3701769233
Short name T504
Test name
Test status
Simulation time 188968744339 ps
CPU time 1793.46 seconds
Started May 16 02:01:26 PM PDT 24
Finished May 16 02:31:22 PM PDT 24
Peak memory 226444 kb
Host smart-7359fe1f-a573-435c-a18f-d949abd29ed6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701769233 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3701769233
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2136932576
Short name T601
Test name
Test status
Simulation time 50499021 ps
CPU time 1.26 seconds
Started May 16 02:03:10 PM PDT 24
Finished May 16 02:03:14 PM PDT 24
Peak memory 215280 kb
Host smart-2f3b5edc-4887-46f7-aa2d-a0b5daad8633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136932576 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2136932576
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3257448378
Short name T324
Test name
Test status
Simulation time 33711690 ps
CPU time 1.01 seconds
Started May 16 02:03:13 PM PDT 24
Finished May 16 02:03:17 PM PDT 24
Peak memory 214304 kb
Host smart-7aae9e2f-bf9c-4868-a5d8-c64329488e58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257448378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3257448378
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.188610280
Short name T505
Test name
Test status
Simulation time 10660250 ps
CPU time 0.88 seconds
Started May 16 02:03:11 PM PDT 24
Finished May 16 02:03:14 PM PDT 24
Peak memory 215728 kb
Host smart-c3d78045-f8f9-49e5-9e65-90be5e49bce1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188610280 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.188610280
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.4115654710
Short name T694
Test name
Test status
Simulation time 54123042 ps
CPU time 1.02 seconds
Started May 16 02:03:11 PM PDT 24
Finished May 16 02:03:14 PM PDT 24
Peak memory 216700 kb
Host smart-7bd23b5f-0ad8-4b95-966e-9473ae7c678e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115654710 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.4115654710
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1176498744
Short name T669
Test name
Test status
Simulation time 26117218 ps
CPU time 1.36 seconds
Started May 16 02:03:12 PM PDT 24
Finished May 16 02:03:16 PM PDT 24
Peak memory 229208 kb
Host smart-a3485012-a21f-4a07-a023-e84f6788cd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176498744 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1176498744
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.544423362
Short name T779
Test name
Test status
Simulation time 48495612 ps
CPU time 1.43 seconds
Started May 16 02:03:11 PM PDT 24
Finished May 16 02:03:15 PM PDT 24
Peak memory 217996 kb
Host smart-70701d4e-bc44-4365-b755-a9909fa9efa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544423362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.544423362
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2814525455
Short name T154
Test name
Test status
Simulation time 38210808 ps
CPU time 0.93 seconds
Started May 16 02:03:18 PM PDT 24
Finished May 16 02:03:20 PM PDT 24
Peak memory 215180 kb
Host smart-6196dedd-65b9-4682-bff5-62bf0fe5a3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814525455 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2814525455
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3833660435
Short name T333
Test name
Test status
Simulation time 57926317 ps
CPU time 1.01 seconds
Started May 16 02:03:13 PM PDT 24
Finished May 16 02:03:17 PM PDT 24
Peak memory 214972 kb
Host smart-15f2b25f-8cab-4ee8-b2ea-6f18bba23f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833660435 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3833660435
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2635992620
Short name T621
Test name
Test status
Simulation time 1097648733 ps
CPU time 3.46 seconds
Started May 16 02:03:13 PM PDT 24
Finished May 16 02:03:20 PM PDT 24
Peak memory 216680 kb
Host smart-e44a936c-b285-4b5f-9993-7754f1a7b26e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635992620 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2635992620
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1041153386
Short name T666
Test name
Test status
Simulation time 214144919522 ps
CPU time 811 seconds
Started May 16 02:03:14 PM PDT 24
Finished May 16 02:16:48 PM PDT 24
Peak memory 223360 kb
Host smart-7a3093f6-dd5d-4e12-8fd0-3d263c1f674b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041153386 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1041153386
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3911689056
Short name T810
Test name
Test status
Simulation time 47717404 ps
CPU time 1.16 seconds
Started May 16 02:03:11 PM PDT 24
Finished May 16 02:03:15 PM PDT 24
Peak memory 215364 kb
Host smart-a3440613-d2b6-4350-accb-6221f16600b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911689056 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3911689056
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.925816989
Short name T438
Test name
Test status
Simulation time 18199275 ps
CPU time 0.95 seconds
Started May 16 02:03:12 PM PDT 24
Finished May 16 02:03:17 PM PDT 24
Peak memory 206244 kb
Host smart-16c4ad99-6878-47c7-bd18-64ca2d7cc839
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925816989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.925816989
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3224595420
Short name T430
Test name
Test status
Simulation time 29805972 ps
CPU time 0.9 seconds
Started May 16 02:03:11 PM PDT 24
Finished May 16 02:03:14 PM PDT 24
Peak memory 215128 kb
Host smart-2612470c-8910-448f-ae05-89172d9a44b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224595420 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3224595420
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3488914945
Short name T177
Test name
Test status
Simulation time 104286382 ps
CPU time 1.16 seconds
Started May 16 02:03:12 PM PDT 24
Finished May 16 02:03:15 PM PDT 24
Peak memory 216592 kb
Host smart-e321be6b-d9eb-4da2-ad40-ccbb3a842487
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488914945 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3488914945
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2876324372
Short name T481
Test name
Test status
Simulation time 46173262 ps
CPU time 1.13 seconds
Started May 16 02:03:13 PM PDT 24
Finished May 16 02:03:18 PM PDT 24
Peak memory 223360 kb
Host smart-f5c7a78d-bd5f-440e-a578-3f203d17bb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876324372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2876324372
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3304348258
Short name T617
Test name
Test status
Simulation time 107327285 ps
CPU time 1.67 seconds
Started May 16 02:03:10 PM PDT 24
Finished May 16 02:03:13 PM PDT 24
Peak memory 218092 kb
Host smart-3a35bd3f-2fd5-436a-8bfa-6244eb3c8433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304348258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3304348258
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1326745115
Short name T823
Test name
Test status
Simulation time 36568575 ps
CPU time 0.9 seconds
Started May 16 02:03:12 PM PDT 24
Finished May 16 02:03:15 PM PDT 24
Peak memory 215300 kb
Host smart-d914708c-8827-4b08-b937-363b7f1aff82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326745115 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1326745115
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2547967972
Short name T631
Test name
Test status
Simulation time 16806838 ps
CPU time 0.97 seconds
Started May 16 02:03:13 PM PDT 24
Finished May 16 02:03:17 PM PDT 24
Peak memory 214972 kb
Host smart-65f0ed7c-fced-4537-88df-3cf0779dabd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547967972 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2547967972
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.2767374041
Short name T216
Test name
Test status
Simulation time 525730378 ps
CPU time 5.6 seconds
Started May 16 02:03:14 PM PDT 24
Finished May 16 02:03:23 PM PDT 24
Peak memory 214980 kb
Host smart-f245f4c3-2bfb-475a-824c-1bfc63e76a3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767374041 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2767374041
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.4087878359
Short name T571
Test name
Test status
Simulation time 26179344412 ps
CPU time 631.99 seconds
Started May 16 02:03:10 PM PDT 24
Finished May 16 02:13:44 PM PDT 24
Peak memory 217108 kb
Host smart-79ab1aca-1f8c-4493-9c99-8597f22c9bfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087878359 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.4087878359
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1627929852
Short name T92
Test name
Test status
Simulation time 63546430 ps
CPU time 1.19 seconds
Started May 16 02:03:12 PM PDT 24
Finished May 16 02:03:16 PM PDT 24
Peak memory 215304 kb
Host smart-067bb84c-a90f-424c-af9b-bc70644244ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627929852 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1627929852
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.491250354
Short name T790
Test name
Test status
Simulation time 30635394 ps
CPU time 0.87 seconds
Started May 16 02:03:10 PM PDT 24
Finished May 16 02:03:13 PM PDT 24
Peak memory 214860 kb
Host smart-5339268a-da7a-4fa4-8fc9-788063f711e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491250354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.491250354
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.11720786
Short name T592
Test name
Test status
Simulation time 44557859 ps
CPU time 0.84 seconds
Started May 16 02:03:12 PM PDT 24
Finished May 16 02:03:16 PM PDT 24
Peak memory 216156 kb
Host smart-b50a44aa-940d-4f51-b856-2232c01333c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11720786 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.11720786
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.64397600
Short name T32
Test name
Test status
Simulation time 82174902 ps
CPU time 1.04 seconds
Started May 16 02:03:09 PM PDT 24
Finished May 16 02:03:12 PM PDT 24
Peak memory 216744 kb
Host smart-03093132-e69b-4bd9-a186-15604c707d23
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64397600 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_dis
able_auto_req_mode.64397600
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.97528689
Short name T460
Test name
Test status
Simulation time 23897628 ps
CPU time 0.99 seconds
Started May 16 02:03:11 PM PDT 24
Finished May 16 02:03:14 PM PDT 24
Peak memory 219112 kb
Host smart-a339157f-5ebf-4ba5-bb43-4d8742008815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97528689 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.97528689
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.728582620
Short name T678
Test name
Test status
Simulation time 65852806 ps
CPU time 1.23 seconds
Started May 16 02:03:13 PM PDT 24
Finished May 16 02:03:18 PM PDT 24
Peak memory 218104 kb
Host smart-b39bf600-27d0-4085-9ed8-9661ae53902a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728582620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.728582620
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2115124406
Short name T767
Test name
Test status
Simulation time 27281951 ps
CPU time 1.01 seconds
Started May 16 02:03:11 PM PDT 24
Finished May 16 02:03:14 PM PDT 24
Peak memory 223544 kb
Host smart-e961c4d7-32f5-439e-93c2-5d7700580d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115124406 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2115124406
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.557722997
Short name T547
Test name
Test status
Simulation time 18063564 ps
CPU time 1.02 seconds
Started May 16 02:03:15 PM PDT 24
Finished May 16 02:03:18 PM PDT 24
Peak memory 214976 kb
Host smart-0b35f27a-2dd1-4e4e-a1b5-d4f48f7cf804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557722997 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.557722997
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2096973045
Short name T742
Test name
Test status
Simulation time 550586159 ps
CPU time 3.66 seconds
Started May 16 02:03:09 PM PDT 24
Finished May 16 02:03:14 PM PDT 24
Peak memory 216604 kb
Host smart-783cc230-8a28-4432-b0ac-60b5a757c002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096973045 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2096973045
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3654644156
Short name T204
Test name
Test status
Simulation time 100911116534 ps
CPU time 2352.2 seconds
Started May 16 02:03:13 PM PDT 24
Finished May 16 02:42:29 PM PDT 24
Peak memory 227672 kb
Host smart-f2bd3485-4b48-45c5-815b-6412502ba621
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654644156 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3654644156
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.4000911140
Short name T196
Test name
Test status
Simulation time 27939842 ps
CPU time 1.29 seconds
Started May 16 02:03:20 PM PDT 24
Finished May 16 02:03:24 PM PDT 24
Peak memory 215200 kb
Host smart-90809395-b165-45e8-8ad8-d63852a85408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000911140 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.4000911140
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2043665007
Short name T512
Test name
Test status
Simulation time 14547581 ps
CPU time 0.89 seconds
Started May 16 02:03:22 PM PDT 24
Finished May 16 02:03:27 PM PDT 24
Peak memory 206184 kb
Host smart-0e0d0168-5096-4ddb-b105-8ee61201db08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043665007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2043665007
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.719042211
Short name T581
Test name
Test status
Simulation time 26140760 ps
CPU time 0.83 seconds
Started May 16 02:03:26 PM PDT 24
Finished May 16 02:03:30 PM PDT 24
Peak memory 215092 kb
Host smart-10a61486-8fab-4889-bee9-5a48ec70a420
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719042211 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.719042211
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3902575222
Short name T526
Test name
Test status
Simulation time 96432241 ps
CPU time 1.1 seconds
Started May 16 02:03:21 PM PDT 24
Finished May 16 02:03:25 PM PDT 24
Peak memory 217980 kb
Host smart-1b091039-f8e6-4971-a9a7-d0d58868d14e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902575222 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3902575222
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1210667815
Short name T478
Test name
Test status
Simulation time 140559059 ps
CPU time 1.04 seconds
Started May 16 02:03:19 PM PDT 24
Finished May 16 02:03:22 PM PDT 24
Peak memory 218480 kb
Host smart-bd3babed-4efd-47f9-9d8e-cc042928fe56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210667815 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1210667815
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2660464266
Short name T573
Test name
Test status
Simulation time 110434436 ps
CPU time 2.58 seconds
Started May 16 02:03:18 PM PDT 24
Finished May 16 02:03:22 PM PDT 24
Peak memory 219596 kb
Host smart-eeea3271-8ac0-4feb-9331-daee7d9a4942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660464266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2660464266
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3684619565
Short name T97
Test name
Test status
Simulation time 40069609 ps
CPU time 0.9 seconds
Started May 16 02:03:24 PM PDT 24
Finished May 16 02:03:28 PM PDT 24
Peak memory 214984 kb
Host smart-34d8838e-9c7c-48cf-b207-37bdae7c159b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684619565 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3684619565
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3223386345
Short name T491
Test name
Test status
Simulation time 45173442 ps
CPU time 0.92 seconds
Started May 16 02:03:09 PM PDT 24
Finished May 16 02:03:12 PM PDT 24
Peak memory 214960 kb
Host smart-1c936227-abe3-4a7b-9014-2ef4d8f9d030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223386345 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3223386345
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1381077990
Short name T353
Test name
Test status
Simulation time 215987403 ps
CPU time 2.92 seconds
Started May 16 02:03:18 PM PDT 24
Finished May 16 02:03:22 PM PDT 24
Peak memory 216848 kb
Host smart-6352859b-41b2-46ec-8b01-c5b467c59e79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381077990 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1381077990
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3001074568
Short name T541
Test name
Test status
Simulation time 68536072580 ps
CPU time 559.83 seconds
Started May 16 02:03:11 PM PDT 24
Finished May 16 02:12:33 PM PDT 24
Peak memory 223392 kb
Host smart-303142d5-1af4-4a14-8303-f55c0e3ef321
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001074568 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3001074568
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1954105452
Short name T166
Test name
Test status
Simulation time 24323014 ps
CPU time 1.2 seconds
Started May 16 02:03:21 PM PDT 24
Finished May 16 02:03:25 PM PDT 24
Peak memory 215320 kb
Host smart-c1be3903-79ad-41be-ad2a-f48547f12190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954105452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1954105452
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1618802296
Short name T684
Test name
Test status
Simulation time 17885649 ps
CPU time 0.84 seconds
Started May 16 02:03:21 PM PDT 24
Finished May 16 02:03:25 PM PDT 24
Peak memory 206500 kb
Host smart-8012ee5b-a7b6-4d5d-a350-39c34094dadd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618802296 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1618802296
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3304734333
Short name T492
Test name
Test status
Simulation time 28361409 ps
CPU time 1.13 seconds
Started May 16 02:03:19 PM PDT 24
Finished May 16 02:03:23 PM PDT 24
Peak memory 217852 kb
Host smart-fe7c7041-8c37-4df3-b78e-8be56edd1751
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304734333 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3304734333
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.1574634601
Short name T498
Test name
Test status
Simulation time 23613357 ps
CPU time 1 seconds
Started May 16 02:03:26 PM PDT 24
Finished May 16 02:03:30 PM PDT 24
Peak memory 215112 kb
Host smart-5e881750-a69c-4c37-8fdc-ebff909b6be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574634601 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1574634601
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1236376053
Short name T420
Test name
Test status
Simulation time 47502860 ps
CPU time 1.31 seconds
Started May 16 02:03:22 PM PDT 24
Finished May 16 02:03:27 PM PDT 24
Peak memory 218172 kb
Host smart-b60357f0-43e4-467f-b54b-60c846d8b3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236376053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1236376053
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1948666877
Short name T109
Test name
Test status
Simulation time 78024753 ps
CPU time 0.82 seconds
Started May 16 02:03:20 PM PDT 24
Finished May 16 02:03:23 PM PDT 24
Peak memory 215112 kb
Host smart-98743a70-34b4-4b3a-ac9c-e32ecdaa95d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948666877 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1948666877
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1902130065
Short name T672
Test name
Test status
Simulation time 29437014 ps
CPU time 0.94 seconds
Started May 16 02:03:21 PM PDT 24
Finished May 16 02:03:26 PM PDT 24
Peak memory 214968 kb
Host smart-c9585959-1d30-44d8-9598-41be83676b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902130065 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1902130065
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2675199446
Short name T453
Test name
Test status
Simulation time 342423391 ps
CPU time 4.04 seconds
Started May 16 02:03:27 PM PDT 24
Finished May 16 02:03:33 PM PDT 24
Peak memory 214920 kb
Host smart-a1c49346-b79c-4d50-874e-862abe5cc21a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675199446 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2675199446
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.292628058
Short name T728
Test name
Test status
Simulation time 15822169752 ps
CPU time 348.37 seconds
Started May 16 02:03:26 PM PDT 24
Finished May 16 02:09:17 PM PDT 24
Peak memory 217152 kb
Host smart-505f17a9-ae7f-4ab0-b826-91aa58a831d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292628058 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.292628058
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3641348238
Short name T26
Test name
Test status
Simulation time 122100238 ps
CPU time 1.35 seconds
Started May 16 02:03:20 PM PDT 24
Finished May 16 02:03:24 PM PDT 24
Peak memory 215240 kb
Host smart-e07c24a4-b3b3-43b4-a118-9f170de06bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641348238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3641348238
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.359779689
Short name T363
Test name
Test status
Simulation time 10442368 ps
CPU time 0.81 seconds
Started May 16 02:03:22 PM PDT 24
Finished May 16 02:03:27 PM PDT 24
Peak memory 206052 kb
Host smart-d8c74d4b-15b7-4e6b-b55f-d30b51ca4481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359779689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.359779689
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1750011639
Short name T389
Test name
Test status
Simulation time 39399431 ps
CPU time 0.88 seconds
Started May 16 02:03:20 PM PDT 24
Finished May 16 02:03:24 PM PDT 24
Peak memory 216164 kb
Host smart-c422881f-c073-4e7a-8d6b-dc2b6efd0f0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750011639 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1750011639
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.29402953
Short name T46
Test name
Test status
Simulation time 149464121 ps
CPU time 1.03 seconds
Started May 16 02:03:20 PM PDT 24
Finished May 16 02:03:23 PM PDT 24
Peak memory 216508 kb
Host smart-309e2578-e3ea-4335-82b9-b3eb987d40ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29402953 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_dis
able_auto_req_mode.29402953
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1117381920
Short name T646
Test name
Test status
Simulation time 20852051 ps
CPU time 1.14 seconds
Started May 16 02:03:24 PM PDT 24
Finished May 16 02:03:29 PM PDT 24
Peak memory 219132 kb
Host smart-7af4623e-627e-42a2-a212-d4e094a2a12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117381920 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1117381920
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3963837377
Short name T355
Test name
Test status
Simulation time 83576290 ps
CPU time 1.19 seconds
Started May 16 02:03:23 PM PDT 24
Finished May 16 02:03:28 PM PDT 24
Peak memory 216736 kb
Host smart-a1870686-1c77-4465-968f-203f1526d0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963837377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3963837377
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2213352055
Short name T170
Test name
Test status
Simulation time 37318715 ps
CPU time 0.96 seconds
Started May 16 02:03:23 PM PDT 24
Finished May 16 02:03:27 PM PDT 24
Peak memory 215360 kb
Host smart-d6fced51-d850-46ef-a511-431e1a288b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213352055 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2213352055
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2017728614
Short name T792
Test name
Test status
Simulation time 45435537 ps
CPU time 0.92 seconds
Started May 16 02:03:22 PM PDT 24
Finished May 16 02:03:26 PM PDT 24
Peak memory 214980 kb
Host smart-35c06477-75cc-41e4-85cc-1f886d1d25a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017728614 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2017728614
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.595957173
Short name T495
Test name
Test status
Simulation time 313788161 ps
CPU time 2.78 seconds
Started May 16 02:03:20 PM PDT 24
Finished May 16 02:03:25 PM PDT 24
Peak memory 216624 kb
Host smart-53342617-39e0-4268-bfd5-8b3ba4e7452b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595957173 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.595957173
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1772038231
Short name T496
Test name
Test status
Simulation time 82797254214 ps
CPU time 1018.37 seconds
Started May 16 02:03:19 PM PDT 24
Finished May 16 02:20:19 PM PDT 24
Peak memory 223012 kb
Host smart-21ff435a-2b03-48e4-a295-63cfe5353ccb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772038231 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1772038231
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1980204774
Short name T168
Test name
Test status
Simulation time 28793097 ps
CPU time 1.33 seconds
Started May 16 02:03:25 PM PDT 24
Finished May 16 02:03:29 PM PDT 24
Peak memory 215364 kb
Host smart-ae2b30fa-a10b-4393-8603-549a9f914ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980204774 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1980204774
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3525878723
Short name T850
Test name
Test status
Simulation time 61264666 ps
CPU time 0.95 seconds
Started May 16 02:03:22 PM PDT 24
Finished May 16 02:03:27 PM PDT 24
Peak memory 206292 kb
Host smart-dc7612a0-f689-4c8c-ba8b-2cb307728829
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525878723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3525878723
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.376301013
Short name T527
Test name
Test status
Simulation time 14196876 ps
CPU time 0.93 seconds
Started May 16 02:03:20 PM PDT 24
Finished May 16 02:03:24 PM PDT 24
Peak memory 216152 kb
Host smart-7d4fc1e3-cdde-485d-8d8e-5e81a55fda87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376301013 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.376301013
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1855024233
Short name T246
Test name
Test status
Simulation time 33724318 ps
CPU time 1.19 seconds
Started May 16 02:03:25 PM PDT 24
Finished May 16 02:03:29 PM PDT 24
Peak memory 218004 kb
Host smart-cacfc03d-ba2c-4003-81f4-7a574e86373b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855024233 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1855024233
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.104328497
Short name T552
Test name
Test status
Simulation time 20186578 ps
CPU time 1.08 seconds
Started May 16 02:03:23 PM PDT 24
Finished May 16 02:03:28 PM PDT 24
Peak memory 219272 kb
Host smart-6a697619-80f1-4b01-a095-3e2e94b4f583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104328497 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.104328497
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3875195129
Short name T447
Test name
Test status
Simulation time 342789215 ps
CPU time 2.03 seconds
Started May 16 02:03:20 PM PDT 24
Finished May 16 02:03:25 PM PDT 24
Peak memory 218380 kb
Host smart-32864e14-5d79-4225-970a-be93bdfea4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875195129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3875195129
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1981902307
Short name T735
Test name
Test status
Simulation time 43882028 ps
CPU time 0.87 seconds
Started May 16 02:03:22 PM PDT 24
Finished May 16 02:03:27 PM PDT 24
Peak memory 215136 kb
Host smart-0041c67b-b38a-4524-9426-d424684b1959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981902307 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1981902307
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.539058336
Short name T533
Test name
Test status
Simulation time 41821636 ps
CPU time 0.87 seconds
Started May 16 02:03:20 PM PDT 24
Finished May 16 02:03:25 PM PDT 24
Peak memory 214980 kb
Host smart-30de9399-94a5-46a7-8588-fa49bbf5b569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539058336 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.539058336
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1246753471
Short name T572
Test name
Test status
Simulation time 2074421332 ps
CPU time 4.5 seconds
Started May 16 02:03:22 PM PDT 24
Finished May 16 02:03:30 PM PDT 24
Peak memory 214884 kb
Host smart-763b6932-4af0-493f-9db9-ef41c251737c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246753471 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1246753471
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.692933239
Short name T608
Test name
Test status
Simulation time 529898828556 ps
CPU time 816.79 seconds
Started May 16 02:03:20 PM PDT 24
Finished May 16 02:17:00 PM PDT 24
Peak memory 221484 kb
Host smart-8964aad3-3e34-49a1-8fca-38b78f05d729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692933239 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.692933239
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3672208468
Short name T801
Test name
Test status
Simulation time 58843545 ps
CPU time 1.33 seconds
Started May 16 02:03:21 PM PDT 24
Finished May 16 02:03:26 PM PDT 24
Peak memory 215316 kb
Host smart-08ace209-2e5f-4f79-8ed6-09515e10167c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672208468 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3672208468
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3472949836
Short name T462
Test name
Test status
Simulation time 15277882 ps
CPU time 0.94 seconds
Started May 16 02:03:22 PM PDT 24
Finished May 16 02:03:26 PM PDT 24
Peak memory 206224 kb
Host smart-b08bcc6a-770a-4c4a-98ab-48d64f66d36d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472949836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3472949836
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1241502405
Short name T174
Test name
Test status
Simulation time 11835340 ps
CPU time 0.94 seconds
Started May 16 02:03:25 PM PDT 24
Finished May 16 02:03:29 PM PDT 24
Peak memory 216188 kb
Host smart-49667c5a-ca2f-4827-9e65-34401d890e54
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241502405 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1241502405
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_genbits.3018221126
Short name T623
Test name
Test status
Simulation time 106906565 ps
CPU time 1.25 seconds
Started May 16 02:03:24 PM PDT 24
Finished May 16 02:03:29 PM PDT 24
Peak memory 217940 kb
Host smart-408c290c-856b-4d3e-9e33-a4fbd51c66bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018221126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3018221126
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_smoke.2063219851
Short name T143
Test name
Test status
Simulation time 17905358 ps
CPU time 0.97 seconds
Started May 16 02:03:23 PM PDT 24
Finished May 16 02:03:28 PM PDT 24
Peak memory 214960 kb
Host smart-5a4e1616-4960-4115-a469-c01a1e7c2bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063219851 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2063219851
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1527829058
Short name T249
Test name
Test status
Simulation time 263853126 ps
CPU time 4.01 seconds
Started May 16 02:03:22 PM PDT 24
Finished May 16 02:03:29 PM PDT 24
Peak memory 217868 kb
Host smart-6281ef2b-9c6f-481b-98b0-f1d409e0079b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527829058 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1527829058
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.166953102
Short name T296
Test name
Test status
Simulation time 96748535599 ps
CPU time 2479.62 seconds
Started May 16 02:03:23 PM PDT 24
Finished May 16 02:44:46 PM PDT 24
Peak memory 231412 kb
Host smart-8db3d625-80b8-4905-a49a-c9b76e8fe1b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166953102 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.166953102
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.169671158
Short name T751
Test name
Test status
Simulation time 77117817 ps
CPU time 1.22 seconds
Started May 16 02:03:36 PM PDT 24
Finished May 16 02:03:39 PM PDT 24
Peak memory 215364 kb
Host smart-89722113-6fca-4095-b833-2d22256964d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169671158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.169671158
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1632933645
Short name T374
Test name
Test status
Simulation time 23151284 ps
CPU time 0.9 seconds
Started May 16 02:03:35 PM PDT 24
Finished May 16 02:03:39 PM PDT 24
Peak memory 206276 kb
Host smart-4fb6fabf-b24b-4a5a-8ac7-0c04edfb6920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632933645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1632933645
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3040139464
Short name T178
Test name
Test status
Simulation time 36416590 ps
CPU time 1.3 seconds
Started May 16 02:03:30 PM PDT 24
Finished May 16 02:03:32 PM PDT 24
Peak memory 216580 kb
Host smart-22676c52-d52a-4831-a423-d4aed38bd766
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040139464 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3040139464
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.2025257142
Short name T53
Test name
Test status
Simulation time 34318198 ps
CPU time 1.02 seconds
Started May 16 02:03:31 PM PDT 24
Finished May 16 02:03:33 PM PDT 24
Peak memory 229256 kb
Host smart-fa4bfb5d-f36b-4524-9412-b31cbbaf1a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025257142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2025257142
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.119876099
Short name T648
Test name
Test status
Simulation time 71496490 ps
CPU time 2.35 seconds
Started May 16 02:03:21 PM PDT 24
Finished May 16 02:03:27 PM PDT 24
Peak memory 218408 kb
Host smart-d4012d3b-96bb-4dcd-a349-d16c405bd875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119876099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.119876099
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3070568081
Short name T132
Test name
Test status
Simulation time 29459267 ps
CPU time 1.08 seconds
Started May 16 02:03:22 PM PDT 24
Finished May 16 02:03:27 PM PDT 24
Peak memory 223568 kb
Host smart-3b4d5c60-a201-4887-814f-baf6e996e9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070568081 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3070568081
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1247265725
Short name T827
Test name
Test status
Simulation time 27800003 ps
CPU time 0.95 seconds
Started May 16 02:03:24 PM PDT 24
Finished May 16 02:03:29 PM PDT 24
Peak memory 214896 kb
Host smart-f7a268ef-c574-486b-a3e2-668d9b7cb41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247265725 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1247265725
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.105858741
Short name T576
Test name
Test status
Simulation time 298975326 ps
CPU time 5.86 seconds
Started May 16 02:03:22 PM PDT 24
Finished May 16 02:03:32 PM PDT 24
Peak memory 216452 kb
Host smart-82f0c5e6-4be8-4377-9966-016db6bde60e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105858741 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.105858741
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2381670284
Short name T208
Test name
Test status
Simulation time 26385148386 ps
CPU time 285.22 seconds
Started May 16 02:03:19 PM PDT 24
Finished May 16 02:08:06 PM PDT 24
Peak memory 223468 kb
Host smart-0f06f692-6a7a-4af7-9084-ab42b74c968a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381670284 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2381670284
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2212557559
Short name T277
Test name
Test status
Simulation time 24925577 ps
CPU time 1.29 seconds
Started May 16 02:03:31 PM PDT 24
Finished May 16 02:03:35 PM PDT 24
Peak memory 215340 kb
Host smart-8401f294-dbc2-4c87-8d34-eb8a72663a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212557559 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2212557559
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2938891537
Short name T325
Test name
Test status
Simulation time 55403054 ps
CPU time 0.89 seconds
Started May 16 02:03:35 PM PDT 24
Finished May 16 02:03:38 PM PDT 24
Peak memory 214504 kb
Host smart-a9e50edb-5f2d-48ce-9e5f-13e8df03ce24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938891537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2938891537
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1411425044
Short name T609
Test name
Test status
Simulation time 16596913 ps
CPU time 0.86 seconds
Started May 16 02:03:31 PM PDT 24
Finished May 16 02:03:33 PM PDT 24
Peak memory 215180 kb
Host smart-454d6634-51ae-4e33-959b-955af5cc3dbf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411425044 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1411425044
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.4120424924
Short name T620
Test name
Test status
Simulation time 34144937 ps
CPU time 1.1 seconds
Started May 16 02:03:36 PM PDT 24
Finished May 16 02:03:39 PM PDT 24
Peak memory 216708 kb
Host smart-0946e292-c1c0-4396-b46b-f65f3bc31cda
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120424924 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.4120424924
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3905498852
Short name T426
Test name
Test status
Simulation time 91788054 ps
CPU time 1.04 seconds
Started May 16 02:03:35 PM PDT 24
Finished May 16 02:03:38 PM PDT 24
Peak memory 223392 kb
Host smart-f57b14f3-2631-4f2c-89f1-871c488493d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905498852 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3905498852
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1569031885
Short name T282
Test name
Test status
Simulation time 41868808 ps
CPU time 1.52 seconds
Started May 16 02:03:32 PM PDT 24
Finished May 16 02:03:36 PM PDT 24
Peak memory 218040 kb
Host smart-c6875e4b-556c-4dcc-b989-8e68a9d9339d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569031885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1569031885
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.969633518
Short name T108
Test name
Test status
Simulation time 21310440 ps
CPU time 1.09 seconds
Started May 16 02:03:30 PM PDT 24
Finished May 16 02:03:33 PM PDT 24
Peak memory 215428 kb
Host smart-e5dc42a6-1855-402e-809c-4a72abfcca6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969633518 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.969633518
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.380416637
Short name T345
Test name
Test status
Simulation time 42822322 ps
CPU time 0.97 seconds
Started May 16 02:03:36 PM PDT 24
Finished May 16 02:03:40 PM PDT 24
Peak memory 214972 kb
Host smart-1a271a83-9cfd-4b21-ab0c-70439eac1bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380416637 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.380416637
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2467373764
Short name T319
Test name
Test status
Simulation time 749217012 ps
CPU time 4.88 seconds
Started May 16 02:03:35 PM PDT 24
Finished May 16 02:03:42 PM PDT 24
Peak memory 219488 kb
Host smart-10615f76-5485-4eb9-8c0a-dc52c80f2e00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467373764 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2467373764
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3470230888
Short name T203
Test name
Test status
Simulation time 87013544410 ps
CPU time 530.68 seconds
Started May 16 02:03:30 PM PDT 24
Finished May 16 02:12:22 PM PDT 24
Peak memory 223368 kb
Host smart-110e3ced-dbfe-4bb3-8830-2204d0a0a86b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470230888 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3470230888
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2285368742
Short name T813
Test name
Test status
Simulation time 154589648 ps
CPU time 1.4 seconds
Started May 16 02:01:34 PM PDT 24
Finished May 16 02:01:37 PM PDT 24
Peak memory 215380 kb
Host smart-c50fcc6a-3869-457c-a0ad-ac646d0b4e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285368742 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2285368742
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1535976513
Short name T129
Test name
Test status
Simulation time 19141268 ps
CPU time 0.92 seconds
Started May 16 02:01:37 PM PDT 24
Finished May 16 02:01:40 PM PDT 24
Peak memory 206260 kb
Host smart-f8e6c770-bbb8-4e71-977d-22d1ebd3ef47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535976513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1535976513
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3525671243
Short name T410
Test name
Test status
Simulation time 23201476 ps
CPU time 0.93 seconds
Started May 16 02:01:34 PM PDT 24
Finished May 16 02:01:36 PM PDT 24
Peak memory 216012 kb
Host smart-ff348d19-3e26-43a6-8213-e8ef245afb19
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525671243 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3525671243
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3489675618
Short name T198
Test name
Test status
Simulation time 195616105 ps
CPU time 1.08 seconds
Started May 16 02:01:36 PM PDT 24
Finished May 16 02:01:39 PM PDT 24
Peak memory 219276 kb
Host smart-02f4eedf-5d2a-4514-b7fd-1643eda42be5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489675618 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3489675618
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3876651496
Short name T68
Test name
Test status
Simulation time 22111543 ps
CPU time 1.07 seconds
Started May 16 02:01:36 PM PDT 24
Finished May 16 02:01:38 PM PDT 24
Peak memory 223456 kb
Host smart-13c245e3-a60a-461e-a34d-20daba7bd7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876651496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3876651496
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1705795825
Short name T153
Test name
Test status
Simulation time 66041467 ps
CPU time 1.6 seconds
Started May 16 02:01:35 PM PDT 24
Finished May 16 02:01:39 PM PDT 24
Peak memory 218408 kb
Host smart-cf8ac927-1d1a-4895-b853-728ad776a15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705795825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1705795825
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1464122889
Short name T818
Test name
Test status
Simulation time 23141523 ps
CPU time 1.09 seconds
Started May 16 02:01:34 PM PDT 24
Finished May 16 02:01:36 PM PDT 24
Peak memory 215032 kb
Host smart-316c5a3a-4355-4be7-bc41-b5b43e336502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464122889 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1464122889
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2274781092
Short name T17
Test name
Test status
Simulation time 4569461032 ps
CPU time 8.23 seconds
Started May 16 02:01:33 PM PDT 24
Finished May 16 02:01:43 PM PDT 24
Peak memory 241108 kb
Host smart-7b231582-1c54-431a-b2a0-031c9e10f944
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274781092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2274781092
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2849375714
Short name T375
Test name
Test status
Simulation time 53585760 ps
CPU time 0.99 seconds
Started May 16 02:01:35 PM PDT 24
Finished May 16 02:01:38 PM PDT 24
Peak memory 214992 kb
Host smart-bca3feba-bcbc-470e-a9bc-34c4b03b0247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849375714 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2849375714
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1743279742
Short name T100
Test name
Test status
Simulation time 363373710 ps
CPU time 2.48 seconds
Started May 16 02:01:34 PM PDT 24
Finished May 16 02:01:38 PM PDT 24
Peak memory 216528 kb
Host smart-4424aec0-92f1-4f5a-82c1-2b4c2e668148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743279742 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1743279742
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2732007761
Short name T188
Test name
Test status
Simulation time 17650724466 ps
CPU time 449.01 seconds
Started May 16 02:01:37 PM PDT 24
Finished May 16 02:09:08 PM PDT 24
Peak memory 218652 kb
Host smart-b8cedc61-1a51-4986-881a-239afeace4e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732007761 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2732007761
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1066160666
Short name T199
Test name
Test status
Simulation time 181981945 ps
CPU time 1.3 seconds
Started May 16 02:03:33 PM PDT 24
Finished May 16 02:03:36 PM PDT 24
Peak memory 215352 kb
Host smart-2ff6aa6e-48da-47ce-8dd8-825b2a4c374a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066160666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1066160666
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2451319607
Short name T521
Test name
Test status
Simulation time 49206898 ps
CPU time 0.88 seconds
Started May 16 02:03:33 PM PDT 24
Finished May 16 02:03:36 PM PDT 24
Peak memory 214420 kb
Host smart-1c9ccda4-47f1-43a1-a417-68b02d20a799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451319607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2451319607
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3231418076
Short name T340
Test name
Test status
Simulation time 22494791 ps
CPU time 0.84 seconds
Started May 16 02:03:31 PM PDT 24
Finished May 16 02:03:34 PM PDT 24
Peak memory 215684 kb
Host smart-9fc5fb4f-3372-4b84-a632-a0ec6b970221
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231418076 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3231418076
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_err.1556758299
Short name T7
Test name
Test status
Simulation time 20779462 ps
CPU time 1.18 seconds
Started May 16 02:03:35 PM PDT 24
Finished May 16 02:03:38 PM PDT 24
Peak memory 219432 kb
Host smart-8c24af0d-7727-46b4-8ade-8b60abcab55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556758299 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1556758299
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3520211667
Short name T515
Test name
Test status
Simulation time 44471851 ps
CPU time 1.8 seconds
Started May 16 02:03:34 PM PDT 24
Finished May 16 02:03:39 PM PDT 24
Peak memory 218020 kb
Host smart-9dc7bef3-e3fb-4174-be53-9009ae44e93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520211667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3520211667
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_smoke.1038287164
Short name T323
Test name
Test status
Simulation time 25951628 ps
CPU time 0.91 seconds
Started May 16 02:03:32 PM PDT 24
Finished May 16 02:03:36 PM PDT 24
Peak memory 214932 kb
Host smart-007af5dd-9005-4ff8-b6da-1ca8d30777cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038287164 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1038287164
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.347454356
Short name T326
Test name
Test status
Simulation time 179405177 ps
CPU time 2.45 seconds
Started May 16 02:03:31 PM PDT 24
Finished May 16 02:03:36 PM PDT 24
Peak memory 216552 kb
Host smart-6bb5d683-0baa-45af-84fd-9c37dc034c46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347454356 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.347454356
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.878696285
Short name T744
Test name
Test status
Simulation time 63007548229 ps
CPU time 1425.06 seconds
Started May 16 02:03:31 PM PDT 24
Finished May 16 02:27:18 PM PDT 24
Peak memory 221792 kb
Host smart-85370109-6075-4cf0-8d7b-b443daa922ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878696285 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.878696285
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2536075060
Short name T619
Test name
Test status
Simulation time 26212831 ps
CPU time 1.19 seconds
Started May 16 02:03:33 PM PDT 24
Finished May 16 02:03:36 PM PDT 24
Peak memory 215328 kb
Host smart-1c7e3b45-a54c-4535-84eb-a54c8d904d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536075060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2536075060
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.232049242
Short name T354
Test name
Test status
Simulation time 24525191 ps
CPU time 1.08 seconds
Started May 16 02:03:37 PM PDT 24
Finished May 16 02:03:40 PM PDT 24
Peak memory 206240 kb
Host smart-772974c8-7894-4c7d-aea7-73753f7cd22c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232049242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.232049242
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.198037681
Short name T734
Test name
Test status
Simulation time 36836911 ps
CPU time 0.88 seconds
Started May 16 02:03:31 PM PDT 24
Finished May 16 02:03:35 PM PDT 24
Peak memory 216156 kb
Host smart-d5815385-c2e8-4514-a423-7665d0135295
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198037681 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.198037681
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_err.1930010230
Short name T45
Test name
Test status
Simulation time 43895173 ps
CPU time 0.99 seconds
Started May 16 02:03:32 PM PDT 24
Finished May 16 02:03:35 PM PDT 24
Peak memory 219328 kb
Host smart-7a5ff722-a484-40ff-bc0f-552aa03c84b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930010230 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1930010230
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2651944810
Short name T317
Test name
Test status
Simulation time 47041286 ps
CPU time 1.2 seconds
Started May 16 02:03:31 PM PDT 24
Finished May 16 02:03:35 PM PDT 24
Peak memory 217796 kb
Host smart-bef4f5d3-8b90-4d39-9685-ee00718f4ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651944810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2651944810
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1906030006
Short name T437
Test name
Test status
Simulation time 22039997 ps
CPU time 1.02 seconds
Started May 16 02:03:36 PM PDT 24
Finished May 16 02:03:39 PM PDT 24
Peak memory 215360 kb
Host smart-d1d90e43-4e41-4313-ad8f-aab7224b1d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906030006 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1906030006
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.596386653
Short name T681
Test name
Test status
Simulation time 131723926 ps
CPU time 0.92 seconds
Started May 16 02:03:35 PM PDT 24
Finished May 16 02:03:38 PM PDT 24
Peak memory 214872 kb
Host smart-110e8c6c-eafc-4f2d-822d-cf0723d15814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596386653 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.596386653
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3311884685
Short name T338
Test name
Test status
Simulation time 732308323 ps
CPU time 1.53 seconds
Started May 16 02:03:29 PM PDT 24
Finished May 16 02:03:32 PM PDT 24
Peak memory 215048 kb
Host smart-0298a91e-effc-41b8-8912-a1316d79716b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311884685 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3311884685
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.952932889
Short name T507
Test name
Test status
Simulation time 337255323975 ps
CPU time 2183.18 seconds
Started May 16 02:03:35 PM PDT 24
Finished May 16 02:40:01 PM PDT 24
Peak memory 230052 kb
Host smart-abb6a486-b915-427b-b780-c58132241844
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952932889 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.952932889
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1897611497
Short name T626
Test name
Test status
Simulation time 29168753 ps
CPU time 1.25 seconds
Started May 16 02:03:47 PM PDT 24
Finished May 16 02:03:49 PM PDT 24
Peak memory 215468 kb
Host smart-46392bc9-9356-46d4-b2c0-56acb79a51de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897611497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1897611497
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.557611478
Short name T130
Test name
Test status
Simulation time 29842220 ps
CPU time 0.98 seconds
Started May 16 02:03:47 PM PDT 24
Finished May 16 02:03:49 PM PDT 24
Peak memory 214440 kb
Host smart-951a777b-f5cc-41cf-9fc2-ebd483aa1996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557611478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.557611478
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3713882835
Short name T200
Test name
Test status
Simulation time 11777275 ps
CPU time 0.91 seconds
Started May 16 02:03:47 PM PDT 24
Finished May 16 02:03:49 PM PDT 24
Peak memory 215336 kb
Host smart-bbd2cd0b-3c61-45a8-bd20-8e86065e2b06
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713882835 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3713882835
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2074382596
Short name T789
Test name
Test status
Simulation time 23310015 ps
CPU time 1.03 seconds
Started May 16 02:03:53 PM PDT 24
Finished May 16 02:03:56 PM PDT 24
Peak memory 216472 kb
Host smart-1906cae3-e5d2-4031-9597-11169f5261f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074382596 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2074382596
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1253854101
Short name T37
Test name
Test status
Simulation time 58906925 ps
CPU time 0.89 seconds
Started May 16 02:03:41 PM PDT 24
Finished May 16 02:03:42 PM PDT 24
Peak memory 219080 kb
Host smart-7b0e2c44-9973-41be-855b-6ca3c5047485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253854101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1253854101
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1033394894
Short name T401
Test name
Test status
Simulation time 45198440 ps
CPU time 1.57 seconds
Started May 16 02:03:36 PM PDT 24
Finished May 16 02:03:40 PM PDT 24
Peak memory 217900 kb
Host smart-865f5882-a8d4-4a9a-b513-ef2aac246018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033394894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1033394894
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1539092441
Short name T643
Test name
Test status
Simulation time 36482690 ps
CPU time 0.88 seconds
Started May 16 02:03:47 PM PDT 24
Finished May 16 02:03:49 PM PDT 24
Peak memory 215084 kb
Host smart-c056a68d-0826-49da-8473-55dc08742109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539092441 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1539092441
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2399503555
Short name T634
Test name
Test status
Simulation time 59637094 ps
CPU time 0.95 seconds
Started May 16 02:03:33 PM PDT 24
Finished May 16 02:03:37 PM PDT 24
Peak memory 214952 kb
Host smart-3eae5507-0f8f-413a-b384-f85a82ffb382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399503555 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2399503555
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3254801385
Short name T582
Test name
Test status
Simulation time 504643985 ps
CPU time 5.06 seconds
Started May 16 02:03:32 PM PDT 24
Finished May 16 02:03:39 PM PDT 24
Peak memory 216676 kb
Host smart-00bddbfc-ffe4-4ab4-b380-765db9658500
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254801385 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3254801385
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2465099581
Short name T701
Test name
Test status
Simulation time 22202087885 ps
CPU time 475.55 seconds
Started May 16 02:03:35 PM PDT 24
Finished May 16 02:11:33 PM PDT 24
Peak memory 217676 kb
Host smart-0dc1af91-7a3a-4029-8afe-f6b0e4b9cfa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465099581 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2465099581
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.4140313304
Short name T269
Test name
Test status
Simulation time 28441085 ps
CPU time 1.32 seconds
Started May 16 02:03:48 PM PDT 24
Finished May 16 02:03:51 PM PDT 24
Peak memory 215340 kb
Host smart-5b9d876a-cee8-46b6-9bb2-13a7bc123396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140313304 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.4140313304
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.500621891
Short name T564
Test name
Test status
Simulation time 46918718 ps
CPU time 0.89 seconds
Started May 16 02:03:46 PM PDT 24
Finished May 16 02:03:48 PM PDT 24
Peak memory 206284 kb
Host smart-e1083297-948b-4a19-b244-0598b6a2f0ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500621891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.500621891
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2139791634
Short name T794
Test name
Test status
Simulation time 27633476 ps
CPU time 0.84 seconds
Started May 16 02:03:48 PM PDT 24
Finished May 16 02:03:51 PM PDT 24
Peak memory 215208 kb
Host smart-5bcdd377-da5c-474b-89b4-c5f8880eef50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139791634 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2139791634
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1027969148
Short name T738
Test name
Test status
Simulation time 406961005 ps
CPU time 1.19 seconds
Started May 16 02:03:47 PM PDT 24
Finished May 16 02:03:49 PM PDT 24
Peak memory 216340 kb
Host smart-529bf025-0a38-44b3-9dd9-dc3251d68d74
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027969148 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1027969148
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1660445073
Short name T839
Test name
Test status
Simulation time 32362147 ps
CPU time 0.89 seconds
Started May 16 02:03:46 PM PDT 24
Finished May 16 02:03:48 PM PDT 24
Peak memory 218032 kb
Host smart-5d9a5056-3fb0-4a5b-b0ae-cbd5d5e3210e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660445073 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1660445073
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1063208346
Short name T618
Test name
Test status
Simulation time 123461628 ps
CPU time 2.94 seconds
Started May 16 02:03:47 PM PDT 24
Finished May 16 02:03:52 PM PDT 24
Peak memory 219660 kb
Host smart-3f9adc33-eb54-4b14-9420-434dfd8b8bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063208346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1063208346
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.497741336
Short name T602
Test name
Test status
Simulation time 55492502 ps
CPU time 0.92 seconds
Started May 16 02:03:48 PM PDT 24
Finished May 16 02:03:50 PM PDT 24
Peak memory 214900 kb
Host smart-dc81186a-c459-4d48-a232-3f29c4b70f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497741336 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.497741336
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.4213715017
Short name T339
Test name
Test status
Simulation time 30803231 ps
CPU time 0.92 seconds
Started May 16 02:03:46 PM PDT 24
Finished May 16 02:03:48 PM PDT 24
Peak memory 214936 kb
Host smart-905cccdd-2ab6-4c2a-b54d-6816694a28a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213715017 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.4213715017
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3798930064
Short name T417
Test name
Test status
Simulation time 314050151 ps
CPU time 6.02 seconds
Started May 16 02:03:49 PM PDT 24
Finished May 16 02:03:56 PM PDT 24
Peak memory 216628 kb
Host smart-8441c79a-d496-4c2c-8339-d03dcf5951da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798930064 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3798930064
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.51094246
Short name T745
Test name
Test status
Simulation time 523517526540 ps
CPU time 2089.24 seconds
Started May 16 02:03:47 PM PDT 24
Finished May 16 02:38:38 PM PDT 24
Peak memory 229100 kb
Host smart-abee8b7e-53e5-4cf1-9587-452d9d2e6b12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51094246 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.51094246
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.300343079
Short name T668
Test name
Test status
Simulation time 181697715 ps
CPU time 1.19 seconds
Started May 16 02:03:46 PM PDT 24
Finished May 16 02:03:47 PM PDT 24
Peak memory 215360 kb
Host smart-a15c4ee3-08d5-4414-b35b-ac355868b3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300343079 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.300343079
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3443019006
Short name T360
Test name
Test status
Simulation time 16316889 ps
CPU time 0.92 seconds
Started May 16 02:03:49 PM PDT 24
Finished May 16 02:03:51 PM PDT 24
Peak memory 206272 kb
Host smart-b0803eee-a4e0-4579-88e4-b846d7e04452
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443019006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3443019006
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2374754756
Short name T20
Test name
Test status
Simulation time 14318048 ps
CPU time 0.95 seconds
Started May 16 02:03:48 PM PDT 24
Finished May 16 02:03:50 PM PDT 24
Peak memory 215368 kb
Host smart-2cfe97f7-5f6d-43cc-9579-5213b94af706
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374754756 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2374754756
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.308614303
Short name T57
Test name
Test status
Simulation time 33840204 ps
CPU time 1.33 seconds
Started May 16 02:03:46 PM PDT 24
Finished May 16 02:03:49 PM PDT 24
Peak memory 216668 kb
Host smart-48d1204f-7ce7-429b-a130-104faac7ee62
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308614303 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.308614303
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.4049446902
Short name T58
Test name
Test status
Simulation time 23937725 ps
CPU time 0.94 seconds
Started May 16 02:03:53 PM PDT 24
Finished May 16 02:03:56 PM PDT 24
Peak memory 214884 kb
Host smart-f1071fb5-1625-4e61-baf0-c4c557c89f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049446902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.4049446902
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1926028048
Short name T752
Test name
Test status
Simulation time 243353015 ps
CPU time 1.7 seconds
Started May 16 02:03:47 PM PDT 24
Finished May 16 02:03:50 PM PDT 24
Peak memory 218132 kb
Host smart-2264104f-a6cd-4e88-bb24-dbcb066303be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926028048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1926028048
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2404806766
Short name T499
Test name
Test status
Simulation time 22282679 ps
CPU time 1.13 seconds
Started May 16 02:03:40 PM PDT 24
Finished May 16 02:03:42 PM PDT 24
Peak memory 215104 kb
Host smart-ed53bb4e-efaa-4f6a-8f2c-bff3a7b4d6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404806766 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2404806766
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3485261026
Short name T366
Test name
Test status
Simulation time 19166514 ps
CPU time 1.02 seconds
Started May 16 02:03:53 PM PDT 24
Finished May 16 02:03:56 PM PDT 24
Peak memory 214972 kb
Host smart-733e0e68-fcd6-4a78-b963-64a9ace56650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485261026 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3485261026
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3349499054
Short name T599
Test name
Test status
Simulation time 229878741 ps
CPU time 2.83 seconds
Started May 16 02:03:47 PM PDT 24
Finished May 16 02:03:51 PM PDT 24
Peak memory 216552 kb
Host smart-9aa6cd0b-65d8-49fa-a929-c32ac252b383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349499054 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3349499054
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2853680638
Short name T205
Test name
Test status
Simulation time 19063129822 ps
CPU time 413.97 seconds
Started May 16 02:03:54 PM PDT 24
Finished May 16 02:10:49 PM PDT 24
Peak memory 217864 kb
Host smart-9ffbea20-3484-4fb1-90b4-5de06a4f5c43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853680638 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2853680638
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2561099337
Short name T278
Test name
Test status
Simulation time 236614656 ps
CPU time 1.33 seconds
Started May 16 02:03:52 PM PDT 24
Finished May 16 02:03:56 PM PDT 24
Peak memory 215368 kb
Host smart-e14b315d-48fb-4a5b-aa5c-5d4d6c9fbbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561099337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2561099337
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3874196372
Short name T736
Test name
Test status
Simulation time 69282992 ps
CPU time 0.98 seconds
Started May 16 02:03:51 PM PDT 24
Finished May 16 02:03:54 PM PDT 24
Peak memory 206296 kb
Host smart-b549dd69-1c4e-41b5-8b4b-d70824a599b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874196372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3874196372
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1652288580
Short name T463
Test name
Test status
Simulation time 15683757 ps
CPU time 0.84 seconds
Started May 16 02:03:52 PM PDT 24
Finished May 16 02:03:55 PM PDT 24
Peak memory 215736 kb
Host smart-46ebdfda-7651-4950-86d2-395e52d5b34f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652288580 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1652288580
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3132409474
Short name T189
Test name
Test status
Simulation time 112708459 ps
CPU time 1.29 seconds
Started May 16 02:03:51 PM PDT 24
Finished May 16 02:03:54 PM PDT 24
Peak memory 216656 kb
Host smart-af03fa0f-9106-416f-bfa4-547380f5f4c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132409474 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3132409474
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2869313606
Short name T180
Test name
Test status
Simulation time 32285869 ps
CPU time 1.43 seconds
Started May 16 02:03:51 PM PDT 24
Finished May 16 02:03:55 PM PDT 24
Peak memory 219240 kb
Host smart-0c23b3f8-e16b-4c1e-9ae8-10879fb82632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869313606 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2869313606
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1976460951
Short name T750
Test name
Test status
Simulation time 74540284 ps
CPU time 1.21 seconds
Started May 16 02:03:52 PM PDT 24
Finished May 16 02:03:55 PM PDT 24
Peak memory 216916 kb
Host smart-42e3a2ee-4acb-48dd-9867-49f2dbafb105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976460951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1976460951
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2534359884
Short name T674
Test name
Test status
Simulation time 30316822 ps
CPU time 1.05 seconds
Started May 16 02:03:52 PM PDT 24
Finished May 16 02:03:55 PM PDT 24
Peak memory 223548 kb
Host smart-075821a7-b5f1-4343-9f4c-3beabb05ae1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534359884 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2534359884
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2478862084
Short name T661
Test name
Test status
Simulation time 30954022 ps
CPU time 0.99 seconds
Started May 16 02:03:53 PM PDT 24
Finished May 16 02:03:56 PM PDT 24
Peak memory 214888 kb
Host smart-a67fec9f-0ace-4a01-8880-f2c7d367a09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478862084 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2478862084
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.638562669
Short name T656
Test name
Test status
Simulation time 707974250 ps
CPU time 7.06 seconds
Started May 16 02:03:52 PM PDT 24
Finished May 16 02:04:01 PM PDT 24
Peak memory 216708 kb
Host smart-f16dc1ac-c49e-4096-ac29-a32279f6058a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638562669 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.638562669
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.296569075
Short name T211
Test name
Test status
Simulation time 151703954121 ps
CPU time 2052.93 seconds
Started May 16 02:03:52 PM PDT 24
Finished May 16 02:38:07 PM PDT 24
Peak memory 226232 kb
Host smart-028e9f64-9c41-448f-bc9a-53193cd101d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296569075 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.296569075
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert_test.663957828
Short name T702
Test name
Test status
Simulation time 14278552 ps
CPU time 0.94 seconds
Started May 16 02:04:02 PM PDT 24
Finished May 16 02:04:08 PM PDT 24
Peak memory 214436 kb
Host smart-75c5b504-6d69-4a0f-acbc-ce0b39eeb077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663957828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.663957828
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3991793605
Short name T464
Test name
Test status
Simulation time 13541846 ps
CPU time 0.96 seconds
Started May 16 02:04:02 PM PDT 24
Finished May 16 02:04:07 PM PDT 24
Peak memory 215788 kb
Host smart-06ec3104-4549-4b77-b84a-b8b9a6cc2ad1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991793605 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3991793605
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2062685984
Short name T816
Test name
Test status
Simulation time 40527218 ps
CPU time 1.09 seconds
Started May 16 02:04:01 PM PDT 24
Finished May 16 02:04:05 PM PDT 24
Peak memory 217980 kb
Host smart-e9dc39d8-df3c-48f9-be26-99e8ee3e4e67
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062685984 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2062685984
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1631263614
Short name T413
Test name
Test status
Simulation time 23427945 ps
CPU time 1.2 seconds
Started May 16 02:04:03 PM PDT 24
Finished May 16 02:04:08 PM PDT 24
Peak memory 229004 kb
Host smart-643ffed8-2b38-4dd1-afcc-a23bfda40c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631263614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1631263614
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.4214643295
Short name T322
Test name
Test status
Simulation time 43572506 ps
CPU time 1.77 seconds
Started May 16 02:03:52 PM PDT 24
Finished May 16 02:03:56 PM PDT 24
Peak memory 217712 kb
Host smart-a4f40fc9-58bc-4939-a94a-ce49d5954a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214643295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.4214643295
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.513636200
Short name T397
Test name
Test status
Simulation time 33956043 ps
CPU time 0.84 seconds
Started May 16 02:03:52 PM PDT 24
Finished May 16 02:03:55 PM PDT 24
Peak memory 215168 kb
Host smart-fe77aca8-c40b-49b4-bbd4-df10ae2ac7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513636200 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.513636200
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.14810941
Short name T739
Test name
Test status
Simulation time 16062092 ps
CPU time 1.13 seconds
Started May 16 02:03:52 PM PDT 24
Finished May 16 02:03:55 PM PDT 24
Peak memory 214944 kb
Host smart-e52b1c8f-ca33-4e47-943a-e2baa8a16d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14810941 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.14810941
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1964879888
Short name T289
Test name
Test status
Simulation time 331784429 ps
CPU time 2.23 seconds
Started May 16 02:03:52 PM PDT 24
Finished May 16 02:03:57 PM PDT 24
Peak memory 214956 kb
Host smart-f87a2391-58ad-4679-9d0f-2c875b4b6d1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964879888 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1964879888
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2641243701
Short name T423
Test name
Test status
Simulation time 36465783129 ps
CPU time 729.8 seconds
Started May 16 02:03:53 PM PDT 24
Finished May 16 02:16:04 PM PDT 24
Peak memory 217096 kb
Host smart-9920b605-dc2c-45f5-808c-fae02da17c6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641243701 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2641243701
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2955636744
Short name T193
Test name
Test status
Simulation time 33277922 ps
CPU time 1.41 seconds
Started May 16 02:04:03 PM PDT 24
Finished May 16 02:04:09 PM PDT 24
Peak memory 215368 kb
Host smart-990476dc-4853-4f42-8cd8-87d756957457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955636744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2955636744
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.494449789
Short name T642
Test name
Test status
Simulation time 23647637 ps
CPU time 1.09 seconds
Started May 16 02:04:06 PM PDT 24
Finished May 16 02:04:11 PM PDT 24
Peak memory 206340 kb
Host smart-7d415d32-4e97-41b8-8165-80b42f52d960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494449789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.494449789
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3511747214
Short name T88
Test name
Test status
Simulation time 13208505 ps
CPU time 0.95 seconds
Started May 16 02:04:04 PM PDT 24
Finished May 16 02:04:10 PM PDT 24
Peak memory 216200 kb
Host smart-70b6a1ef-bd31-4fcb-a011-a86ad092c5b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511747214 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3511747214
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2409223533
Short name T494
Test name
Test status
Simulation time 44305398 ps
CPU time 1.06 seconds
Started May 16 02:04:03 PM PDT 24
Finished May 16 02:04:08 PM PDT 24
Peak memory 216532 kb
Host smart-b2016f92-796f-49b3-b49d-f6e0b3b6d9d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409223533 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2409223533
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2321221396
Short name T449
Test name
Test status
Simulation time 23348784 ps
CPU time 0.93 seconds
Started May 16 02:04:04 PM PDT 24
Finished May 16 02:04:10 PM PDT 24
Peak memory 218188 kb
Host smart-109a18b2-7f74-478a-9d4f-a799601fec57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321221396 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2321221396
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.4271280472
Short name T372
Test name
Test status
Simulation time 43492522 ps
CPU time 1.12 seconds
Started May 16 02:04:06 PM PDT 24
Finished May 16 02:04:11 PM PDT 24
Peak memory 216776 kb
Host smart-e3abe364-af92-4109-b5f1-9fa0ddffedf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271280472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.4271280472
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.958536400
Short name T106
Test name
Test status
Simulation time 21764386 ps
CPU time 1.05 seconds
Started May 16 02:04:04 PM PDT 24
Finished May 16 02:04:09 PM PDT 24
Peak memory 215536 kb
Host smart-b4c2013c-55b6-44b4-bb5c-7549d3138c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958536400 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.958536400
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.423418720
Short name T776
Test name
Test status
Simulation time 53011977 ps
CPU time 0.95 seconds
Started May 16 02:04:02 PM PDT 24
Finished May 16 02:04:07 PM PDT 24
Peak memory 214916 kb
Host smart-ac166479-c80b-4eac-85a9-effef9ef04de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423418720 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.423418720
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1862577318
Short name T342
Test name
Test status
Simulation time 987790584 ps
CPU time 4.54 seconds
Started May 16 02:04:01 PM PDT 24
Finished May 16 02:04:08 PM PDT 24
Peak memory 216484 kb
Host smart-4b2085ae-9e21-47d3-834a-9255ccb324dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862577318 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1862577318
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2981821279
Short name T513
Test name
Test status
Simulation time 101651024504 ps
CPU time 636.2 seconds
Started May 16 02:04:01 PM PDT 24
Finished May 16 02:14:41 PM PDT 24
Peak memory 220072 kb
Host smart-6364c443-df6a-44ac-8df9-a8e43e651460
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981821279 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2981821279
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2244229237
Short name T74
Test name
Test status
Simulation time 27753435 ps
CPU time 1.26 seconds
Started May 16 02:04:01 PM PDT 24
Finished May 16 02:04:05 PM PDT 24
Peak memory 215360 kb
Host smart-f0e6580a-275c-43af-a46e-9d01d653da98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244229237 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2244229237
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.638053261
Short name T712
Test name
Test status
Simulation time 41601613 ps
CPU time 0.9 seconds
Started May 16 02:04:04 PM PDT 24
Finished May 16 02:04:10 PM PDT 24
Peak memory 214432 kb
Host smart-de8c0ad2-f978-49ad-bc69-38d5491bfd11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638053261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.638053261
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2492274002
Short name T250
Test name
Test status
Simulation time 17172531 ps
CPU time 0.95 seconds
Started May 16 02:04:05 PM PDT 24
Finished May 16 02:04:11 PM PDT 24
Peak memory 217692 kb
Host smart-f9bf6d67-8669-42b2-9ee1-9dc7c9c6af46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492274002 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2492274002
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3294589760
Short name T41
Test name
Test status
Simulation time 25340753 ps
CPU time 1.22 seconds
Started May 16 02:04:06 PM PDT 24
Finished May 16 02:04:11 PM PDT 24
Peak memory 220076 kb
Host smart-c56e6076-e66f-4a63-a7c0-2939f66eb6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294589760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3294589760
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.4063018831
Short name T650
Test name
Test status
Simulation time 39760298 ps
CPU time 1.42 seconds
Started May 16 02:04:04 PM PDT 24
Finished May 16 02:04:09 PM PDT 24
Peak memory 215020 kb
Host smart-2909fa99-f9b1-4de0-9ed7-72ffc53cdd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063018831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.4063018831
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_smoke.381977309
Short name T164
Test name
Test status
Simulation time 28761497 ps
CPU time 1 seconds
Started May 16 02:04:02 PM PDT 24
Finished May 16 02:04:07 PM PDT 24
Peak memory 214828 kb
Host smart-504b78f0-fa42-4411-bee2-3832ccf9334f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381977309 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.381977309
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.4061169668
Short name T567
Test name
Test status
Simulation time 267815103 ps
CPU time 3.03 seconds
Started May 16 02:04:06 PM PDT 24
Finished May 16 02:04:13 PM PDT 24
Peak memory 216508 kb
Host smart-b6abdeb1-ff2e-471e-914b-4a0ea5d1c5cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061169668 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.4061169668
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3262686245
Short name T207
Test name
Test status
Simulation time 336941623557 ps
CPU time 1164.93 seconds
Started May 16 02:04:04 PM PDT 24
Finished May 16 02:23:33 PM PDT 24
Peak memory 221300 kb
Host smart-f801fb89-18ef-40b3-8530-3d806148b9a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262686245 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3262686245
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert_test.2273416136
Short name T584
Test name
Test status
Simulation time 38427997 ps
CPU time 0.85 seconds
Started May 16 02:04:04 PM PDT 24
Finished May 16 02:04:10 PM PDT 24
Peak memory 206492 kb
Host smart-513d6cd0-498a-4615-9aa9-8325c9bf14d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273416136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2273416136
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.441726147
Short name T459
Test name
Test status
Simulation time 64840449 ps
CPU time 0.97 seconds
Started May 16 02:04:02 PM PDT 24
Finished May 16 02:04:08 PM PDT 24
Peak memory 215180 kb
Host smart-3a5cc35f-67f5-463c-b8ce-f1a7c1b383df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441726147 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.441726147
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2739952829
Short name T565
Test name
Test status
Simulation time 83607356 ps
CPU time 1.1 seconds
Started May 16 02:04:02 PM PDT 24
Finished May 16 02:04:07 PM PDT 24
Peak memory 217956 kb
Host smart-a927db78-fa2f-4600-86fb-5f8d2d897f19
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739952829 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2739952829
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1387204439
Short name T82
Test name
Test status
Simulation time 36858193 ps
CPU time 0.98 seconds
Started May 16 02:04:03 PM PDT 24
Finished May 16 02:04:08 PM PDT 24
Peak memory 223256 kb
Host smart-2363d3f1-2ba2-4d30-9a4c-ce411518d346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387204439 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1387204439
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3740491127
Short name T590
Test name
Test status
Simulation time 410558162 ps
CPU time 1.41 seconds
Started May 16 02:04:03 PM PDT 24
Finished May 16 02:04:09 PM PDT 24
Peak memory 219500 kb
Host smart-f676ba56-5229-4977-828e-efaa9ca55a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740491127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3740491127
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.600783789
Short name T112
Test name
Test status
Simulation time 35090910 ps
CPU time 0.88 seconds
Started May 16 02:04:02 PM PDT 24
Finished May 16 02:04:06 PM PDT 24
Peak memory 215116 kb
Host smart-b51d7f1d-2f9e-4bf5-aa35-98a5905dd97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600783789 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.600783789
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2256471605
Short name T536
Test name
Test status
Simulation time 34786107 ps
CPU time 0.99 seconds
Started May 16 02:04:04 PM PDT 24
Finished May 16 02:04:09 PM PDT 24
Peak memory 214972 kb
Host smart-f54cffac-d474-4608-acf8-e6bbdb928d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256471605 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2256471605
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3354229578
Short name T688
Test name
Test status
Simulation time 385324433 ps
CPU time 2.64 seconds
Started May 16 02:04:01 PM PDT 24
Finished May 16 02:04:07 PM PDT 24
Peak memory 216604 kb
Host smart-9f6dddd2-28ae-4744-83ed-47073905623e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354229578 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3354229578
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.828775632
Short name T165
Test name
Test status
Simulation time 36403297655 ps
CPU time 257.38 seconds
Started May 16 02:04:02 PM PDT 24
Finished May 16 02:08:24 PM PDT 24
Peak memory 223364 kb
Host smart-61c1ee6d-7c0d-4c92-89ff-ac9b43dfea86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828775632 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.828775632
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1176266376
Short name T800
Test name
Test status
Simulation time 141536126 ps
CPU time 1.32 seconds
Started May 16 02:01:35 PM PDT 24
Finished May 16 02:01:38 PM PDT 24
Peak memory 215340 kb
Host smart-17af23cf-4588-45a0-849a-4817c8e5b445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176266376 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1176266376
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.341951366
Short name T705
Test name
Test status
Simulation time 12878808 ps
CPU time 0.89 seconds
Started May 16 02:01:44 PM PDT 24
Finished May 16 02:01:46 PM PDT 24
Peak memory 206264 kb
Host smart-018397ac-b01a-44bc-8dc0-119d9d977ca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341951366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.341951366
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1426421015
Short name T603
Test name
Test status
Simulation time 40092637 ps
CPU time 1.07 seconds
Started May 16 02:01:44 PM PDT 24
Finished May 16 02:01:46 PM PDT 24
Peak memory 216860 kb
Host smart-55b2cfb1-74e8-4792-ba4e-5c4a523e1e29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426421015 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1426421015
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.673331503
Short name T783
Test name
Test status
Simulation time 48267281 ps
CPU time 1 seconds
Started May 16 02:01:38 PM PDT 24
Finished May 16 02:01:41 PM PDT 24
Peak memory 218288 kb
Host smart-294a371b-9c71-4fed-86f4-150a68208ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673331503 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.673331503
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2037093529
Short name T523
Test name
Test status
Simulation time 48474124 ps
CPU time 1.19 seconds
Started May 16 02:01:36 PM PDT 24
Finished May 16 02:01:38 PM PDT 24
Peak memory 216928 kb
Host smart-16e33569-01c8-4340-bb78-915b9ddf5fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037093529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2037093529
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.510048292
Short name T107
Test name
Test status
Simulation time 24044486 ps
CPU time 0.94 seconds
Started May 16 02:01:36 PM PDT 24
Finished May 16 02:01:38 PM PDT 24
Peak memory 215324 kb
Host smart-96218028-5025-4074-9d87-b30a2fd81d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510048292 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.510048292
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1159091153
Short name T271
Test name
Test status
Simulation time 17691732 ps
CPU time 1.01 seconds
Started May 16 02:01:34 PM PDT 24
Finished May 16 02:01:36 PM PDT 24
Peak memory 206732 kb
Host smart-4e1f898f-9f04-4f08-8981-ccc2745a9008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159091153 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1159091153
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1098294650
Short name T404
Test name
Test status
Simulation time 24326595 ps
CPU time 0.92 seconds
Started May 16 02:01:38 PM PDT 24
Finished May 16 02:01:41 PM PDT 24
Peak memory 214896 kb
Host smart-6a1ad056-71c7-4ef6-b4b4-af04debcb7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098294650 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1098294650
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.433544217
Short name T217
Test name
Test status
Simulation time 430341325 ps
CPU time 7.99 seconds
Started May 16 02:01:38 PM PDT 24
Finished May 16 02:01:48 PM PDT 24
Peak memory 217968 kb
Host smart-1966845f-12fc-4b29-9dcb-295114522661
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433544217 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.433544217
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.524557719
Short name T212
Test name
Test status
Simulation time 213695815738 ps
CPU time 1372.65 seconds
Started May 16 02:01:38 PM PDT 24
Finished May 16 02:24:32 PM PDT 24
Peak memory 223364 kb
Host smart-be2aef2c-e0e4-430d-9b4a-e7cdeddbe150
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524557719 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.524557719
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.787077280
Short name T529
Test name
Test status
Simulation time 18288411 ps
CPU time 1.12 seconds
Started May 16 02:04:03 PM PDT 24
Finished May 16 02:04:08 PM PDT 24
Peak memory 232228 kb
Host smart-538f651e-89b0-4e20-81c6-f07428122c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787077280 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.787077280
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2843285974
Short name T371
Test name
Test status
Simulation time 32120752 ps
CPU time 1.29 seconds
Started May 16 02:04:03 PM PDT 24
Finished May 16 02:04:08 PM PDT 24
Peak memory 216760 kb
Host smart-2432edb5-cecb-4fbb-a679-778a878a3d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843285974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2843285974
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.3895767700
Short name T76
Test name
Test status
Simulation time 27349387 ps
CPU time 0.95 seconds
Started May 16 02:04:00 PM PDT 24
Finished May 16 02:04:03 PM PDT 24
Peak memory 223260 kb
Host smart-096a18dc-246e-4098-85b2-1ac8878372af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895767700 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3895767700
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.511028220
Short name T845
Test name
Test status
Simulation time 49245230 ps
CPU time 1.7 seconds
Started May 16 02:04:00 PM PDT 24
Finished May 16 02:04:04 PM PDT 24
Peak memory 217840 kb
Host smart-9667e0a6-2883-4002-aeba-db2d2fcf14f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511028220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.511028220
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.3719103264
Short name T518
Test name
Test status
Simulation time 19642547 ps
CPU time 1.09 seconds
Started May 16 02:04:06 PM PDT 24
Finished May 16 02:04:11 PM PDT 24
Peak memory 217924 kb
Host smart-d718de41-00fe-475a-9f47-e0d082a4ef81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719103264 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3719103264
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2961792804
Short name T484
Test name
Test status
Simulation time 34659005 ps
CPU time 1.06 seconds
Started May 16 02:04:05 PM PDT 24
Finished May 16 02:04:10 PM PDT 24
Peak memory 216768 kb
Host smart-01a1fd31-af4a-4a79-9e5f-ed71cecd298a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961792804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2961792804
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.1575022399
Short name T6
Test name
Test status
Simulation time 34466295 ps
CPU time 1.09 seconds
Started May 16 02:04:02 PM PDT 24
Finished May 16 02:04:07 PM PDT 24
Peak memory 229148 kb
Host smart-fd69e041-57cb-4fab-bd7a-6d463929e608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575022399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1575022399
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3453237066
Short name T320
Test name
Test status
Simulation time 711291935 ps
CPU time 6.26 seconds
Started May 16 02:04:01 PM PDT 24
Finished May 16 02:04:11 PM PDT 24
Peak memory 219424 kb
Host smart-504a47ee-cac5-48cf-bcfa-56ca7ca9fcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453237066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3453237066
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.78237349
Short name T539
Test name
Test status
Simulation time 19976411 ps
CPU time 1.18 seconds
Started May 16 02:04:04 PM PDT 24
Finished May 16 02:04:10 PM PDT 24
Peak memory 223196 kb
Host smart-cb317600-d652-4087-8a73-d823bad17397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78237349 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.78237349
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2489285843
Short name T754
Test name
Test status
Simulation time 67266571 ps
CPU time 1.07 seconds
Started May 16 02:04:04 PM PDT 24
Finished May 16 02:04:09 PM PDT 24
Peak memory 216716 kb
Host smart-2b4a9fcb-2e64-4a9e-a18d-0e89c613cd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489285843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2489285843
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.3301224555
Short name T86
Test name
Test status
Simulation time 20642156 ps
CPU time 1.22 seconds
Started May 16 02:04:01 PM PDT 24
Finished May 16 02:04:06 PM PDT 24
Peak memory 223432 kb
Host smart-33162e9b-b2be-4924-ba62-1c548bbf5aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301224555 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3301224555
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.448769507
Short name T528
Test name
Test status
Simulation time 40288957 ps
CPU time 1.45 seconds
Started May 16 02:04:03 PM PDT 24
Finished May 16 02:04:09 PM PDT 24
Peak memory 219152 kb
Host smart-f3fdb09f-a82e-4795-b179-0454a7059143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448769507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.448769507
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.2108255827
Short name T807
Test name
Test status
Simulation time 23283129 ps
CPU time 0.97 seconds
Started May 16 02:04:03 PM PDT 24
Finished May 16 02:04:09 PM PDT 24
Peak memory 218164 kb
Host smart-5d3093fa-a91a-4c70-9a01-1141633b3f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108255827 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2108255827
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.786722279
Short name T451
Test name
Test status
Simulation time 28960717 ps
CPU time 1.17 seconds
Started May 16 02:04:04 PM PDT 24
Finished May 16 02:04:10 PM PDT 24
Peak memory 216772 kb
Host smart-d8f219df-0e3d-4fee-bcd0-7172a896f182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786722279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.786722279
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.1289449413
Short name T610
Test name
Test status
Simulation time 25212787 ps
CPU time 1 seconds
Started May 16 02:04:03 PM PDT 24
Finished May 16 02:04:08 PM PDT 24
Peak memory 218252 kb
Host smart-f1c8d383-3372-40b0-a8aa-a9a56691db10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289449413 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1289449413
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.4058380994
Short name T616
Test name
Test status
Simulation time 57126511 ps
CPU time 2.27 seconds
Started May 16 02:04:04 PM PDT 24
Finished May 16 02:04:11 PM PDT 24
Peak memory 219060 kb
Host smart-0ad6eed8-ea22-4e59-95ec-bdf1c8c29652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058380994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.4058380994
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.3676213552
Short name T101
Test name
Test status
Simulation time 21193531 ps
CPU time 0.97 seconds
Started May 16 02:04:14 PM PDT 24
Finished May 16 02:04:17 PM PDT 24
Peak memory 219132 kb
Host smart-58be3e3d-5bd6-4856-8385-7dc41c4b44b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676213552 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3676213552
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.4258099976
Short name T386
Test name
Test status
Simulation time 76961449 ps
CPU time 1.1 seconds
Started May 16 02:04:17 PM PDT 24
Finished May 16 02:04:21 PM PDT 24
Peak memory 216628 kb
Host smart-cf2de039-d0f2-4557-b738-161ac1cfb3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258099976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.4258099976
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.925502456
Short name T36
Test name
Test status
Simulation time 24541428 ps
CPU time 1.3 seconds
Started May 16 02:04:14 PM PDT 24
Finished May 16 02:04:17 PM PDT 24
Peak memory 229112 kb
Host smart-a2472663-0aa3-41a7-b226-276b7fea1328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925502456 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.925502456
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2245966044
Short name T817
Test name
Test status
Simulation time 34750498 ps
CPU time 1.31 seconds
Started May 16 02:04:13 PM PDT 24
Finished May 16 02:04:15 PM PDT 24
Peak memory 216752 kb
Host smart-f0331055-4aaf-47af-81f9-0fe42e33da44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245966044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2245966044
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.4126346288
Short name T641
Test name
Test status
Simulation time 60544279 ps
CPU time 1.3 seconds
Started May 16 02:01:47 PM PDT 24
Finished May 16 02:01:50 PM PDT 24
Peak memory 215332 kb
Host smart-feab8ef1-b0e1-4dc8-9671-560c97da1009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126346288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.4126346288
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.219374420
Short name T605
Test name
Test status
Simulation time 55378217 ps
CPU time 1.57 seconds
Started May 16 02:01:45 PM PDT 24
Finished May 16 02:01:49 PM PDT 24
Peak memory 206460 kb
Host smart-77c0a440-6ebf-41b7-9ef1-0d52cfc84918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219374420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.219374420
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.994177802
Short name T156
Test name
Test status
Simulation time 62647495 ps
CPU time 1.24 seconds
Started May 16 02:01:44 PM PDT 24
Finished May 16 02:01:47 PM PDT 24
Peak memory 219164 kb
Host smart-36ab3523-404d-4fd3-a8f8-c2c53ab3151b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994177802 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.994177802
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.3587670182
Short name T765
Test name
Test status
Simulation time 37055547 ps
CPU time 1.19 seconds
Started May 16 02:01:46 PM PDT 24
Finished May 16 02:01:49 PM PDT 24
Peak memory 220288 kb
Host smart-bafddb9d-d4f8-45af-a1c7-736aa2621d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587670182 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3587670182
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1788435276
Short name T315
Test name
Test status
Simulation time 40657648 ps
CPU time 1.71 seconds
Started May 16 02:01:44 PM PDT 24
Finished May 16 02:01:47 PM PDT 24
Peak memory 219224 kb
Host smart-5e02841d-87ac-431b-8790-3939f6fc2b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788435276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1788435276
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1929197583
Short name T699
Test name
Test status
Simulation time 20903163 ps
CPU time 1.08 seconds
Started May 16 02:01:47 PM PDT 24
Finished May 16 02:01:50 PM PDT 24
Peak memory 215384 kb
Host smart-efab00f1-d9db-4654-a04d-473a822f2b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929197583 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1929197583
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.3392946071
Short name T103
Test name
Test status
Simulation time 30950766 ps
CPU time 0.98 seconds
Started May 16 02:01:46 PM PDT 24
Finished May 16 02:01:49 PM PDT 24
Peak memory 206792 kb
Host smart-32db1ff6-a332-48ab-b4d9-f68582a0ca73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392946071 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3392946071
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.699376775
Short name T472
Test name
Test status
Simulation time 27164316 ps
CPU time 0.97 seconds
Started May 16 02:01:47 PM PDT 24
Finished May 16 02:01:49 PM PDT 24
Peak memory 214952 kb
Host smart-abb518d8-b522-4375-9ad6-83ebb05c3bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699376775 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.699376775
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.22634597
Short name T466
Test name
Test status
Simulation time 631628185 ps
CPU time 4.32 seconds
Started May 16 02:01:44 PM PDT 24
Finished May 16 02:01:50 PM PDT 24
Peak memory 216428 kb
Host smart-282b0ae7-e2c1-448f-9775-966dea2befa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22634597 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.22634597
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1507743313
Short name T835
Test name
Test status
Simulation time 72274146847 ps
CPU time 1898.9 seconds
Started May 16 02:01:45 PM PDT 24
Finished May 16 02:33:26 PM PDT 24
Peak memory 227672 kb
Host smart-b912e4c5-b704-4724-b38f-2ca072a3e849
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507743313 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1507743313
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.2381979363
Short name T155
Test name
Test status
Simulation time 25108591 ps
CPU time 0.99 seconds
Started May 16 02:04:16 PM PDT 24
Finished May 16 02:04:20 PM PDT 24
Peak memory 218148 kb
Host smart-ae760437-7a61-4fca-93da-59b11fcd5ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381979363 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2381979363
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1496994818
Short name T422
Test name
Test status
Simulation time 41510656 ps
CPU time 1.23 seconds
Started May 16 02:04:15 PM PDT 24
Finished May 16 02:04:18 PM PDT 24
Peak memory 217952 kb
Host smart-3c886dd5-35fd-4620-b7b0-7f3cd0e5b06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496994818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1496994818
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.542113084
Short name T784
Test name
Test status
Simulation time 66320963 ps
CPU time 1.01 seconds
Started May 16 02:04:14 PM PDT 24
Finished May 16 02:04:17 PM PDT 24
Peak memory 218060 kb
Host smart-182cc558-01b8-42b5-a87c-66090c84c9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542113084 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.542113084
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1918544584
Short name T543
Test name
Test status
Simulation time 40319186 ps
CPU time 1.43 seconds
Started May 16 02:04:16 PM PDT 24
Finished May 16 02:04:21 PM PDT 24
Peak memory 219252 kb
Host smart-d801a035-0483-428d-8035-adee0e153316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918544584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1918544584
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.2464092021
Short name T487
Test name
Test status
Simulation time 36205992 ps
CPU time 1.14 seconds
Started May 16 02:04:16 PM PDT 24
Finished May 16 02:04:20 PM PDT 24
Peak memory 217092 kb
Host smart-e0c6ab36-29b7-4efa-8b33-9387a2cf36ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464092021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2464092021
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.430313361
Short name T291
Test name
Test status
Simulation time 51326663 ps
CPU time 1.24 seconds
Started May 16 02:04:15 PM PDT 24
Finished May 16 02:04:19 PM PDT 24
Peak memory 216504 kb
Host smart-60fa3677-248b-4fd4-abab-2646985b76c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430313361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.430313361
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.2572605337
Short name T42
Test name
Test status
Simulation time 85441215 ps
CPU time 0.97 seconds
Started May 16 02:04:15 PM PDT 24
Finished May 16 02:04:18 PM PDT 24
Peak memory 219012 kb
Host smart-40499f75-4d08-46c7-bd3a-a27246a8427f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572605337 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2572605337
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.65389338
Short name T457
Test name
Test status
Simulation time 115249858 ps
CPU time 2.39 seconds
Started May 16 02:04:15 PM PDT 24
Finished May 16 02:04:21 PM PDT 24
Peak memory 218228 kb
Host smart-e607cf13-cb56-4326-a0fa-cef3bd8d8301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65389338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.65389338
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.2088187859
Short name T179
Test name
Test status
Simulation time 50706972 ps
CPU time 1.01 seconds
Started May 16 02:04:17 PM PDT 24
Finished May 16 02:04:22 PM PDT 24
Peak memory 229036 kb
Host smart-49166a64-2eaa-4d9c-a023-4bda37492ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088187859 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2088187859
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2551314469
Short name T687
Test name
Test status
Simulation time 40668923 ps
CPU time 1.32 seconds
Started May 16 02:04:15 PM PDT 24
Finished May 16 02:04:19 PM PDT 24
Peak memory 216832 kb
Host smart-d1f45f70-0769-4ba5-8e00-12eed4070e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551314469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2551314469
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.3192398112
Short name T442
Test name
Test status
Simulation time 34124340 ps
CPU time 0.91 seconds
Started May 16 02:04:19 PM PDT 24
Finished May 16 02:04:23 PM PDT 24
Peak memory 219496 kb
Host smart-beeb1a88-8432-41f8-8edc-d2ac59d0e573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192398112 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3192398112
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3725697168
Short name T671
Test name
Test status
Simulation time 60226585 ps
CPU time 1.61 seconds
Started May 16 02:04:16 PM PDT 24
Finished May 16 02:04:21 PM PDT 24
Peak memory 218172 kb
Host smart-caa73ca9-4505-4205-bd58-ece7e0c3e193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725697168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3725697168
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.252851598
Short name T78
Test name
Test status
Simulation time 30094452 ps
CPU time 0.86 seconds
Started May 16 02:04:15 PM PDT 24
Finished May 16 02:04:18 PM PDT 24
Peak memory 217496 kb
Host smart-cfeaaa36-c8e6-4cb0-baa1-eb53eb652d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252851598 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.252851598
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2927684981
Short name T682
Test name
Test status
Simulation time 524665836 ps
CPU time 4.35 seconds
Started May 16 02:04:17 PM PDT 24
Finished May 16 02:04:25 PM PDT 24
Peak memory 219236 kb
Host smart-68feb00c-a21e-484f-805d-1721086e83ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927684981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2927684981
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.1294144688
Short name T54
Test name
Test status
Simulation time 35852162 ps
CPU time 1.24 seconds
Started May 16 02:04:15 PM PDT 24
Finished May 16 02:04:19 PM PDT 24
Peak memory 229060 kb
Host smart-d62da1b0-2da6-4dba-83db-0d5d34f4f849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294144688 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1294144688
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.4039470750
Short name T395
Test name
Test status
Simulation time 24449810 ps
CPU time 1.2 seconds
Started May 16 02:04:14 PM PDT 24
Finished May 16 02:04:16 PM PDT 24
Peak memory 216680 kb
Host smart-4a797942-5fb8-4a25-87f2-61345c517d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039470750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.4039470750
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.2456871904
Short name T689
Test name
Test status
Simulation time 31021273 ps
CPU time 0.9 seconds
Started May 16 02:04:16 PM PDT 24
Finished May 16 02:04:20 PM PDT 24
Peak memory 218088 kb
Host smart-d7d4ed69-8306-407a-bc19-b2d7d8a49845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456871904 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2456871904
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3700326085
Short name T714
Test name
Test status
Simulation time 40854582 ps
CPU time 1.15 seconds
Started May 16 02:04:18 PM PDT 24
Finished May 16 02:04:23 PM PDT 24
Peak memory 216756 kb
Host smart-9be57e01-0cd7-415b-9f98-c38a500172b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700326085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3700326085
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.221674507
Short name T137
Test name
Test status
Simulation time 23013761 ps
CPU time 1.05 seconds
Started May 16 02:04:17 PM PDT 24
Finished May 16 02:04:21 PM PDT 24
Peak memory 223340 kb
Host smart-7c6bba5e-acb7-43f5-bd41-27e84717f52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221674507 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.221674507
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1403570490
Short name T680
Test name
Test status
Simulation time 50412123 ps
CPU time 1.68 seconds
Started May 16 02:04:16 PM PDT 24
Finished May 16 02:04:20 PM PDT 24
Peak memory 217944 kb
Host smart-322d1bf1-c3ce-45e2-a2f7-5030808dd92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403570490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1403570490
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert_test.1593706405
Short name T335
Test name
Test status
Simulation time 22410759 ps
CPU time 0.83 seconds
Started May 16 02:01:55 PM PDT 24
Finished May 16 02:01:57 PM PDT 24
Peak memory 206212 kb
Host smart-65c63015-a98b-4707-9e19-ade6cbf6093f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593706405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1593706405
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2883824454
Short name T772
Test name
Test status
Simulation time 19149463 ps
CPU time 0.84 seconds
Started May 16 02:01:55 PM PDT 24
Finished May 16 02:01:57 PM PDT 24
Peak memory 215208 kb
Host smart-0d7c17a1-98f2-4dd2-a3c6-19407f5c3b00
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883824454 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2883824454
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2487648308
Short name T195
Test name
Test status
Simulation time 31525840 ps
CPU time 1.2 seconds
Started May 16 02:01:58 PM PDT 24
Finished May 16 02:02:02 PM PDT 24
Peak memory 219280 kb
Host smart-a822a75b-93d6-4d92-a5e9-da72eac5bddb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487648308 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2487648308
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.742251257
Short name T630
Test name
Test status
Simulation time 23017014 ps
CPU time 1.07 seconds
Started May 16 02:01:56 PM PDT 24
Finished May 16 02:02:00 PM PDT 24
Peak memory 223344 kb
Host smart-cf796e68-cc58-4a71-9109-5f5096369c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742251257 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.742251257
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1890479464
Short name T443
Test name
Test status
Simulation time 56996235 ps
CPU time 0.96 seconds
Started May 16 02:01:45 PM PDT 24
Finished May 16 02:01:48 PM PDT 24
Peak memory 216612 kb
Host smart-b377616c-1a07-40d9-9c1f-df5fc204de26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890479464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1890479464
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2396833634
Short name T4
Test name
Test status
Simulation time 30346577 ps
CPU time 0.93 seconds
Started May 16 02:01:46 PM PDT 24
Finished May 16 02:01:49 PM PDT 24
Peak memory 215056 kb
Host smart-1e9f160f-8295-491a-a022-f15b1f325678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396833634 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2396833634
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3755692725
Short name T628
Test name
Test status
Simulation time 18931785 ps
CPU time 1.06 seconds
Started May 16 02:01:46 PM PDT 24
Finished May 16 02:01:48 PM PDT 24
Peak memory 206772 kb
Host smart-1ab15295-3924-4f13-9618-e5da55af7a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755692725 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3755692725
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2081297711
Short name T378
Test name
Test status
Simulation time 65105290 ps
CPU time 0.84 seconds
Started May 16 02:01:46 PM PDT 24
Finished May 16 02:01:49 PM PDT 24
Peak memory 214980 kb
Host smart-1e0c0679-0a75-45a3-9cff-f80970fbb941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081297711 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2081297711
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1872761908
Short name T585
Test name
Test status
Simulation time 1247521790 ps
CPU time 5.28 seconds
Started May 16 02:01:45 PM PDT 24
Finished May 16 02:01:52 PM PDT 24
Peak memory 214992 kb
Host smart-05af7aca-c0bb-45d2-ad02-5a0aac6dad85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872761908 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1872761908
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2750854547
Short name T377
Test name
Test status
Simulation time 106847753330 ps
CPU time 2535.41 seconds
Started May 16 02:01:46 PM PDT 24
Finished May 16 02:44:03 PM PDT 24
Peak memory 228800 kb
Host smart-049a628b-ec2c-48cf-8681-15b0328c4f7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750854547 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2750854547
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.320821336
Short name T710
Test name
Test status
Simulation time 34122375 ps
CPU time 1.03 seconds
Started May 16 02:04:15 PM PDT 24
Finished May 16 02:04:18 PM PDT 24
Peak memory 229016 kb
Host smart-c949caca-5367-4fea-9aee-3d0e8700104a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320821336 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.320821336
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.813408470
Short name T23
Test name
Test status
Simulation time 57020277 ps
CPU time 1.21 seconds
Started May 16 02:04:15 PM PDT 24
Finished May 16 02:04:20 PM PDT 24
Peak memory 216600 kb
Host smart-72d2dca7-5524-472c-b760-2b090aad37dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813408470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.813408470
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.3940505547
Short name T43
Test name
Test status
Simulation time 54083727 ps
CPU time 1.03 seconds
Started May 16 02:04:14 PM PDT 24
Finished May 16 02:04:17 PM PDT 24
Peak memory 219240 kb
Host smart-56449495-8329-4a7c-a898-3a77dce48b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940505547 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3940505547
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2345837738
Short name T432
Test name
Test status
Simulation time 28784023 ps
CPU time 1.32 seconds
Started May 16 02:04:15 PM PDT 24
Finished May 16 02:04:20 PM PDT 24
Peak memory 218048 kb
Host smart-b066bb82-2676-4674-ae11-afff4fc7c078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345837738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2345837738
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.151236721
Short name T5
Test name
Test status
Simulation time 56858915 ps
CPU time 1.03 seconds
Started May 16 02:04:18 PM PDT 24
Finished May 16 02:04:22 PM PDT 24
Peak memory 220272 kb
Host smart-cdbe6e32-3519-4c05-a10b-e8f8424d081c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151236721 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.151236721
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2725009189
Short name T456
Test name
Test status
Simulation time 52505175 ps
CPU time 1.9 seconds
Started May 16 02:04:16 PM PDT 24
Finished May 16 02:04:22 PM PDT 24
Peak memory 218016 kb
Host smart-f5ba79b3-5dce-4eed-86c6-d4e8d6f70b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725009189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2725009189
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.1358915917
Short name T192
Test name
Test status
Simulation time 19602854 ps
CPU time 1.19 seconds
Started May 16 02:04:16 PM PDT 24
Finished May 16 02:04:21 PM PDT 24
Peak memory 223420 kb
Host smart-6595912d-2be8-4c44-aa9f-4722d264b3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358915917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1358915917
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2172968640
Short name T402
Test name
Test status
Simulation time 164270711 ps
CPU time 3.07 seconds
Started May 16 02:04:16 PM PDT 24
Finished May 16 02:04:23 PM PDT 24
Peak memory 219264 kb
Host smart-b65426bd-8356-4360-9203-13d9d96b24d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172968640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2172968640
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.697108824
Short name T69
Test name
Test status
Simulation time 28474505 ps
CPU time 0.86 seconds
Started May 16 02:04:18 PM PDT 24
Finished May 16 02:04:22 PM PDT 24
Peak memory 217648 kb
Host smart-8783ba0a-dd1f-47e9-9f8a-686bb57b60e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697108824 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.697108824
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2405971645
Short name T508
Test name
Test status
Simulation time 256652786 ps
CPU time 1.1 seconds
Started May 16 02:04:15 PM PDT 24
Finished May 16 02:04:18 PM PDT 24
Peak memory 216680 kb
Host smart-32947091-ec12-4145-aac5-825ddfdaa1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405971645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2405971645
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.1039356251
Short name T788
Test name
Test status
Simulation time 19654377 ps
CPU time 1.2 seconds
Started May 16 02:04:15 PM PDT 24
Finished May 16 02:04:20 PM PDT 24
Peak memory 223396 kb
Host smart-2270abd4-a9bc-42fa-87ae-c8f7c9f818ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039356251 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1039356251
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2974751768
Short name T711
Test name
Test status
Simulation time 46636933 ps
CPU time 1.26 seconds
Started May 16 02:04:17 PM PDT 24
Finished May 16 02:04:22 PM PDT 24
Peak memory 216752 kb
Host smart-4ff76f6b-09d6-4e34-a2f8-953a5de02967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974751768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2974751768
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.4285348075
Short name T49
Test name
Test status
Simulation time 41172622 ps
CPU time 1.01 seconds
Started May 16 02:04:18 PM PDT 24
Finished May 16 02:04:23 PM PDT 24
Peak memory 218196 kb
Host smart-ce5c40b8-f502-45bc-83bd-c3e22b67ecc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285348075 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.4285348075
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.687127960
Short name T762
Test name
Test status
Simulation time 106598185 ps
CPU time 1.56 seconds
Started May 16 02:04:17 PM PDT 24
Finished May 16 02:04:22 PM PDT 24
Peak memory 218452 kb
Host smart-3b08f978-e83a-465c-8501-d7d21f170214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687127960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.687127960
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.160655218
Short name T3
Test name
Test status
Simulation time 23655893 ps
CPU time 0.91 seconds
Started May 16 02:04:17 PM PDT 24
Finished May 16 02:04:22 PM PDT 24
Peak memory 217936 kb
Host smart-87a0ec82-8c79-407e-bd27-7167953ba5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160655218 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.160655218
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1354859581
Short name T21
Test name
Test status
Simulation time 24596226 ps
CPU time 1.26 seconds
Started May 16 02:04:14 PM PDT 24
Finished May 16 02:04:16 PM PDT 24
Peak memory 217984 kb
Host smart-15569670-1ded-45bf-ac25-a7ad8bfd0332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354859581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1354859581
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.492321730
Short name T44
Test name
Test status
Simulation time 62672119 ps
CPU time 1.02 seconds
Started May 16 02:04:19 PM PDT 24
Finished May 16 02:04:23 PM PDT 24
Peak memory 220116 kb
Host smart-18344dbc-2e02-4948-8618-ed029c9d851e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492321730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.492321730
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1621221818
Short name T808
Test name
Test status
Simulation time 21300476 ps
CPU time 1.16 seconds
Started May 16 02:04:15 PM PDT 24
Finished May 16 02:04:19 PM PDT 24
Peak memory 219144 kb
Host smart-655c18df-b675-4b12-b53f-f800dc52f9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621221818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1621221818
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.396092031
Short name T829
Test name
Test status
Simulation time 20735698 ps
CPU time 1.12 seconds
Started May 16 02:04:18 PM PDT 24
Finished May 16 02:04:23 PM PDT 24
Peak memory 228956 kb
Host smart-98d7a83a-7dca-4c35-8335-de15b9e9e25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396092031 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.396092031
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2384273177
Short name T843
Test name
Test status
Simulation time 237561565 ps
CPU time 3.31 seconds
Started May 16 02:04:16 PM PDT 24
Finished May 16 02:04:22 PM PDT 24
Peak memory 217068 kb
Host smart-a7c53c71-d536-4254-9dc2-3a2ba4daa7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384273177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2384273177
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3092320150
Short name T270
Test name
Test status
Simulation time 91762100 ps
CPU time 1.29 seconds
Started May 16 02:01:56 PM PDT 24
Finished May 16 02:02:01 PM PDT 24
Peak memory 215360 kb
Host smart-e0582d72-c7f8-410e-9248-4352c9279785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092320150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3092320150
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2834409298
Short name T327
Test name
Test status
Simulation time 27416540 ps
CPU time 0.97 seconds
Started May 16 02:01:55 PM PDT 24
Finished May 16 02:01:58 PM PDT 24
Peak memory 214476 kb
Host smart-cc1e14f7-858f-401b-b92b-c620e5ffe15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834409298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2834409298
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3370441473
Short name T194
Test name
Test status
Simulation time 14544319 ps
CPU time 0.91 seconds
Started May 16 02:01:55 PM PDT 24
Finished May 16 02:01:59 PM PDT 24
Peak memory 215272 kb
Host smart-70d1a5f7-6c4c-4686-8ab2-f82a359017df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370441473 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3370441473
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.4133362849
Short name T844
Test name
Test status
Simulation time 108899186 ps
CPU time 1.08 seconds
Started May 16 02:01:56 PM PDT 24
Finished May 16 02:02:01 PM PDT 24
Peak memory 219244 kb
Host smart-216caad7-9143-482e-ba34-24a53bc41071
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133362849 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.4133362849
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2738504263
Short name T842
Test name
Test status
Simulation time 22767776 ps
CPU time 1.14 seconds
Started May 16 02:01:55 PM PDT 24
Finished May 16 02:01:58 PM PDT 24
Peak memory 218408 kb
Host smart-67416b73-4e4c-40d2-aaa2-1d9fee61bc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738504263 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2738504263
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.613481933
Short name T764
Test name
Test status
Simulation time 34944468 ps
CPU time 1.44 seconds
Started May 16 02:01:56 PM PDT 24
Finished May 16 02:02:00 PM PDT 24
Peak memory 216896 kb
Host smart-8d9b22c1-37f7-4fec-8ba8-26e91fa75703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613481933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.613481933
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3693819092
Short name T448
Test name
Test status
Simulation time 57009334 ps
CPU time 0.89 seconds
Started May 16 02:01:58 PM PDT 24
Finished May 16 02:02:02 PM PDT 24
Peak memory 215048 kb
Host smart-fab7a466-068e-4bcc-b14b-4f6da8cce47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693819092 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3693819092
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1430552536
Short name T275
Test name
Test status
Simulation time 17509542 ps
CPU time 1.01 seconds
Started May 16 02:01:58 PM PDT 24
Finished May 16 02:02:02 PM PDT 24
Peak memory 206692 kb
Host smart-bebbb221-9e9d-4c39-8911-38b4885377ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430552536 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1430552536
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1292276375
Short name T635
Test name
Test status
Simulation time 28230406 ps
CPU time 0.96 seconds
Started May 16 02:01:55 PM PDT 24
Finished May 16 02:01:59 PM PDT 24
Peak memory 214912 kb
Host smart-baa68df7-37bb-4562-b07d-58b3fa77b9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292276375 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1292276375
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2355345655
Short name T737
Test name
Test status
Simulation time 507753758 ps
CPU time 2.45 seconds
Started May 16 02:01:57 PM PDT 24
Finished May 16 02:02:02 PM PDT 24
Peak memory 214984 kb
Host smart-8dd46764-a2b3-4d87-b44f-d5f121d019c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355345655 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2355345655
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.616806262
Short name T676
Test name
Test status
Simulation time 33308304188 ps
CPU time 744.43 seconds
Started May 16 02:01:55 PM PDT 24
Finished May 16 02:14:21 PM PDT 24
Peak memory 218536 kb
Host smart-aa92dce0-9615-4c46-af0a-f09166f05b5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616806262 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.616806262
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.415533929
Short name T595
Test name
Test status
Simulation time 44611969 ps
CPU time 0.86 seconds
Started May 16 02:04:16 PM PDT 24
Finished May 16 02:04:20 PM PDT 24
Peak memory 219068 kb
Host smart-c43a3b61-5ba0-4e26-81ef-a74d4489f76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415533929 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.415533929
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.4149420290
Short name T312
Test name
Test status
Simulation time 54154014 ps
CPU time 1.4 seconds
Started May 16 02:04:14 PM PDT 24
Finished May 16 02:04:17 PM PDT 24
Peak memory 217916 kb
Host smart-26c885a8-7329-4e30-8cf2-c50b5821f8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149420290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.4149420290
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.1261710621
Short name T77
Test name
Test status
Simulation time 43249441 ps
CPU time 0.89 seconds
Started May 16 02:04:37 PM PDT 24
Finished May 16 02:04:41 PM PDT 24
Peak memory 217752 kb
Host smart-ab628bf8-0a43-466e-9bfa-e34101b8fba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261710621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1261710621
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/82.edn_err.1828324120
Short name T837
Test name
Test status
Simulation time 25139250 ps
CPU time 1.28 seconds
Started May 16 02:04:37 PM PDT 24
Finished May 16 02:04:41 PM PDT 24
Peak memory 217988 kb
Host smart-92dc9b75-ead9-4b31-b8b9-eba2695a7136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828324120 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1828324120
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2170243270
Short name T651
Test name
Test status
Simulation time 74378262 ps
CPU time 2.71 seconds
Started May 16 02:04:33 PM PDT 24
Finished May 16 02:04:38 PM PDT 24
Peak memory 219576 kb
Host smart-1d40fbb8-eced-4f99-b156-5c3a4c7e4e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170243270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2170243270
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.578348441
Short name T458
Test name
Test status
Simulation time 20627580 ps
CPU time 1.19 seconds
Started May 16 02:04:33 PM PDT 24
Finished May 16 02:04:36 PM PDT 24
Peak memory 219408 kb
Host smart-03a7c141-f007-4268-9de7-bf70dce090ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578348441 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.578348441
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2353878315
Short name T502
Test name
Test status
Simulation time 82347366 ps
CPU time 1.19 seconds
Started May 16 02:04:30 PM PDT 24
Finished May 16 02:04:33 PM PDT 24
Peak memory 218012 kb
Host smart-8ecde2bf-967d-4695-a670-7fc6c7c1c3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353878315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2353878315
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.762464075
Short name T96
Test name
Test status
Simulation time 20266588 ps
CPU time 1.11 seconds
Started May 16 02:04:25 PM PDT 24
Finished May 16 02:04:28 PM PDT 24
Peak memory 219044 kb
Host smart-d144e724-6d06-43d7-bcbf-ff7f87c87adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762464075 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.762464075
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1007690620
Short name T121
Test name
Test status
Simulation time 194712021 ps
CPU time 1.27 seconds
Started May 16 02:04:30 PM PDT 24
Finished May 16 02:04:34 PM PDT 24
Peak memory 216976 kb
Host smart-833cd546-2bcb-4b69-8a1f-ef8f472854bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007690620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1007690620
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.798320425
Short name T537
Test name
Test status
Simulation time 23430205 ps
CPU time 0.95 seconds
Started May 16 02:04:32 PM PDT 24
Finished May 16 02:04:35 PM PDT 24
Peak memory 219208 kb
Host smart-369eddb3-f60e-49b1-8a28-67db20988f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798320425 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.798320425
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2683719435
Short name T403
Test name
Test status
Simulation time 49332466 ps
CPU time 1.18 seconds
Started May 16 02:04:37 PM PDT 24
Finished May 16 02:04:41 PM PDT 24
Peak memory 219264 kb
Host smart-23cceb44-b0bc-4a79-993a-86ed6839643e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683719435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2683719435
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1226656797
Short name T181
Test name
Test status
Simulation time 24537183 ps
CPU time 0.96 seconds
Started May 16 02:04:25 PM PDT 24
Finished May 16 02:04:28 PM PDT 24
Peak memory 217996 kb
Host smart-48528241-cbba-4141-b7f9-b4872f13d070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226656797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1226656797
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.53654965
Short name T321
Test name
Test status
Simulation time 26377335 ps
CPU time 1.21 seconds
Started May 16 02:04:26 PM PDT 24
Finished May 16 02:04:28 PM PDT 24
Peak memory 219280 kb
Host smart-eb5c6fe2-df22-4ce9-8cfa-7abfc74285d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53654965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.53654965
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1731107510
Short name T31
Test name
Test status
Simulation time 47546880 ps
CPU time 0.98 seconds
Started May 16 02:04:25 PM PDT 24
Finished May 16 02:04:27 PM PDT 24
Peak memory 219024 kb
Host smart-ed4a5486-a440-43d3-8ad2-41a7d363ee56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731107510 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1731107510
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2684651159
Short name T825
Test name
Test status
Simulation time 91589577 ps
CPU time 1.16 seconds
Started May 16 02:04:25 PM PDT 24
Finished May 16 02:04:27 PM PDT 24
Peak memory 216572 kb
Host smart-62df423d-6df4-4a56-a7d1-1d0a7405ffed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684651159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2684651159
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.2962982094
Short name T753
Test name
Test status
Simulation time 35639585 ps
CPU time 0.88 seconds
Started May 16 02:04:37 PM PDT 24
Finished May 16 02:04:41 PM PDT 24
Peak memory 217904 kb
Host smart-6696f81c-1d63-4627-802e-567b2b4cb331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962982094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2962982094
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.4228453803
Short name T332
Test name
Test status
Simulation time 338986634 ps
CPU time 2.07 seconds
Started May 16 02:04:25 PM PDT 24
Finished May 16 02:04:28 PM PDT 24
Peak memory 218140 kb
Host smart-548ebb6d-f3e5-4988-a534-cb1c7ff302d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228453803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.4228453803
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.827171229
Short name T50
Test name
Test status
Simulation time 32968262 ps
CPU time 1.1 seconds
Started May 16 02:04:29 PM PDT 24
Finished May 16 02:04:32 PM PDT 24
Peak memory 218128 kb
Host smart-372d5fb2-5687-4b9a-a229-aa01d96262ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827171229 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.827171229
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/9.edn_alert.716467742
Short name T30
Test name
Test status
Simulation time 27811350 ps
CPU time 1.23 seconds
Started May 16 02:01:54 PM PDT 24
Finished May 16 02:01:57 PM PDT 24
Peak memory 215376 kb
Host smart-24a25f09-8302-4995-a03b-f4435db3bd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716467742 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.716467742
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.45190429
Short name T759
Test name
Test status
Simulation time 10729385 ps
CPU time 0.84 seconds
Started May 16 02:02:06 PM PDT 24
Finished May 16 02:02:08 PM PDT 24
Peak memory 206556 kb
Host smart-b2ab1eaf-5ec6-45e8-b135-2dca7122df08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45190429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.45190429
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.4016662921
Short name T849
Test name
Test status
Simulation time 49782790 ps
CPU time 0.81 seconds
Started May 16 02:01:55 PM PDT 24
Finished May 16 02:01:58 PM PDT 24
Peak memory 215652 kb
Host smart-1dad13da-8428-42df-a8e3-b778bb9b21e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016662921 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.4016662921
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.451000661
Short name T575
Test name
Test status
Simulation time 28962110 ps
CPU time 1.05 seconds
Started May 16 02:01:58 PM PDT 24
Finished May 16 02:02:02 PM PDT 24
Peak memory 217816 kb
Host smart-0bf6e028-8cfa-4106-ac43-f87ce59429c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451000661 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.451000661
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3099490922
Short name T828
Test name
Test status
Simulation time 28751992 ps
CPU time 1.36 seconds
Started May 16 02:01:54 PM PDT 24
Finished May 16 02:01:57 PM PDT 24
Peak memory 220004 kb
Host smart-f0dbbea6-3668-4737-9948-bd845b085245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099490922 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3099490922
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_intr.804872449
Short name T159
Test name
Test status
Simulation time 29153591 ps
CPU time 0.89 seconds
Started May 16 02:01:56 PM PDT 24
Finished May 16 02:02:00 PM PDT 24
Peak memory 215316 kb
Host smart-005c6b98-3ece-45c9-a5c4-128661d497e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804872449 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.804872449
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1515404995
Short name T265
Test name
Test status
Simulation time 16897738 ps
CPU time 1.01 seconds
Started May 16 02:01:57 PM PDT 24
Finished May 16 02:02:01 PM PDT 24
Peak memory 206696 kb
Host smart-75083072-1d7c-4308-9626-8fae07d64962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515404995 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1515404995
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3593707378
Short name T653
Test name
Test status
Simulation time 24168537 ps
CPU time 0.99 seconds
Started May 16 02:01:56 PM PDT 24
Finished May 16 02:02:00 PM PDT 24
Peak memory 214980 kb
Host smart-5e018eb1-f180-48e4-aec3-3be1adb5c203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593707378 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3593707378
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1741305809
Short name T731
Test name
Test status
Simulation time 291583672 ps
CPU time 5.11 seconds
Started May 16 02:01:56 PM PDT 24
Finished May 16 02:02:05 PM PDT 24
Peak memory 217904 kb
Host smart-bd79cb0c-9986-432b-9647-6fbbca10b28e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741305809 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1741305809
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.877098857
Short name T747
Test name
Test status
Simulation time 53475766276 ps
CPU time 1401.19 seconds
Started May 16 02:01:54 PM PDT 24
Finished May 16 02:25:16 PM PDT 24
Peak memory 223564 kb
Host smart-7a7fcf8f-9d6d-45ac-8551-7b47d935c5cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877098857 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.877098857
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.2429359881
Short name T607
Test name
Test status
Simulation time 67029353 ps
CPU time 0.86 seconds
Started May 16 02:04:27 PM PDT 24
Finished May 16 02:04:30 PM PDT 24
Peak memory 217956 kb
Host smart-12fa3848-624c-422f-a8c8-243d7f56ea0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429359881 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2429359881
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2015862206
Short name T488
Test name
Test status
Simulation time 24570769 ps
CPU time 1.16 seconds
Started May 16 02:04:32 PM PDT 24
Finished May 16 02:04:35 PM PDT 24
Peak memory 217736 kb
Host smart-988a9a2b-1810-4b6e-a2bd-f1a9bb77e747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015862206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2015862206
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.533521513
Short name T59
Test name
Test status
Simulation time 26564311 ps
CPU time 1.09 seconds
Started May 16 02:04:34 PM PDT 24
Finished May 16 02:04:37 PM PDT 24
Peak memory 223372 kb
Host smart-8cfb5085-0a75-4a7d-9600-66e4acafcf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533521513 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.533521513
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1932045725
Short name T341
Test name
Test status
Simulation time 49729754 ps
CPU time 1.45 seconds
Started May 16 02:04:32 PM PDT 24
Finished May 16 02:04:36 PM PDT 24
Peak memory 215096 kb
Host smart-14a3b665-9dd0-441d-9b23-7b2869100fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932045725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1932045725
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.4271626183
Short name T781
Test name
Test status
Simulation time 31623727 ps
CPU time 0.98 seconds
Started May 16 02:04:26 PM PDT 24
Finished May 16 02:04:28 PM PDT 24
Peak memory 223312 kb
Host smart-e3725f1f-0362-4998-8bac-1fbcc187a7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271626183 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.4271626183
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1895576823
Short name T514
Test name
Test status
Simulation time 206472279 ps
CPU time 3.2 seconds
Started May 16 02:04:24 PM PDT 24
Finished May 16 02:04:28 PM PDT 24
Peak memory 218612 kb
Host smart-f1213d2f-8517-4234-9f7c-e7b7e746d2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895576823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1895576823
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.1737988506
Short name T95
Test name
Test status
Simulation time 22614923 ps
CPU time 0.93 seconds
Started May 16 02:04:27 PM PDT 24
Finished May 16 02:04:29 PM PDT 24
Peak memory 219024 kb
Host smart-e63ef8be-114a-4399-9af7-9cb003657f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737988506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1737988506
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3141665142
Short name T421
Test name
Test status
Simulation time 50615439 ps
CPU time 1.72 seconds
Started May 16 02:04:27 PM PDT 24
Finished May 16 02:04:30 PM PDT 24
Peak memory 217944 kb
Host smart-69bb856d-883f-432b-93b7-0e823f73a17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141665142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3141665142
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.4173102374
Short name T62
Test name
Test status
Simulation time 71136704 ps
CPU time 1.01 seconds
Started May 16 02:04:28 PM PDT 24
Finished May 16 02:04:30 PM PDT 24
Peak memory 223304 kb
Host smart-0e939982-0f00-416e-9a52-7b27ab186331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173102374 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.4173102374
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.4001495112
Short name T542
Test name
Test status
Simulation time 34202126 ps
CPU time 1.03 seconds
Started May 16 02:04:24 PM PDT 24
Finished May 16 02:04:26 PM PDT 24
Peak memory 217964 kb
Host smart-c0c2a3c1-525a-488b-8110-2048312b8e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001495112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.4001495112
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.1503017733
Short name T847
Test name
Test status
Simulation time 66351295 ps
CPU time 0.9 seconds
Started May 16 02:04:30 PM PDT 24
Finished May 16 02:04:33 PM PDT 24
Peak memory 223260 kb
Host smart-0227bada-8fec-4151-a5eb-ab7060a5cd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503017733 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1503017733
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.824104901
Short name T151
Test name
Test status
Simulation time 57534664 ps
CPU time 1.53 seconds
Started May 16 02:04:28 PM PDT 24
Finished May 16 02:04:31 PM PDT 24
Peak memory 216792 kb
Host smart-68896f0a-3e13-4ef5-a973-ae0eae53be35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824104901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.824104901
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.4128624894
Short name T570
Test name
Test status
Simulation time 70283598 ps
CPU time 1.17 seconds
Started May 16 02:04:37 PM PDT 24
Finished May 16 02:04:41 PM PDT 24
Peak memory 219248 kb
Host smart-e4265c07-9b49-4ac3-a9d3-4b8028ad62ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128624894 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.4128624894
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2937052185
Short name T695
Test name
Test status
Simulation time 36134947 ps
CPU time 1.29 seconds
Started May 16 02:04:30 PM PDT 24
Finished May 16 02:04:34 PM PDT 24
Peak memory 216656 kb
Host smart-409b7890-67c2-403b-98a6-a65636b5f042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937052185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2937052185
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.2812863669
Short name T35
Test name
Test status
Simulation time 32364927 ps
CPU time 1.06 seconds
Started May 16 02:04:37 PM PDT 24
Finished May 16 02:04:41 PM PDT 24
Peak memory 229164 kb
Host smart-597133f1-1e36-4429-bf90-686a1ea27cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812863669 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2812863669
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3842088016
Short name T147
Test name
Test status
Simulation time 36842175 ps
CPU time 1.34 seconds
Started May 16 02:04:30 PM PDT 24
Finished May 16 02:04:34 PM PDT 24
Peak memory 214972 kb
Host smart-9e0463e5-172f-4bd2-aca9-8e66a25ceef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842088016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3842088016
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1601513656
Short name T673
Test name
Test status
Simulation time 34538335 ps
CPU time 1.02 seconds
Started May 16 02:04:38 PM PDT 24
Finished May 16 02:04:42 PM PDT 24
Peak memory 223268 kb
Host smart-d94d322b-7440-4db3-b9f1-687cd142394e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601513656 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1601513656
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1067550145
Short name T574
Test name
Test status
Simulation time 63811052 ps
CPU time 1.09 seconds
Started May 16 02:04:27 PM PDT 24
Finished May 16 02:04:30 PM PDT 24
Peak memory 219184 kb
Host smart-3c8e062f-5f86-4fb4-8060-babcbeb1afc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067550145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1067550145
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.2813322464
Short name T511
Test name
Test status
Simulation time 37035686 ps
CPU time 0.94 seconds
Started May 16 02:04:36 PM PDT 24
Finished May 16 02:04:40 PM PDT 24
Peak memory 219428 kb
Host smart-de5d7b3a-0145-433c-9420-279c5d5fc653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813322464 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2813322464
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.106211269
Short name T777
Test name
Test status
Simulation time 54377394 ps
CPU time 1.46 seconds
Started May 16 02:04:35 PM PDT 24
Finished May 16 02:04:38 PM PDT 24
Peak memory 218212 kb
Host smart-207ecca8-3da5-4441-9018-a969afd00884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106211269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.106211269
Directory /workspace/99.edn_genbits/latest
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